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Hi all, Has anyone had a problem with the latest Leonardo version (2002d) and the "virtex2_multipliers" variable? Even though I set it to FALSE, Leonardo insists on using one of the embedded multipliers. The thing is that when I run exactly the same synth script with exactly the same source code but with the previous Leonardo versions (2002b, 2002c), this variable is properly understodod. Any clue? Thanks in advance for your answers! Tomas Motos Lopez FPGA Designer NERA Networks AS Any clueArticle: 49001
> * not run your simulation in Modelsim; If not, then how else do you do simulations in ISE? adrianArticle: 49002
No... using ND doesn't work. adrian > I think I may have solved my own problem... I can use the ND pin, I think! > > adrianArticle: 49003
A question for anyone who has used the coregen IP module for an SDA FIR filter... If your input sample rate is longer than the number of clock cycles per output ie. L=4, but input sample rate is =8, and RFD is toggled (Low-Hi-Low) only at each data input ie. every 8 clock cycles, then what happens to the internal data? Is the internal structure like a shift register, so that I don't need to worry about the filter continuing to run after the data output? Or will the filter continue to run, even though I haven't given it new data ie. the internal registers will empty? Thanks adrianArticle: 49004
HI I am trying to implement a little ALU in VHDL. Below is a toned down portion of my code. When I try and compile it using Quartus 2.1, Web Edition, I get the following run time error message that pops up in a window: Internal Error: Sub-system: LPMS, File: ./lpms_root.cpp, Line: 842 (op->is_signed() && op_iterm->is_vcc()) || (!op->is_signed() && op_iterm->is_gnd()) Quartus II Version 2.1 Build 166 07/08/2002 SJ Web Edition Here is my code, please note that I cannot change the entity as it is 100% correct for the remaining SIGNED operations: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY ALU IS PORT ( A : IN SIGNED (11 downto 0); B : IN SIGNED (11 downto 0); CLK : IN STD_LOGIC; Z : OUT SIGNED (11 downto 0) ); END ALU; ARCHITECTURE ALU_architecture OF ALU IS BEGIN arithmetic: PROCESS(CLK) BEGIN if CLK'event then Z <= SHIFT_RIGHT(A, TO_INTEGER(UNSIGNED(B(2 DOWNTO 0)))); end if ; END PROCESS; END ALU_architecture; If anyone has any suggestions on why the error is present or ideas how else to perform a shift using the 2 input variables, they will be greatly appreciated because I am about to pull my hair out! Thanks RyanArticle: 49005
Hmmm, we have a couple license for ModelSIM XE that removes the recommended size limit, however when a key is not available we use starter licenses. Perhaps the newer version of ModelSim won't allow you to load designs of a certain size but in the past when loading large designs I received the warning that the design exceeded the recommended the limit.<br> <br> However, even with a project consisting of 30,000 lines the starter version ran it with the warning and with no noticeable performance difference between the starter license and the hardware keyed license...<br> <br> Maybe we should have asked for our money back :PArticle: 49006
SH7 -
I did as you suggested, installing and overwriting a boatload of
files.
Alas, no positive results yet.
I slowed down the clock and selected a faster part as well. No
dice.
Bill
Spam Hater wrote:
>
> Bill,
>
> Did you install the ModelSim library updates? The ones that come in a
> zip file so there's no way to back them out?
>
> If so, that's your problem. I had to re-install ModelSim to get rid
> of them to fix the same problem.
>
> Dig into the waveform of the post-fit cpld, and you will see way too
> many X's on the signals.
>
> SH7
>
> On Sun, 27 Oct 2002 15:07:59 GMT, Bill Turnip <BTurnip@wellspring.org>
> wrote:
>
> >Hello group:
> > I'll try to keep this short. I have a simple asynchronous Verilog
> >module that takes 3 inputs to produce a few simple outputs.
> >Behavorially, the module works fine. I pumped the design through
> >WebPACK and targeted an FPGA as well as a CPLD. Behavorially, the
> >post-PAR and post-fit models simulate and match the behavorial model
> >(now with various delays, of course). To switch back and forth between
> >FPGA <> CPLD I simply changed the "properties" of the project, and
> >re-synthesized, etc. The verilog code for the module being implemented
> >as well as the testbench were the same for both the FPGA and CPLD
> >cases. I let the Xilinx IDE handle all the background stuff for the
> >ModelSim simulations of the post-PAR, post-Fit models.
> > So, I then made the design synchronous - added a clock as well as a
> >reset and made small modifications to the testbench - and repeated the
> >exercise above. The FPGA implementation works fine, with the behavorial
> >functionality matching the post-PAR (and post-map, post-translate, etc.)
> >functionality, now with delays of course. However, the post-fit CPLD
> >implementation does not work functionally at all! Again, I am using the
> >same testbench and verilog code for the two synchronous
> >implementations. It seems the post-Fit CPLD design is "stuck." The
> >outputs are correct for the first set of inputs passed to it from the
> >testbench, but after this they never change, as if time is not passing.
> >But the same exact code works for the FPGA! I'm new to this area, but
> >it doesn't seem to make sense. Do I need to do something special for
> >the clock or reset in the post-Fit code for the CPLD that is transparent
> >for the FPGA? I expected the CPLD implementation to be easier and less
> >complicated.
> > Thanks for any insight to this very interesting issue.
> >- BT
Article: 49007On Tue, 29 Oct 2002 16:20:39 +0200, "Ryan" <ryans@cat.co.za> wrote: >HI > >I am trying to implement a little ALU in VHDL. Below is a toned down portion >of my code. When I try and compile it using Quartus 2.1, Web Edition, I get >the following run time error message that pops up in a window: > >Internal Error: Sub-system: LPMS, File: ./lpms_root.cpp, Line: 842 >(op->is_signed() && op_iterm->is_vcc()) || (!op->is_signed() && >op_iterm->is_gnd()) >Quartus II Version 2.1 Build 166 07/08/2002 SJ Web Edition > >Here is my code, please note that I cannot change the entity as it is 100% >correct for the remaining SIGNED operations: > > >LIBRARY ieee; >USE ieee.std_logic_1164.all; >USE ieee.numeric_std.all; > > >ENTITY ALU IS > PORT > ( > A : IN SIGNED (11 downto 0); > B : IN SIGNED (11 downto 0); > CLK : IN STD_LOGIC; > Z : OUT SIGNED (11 downto 0) > ); > >END ALU; > >ARCHITECTURE ALU_architecture OF ALU IS >BEGIN > >arithmetic: > PROCESS(CLK) > BEGIN > if CLK'event then > > Z <= SHIFT_RIGHT(A, TO_INTEGER(UNSIGNED(B(2 DOWNTO 0)))); > > end if ; > END PROCESS; >END ALU_architecture; > >If anyone has any suggestions on why the error is present or ideas how else >to perform a shift using the 2 input variables, they will be greatly >appreciated because I am about to pull my hair out! It's possible that the Quartus synthesizer is having difficulty with a variable shift. Try it with a constant instead of B and if that works you can write a case statement which enumerates all 8 possibilities of B and shifts A with that constant. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 49008
Hi I wonder if it there is any internal generated clock inside the Virtex-II devices that I could use to clock a register. The XC4000 had a component called OSC4 that could be used internal. Is it possible to connect to the CCLK from within the Virtex-II? I need this during system initialization. Thanks /Patrik -- Patrik Eriksson | patrik.eriksson@netinsight.net Net Insight AB | phone: +46 8 685 04 89 Västberga Allé 9 | fax: +46 8 685 04 20 SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.netArticle: 49009
Nico; One general suggestion would be to calculate the switching losses in all the I/O pins based on the drive current and switching frequnency of these I/O pins, and then combine this with internal power losses. There is also some static power loss in the I/O pins that you may need to account for. But the biggest variable is the I/O pins and then the internal logic that gets "awakened" or put to "sleep" during the normal modes of operation, but for a worst case assume all the designed logic is running and drawing power. I have found pretty good success with the LT1773 from Linear Tech in terms of 1.5V and 3.3V regulators close to the FPGA. Regards, James nico.fleurinck@verhaert.com (Nico Fleurinck) wrote in message news:<d2af0dc.0210280047.40a11a00@posting.google.com>... > Dear all, > I'm doing for the first time a design with a virtex FPGA. > The FPGA is a XC2V2000 of xilinx. > This question is for everybody that has some experience with xilinx > fpgas. > Can you share with me the power regulation you did for your xilinx > FPGA? > I'm thinking to use the TI LDOs; UC385-1 and UC385-3. > > The FPGA will be put on a compact-PCI board, so i receive form the > backplane a 3.3V power supply, i need to generate the 1.5V for the > internal core, i will do this via 2 LDOs from 3.3V -> 2.5V and from > 2.5V -> 1.5V. I do this to reduce the power dissipation of the LDOs. > > I know that there is a power estimator of xilinx, but on this stage of > the project it is not possible to fill-in this sheet for an estimation > of the power consumption. > > So if you can tell me how you did your power estimation i can try it > on my design. > > All information you can share with me is more than welcom. > > Best regards and thanks for reading this mail. > > Nico Fleurinck > > nico.fleurinck@verhaert.com > 0032/(0) 3 250 1984Article: 49010
Noddy wrote:
>>* not run your simulation in Modelsim;
> If not, then how else do you do simulations in ISE?
There are other Verilog simulators that you can use. We use Icarus
Verilog to simulate our Xilinx designs, but there are other options:
1) Buy a full version of Modelsim,
2) Buy any of a multitude of other Verilog simulators that can be
used to simulate Xilinx designs,
3) Use one of the free Verilog simulators that are available
The EEDesign.com page has a list here:
http://www.eedesign.com/resources/opensourcelinks.html
4) Synthesize your design and use a gate level synthesizer, ...
--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
steve at picturel.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
abuse@xo.com
uce@ftc.gov
Article: 49011stenasc@yahoo.com (Bob) wrote in message news:<20540d3a.0210280751.7efb8790@posting.google.com>... > Hi. > > I want to create a filter on an FPGA. The filter is a 25 tap FIR. It > is to be used for an audio application. What kind of chip resources > ie no. of flops > would this use. Is it possible to use existing C code for a DSP to > implement this? > > Thanks for your help > > Bob Hello Bob If you want to be very lazy, ONEoverT will produce the filter for you. It ouputs the filter in VHDL along with a testbench and simulation data files. It costs aprox. $700 not including VHDL module but if you look at the dsp ezine at this location. Unfortunately no Verilog module is available. www.globaldsp.com it gives you a code when entered on the Tyder site will give you approx 25% discount on the filter design package. This discount is not mentioned on the Tyder site. AlanArticle: 49012
"Patrik Eriksson" <patrik.eriksson@netinsight.net> schrieb im Newsbeitrag news:3DBEB12F.50504@netinsight.net... > Hi > > I wonder if it there is any internal generated clock inside the > Virtex-II devices that I could use to clock a register. The XC4000 had a > component called OSC4 that could be used internal. Is it possible to > connect to the CCLK from within the Virtex-II? I need this during system > initialization. No, there is no such internal clock. Why do you need this? -- MfG FalkArticle: 49013
Oh no, to the contrary. They don't have the Max3000 family on the webedition of Quartus2. That to convince the users to get the the professional version for 2000$US. The pro version does support Max3000. The same with APEX1k, I think. Call it politics. Anyway, both together cover the lower end. Rene Karl de Boois wrote: > You don't wanna use the families that are not supported by QuartusII ! The > main reason for using MAXPlus2 would be the relaxed system requirements for > your workstation. > > Karl. > "Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message > news:3DBD9B6A.5030508@dplanet.ch... > >>Not all families are supported by the web edition. >>For some the MaxPlus2 is required. >> >>Rene >> >>Fredrik wrote: >> >>>Hi, >>>There is a learning curve but it is no big think to get used to >>>Alteras software. There is indeed a free version of QuartusII avalible >>>called QuartusII Web Edition, this software supports all familys but >>>not all densities. Full information is avalible on Alteras Web. >>>Cheers >>>Fredrik >>>"Soul in Seoul" <Far@East.Design> wrote in message >> > news:<3dbcedf0$1@news.starhub.net.sg>...Article: 49014
Two entirely different things. The arbiter is for the motherboard/system to arbitrate REQ/GNT signals from each of the PCI masters. There is no real standard PCI arbiter as far as I know. It could use any arbitration scheme you could come up with, it's not that tough to do... "Blackie Beard" <BlackBeard@FearlessImmortalWretch.com> wrote in message news:6PBt9.5670$wm6.3413@nwrddc01.gnilink.net... > I'd like the whole PCI Master core, myself. If anyone > has it in Verilog, I'd sure like to get that for free. Also, > I wonder if I could get USB, Firewire, PCMCIA and IDE. > I asked Palmchip, but they said I had to pay. Darn. > > BB > > =========================================== > > "DRENGER GABI" <DRENGER@EVS.CO.IL> wrote in message > news:974ec56.0210230654.2b8af54e@posting.google.com... > > Hi all, > > > > I am looking for a PCI arbiter > > "core" that could be droped in a ALTERA FPGA > > > > THANK'S > > > > Gabi > >Article: 49015
"Geoffrey Furman" <geoff_furman@iisvr.com> schrieb im Newsbeitrag news:urtg44jutcphfb@corp.supernews.com... > As it was explained to me by folks at Xilinx (or as I understood it). > > Xilinx internally has buses (long lines???) with multiple tristate drivers. > The benefit is in the generation of wired logic (wide muxes). In using > these tristate drivers, you must be careful to prevent bus contention. No, the Tristates are no real tristates in Virtex anymore. So there are no danger for contention. > Sounds like a design/engineering problem and not a technology problem to me. Its half/half. > And don't confuse this with the fact that all boards / ICs on power up > require a current spike to charge up stray capacitance. It doesn't sound > like capacitance to me it sounds like rogue FETs shorting VCC to GND. Thats is. but its not the tristates, its the whole configuration RAM that is in and undefined state and so can caues a VC-GND short. But this has been fixed in Virtex-II/PRO. -- MfG FalkArticle: 49016
As it was explained to me by folks at Xilinx (or as I understood it). Xilinx internally has buses (long lines???) with multiple tristate drivers. The benefit is in the generation of wired logic (wide muxes). In using these tristate drivers, you must be careful to prevent bus contention. Apparently these drivers don't power up off so that there is by default bus contention until the device reaches a certain voltage level. I was led to believe that the issue has has been around for a while but it was not until the speed and density of the devices increased that it became a problem. Sounds like a design/engineering problem and not a technology problem to me. And don't confuse this with the fact that all boards / ICs on power up require a current spike to charge up stray capacitance. It doesn't sound like capacitance to me it sounds like rogue FETs shorting VCC to GND. "Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:aph3bk$s60$1$8300dec7@news.demon.co.uk... > Steve Knapp wrote > > The Power On Surge current associated with some Xilinx devices all boils > > down to something relatively easy to accomplish in most applications. > > However, I agree that the terse data sheet specification, without any > > background information, creates a number of unanswered questions. > > <snip> > > Just wondering - what is the general approach for avoiding this > effect in the design of recent FPGAs such as VirtexII? And do > commodity SRAMs have the same problem? > > > >Article: 49017
Are you using the XST or the FPGA Express design flow? Do you have a choice? The last time I saw this, it was a combination of things: The tools didn't line up, and I had a couple inferred latches in my code. And I switched design flows. I did them all at the same time, so I really don't know if it was any one thing, or some combination of the three. Sorry, SH7 On Tue, 29 Oct 2002 14:36:22 GMT, Bill Turnip <BTurnip@wellspring.org> wrote: >SH7 - > > I did as you suggested, installing and overwriting a boatload of >files. >Alas, no positive results yet. > I slowed down the clock and selected a faster part as well. No >dice. > >Bill > >Spam Hater wrote: >> >> Bill, >> >> Did you install the ModelSim library updates? The ones that come in a >> zip file so there's no way to back them out? >> >> If so, that's your problem. I had to re-install ModelSim to get rid >> of them to fix the same problem. >> >> Dig into the waveform of the post-fit cpld, and you will see way too >> many X's on the signals. >> >> SH7 >> >> On Sun, 27 Oct 2002 15:07:59 GMT, Bill Turnip <BTurnip@wellspring.org> >> wrote: >> >> >Hello group: >> > I'll try to keep this short. I have a simple asynchronous Verilog >> >module that takes 3 inputs to produce a few simple outputs. >> >Behavorially, the module works fine. I pumped the design through >> >WebPACK and targeted an FPGA as well as a CPLD. Behavorially, the >> >post-PAR and post-fit models simulate and match the behavorial model >> >(now with various delays, of course). To switch back and forth between >> >FPGA <> CPLD I simply changed the "properties" of the project, and >> >re-synthesized, etc. The verilog code for the module being implemented >> >as well as the testbench were the same for both the FPGA and CPLD >> >cases. I let the Xilinx IDE handle all the background stuff for the >> >ModelSim simulations of the post-PAR, post-Fit models. >> > So, I then made the design synchronous - added a clock as well as a >> >reset and made small modifications to the testbench - and repeated the >> >exercise above. The FPGA implementation works fine, with the behavorial >> >functionality matching the post-PAR (and post-map, post-translate, etc.) >> >functionality, now with delays of course. However, the post-fit CPLD >> >implementation does not work functionally at all! Again, I am using the >> >same testbench and verilog code for the two synchronous >> >implementations. It seems the post-Fit CPLD design is "stuck." The >> >outputs are correct for the first set of inputs passed to it from the >> >testbench, but after this they never change, as if time is not passing. >> >But the same exact code works for the FPGA! I'm new to this area, but >> >it doesn't seem to make sense. Do I need to do something special for >> >the clock or reset in the post-Fit code for the CPLD that is transparent >> >for the FPGA? I expected the CPLD implementation to be easier and less >> >complicated. >> > Thanks for any insight to this very interesting issue. >> >- BTArticle: 49018
-- important attribute that link with LPM_RAM_DP > attribute macrocell : boolean; > attribute macrocell of LPM_RAM_DP : component is true; > attribute LPM_TYPE of LPM_RAM_DP : component is "LPM_RAM_DP"; the last line should read: attribute LPM_TYPE : string; attribute LPM_TYPE of LPM_RAM_DP : component is "LPM_RAM_DP"; Avansih Bharati @Altium avanish.bharati@altium.com.au (Avanish) wrote in message news:<da3d6364.0210282201.64e51762@posting.google.com>... > Hi > > Try actually adding couple of attributes in your code and then > synthesise. > In you component declaration section of your code add. > > component LPM_RAM_DP > generic ( > > LPM_TYPE : string := LPM_RAM_DP; > > etc... > ); > > port (RDCLOCK : in std_logic := '0' > etc.. > ); > end component; > > -- important attribute that link with LPM_RAM_DP > attribute macrocell : boolean; > attribute macrocell of LPM_RAM_DP : component is true; > attribute LPM_TYPE of LPM_RAM_DP : component is "LPM_RAM_DP"; > > Here I am using "macrocell" but I am sure Leonardo should have one > built in or even recognise something like this too. > attribute BOX_TYPE : string; > attribute BOX_TYPE of LPM_RAM_DP : component is "BLACK_BOX"; > > This brings me to a question for everyone. What is the standard > BLACK_BOX attribute in VHDL for synthesis tools? Is there one! > > Hope this helps > > Avanish Bharati > Altium > > > > Prager Roman <rprager@frequentis.com> wrote in message news:<apjskp$c6o$1@frqvie15ux.frequentis.frq>... > > wrote: > > > Hi all, > > > I'm in trouble with leonardo : I have a design > > > in vhdl which instanciates lpm functions such as lpm_ram_dp > > > and I would like to synthesize it with leonardo for the APEX20Ke > > > technology. > > > The problem is that it seems that leonardo doesn't recognize those > > > primitives : it generates black boxes with name such as : > > > lpm_ram_dp_REGISTERED_REGISTERED_8_tp_tperg4_tperg4lf_stephane_nios_essai_soft_onchip_memory_0_lane1mif_UNREGISTERED_8_USE_EAB_ON_REGISTERED > > > > wich can't be read by the P&R quartus. > > > So, my question is : > > > Do I have to : > > > 1) configure leonardo to directly synthesize lpm megafunctions (how ?) > no > > > 2) tell leonardo not to change the name (ie keep lpm_ram_dp) by not adding > > > generic parameters (how ?) > > > 3) Not synthesize entities containing lpm (but somes are in an ugly generated code) > > > 4) other ? > > Altera Support told us to leave the lpm- functions as blackboxes and do not > > try to synthesize them with Leonardo. (which seems to be the same as you > > are doing). > > > > Indeed, I get such instance names as you mentioned above, but in my case, Quartus > > has no problem reading the edf- file. > > But it depends on Leonardo settings. What does the exact error message look > > like?. E.g. I once had problems, when I also allowed Leonardo to put in the > > logic cells for the pins. > > > > Roman > > > > > thanks very much for your help . I'm on it for a long time now > > > and I'm getting mad. > > > > Thanks a lot. > > > > StephaneArticle: 49019
Stelios Zontos wrote: > Dear all, > > me and my partners have designed and successfully implemented the electronic > part of a WDM ring node (Burst Mode Rx/Tx, data storage, MAC protocol). The > electronic part consists of two boards and many FPGAs. We tested our > equipment and we are now interested to present our work to a > conference/journal. Can somebody give me information on some conferences and > on the content of the paper? It is the first time we like to edit a paper on > hardware implementation :) > > Thanks in advance > H. > > > U can send to FPL,FCCM and also to this conference fpga2003.ece.ubc.caArticle: 49020
It is too late for FPGA2003, paper selection is just about done. FPL, FCCM and
MAPLD are other options. Applications papers are usually scrutinized closely, and
if it doesn't offer something more than a "we made this neat widget, and ain't it
nice", it is not likely to be accepted. Things to look for in an apps paper are a
novel application of FPGA resources, techniques or capability (such as
reconfiguration). It helps tremendously to offer something in the paper that is
applicable to other designs as well. Please consider that as you prepare your
paper. Most of these conferences require a pretty much completed paper for
submission.
Kolin Paul wrote:
> Stelios Zontos wrote:
> > Dear all,
> >
> > me and my partners have designed and successfully implemented the electronic
> > part of a WDM ring node (Burst Mode Rx/Tx, data storage, MAC protocol). The
> > electronic part consists of two boards and many FPGAs. We tested our
> > equipment and we are now interested to present our work to a
> > conference/journal. Can somebody give me information on some conferences and
> > on the content of the paper? It is the first time we like to edit a paper on
> > hardware implementation :)
> >
> > Thanks in advance
> > H.
> >
> >
> >
>
> U can send to FPL,FCCM and also to this conference
> fpga2003.ece.ubc.ca
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49021Bill, Have you simulated the powerup process of your CPLD design? To be more specific you have to include the following code in your testbench: reg PRLD; assign glbl.PRLD = PRLD; initial begin PRLD = 1; #100; PRLD = 0; end This tells the simulator that you are powering up the device and it will assign your power-up values to the signals. Otherwise they show as "X"s. Regards, -- Georgi Bill Turnip <BTurnip@wellspring.org> wrote in message news:<3DBE9D24.9206C4F@wellspring.org>... > SH7 - > > I did as you suggested, installing and overwriting a boatload of > files. > Alas, no positive results yet. > I slowed down the clock and selected a faster part as well. No > dice. > > Bill > > Spam Hater wrote: > > > > Bill, > > > > Did you install the ModelSim library updates? The ones that come in a > > zip file so there's no way to back them out? > > > > If so, that's your problem. I had to re-install ModelSim to get rid > > of them to fix the same problem. > > > > Dig into the waveform of the post-fit cpld, and you will see way too > > many X's on the signals. > > > > SH7 > > > > On Sun, 27 Oct 2002 15:07:59 GMT, Bill Turnip <BTurnip@wellspring.org> > > wrote: > > > > >Hello group: > > > I'll try to keep this short. I have a simple asynchronous Verilog > > >module that takes 3 inputs to produce a few simple outputs. > > >Behavorially, the module works fine. I pumped the design through > > >WebPACK and targeted an FPGA as well as a CPLD. Behavorially, the > > >post-PAR and post-fit models simulate and match the behavorial model > > >(now with various delays, of course). To switch back and forth between > > >FPGA <> CPLD I simply changed the "properties" of the project, and > > >re-synthesized, etc. The verilog code for the module being implemented > > >as well as the testbench were the same for both the FPGA and CPLD > > >cases. I let the Xilinx IDE handle all the background stuff for the > > >ModelSim simulations of the post-PAR, post-Fit models. > > > So, I then made the design synchronous - added a clock as well as a > > >reset and made small modifications to the testbench - and repeated the > > >exercise above. The FPGA implementation works fine, with the behavorial > > >functionality matching the post-PAR (and post-map, post-translate, etc.) > > >functionality, now with delays of course. However, the post-fit CPLD > > >implementation does not work functionally at all! Again, I am using the > > >same testbench and verilog code for the two synchronous > > >implementations. It seems the post-Fit CPLD design is "stuck." The > > >outputs are correct for the first set of inputs passed to it from the > > >testbench, but after this they never change, as if time is not passing. > > >But the same exact code works for the FPGA! I'm new to this area, but > > >it doesn't seem to make sense. Do I need to do something special for > > >the clock or reset in the post-Fit code for the CPLD that is transparent > > >for the FPGA? I expected the CPLD implementation to be easier and less > > >complicated. > > > Thanks for any insight to this very interesting issue. > > >- BTArticle: 49022
Ryan,
There is a problem with Quartus 2.1 with the implementation of
SHIFT_RIGHT arithmetic. This is fixed in the next release of Quartus
(version 2.2 due at the end of November). To work around this, you can
implement your own SHIFT_RIGHT_ARITH function. There are numerous ways
to do this; here's one example. This will probably be a little less
efficient than the true SHIFT_RIGHT.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY shift_ie IS
PORT
(
A : IN SIGNED (11 downto 0);
B : IN SIGNED (11 downto 0);
CLK : IN STD_LOGIC;
Z : OUT SIGNED (11 downto 0)
);
END shift_ie;
ARCHITECTURE ALU_architecture OF shift_ie IS
FUNCTION SHIFT_RIGHT_ARITH (ARG: SIGNED(11 downto 0); SHIFT_DIST :
NATURAL) return SIGNED IS
variable TEMP : UNSIGNED (11 downto 0);
variable K : NATURAL;
BEGIN
if (SHIFT_DIST = 0) then
return ARG;
else
TEMP := SHIFT_RIGHT(UNSIGNED(ARG), SHIFT_DIST);
for K in 0 to 11 loop
IF (K > (11 - SHIFT_DIST)) THEN
TEMP(K) := ARG(11);
END IF;
end LOOP;
return SIGNED(TEMP);
end IF;
END SHIFT_RIGHT_ARITH;
BEGIN
arithmetic:
PROCESS(CLK)
BEGIN
IF CLK'event and CLK = '1' then
Z <= SHIFT_RIGHT_ARITH(A, TO_INTEGER(UNSIGNED(B(2 DOWNTO 0))));
end if ;
END PROCESS;
END ALU_architecture;
Hope this helps. You can also contact Altera technical support at
800-800-3753.
-Gary
"Ryan" <ryans@cat.co.za> wrote in message news:<3dbf22af.0@obiwan.eastcoast.co.za>...
> HI
>
> I am trying to implement a little ALU in VHDL. Below is a toned down portion
> of my code. When I try and compile it using Quartus 2.1, Web Edition, I get
> the following run time error message that pops up in a window:
>
> Internal Error: Sub-system: LPMS, File: ./lpms_root.cpp, Line: 842
> (op->is_signed() && op_iterm->is_vcc()) || (!op->is_signed() &&
> op_iterm->is_gnd())
> Quartus II Version 2.1 Build 166 07/08/2002 SJ Web Edition
>
> Here is my code, please note that I cannot change the entity as it is 100%
> correct for the remaining SIGNED operations:
>
>
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
> USE ieee.numeric_std.all;
>
>
> ENTITY ALU IS
> PORT
> (
> A : IN SIGNED (11 downto 0);
> B : IN SIGNED (11 downto 0);
> CLK : IN STD_LOGIC;
> Z : OUT SIGNED (11 downto 0)
> );
>
> END ALU;
>
> ARCHITECTURE ALU_architecture OF ALU IS
> BEGIN
>
> arithmetic:
> PROCESS(CLK)
> BEGIN
> if CLK'event then
>
> Z <= SHIFT_RIGHT(A, TO_INTEGER(UNSIGNED(B(2 DOWNTO 0))));
>
> end if ;
> END PROCESS;
> END ALU_architecture;
>
> If anyone has any suggestions on why the error is present or ideas how else
> to perform a shift using the 2 input variables, they will be greatly
> appreciated because I am about to pull my hair out!
>
> Thanks
> Ryan
Article: 49023Hi Stephen, Without seeing your .ESF file itself it is hard to definitely pinpoint the problem However, here are some questions and suggestions. 1) Have you tried to move the regions at all through TCL? You mention this later on in your posting (just changing the ll_origin assignment does NOT refresh the node locations. Currently this must be done through the GUI). Changing the LL_ORIGIN statement through TCL is an almost sure-fire way to break things. 2) Have you tried changing the LL_PARENT assignment through TCL? Changing the parent may require the region to be moved. The GUI knows how to handle this, but the TCL interface does not. As a result, some regions may not be within their parent region. This will also generate messages like the ones you are seeing. Again, do not change the LL_PARENT from TCL. 3) It is always a good idea to have registered boundaries between modules. Some things you can check to help you narrow down what is going wrong are: 1) Use the GUI to do the same steps that you are trying to do from TCL. Does it work there? (if it does, I would guess that your problems are related to number 1 or 2 above) Do the regions show up RED in the Logiclock Window after you import them? Or does everything look okay and you still get these error messages when compiling? (in this case I would say #3 above is part of your problem) 2) Use the GUI in the lower level to see if the regions are okay (ie all nodes are within the region boundaries) On a side note, here are some comments about your methodology: You say that multiple people are working co-operatively on this design. I assume that you need the TCL script because people may change the placement of lower level modules and you want to have an automatic merge and update of the top-level design. I would recommend you go about doing this as follows: Do your initial merge using the GUI. Do your importing, moving, changing parents etc. all through the GUI the first time. Now that you have a "good" top level design where everything works and makes sense, you are are ready to use the TCL script to "update" any of the regions that need changing. Using the cmp logiclock_import 0 1 0 1 0 "region_name" Where region_name is the name of the region you want to update, and in your case you would run this command once for every region. This command preserves the placement of the region in the top level, and the LL_PARENT settings. With this flow, you can do all of your top-level floorplanning, and only update the contents of the regions. As an additional benefit, it also eliminates the need to try to move regions around using TCL, while only forcing you to use the GUI once. Hope this helps. -Gary Sugita stephen.busch@web.de (stephen) wrote in message news:<6643d19f.0210240712.62595be2@posting.google.com>... > Hi, > I'm using the LogicLock design flow to incrementally place and route > a design on a APEX1500KE device. Several people work on the project > and I > need to automate the compilation flow, so everything is done with tcl > scripts. > > I followed the instructions from Altera but I still have some > problemes. The structure of the design is something like this : > top +-- A > | +--- AA > | +--- AB > | +---ABA > | +---ABB > +-- B > | +--- BA > | +--- BB > | +---BBA > | +---BBB > > Here is what I do : > . I generate a edf file for each module (AA, BA, ABA, ABB, BBA, BBB) > with Leonardo. > . I run quartus for each submodule (AA, BA, ABA, ABB, BBA, BBB) to > generate the esf and vqm files. Each submodule contains one or > more > LogicLock regions. > . to generate the esf and vqm file of bloc AB I use the vqm and esf > files > generated for ABA and ABB plus an additional edf file. To enforce > the > hierarchie I use the LL_PARENT assignment. I change this > assignment > after importing the lower level .esf files, otherwise it doesn't > work. > ... > . for the final place and route I use the files A.vqm A.esf B.vqm > B.esf and > top.edf. The LogicLock regions defined are visible and have the > correct > size at the top level. The position is chosen automaticly by > quartus > for the moment. > > For the lower levels everything is fine but I get some problems at the > top > level. I get a lot of messages like the one : > Warning: Ignored back-annotated location assignment on node > bmicro:bmicro_inst|i2c:i2c_enabled_i2c_inst|i2c_intermediaire:i2c_intermediaire_inst|i2c_reste:reste|modgen_eq_445_ix46~I_I > assigned to LogicLock region > i2c_i2c:i2c_enabled_i2c_inst_bmicro:bmicro_inst because location is > outside region boundaries > How could this happen ? At the lower levels all the cells where inside > the > logiclock region and I didn't get the message. For the moment I didn't > try > to move manually the regions. > > Quartus also complains about carry chains it couldn't place inside a > low level > logiclock region. But I didn't get this message when it fitted this > region or > the next higher level. > > My next problem is that I need to chose the position of the logiclock > regions > because of timing issues. I can do this using the quartus gui but I > want to > move them from a tcl script. When I only change the LL_ORIGIN > assignment > the LL_LOCATION assignments aren't updated. Does anyone know which > command > I need to run ? > > thanks for you help > stephenArticle: 49024
Hi, I'm looking for a recommendation for a serial EEPROM to use to program an Altera 1k100. I prefer an 8-pin DIP package that is pin-compatible with the Altera EPC1PC8. Thanks, Scott
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