Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi! Does anyone know or have used the Quartus II? If so, I am looking for an inexpensive FPGA such that I can build a cable to communicate with the chip directly. I don't want to purchase the programmer. Some of these kits are $150. I am on a budget and just want to get my feet wet. Can someone recommend an FPGA (or CPLD if it's best) such that I can use Quartus II VHDL or if that application is not the best please recommend one. My goal is to program an FPGA with free software and a simple cable I can construct. Once I get the hang of it, I'll be willing to buy something better. I don't want to spend 100s of $ on something that doesn't work with me well. Can someone please give me some hints? Thanks!Article: 56926
Followup to: <3EF0774B.BB3A8743@yahoo.com> By author: rickman <spamgoeshere4@yahoo.com> In newsgroup: comp.arch.fpga > > > > Quickswitches is the way to deal with that. They aren't very > > expensive and they handle 5.0<->3.3 V PCI just fine. > > Yes, but that is very expensive in terms of board area. PC/104 is a > very compact format and level converters take up way too much space to > be practical. I am facing the same problem. I am planning to use a 5 > volt tolerant CPLD if I can get the right pricing. > I'm surprised you think they take up that much space. I'm sitting in front of a PC-104+ board which uses quickswitches for the voltage conversion and the whole set of level converters takes up a rectangle of about 6x40 mm. It's not insignificant, but it's quite tiny compared to the PC-104+ connector itself. On our board it is more than well compensated for by being able to use a more advanced FPGA. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 56927
Philip Freidin <philip@fliptronics.com> wrote in message news:<a730fv8ie9qo30r0c2af1bbe1fhjbffhqb@4ax.com>... > On 17 Jun 2003 19:56:26 -0700, panjuhwa_fpga@yahoo.com (PanJuHwa) wrote: > >Can we actually do that, and how? > >Will a larger time be incurred in configuring with rbt, since each bit > >is represented by 1 byte in ascii? Can we convert *.rbt back to *.bit? > >Thanks! > > If you are storing the bitstream in a PROM, or using a local > processor for configuration, you need to get it into the > right format. Neither the RBT or BIT files are exactly right. > > Either use a PROM formatting progam that reads these files and > formats it appropriately, or write your own. What then is the correct format? If I'm using a local processor for configuration, what are the steps to take to configure the FPGA, if I have on hand an RBT file? Thanks for your help again. > > Getting back to your original question: The difference in speed > of the two file formats is how long it takes you to read the file, > which is about 8:1 . Depending on environment, this is irrelevant. > > Philip Freidin > > > > > Philip Freidin > FliptronicsArticle: 56928
Three companies come to mind that do these conversions, Atmel, AMI and Chip Express. I contracted with Atmel once to help a customer convert a design from a FPGA to ASIC. The original flow was schematic with no regard to gated clocks, testability, etc, etc. They had alot of timing issues in previous conversions and I saw why. You didn't say how your original design was captured, VHDL, verilog or schematic. What is the time crunch, month? two months? six months? If you didn't do a synchronous design, (combinatorially generated clocks) you are going to have BIG problems regardless of how the design ends up in ASIC form. Remember timing changes from FPGA to ASIC. Good luck and watch those NREs. Jerry "Nagaraj" <nagaraj_c_s@yahoo.com> wrote in message news:91710219.0306172121.37274fb1@posting.google.com... > Hello all, > I have my prototype design in Spartan IIE 400K -7 device (package > FT256). As our high volume application is power,size and cost > oriented, we have to migrate to ASIC. > Because of time crunch, we are not in a position to follow the entire > ASIC design flow. > I want you to suggest some alternatives. One alternative I have in > mind is this. If Xilinx or 3rd party can take our FPGA design and map > it to a one-to-one customized ASIC, we can save the time on ASIC flow > and ASIC verification. What I mean is that start with the FPGA device > and do these things: > 1. Remove the unused dedicated resources as well as logic/routing > resources (for example we are using only 5% of BRAMs. So all other > BRAMs can be removed) > 2. Remove IOBs of unused pins and keep only those pins which are in > use (we are using only 30% of I/O pins.) > 3. Change the packaging if possible. > > My question is whether this kind of service is available with XILINX > or any other 3rd parties? > If not could you suggest some other alternative? > > Regards, > Nagaraj CSArticle: 56929
The format of the partial reconfiguration bitstream generated by BITGEN differs from that presented in XAPP151. There is an additional write to FAR register with frame address set to RAM Block 0 following the normal data frames writes and prior to CRC check. Which is the format to adopt? Or does it matter whether or not the additional FAR write is included? BITGEN GENERATED BITSTREAM FORMAT Write the COR with the Shutdown bit = 1. Write the START command into the CMD register. Write the pre-calculated CRC to the CRC register, or do a RESET CRC command to the CMD register. Clock the shutdown sequence. Write the AGHIGH command to the CMD register to prevent internal contention. Write the COR with shutdown = 0. Write all your frames. ***************ADDITONAL FAR WRITE.******** Write the CRC check value into the CRC. Write the LFRM command to the CMD register. Write one dummy frame to the FDRI register. Write the START command to the CMD register. Write the CRC value into the CRC. Clock the startup.Article: 56930
you can try here http://www.fpga4fun.com/board_pluto.html if you're willing to assemble the board yourself. JeanArticle: 56931
Peter Alfke wrote: > > Here is what I learned: > Based on idle-current measurements of the Spartan3-50 and -1000 > (the -50 has 1536 LUTs and flip-flops, the -1000 has 15,360 LUTs and > f-fs) > > The -50 has a typical Icc0 for the core of 50 mA, and 75 mA for Iccaux > The -1000 has a typical Icc0 for the core of 150 mA, and again 75 mA for Iccaux. > The core uses 1.2 V, Vccaux is 2.5 V. > > These idle-current measurements were taken at room temperature, and they > are not guaranteed max values. Interesting. But better than a Pentium :) -50 50mA/60mW 75 mA/187.5mW = 247mW -1000 150mA/180mW 75 mA/187.5mW = 367mW Darn, my 150mW guess was a bit low, tho I could claim that was meaning the core only, and not the Iccaux :) A couple of questions appear in these numbers. Q: I can understand the core has junctions by the truckload, but why the Icc aux - where is this going ? Q: numbers are 3:1 for 50:1000, suggests a junction-count ratio of only 3:1 between 50 & 1000 device - sounds low ? Q: how do these scale with Temp ? <paste> > There is leakage current, and then there is leakage current... > > In the distant past, leakage current was usually the current through a > reverse-biased junction or diode, and any good process allowed very low > leakage current at room temperature. Microamps of leakage were a sign of > something fishy, and the part was (or should be) rejected. > > Now we have something called sub-threshold leakge current. It is a > current that takes the normal, legitimate path from source to drain > through a transistor that is supposed to be turned off by a high enough > gate voltage. Trouble is, the available gate voltage does not exceed the > threshold enough to really turn the transistor off. So there are several > nanoamps of current, sub-threshold leakage current, but NOT > reverse-biased diode leakage current. And it is not an indication of > poor processing. With millions of transistors even in our small chips, > this current takes on undesirable proportions, but there is nothing we > or you can do about it. > Of course you can always buy the older more conservative 0.25 and 0.35 > micron parts that can turn off their transistors perfectly... > High-performance sub-micron CMOS cannot have low idle current. > Then everyone should find this interesting : http://www.toshiba.co.jp/about/press/2003_06/pr1001.htm Seems Toshiba have found a way to make a 1000:1 gain in what they only call 'gate leakage' static Icc numbers, and at 65nm design point. They do not give actual Icc figures. -jgArticle: 56932
On 18 Jun 2003 18:49:59 -0700, panjuhwa_fpga@yahoo.com (PanJuHwa) wrote:
>Philip Freidin <philip@fliptronics.com> wrote in message news:<a730fv8ie9qo30r0c2af1bbe1fhjbffhqb@4ax.com>...
>> If you are storing the bitstream in a PROM, or using a local
>> processor for configuration, you need to get it into the
>> right format. Neither the RBT or BIT files are exactly right.
>> Either use a PROM formatting progam that reads these files and
>> formats it appropriately, or write your own.
>
> What then is the correct format? If I'm using a local processor for
>configuration, what are the steps to take to configure the FPGA, if I
>have on hand an RBT file?
>
> Thanks for your help again.
There are so many possibilities, and you haven't given enough
info to guess what way you are going. So here is an example:
Loading FPGA with serial slave mode.
Bitstream is in RBT format.
Local processor is an 8 bit micro, with assorted parallel port
bits that can be individually set high and low.
Micro has sufficient EPROM/FLASH memory to hold its program
and the config data for the FPGA.
Connect uP parallel output port bits to FPGA Din, CCLK, PROGRAM
Connect uP parallel input bits to FPGA DONE, INIT, Pullup resistor on both
Go read http://www.fpga-faq.com/archives/33100.html#33108
Take the .RBT data, and write a dinky program to take the data
starting at line with 1111111... and turn it into initialization
data for your microprocessor:
i.e. (spaces added for clarity on lines 8 and 9)
Xilinx ASCII Bitstream
Created by Bitstream E.35
Design name: lin_prod.ncd
Architecture: xc4000xl
Part: 4085xlbg560
Date: Mon Jun 10 14:29:19 2003
Bits: 1924992
11111111 00100001 11010101 11110111 10011111
01011011 11111111 11111111 11011111 11111101
11011111 11011101 11111101 11011111 11011101
etc ....
becomes (if you are programming micro in assembler)
config_data:
DB $FF, $21, $D5, $F7, $9F
DB $5B, $FF, $FF, $DF, $FD
DB $DF, $DD, $FD, $DF, $DD
etc ....
becomes (if you are programming micro in C)
char config_data[240626] = {
0xFF, 0x21, 0xD5, 0xF7, 0x9F,
0x5B, 0xFF, 0xFF, 0xDF, 0xFD,
0xDF, 0xDD, 0xFD, 0xDF, 0xDD,
etc ....
};
You will find that after the end of the bitstream, you NEED
to send some extra "1" bits for the chip to sequence through
the startup states. I make the data array longer by 2 bytes,
and set all bits to a "1". This works fine.
Assemble/compile in with your micro's program.
Write code that reads this data when your system starts up,
and sends it out to the FPGA one bit at a time.
The data is sent MSB first, in byte sequence as given
in the above examples of config-data. If you had assembled
this data backwards (which happens because people are careless)
then you would send it out LSB first. Just be consistent. The
data MUST (MUST , MUST, MUST) arrive at the FPGA in the same
order that it appears in the .RBT file if you read it from
left to right, top to bottom.
Before starting to send the data, to the FPGA, You need to get
it ready.
Set the PROGRAM signal low.
Check that the DONE and INIT are both LOW
Set the PROGRAM signal high
Wait for INIT to go HIGH
Wait 5 more microseconds
Start sending data
To bit-bang the data out to the FPGA, the sequence looks
something like this:
repeat:
Set CCLK line low.
Set Din line to the next bit
set CCLK line high.
are we done? if not go to repeat
While sending the data, if INIT goes low, you have a framing
or CRC error.
When you have finished sending all the data, the DONE signal
should go high (sometime during the trailing 16 "1" bits).
You can see some more detailed code at:
http://www.fpga-faq.com/FAQ_Pages/0028_Downloading_a_Bitstream_under_Linux.htm
There are several other ways to configure the FPGAs, including
parallel and JTAG. The mechanism of getting the data to the
FPGA is different, but in the limit, the data that is loaded is
exactly the same, and the bit order must be exactly as given.
Philip Freidin
Philip Freidin
Fliptronics
Article: 56933"H. Peter Anvin" wrote: > > Followup to: <3EF0774B.BB3A8743@yahoo.com> > By author: rickman <spamgoeshere4@yahoo.com> > In newsgroup: comp.arch.fpga > > > > > > Quickswitches is the way to deal with that. They aren't very > > > expensive and they handle 5.0<->3.3 V PCI just fine. > > > > Yes, but that is very expensive in terms of board area. PC/104 is a > > very compact format and level converters take up way too much space to > > be practical. I am facing the same problem. I am planning to use a 5 > > volt tolerant CPLD if I can get the right pricing. > > > > I'm surprised you think they take up that much space. I'm sitting in > front of a PC-104+ board which uses quickswitches for the voltage > conversion and the whole set of level converters takes up a rectangle > of about 6x40 mm. It's not insignificant, but it's quite tiny > compared to the PC-104+ connector itself. On our board it is more > than well compensated for by being able to use a more advanced FPGA. I only wish I had that much space. First, I suspect your board is slave only, ours is master *and* slave. So we would need a lot more parts. But even so, 240 mm^2 is only slightly smaller than the 17 x 17 mm BGA that will be either a CPLD or an FPGA that will not only provide the 5 volt tolerant IOs, but will also provide the PC/104 interface logic as well as a lot of other stuff... *and* do it all in a relatively low power mode with the main FPGA and DSP (power hogs) powered down if needed. The Altera EP1K30 is looking pretty good. The standard pricing is about $17, so I should be able to get it for about $12 or so which is about the same price as a bunch of MSI parts to just do the isolation. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56934
I am trying to get a bidirectional data bus connected to a ram block. the bus data: BUS_Data : inout std_logic_vector(7 downto 0); the ram: RAM: RAMB4_S8 port map ( DI => BUS_Data, EN => '1', WE => BUS_WriteEnable, RST => Reset, CLK => Clock, ADDR => BUS_Address, DO => local_DataO (some local 8 bit signal) ); the tri-state: BUS_Data <= local_DataO when (BUS_WriteEnable = '0') else (others => 'Z'); modelsim shows my BUS_Data signal as conflicts (X) all through the simulation; I tried tons of variations, etc it still does not work. How can I achieve that? I just need a bidirectional 8 bit data bus connected to a ram and other components; but as soon as I added tristate buffers to my design, I started to have major issues with conflictsArticle: 56935
nospam <nospam@nospam.invalid> wrote in message news:<581uev026jm0r96pt2duth2pdbv7jbalk7@4ax.com>...
> Given this construct
>
> always @(posedge CLK or posedge RST) begin
> if(RST || crrst) begin
> mst <= 0;
> end else if(en1) begin
> mst <= 1;
> end
> end
>
Hi,
why don't try like this.
wire new_rst = RST || crrst;
always @(posedge CLK or posedge new_rst)
begin
if(new_rst)
begin
mst <= 0;
end
else if(en1)
begin
mst <= 1'b1;
end
end
> the current XST barfs about not matching "known FF".
> XST is happy with this equivalent construct
>
> always @(posedge CLK or posedge RST) begin
> if(RST) begin
> mst <= 0;
> end else if(en1 || crrst) begin
> mst <= !crrst;
> end
> end
>
>
> Is this the least ugly alternative?
Article: 56936Followup to: <3EF12CCF.8D13956B@yahoo.com> By author: rickman <spamgoeshere4@yahoo.com> In newsgroup: comp.arch.fpga > > > > I'm surprised you think they take up that much space. I'm sitting in > > front of a PC-104+ board which uses quickswitches for the voltage > > conversion and the whole set of level converters takes up a rectangle > > of about 6x40 mm. It's not insignificant, but it's quite tiny > > compared to the PC-104+ connector itself. On our board it is more > > than well compensated for by being able to use a more advanced FPGA. > > I only wish I had that much space. First, I suspect your board is slave > only, ours is master *and* slave. > It's PCI-104 only, but carries all the PCI-104 signals (only one set of INT#, CLK, REQ# and GNT#, though.) The only difference between master and slave is the REQ# and GNT# signals. We don't use the ISA side. > So we would need a lot more parts. But even so, 240 mm^2 is only > slightly smaller than the 17 x 17 mm BGA that will be either a CPLD > or an FPGA that will not only provide the 5 volt tolerant IOs, but > will also provide the PC/104 interface logic as well as a lot of > other stuff... *and* do it all in a relatively low power mode with > the main FPGA and DSP (power hogs) powered down if needed. > > The Altera EP1K30 is looking pretty good. The standard pricing is about > $17, so I should be able to get it for about $12 or so which is about > the same price as a bunch of MSI parts to just do the isolation. Right, if you need something in that class then it's not worth having the isolation separate. For higher density parts, though, the price goes way up, or 5V parts are completely unavailable. However, you're quite a bit off on the price. You need two QS34X245Q3 parts (each handles 32 signals), and they list for $1.60 apiece on Avnet. Not competitive for low end stuff, obviously. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 56937
Hello, I need to port the JAM STAPL player, version 2.3, to MS-DOS. Unfortunately my .jam file has a size > 64k and so on line 192 of jamheap.c the if instruction failed and jam.exe exit with error: Error on line 57: out of memory. Program terminated. Any idea to overcome this problem? Thanks in advance.Article: 56938
"Bazaillion" <nospam@nospam.org> schrieb im Newsbeitrag news:3tr1fvoht0mhnbfaer4c2o39dij8v57rr0@4ax.com... > So could a Spartan IIe 300K be used to create a graphics processor > (GPU Only) for a homebrew console on > par with like a 16 Bit SuperNintendo (SNES) ? A a rough guess I would say this is possible. Most of the ressources in the pacman from fpgaarcade.com is used for the Z80 implementation. > Or for that matter could any FPGA board under $1000 give this kind of > performance or could they even do better? The Spartan-IIE series is the way to go. Maybe there is a board available with a 400 or even 600k gate part. I dont know aboput Altera parts. -- Regards FalkArticle: 56939
muthu_nano@yahoo.co.in (Muthu) wrote: >nospam <nospam@nospam.invalid> wrote in message news:<581uev026jm0r96pt2duth2pdbv7jbalk7@4ax.com>... >> Given this construct >> >> always @(posedge CLK or posedge RST) begin >> if(RST || crrst) begin >> mst <= 0; >> end else if(en1) begin >> mst <= 1; >> end >> end >> > > >Hi, >why don't try like this. > >wire new_rst = RST || crrst; > >always @(posedge CLK or posedge new_rst) >begin > if(new_rst) > begin > mst <= 0; > end > else if(en1) > begin > mst <= 1'b1; > end >end That isn't quite the same, crrst is a synchronous clear in the original. I had seen a Xilinx suggestion of moving logic expressions outside the always block to work around the problem.Article: 56940
H. Peter Anvin <hpa@zytor.com> wrote: : Followup to: <3EF0774B.BB3A8743@yahoo.com> : By author: rickman <spamgoeshere4@yahoo.com> : In newsgroup: comp.arch.fpga :> > :> > Quickswitches is the way to deal with that. They aren't very :> > expensive and they handle 5.0<->3.3 V PCI just fine. :> :> Yes, but that is very expensive in terms of board area. PC/104 is a :> very compact format and level converters take up way too much space to :> be practical. I am facing the same problem. I am planning to use a 5 :> volt tolerant CPLD if I can get the right pricing. :> : I'm surprised you think they take up that much space. I'm sitting in : front of a PC-104+ board which uses quickswitches for the voltage : conversion and the whole set of level converters takes up a rectangle : of about 6x40 mm. It's not insignificant, but it's quite tiny : compared to the PC-104+ connector itself. On our board it is more : than well compensated for by being able to use a more advanced FPGA. Any source for those quick switches in small quantities? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 56941
Hi Thomas
"Thomas" <tom3@protectedfromreality.com> escribió en el mensaje
news:oprqzy3agpmo2d8p@news3.news.adelphia.net...
>
> I am trying to get a bidirectional data bus connected to a ram block.
>
> the bus data:
>
> BUS_Data : inout std_logic_vector(7 downto 0);
>
> the ram:
>
> RAM: RAMB4_S8 port map ( DI => BUS_Data, EN => '1', WE => BUS_WriteEnable,
> RST => Reset, CLK => Clock, ADDR => BUS_Address, DO => local_DataO (some
> local 8 bit signal) );
>
> the tri-state: BUS_Data <= local_DataO when (BUS_WriteEnable = '0') else
> (others => 'Z');
>
> modelsim shows my BUS_Data signal as conflicts (X) all through the
> simulation; I tried tons of variations, etc it still does not work. How
can
> I achieve that?
If you're using modelsim you can open the dataflow window to show
the drivers of your tristate bus (or any other signal) and trace where your
X's come from.
It usually helps to put all driver enables together in the wave window to
see if they overlap.
You'll get X not only when bus conflicts but also if you're trying to drive
the bus with an
unknown value (for example, reading a non-initialized RAM cell and using the
result data
to drive the bus).
>
> I just need a bidirectional 8 bit data bus connected to a ram and other
> components; but as soon as I added tristate buffers to my design, I
started
> to have major issues with conflicts
Regards
Francisco Rodriguez
================================================================
Francisco Rodriguez Ballester (prodrig at disca dot upv dot es)
Postal address: Dept. DISCA, EUI - Univ. Politecnica de Valencia
c/Camino de Vera s/n, E-46022, VALENCIA (SPAIN)
tlf: +(34) 96 387 70 07 ext. 75759 - fax: +(34) 96 387 75 79
================================================================
Article: 56942This is quite a remarkable info. Do you mean the "Quiescent supply current" (Icco in the data-sheets)? And why do you report only the maximum value (3 or 6mA, document DS06 v1.6) and not also a typical one? Basing on these values we renounced to try a porting from Acex to Spartan in a project in which the standby current was a very important factor. So I am now stuck with the Cyclone (it costs a lot less than Acex), which I fear in standby could require a significant current. Iode "Austin Lesea" <Austin.Lesea@xilinx.com> ha scritto nel messaggio news:3EF08BA4.19E96043@xilinx.com... > Rick, > > SpartanXL is still the best FPGA when it comes to quiescent leakage current. Most > parts come in below 100 uA. We have customers who use the SpartanXL for > applications where they need this extrememly low standby current. Note that we do > not specify this current (as it is a low cost product, and leakage current is not > supposed to be a limiting factor for yield). > > Also, don't forget startup current. SpartanXL has none, and Virtex II, II Pro, > and Spartan 3 have no startup current that is any larger than the standby > current. This can not be said for other FPGAs (from X as well as ....). > > Austin > > rickman wrote: > > > Iode wrote: > > > > > > Hi to everyone, > > > > > > Has anyone had experience porting a design from Acex to Cyclone? What should > > > I expect from the point of view of power consumption? Using the calculator > > > tools give worrying results: comparing a c30 with a 1k50 I have 33.5mA of > > > standby current for Cyclone, 5 mA for Acex; I/Os consumption also seems to > > > be higher in Cyclone; core consumption seems to be less but, all in all, am > > > I going to need more or less power using Cyclone? > > > > > > Perhaps less power while the clock is running but more power when in > > > stand-by? > > > > I am very glad you posted this question. I had been looking at using a > > CPLD in this design for the PC/104 bus interface, but all of the parts I > > was considering had limitations. But the ACEX 1K parts seem to meet all > > the needs and are still relatively low power. 5 mA standby is better > > than some of the CPLDs! I estimated a max power consumption of 40 mA > > running at 50 Mhz so this part hangs in there with the CPLDs in terms of > > dynamic power as well. > > > > If I can get a decent price, this part will solve a lot of my problems. > > > > BTW, I suggest that you call Altera support at 800-800-3753. I have > > found them to be very helpful and they even answer the phone fairly > > quickly. > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX >Article: 56943
Hi , How can you drive the inout port from inside the logic? Meaning if I have defined a variable and I want to assign this variable to inout port( bidirectional), then it didn't work. Eg. If have a shared variable A and I want to assign this value to the bidirectional bus B (inout). But in simulation I can't see anything happening. Rgds IsaacArticle: 56944
hi, guys, I am interested in developing high speed wireless modem (modulation/demodulation, channel coding/decoding and equalization) using FPGA. But I am new to FPGA. Anyone can evaluate if it worthy? 1. How long does it take to get into FPGA design? 2. How much money is needed for a FPGA development kit? Thanks in advance. FeiArticle: 56945
see my post about the bidirectional bus, I have the same problem; in theory: IOPort : inout Input: in Output : out process(IOPort, Output) is begin Input <= IOPort if(ReadingFromTheOutside = '1') then IOPort <= Output; else IOPort <= (others => 'Z'); end if; end process; should work, at least according to all docs I have read; in practice I can not make it work and I am looking for the answer. I always end up with a conflict (X) on the signal On 19 Jun 2003 06:19:41 -0700, Isaac <fpga_uk@yahoo.co.uk> wrote: > Hi , > How can you drive the inout port from inside the logic? > Meaning if I have defined a variable and I want to assign this > variable to inout port( bidirectional), then it didn't work. > Eg. If have a shared variable A and I want to assign this value to the > bidirectional bus B (inout). But in simulation I can't see anything > happening. > > Rgds > > Isaac >Article: 56946
"H. Peter Anvin" wrote: > > Followup to: <3EF12CCF.8D13956B@yahoo.com> > By author: rickman <spamgoeshere4@yahoo.com> > In newsgroup: comp.arch.fpga > > > > > > I'm surprised you think they take up that much space. I'm sitting in > > > front of a PC-104+ board which uses quickswitches for the voltage > > > conversion and the whole set of level converters takes up a rectangle > > > of about 6x40 mm. It's not insignificant, but it's quite tiny > > > compared to the PC-104+ connector itself. On our board it is more > > > than well compensated for by being able to use a more advanced FPGA. > > > > I only wish I had that much space. First, I suspect your board is slave > > only, ours is master *and* slave. > > > > It's PCI-104 only, but carries all the PCI-104 signals (only one set > of INT#, CLK, REQ# and GNT#, though.) The only difference between > master and slave is the REQ# and GNT# signals. We don't use the ISA > side. > > > So we would need a lot more parts. But even so, 240 mm^2 is only > > slightly smaller than the 17 x 17 mm BGA that will be either a CPLD > > or an FPGA that will not only provide the 5 volt tolerant IOs, but > > will also provide the PC/104 interface logic as well as a lot of > > other stuff... *and* do it all in a relatively low power mode with > > the main FPGA and DSP (power hogs) powered down if needed. > > > > The Altera EP1K30 is looking pretty good. The standard pricing is about > > $17, so I should be able to get it for about $12 or so which is about > > the same price as a bunch of MSI parts to just do the isolation. > > Right, if you need something in that class then it's not worth having > the isolation separate. For higher density parts, though, the price > goes way up, or 5V parts are completely unavailable. > > However, you're quite a bit off on the price. You need two QS34X245Q3 > parts (each handles 32 signals), and they list for $1.60 apiece on > Avnet. Not competitive for low end stuff, obviously. I was going to use bus exchange transceiver registers to share the interface to the FPGA to cut on the pin count. To use these parts as buffers would require that I go to a larger FPGA which would cost signficantly more $$$. Even so. How can you handle 88 signals with two 32 bit parts? There are 16 Data 27 Addr 11 IRQ 14 DMA 8 Cntl 12 MISC -------- 88 Total Slave mode 16 IO (Data) 42 In 30 Out If you use these larger 32 bit parts, you end up wasting a few bits because the IOs don't divide evenly into groups you can assign to the same register (like the SA address and the LA address). Also the IRQ needs individual controls on each of the 11 lines. By the time you are done, it ends up being more real estate than a 5 volt PLD or you need a 5 volt PLD for all the control signals. In either case, you still need a lot more IOs on the main FPGA which drives up the cost unless you needed the larger part for gate count and the IOs were there anyway. That is normally not true with the newer FPGAs. In our case we will need an XC3S400 just to get the IO count. Going to an XC3S1000 will cost a lot more. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56947
I created a video output on a CPLD (CoolRunner 2) and a FPGA (Spartan 2e); it is actually pretty straighforward. I did a video composite output, so the color is the biggest issue (not solved yet, but I have two solutions); black and white is easy. If you go with VGA it is much simpler. The biggest issue you will have to deal with is ringing because it shows on the TV. you can make it with a few counters On Thu, 19 Jun 2003 12:14:30 +0200, Falk Brunner <Falk.Brunner@gmx.de> wrote: > "Bazaillion" <nospam@nospam.org> schrieb im Newsbeitrag > news:3tr1fvoht0mhnbfaer4c2o39dij8v57rr0@4ax.com... > >> So could a Spartan IIe 300K be used to create a graphics processor >> (GPU Only) for a homebrew console on >> par with like a 16 Bit SuperNintendo (SNES) ? > > A a rough guess I would say this is possible. Most of the ressources in > the > pacman from fpgaarcade.com is used for the Z80 implementation. > >> Or for that matter could any FPGA board under $1000 give this kind of >> performance or could they even do better? > > The Spartan-IIE series is the way to go. Maybe there is a board available > with a 400 or even 600k gate part. > I dont know aboput Altera parts. > > -- > Regards > Falk > > > > > >Article: 56948
Uwe Bonnes wrote: > > H. Peter Anvin <hpa@zytor.com> wrote: > : Followup to: <3EF0774B.BB3A8743@yahoo.com> > : By author: rickman <spamgoeshere4@yahoo.com> > : In newsgroup: comp.arch.fpga > :> > > :> > Quickswitches is the way to deal with that. They aren't very > :> > expensive and they handle 5.0<->3.3 V PCI just fine. > :> > :> Yes, but that is very expensive in terms of board area. PC/104 is a > :> very compact format and level converters take up way too much space to > :> be practical. I am facing the same problem. I am planning to use a 5 > :> volt tolerant CPLD if I can get the right pricing. > :> > > : I'm surprised you think they take up that much space. I'm sitting in > : front of a PC-104+ board which uses quickswitches for the voltage > : conversion and the whole set of level converters takes up a rectangle > : of about 6x40 mm. It's not insignificant, but it's quite tiny > : compared to the PC-104+ connector itself. On our board it is more > : than well compensated for by being able to use a more advanced FPGA. > > Any source for those quick switches in small quantities? Avnet will sell them in mult of 24 on the web. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56949
Rick, The question of IO vs logic is always an issue here. Thanks for the feedback on the subject. It is something that we can never make everyone happy with. It is also something that if we add more IO, we directly increase the die size (at these sub micron geometries) as the IO doesn't shrink, but the core does. If you have some suggestions on a "family" of parts with IOs and logic sizes, I would appreciate hearing about it. In fact, if anyone has a strong opinion about LUT/IO/part, fill it out and email it to me: (for example- need more family members, but you get the idea) part LUTs IOs smallest 1500 200 mid 15,000 500 large 60,000 1000 ???? Austin rickman wrote: > Austin Lesea wrote: > > > > Rick, > > > > All true and accurate obsevations. > > > > SpartanXL has such a large following, that it is not going anywhere soon (ie it is fully > > supported for new designs). > > > > For example, we still support and manufacture the 3000A and 3100A FPGAs (although not > > recommended for new designs). Who else has support for designs that are this old? By > > Peter's IC time scale, these are ancient history! > > > > Have you looked at the small Virtex II parts recently (ie for price)? The 2V40, 2V80, > > 2V250 are all still there, and might be a good choice (no startup current)? > > Thanks for the ideas. I guess I had forgotten that the startup current > was fixed in the XC2V parts. Sometimes it is hard to keep it all > straight. But they require 1.5 volt power which is not present in that > part of the board. The board has three separate power zones and this > one has 5, 3.3 and 2.5 volts. I don't really want to add another > regulator. Also 65 mA typ Iccintq is not so low. I am trying to keep > the total FPGA power to about 50 mA or less. > > But the main problem is the price. Unless the web pricing is way out of > whack, I can't afford $80 for the XC2V250 which I need to get the IO > count. The Coolrunner starts lower than that and I still have not been > able to get disti prices to my $20 target. The XC2V40 is really tiny > and the XC2V80 is only a bit better. > > > Just because it is in the Virtex line doesn't automatically mean that it isn't used for > > volume or low cost applications. It was the intent of the APD group here to cover the > > smaller and higher volume applications with a more advanced product when we created the > > smaller Virtex II parts. > > That sounds good to me, but the prices are way up there still. The > XC2V40 might have some applications, but I can't use it at $25. > > > As with any smaller geometry, the leakage is going up (fast), so I am beginning to think > > of Virtex II as something like "classic cola" which represents a really good > > price/performance/feature point in the FPGA space, and one that is hard to improve upon > > (but we never stop trying). > > I know it is hard to make much money on the smaller, low cost parts. > But those are what most of our boards need. The XC3S400 fits our needs > because of the IO count, not the slice count. For our needs it is > actually large by any other measure. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z