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Messages from 61775

Article: 61775
Subject: Re: Counting ones
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 10 Oct 2003 12:19:37 -0700
Links: << >>  << T >>  << A >>
John, just to be contrary:
Remember my suggestion of using a 4K x 4 dual-ported BlockROM. So it can
take 24 inputs and generate two 4-bit outputs that then have to be
combined externally. On two BlockROMs you can have 48 inputs and then
combine 4 sets of 4 inputs in one or two CLBs. Fast and simple, but
needs a trigger clock, since BlockROMs are synchronous.

Peter Alfke, Xilinx Applications

>>>>>>>>>>>>  220 lines of un-needed quote removed by archive manager



Article: 61776
Subject: Re: pci-x133 to parallel pci-66
From: Richard Iachetta <iachetta@us.ibm.com>
Date: Fri, 10 Oct 2003 14:40:32 -0500
Links: << >>  << T >>  << A >>
In article <3F85E01C.A0E99EFA@xilinx.com>, eric.crabill@xilinx.com says...
> you will need to put in some design
> effort.

That's an understatement!

-- 
Rich Iachetta
I do not speak for IBM

Article: 61777
Subject: Re: pci-x133 to parallel pci-66
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Fri, 10 Oct 2003 20:17:31 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3F86E3E4.BED89355@xilinx.com>,
Eric Crabill  <eric.crabill@xilinx.com> wrote:
>PCI and PCI-X are not busses that provide guaranteed
>bandwidth.  I've seen bandwidth on a PCI 64/66 bus fall
>to 40 Mbytes/sec during certain operations because the
>devices on it were designed poorly (mostly for the
>reasons I stated in the first paragraph).

Also just type of transaction can contribute as well.  Just TRY
streaming through (in -> memory -> out) two 1 Gb ethernet ports when
you have full rate, minimum sized packets, using PCI or PCI-X based
hardware.

>I'm not trying to discourage you from using a Xilinx
>solution.  However, I'd prefer that potential customers
>make informed design decisions that result in the best
>combination of price/performance/features.

A very good attitude, I wish more companies would give such advice.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 61778
Subject: Questions on Function Approximation (using FPGAs)
From: dlee79@yahoo.com (D Lee)
Date: 10 Oct 2003 13:35:12 -0700
Links: << >>  << T >>  << A >>
Dear all,

I am working on (compound) function approximation with one input
variable using piecewise polynomial approximation with non-linear 
joints. These approximations are implemented in hardware using Xilinx FPGAs.

Example of such functions include: f(x)=sqrt(-ln(x)) or
f(x)=x*ln(x) where x = [0,1), which are used for Gaussian noise
generation (Box-Muller method) and Entropy calculation
respectively.

Does anyone know any other real-life applications where compound
functions need to be approximated?

My second question is on the function f(x)=sqrt(-ln(x)) over x =
[0,1). This function is highly non-linear and approaches infinity
as x gets close to zero. This requires floating point
implementation (due to the large polynomial coefficients, which I
want to avoid). Are there any transformations I am apply to the
function to decompose it 2 or more functions that are more linear?
(Note that ln(x) is also highly non-linear over x = [0,1))


Regards,

Dong-U Lee

Article: 61779
Subject: Virtex-II Pro Core Voltage on ML300
From: qlyus@yahoo.com (qlyus)
Date: 10 Oct 2003 13:59:20 -0700
Links: << >>  << T >>  << A >>
The core voltage on Xilinx Eval board ML3000 is 1.65V, according to
both schematic diagram and user's guide.  It is not 1.5V as datasheet
says. Can somebody shed light on why?

Thanks

-qlyus

Article: 61780
(removed)


Article: 61781
Subject: Re: Why no synthesis?
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Fri, 10 Oct 2003 14:16:14 -0700
Links: << >>  << T >>  << A >>
Vazquez wrote:
> Dear Mr Treseler,
> 
> thank youu for your answer. I have looked at the pdf-file you recommended.
> On page 50 there is the VHDL description of a single-clock synchronous RAM,
> but I use two clocks.

If you want to infer a dual clock ram,
you need to have a process for each clock.
See the architecture for lpm_ram_dp in

http://www.edif.org/lpmweb/more/220model.vhd

for an example.

However, if you want to simplify your timing
analysis, consider synchronizing your accesses
to a single clock and using a single clock ram.

  -- Mike Treseler


Article: 61782
Subject: Re: Questions on Function Approximation (using FPGAs)
From: Terje Mathisen <terje.mathisen@hda.hydro.com>
Date: Fri, 10 Oct 2003 23:22:01 +0200
Links: << >>  << T >>  << A >>
D Lee wrote:

> Dear all,
> 
> I am working on (compound) function approximation with one input
> variable using piecewise polynomial approximation with non-linear 
> joints. These approximations are implemented in hardware using Xilinx FPGAs.
> 
> Example of such functions include: f(x)=sqrt(-ln(x)) or
> f(x)=x*ln(x) where x = [0,1), which are used for Gaussian noise
> generation (Box-Muller method) and Entropy calculation
> respectively.
> 
> Does anyone know any other real-life applications where compound
> functions need to be approximated?

sqrt(1/x) is used so often that more than one modern cpu contains 
built-in lookup tables to generate a good starting point for a NR iteration.

> My second question is on the function f(x)=sqrt(-ln(x)) over x =
> [0,1). This function is highly non-linear and approaches infinity
> as x gets close to zero. This requires floating point
> implementation (due to the large polynomial coefficients, which I
> want to avoid). Are there any transformations I am apply to the
> function to decompose it 2 or more functions that are more linear?
> (Note that ln(x) is also highly non-linear over x = [0,1))

My first guess would be to look for some kind of rational approximation, 
even if this does require a final division.

Terje

-- 
- <Terje.Mathisen@hda.hydro.com>
"almost all programming can be viewed as an exercise in caching"


Article: 61783
Subject: Re: Virtex-II Pro Core Voltage on ML300
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Fri, 10 Oct 2003 14:27:17 -0700
Links: << >>  << T >>  << A >>
qlyus,

Yes.  I can do that.

Initial samples from the very first lots of silicon required a Vccint of
1.65 volts due to a design issue (check with your FAE to read the errata
list for the ES parts).  This was more than two years ago, now.

This issue was addressed (fixed) long before we started shipping
production parts.

Since 1.65 volts is allowed per the absolute maximum specifications, and
the parts were tested at these conditions, we could ship them as ES, and
be assured that they would meet all applicable specifications.

Please be certain that the board and part you have is from this early
lot, as it will be marked with the "ES" marking, rather than the standard
production marking.

I am assuming this is a ML300 board, not a ML3000....

Austin

qlyus wrote:

> The core voltage on Xilinx Eval board ML3000 is 1.65V, according to
> both schematic diagram and user's guide.  It is not 1.5V as datasheet
> says. Can somebody shed light on why?
>
> Thanks
>
> -qlyus


Article: 61784
Subject: Re: Graphics rendering revisited
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Fri, 10 Oct 2003 16:50:45 -0500
Links: << >>  << T >>  << A >>


Vinh Pham wrote:

>>Interesting theoretical enterprise, but I really don't see the point.
>>    
>>
>
>Someone just had a rare situation where they couldn't use a frame buffer.
>You can think of it as an intellectual exercise :_)
>
>  
>
>>I remember quite some years ago talking to a guy who had invested millions
>>    
>>
>of $ in developing
>
>Hahaha no wonder he refused to believe you.  Sort of like when you buy a
>crappy product, but you make yourself believe it's great, because of all the
>money you spent on it.
>
>Did E&S's vector display draw only outlines of spheres, or shaded?  Shading
>with x-y vectors doesn't sound too fun.
>  
>
Oh, no, it painted them in very nicely.  I don't remember whether it had 
a variable-width
electron beam.  They use this in the Rediffusion flight simulators and 
some other
gear that I think had E&S image generators at the end of the processing 
chain.
It looked much like Gouraud shading.  Yes, that's why the thing cost 
several hundred
K $.

>What do you think was the main reason why people switched to pixel/raster?
>Simplicity?  Scales better?
>  
>
Plain cost.  Imagine how insanely difficult it would be to have a color 
CRT with a
variable beam width, able to deflect from one side of the screen to the 
other in a
couple of uS, and maintain focus and purity while doing all that!  Then, 
you need a
geometry engine and have to solve all the occlusion and clipping 
problems while
flying through  the graphics data base one time only.  With raster, you 
can push a
lot of that work into the logic such that it all gets sorted out when 
the most foreground
pixel is rewritten.  With vector, you better not write an occluded 
background mark,
because the CRT can't erase what it has already drawn.  Larger, faster, 
cheaper memory
made raster POSSIBLE!  When E&S designed this stuff, you just couldn't 
do read-modify-
write cycles fast enough to make a usable raster system without making 
something
like a 1024-bit wide memory word, and doing all the read-modify-write 
work at
1024-bit word width.  There actually were some late 1970's imaging 
systems that
did this, they cost about $3 million per viewport and filled 5 6-foot 
rack cabinets.
Obviously, only for the absolute highest-end flight simulator systems 
and such.

Jon


Article: 61785
Subject: Re: Graphics rendering revisited
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Fri, 10 Oct 2003 16:55:19 -0500
Links: << >>  << T >>  << A >>
Martin Euredjian wrote:

"Jon Elson" <jmelson@artsci.wustl.edu> wrote:

  
I guess you are talking about raster-scan displays without a pixel to
    
pixel
  
frame buffer behind it, and not about vector-drawing displays (like an
oscilloscope in X-Y mode).

Interesting theoretical enterprise, but I really don't see the point.
    

And you wouldn't outside of a contextual reference frame that allowed you to
understand where/why this might be important.  It's a very narrow field of
application.  Not mainstream at all.


  
Well, I'm still not sure I understand it, after reading all the above.  The reason for
this is to convert from one video fomat (HD broadcast?) to another (high-end 
computer LCD monitor - DVI) without introducing a one (or more) frame delay?
But, apparently, you ARE forced to delay the 2nd field, to make it show on a
non-interlaced display.

Or, do the different scan rates come into play, as the output frame rate has no
relationship to the input frame rate?

Jon



Article: 61786
Subject: Re: Counting ones
From: "John_H" <johnhandwork@mail.com>
Date: Fri, 10 Oct 2003 22:21:16 GMT
Links: << >>  << T >>  << A >>
Peter's:  solution for 48 bits:
  2 BlockRAMs, 16 LUTs
  BlockRAM  tcko + 2 levels carry chain
John's solution for 30 bits:
  Resources:  46 LUTs (giving him 1 LUT per CYAdd bit)
  Delay:  2 levels LUTs + 3 levels carry chain
John_H's solution for 31 bits (mine, at end):
  Resources:  41 LUTs
  Delay: 3 levels LUTs + 2 levels carry chain

"Peter Alfke" <peter@xilinx.com> wrote in message
news:3F870649.447B1CA3@xilinx.com...
> John, just to be contrary:
> Remember my suggestion of using a 4K x 4 dual-ported BlockROM. So it can
> take 24 inputs and generate two 4-bit outputs that then have to be
> combined externally. On two BlockROMs you can have 48 inputs and then
> combine 4 sets of 4 inputs in one or two CLBs. Fast and simple, but
> needs a trigger clock, since BlockROMs are synchronous.
>
> Peter Alfke, Xilinx Applications


See original post for John's earlier comments as well as my own.  In John's
form of ASCII art is the 3-input LUT form of a 31 bit adder that won't work
for 32 bits wihtout adding a bit of extra junk but is a more common need.

- John_H

   ___
0-| F |          ___
0-| A |-1-----1-|   |-2-----+
0-|_3_|-0-----0-| * |-1---+ |
   ___    +---1-|   |-0-+ | |
0-| F |   | +-0-|___|   | | |
0-| A |-1-+ |     |     | | |
0-|_3_|-0---+     0     | | |    ___
0-----------------+     | | +-2-| C |
   ___                  | +---1-| Y |-3-------+
0-| F |          ___    +-----0-| A |-2-----+ |
0-| A |-1-----1-|   |-2-------2-| d |-1---+ | |
0-|_3_|-0-----0-| * |-1-------1-| d |-0-+ | | |
   ___    +---1-|   |-0-------0-|___|   | | | |
0-| F |   | +-0-|___|             |     | | | |
0-| A |-1-+ |     |               0     | | | |
0-|_3_|-0---+     0               |     | | | |
0-----------------+               |     | | | |
0---------------------------------+     | | | |
   ___                                  | | | |
0-| F |          ___                    | | | |
0-| A |-1-----1-|   |-2-----+           | | | |
0-|_3_|-0-----0-| * |-1---+ |           | | | |
   ___    +---1-|   |-0-+ | |           | | | |    ___
0-| F |   | +-0-|___|   | | |           | | | +-3-|   |
0-| A |-1-+ |     |     | | |           | | +---2-| C |-4
0-|_3_|-0---+     0     | | |    ___    | +-----1-| Y |-3
0-----------------+     | | +-2-| C |   +-------0-| A |-2
   ___                  | +---1-| Y |-3---------3-| d |-1
0-| F |          ___    +-----0-| A |-2---------2-| d |-0
0-| A |-1-----1-|   |-2-------2-| d |-1---------1-|   |
0-|_3_|-0-----0-| * |-1-------1-| d |-0---------0-|___|
   ___    +---1-|   |-0-------0-|___|               |
0-| F |   | +-0-|___|             |                 0
0-| A |-1-+ |     |               0                 |
0-|_3_|-0---+     0               |                 |
0-----------------+               |                 |
0---------------------------------+                 |
0---------------------------------------------------+

LUT count:
   16            12               8                 5   =  41

* The 2bit+2bit+1bit LUTS (0-7 result) are implemented as
  3 levelsof logic implemented with 3-input LUTs.



Article: 61787
Subject: Re: Counting ones
From: "John_H" <johnhandwork@mail.com>
Date: Fri, 10 Oct 2003 22:24:05 GMT
Links: << >>  << T >>  << A >>
...oops.
Mine was 45 LUTs.  16 luts in the second stage, not 12.
Delays stand as indicated



Article: 61788
Subject: Re: Counting ones
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 10 Oct 2003 16:18:06 -0700
Links: << >>  << T >>  << A >>
From a silicon-area efficiency the BlockRAM approach loses, for two
BRAMs occupy as much area as 24 CLBs = 192 LUTs.
But since this is not an a la carte restaurant where you have the option
to pay only for what you use, the BlockRAM can sometimes be considered
free, if nothing else needs it.
Who said choices were easy...
Peter Alfke
==================================
John_H wrote:
> 
> Peter's:  solution for 48 bits:
>   2 BlockRAMs, 16 LUTs
>   BlockRAM  tcko + 2 levels carry chain
> John's solution for 30 bits:
>   Resources:  46 LUTs (giving him 1 LUT per CYAdd bit)
>   Delay:  2 levels LUTs + 3 levels carry chain
> John_H's solution for 31 bits (mine, at end):
>   Resources:  41 LUTs
>   Delay: 3 levels LUTs + 2 levels carry chain
> 
> "Peter Alfke" <peter@xilinx.com> wrote in message
> news:3F870649.447B1CA3@xilinx.com...
> > John, just to be contrary:
> > Remember my suggestion of using a 4K x 4 dual-ported BlockROM. So it can
> > take 24 inputs and generate two 4-bit outputs that then have to be
> > combined externally. On two BlockROMs you can have 48 inputs and then
> > combine 4 sets of 4 inputs in one or two CLBs. Fast and simple, but
> > needs a trigger clock, since BlockROMs are synchronous.
> >
> > Peter Alfke, Xilinx Applications
> 
> See original post for John's earlier comments as well as my own.  In John's
> form of ASCII art is the 3-input LUT form of a 31 bit adder that won't work
> for 32 bits wihtout adding a bit of extra junk but is a more common need.
> 
> - John_H
> 
>    ___
> 0-| F |          ___
> 0-| A |-1-----1-|   |-2-----+
> 0-|_3_|-0-----0-| * |-1---+ |
>    ___    +---1-|   |-0-+ | |
> 0-| F |   | +-0-|___|   | | |
> 0-| A |-1-+ |     |     | | |
> 0-|_3_|-0---+     0     | | |    ___
> 0-----------------+     | | +-2-| C |
>    ___                  | +---1-| Y |-3-------+
> 0-| F |          ___    +-----0-| A |-2-----+ |
> 0-| A |-1-----1-|   |-2-------2-| d |-1---+ | |
> 0-|_3_|-0-----0-| * |-1-------1-| d |-0-+ | | |
>    ___    +---1-|   |-0-------0-|___|   | | | |
> 0-| F |   | +-0-|___|             |     | | | |
> 0-| A |-1-+ |     |               0     | | | |
> 0-|_3_|-0---+     0               |     | | | |
> 0-----------------+               |     | | | |
> 0---------------------------------+     | | | |
>    ___                                  | | | |
> 0-| F |          ___                    | | | |
> 0-| A |-1-----1-|   |-2-----+           | | | |
> 0-|_3_|-0-----0-| * |-1---+ |           | | | |
>    ___    +---1-|   |-0-+ | |           | | | |    ___
> 0-| F |   | +-0-|___|   | | |           | | | +-3-|   |
> 0-| A |-1-+ |     |     | | |           | | +---2-| C |-4
> 0-|_3_|-0---+     0     | | |    ___    | +-----1-| Y |-3
> 0-----------------+     | | +-2-| C |   +-------0-| A |-2
>    ___                  | +---1-| Y |-3---------3-| d |-1
> 0-| F |          ___    +-----0-| A |-2---------2-| d |-0
> 0-| A |-1-----1-|   |-2-------2-| d |-1---------1-|   |
> 0-|_3_|-0-----0-| * |-1-------1-| d |-0---------0-|___|
>    ___    +---1-|   |-0-------0-|___|               |
> 0-| F |   | +-0-|___|             |                 0
> 0-| A |-1-+ |     |               0                 |
> 0-|_3_|-0---+     0               |                 |
> 0-----------------+               |                 |
> 0---------------------------------+                 |
> 0---------------------------------------------------+
> 
> LUT count:
>    16            12               8                 5   =  41
> 
> * The 2bit+2bit+1bit LUTS (0-7 result) are implemented as
>   3 levelsof logic implemented with 3-input LUTs.

Article: 61789
Subject: Re: Graphics rendering revisited
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Fri, 10 Oct 2003 23:53:35 GMT
Links: << >>  << T >>  << A >>
"Jon Elson" wrote:

>Well, I'm still not sure I understand it, after reading all the above.

Because of the nature of the work I can't get into the sort of detail that
would paint the whole picture for you.  I apologize for that.

One way to look at it might be from the point of view of resources, data
rates, etc.  As you hike up in resolution/frame rate (say, 4K x 4K at 60
frames per second, which is what I'm working on) you need some pretty
massive frame store widths to be able to slow things down to where the
processing is manageable.  I was looking into the idea of not having to add
yet another frame buffer for something as "simple" as drawing very basic
graphic primitives (let's just call them cursors used to mark things).  If
this could be done in real time, as the actual display data is being output
it would/could make an important difference in the design.

I also have a requirement to have a 1 to 1 correspondence between input
image and the corresponding sampled data which will appear on screen as
these graphic primitives.  No big deal.  The display data actually goes to
another processor at the same time it hits goes to a display system.  If you
are rendering your graphics to a separate frame buffer you will have to add
one more frame of delay to the output image in order to guarantee
coincidence.  The memory required is not as much of an issue as the added
frame delay.  I truly can't get into it much farther than this.

Again, just a look-see for a better way to do it in real time.  I'm already
doing it in real time.  So, I know it is possible.  Just looking for a
better way, if it existed and was publicly available.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"





Article: 61790
Subject: Re: Counting ones
From: john.l.smith@titan.com (John)
Date: 10 Oct 2003 18:03:57 -0700
Links: << >>  << T >>  << A >>
john.l.smith@titan.com (John) wrote in message news:<5b9931fd.0310101049.45df7d20@posting.google.com>...

<lots of stuff, prolly too much, snipped>

Correction/amendment to (30,5) counter (6 CLBs):
   ___ 
0-| F |        
0-| A |-1-------+     
0-|_3_|-0-----+ |    
   ___        | |    ___
0-| F |       | +-1-| F |
0-| A |-1-----|---1-| A |-2-----------+
0-|_3_|-0-+ +-|---1-|_3_|-1---------+ |
   ___    | | |      ___            | |     ___
0-| F |   +-|-|---0-| F |           | +--2-|   |
0-| A |-1---+ +---0-| A |-1--+      +----1-| C |
0-|_3_|-0---------0-|_3_|-0--|-----------0-| Y |
                             |     ___     | A |
                             +--1-| F |    | d |-3----+
                            +---1-| A |--2-| d |-2---+|
                            | +-1-|_3_|--1-|   |-1--+||
                            | |        +-0-|___|-0-+|||
                            | |   '0'--+     |     ||||
                            | |              0     ||||
0---------------------------|-|--------------+     ||||
   ___                      | |                    ||||
0-| F |                     | |                    ||||
0-| A |-1-------+           | |                    ||||
0-|_3_|-0-----+ |           | |                    ||||
   ___        | |    ___    | |                    ||||
0-| F |       | +-1-| F |   | |                    ||||
0-| A |-1-----|---1-| A |-2-|-|-------+            ||||    ___
0-|_3_|-0-+ +-|---1-|_3_|-1-+ |       |            ||||   |   |
   ___    | | |      ___      |       |            |||+-3-|   |
0-| F |   +-|-|---0-| F |     |       |            ||+--2-| C |
0-| A |-1---+ +---0-| A |-1---|-----+ |            |+---1-| Y |-4
0-|_3_|-0---------0-|_3_|-0---|---+ | |            +----0-| A |-3
   ___                        |   | | |                   | d |-2
0-| F |                       |   | | |                   | d |-1
0-| A |-1-------+             |   | | |            +----3-|   |-0
0-|_3_|-0-----+ |             |   | | |            |+---2-|   |
   ___        | |    ___      |   | | |            ||+--1-|   |
0-| F |       | +-1-| F |     |   | | |     ___    |||+-0-|___|
0-| A |-1-----|---1-| A |-2---|-+ | | +--2-| C |-3-+|||     |
0-|_3_|-0-+ +-|---1-|_3_|-1---+ | | +----1-| Y |-2--+||     0
   ___    | | |      ___        | +------0-| A |-1---+|     |
0-| F |   +-|-|---0-| F |       +--------2-| d |-0----+     |
0-| A |-1---+ +---0-| A |-1--------------1-| d |            |
0-|_3_|-0---------0-|_3_|-0--------------0-|___|            |
                                             |              |
                                             0              |
0--------------------------------------------+              |
0-----------------------------------------------------------+

LUT Count:
    18       +        12       +   2    +   10      +       6  = 48
48 LUTs = 6 CLBs
Pipeline to taste...

Article: 61791
Subject: Re: Digesting runs of ones or zeros "well"
From: Ray Andraka <ray@andraka.com>
Date: Fri, 10 Oct 2003 21:19:50 -0400
Links: << >>  << T >>  << A >>
Tim,

Philip pointed out that my link was to your website, which I totally
missed.  Got a good laugh out of Philip's pointing it out though!


Ray Andraka wrote:

> Depends on the HDL.  VHDL certainly is.  There is a link on my links
> page of my website to an example of some VHDL that does exactly this,
> which IIRC is a function call.
>
> Tim wrote:
>
> > Ray Andraka wrote:
> > > I'd rather use a function or procedure within the HDL so that the
> > > boolean expression is in the code and is used directly to generate
> > > the init value.
> >
> > Not possible for the HDL which is not a complete
> > programming language ;-)
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 61792
Subject: Re: Xilinx XC2S50: Unable to configure through slave serial mode
From: wv9557@yahoo.com (Will)
Date: 10 Oct 2003 21:49:01 -0700
Links: << >>  << T >>  << A >>
RESET, INIT, PROG, DONE, TCK and TMS  should have pullup resistors. Well, at
least that's how I wired  my XC4000 board :)

do_not_reply_to_this_addr@yahoo.com (Sumit Gupta) wrote in message news:<ae680d56.0310100945.7e0c4801@posting.google.com>...
> Hi
> 
> I am trying to build a prototype Spartan-II board.
> 
> 1. I am using a XC2S50 TQ144 part with all the mode pins tied to
> VCCINT
> 2. I am using Xilinx webpack 4.2
> 3. The parallel cable is from insight electronics (Model IJC-2)
> 4. I am using a general purpose PCB and a QFP144 adapter from
> adapters.com to connect the FPGA to the PCB.
> 
> Now when I compile a simple test module and try to download the bit
> file through Xilinx iMPACT tool, it gives an error saying
> "Configuration failed: done pin did not go high".
> 
> What could be the cause and how can I debug it.
> 
> Thanks
> Sumit

Article: 61793
Subject: from jedec to schematic ??
From: "blisca" <blisca@tiscalinet.it>
Date: Sat, 11 Oct 2003 07:54:48 GMT
Links: << >>  << T >>  << A >>
hi, i need to convert a jed file  the abel-hdl,the file is for a lattice
1032e fpga,i tried with the utility jed2ahdl but it works only with small
logic arrays,can someone help me?



Article: 61794
Subject: Re: Graphics rendering revisited
From: "Vinh Pham" <a@a.a>
Date: Sat, 11 Oct 2003 18:22:49 GMT
Links: << >>  << T >>  << A >>
> It looked much like Gouraud shading.  Yes, that's why the thing cost
> several hundred K $.

Eeesh, shading with vectors.  If there's a will, and a wallet, there's a way
I suppose.

> flying through  the graphics data base one time only.  With raster, you
> can push a lot of that work into the logic such that it all gets sorted
out when

I guess it's like software defined radios where more and more of the analog
processing gets pushed into the digital world, for the flexibility.

> Larger, faster, cheaper memory made raster POSSIBLE!  When E&S
> designed this stuff, you just couldn't do read-modify-write cycles fast
> enough to make a usable raster system without making something like a
> 1024-bit wide memory word

So back then vector graphics was quite viable, but they underestimated how
quickly memory technology would advance.  One of those fabled "paradigm
shifts?"

Thanks for the insights Jon.  Looks like E&S is still chugging along, on the
raster bandwagon http://www.xilinx.com/company/success/evans.htm


--Vinh



Article: 61795
Subject: RAM in Xilinx Spartan II
From: Joe Lawrence <jdl1291ZZ@njit.edu>
Date: Sat, 11 Oct 2003 16:00:11 -0400
Links: << >>  << T >>  << A >>
I've got a beginner question concerning instantiating RAM inside a 
Spartan II XC2S50 using WebPack.  When attempting something like the 
following:

type ram_array is array(0 to memsize-1) of std_logic_vector(width-1 
downto 0);

the HDL synthesis reports using a 8-bit 1024-to-1 multiplexer.  Is the 
synthsizer trying to build the RAM out of flipflops?  Should I build my 
RAM out of ram32x1s type primitives instead?

-- Joe Lawrence
    take out the ZZ's for email


Article: 61796
Subject: FPGA Editor: Macro(Xilinx)
From: nickel <>
Date: Sat, 11 Oct 2003 15:16:29 -0700
Links: << >>  << T >>  << A >>
Hi, 
I would like to create a macro which uses the routing resources that need to be reserved in my design. 

Do I have to do that manually in FPGA editor or there is another automatic way? 

Thanks 

Nickel 

Article: 61797
Subject: video effects eval boards
From: "Brad Leyz" <email@yahoo.com>
Date: Sat, 11 Oct 2003 16:06:09 -0700
Links: << >>  << T >>  << A >>
Im looking for an fgpa solution that will assist in creating special video effects, preferrably hdtv, but otherwise standard video 
its possible standard video boards will do these functions, but Id like more access into registers, etc as eval kits seem to have. 

are there any popular video processing kits? thanks! 


Article: 61798
Subject: Re: FPGA Editor: Macro(Xilinx)
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Sat, 11 Oct 2003 23:09:59 GMT
Links: << >>  << T >>  << A >>
<nickel> wrote:

> I would like to create a macro which uses the routing resources that need
to be reserved in my design.
> Do I have to do that manually in FPGA editor or there is another automatic
way?

Can you provide more information?  Why is it that you want to include
routing in your macro?  An RPM is relatively easy to generate.  And you can
use various constraints to ensure that some of the routing is done per your
requirements.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



Article: 61799
Subject: Re: RAM in Xilinx Spartan II
From: "Vinh Pham" <a@a.a>
Date: Sun, 12 Oct 2003 06:36:10 GMT
Links: << >>  << T >>  << A >>
> type ram_array is array(0 to memsize-1) of std_logic_vector(width-1
> downto 0);

your type declaration looks okay, so it's probably a problem with the
"process" statement where you're using the signal of type "ram_array."
could you post that code up?

try searching for "inferring ram" in XST's user manual or on xilinx's web
site.  they should give you a template of how to word your VHDL such that
XST can properly infer your ram.


--Vinh





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