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Aart van Beuzekom <aart@westcontrol.dontspamme.com> wrote: : Hi, : Can anybody tell me a practical way (in VHDL) to count the number of : ones in a bit pattern? Counting should be done with combinatorial logic, : which means that a for-to loop cannot be used here (but being quite new : to FPGA and VHDL, I'm not even sure). The number of bits to be counted : is about 30, so a single look-up table is not the solution, using only a : Spartan II. : Any suggestions? Purpose is amongst others pattern matching, where I : count how many bits differ from the expected result. It has been discussed before. Try www.deja.com to search this group for old answers. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 61126
Hello,
I am trying to transform a functional behavioral description of
a controller module to real hardware in a Cyclone device(EP1C6C256C7).
The VHDL model of the controller is responsible for the control of the
write and read transactions to a data field (two-dimensional array)
which could
be for example a SRAM block.
The problem is that the write- and read- addresses and the
-next-addresses of the SRAM are calculated in smaller subarrays which
also have a two dimensional structure. However these sub-arrays are
too large to be exclusively synthesized
in logical ressources of the FPGA. So doubtless the memory bits in the
Cyclone device which are available in form of RAM, ROM, FIFOs have to
be used in order
to afford the synthesis.
The problem is how to split the behavioral description into
submodules to achieve the same functionality on the one hand and to
use the memory bits on the other hand. An essential question is where
and how
to place the control logic cleverly.
Maybe someone has some good or basic idea. I would be grateful for any
suggestion.
Some examplary VHDL code of the functional description of the module.
The signal row_write represents the current blocknumber of the
SRAM-block and is
gathered from a fifo which comprises blocknumbers from 0 to 255.
(tb_data_out)
The SRAM-block is described as if being whithin the file controller.
The question here is how to "detach" or to split this array and the
other sub-arrays.
----------------------------------------------------------------------
----------------------------------------------------------------------
generic( ROW_ADDR_BITS: integer:= 8;
ROWS : integer:= 256;
COL_ADDR_BITS: integer:= 3;
COLS : integer:= 8
);
type t_matri is array (0 to COLS*ROWS-1) of std_logic_vector(7 downto
0);
signal data : t_matri;
type t_addr is array (0 to ROWS-1) of std_logic_vector(ROW_ADDR_BITS-1
downto 0);
signal next_addr : t_addr;
type t_col is array (0 to ROWS-1) of std_logic_vector(COL_ADDR_BITS-1
downto 0);
signal last_col : t_col;
signal row_write : integer range 0 to 255;
begin
.
.
.
if (write='1' and writing='0' and lsfull='0') then
if tb_empty='0' then
row_write <= conv_integer(tb_data_out);
last_col(row_write) <= "000";
data(row_write*COLS + conv_integer(last_col(row_write)))
<=data_in;
// Here the argument of data consists of the sum of two values
which are from two different sub-arrays.
Question: How to deal this split in real hardware-blocks?
.
.
.
elsif (write='1' and writing='1' and lsfull='0') then
.
.
.
next_addr(row_write) <= tb_data_out;
end if;
---------------------------------------------------------------------
---------------------------------------------------------------------
Thank you very much for your help.
Best regards
Andrés Vázquez
G & D - Digital System Development
email: andres.vazquez@gmx.de
Article: 61127Jan Panteltje wrote: > > On a sunny day (26 Sep 2003 14:00:52 -0700) it happened ramntn@yahoo.com (ram) > wrote in <61c2cc9d.0309261300.38798162@posting.google.com>: > > >the same with me, my inbox is pounded with bulk mail and i exceed storage in 20 min. > >i lost my id too > >Is there any soln to get away from this > >ram > > > I found some sort of solution here: > www.sneakemail.com > The way it works is that they create a random email address at their domain, > and you use that. > Then they forward it to your real email. > The sender does not get to see the real email address. > Once the spammers get hold of it, you simply generate a new random address. > > I have it now on my website, for feedback, such a random address (for > feedback for open source software), and it seems to work (just testing). > Once they spam it, I will just generate a new one, and change the link. > Also I followed the advice of some person here, (thank you for the link, mm > they should have referral fees) and bought my own domain from > www.mydoname.com.. > That site actually is using domainsbyproxy.com. > www.panteltje.com is up now (redirect). > Did cost me 25 $ for a year. > We will see how it goes from here, still need to print new cards (yahoo email > was on it). > Yahoo is still full within the hour... > Anyway its cool to have your own domain :-) > JP Let me tell you one downside of having your own domain. Unless you only use a few addresses, the spammers will make up addresses that don't exist. If you receive every possible address at that domain, you will start getting email to all sorts of silly, made up addresses. To prevent this you will need to either track the made up addresses and toss them at the server, or you will need to toss everything by default and just forward the addresses you are using. Also don't plan to keep using the one address you are forwarding to from domainsbyproxy.com. BTW, what is the point of printing cards at all if you have to change your email address from time to time? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61128
Jake Janovetz wrote: > > It's interesting you say this. I have my own domain name which I use > for private email but I would never post the email address on Usenet > (even with a NOSPAM thing in it). You can use filter software to put > things into different folders. For example, when registering on > various corporate web pages, I often use newly generated emails: > > robert-analogdevices@mydomain.com > robert-xilinx@mydomain.com > > When mail comes from those sites, it is placed into my folders "Analog > Devices" or "Xilinx". If I start getting spam on one, I know who sold > the database! And, it does a much better job at keeping my real email > address clean (which has been clean for almost four years now). > > For usenet, you can see I signed up using a different email address on > Yahoo. I do this as well. But I have found that vendors (including FPGA and CAD vendors) are pretty good at playing dumb about using your email address for spam. Every time I have given an email address to either Xilinx or Altera, regardless of whether I ask to be included or excluded from marketing materials (or even if the address is just given to support), I have ended up getting one form of spam or another to that address. I have even had email addresses twisted and received CAD spam to them. There is no rock.collins@arius.com, but I get email from a CAD rep and no matter how much I complain to the rep firm or to their vendors, I keep getting it. When it comes to email spam, there is no honor among theives. Even when you catch otherwise honest vendors at it, they don't stop. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61129
Hal Murray wrote: > > > I've had the same email address for almost eight years now, and > > I've never tried very hard to hide it, meaning that when I post to > > public forums like this I use my real email addr. I'm now > > receiving on the order of 300-400 (brutally repetitive) spam > > emails per 24hr period, > > It's well known that spammers harvest usenet. If you post > without munging you will get spam. That may be one of those overratted known facts. I remember someone doing a study where they set up several email addresses and used them in several different ways to study the rate of spam. The newsgroup posted emails got relatively little spam. I believe the rate of spam did not go up dramatically until they started using web pages that required email addresses like the greeting cards, etc. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61130
Aart van Beuzekom schrieb: > Hi, > > Can anybody tell me a practical way (in VHDL) to count the number of > ones in a bit pattern? Counting should be done with combinatorial logic, > which means that a for-to loop cannot be used here (but being quite new > to FPGA and VHDL, I'm not even sure). The number of bits to be counted > is about 30, so a single look-up table is not the solution, using only a > Spartan II. > Its not VHDL, but: if you have bits numberd x0, x1, x2, x3 ... x30 than you can simply add them: Y = x0 + x1 + x2 + ... x30 for counting ONE's greetings, Bertram -- Bertram Geiger, Graz - AUSTRIA Private Mail: remove the letters "b a d" from my reply addressArticle: 61131
Uwe Bonnes wrote: > Aart van Beuzekom <aart@westcontrol.dontspamme.com> wrote: > : Hi, > > : Can anybody tell me a practical way (in VHDL) to count the number of > : ones in a bit pattern? Counting should be done with combinatorial logic, > : which means that a for-to loop cannot be used here (but being quite new > : to FPGA and VHDL, I'm not even sure). The number of bits to be counted > : is about 30, so a single look-up table is not the solution, using only a > : Spartan II. > > : Any suggestions? Purpose is amongst others pattern matching, where I > : count how many bits differ from the expected result. > > It has been discussed before. Try www.deja.com to search this group for old > answers. > > Bye Hi Uwe, Thanks for four response. Fortunately, I checked this newsgroup's archive before posting. The problem is that it isn't exactly pattern matching I want, but counting the number of errors (at the other end of a poor communication link) in a bitstream, compared to an expected pattern. Something that for example can be used to find a kind of preamble signal. Any more suggestions? AartArticle: 61132
Thanks for the info, everybody. I have a spam filter that steers about half of the normal junk into my delete folder. I've become inured to this stuff. It's the MS emails with virus attachments that force me to click on a Norton warning box for each one that has put me over the edge. It takes me at least 15 minutes each morning now to manually wade through it all. I'm going to abandon this address today. It's beyond salvaging. RJS "Robert Sefton" <rsefton@nextstate.com> wrote in message news:YVsdb.12231$T46.6679@twister.socal.rr.com... > I've had the same email address for almost eight years now, and > I've never tried very hard to hide it, meaning that when I post to > public forums like this I use my real email addr. I'm now > receiving on the order of 300-400 (brutally repetitive) spam > emails per 24hr period, and in the last couple of weeks I've been > getting about 100-200 bogus > Microsoft-security-patch-with-virus-attachment emails per day on > top of that (Norton Antivirus pops up a warning box for each one > it detects and I have to manually step through them). I've been > patiently waiting for the Microsoft patch garbage to die off, but > it hasn't. > > I'm a consultant and have my own domain name (nextstate.com), but > I've finally decided to abandon it and start using a roadrunner > email address. I won't bore you with my rage and frustration, but > I'm curious how other people are avoiding, filtering out, or > fighting back against this crap. Shouldn't the ISPs be attacking > this problem with a little bit more enthusiasm? > > Very pissed off in San Diego, > > RJS > >Article: 61133
Duane Clark <junkmail@junkmail.com> wrote in message news:<bl7qoa0214j@enews1.newsguy.com>... > Pablo Bleyer Kocik wrote: > > > > Actually, in my company the only missing EDA link for Windows - Linux > > shift is Xilinx ISE. ;O( I don't care very much for a release date > > --if there really is a Linux ISE coming that would be a relief and > > will let us plan things accordingly. > > The Linux version of ISE is already out (except for Impact). It is > Webpack that has not yet been released in a Linux version. Since Webpack > is basically just ISE limited to certain devices, I would not expect a > long wait. > > As a wild guess, maybe Xilinx wants to use their (probably somewhat more > savy) ISE customers to find bugs, before releasing Webpack. Oh, yes. Sorry, I was talking about ISE Webpack. Cheers.Article: 61134
Robert Sefton wrote: > > I've had the same email address for almost eight years now, and > I've never tried very hard to hide it, meaning that when I post to > public forums like this I use my real email addr. I'm now > receiving on the order of 300-400 (brutally repetitive) spam > emails per 24hr period, and in the last couple of weeks I've been > getting about 100-200 bogus > Microsoft-security-patch-with-virus-attachment emails per day on > top of that (Norton Antivirus pops up a warning box for each one > it detects and I have to manually step through them). I've been > patiently waiting for the Microsoft patch garbage to die off, but > it hasn't. > > I'm a consultant and have my own domain name (nextstate.com), but > I've finally decided to abandon it and start using a roadrunner > email address. I won't bore you with my rage and frustration, but > I'm curious how other people are avoiding, filtering out, or > fighting back against this crap. Shouldn't the ISPs be attacking > this problem with a little bit more enthusiasm? If you have your own domain name, why can't you pick different addresses at that domain? The only problem I find with having my own domain is that I like to keep the addresses open but I get spam sent to a bunch of made up addresses. So I have to discard those specific addresses. Otherwise I don't get much spam that I can't easily filter. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61135
"Bertram Geiger" <badnews_geiger@aon.at> wrote in message news:3F784164.2000108@aon.at... > Aart van Beuzekom schrieb: > > Hi, > > > > Can anybody tell me a practical way (in VHDL) to count the number of > > ones in a bit pattern? Counting should be done with combinatorial logic, > > which means that a for-to loop cannot be used here (but being quite new > > to FPGA and VHDL, I'm not even sure). The number of bits to be counted > > is about 30, so a single look-up table is not the solution, using only a > > Spartan II. > > > Its not VHDL, but: > if you have bits numberd x0, x1, x2, x3 ... x30 than you can simply add > them: Y = x0 + x1 + x2 + ... x30 for counting ONE's I don't remember it being discussed so recently. It might be too far back to find, or maybe another newsgroup. comp.arch might be a good choice. Anyway, adding with carry save adders is the best combinatorial algorithm I know of. I don't know how well it works in an FPGA, though. -- glenArticle: 61136
Actually setup and hold times are to prevent metastabiltity. In this case it is most likely that the OP does not care if the output reflects the changed input or not. So either a 1 or a 0 would do fine. But metastability has the potential of spreading through a circuit and causing erroneous operation. The problem here is that the OP does not understand the issue of metastability. It is not clear to me if he had really fixed anything by changing his simulation or if he is just covering up a potential problem in his design. To the best of my knowledge, there is no good simulation of metastability and it can be hard to simulate a circuit that "fixes" metastability since it only sees that the setup and hold were violated and does not understand that the "fix" will solve the problem with a very low failure rate. So the OP may be doing the right thing to get the simulation to work as long as he understands the metastability issue. Simon Peacock wrote: > > I stand corrected.. but as with metastability.. you always get a 50/50 > chance of being right :-) > but I believe setup or hold both give the same problem. > > Simon > > "Vinh Pham" <a@a.a> wrote in message > news:SpScb.15906$5z.8325@twister.socal.rr.com... > > > congratulations.. I think you have simulated metastability :-) > > > dat doesn't need to be in your sensitivity list as dat changing won't > > affect > > > the simulation result unless clk changes. > > > > > > What you are seeing is a setup time violation. > > > > Simon, I think if you carefully look at the timing diagram, it's clearly a > > hold-time violation. And what an awful flip-flop, to have such a long > > meta-stability resolution time. Perhaps an upgrade to Aldec 6.1 will > > provide better performing flip-flop models. > > > > Just joking, of course :_) > > > > > > Regards, > > Vinh > > > > > > -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61137
Hi, I m new in FPGA. I m sure that someone has for me an answer to my issue. I work with XC2S300 of the Spartan Familly. when I implement I get the following warning message: Warning: NgdBuild: 477 - clock net 'clk_bufgp has non clock connections. These problematic connections include pin i1 on block u1_io with type LUT2 .. I try to do gating clock. What I can do?Article: 61138
Aart van Beuzekom <aart@westcontrol.dontspamme.com> wrote: : Uwe Bonnes wrote: :> Aart van Beuzekom <aart@westcontrol.dontspamme.com> wrote: ... :> It has been discussed before. Try www.deja.com to search this group for old :> answers. :> :> Bye : Hi Uwe, : Thanks for four response. Fortunately, I checked this newsgroup's : archive before posting. The problem is that it isn't exactly pattern : matching I want, but counting the number of errors (at the other end of : a poor communication link) in a bitstream, compared to an expected : pattern. Something that for example can be used to find a kind of The second hit on deja in a search for "fpga counting ones" gives: >Re: Counting the number of ones present ... > comp.lang.verilog - 8 Jul 2002 by John_H - View Thread (10 articles) http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&oe=UTF-8&threadm=3D29BF6F.C2CA3906%40mail.com&rnum=2&prev=/groups%3Fq%3Dfpga%2Bcounting%2Bones%26hl%3Den%26lr%3D%26ie%3DUTF-8%26oe%3DUTF-8%26start%3D0%26sa%3DN The 6th hit is Re: Count 1's algorithm... ... To count 16 ones you would need 5 CLBs and have one ... you have to do it and how many bits you are counting. ... with a fanin and fanout of 2. The FPGA LUTs generally ... comp.arch.fpga - 4 Feb 2000 by Dragon - View Thread (11 articles) Hope this helps -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 61139
I made the mistake of posting *one* article to this group by using my real
e-mail address. Now the Swen (news backwards) spam count is 1157.
Well, I must bear the consequences of my own stupidity.
For those building up filters, this is what I have used to build mine:
- The SUBJECT header is all capitals, as it usually is "Subject"
- The To header never contains your address (good safety rule)
- The size of the attached virus is 106,496 Bytes (also good safety rule)
If you want to be super-safe with false positives, you might even want
to take md5 sum from the attachment by using e.g. [1]
- The attachemt is executable, so the suffix is
.(asd|bat|chm|cmd|com|dll|exe|hlp|hta|js|jse|lnk|ocx|pif|scr|shb|shm|
shs|vb|vbe|vbs|vbx|vxd|wsf) (There might be some more)
And the obvious ones to be used in conjunction with the ones above:
- The body contains:
"September 2003, Cumulative Patch" or
"<BR><BR><BR>Undeliver(able|ed) (message|mail|to)"
[1] http://elonen.iki.fi/code/misc-notes/mpartinfo2hdr/
Hope these helps,
T.Rissa
tpr at doc ic ac uk
Neeraj Varma <> wrote:
> I have the same problem, and I use the "Message Rules" in Outlook Express,
> it has at-least brought down the spam by 50%...as and when the mail arrives
> look for the keywords in the subject or in the email address or in the from
> line, and go on adding them. The action I've set for emails with these
> specific keywords is to delete them from the server so that they are not
> downloaded at all ( i use a pop3 mailbox). but it is a menace...and scares
> me from posting on usenet...
Article: 61140
Hi Aart
There is an excellent example of a combinational ones counter in the course
notes on our Comprehensive VHDL course ;-) Check out my employers website
for more details...
Our example does use a for loop - I'm not sure why you feel a for-loop
cannot be used for combinational logic, unless you are putting wait
statements inside the for loop, and in that case it probably won't
synthesise (unless you have a behavoral compiler). To work out what a loop
will do, simply replicate the contents of the loop once for each iteration
of the loop, replacing the loop parameter with a constant. eg
process(b , c)
begin
for i in 0 to 3 loop
a(i) = b(i) and c(3-i);
end loop
end process;
is equivalent to
process(b , c)
begin
a(0) = b(0) and c(3);
a(1) = b(1) and c(2);
a(2) = b(2) and c(1);
a(3) = b(3) and c(0);
end process;
Try a for-loop looping the entire 'range of your error vector. Inside the
for loop, sum all the bits. So long as you get the types right and don't put
any timing in the loop, it will synthesise to combinational logic.
HTH
Ian Poole
--
Ian Poole, Consultant and Trainer
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
"Aart van Beuzekom" <aart@westcontrol.dontspamme.com> wrote in message
news:bl8u9v$1v5$1@news.netpower.no...
> Hi,
>
> Can anybody tell me a practical way (in VHDL) to count the number of
> ones in a bit pattern? Counting should be done with combinatorial logic,
> which means that a for-to loop cannot be used here (but being quite new
> to FPGA and VHDL, I'm not even sure). The number of bits to be counted
> is about 30, so a single look-up table is not the solution, using only a
> Spartan II.
>
> Any suggestions? Purpose is amongst others pattern matching, where I
> count how many bits differ from the expected result.
>
> Thanks,
>
> Aart
>
Article: 61141jose <jyab2@yahoo.com> wrote: : Hi, : I m new in FPGA. : I m sure that someone has for me an answer to my issue. I work with : XC2S300 of the Spartan Familly. when I implement I get the following : warning message: : Warning: NgdBuild: 477 - clock net 'clk_bufgp has non clock : connections. These : problematic connections include pin i1 on block u1_io with type LUT2 : .. : I try to do gating clock. First rule: Don't use gated clocks, use the CE input instead. : What I can do? Second it looks like you bring in a signal through a clock input, but don't use it as clock, e.g. you use the input clock as input to a logic gate and you feed the output of that gate to the clock network. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 61142
I am using Xilinx ISE6.1.01i I would like to use a falling clock on a core (binary counter), This core does not have a falling edge "selection" such as the BRAM... I tried the use the FALLING constrain with no success.(no effect) My question is : is it possible to use the FALLING constrain with cores? Thanks Patrice FavreauArticle: 61143
Hello I looked much at the Xilinx WebPage, but didn't found the right answer, so I ask you to help me. I'm using a Virtex2 device and want to configure it over a small microcontroller and a CPLD in Slave Parallel mode. I have found many information about file formats (MCS,TEK,EXO,..). But I want a file which contains only the pure bitstream which I can store in my flash and send bytewise to the FPGA during configuration. Which tool must I use to get from the *.bit file such a file? Thanks, Reiner Abl _____________________________________________________________________ Reiner Abl IQ-Mobil GmbH 82515 Wolfratshausen www.iqmobil.de GermanyArticle: 61144
The Linux version of WebPACK is not scheduled, but as I posted in June, it will probably be in our 7.1 release (Sept '04). We use Bristol to get our Windows GUIs working on Solaris and Linux and yes, we do pay a royalty per seat. For now, Linux users will have to use Wine or purchase ISE BaseX. Steve Pablo Bleyer Kocik wrote: >Duane Clark <junkmail@junkmail.com> wrote in message news:<bl7qoa0214j@enews1.newsguy.com>... > > >>Pablo Bleyer Kocik wrote: >> >> >>> Actually, in my company the only missing EDA link for Windows - Linux >>>shift is Xilinx ISE. ;O( I don't care very much for a release date >>>--if there really is a Linux ISE coming that would be a relief and >>>will let us plan things accordingly. >>> >>> >>The Linux version of ISE is already out (except for Impact). It is >>Webpack that has not yet been released in a Linux version. Since Webpack >>is basically just ISE limited to certain devices, I would not expect a >>long wait. >> >>As a wild guess, maybe Xilinx wants to use their (probably somewhat more >>savy) ISE customers to find bugs, before releasing Webpack. >> >> > > Oh, yes. Sorry, I was talking about ISE Webpack. > > Cheers. > >Article: 61145
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:bl9cg6$7uq$1@news.tu-darmstadt.de... > Aart van Beuzekom <aart@westcontrol.dontspamme.com> wrote: > : Hi, > > : Can anybody tell me a practical way (in VHDL) to count the number of > : ones in a bit pattern? <snip> In either the Xilinx or Altera architecture, it's probably most efficient to pre-add in groups of 4 bits then add thse results in an adder tree. For 32 bits (for instance) you can get 8 values with counts of 0-4 with simple LUTs. The next stages give 4 values of 0-8 by adding the previous values in pairs, the next level is 2 values of 0-16 and the last stage is a single adder with a result from 0 to 32. This can be extended to whatever quantity of bit errors you want to count per-cycle. If you just try to add all 32 bits in one line - which is entirely valid - some synthesizers will give you poor results. The structured coding tesnds to give structured results. If you need higher speed, you can pipeline the adder tree to get extreme clock rates. - John_HArticle: 61146
On 28 Sep 2003 11:21:57 -0700, prashantj@usa.net (Prashant) wrote: >Thanks Muzzafer, > >So how does this work for pins on an FPGA ? I have specified some of >the FPGA pins as bidirectional pins. I'm using the bidirectional pins >to read from a register in the code or to write from a different >register in the code. >I dont understand how to specify the direction signal for the pins. I >can do this at the signal/register level within the logic. But how are >the bidirectional IO pins controlled ? Suppose the following is your fpga top level: module mydesign(rd_wrb, address, data); input rd_wrb; input [7:0] address; inout [7:0] data; and this is your register block reg [7:0] registers [7:0]; this is how you write to the memory always @(rd_wrb or address or data) if (!rd_wrb) registers[address] = data; and this is how you read from the registers including direction control wire [7:0] data = rd_wrb ? registers[address] : 8'hZ; this last line shows you control the direction signal for the pins. You take the input rd_wrb and connect it to the active high OE port of the data pins. Hope this help. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 61147
Aart van Beuzekom wrote: > Hi, > > Can anybody tell me a practical way (in VHDL) to count the number of > ones in a bit pattern? Related thread: http://groups.google.com/groups?q=pattern_recognizer -- Mike TreselerArticle: 61149
Robert Sefton wrote: > I'm curious how other people are avoiding, filtering out, or > fighting back against this crap. The latest version of netscape (and mozilla) has a most excellent junk mail router. It does a good job right out of the box and you can train it further by example rather than by keyword. -- Mike Treseler -- mike.treseler@flukenetworks.com
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