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Messages from 62300

Article: 62300
Subject: Re: Thank to you and Google
From: "Christos" <chris_saturnNOSPAM@hotmail.com>
Date: Fri, 24 Oct 2003 18:55:09 +0200
Links: << >>  << T >>  << A >>
Hi,
Did you try to press the button "headers"?
It has worked for all the people complaining at my office.!!
I am not sure why the OE does not download all messages..
But I guess it has to do something with max headers and waste of space
settings.

Anyway, hope it helps..


"MM" <mbmsv@yahoo.com> wrote in message
news:bnba40$vd0oq$1@ID-204311.news.uni-berlin.de...
> "Valentin Tihomirov" <valentin@abelectron.com> wrote in message
> news:3f991c5a$1_1@news.estpak.ee...
> > Stupid OE shows only your last message. Which newsreader do you use?
>
> Newsreader has nothing to do with this, it's the news server that you are
> connected to. You might try talking to your IP about the issue or use one
of
> the free servers. A very good one is news.individual.net (someone
> recommended it to me earlier on this group). The only problem with it is
> that you have to register and it seems that they actually have a live
person
> who does the registrations, so it may take 1-2 days. Their site is
> http://www.individual.net/
>
> /Mikhail
>
>



Article: 62301
Subject: Re: Are clock and divided clock synchronous?
From: Peter Molesworth <noemail@anonymous.net>
Date: Fri, 24 Oct 2003 21:04:02 -0000
Links: << >>  << T >>  << A >>
Matt,

In the two examples you provide below you are generating divided clocks on 
dclk and then using this to clock registers in the design. This will mean 
that there will be skew introduced between registers on the main clock 
domain and registers on the dclk domain. This skew may become quite large 
and cause problems. Also the synthesis tool will not be able to properly 
optimize any logic that crosses between the two clock domains.

In the example I gave, all registers are clocked using the main global 
clock. I achive the lower "clock" rate at the registers by using the 
EnableDiv3 signal as a synchronous enable to the registers. This means 
that there is not any excessive skew between register as they will all be 
on the same low-skew clock net. The synthesis tool will be happy about 
optimizing between registers passing between the fast and slow parts of 
the design and to ensure the synthesis/place&route tools only optimize as 
much as is required you can specify register-register paths in the low 
speed parts of the design as multi cycle paths.

Cheers,

Pete.

On Fri, 24 Oct 2003 09:07:00 +0100, Matt North 
<m.r.w.north@NO_SPAMrl.ac.uk> wrote:

> I have always used a counter clocked on the global clk, and then used 
> one of
> the signals
> that make up the counter's vector as my divided clk signal.
>
> e.g.
> signal cnt: std_logic_vector(7 downto 0);
>
> process(...)
> ....
>     if rising_edge(clk) then
>             cnt<=cnt+1;
> ....
> end;
> --divided clk
> dclk<=cnt(4);
>
> How does the above code differ in terms of reliability or good code 
> practice
> too;
>
> signal n: integer;
>
> process(...)
> ....
>     if rising_edge(clk) then
>         if rst='0' or n=10 then
>             n<=0;
>         else
>             n<=n+1;
>         end if;
>     end if;
> end process;
>
> d_clk<='0' when n<=5 else '1';
> ....
>
> Both produce divided clocks.
>
> Matt
>
> "Peter Molesworth" <noemail@anonymous.net> wrote in message
> news:oprxidmzi40ve4v7@news.tiscali.co.uk...
>> > Divided clock seems synchronous to original clk in terms it is stable 
>> on
>> > clk
>> > edage. On the other hand, synchronous signals should switch
> simultaneusly
>> > while divided signal is calculated on the clk egdage; hence, it 
>> switches
>> > after Thold and the condition is not met. I understand principles of
>> > asynchronous communication. Should I treat divided clock as an
>> > asynchronous
>> > clock domain? Any references are appretiated.
>> >
>> >
>>
>> Valentin,
>>
>> For all but the simplest of designs divided clocks should be treated as
>> asynchronous and avoided if possible. There are several reasons for 
>> this.
>>
>> 1) Your divided clock will have a small delay relative to the real 
>> clock.
>> If you use this to clock a register which takes in a signal clocked from
>> the original clock domain it may be possible for the setup/hold to be
>> violated or data to be taken when it shouldn't have been (i.e a clock
>> early). I think you were implying this above.
>>
>> 2) If you have logic which works accross the two clock domains e.g. data
>> clocked from main clock domain goes through logic and is registed on
>> divided clock domain or vice-versa then the synthesis tool may have a 
>> hard
>> time performing optimization on logic in that part of the design.
>>
>> 3) Unless you have spare high-speed global resources in your design and
>> the target technology allows the connection of a register output onto
>> these nets (most modern fpga's are okay with this!) then the divided 
>> clock
>> may get routed on the normal routing nets. If you have lots of registers
>> driven from the divided clock the fanout may start to become significant
>> and hence the skew between the clock domains will get larger. If the 
>> skew
>> starts to become significant it then becomes more difficult to ensure 
>> that
>> the design will work over all temperature/voltage conditions as this 
>> will
>> introduce skew between registers on the divided domain aswell as between
>> the divided and main clock domain. To overcome this the
>> synthesis/place&route tools may try to insert buffers to split down the
>> net. This may in turn introduce more skew between some registers on your
>> divided net.
>>
>> So to overcome these issues I would suggest trying alternative method of
>> coding to reduce this problem to a minimum. The way I do things if I 
>> want
>> a slower clock is as follows:
>>
>> For example, say I want a clock that is 1/3 the system clock, I would
>> create a 2-bit counter that counts 0 to 2 and rolls over. When the 
>> counter
>> equals 2 a signal EnableDiv3 is asserted to '1' (and is '0' for all 
>> other
>> values). I then use this signal as a synchronous enable to the 
>> registers I
>> want to run a 1/3 speed but still clock the registers off the system
>> clock.
>>
>> EnableGen : process (nReset, Clock)
>>              begin
>>                 if (nReset = '0') then
>>                    EnableCount <= 0;
>>                    EnableDiv3 <= '0';
>>                 elsif rising_edge (Clock) then
>>                    if (EnableCount = 2) then
>>                       EnableCount <= 0;
>>                       EnableDiv3 <= '1';
>>                    else
>>                       EnableCount <= EnableCount + 1;
>>                       EnableDiv3 <= '0';
>>                    end if;
>>                 end if;
>>              end process;
>>
>> SomeRegister : process (nReset, Clock)
>>                 begin
>>                    if (nReset = '0') then
>>                       MySignalReg <= '0';
>>                    elsif rising_edge (Clock) then
>>                       if (EnableDiv3) then
>>                          MySignalReg <= MyDataValue;
>>                       else
>>                          MySignalReg <= MySignalReg;
>>                       end if;
>>                    end if;
>>                 end process;
>>
>> This solves 1) and 2) above. For item 3) there is still the problem of
>> high fan-out on the enable signal. This will be solved by the
>> synthesis/place&route tool by inserting buffers. However, in this case 
>> the
>> registers are still clocked by the system clock so any skew on enable 
>> will
>> be okay so long as it dosen't violate setup/hold at the destination
>> registers.
>>
>> I hope this is what you were asking for. If you need anything else 
>> please
>> let me know.
>>
>> Cheers,
>>
>> Pete.
>
>

Article: 62302
Subject: Re: Are clock and divided clock synchronous?
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 24 Oct 2003 16:37:41 -0700
Links: << >>  << T >>  << A >>
I agree with the other Peter, but I might add:
If you use the Digital Clock Manager in Virtex-II or Spartan3,  you have
four outputs with practically zero skew (<100ps?)between them, and they
can be fractions or multiples of the incoming clock. When you distribute
these signals on global clocks, there will not be any hold-time caused
problems. The skew is definitely less than any clock-to-Q.
The advantage of a fractional clock is of course lower power consumption.
The problem would be clock-skew and potentially unreliable operation,
unless you use the DCM for division or multiplication (or both simultaneously!).
Peter Alfke, Xilinx Applications
=====================


Article: 62303
Subject: Re: Picoblaze development tool
From: "Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com>
Date: Sat, 25 Oct 2003 11:30:11 +0200
Links: << >>  << T >>  << A >>
Henk van Kampen wrote:
> Recently I have updated my Picoblaze (tm Xilinx) development tool
> pBlazIDE and added some documentation. Additionally I have published
> some example code and demonstration files. Please feel free to check
> this out. Its all freeware. Check under 'Tools'.
> 
> Regards,
> Henk van Kampen
> www.mediatronix.com

Dear Henk,

Could you explain what we can do with your JTAG option ? Can we do 
on-chip PicoBlaze debugging or ROM download ?

If yes, this is very interesting.

Actually, we are working on reconfigurable high speed automat machine. 
We will try to use picoblaze as base. One automat will have about 10 to 
100 picoblaze. The goal is to keep the speed and true multi-processing 
achitechture of sequencial function.

Laurent
www.amontec.com


Article: 62304
Subject: Searching for 802.11a/g implementations
From: dbeberman@earthlink.net (David)
Date: 25 Oct 2003 07:49:03 -0700
Links: << >>  << T >>  << A >>
Hi, 

I've been reading the archives of this list, and the FAQ.  I haven't
seen much about 802.11a and g phy implementations.  Does anybody know
where I might find 802.11a/g VHDL, Verilog or other implementations.
This does not need to be open source, however, I am looking for
something that I will be able to add my own modifications to.

Thanks,

David

Article: 62305
Subject: Re: Running Quartus II on ReadHat Linux 9.0
From: H. Peter Anvin <hpa@zytor.com>
Date: 25 Oct 2003 14:38:36 -0700
Links: << >>  << T >>  << A >>
Followup to:  <87smljd8i6.fsf@zener.home.gustad.com>
By author:    Petter Gustad <newsmailcomp6@gustad.com>
In newsgroup: comp.arch.fpga
>
> uselinux2000@yahoo.com (linux user) writes:
> 
> 
> >    Altera has very talented engineers, and there is no doubt in my
> > mind that very soon a nice install, possibly similar to the one of
> > Open Office (GUI based) will be available for Linux.
> 
> I've been a Linux user since 1993 and I'm very happy to see that Linux
> support from the major FPGA vendors is improving.
> 
> However, I would like Altera and Xilinx to spend their efforts on other
> things than a GUI based install program. I recall all the problems I
> have had over the years with the Xilinx GUI based install program
> under Solaris. It would sit there for days flashing cute ads without
> installing anything :-( A simple tar would done the job. Of course you
> most likely need a way of specifying which devices and parts to
> install, but that's about it. Sometimes I install Linux software on
> file servers which don't even have X11.
> 

Indeed.  Most Linux users would vastly prefer one or more RPMs which
"just work" once installed.  Interactive install is not a good thing.

	-hpa
-- 
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
If you send me mail in HTML format I will assume it's spam.
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64

Article: 62306
Subject: Re: Running Quartus II on ReadHat Linux 9.0
From: "Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl>
Date: Sat, 25 Oct 2003 23:07:50 GMT
Links: << >>  << T >>  << A >>
Hi Andre,

> 4) Suse 9.0: did anyone try?

I did try Suse 8.1, 8.2 and 9.0, and in allcases it failed at an unexpected
point. GUI came up nicely and stuff, and for MAX devices you'll get some
wonderful results, but for SRAM-based devices, something is going wrong.
Someone within development is looking at this though, and I have his phone
number...

Best regards,



Ben



Article: 62307
Subject: Re: Running Quartus II on ReadHat Linux 9.0
From: "Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl>
Date: Sat, 25 Oct 2003 23:29:45 GMT
Links: << >>  << T >>  << A >>

"Jan De Ceuster" <jandc@elis.ugent.be> wrote in message
news:bn59aj$tqj$1@gaudi2.UGent.be...
> >>And now it works... Maybe Altera should write a cleaner script that
> >>first checks if it's a Red Hat distribution...
> >
> >
> > Yes. But it would have been even better if they checked for the
> > *features* they need rather than checking the distribution.
>
> Indeed and I even had to manualy add some directories to the librarypath
to get
> everything up and running. It just doesn't look profecional to me. 2 days
work
> (at most) for a decent engineer and the scripts would have been perfect.
I'm a
> bit dissapointed...

Never needed to do this - and I'm running Gentoo Linux, an utterly
unsupported (but rather good) distribution. It just runs out of the box.
I've been working on Altera's system identification scripts in the past.

Trouble with all this distribution stuff is that there is no defined
standard that tells you how to determine which distribution a system is
running on. Even doing an "ls -l /etc | grep *release" will not give you the
full info, because every distro puts different things into these files, plus
they may have, for example redhat-release and lsb-release, containing
different data structures. Determining the kernel version and/or glibc
version is useless (Suse 9.0 reports 2.4.21-99 or so), glibc versions may or
may not have NTPL support using the same version number and more of that
stuff. Really messy.

I think that if Altera could find a waterproof way of figuring out which
distribution and version of it it's running on, plus its capability model,
it would be worth a patent, even if they didn't apply for it ;-)

If you have any tips (including just mentioning which directories you still
had to add), you're welcome to post them.

Best regards,


Ben



Article: 62308
Subject: Modeling hardware in Matlab/Simulink (delay, etc.)?
From: moe <moh@speakhard.net>
Date: Sat, 25 Oct 2003 22:39:24 -0400
Links: << >>  << T >>  << A >>
Hello all,

I need some guidedance on how to go about modeling an algorithm before I
design it into an FPGA.

I'd like to use Matlab to run the simulation.  Instead of just sanity
check, I also need to optimize the size (# of bits) of several
parameters.  It'll be a balance act between # of bits (hence, FPGA
performance) and precision of the algorithm output.  FPGA needs to run
150+Mhz, and the parameter sizes may end up being somewhat of an odd
size (48?  56?), perhaps up to 64.  The algorithm is made up of mostly
adders and delay elements.

So far, it looks like I need to use Simulink with Fixed-point blockset.
Is that sufficient, or is there a better way to do this?   I've been
reading previous posts in different places, and it sounds like modeling
delay isn't as easy as it should be.  Is that true?  I was able to use
'Triggered subsystem' to model a FF without much problem, but then it
was for a very simple single bit data path.

I'd appreciate any input, feedback, insight, suggestion.  I'm sending
this to VHDL/Verilog newsgroups for a wider audience.

Please replace 'hard' with 'easy' in my email addr, if replying via
email.

-moe



Article: 62309
Subject: Re: Are clock and divided clock synchronous?
From: Jeff Cunningham <jcc@sover.net>
Date: Sun, 26 Oct 2003 04:15:59 GMT
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> If you use the Digital Clock Manager in Virtex-II or Spartan3,  you have
> four outputs with practically zero skew (<100ps?)between them, and they
> can be fractions or multiples of the incoming clock. When you distribute
> these signals on global clocks, there will not be any hold-time caused
> problems. The skew is definitely less than any clock-to-Q.

Just to make sure I understand, this is NOT the case with the Spartan-2 
DLL is it, i.e. the skew is not so well behaved in the DLL.

Jeff


Article: 62310
Subject: Hex display with Quartus simulation
From: Pratip Mukherjee <pratipm@hotmail.com>
Date: Sun, 26 Oct 2003 04:35:55 GMT
Links: << >>  << T >>  << A >>
Hi,
If I have a port defined as std_logic_vector(n downto 0), Quartus simulator 
is showing the individual bits in binary values. How do I make it display 
all the bits together in a hex mode.
Thanks in advance.

Pratip Mukherjee

Article: 62311
Subject: Re: Searching for 802.11a/g implementations
From: johnhandwork@mail.com (John_H)
Date: 25 Oct 2003 21:49:49 -0700
Links: << >>  << T >>  << A >>
dbeberman@earthlink.net (David) wrote in message (Saturday) news:<366a0905.0310250649.7e4883f@posting.google.com>...
> Hi, 
> 
> I've been reading the archives of this list, and the FAQ.  I haven't
> seen much about 802.11a and g phy implementations.  Does anybody know
> where I might find 802.11a/g VHDL, Verilog or other implementations.
> This does not need to be open source, however, I am looking for
> something that I will be able to add my own modifications to.
> 
> Thanks,
> 
> David


dbeberman@earthlink.net (David) wrote in message (Thursday) news:<366a0905.0310230935.1e6ef60@posting.google.com>...

>> Hi, I've searched the archive for this newsgroup, and read the FAQ.
>> I'm wondering if anybody can help me locate an 802.11a or g phy VHDL,
>> Verilog or other implementation.
>> 
>> Thanks,
>> 
>> David
>> dbeberman@earthlink.net


This is the FPGA group.  We tend to be digital.  Are you aware that
the phy (as in "physical") tends to be an analog endeavor?  Do you
mean that you want a MAC (Media Access Controller) to interface to a
known external phy?

Most manufacturers that present 802.11 solutions do so with chipsets. 
You may see some single-chip solutions for 802.11a/b/g in the near
future but it looks like they aren't out quite yet.

Article: 62312
Subject: Virtex2 DCMs
From: "Niv" <niv**SPAM_OFF**@ntlworld.com>
Date: Sun, 26 Oct 2003 07:12:54 -0000
Links: << >>  << T >>  << A >>
Hi, I'm generating an internal clock freq. from the ext. osc by using 2
DCMs', (1 wont do it).
The first generates 6/5 of ext freq and 2nd 32/25 of that.
All simulates OK in modelsim.
However, when I synth & then PAR, the PAR tool fails at the translate stage
due to some sort of "TNM" error on the 6/5 clock between the 2 DCMs.  It
seems to be some  "............dup0"  signal which the synth tool may have
created?

Anyway, couldn't get past this so routed 6/5 to a pin and then back in again
to 2nd DCM, all works fine!!!

So, how do I get it to synth/PAR without the external mid clock connection?

TIA, Niv.



Article: 62313
Subject: Verilog Program With A Problem
From: blueforest2@yahoo.com (Bose)
Date: 26 Oct 2003 00:15:16 -0700
Links: << >>  << T >>  << A >>
Hi to all,

I'm writing a program using verilog at the moment. The program that
i'm doing now is one of many blocks that will be finally linked up
together...Right now, i'm having some problems with my program...In my
program, i have a part where i need to compare the input(eingated) &
an output(eout_prev) of another program which is a D flip flop. So in
my program what should i define "eout_prev" as? An input, output, reg
...?
I need help urgently. Anyone can help me out ?

Thanks a lot! :-)

Below is my program & the D flip flop program ,and i have pointed to
where my problem lies.


--------------------------------------------------------------------------------

`timescale 1ns/1ps

module encoder(eingated, clr, clk, keydet, inhibit, eout);
 
input [3:0]eingated;
input clr, clk;
output keydet, inhibit;
output [3:0]eout;
reg [3:0]eout;
reg keydet, inhibit;

parameter idle = 1'b0, keypressed = 1'b1;
reg [1:0] cur_state, next_state;
reg eout_prev;


always @(posedge clk or negedge clr)
begin
      if(clr==0)
         cur_state = idle;
      else
         cur_state = next_state;
end



always@(cur_state or eingated or eout or eout_prev) 
begin
      case(cur_state)
      idle : if (eingated == 4'b1110 || eingated == 4'b1101 ||
eingated == 4'b1011 || eingated == 4'b0111)
             begin
                keydet = 1'b1;
                inhibit = 1'b1;
                next_state = keypressed;
             end
             else
             begin
                 keydet = 1'b0;
                 inhibit = 1'b0;
                 next_state = idle;
             end

     
  keypressed : if (eingated == 4'b1110 || eingated == 4'b1101 ||
eingated == 4'b1011 || eingated == 4'b0111)
               if (eout == eout_prev)       <------- What to define
               begin                                 "eout_prev" as?
                  keydet = 1'b1;		
                  inhibit = 1'b1;
                  next_state = keypressed;
               end
               else
               begin
                  keydet = 1'b0;		
                  inhibit = 1'b1;
                  next_state = idle;
               end
               else               
               begin
                  keydet = 1'b0;		
                  inhibit = 1'b0;
                  next_state = idle;
               end
      endcase
end


always @(eingated)
begin
   case (eingated)
       4'b1110: eout = 2'b00;
       4'b1101: eout = 2'b01;
       4'b1011: eout = 2'b10;  
       4'b0111: eout = 2'b11;
       default: eout = 2'b0;
   endcase    
end

endmodule      


--------------------------------------------------------------------------------
Below is the program of the D flip flop with output "eout_prev" :



`timescale 1ns/1ps

module eoutTemp(eout, keydet, clear, eout_prev);

input [1:0] eout;
input keydet, clear;

output [1:0] eout_prev;
reg [1:0] eout_prev;

always @(posedge keydet or negedge clear)
   if(clear==0)
      eout_prev<=2'b0;
   else eout_prev<={eout};

endmodule

Article: 62314
Subject: bugfix
From: "DIYByteblaster" <DIYByteblaster@nospam.de>
Date: Sun, 26 Oct 2003 08:34:36 +0100
Links: << >>  << T >>  << A >>
Bugfix (the bit order in the rbf file is revers)
------------------------
Private Sub Command1_Click()
Dim filelength As Long
Dim l As Long
Dim ok As Boolean
Dim rs As Byte
Dim b As Byte
Dim chipid As Byte
Dim i As Integer
Dim tb As Byte

For l = 0 To 524287
bytebuffer(l) = 255
Next l

chipid = ReadID
If chipid = 16 Then
 MsgBox "ChipID: EPCS1"
Else
 If chipid = 17 Then
  MsgBox "ChipID: EPCS4"
  Else
  MsgBox "no configuration device found"
  Exit Sub
  End If
End If





CommonDialog1.CancelError = True
On Error GoTo ErrHandler
CommonDialog1.Flags = cdlOFNHideReadOnly
CommonDialog1.Filter = "Alle Dateien (*.*)|*.*|" & "AS File (*.rbf)|*.rbf"
CommonDialog1.FilterIndex = 2
CommonDialog1.ShowOpen

Open CommonDialog1.FileName For Binary Access Read As #1
Seek #1, 1
filelength = LOF(1)
For l = 0 To (filelength - 1)

Get #1, l + 1, b

tb = 0

For i = 1 To 8
 tb = tb \ 2
 If b > 127 Then
 tb = tb + 128
 b = b - 128
 End If
 b = b * 2
Next i
bytebuffer(l) = tb
Next l

Close #1




WriteEnable
EraseBulk
Do
rs = ReadStatus
Loop Until (rs Mod 2) = 0

For l = 0 To (filelength - 1)
 WriteEnable
 b = bytebuffer(l)
 WriteB l, b
 Do
 rs = ReadStatus
 Loop Until (rs Mod 2) = 0

  If (l Mod 100) = 0 Then
  Form1.Caption = "programming: " + Str(1 + l * 100 \ filelength) + "%"
  DoEvents
  End If

Next l

ok = True
For l = 0 To (filelength - 1)
 If bytebuffer(l) <> ReadB(l) Then
  ok = False
 End If

  If (l Mod 100) = 0 Then
  Form1.Caption = "verifing: " + Str(1 + l * 100 \ filelength) + "%"
  DoEvents
  End If


Next l

If ok Then
 MsgBox "OK"
Else
 MsgBox "NOT OK"
End If


Exit Sub

ErrHandler:
MsgBox "File Open Error"
Close #1
End Sub



Article: 62315
Subject: Re: Altera cyclone circuit board indicator
From: Ben Popoola <b.popoola@ntlworld.com>
Date: Sun, 26 Oct 2003 08:01:18 +0000
Links: << >>  << T >>  << A >>
Khim Bittle wrote:

> On Thu, 23 Oct 2003 04:31:26 +0100, Ben Popoola
> <b.popoola@ntlworld.com> wrote:
> 
> 
>>I wish to connect a LED to the CONF_DONE pin of a cyclone FPGA to 
>>indicate when configuration has been completed.
>>
>>The CONF_DONE pin is an open collector pin that is pulled high via a 10K 
>>resistor when configuration is completed.
>>
>>Do I connect my circuit board indicator to ground (through another 
>>resistor) or should I connect it to the power rail?
>>
>>Thanks
>>Ben
>>
> 
> 
> Another idea which I just used on a cyclone design .. i put a small
> smt led from the NCEO pin to ground via a 220 resistor, the led
> flashes when power is first applied during configuration, if the led
> remains on there is a problem.  I like this particularly for multiple
> cyclones loading from one flash device since each cyclone can have
> it's own led beside the chip indicating which cyclone did not
> configure instead of using the conf_done pins because these are tied
> together for a multiple cyclone string and cannot point to the chip. 
> 

This sounds like a reasonable alternative solution but I would like the 
indicator to come on after configuration.


Article: 62316
Subject: Re: Verilog Program With A Problem
From: "Peng Cong" <pc_dragon@sohu.com>
Date: Sun, 26 Oct 2003 17:54:53 +0800
Links: << >>  << T >>  << A >>
In module encoder, "eout_prev" is an input

"Bose" <blueforest2@yahoo.com> 写入消息新闻
:a395f2ee.0310252315.1ae0a344@posting.google.com...
> Hi to all,
>
> I'm writing a program using verilog at the moment. The program that
> i'm doing now is one of many blocks that will be finally linked up
> together...Right now, i'm having some problems with my program...In my
> program, i have a part where i need to compare the input(eingated) &
> an output(eout_prev) of another program which is a D flip flop. So in
> my program what should i define "eout_prev" as? An input, output, reg
> ...?
> I need help urgently. Anyone can help me out ?
>
> Thanks a lot! :-)
>
> Below is my program & the D flip flop program ,and i have pointed to
> where my problem lies.
>
>
> --------------------------------------------------------------------------
------
>
> `timescale 1ns/1ps
>
> module encoder(eingated, clr, clk, keydet, inhibit, eout);
>
> input [3:0]eingated;
> input clr, clk;
> output keydet, inhibit;
> output [3:0]eout;
> reg [3:0]eout;
> reg keydet, inhibit;
>
> parameter idle = 1'b0, keypressed = 1'b1;
> reg [1:0] cur_state, next_state;
> reg eout_prev;
>
>
> always @(posedge clk or negedge clr)
> begin
>       if(clr==0)
>          cur_state = idle;
>       else
>          cur_state = next_state;
> end
>
>
>
> always@(cur_state or eingated or eout or eout_prev)
> begin
>       case(cur_state)
>       idle : if (eingated == 4'b1110 || eingated == 4'b1101 ||
> eingated == 4'b1011 || eingated == 4'b0111)
>              begin
>                 keydet = 1'b1;
>                 inhibit = 1'b1;
>                 next_state = keypressed;
>              end
>              else
>              begin
>                  keydet = 1'b0;
>                  inhibit = 1'b0;
>                  next_state = idle;
>              end
>
>
>   keypressed : if (eingated == 4'b1110 || eingated == 4'b1101 ||
> eingated == 4'b1011 || eingated == 4'b0111)
>                if (eout == eout_prev)       <------- What to define
>                begin                                 "eout_prev" as?
>                   keydet = 1'b1;
>                   inhibit = 1'b1;
>                   next_state = keypressed;
>                end
>                else
>                begin
>                   keydet = 1'b0;
>                   inhibit = 1'b1;
>                   next_state = idle;
>                end
>                else
>                begin
>                   keydet = 1'b0;
>                   inhibit = 1'b0;
>                   next_state = idle;
>                end
>       endcase
> end
>
>
> always @(eingated)
> begin
>    case (eingated)
>        4'b1110: eout = 2'b00;
>        4'b1101: eout = 2'b01;
>        4'b1011: eout = 2'b10;
>        4'b0111: eout = 2'b11;
>        default: eout = 2'b0;
>    endcase
> end
>
> endmodule
>
>
> --------------------------------------------------------------------------
------
> Below is the program of the D flip flop with output "eout_prev" :
>
>
>
> `timescale 1ns/1ps
>
> module eoutTemp(eout, keydet, clear, eout_prev);
>
> input [1:0] eout;
> input keydet, clear;
>
> output [1:0] eout_prev;
> reg [1:0] eout_prev;
>
> always @(posedge keydet or negedge clear)
>    if(clear==0)
>       eout_prev<=2'b0;
>    else eout_prev<={eout};
>
> endmodule



Article: 62317
Subject: Re: Running Quartus II on ReadHat Linux 9.0
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: 26 Oct 2003 11:18:27 +0100
Links: << >>  << T >>  << A >>
"Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl> writes:

> Trouble with all this distribution stuff is that there is no defined
> standard that tells you how to determine which distribution a system is
> running on. Even doing an "ls -l /etc | grep *release" will not give you the
> full info, because every distro puts different things into these files, plus
> they may have, for example redhat-release and lsb-release, containing
> different data structures. Determining the kernel version and/or glibc
> version is useless (Suse 9.0 reports 2.4.21-99 or so), glibc versions may or
> may not have NTPL support using the same version number and more of that
> stuff. Really messy.

I think it's wrong to check for the distribution. One should check for
the functionality required by the tool. If you require a certain
thread library, check for that and report that installation fails
since the specific thread library is not present.

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 62318
Subject: SDRAM Controller
From: george_mercury@hotmail.com (George)
Date: 26 Oct 2003 04:19:56 -0800
Links: << >>  << T >>  << A >>
Hi!
I am a bit new to FPGAs, so far I have only worked with CPLDs ( Xilinx
9500 family ). Now I would like to use a Spartan 2E ( with WebPack 5.2
and VHDL ) to make a SDRAM controller.

I have searched this archive but I haven't found any topic related to
my question. Here's the deal. When data needs to be transfered to the
SDRAM the controller sends out data prior to generating the rising
edge of the SDRAM's clock. So the way I see it, the fpga must generate
two clocks, one for the controller and one for the SDRAM. The SDRAM
clock must be by 90 out of phase of the controller clock ( the SDRAM
clock must be delayed for 1/4 of the cycle of the controller clock ),
in order for data to appear on DQ lines before the rising edge of
SDRAM's clk. I am right so far, or am I way off? And If I am right,
how do you generate the SDRAM clock ( do you use a DLL to phase-shift
the input clock ? ).

Best regards
George Mercury

Article: 62319
Subject: Re: Picoblaze development tool
From: henk@mediatronix.com (Henk van Kampen)
Date: 26 Oct 2003 06:18:38 -0800
Links: << >>  << T >>  << A >>
Dear Laurent:

> Could you explain what we can do with your JTAG option ? Can we do 
> on-chip PicoBlaze debugging or ROM download ?

That is the idea. You can generate an SVF file by including in your
source file:
       SVF "testjtag.svf"

It will generate an SVF file based on the specifications in the JTAG
tab of the settings dialog and your source. Since this is still in its
infance please let me know is this is useful or what to change/add.
Since your are an probably an expert on JTAG considering your
Chamelion product I welcome your advice.

> Actually, we are working on reconfigurable high speed automat machine. 
> We will try to use picoblaze as base. One automat will have about 10 to 
> 100 picoblaze. The goal is to keep the speed and true multi-processing 
> achitechture of sequencial function.

Very interesting. You will, however, need a lot of blockrams. And with
the JTAG option you can not use two PB's with one blockram. By the
way, how do you want to let the PB's communicate? One of my own wishes
for pBlazIDE is to be able to simulate several PB's in cooperation.
This will need some for of inter I/O port, which needs to be simulated
and therefore some how specified. I also have used more than 1 PB in a
design and have them communicate but that was by some form of
dual-ported RAM. So let me know what your ideas are.

Henk van Kampen
www.mediatronix.com

Article: 62320
Subject: Re: Modeling hardware in Matlab/Simulink (delay, etc.)?
From: tom1@launchbird.com (Tom Hawkins)
Date: 26 Oct 2003 12:38:08 -0800
Links: << >>  << T >>  << A >>
moe <moh@speakhard.net> wrote in message news:<3F9B33DB.5ED63369@speakhard.net>...
> Hello all,
> 
> I need some guidedance on how to go about modeling an algorithm before I
> design it into an FPGA.
> 
> I'd like to use Matlab to run the simulation.  Instead of just sanity
> check, I also need to optimize the size (# of bits) of several
> parameters.  It'll be a balance act between # of bits (hence, FPGA
> performance) and precision of the algorithm output.  FPGA needs to run
> 150+Mhz, and the parameter sizes may end up being somewhat of an odd
> size (48?  56?), perhaps up to 64.  The algorithm is made up of mostly
> adders and delay elements.

You may want to consider Confluence (CF) for modeling your initial
design.
Like Simulink, CF is a structural dataflow language, i.e., you design
with systems and subsystems, wires and ports.  But instead of a GUI,
CF is textual language.

The main strength of Confluence is it's extensive use of parameters;
every CF variable is a configuration parameter that controls how a
system is created.  Therefore it's easy to add parameters to
experiment with design tradeoffs such as signal precision and system
architecture.

For simulation, Confluence compiles into cycle and bit accurate C and
Python models.  I personally prefer Python as a high-level testbench
language, but compiled C is very fast.  Also, it's straightforward to
integrate C models into Matlab via Simulink s-functions.


> 
> So far, it looks like I need to use Simulink with Fixed-point blockset.
> Is that sufficient, or is there a better way to do this?   I've been
> reading previous posts in different places, and it sounds like modeling
> delay isn't as easy as it should be.  Is that true?  I was able to use
> 'Triggered subsystem' to model a FF without much problem, but then it
> was for a very simple single bit data path.

If you're targeting an FPGA, your delays (aka. registers) should be
synchronous, i.e., the output data only changes on the clock edge.  If
you only have one clock domain, synchronous registers are modeled in
Simulink as a unit delay block (1/z).  I would stay away from
triggered subsystems because their
semantics do not correspond to hardware.  If you need a delay with a
synchronous
reset and enable, you can add a couple switches in front of the 1/z as
shown in the following pseudo code:

  UnitDelayInput = Reset ? 0 : (Enable ? Input : UnitDelayOutput)
  Output = UnitDelayOutput

In terms of delays, Confluence is a purely synchronous language; all
registers are synchronous.  For example, gluing a chain of 7 delays
together is done like this:

  {Delay, 7 DataIn, DataOut}

Note that 7 is a configuration parameter.  Techincally speaking,
DataIn is too.  One nice feature of the language is clocks, resets,
and enables are implicit.  This allows you to clock, reset, or enable
entire subsystems, without having to drag these signals down to every
register in a hierarchy.

You can find Confluence at: http://www.launchbird.com/download.html

If you'd like to see a particular example, let me know.

Regards,
Tom

--
Tom Hawkins
Launchbird Design Systems, Inc.
952-200-3790
http://www.launchbird.com/


> 
> I'd appreciate any input, feedback, insight, suggestion.  I'm sending
> this to VHDL/Verilog newsgroups for a wider audience.
> 
> Please replace 'hard' with 'easy' in my email addr, if replying via
> email.
> 
> -moe

Article: 62321
Subject: Picky WebPACK 6.1
From: "Pablo Bleyer Kocik" <pbleyerN@SPAMembedded.cl>
Date: Sun, 26 Oct 2003 20:15:51 -0300
Links: << >>  << T >>  << A >>
 Hello.

 I am designing a memory interface for an MCU in a SpartanII with Webpack
6.1.02i. To optimize pin usage in my design, address and data buses are
muxed and I am trying to use latched addresses.

 To synthetize my latch under Verilog, I first wrote.

always @(AD, A_g) if (A_g) A_r <= AD;

 where AD is the address/data vector input of type reg[7:0], A_g is the gate
signal and A_r the internal address latch. According to the Libraries Guide,
multiple transparent data latches are implemented as macros in the SpartanII
and the synthesis step reports me and 8-bit latch being generated with the
same Verilog syntax suggested by this guide. However, translate gives
warnings and mapping fails:

[...]
Checking expanded design ...
WARNING:NgdBuild:477 - clock net 'A_g_BUFGP' has non-clock connections.
These
   problematic connections include:
     pin I1 on block I2_EnableTr_INV1 with type LUT3
[...]
Started process "Map".

Using target part "2s100tq144-5".
ERROR:MapLib:93 - Illegal LOC on IPAD symbol "A_g" or BUFGP symbol
"A_g_BUFGP"
   (output signal=A_g_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB
site.

 Now, I look into the Libraries Guide again and I see that latches with
inverted gates are primitives in the SpartanII. I change my equations a
little:

 wire nA_g = !A_g;
 always @(AD, nA_g) if (!nA_g) A_r <= AD;

 And, voil, this time it works. Synthesis reports also an 8-bit latch being
detected.

 Why is Webpack being so picky? I was expecting that it should have detected
automatically the inverted gate signal and generated the correct signal for
its primitive itself...

 Also, I have being trying unsuccessfully to get it to recognize and infer
block rams correctly for memory arrays, following the Verilog syntax
suggested by the Xilinx synthesis guide, but most of the time it generates
distributed RAMs...

 Regards.



Article: 62322
Subject: Does a dont_use statement exist?
From: "kris" <twofold@gmx.net>
Date: Sun, 26 Oct 2003 23:50:38 GMT
Links: << >>  << T >>  << A >>
Hi guys,

Is it possible to somehow put a synthesis constraint
(preferably with a flag or with directly in the verilog netlist and
otherwise in the synthesis constraint file)
such that the MUXes from the slices (e.g. MUXF5) are not used, but instead
all logic is
mapped directly onto the LUT's without these Muxes?

Like for example for an asic design you can tell to synopsys to not use
certain standard cells
by "set_dont_use { lib/gate }"
I'm looking for the FPGA equivalent.

Is this uberhaupt possible?
I'm using ISE 5.2 of Xilinx. The FPGA platform is the Virtex II..

Thanks,

Kris




Article: 62323
Subject: Re: SDRAM Controller
From: David R Brooks <davebXXX@iinet.net.au>
Date: Mon, 27 Oct 2003 08:22:51 +0800
Links: << >>  << T >>  << A >>
If you are using Virtex-II or Spartan-III, the Xilinx DCM block
provides 4 clock outputs, at 90 degree intervals.
See XAPP134 & 200 for some ideas.

george_mercury@hotmail.com (George) wrote:

:Hi!
:I am a bit new to FPGAs, so far I have only worked with CPLDs ( Xilinx
:9500 family ). Now I would like to use a Spartan 2E ( with WebPack 5.2
:and VHDL ) to make a SDRAM controller.
:
:I have searched this archive but I haven't found any topic related to
:my question. Here's the deal. When data needs to be transfered to the
:SDRAM the controller sends out data prior to generating the rising
:edge of the SDRAM's clock. So the way I see it, the fpga must generate
:two clocks, one for the controller and one for the SDRAM. The SDRAM
:clock must be by 90 out of phase of the controller clock ( the SDRAM
:clock must be delayed for 1/4 of the cycle of the controller clock ),
:in order for data to appear on DQ lines before the rising edge of
:SDRAM's clk. I am right so far, or am I way off? And If I am right,
:how do you generate the SDRAM clock ( do you use a DLL to phase-shift
:the input clock ? ).
:
:Best regards
:George Mercury


Article: 62324
Subject: Re: Hex display with Quartus simulation
From: "Subroto Datta" <sdatta@altera.com>
Date: Mon, 27 Oct 2003 02:25:59 GMT
Links: << >>  << T >>  << A >>
Use the waveform editor and arrange the individual bits in order, with MSB
on top, LSB at the bottom. Click with the right button and use the Group
command. It will ask for the name of the group and the radix with which to
display it. Hope that helps.

- Subroto Datta
Altera Corp.

"Pratip Mukherjee" <pratipm@hotmail.com> wrote in message
news:Xns94206147D5C7pratipmhotmailcom@204.127.199.17...
> Hi,
> If I have a port defined as std_logic_vector(n downto 0), Quartus
simulator
> is showing the individual bits in binary values. How do I make it display
> all the bits together in a hex mode.
> Thanks in advance.
>
> Pratip Mukherjee





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