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Thank you for your advice. But in the CoreGenerator I could only choose wether to use the rising or the falling edge. I could not find which clock is meant. I use a development board from Xilinx ( --> Spartan-IIE-LC). I know that a 100 MHz oscillator is used in the design. It is connected to one of the 4 global clock nets. I suppose the ILA Core uses this clock. But yet I didn't find a pull down menue or a dialog box in the GUI to choose which clock signal of the design is used for sampling the signals. Can you tell me where to choose it? Tobias >Article: 66326
Tobias Möglich wrote: > Thank you for your advice. > But in the CoreGenerator I could only choose wether to use the rising or the > falling edge. > I could not find which clock is meant. > I use a development board from Xilinx ( --> Spartan-IIE-LC). > I know that a 100 MHz oscillator is used in the design. It is connected to one > of the 4 global clock nets. > I suppose the ILA Core uses this clock. But yet I didn't find a pull down menue > or a dialog box in the GUI to choose > which clock signal of the design is used for sampling the signals. > > Can you tell me where to choose it? You assign the clock when you instantiate the ILA in your design. CoreGenerator can generate example VHDL-files for you, if you check the corresponding option. Then you can assign whatever clock you like to the "CLK"-port of the ILA core in the instantiation. With Chipscope Pro comes a "Core Inserter" you can use. It offers a GUI to make all the signal connections, including the clock. That way, you don't have to instantiate ILA/ICON in your design. -- Sean Durkin Fraunhofer Institute for Integrated Circuits (IIS) Am Wolfsmantel 33, 91058 Erlangen, Germany http://www.iis.fraunhofer.de mailto:23@iis.42.de ([23 , 42] <=> [durkinsn , fraunhofer])Article: 66327
There has been a push away from using GSR resources. Synthesisers probably now have the feature removed or turned off for modern families. I think this has been done mainly for simulation purposes and to speed up timing. My way around this is to use a small lfsr, or other counter, and recognise a pattern of '1's and '0's. Make your reset active when the pattern of the lfsr does not match you given final state (final state freezes count). Whatever default power up state of the flip-flops, be in '0' or '1', you won't start with pattern that releases reset. The output can be used for GSR driving or wired reset. John Adair Enterpoint Ltd. This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:40313fb8$0$6685$fa0fcedb@lovejoy.zen.co.uk... > In most FPGA designs I've done there's been an external reset > input which has been used as the power on reset mechanism. > > I'm now doing a design for a Spartan-3 with no external reset, > and I've some signals I need pre-set so I need to use the > internal asynch reset mechanism. > > I've read here in the past of the problems of using the GSR, > but in this design there are synchronous enables which > control the data flow. The functionality of these means there > shouldn't be any timing problems out of reset. > > I was under the impression that if you had a top level signal > which was used in the usual VHDL asynchronous reset template > manner, the synthesis tools would pick it out and connect it > to the GSR net. > > I'm using XST and getting .. > > "Signal <rst> is used but never assigned. Tied to value 0." > > > So what do I need to do to get 'rst' connected to the GSR > net? > > I've spent a fair bit of time searching the Xilinx site/docs > and googling this group with no results. It seems to be one > of those things that I should probably know, but just can't > find anywhere. > > Thanks for any pointers, > > > Nial. > >Article: 66328
> There has been a push away from using GSR resources. Synthesisers probably > now have the feature removed or turned off for modern families. I think this > has been done mainly for simulation purposes and to speed up timing. It looks like it John, a search for 'GSR' in the XST user guide only comes up with one hit, and that's for the Synplicity directive "xc_isgsr" which has no XST equivalent. > My way around this is to use a small lfsr, or other counter, and recognise a > pattern of '1's and '0's. Make your reset active when the pattern of the > lfsr does not match you given final state (final state freezes count). > Whatever default power up state of the flip-flops, be in '0' or '1', you > won't start with pattern that releases reset. The output can be used for GSR > driving or wired reset. I'd thought of this, but it felt like a bit of a bodge. I suppose it should be reliable as the data sheet stipulates that the registers power up to '0' unless otherwise specified. Have you had any problems with it? I'll give it a go and see how I get on. Thanks, Nial.Article: 66329
I have not had any issues doing this. The synthesiser will usually pick a flop macro with '0' default but if it chooses a '1' default type you are covered by looking for pattern of mixed '0's and '1's. It is very unlikely that the pattern you choose will be the same as the synthesiser by way of the power up defaults. You can always double check and have a look using FPGA Editor or the equivalent. John Adair Enterpoint Ltd. This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:4031fad1$0$25865$fa0fcedb@lovejoy.zen.co.uk... > > There has been a push away from using GSR resources. Synthesisers probably > > now have the feature removed or turned off for modern families. I think > this > > has been done mainly for simulation purposes and to speed up timing. > > It looks like it John, a search for 'GSR' in the XST user guide only comes > up with one hit, and that's for the Synplicity directive "xc_isgsr" which > has no XST equivalent. > > > > My way around this is to use a small lfsr, or other counter, and recognise > a > > pattern of '1's and '0's. Make your reset active when the pattern of the > > lfsr does not match you given final state (final state freezes count). > > Whatever default power up state of the flip-flops, be in '0' or '1', you > > won't start with pattern that releases reset. The output can be used for > GSR > > driving or wired reset. > > I'd thought of this, but it felt like a bit of a bodge. > I suppose it should be reliable as the data sheet stipulates that > the registers power up to '0' unless otherwise specified. > > Have you had any problems with it? > > I'll give it a go and see how I get on. > > Thanks, > > > Nial. > >Article: 66330
Thanks Peter, Hopefully I should be able to program the V2Pros now. Adarsh "Peter Alfke" <peter@xilinx.com> wrote in message news:40317F78.620BAB17@xilinx.com... > I forgot to mention: > All INITbar outputs are connected together, with a 1 kilohm pull-up > resistor, and hold the SPROM reset while that common pin is Low. > This guarantees that all chips wait for the slowest device to come out > of power-on reset (POR) > Peter Alfke. > > Peter Alfke wrote: > > > > One of the V2P7 chips is the master and drives CCLK to the SPROM and to > > the other V2P7s, the other seven V2P7s must be in slave serial mode and > > receive CCLK. Al Din pins are tied together and thus receive the same > > bitstream from the SPROM.. > > > > Peter Alfke > > > > Adarsh Kumar Jain wrote: > > > > > > Hi, > > > I am trying to configure 8 Virtex 2 Pros (V2P7) (with the same bitstream) on > > > a single board. > > > I will use the the Master Serial programming mode. > > > Are there known issues which i need to worry about ? > > > Any documentation available ? Prior Experience ? > > > Thanks in advance, > > > AdarshArticle: 66331
Kelvin, bus macro sent via Email. Anybody else need this part just ask!! John, I'm glad it's not just me! Also, thanks to John, the partial reconfig list is now active at http://www.itee.uq.edu.au/~listarch/partial-reconfig/ just one thought however, does it have to be restriced to Xilinx devices?? Cheers All, Ian.Article: 66333
Hi Nial, I'm not quite sure if it solves your problem, but i currently use the ROC (ResetOnConfiguration) primitive to connect the reset signal to the GSR. You'll find more information about it in the Xilinx "Libraries Guide" (lib.pdf). Kind regards, Lars.Article: 66334
Sean Durkin wrote: > Tobias Möglich wrote: > > Thank you for your advice. > > But in the CoreGenerator I could only choose wether to use the rising or the > > falling edge. > > I could not find which clock is meant. > > I use a development board from Xilinx ( --> Spartan-IIE-LC). > > I know that a 100 MHz oscillator is used in the design. It is connected to one > > of the 4 global clock nets. > > I suppose the ILA Core uses this clock. But yet I didn't find a pull down menue > > or a dialog box in the GUI to choose > > which clock signal of the design is used for sampling the signals. > > > > Can you tell me where to choose it? > You assign the clock when you instantiate the ILA in your design. > CoreGenerator can generate example VHDL-files for you, if you check the > corresponding option. Then you can assign whatever clock you like to the > "CLK"-port of the ILA core in the instantiation. > > With Chipscope Pro comes a "Core Inserter" you can use. It offers a GUI > to make all the signal connections, including the clock. That way, you > don't have to instantiate ILA/ICON in your design. > Ouuh yes - I see. I use the "Core Inserter". And I already connected the clock signal to a certain oscillator in my hardware. I forgot that I did it. And now I wondered why it worked. Thank you very much. Question: Is it possible to see the clock signal also in the scope? Or ist only possible to see the Data/ and trigger signals? TobiasArticle: 66335
> > Thank you for your advice. I tried to use ModelSim Starter XE. But it has not much resources (free version). But now I downloaded ChipScope (free version) and it seems to help !!! Question: Is it also possible to analyse signals of IO pins. It seems to me that they are not available in the "ChipScope Analyser". Is it so? Or is it a mistake of mine. Yet I couldn't manage to display signals which come directly from a IO pad in the scope TobiasArticle: 66336
Tobias Möglich wrote: > Question: Is it possible to see the clock signal also in the scope? > Or ist only possible to see the Data/ and trigger signals? Well, you can add clock signals to the data signals you want to sample like any other signal... But since you always sample at the rising or falling edge of your clock, it will always be 1 or 0, respectively, so that's not really useful. -- Sean Durkin Fraunhofer Institute for Integrated Circuits (IIS) Am Wolfsmantel 33, 91058 Erlangen, Germany http://www.iis.fraunhofer.de mailto:23@iis.42.de ([23 , 42] <=> [durkinsn , fraunhofer])Article: 66337
Thank you for your advice. Ahm, but where is it possible to set the switch? Is it done in the ucf-file or in a GUI ? Tobias John Adair wrote: > IOBs can be used as general resource and the tools can make use of these > resources. Try the switch "USE BONDED I/OS" in the P&R properties to see if > that makes your issue go away. > > John Adair > Enterpoint Ltd. > > This message is the personal opinion of the sender and not that necessarily > that of Enterpoint Ltd.. Readers should make their own evaluation of the > facts. No responsibility for error or inaccuracy is accepted. > > "Tobias Möglich" <Tobias.Moeglich@gmx.net> wrote in message > news:4030F01F.92CDA398@gmx.net... > > Hello > > > > I use Xilinx ISE 6.1 for synthesis. > > I discovered in the floorplanner that there are used very much IOB's. > > Even more than used IO pads. > > Why that ?? Is it for the reason of timing constraints (for example > > delays)?? > > As far as I know, I haven't made any timing constraint in my design. > > Is it possible not to use so many IOB's. > > How can I tell ISE to do so ? > > > > > > Greatings Tobi. > >Article: 66338
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:<4031ec0e$0$19544$fa0fcedb@lovejoy.zen.co.uk>... > > The STARTBUF_SPARTAN3 module does the same thing, but with an > output you can connect to your HDL reset lines which mirrors > the GSR net. Thus simulations should match real life. > > > This doesn't help me tie my top level 'rst' net to the GSR. > I've checked through my design and _all_ my asynch reset > declarations use this net with the correct polarity. > > Any more ideas? > > > Nial. Hi Nial, Yeah, tricky one, what I've done in the past is use the STARTBUF_whatever instantiation, its output connected to rst, and its input tied to an 'unconnected on the PCB' or an unbonded IOB with the PULLUP turned on. This stops things being optimised away. I've used John's method too; it's just as bodgy as the IOB method but gets the job done! In fact I just looked at my latest masterpiece; I did the IOB thing above but left out the STARTBUF_ instantiation. All my FFs get set or reset on power up correctly, as if by magic! Cheers, Syms.Article: 66339
Look in the GUI. It can probably also be done at command line/batch file too but I don't use command line very often. It might be worth looking at exactly what is being used in the IOBs with FPGA Editor. You might find you don't have a real issue but of course that depends on your design and your future plans for unused IOBs etc etc. John Adair Enterpoint Ltd. This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Tobias Möglich" <Tobias.Moeglich@gmx.net> wrote in message news:403243E5.DE36C22@gmx.net... > Thank you for your advice. > Ahm, but where is it possible to set the switch? > Is it done in the ucf-file or in a GUI ? > > Tobias > > > > John Adair wrote: > > > IOBs can be used as general resource and the tools can make use of these > > resources. Try the switch "USE BONDED I/OS" in the P&R properties to see if > > that makes your issue go away. > > > > John Adair > > Enterpoint Ltd. > > > > This message is the personal opinion of the sender and not that necessarily > > that of Enterpoint Ltd.. Readers should make their own evaluation of the > > facts. No responsibility for error or inaccuracy is accepted. > > > > "Tobias Möglich" <Tobias.Moeglich@gmx.net> wrote in message > > news:4030F01F.92CDA398@gmx.net... > > > Hello > > > > > > I use Xilinx ISE 6.1 for synthesis. > > > I discovered in the floorplanner that there are used very much IOB's. > > > Even more than used IO pads. > > > Why that ?? Is it for the reason of timing constraints (for example > > > delays)?? > > > As far as I know, I haven't made any timing constraint in my design. > > > Is it possible not to use so many IOB's. > > > How can I tell ISE to do so ? > > > > > > > > > Greatings Tobi. > > > >Article: 66340
Hi Jeroen. One subtle "feature" of the GNU compiler is that it treats files with the extension ".C" (capital 'c') as a C++ file. If you were planning this to be purely c-language, you'll run into some strange errors. Try changing the extension from ".C" to ".c" and re-compile. -Joel- "Jeroen" <dev@null.com> wrote in message news:<402cdb03$0$567$e4fe514c@news.xs4all.nl>... > Hi, > > I'm working on a Cyclone FPGA with NIOS project, which contains an onchip > bootrom. I want to use a makefile to generate the contents of this bootrom. > At first I used a single .C file which worked fine, but now I'm using a > makefile and I can't get it to work. Can't find anything about it in the > Altera documentation or website. My makefile is very simple and only > contains one line to nios-build a bunch of C files. > The command I use is "make -f %2/myproject.make" but it terminates with a > strange error. > > Anyone any experience with this? > > JeroenArticle: 66341
kams wrote: > I had done the timing simulation with micron SDRAM . Read and write > operations are proper. But the same is not working in virtex2 FPGA > board.could you please give some suggestions to improve testing? Lack of synchronization is tough to find in simulation. But the answer is the same in any case. You need synchronization. Consider running your cpu and sdram on the same clock. That's the easiest way. -- Mike TreselerArticle: 66342
"Lars Unger" <larsu@ida.ing.tu-bs.de> wrote in message news:Pine.LNX.4.50.0402171641240.23416-100000@tom.ida.ing.tu-bs.de... > Hi Nial, > > I'm not quite sure if it solves your problem, but i currently use > the ROC (ResetOnConfiguration) primitive to connect the reset > signal to the GSR. You'll find more information about it in the > Xilinx "Libraries Guide" (lib.pdf). > > Kind regards, > Lars. Thanks Lars, I've implemented the reset count as discussed with John earlier. This looks cleaner though so I'll try it tomorrow and report back results. NialArticle: 66343
thanx, have made a script (thanx to a post by R Andraka where he mentioned some interesting matlab functions) in matlab and i found my coefficient and the FIR is up and running ;-) thanx yttrium "Marlboro" <ccon67@netscape.net> wrote in message news:e3fd5378.0402161950.5bdb7eea@posting.google.com... > "Yttrium" <Yttrium@pandora.be> wrote in message news:<sSNXb.2451$hs5.60476@phobos.telenet-ops.be>... > > wo when i have 0.002100205514 as a coefficient i enter it in the COE > > file as 2100205514 with the radix=10 and the width as i want it to be > > (with changing the coefficient to the size that it can fit the width!)? > > > > greetings, > > > > Yttrium > > > > > > <ccon> wrote in message news:ee82680.2@WebX.sUN8CHnE... > > scale your numbers to integer, the coef width depends on the > > resolution(decimal points)you wish. > > -- > > yup, it's something like that, and it also depends on max/min range of > your coefficients. For the number in your example you will need 32 bit > coe, and if your coef is signed you will need 1 more bit. In > practical you may reduce your resolution to fit in smaller device. > Generally speaking, you may ask yourself what kind of device you can > afford? what is your data width? howmany taps? and what kind of > FIR?...Article: 66344
Hi, i tried to find some references for lossless compression algorithms implemented in fpga. I found a lot about bitstream compression but (nearly) nothing about fpga implementations of lossless compression algorithms. Which lossless compression algorithms are suited for fpga implementation. Thank you.Article: 66345
Please submit your MHS to xilinx support. Dirk wrote: > Hy all! > > Since an view days I am using the EDK 6.1i from Xilinx. Now I tried to > use their reference design "opb_ssp1_v1_00_a". It's a design for the > Virtex II pro with an OPB-slave with interrupt support. > > But when I try to generate the bitstream, I get an error like this: > > - Running XST synthesis > opb_core_ssp1_wrapper (opb_core_ssp1) - > X:\v2p\opb_ssp1_v1_00_a\system.mhs:243 - > Running XST synthesis > ERROR:Xst:807 - E:/Programme/edk/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd > line 189: arguments of 'and' operator must have sa > me lengths. > ERROR:MDT - HDL synthesis failed! > ERROR:MDT - platgen failed with errors! > > Hm, I am not very familiar with VHDL and the EDK and I have no idea > what to do! > > Thank you - > > Dirk -- / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USAArticle: 66346
"Antti" <antti1000@yahoo.com> wrote in message news:<Yo1Xb.9392$g4.191012@news2.nokia.com>... > Thanks for your replies, > > As it turned out, the main (!) problem was timing related..but simply > clocking the controller and memory card with opposite clock edges seemed to > solve the problem..both in simulation and hardware :) Sounds like you had either a setup and hold problem, or perhaps you didn't check your timing constraints, or you didn't set timing constraints, or you have layout flight-time problems, or something. Or you have clock skew between the controller and the memory. Describe your clock structure. ---aArticle: 66347
Ian wrote: > Also, thanks to John, the partial reconfig list is now active at > > http://www.itee.uq.edu.au/~listarch/partial-reconfig/ Thanks for the advertising Ian :) Anyone wanting to join can send an email to majordomo@itee.uq.edu.au, with the *body text* subscribe partial-reconfig > just one thought however, does it have to be restriced to Xilinx devices?? Not at all - I just wonder how much of the detailed implementation / tool flow discussion would be relevant between brands A & X. I'm happy to broaden the charter to partial and dynamic reconfiguration generally. Regards, JohnArticle: 66348
lenz wrote: >Hi, > >i tried to find some references for lossless compression >algorithms implemented in fpga. I found a lot about >bitstream compression but (nearly) nothing about fpga >implementations of lossless compression algorithms. > >Which lossless compression algorithms are suited for fpga >implementation. > > Some years ago I had a need for a losslessly compressed database, and found some source code for the Lempel-Ziv-Welch compression program (LZW). I extracted the core code from it and inserted it into the database read-write program, and got it working. I didn't dwell on the details, but it looked pretty simple to me. It built a 'dictionary' of multi-byte patters it had seen, and assigned single-byte and then later 9, 10, 11, 12-etc. bit codes for these patterns. These functions seem like they could be done with an FPGA and an external RAM to hold the dictionary. (The dictionary is written in the output stream one entry at a time during compression, and then rebuilt when decompressing. You should be able to find some source code for LZW somewhere. JonArticle: 66349
Imagine you want to have an FPGA board that has a USB port and no other connection (i.e., no other way to upload a bitstream). Can that FPGA bootstrap itself over the USB port? There would be a 'boot' bitstream in some flash on the board and the FPGA would be configured initially with that bitstream. The function of that bitstream would be to make the FPGA listen on the USB port for another bitstream that is then used to configure the FPGA for its real function. Can this be done? Without external memory (other than the boot flash)? Just curious... -- GPG: D5D4E405 - 2F9B BCCC 8527 692A 04E3 331E FAF8 226A D5D4 E405
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