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"Kevin Neilson" <kevin_neilson@removethiscomcast.net> writes:
> That is a great question. It seems to me that the DCM really needs an
> output, in the clk2x domain, that tells you which cycles are aligned with
> the 1x clock. It's very often that I have to transfer data from the 1x
> domain to the 2x domain and then it's very useful to know this so I can
> maximize setup time.
>
> The way I do it is to have a 'T' flop (that toggles every cycle) in the 1x
> clock domain. This gets sampled in the 2x domain, and an edge detector in
> the fast domain determines which 2x cycles are aligned with the 1x cycles.
How much skew do you tolerate with that design?
My idea was to have two FFs that was clocked by the falling and rising
edge of the clk2x.
clk2x------------
| ______ | ______
|-o|> | |--|> |
| | | |
clk-----|D Q|-----|D Q|---- clk_ce
| | | |
------ ------
If duty cycles are 50/50 this should tolerate quite som skew, right?
Takes two slices.
Hmm, if you use clk90 and ckl2x, you could sample on rising edge of
clk2x, and then you only need one FF.
Objections anyone?
Homann
--
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se
Article: 66751On Wed, 25 Feb 2004 23:32:31 +0000 (UTC), Sander Vesik <sander@haldjas.folklore.ee> wrote: > Taavi Hein <hein@bps.co.ee> wrote: >> >>>> * The licensee Will agree that the PCI IP core will be used only for >>>> non-commercial, non-profit, non-academic research, and personal >>>> purposes. >> >> I could live with that restriction. > > Really? Oops! I missed the "non-" in front of academic research... I'm sorry Kevin, but I'll have to take back the above statement. -- Taavi Hein, ...who sometimes tries to read too fast.Article: 66752
Hallo,
"Avinash Sharma" <asharma3@REMOVETHIS.uiuc.edu.NOSPAM> writes:
> is it true that one-hot encoding for FSM's is used in FPGA's? If so,
> why? is it due to the large amount of registers available i.e: enough
> registers to store all states? what kind of encoding is using in ASIC's?
have a look at this:
http://toolbox.xilinx.com/docsan/2_1i/data/common/sim/app1.htm
Florian
--
int m,u,e=0;float l,_,I;main(){for(;1840-e;putchar((++e>907&&942>e?61-m:u)
["\t#*fg-pa.vwCh`lwp-e+#h`lwP##mbjqloE"]^3))for(u=_=l=0;79-(m=e%80)&&
I*l+_*_<6&&26-++u;_=2*l*_+e/80*.09-1,l=I)I=l*l-_*_-2+m/27.;}
Article: 66753"Jim Granville" <no.spam@designtools.co.nz> wrote in message news:Le8%b.28417$ws.3197913@news02.tsnz.net... <snip> > You can get a feel for jitter, and what matters, by doing some > slew/threshold calculations. > eg consider a clock signal slewing at 1Volt/ns, and apply 10mv of > threshold noise ( combined effects of Vcc noise ,Gnd bounce and > crosstalk ) then purely the threshold modulation gives 10ps of jitter. > So, in CMOS a clean (linear) low noise power supply will help, > as will short, shielded traces for Osc module -> PLD. > Faster edges from the Osc module will help (if you get the choice), > and keeping any async, or random content signals 'away' from the clock > divider portion of the PLD. > If you have a PLD+HC04, doing only /2, you could consider a HC1G79 > which is a tiny logic FF, to do both jobs. With NO other signals, > and very low power, as well as a tiny package, this should have the > lowest possible jitter. > > In Audio, I believe jitter affects absolute noise floors, so you could > look for that effect. > At 48KHz that's ~20us, so 20ns jitter is -60dB, and 20ps jitter > is -120dB (numeric ratio only) - so it's not entirely snake > oil, jitter numbers well under 1ns could have a measurable (if not > audible:) impact. > > For some real values quoted by process, see OnSemi's TND301 > http://www.onsemi.com/pub/Collateral/TND301-D.PDF > > -jg > Thanks Jim for your feedback. I will try to do some calculations as you suggest, at least to know what ballpark we are likely to be in! That OnSemi document looks very useful - I will read it properly as soon as I get a moment. I'm not quite sure what you mean about the HC1G79. To give you more info, the CPLD buffers and proceses the digitial bitstream with the help of some SRAM and other ICs and then spits it out. The output is then buffered via a NOT gate to parallel NOT gates of the HC04 to provide enough drive for a pulse transformer (I now realise I should have mentioned the gates and the pulse transformer in the beginning, as they could also have a significant effect on jitter - I was more concerned about the CPLD initially). I've googled for HC1G79 but to no avail so far. JimArticle: 66754
----- -----
| 1 |-----------| 5 |--------------------|
----- ----- |
| |
----- | -----
| 2 |-------------- | 7 |
----- -----
|
----- ----- |
| 3 |-----------| 6 |--------------------|
----- -----
|
----- |
| 4 |--------------|
-----
I have 7 bins, called bin1, bin2,..., bin7. And 7 nodes called node1,
node2, ..., node7. Bin2 is adjacent to bin 1, bin3 is adjacent to
bin2, etc. The distance between bin2 and bin1 is 1, The distance
between bin7 and bin3 is 4, etc.
Each of the bins is to contain one node.
The nodes are connected as per the graph above, ie node1 is connected
only to node5, node5 is connected to nodes1,2,7. Etc.
The goal is to pack the nodes into these bins with the smallest TOTAL
length.
The nodes selection procedure would be a greedy process whereby
(1) the node which has the maximum connectivity would be selected
first and put in the centre bin;
(2) the next node selected must have been connected to the last node,
and be the one with the maximum connectivity. Repeat until all nodes
are in bins.
Write a generalised procedure to effectively pack the nodes into the
bins in order to achieve the minimum length.
Good luck!
Thanks,
Chris
Article: 66755Timothy Campbell wrote: > I am using Modelsim SE 5.8 to simulate cascaded DCMs. I have two DCMs > cascaded, the first with CLKIN running at 10Mhz. I am using the CLK2X of > the first as the CLKIN for the second DCM. The desired output is CLK2X > of the second DCM (I am trying to generate a 40Mhz clock from a 10Mhz > clock). When I simulate, I recieve the following warning: > > # ** Warning: Timing Violation Error : Input Clock Period Jitter on > instance * exceeds 0.001 ns Locked CLKIN Period = 0.1 ns Current CLKIN > Period = 0.3 ns > # Time: 675 ns Iteration: 2 Instance: /dcmtest224/xlxi_1037 > > I cannot get the second DCM to lock as well. Any suggestions would be > most appreciated. > > Best Regards, > T. Justin Campbell If you connect the inverted "lock" output from the first DCM to the reset input of the second one it will work fine, provided you are within the frequency range of the DCMs. --- jakabArticle: 66756
Iam using 2 process type FSM in my VHDL code the problem is the FSM is not working correctly , It hazards randomly when I checked the syntheizer reprt I founded that "Using one-hot encoding for signal <currentstate>" It automatically uses one hot techneque for the FSM Now , how can I force it to use "gray" type ?Article: 66757
Andrew Reilly <andrew@gurney.reilly.home> wrote in message news:<slrnc3qchh.1coi.andrew@gurney.reilly.home>... > On 25 Feb 2004 13:09:41 -0800, OP wrote: > > What is the difference between a hardware implementation of an > > algorithm and a software one. > > It's all hardware. If it's not hardware, it's not doing > anything (see question below). > > > How do you say an algorithm is faster in one and slower in other.. if > > it's based on timing how do you do that?? What makes it faster in one > > and not in other?? > > The faster one is the one that takes less time to do whatever > it was that you wanted done. This involves actually doing > the thing in question. Only hardware actually does stuff, > therefore, ipso facto, hardware is faster. > > As my Dad used to say: as fast as ten thousand gazebos. And what do you say if the native programming language for a cpu is very friendly to running event driven and parallel code such as Occam or better still HDL. Then you can write something like Verilog or HandelC on a cpu and call it HW at least for some types of apps that might actually be HW or SW. And you can take that same code or pieces of it and synth it into HW too with synthesis for some speedups if you know what you are doing. What would be the natural way for the HW(SW) to communicate with the SW(HW), probably messages at the interface between event scheduler and actual HW. occam made this sound easy, but HDL needs some thinking about.Article: 66758
Hi, I am trying to configure V2P7s with JTAG, but after the iMPACT tool says programming succeeded, the done pin remains low and all the outputs remain High. I have 8 V2P7s in parallel and they all the drive the same DONE line. What happens when we just program one of the 8 devices with JTAG in such a setup ? PLEASE HELP !!! Thanks in advance, AdarshArticle: 66759
Austin, I agree that performance claims will have to wait, but Jesse Kempa posted the LE results for a Nios softcore on Stratix I vs. II. The numbers showed just north of 30% fewer LE's used. Perhaps you (or someone else) could get your hands on an early version of Quartus II v4 and build some of your own designs and see for yourself. I'm sure everyone here would be interested in the results. Maybe someone from Altera would be willing to do it for you. It would be best for someone to use real world designs that they already have ported to both X and A. Ken "austin" <austin@xilinx.com> wrote in message news:c1jt6i$72u1@cliff.xsj.xilinx.com... > Michael, > > Thank you very much. I have read all of the publicly available > materials, and am still puzzled by the claims. > > Any claims of remarkable efficiency, you may understand, I am quite > leary of. For example, if the claim of a St2 50% speed improvement is > really true, then our demonstrated 40% speed improvement on average in > the i6.2 release makes St2 only 10% faster than our 2 year old V2 > Pro.....lowest speed grade. So leaving marketing to those who enjoy it, > I will forego any claims of performance, and just ask about architecture. > > I was unclear on just how a ALM is any different from drawing the box > differently around the components. I am still puzzled, but the block > diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it > was actually designed this way then that is simply what it is. A true 6 > LUT has 64 memory cells and the associated logic, and two of these seems > a bit excessive and would not require any other logic or muxes at all. > Combining existing 4 LUTs to deliver some of the possible terms of a 6 > LUT is a completely different matter. > > Regardless, it is enjoyable to hear about any radical or innovative new > architecture, as there are so many that now dot the landscape as dead > skeletons of past FPGAs. > > AustinArticle: 66760
"H.Azmi" <haythamazmi@hotmail.com> wrote in message news:34c5542c.0402260612.227ac1fa@posting.google.com... > > Now , how can I force it to use "gray" type ? This depends on the synthesizer you are using. Generally speaking, it can either be done through the synthesizer settings or via synthesizer attributes embedded in the VHDL code. Check your synthesizer's manual. /Mikhail -- To reply directly: matusov at square peg ca (join the domain name in one word and add a dot before "ca")Article: 66761
"Davka" <mygarbagepail@hotmail.com> wrote in message news:<W01%b.2$mA3.6454@news.uswest.net>... > Heh. Heheh. > > I learned APL when I was a kid. I love it too. It taught me respect for > languages that > don't have an implicit order of operations. > > I, too, have been programming in Forth for 20+ years. I wrote a multi-user > virtual > reality system that used byte-coded Forth to move virtual objects between > hosts > on the Internet. One of the things that struck me is that's it's less > awkward to write > long floating-point expressions multiplying sine and cosine terms in Forth > than it is in C. That's > why Forth came to mind as language for designing filters, etc. Also for > physical modeling > of musical instruments. It's easy to build up waveguides, etc into function > blocks that can > be strung together on the command line. *Everything* is better with an > interactive command > prompt. > > The scripting language for the virtual reality objects was Forth, but the > Forth interpreter itself was written in > plain-vanilla C for portability. It ran fast enough (on Pentium 90s with > software-only 3D rendering!) Hmmm...that reminds me quite a bit of the "Metatopia" project. http://metatopia.sourceforge.net/ http://www.immersive.com/ Do you still have the code? Are you doing anything with it? > My goals for asking about DSP and Forth processors: > > I'm teaching myself digital design and DSP. > > My first substantial FPGA project was a minimal instruction set 16-bit Forth > processor. It simulates at 90+ MIPS > in a small Altera Cyclone part. It uses about 800 LEs. Cool. You should get this added to Jeff Fox's "Forth chips" page. > And hardware for separating signals on the ham radio bands. And hardware to > develop multi-processing > ideas I've been toying with for years. Interesting. I do think that wireless processing are the "new frontier" for hardware hackers. I have scene a packat modem implemented in FPGA. I'll send you the link if you're interested. Jeff should be able to give you some info of multi-processing MISC since that's something he's worked on in the past and seems to be the focus of the latest Chuck work (25x). Regards, John M. DrakeArticle: 66762
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<KX7%b.2619$6k.0@newssvr27.news.prodigy.com>... > Have you consider just doing it the FPGA way? I haven't stopped to think > about what's required but you can certainly create building blocks in > hardware (say, filters). I wasn't aware that the "FPGA way" and a Forth processor were mutually exclusive. Certainly Forth CPUs have had DSPs built into them before. > Of course, an optimized Forth machine would/could make it very interactive > and fun to play with. Is there an implementation of Forth for PowerPC? Mops can generate PowerPC code. As for embedded PowerPC I was surprised that I didn't see a SwiftX or VFX implementation on their websites although both supported ColdFire. Regards, John M. DrakeArticle: 66763
Martin Euredjian wrote: > Chris Carlen wrote: > > >>I have a module test_delay8 that instantiates a module Delay8Bit, which >>in turn instantiates two further modules, an 8-bit comparator and an >>8-bit counter, where the counter is inferred from the XST library. >> >>But I get lots of warnings about inputs and signals not used: > > > <SNIP> > >>WARNING:Xst:647 - Input <Delay<7>> is never used. > > > Chris, > > I didn't have time to look at your code. I'll just offer a couple of > pointers here. > > The Xilinx tools will optimize away logic you are not using. In doing so, a > path that you thought was complete might endup without logic to connect to. > A warning will be issued to let you know. > > In general terms, take a look at your design and make sure that every single > signal contributes to physical chip outputs. That's the key. If a singnal, > say, the high bit of a counter, doesn't influence an output at all, the > tools will remove that flip-flop and anything else prior to that flip-flop > that does not add anything to the mix. > > I soft of doesn't make sense in the context of building out a design, when > you might not have all the blocks ready. It can be a real pain. One > approach is to put in dummy blocks that do something with signals you are > not using yet (a large AND function, for example, with the single output > assigned to a pin). Yeah, I gather what's happening is that it sees a constant applied to the input of some function, and reduces the logic. In the process, the input becomes superfluous. Thanks for the reply. Good day! -- ____________________________________ Christopher R. Carlen Principal Laser/Optical Technologist Sandia National Laboratories CA USA crcarle@sandia.govArticle: 66764
Hi:
I have a Verilog design for a Xilinx XPLA3 CPLD consisting of a toplevel
module that instantiates several other modules. I am developing in
WebPACK 5.2i.
The current design requires a single clock signal. I am supplying that
clock through one of the INn/CLKn inputs of the XPLA3 architecture.
Must I do anything special in the Verilog in order to ensure that the
clock is routed through the chip using the dedicated clock distribution
lines rather than through general purpose logic signal routing?
For instance, should I use BUF, BUFG, and/or BUFSR ?
Thanks for comments. Exerpts of my code shown below:
From myproj.ucf file:
NET "Clk10kHz" LOC = "p89"; <--- p89 is IN1/CLK1
NET "Vsync" LOC = "p79";
NET "InhReq" LOC = "p78";
NET "Inhibit" LOC = "p77";
NET "Grab" LOC = "p76";
From top level Verilog module:
module Cam_Inh_1(Vsync, InhReq, Inhibit, Grab, Clk10kHz);
input wire Vsync, InhReq, Clk10kHz;
output wire Inhibit, Grab;
wire inhibit_out, grab_out;
// In this instantiation of a sub-module, we just pass the clock along
Cam_Inh CameraInhibit1( .Vsync(~Vsync), .InhReq(~InhReq),
.Inhibit(inhibit_out),
.Grab(grab_out), .Clk10kHz(Clk10kHz) );
assign Inhibit = ~inhibit_out;
assign Grab = ~grab_out;
endmodule
The module "Cam_Inh" also passes the clock along to lower modules, where
it finally gets used in a counter.
--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov
Article: 66765Patrik <pclad.adr@firemail.de> wrote in message news:<opr3vqbzylhr4cxo@news.t-online.de>... > Hi, > > I try to program a JTAG chain with a MAX7064S and a MAX7032S via JTAG with > a microcontroller. The problem is, that I couldn't find the JTAG opcodes > for ISP. Is there any documentation about it? > > Thanks, > Patrik Hi Patrik, The way to program the MAX 7000S is by using Jam. Jam is a language for manipulating the JTAG chain - you can actually use it to do pretty much anything JTAG related, but it's optimized for programming CPLDs. The advantage is that the process of programming through JTAG is somewhat complicated, and this makes it quite easy. The basic idea is like this: 1. You use Quartus II (or MAX+PLUS II) to make the Jam file after compilation. 2. Altera supplies source code for the "Jam Player". You compile this for your microprocessor. 3. You load the Jam file into your system memory. 4. The microprocessor runs the Jam player, which reads the Jam file, and executes it. While executing, it manipulates the JTAG pins on the MAX device to program it. The Jam player can also verify the programming. There's a lot more detail behind this, so there's info on the Altera web site. This page has all the Jam downloads: https://www.altera.com/support/software/download/programming/jam/jam-index.jsp This app note gives general info about ISP (In-System Programming) for CPLDs. http://www.altera.com/literature/an/an095.pdf This app note gives more details about using Jam for ISP. http://www.altera.com/literature/an/an122.pdf Happy Programming! Greg Steinke gregs@altera.com Altera CorporationArticle: 66766
I am looking for a good, reasonably priced FPGA evaluation board for general development. Any good suggestions? My preference is to Xilinx. J.Article: 66767
If the done lines are wired in parallel then any un-configured device will drive DONE low. Probably a bit late now but it is always worth putting a jumper or zero ohm resistor from each of the FPGAs DONE connections so that you can isolate them individually if you need to. John Adair Enterpoint Ltd. This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Adarsh Kumar Jain" <Adarsh.Jain@cern.ch> wrote in message news:c1l0tn$6mi$1@sunnews.cern.ch... > Hi, > I am trying to configure V2P7s with JTAG, but after the iMPACT tool says > programming succeeded, the done pin remains low and all the outputs remain > High. > I have 8 V2P7s in parallel and they all the drive the same DONE line. > What happens when we just program one of the 8 devices with JTAG in such a > setup ? > PLEASE HELP !!! > Thanks in advance, > Adarsh > >Article: 66768
Kenneth, We noted that, and it is probably absolutely true. That would yield the same results that we already achieve with our present architecture because a 30% improvement is what is expected (and delivered) by the Virtex LUTs and mux wiring. I grant that they have now achieved parity in LUT usage with our two year old product. They have even improved its speed performance over their St1 by quite a bit, too. Good news for Altera customers. Austin Kenneth Land wrote: > Austin, > > I agree that performance claims will have to wait, but Jesse Kempa posted > the LE results for a Nios softcore on Stratix I vs. II. The numbers showed > just north of 30% fewer LE's used. > > Perhaps you (or someone else) could get your hands on an early version of > Quartus II v4 and build some of your own designs and see for yourself. I'm > sure everyone here would be interested in the results. Maybe someone from > Altera would be willing to do it for you. > > It would be best for someone to use real world designs that they already > have ported to both X and A. > > Ken > > "austin" <austin@xilinx.com> wrote in message > news:c1jt6i$72u1@cliff.xsj.xilinx.com... > >>Michael, >> >>Thank you very much. I have read all of the publicly available >>materials, and am still puzzled by the claims. >> >>Any claims of remarkable efficiency, you may understand, I am quite >>leary of. For example, if the claim of a St2 50% speed improvement is >>really true, then our demonstrated 40% speed improvement on average in >>the i6.2 release makes St2 only 10% faster than our 2 year old V2 >>Pro.....lowest speed grade. So leaving marketing to those who enjoy it, >>I will forego any claims of performance, and just ask about architecture. >> >>I was unclear on just how a ALM is any different from drawing the box >>differently around the components. I am still puzzled, but the block >>diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it >>was actually designed this way then that is simply what it is. A true 6 >>LUT has 64 memory cells and the associated logic, and two of these seems >>a bit excessive and would not require any other logic or muxes at all. >> Combining existing 4 LUTs to deliver some of the possible terms of a 6 >>LUT is a completely different matter. >> >>Regardless, it is enjoyable to hear about any radical or innovative new >>architecture, as there are so many that now dot the landscape as dead >>skeletons of past FPGAs. >> >>Austin > > >Article: 66769
Jim Granville <no.spam@designtools.co.nz> wrote in message news:<T9d%b.28459$ws.3202154@news02.tsnz.net>... > Michael, > Since you popped your head over the parapet... :) > > What's the story on MAX II Devices ?. There was glossary, timing > and lib files gradually appearing, and suddenly the Altera > web is cleansed and it's like MAX II is now 'off the radar' ?. > Would seem to indicate some problems..... > > -jg Hi Jim: Rest assured there are no problems. The www.altera.com site was refreshed; what you are experiencing is "housecleaning" on the site. MAX II data, lib files and documentation will be posted on altera.com when the product is launched - stay tuned. Luanne Schirrmeister -AlteraArticle: 66770
hi all currently I need to analize the FPGA configuration file....(for example, recent Xilinx or Altera device)........how it is organized... Could anybody point me out to the reference....or material thanks in advanceArticle: 66771
let me make one more inquiry what do you think...best textbook (or article or whatever) to understand the state of art FPGA architecture ? thanks againArticle: 66772
Memories of PREP, theidealistic but futile attempt at standardized benchmarks... I really do not like the marketing twist that this thread is taking. Xilinx had extra muxes for many years, Altera counters with more LUT bits, Xilinx explains that Altera shares LUT inputs and has congested routing,... and the spin goes on. In reality its a synthesis and routing software issue. I bet Altera can cook up an application where their LUTs look terrific, and Xilinx can conjure an application where the limited access just chokes the Altera LUTs. And who would be wiser ? Don't expect "gentleman-like" behavior from marketing, the stakes are too high. But let's at least keep this newsgroup somewhat gentleman-like... :-) Peter Alfke ============== Kenneth Land wrote: > > Austin, > > I agree that performance claims will have to wait, but Jesse Kempa posted > the LE results for a Nios softcore on Stratix I vs. II. The numbers showed > just north of 30% fewer LE's used. > > Perhaps you (or someone else) could get your hands on an early version of > Quartus II v4 and build some of your own designs and see for yourself. I'm > sure everyone here would be interested in the results. Maybe someone from > Altera would be willing to do it for you. > > It would be best for someone to use real world designs that they already > have ported to both X and A. > > Ken > > "austin" <austin@xilinx.com> wrote in message > news:c1jt6i$72u1@cliff.xsj.xilinx.com... > > Michael, > > > > Thank you very much. I have read all of the publicly available > > materials, and am still puzzled by the claims. > > > > Any claims of remarkable efficiency, you may understand, I am quite > > leary of. For example, if the claim of a St2 50% speed improvement is > > really true, then our demonstrated 40% speed improvement on average in > > the i6.2 release makes St2 only 10% faster than our 2 year old V2 > > Pro.....lowest speed grade. So leaving marketing to those who enjoy it, > > I will forego any claims of performance, and just ask about architecture. > > > > I was unclear on just how a ALM is any different from drawing the box > > differently around the components. I am still puzzled, but the block > > diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it > > was actually designed this way then that is simply what it is. A true 6 > > LUT has 64 memory cells and the associated logic, and two of these seems > > a bit excessive and would not require any other logic or muxes at all. > > Combining existing 4 LUTs to deliver some of the possible terms of a 6 > > LUT is a completely different matter. > > > > Regardless, it is enjoyable to hear about any radical or innovative new > > architecture, as there are so many that now dot the landscape as dead > > skeletons of past FPGAs. > > > > AustinArticle: 66773
In article <103s244a4ugb899@news.supernews.com>, Kenneth Land <kland1@neuralog1.com1> wrote: >Austin, > >I agree that performance claims will have to wait, but Jesse Kempa posted >the LE results for a Nios softcore on Stratix I vs. II. The numbers showed >just north of 30% fewer LE's used. Considering the impressive design mapping required in the NIOS 2 (the FPGA talk on the subject was VERY-cool), how much redesign was done/needed for Stratix II? Or is this Nios 1.1? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 66774
On a sunny day (Thu, 26 Feb 2004 09:59:07 GMT) it happened "p" <chaosdynasty@hotmail.com> wrote in <Lrj%b.619427$X%5.315413@pd7tw2no>: >By the way, if anyone wants the SM specifications, I can put them on my site >for download Yes please. JP
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