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Messages from 66775

Article: 66775
Subject: Re: JTAG Opcodes for Altera MAX7000S
From: Patrik <pclad.adr@firemail.de>
Date: Thu, 26 Feb 2004 18:53:01 +0100
Links: << >>  << T >>  << A >>
Hi Greg,

the problem is, that I have to program the devices with a microcontroler, 
not an embedded Processor. Therefor I cannot use the JAM language, because 
the JAM Interpreter wouldn't compile on an microcontroler (maybe a ATMEL, 
it's not decisioned, yet).

Thanks,
Patrik

Article: 66776
Subject: Re: Done Pin Remains Low after JTAG Configuration of V2Pro
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Thu, 26 Feb 2004 10:18:45 -0800
Links: << >>  << T >>  << A >>

Did you set the configuration startup clock to
the JTAG clock (versus the default value, which
is CCLK?)

Eric

Adarsh Kumar Jain wrote:
> 
> Hi,
> I am trying to configure V2P7s with JTAG, but after the iMPACT tool says
> programming succeeded, the done pin remains low and all the outputs remain
> High.
> I have 8 V2P7s in parallel and they all the drive the same DONE line.
> What happens when we just program one of the 8 devices with JTAG in such a
> setup ?
> PLEASE HELP !!!
> Thanks in advance,
> Adarsh

Article: 66777
Subject: Re: VHDL FSM Problem
From: =?iso-8859-1?Q?Michael_Sch=F6berl?= <MSchoeberl@ratnet.stw.uni-erlangen.de>
Date: Thu, 26 Feb 2004 19:22:52 +0100
Links: << >>  << T >>  << A >>
> Now , how can I force it to use "gray" type ?

I'm quite sure that this will NOT solve the problem ...


check the following:

- all inputs to the state machine must be synchronous to 
the clock ... that means they must be registered with the
same clock before they are used inside ... 

- the timing-constraints are correct and met 



bye,
Michael


Article: 66778
Subject: Re: Suggestions: Eval/Demo Board.
From: "kyokpae acn" <kyokpae@acn.waw.pl>
Date: Thu, 26 Feb 2004 19:27:25 +0100
Links: << >>  << T >>  << A >>
Hi,

> I am looking for a good, reasonably priced FPGA evaluation board for
general
> development.  Any good suggestions?
>
> My preference is to Xilinx.


        Check this one then ->
http://www.nuhorizons.com/services/development/Xilinx/SpartanIIE/SpartanIIEB
oard.html

greetings!
kyokpae



Article: 66779
Subject: Re: Automatic Placement algorithm, help needed
From: p.black@acm.org (Paul E. Black)
Date: 26 Feb 2004 13:36:22 -0500
Links: << >>  << T >>  << A >>
chjones@dacafe.com (Chris Jones) writes:

> I have 7 bins, called bin1, bin2,..., bin7. And 7 nodes called node1,
> node2, ..., node7. Bin2 is adjacent to bin 1, bin3 is adjacent to
> bin2, etc. The distance between bin2 and bin1 is 1, The distance
> between bin7 and bin3 is 4, etc.
> 
> Each of the bins is to contain one node.
> 
> The goal is to pack the nodes into these bins with the smallest TOTAL
> length.

Maybe a Huffman coding-like procedure would work better.  Huffman
coding tends to optimize clusters, letting the root take care of
itself.  Perhaps: pick those *farthest* from the root and cluster (lay
out) those.  Then lay out the clusters, etc.

I think the example you gave, with seven nodes in a balanced tree,
won't demonstrate the relative merits of some assignment schemes.

-paul-
-- 
Paul E. Black (p.black@acm.org)

Article: 66780
Subject: Re: one more inquiry....fpga architecture
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 26 Feb 2004 11:01:21 -0800
Links: << >>  << T >>  << A >>
The most up-to-date information is always at the vendors' websites.
Any printed book is unavoidably several years behind...
Thisa is a fast-moving technology.
Peter Alfke
======================
hurjy wrote:
> 
> let me make one more inquiry
> 
> what do you think...best textbook (or article or whatever) to understand the
> state of art FPGA architecture ?
> 
> thanks again

Article: 66781
(removed)


Article: 66782
Subject: Re: Suggestions: Eval/Demo Board.
From: "Manfred Kraus" <makra7960@tiscali.de>
Date: Thu, 26 Feb 2004 20:13:42 +0100
Links: << >>  << T >>  << A >>
You might also check:

http://www.fpga-karten.de/english/indexenglish.htm

Sorry, could nor resist.
-Manfred

"Invisible One" <Invisible_1@sympatico.ca> wrote in message
news:9Gp%b.15349$Mo4.529748@news20.bellglobal.com...
> I am looking for a good, reasonably priced FPGA evaluation board for
general
> development.  Any good suggestions?
>
> My preference is to Xilinx.
>
> J.
>
>



Article: 66783
Subject: Re: Stratix 2 ALUT architecture patented ?
From: "Kenneth Land" <kland1@neuralog1.com1>
Date: Thu, 26 Feb 2004 13:16:59 -0600
Links: << >>  << T >>  << A >>

Hi Peter,

I was suggesting that the engineers on this group *bypass* the marketing
groups of A and X and post how *their* designs map between the new choices.

Or are the people in this thread the marketing people you're warning us
about.  I'm too new to know better.  I know (of) you and that you're with X,
but not the others.

Sure someone could intentionally mislead, but I'd at least like to know how
some typical fpga group reader's design(s) mapped onto the latest offerings.

I know you could trust my designs, because I don't know enough to tweak them
for X or A.  I'll bet there are many others who don't tweak designs to that
level either. (probably for better reasons :)

Ken


"Peter Alfke" <peter@xilinx.com> wrote in message
news:403E2BA6.AE630B1F@xilinx.com...
> Memories of PREP, theidealistic but futile attempt at standardized
benchmarks...
> I really do not like the marketing twist that this thread is taking.
>
> Xilinx had extra muxes for many years, Altera counters with more LUT
> bits, Xilinx explains that Altera shares LUT inputs and has congested
> routing,... and the spin goes on.
> In reality its a synthesis and routing software issue.
>
> I bet Altera can cook up an application where their LUTs look terrific,
> and Xilinx can conjure an application where the limited access just
> chokes the Altera LUTs. And who would be wiser ?
>
> Don't expect "gentleman-like" behavior from marketing, the stakes are
> too high.
> But let's at least keep this newsgroup somewhat gentleman-like... :-)
> Peter Alfke
> ==============
> Kenneth Land wrote:
> >
> > Austin,
> >
> > I agree that performance claims will have to wait, but Jesse Kempa
posted
> > the LE results for a Nios softcore on Stratix I vs. II.  The numbers
showed
> > just north of 30% fewer LE's used.
> >
> > Perhaps you (or someone else) could get your hands on an early version
of
> > Quartus II v4 and build some of your own designs and see for yourself.
I'm
> > sure everyone here would be interested in the results.  Maybe someone
from
> > Altera would be willing to do it for you.
> >
> > It would be best for someone to use real world designs that they already
> > have ported to both X and A.
> >
> > Ken
> >
> > "austin" <austin@xilinx.com> wrote in message
> > news:c1jt6i$72u1@cliff.xsj.xilinx.com...
> > > Michael,
> > >
> > > Thank you very much.  I have read all of the publicly available
> > > materials, and am still puzzled by the claims.
> > >
> > > Any claims of remarkable efficiency, you may understand, I am quite
> > > leary of.  For example, if the claim of a St2 50% speed improvement is
> > > really true, then our demonstrated 40% speed improvement on average in
> > > the i6.2 release makes St2 only 10% faster than our 2 year old V2
> > > Pro.....lowest speed grade.  So leaving marketing to those who enjoy
it,
> > > I will forego any claims of performance, and just ask about
architecture.
> > >
> > > I was unclear on just how a ALM is any different from drawing the box
> > > differently around the components.  I am still puzzled, but the block
> > > diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if
it
> > > was actually designed this way then that is simply what it is.  A true
6
> > > LUT has 64 memory cells and the associated logic, and two of these
seems
> > > a bit excessive and would not require any other logic or muxes at all.
> > >   Combining existing 4 LUTs to deliver some of the possible terms of a
6
> > > LUT is a completely different matter.
> > >
> > > Regardless, it is enjoyable to hear about any radical or innovative
new
> > > architecture, as there are so many that now dot the landscape as dead
> > > skeletons of past FPGAs.
> > >
> > > Austin



Article: 66784
Subject: Re: Altera ACEX chip wide reset
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 26 Feb 2004 14:21:38 -0500
Links: << >>  << T >>  << A >>
Martin Thompson wrote:
> 
> gregs@altera.com (Greg Steinke) writes:
> 
> > Martin Thompson <martin.j.thompson@trw.com> wrote in message news:<uishvxwee.fsf@trw.com>...
> > > gregs@altera.com (Greg Steinke) writes:
> > > <snip>
> > > > Rick,
> > > >
> > > > When the ACEX device is initialized after configuration, or when you
> > > > assert the Chip Wide Reset, the FFs are all set to 0. There are two
> > > > ways of achieving your goal of having an FF power up to 1.
> > > >
> > > > 1. You can code the VHDL so that you end up with a NOT gate before the
> > > > D of the FF, and another NOT gate after the Q of the FF. Any logic
> > > > that the FF drives would actually be driven by the NOT gate in the
> > > > HDL. When the FF powers up at 0, it will appear as 1 by the rest of
> > > > the logic. But in normal operation, the double-negation will have no
> > > > effect. You'll have to be careful with simulation however, since the
> > > > FF's value will be the opposite of what you expect. This works in
> > > > MAX+PLUS II or Quartus II as it's simply an HDL code.
> > > >
> > >
> > > IIRC the 10K, on which the 1K is based, cannot do a preset without NOT
> > > gates anyway, irrespective of whether it's a chip-side reset, or not.
> > > If you write an aync reset clause that initialises something to a '1',
> > > Synplify (at least) will put the appropriate NOT gates in for you.
> > > Which will then hammer your tco for any pins you want to default to a
> > > '1' - like ooh, maybe a chip-select....  Not that I bear the scars or
> > > anything :-)
> >
> <snip>
> > Martin,
> > The ACEX 1K (and FLEX 10K) LE has an async clear and an async load. An
> > async preset could be implemented by the NOT technique or by using the
> > async load. A design that uses just the preset will generally end up
> > using the NOT technique, whereas a design that uses a preset and a
> > clear will use the async load technique.
> >
> 
> True - my memory was only of the IOEs.  However, if you want a preset,
> you have to sacrifice DATA3 in the LUT according to my datasheet (as
> implicated by the use of the term "load" rather than "preset").  I
> knew I'd recalled something about presets not being quite as "free" as
> resets :-)
> 
> > The IO Element has a programmable inversion in it to accomodate the
> > NOT technique. So for example if an LE register drives a pin, and the
> > design calls for the register to be async preset, the compiler will
> > use the NOT technique and implement the after-register NOT in the IOE.
> > However, the best tCO is obtained by using the IOE register, and the
> > programmable inversion is before the D of the IOE register. So there
> > is no way to implement an async preset in the IOE, which is probably
> > the reason for the tCO pushout that you saw - the register was moved
> > into an LE which increases tCO.
> >
> > If you see a design where an async-preset LE drives a pin, and there's
> > an extra LE put into the path to implement the NOT gate, this is a bug
> > and should be reported to Altera and/or Synplicity. But I'll bet that
> > the tCO pushout is due to the register moving from the IOE to the LE.
> >
> 
> Yes, that is what was happening - it was a while ago, I remember now!
> What happens to the power-up (not reset) behaviour?  Does it still
> power up low until the reset occurs?

The data sheet is one thing.  But I was asking about how to get the FF
to use whatever is available.  From what I read in the data sheet, it
looks like a preset can be done by putting a 1 on DATA3.  This will also
become part of the power on reset as well as the reset pin function. 
But it also appears that to use it I have to provide an async set in my
code separate from the global reset.  

Either way this does not look good.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 66785
Subject: Re: Stratix 2 ALUT architecture patented ?
From: sense_1909S_VDB@yahoo.com (google_guy)
Date: 26 Feb 2004 11:22:32 -0800
Links: << >>  << T >>  << A >>
austin <austin@xilinx.com> wrote in message news:<c1jt6i$72u1@cliff.xsj.xilinx.com>...
> Michael,
> 
> Thank you very much.  I have read all of the publicly available 
> materials, and am still puzzled by the claims.
> 
> Any claims of remarkable efficiency, you may understand, I am quite 
> leary of.  

I can understand why.  The way that Xilinx twists facts in their data
sheets would certainly lead them to expect that of everyone.  Just how
many LCs *do* your parts have???


> For example, if the claim of a St2 50% speed improvement is 
> really true, then our demonstrated 40% speed improvement on average in 
> the i6.2 release makes St2 only 10% faster than our 2 year old V2 
> Pro.....lowest speed grade.  So leaving marketing to those who enjoy it, 
> I will forego any claims of performance, and just ask about architecture.

What kind of gobbledygook is that?  Correct me if I am wrong, but your
V2 is the newest and fastest parts you have, right?  Certanly you
can't tout the Spartan 3 since not many people have even seen them and
they are much slower than most people would have expected given a 90
nm process.

And exactly how do you get a 40% speed advantage over anything with
your software?  Do you have benchmarks to back that up?


> I was unclear on just how a ALM is any different from drawing the box 
> differently around the components.  I am still puzzled, but the block 
> diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it 
> was actually designed this way then that is simply what it is.  A true 6 
> LUT has 64 memory cells and the associated logic, and two of these seems
> a bit excessive and would not require any other logic or muxes at all. 
>   Combining existing 4 LUTs to deliver some of the possible terms of a 6 
> LUT is a completely different matter.

I don't follow this.  Are you saying their approach is good or bad? 
If you are saying it is good, then you are agreeing with them.  If you
are saying it is bad, aren't you also saying it is just like yours?  I
guess the patents will tell all.

 
> Regardless, it is enjoyable to hear about any radical or innovative new 
> architecture, as there are so many that now dot the landscape as dead 
> skeletons of past FPGAs.

Yes, and some of those are in a unmarked grave out behind your
facility, no?  What was that company name... was it Plus Logic?  How
about NeoCAD?  What are the others... ?

Article: 66786
Subject: Re: Dual-stack (Forth) processors
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 26 Feb 2004 14:25:11 -0500
Links: << >>  << T >>  << A >>
jmdrake wrote:
> 
> "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<KX7%b.2619$6k.0@newssvr27.news.prodigy.com>...
> 
> > Have you consider just doing it the FPGA way?  I haven't stopped to think
> > about what's required but you can certainly create building blocks in
> > hardware (say, filters).
> 
> I wasn't aware that the "FPGA way" and a Forth processor were mutually
> exclusive.  Certainly Forth CPUs have had DSPs built into them before.
> 
> > Of course, an optimized Forth machine would/could make it very interactive
> > and fun to play with.  Is there an implementation of Forth for PowerPC?
> 
> Mops can generate PowerPC code.  As for embedded PowerPC I was surprised
> that I didn't see a SwiftX or VFX implementation on their websites
> although both supported ColdFire.

I believe that is because both companies are reactive rather than
proactive.  They port to a new platform when they are paid to do it. 
They don't speculate on their own dime.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 66787
Subject: Re: Stratix 2 ALUT architecture patented ?
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 26 Feb 2004 11:47:57 -0800
Links: << >>  << T >>  << A >>
Guy?

Comments below.


google_guy wrote:
> austin <austin@xilinx.com> wrote in message news:<c1jt6i$72u1@cliff.xsj.xilinx.com>...
> 
>>Michael,
>>
>>Thank you very much.  I have read all of the publicly available 
>>materials, and am still puzzled by the claims.
>>
>>Any claims of remarkable efficiency, you may understand, I am quite 
>>leary of.  
> 
> 
> I can understand why.  The way that Xilinx twists facts in their data
> sheets would certainly lead them to expect that of everyone.  Just how
> many LCs *do* your parts have???
Easy, just look at how many LUTs there are in the data sheet.  You can 
inflate the naw numbers any way you like, as opposed to using our "rules."
> 
> 
> 
>>For example, if the claim of a St2 50% speed improvement is 
>>really true, then our demonstrated 40% speed improvement on average in 
>>the i6.2 release makes St2 only 10% faster than our 2 year old V2 
>>Pro.....lowest speed grade.  So leaving marketing to those who enjoy it, 
>>I will forego any claims of performance, and just ask about architecture.
> 
> 
> What kind of gobbledygook is that?  Correct me if I am wrong, but your
> V2 is the newest and fastest parts you have, right?  Certanly you
> can't tout the Spartan 3 since not many people have even seen them and
> they are much slower than most people would have expected given a 90
> nm process.
V2Pro is the latest production avaliable offering in 130 nm.
> 
> And exactly how do you get a 40% speed advantage over anything with
> your software?
By being more clever than we were one year ago.
   Do you have benchmarks to back that up?
Yes.  Contyact your FAE and they will be delighted to show you the 
benchmarks of over 200 large actual customer designs that we have in our 
tool test suite.
> 
> 
> 
>>I was unclear on just how a ALM is any different from drawing the box 
>>differently around the components.  I am still puzzled, but the block 
>>diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it 
>>was actually designed this way then that is simply what it is.  A true 6 
>>LUT has 64 memory cells and the associated logic, and two of these seems
>>a bit excessive and would not require any other logic or muxes at all. 
>>  Combining existing 4 LUTs to deliver some of the possible terms of a 6 
>>LUT is a completely different matter.
> 
> 
> I don't follow this.  Are you saying their approach is good or bad?
Neither.  It just looked at first glance that they had some muxes (just 
like we do).  That they have a more direct LUT/MUX/LUT path which is 
faster may be true, and that would be good.

> If you are saying it is good, then you are agreeing with them.
Hey, what is wrong with that?  Yes, it is good.
   If you
> are saying it is bad, aren't you also saying it is just like yours?  I
> guess the patents will tell all.
> 
>  
> 
>>Regardless, it is enjoyable to hear about any radical or innovative new 
>>architecture, as there are so many that now dot the landscape as dead 
>>skeletons of past FPGAs.
> 
> 
> Yes, and some of those are in a unmarked grave out behind your
> facility, no?
Yes.
   What was that company name... was it Plus Logic?  How
> about NeoCAD?  What are the others... ?
I will let you tell us.

Article: 66788
Subject: Re: altera, xilinx susceptible to power transients?
From: visualfor@yahoo.com (Naveed)
Date: 26 Feb 2004 11:48:55 -0800
Links: << >>  << T >>  << A >>
Andraka,

There is no amount of capacitors that will save me from the
transients.  My FPGA 1.5V supply share the same ground as programmable
0-800V power supply (different planes but connected).  So if some body
touches the 800V power supply with a probe for measurement, it creates
spikes all over. You can reduce them, but not completely eliminate
them.

If I did not have ceramics (in decades) all over, then these spikes
would have been 2-3V at the FPGA, but they are about 1V now.

We don't mind these transients, as these boards will not be probed in
actual use.

But if that was not the case, then I would have done one of the
followings:
1.  Isolate the digital and power supplies (expensive option)
2.  Use a 5 or 3.3V core logic, and use expensive filtering scheme for
Core supply (including inductors)

Thanks,

Naveed


Ray Andraka <ray@andraka.com> wrote in message 
> 5-10ns is a very narrow spike on the power, which should be caught mostly by your power supply bypassing.
> It is quite possible you have insufficient power supply bypassing on your board which is causing upsets or
> false clock transitions due to the narrow transients.  Try it with much slower changes in the supply
> voltage, you'll see then that the chip continues to operate (although it slows down) as power is reduced
> until the reconfiguration reset trips.
> 
>

Article: 66789
Subject: Re: Inquiry on configuration file analysis
From: PO Laprise <pl_N0SP4M_apri@cim._N0SP4M_mcgill.ca>
Date: Thu, 26 Feb 2004 19:51:35 GMT
Links: << >>  << T >>  << A >>
hurjy wrote:
> hi all
> 
> currently I need to analize the FPGA configuration file....(for example,
> recent Xilinx or Altera device)........how it is organized...
> 
> Could anybody point me out to the reference....or material
> 
> thanks in advance
> 

I know for a fact that Xilinx's "Virtex-II Platform FPGA User Guide" 
(UG002, not to be confused with the datasheet, which is DS031) contains 
a good amount of detail on that device's configuration in the 
Configuration->Configuration Details section, and I suppose that the 
guides for their other devices have the same type of info.  Also look 
for xapp151, which covers the Virtex family configuration architecture, 
which is similar to the Virtex-II, Spartan-II and Spartan-III 
architectures.  Unfortunately (for the curious and anal amongst us ;), 
some of the details haven't been made public (or hadn't when I last 
looked at this stuff), I suppose for IP protection reasons.  I don't 
know about Altera devices, sorry.

-- 
Pierre-Olivier

-- to email me directly, remove all _N0SP4M_ from my address --


Article: 66790
Subject: Re: Altera ACEX chip wide reset
From: Jim Granville <no.spam@designtools.co.nz>
Date: Fri, 27 Feb 2004 09:23:35 +1300
Links: << >>  << T >>  << A >>
Greg Steinke wrote:
<snip>
> You will be happy to know that we have enhanced the IOE registers of
> the Stratix and Cyclone FPGAs. In these devices, you can choose to
> have an async clear or async preset on an IOE. This is selectable per
> IOE. Furthermore, an IOE register that uses the async preset will
> power up high. Perfect for your active-low chip select.
> 
> For the second question -
> In ACEX 1K FPGAs, on the silicon level, the chip-wide reset sets all
> the registers to zero. The NOT technique that I proposed simply
> modifies the LUT that feeds the register, and the LUTs that the
> register feeds, to add the NOT gates. 

  One small detail - on these Async resets, how is reset recovery
( trailing edge of ASYNC RST, to any appearing Clocks ) handled inside 
the device ?

-jg


Article: 66791
Subject: Re: Altera ACEX chip wide reset
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 26 Feb 2004 15:40:01 -0500
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> 
> Greg Steinke wrote:
> <snip>
> > You will be happy to know that we have enhanced the IOE registers of
> > the Stratix and Cyclone FPGAs. In these devices, you can choose to
> > have an async clear or async preset on an IOE. This is selectable per
> > IOE. Furthermore, an IOE register that uses the async preset will
> > power up high. Perfect for your active-low chip select.
> >
> > For the second question -
> > In ACEX 1K FPGAs, on the silicon level, the chip-wide reset sets all
> > the registers to zero. The NOT technique that I proposed simply
> > modifies the LUT that feeds the register, and the LUTs that the
> > register feeds, to add the NOT gates.
> 
>   One small detail - on these Async resets, how is reset recovery
> ( trailing edge of ASYNC RST, to any appearing Clocks ) handled inside
> the device ?

It's not, just like any other async reset.  You need to either provide a
sync reset to critical logic or design it so that it has a couple of
post reset states that only vary by one FF, like a gray code.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 66792
Subject: Re: Free PCI-bridge in VHDL for Spartan-IIE
From: Sander Vesik <sander@haldjas.folklore.ee>
Date: Thu, 26 Feb 2004 20:41:08 +0000 (UTC)
Links: << >>  << T >>  << A >>
Kevin Brace <k0evinbr1ace@m2ail.c3om> wrote:
>         The $100 PCI IP core license is intended for hobbyists, FPGA
> enthusiasts, Verilog learners, and students who want to make their own
> PCI device for personal use.
> I believe there are potentially several hundred people in the US who are
> willing to pay $100 for the license.
> It is my perception that people who do research can probably pay more
> than a personal user, so I feel like I should charge more for a license
> than a personal user.
> If cost is that much of an issue, ask Xilinx because I read in this
> newsgroup while back that they do sometimes donate their PCI IP core to
> educational institutions.
> I just don't intend to compete with a free one.

anyways, its up to you what you do. Seeing a marketplace of non-mass 
production IP cores emerge would ceertainly be nice.

> 
> 
> Kevin Brace
> 

-- 
	Sander

+++ Out of cheese error +++

Article: 66793
Subject: Re: Basic jitter from a CPLD (XC7500XL)
From: Jim Granville <no.spam@designtools.co.nz>
Date: Fri, 27 Feb 2004 09:56:45 +1300
Links: << >>  << T >>  << A >>
Jim wrote:
> Thanks Jim for your feedback. I will try to do some calculations as you
> suggest, at least to know what ballpark we are likely to be in! That OnSemi
> document looks very useful - I will read it properly as soon as I get a
> moment.
> 
> I'm not quite sure what you mean about the HC1G79. To give you more info,
> the CPLD buffers and proceses the digitial bitstream with the help of some
> SRAM and other ICs and then spits it out. The output is then buffered via a
> NOT gate to parallel NOT gates of the HC04 to provide enough drive for a
> pulse transformer (I now realise I should have mentioned the gates and the
> pulse transformer in the beginning, as they could also have a significant
> effect on jitter - I was more concerned about the CPLD initially).

When you use the slew model, you can appreciate any pulse transformer ( 
with its slow slew rates ) will likely have a big effect on jitter.

  Why is the transformer there, and do you work on both sides of it
- ie is the RX side your design ? Some care will be needed there,
to both keep Tsu/Th ok, and to minimise clock path degrade.

 >I've googled for HC1G79 but to no avail so far.

http://www.philipslogic.com/products/picogate/flipflops/

-jg


Article: 66794
Subject: Re: altera, xilinx susceptible to power transients?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 26 Feb 2004 16:00:27 -0500
Links: << >>  << T >>  << A >>
My point is that the narrow transients you are seeing are not something normally seen on a properly designed
circuit board.  They are not sufficient to trip the reconfiguration but are sufficient to mess up state in the
FPGA.  Question: are you seeing the FPGA lose part of its configuration, or are you just seeing upset of the
user circuit state (in which case a reset of the logic without reconfiguring would fix it)?  Good chance it is
the latter, not the former based on your description of the crummy power rails.  If you are concerned about this
(sounds like perhaps you are not), then better isolation from that 800v supply is the only answer.

Naveed wrote:

> Andraka,
>
> There is no amount of capacitors that will save me from the
> transients.  My FPGA 1.5V supply share the same ground as programmable
> 0-800V power supply (different planes but connected).  So if some body
> touches the 800V power supply with a probe for measurement, it creates
> spikes all over. You can reduce them, but not completely eliminate
> them.
>
> If I did not have ceramics (in decades) all over, then these spikes
> would have been 2-3V at the FPGA, but they are about 1V now.
>
> We don't mind these transients, as these boards will not be probed in
> actual use.
>
> But if that was not the case, then I would have done one of the
> followings:
> 1.  Isolate the digital and power supplies (expensive option)
> 2.  Use a 5 or 3.3V core logic, and use expensive filtering scheme for
> Core supply (including inductors)
>
> Thanks,
>
> Naveed
>
> Ray Andraka <ray@andraka.com> wrote in message
> > 5-10ns is a very narrow spike on the power, which should be caught mostly by your power supply bypassing.
> > It is quite possible you have insufficient power supply bypassing on your board which is causing upsets or
> > false clock transitions due to the narrow transients.  Try it with much slower changes in the supply
> > voltage, you'll see then that the chip continues to operate (although it slows down) as power is reduced
> > until the reconfiguration reset trips.
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 66795
Subject: Re: Why warnings: "Input <xyz> never used???"
From: Kevin Brace <k0evinbr1ace@m2ail.c3om>
Date: Thu, 26 Feb 2004 15:02:21 -0600
Links: << >>  << T >>  << A >>
Hi Chris,

It's off topic, and it is probably none of my business to suggest (I
almost used the word "criticize," but I instead used "suggest," so that
you won't feel offended.), but why instantiate a vendor specific library
primitive and Verilog gate primitives when you don't have to?
These are the two examples I am talking about.
______________________________________________________________________
FDC FF1 ( .Q(Out), .C(Trig_in), .CLR(CompMatchOut), .D(h) );

______________________________________________________________________


        Why instantiate an FDC?
You should be able to replace it with the following code (Assuming that
what I am doing is correct), and the synthesis tool should infer you an
FDC.

______________________________________________________________________
reg Out;

always @ (posedge Trig_in or posedge CompMatchOut) begin

    if (CompMatchOut == 1'b1) begin
        Out  <= 1'b0;

    end
    else begin
        Out  <= h;

    end
end
______________________________________________________________________


______________________________________________________________________
module Compare8(Q, A, B);
   output wire Q;
   input wire [7:0] A;
   input wire [7:0] B;

   wire X7, X6, X5, X4, X3, X2, X1, X0;

   xnor
     XNOR7 (X7, A[7], B[7]),
     XNOR6      (X6, A[6], B[6]),
     XNOR5      (X5, A[5], B[5]),
     XNOR4      (X4, A[4], B[4]),
     XNOR3      (X3, A[3], B[3]),
     XNOR2      (X2, A[2], B[2]),
     XNOR1      (X1, A[1], B[1]),
     XNOR0      (X0, A[0], B[0]);

   and (Q, X7, X6, X5, X4, X3, X2, X1, X0);

endmodule
______________________________________________________________________


        Also, why instantiate Verilog gate primitives when you should be
able to do the same thing for less code?
______________________________________________________________________
module Compare8(Q, A, B);
   output Q;
   input[7:0] A;
   input[7:0] B;

   assign Q = (A[7:0] == B[7:0]);

endmodule
______________________________________________________________________



        I believe those two changes I made are correct, but you will
have to make sure that they work correctly.


Kevin Brace

Article: 66796
Subject: Re: one more inquiry....fpga architecture
From: "fabbl" <nospam@nospam.com>
Date: Thu, 26 Feb 2004 21:10:59 GMT
Links: << >>  << T >>  << A >>
Another place is through the distributers of the parts themselves (Insight,
Avnet etc.) Usually they have a heads-up on new products as well as market
direction that drives them.



Article: 66797
Subject: Re: VHDL FSM Problem
From: pascal <>
Date: Thu, 26 Feb 2004 13:26:55 -0800
Links: << >>  << T >>  << A >>
You might also want to check the clock integrity. double edges can wreck havoc 
with one-hot fsms (the bit at '1' gets cleared but doesn't offer enough setup 
time for the next bit to get set, so one-hot is at all 0s). 


Article: 66798
Subject: Suggestions
From: cvmnk@yahoo.com (naveen)
Date: 26 Feb 2004 13:33:40 -0800
Links: << >>  << T >>  << A >>
Hi all,

Im a fresh graduate from wright state university, OHIO, USA. My
master's degree concentrated towards VLSI designing(3.9 GPA). I really
want to build my career on FPGA Design, Testing and Fault tolerance.
My course structure concentrated on all VLSI/digital design aspects
and VHDL, Verilog programming languages, B square logic which
compliments FPGA designing. One of my courses directly dealt working
with Xilinx based XC2V100 FPGA chip and implementing two real time
projects(GPP-general purpose processor and change making machine).

I was involved in an individual project where I have done extensive
research on different Diagnosis and Fault Tolerance techniques such as
Roving stars, Low Overhead FT, Incremental Routing for xilinx based
FPGA's and "Roving stars" method was adopted and comprehensive
coverage for different faults were verified. I can mail you the paper.

I'd like to know if there's any openings(full time or co-op) in this
field or any suggestions i can get regarding any companies where i can
apply for fpga design and fault tolerance. I know its really difficult
to get a job. If you want I can send my resume.

regards,
Naveen

Article: 66799
Subject: DPRAM design issue
From: ianwyb@yahoo.com (ian)
Date: 26 Feb 2004 13:36:53 -0800
Links: << >>  << T >>  << A >>
hi, Folks,
I have a dual port RAM with the same width at both side, which is
32bit. However, the data in at A side is only 16 bit wide. So in order
to pass the data in and fill the RAM entry, i need to use some wrapper
logic (mux?) to pass data in to fill the upper and lower 16 bits in
one address of the DRAM in two consequtive clock cycles. Therefore as
issue of testablity arises, since the mux logic is not insertable in
terms of scan flops. also I have to introduce a clock cycle latency
into the A side to fill up the  32 bit entry. Are there any nice
tricks to avoid both of the problems? (of course without changing the
DPRAM.)
Thanks in advance

Ian



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