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Messages from 88400

Article: 88400
Subject: Re: Easy USB2.0 hi-speed device solutions ?
From: Alex <al.lopich@gmail.com>
Date: Wed, 17 Aug 2005 14:39:44 +0100
Links: << >>  << T >>  << A >>
Hi, I am not sure if there will be any cheaper solutions but check
www.opalkelly.com, they might have some stuff you need. Also it might be  
an alternative way
to build such system yourself with chips from Cypress or FTDI, as they  
provide with all necessary drivers and so on.
Regards


-- 
Alex

Article: 88401
Subject: Re: Evolutionary VHDL code example
From: "Eric" <ericjohnholland@hotmail.com>
Date: 17 Aug 2005 06:43:40 -0700
Links: << >>  << T >>  << A >>
Hey Ankit,

I did a little bit of searching and I couldn't find an example of an
evolutionary alogrithm in VHDL.

All of the Genetic FPGA work I found is done on a PC, the end product
of the evolutionary algorithim is to create the VHDL. Not the VHDL
creating itself.

Take a look at this masters Thesis
http://www.ce.chalmers.se/~mek man/MasterThesis.pdf

First you Create a template statemachine.
Then run an evolutionary program on your PC. The fitness function is a
VHDL test bench that excites the "Evolved" VHDL code This is done using
Mentor or some other simulator. This processed is continued until the
"Evolved" VHDL description functions the way you want it. Then you
download it into a FPGA.

So you see the evolutionary process is run on a PC not the FPGA. The
FPGA VHDL code is the end product.

Eric


Article: 88402
Subject: Re: Evolutionary VHDL code example
From: "Eric" <ericjohnholland@hotmail.com>
Date: 17 Aug 2005 06:46:28 -0700
Links: << >>  << T >>  << A >>
http://www.ce.chalmers.se/~mekman/MasterThesis.pdf


Article: 88403
Subject: Re: Xilinx ISE on remtoe Display
From: Sean Durkin <smd@despammed.com>
Date: Wed, 17 Aug 2005 15:48:05 +0200
Links: << >>  << T >>  << A >>
Andrew Greensted wrote:
> If use use the xhost system, and manually set $DISPLAY project navigator
> works. So perhaps it just doesn't like the way SSH tunnels the X stuff.
> 
> Shame, I'd have preferred doing it over ssh
I have ISE6.3 running on SuSE9.3, and it works fine over SSH. $DISPLAY
is set to "localhost:13.0" for example, no other settings were
neccessary in my case.

cu,
Sean

Article: 88404
Subject: Re: XST (ISE 6.1i): Error: It's interesting and surprising
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 17 Aug 2005 06:50:46 -0700
Links: << >>  << T >>  << A >>
>
> What flip-flop has four clocks?
>
Dunno, but just imagine the phantasmagorical metastability polemic that such 
a Machiavellian device would foment!
Cheers, Syms. 



Article: 88405
Subject: Re: Easy USB2.0 hi-speed device solutions ?
From: "Manfred Kraus" <nobody@nowhere.not>
Date: Wed, 17 Aug 2005 16:14:09 +0200
Links: << >>  << T >>  << A >>
Sorry, I can not resist.

Have you checked the boards from CESYS GmbH ?
http://www.segor.de/cesyse.htm


regards
Manfred



"Mike Harrison" <mike@whitewing.co.uk> schrieb im Newsbeitrag 
news:i326g15o5vohtc4102td43lmdcsi5ejceg@4ax.com...
> I'm looking for an easy-to-use USB2.0 hi-speed device solution with the 
> minimum of software work
> required to get a lot of data from a device into a PC.
>
> I've found https://www.quickusb.com/ which looks to be exactly what I 
> want, providing DLL calls to
> use at the PC end to get chunks of data, but it seems somewhat expensive 
> ($150), especially with
> their connector break-out board ($79 for a PCB with 5 connectors on it!)
>
> If that's the only thing around, I'll use it, but was wondering if anyone 
> knows of anything similar
> that would be worth a look (lower priced would be nice..)
>
> Also, does anyone have any feedback on this product & the company ( can't 
> say I'm impressed so far
> after emailing an ordering enquiry 2 days ago with no reply yet...).
> This is initially for a 1-off project, but as I may well need USB2 for 
> future production projects,
> it would be useful to get familiar with something that had a price more 
> viable for production use. 



Article: 88406
Subject: Re: Xilinx ISE on remtoe Display
From: Hiding in Plain Sight <hidinginplainsight@earthlink.net>
Date: Wed, 17 Aug 2005 10:44:41 -0400
Links: << >>  << T >>  << A >>
On Wed, 17 Aug 2005 13:35:06 +0100, Andrew Greensted wrote:

> Hi All,
> 
> I'm trying to persuade xilinx ISE to display on a remote machine.
> ISE is installed on a solaris box, and I want to display the GUIS on a 
> linux box.
> 
> I've got X11 forwarding over SSH working fine. but for some reason the 
> project navigator just will not display.
> 
> Both coregen and floorplanner pop up fine.
> 
> I've got a feeling that Project Navigator is just refusing to work with 
> a $DISPLAY set to anything other than :0
> 
> Has anyone else had this problem. Or better still, has anyone been able 
> to get Project Navigator to display on a linux box over a remote 
> connection from a solaris Box.
> 
> ISE 6.3i
> Solaris 9
> Gentoo
> 
> Many thanks
> Andy
ISE works fine for me through an ssh tunnel but I've got Fedora Core 3 on
both my server and my workstation, your problem could be Solaris related.
I'm using the 7.1sp3 tools. The server is running 64 bit FC3, the
workstation is running 32 bit FC3.

I do get the following warning when I start ISE but it doesn't seem to
effect anything,

OLE API Function OleInitialize is not
currently implemented. Further warnings will be suppressed

Article: 88407
Subject: Re: FPGA-Based system design project
From: "Eric" <ericjohnholland@hotmail.com>
Date: 17 Aug 2005 07:58:30 -0700
Links: << >>  << T >>  << A >>
Check out 

Opencores.org

They have lots of projects.


Article: 88408
Subject: Re: FPGA-Based system design project
From: Javier Castillo <jcastillo@opensocdesign.com>
Date: Wed, 17 Aug 2005 17:01:38 +0200
Links: << >>  << T >>  << A >>
OpenRISC project need contributions. If you are interested on Open
Hardware Microprocessor you can add new features to OR1200 processor,
like a new cache system with associativity or to integrate the FPU
inside the datapath. We can talk about it if you want.

Regards

Javier Castillo
 

On 17 Aug 2005 07:58:30 -0700, "Eric" <ericjohnholland@hotmail.com>
wrote:

>Check out 
>
>Opencores.org
>
>They have lots of projects.


Article: 88409
Subject: Re: Xilinx ISE on remtoe Display
From: Andrew Greensted <ajg112@ohm.york.ac.uk>
Date: Wed, 17 Aug 2005 16:10:57 +0100
Links: << >>  << T >>  << A >>
hidinginplainsight@earthlink.net:
> ISE works fine for me through an ssh tunnel but I've got Fedora Core 3 on
> both my server and my workstation, your problem could be Solaris related.
> I'm using the 7.1sp3 tools. The server is running 64 bit FC3, the
> workstation is running 32 bit FC3.

sean:
 > I have ISE6.3 running on SuSE9.3, and it works fine over SSH. $DISPLAY
 > is set to "localhost:13.0" for example, no other settings were
 > neccessary in my case.

That's encouraging. Perhaps I'll have a deeper dig around another time.

Until then everything is working fine with using the xauth approach. 
Luckily my workstation only has a single direct LAN connection to my 
display machine, so I can keep security tight.

> I do get the following warning when I start ISE but it doesn't seem to
> effect anything,
> 
> OLE API Function OleInitialize is not
> currently implemented. Further warnings will be suppressed

I've been getting the same warning too, whether I'm displaying locally 
or remotely. I don't think it's important.

Andy

-- 
Dr. Andrew Greensted      Department of Electronics
Bio-Inspired Engineering  University of York, YO10 5DD, UK

Tel: +44(0)1904 432379    Mailto: ajg112@ohm.york.ac.uk
Fax: +44(0)1904 433224    Web: www.bioinspired.com/users/ajg112

Article: 88410
Subject: Re: Evolutionary VHDL code example
From: Andrew Greensted <ajg112@ohm.york.ac.uk>
Date: Wed, 17 Aug 2005 16:15:30 +0100
Links: << >>  << T >>  << A >>
apsolar@rediffmail.com wrote:
> Hello everyone
> Does anyone where I can find a simple VHDl code example based on
> evolutionary algorithms.I am doing a project on evolvable hardware.
> This will help me get a start on the implementation of Evolvable
> Hardware.
> Ankit Parikh
> Manukau Institute Of Technology
> 

You might find the proceedings of these conferences will give you some 
useful pointers, and references:

http://ic.arc.nasa.gov/projects/eh2005/
http://ices03.idi.ntnu.no/
http://www.isgec.org/gecco-2005/
http://147.83.49.249:8090/

I'm sure a lot of the authors will have accessible PDFs of their papers.

Andy
-- 
Dr. Andrew Greensted      Department of Electronics
Bio-Inspired Engineering  University of York, YO10 5DD, UK

Tel: +44(0)1904 432379    Mailto: ajg112@ohm.york.ac.uk
Fax: +44(0)1904 433224    Web: www.bioinspired.com/users/ajg112

Article: 88411
Subject: Re: Chipscope pro : timing constraint?
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Wed, 17 Aug 2005 11:19:15 -0600
Links: << >>  << T >>  << A >>
Pasacco wrote:
> dear chip scope pro users
> 
> Problem with VIO occurred in ChipScope Pro, ISE6.3.
> 
> i am (still -: ) exercising VIO,IlA with "asynchronous reset,
> asynchronous enable, 4 bit counter"
> 
> It works fine in ILA. That is the signal changes " 0 1 2 3 4 ...."
> 
> Problem is that, in VIO console, the signal behavior is not the same as
> ILA. That is the signal changes " 2 9 3 0 9 7 ...", which is
> unexpected.
> 
> I am not still sure that this behavior in VIO is problematic or not.
> 
> 

The VIO functionality and the ILA functionality are very different from
each other.

The ILA core captures data for every clock edge and presents the data to
the display when the buffer is full.

The VIO core allows you to insert control (inputs) and display sampled
status (outputs) similar to using a bank of push buttons or switches
for inputs or LEDs for outputs. There are arrows in the display for
that indicate activity occurred between the sampled points, so if the
previous value was 0 and the new value is 0 you can tell if blipped up
to a one and back again.

What you describe sounds like a normal sampling of the data set with a
free running counter.

Ed

Article: 88412
Subject: Re: Xilinx ISE on remtoe Display
From: Adrian Knoth <adi@thur.de>
Date: Wed, 17 Aug 2005 18:45:20 +0000 (UTC)
Links: << >>  << T >>  << A >>
Andrew Greensted <ajg112@ohm.york.ac.uk> wrote:

> Hi All,

Hi!

> I'm trying to persuade xilinx ISE to display on a remote machine.

I cannot talk about ISE, but XPS works through ssh -X.

There is one thing worth mentioning it: if I try to run XPS on
my local display (no remote usage), I have to set DISPLAY
to ":0", but it is *not* working when DISPLAY is set to ":0.0" (which
is the default on my debian system).

HTH

-- 
mail: adi@thur.de  	http://adi.thur.de	PGP: v2-key via keyserver

Win95 ist wirklich intelligent. Es macht immer das, was du nicht willst.

Article: 88413
Subject: Re: Chipscope pro : timing constraint?
From: "Pasacco" <pasacco@gmail.com>
Date: 17 Aug 2005 11:57:14 -0700
Links: << >>  << T >>  << A >>
Cycle accurate sampling can not be seen in VIO. That's was not a
problematic one. Thankyou for comment.

BTW, in the code below, I can not see the expected behavior of signal
'counter' in ILA.

Problem is that I only see : 4 4 4 4 .........

When rst = 0, en = 1, the signal change "0 1 2 3 4 " should be seen in
ILA waveform.
But actually so signal change can be seen.

What is the problem?
By the way, Is this problem?

Thankyou.

------------------------------------------------------------------------
-- Expected signal 'counter' behavior :  0 1 2 3 4 4 4 4 .....
------------------------------------------------------------------------
entity top is
port
(  clk : in std_logic;
   cnt : out std_logic_vector(3 downto 0)  );
end top;

architecture behave of top is
signal counter : std_logic_vector(3 downto 0):=(others=>'0');

signal rst, en: std_logic;            -- In VIO, reset=0, enable=1

begin
  process(en,rst,clk,counter)
  begin
   if en='0' then
       counter <= (others => '0');
   elsif rst='1' then
     counter <= (others => '0');
   elsif counter <= "0011" then
     if ( clk'event and clk = '1') then
        counter <= counter + 1;
     end if;
   end if;     
  end process;
  cnt <= counter(3 downto 0);
end behave;


Article: 88414
Subject: Modelsim on a remote display
From: "Marco" <marcotoschi@nospam.it>
Date: Wed, 17 Aug 2005 21:43:46 +0200
Links: << >>  << T >>  << A >>
Hallo,
I'm using modelsim se into a windows xp pc.

There is a way to use it into another windows xp pc with remote desktop?

Marco 



Article: 88415
Subject: Re: Modelsim on a remote display
From: "unfrostedpoptart" <david@therogoffs.com>
Date: 17 Aug 2005 12:55:24 -0700
Links: << >>  << T >>  << A >>
vnc (lots of versions - I use UltraVNC -
http://ultravnc.sourceforge.net/)


Article: 88416
Subject: Problem with quartus 5.0 sp1
From: czerstwy <czebaka@o2.pl>
Date: Wed, 17 Aug 2005 22:18:16 +0200
Links: << >>  << T >>  << A >>
Hello

I've got problem with Quartus 5.0 with Service Pack 1. Problem occurs in 
compilation process after fitting. When assembling is at 47% I get 
'Quartus II Internal Error' which says:

'Internal Error: Sub-system: ASM, File: asm_ram_model_base.cpp, Line: 3430
clock_is_used == clock_found
Quartus II Version 5.0 Build 168 06/22/2005 SJ Web Edition
Service Pack Installed:  1'

I used to get this kind of errors earlier in this and previous versions 
of Quartus, but restarting Quartus or computer was always a solution.

Project is for Acex EP1K30 device and contains 2 lpm_ram_dp megafunctions.

Can anyone give me directions what can cause this kind of problems?

Best Regards
czerstwy

Article: 88417
Subject: Re: Problem with quartus 5.0 sp1
From: "Subroto Datta" <sdatta@altera.com>
Date: 17 Aug 2005 15:38:42 -0700
Links: << >>  << T >>  << A >>
Is there a Mysupport service request number on this? Also please send
me a project archive of your design so that we can reproduce the
problem in house.

Subroto Datta
Altera Corp.


Article: 88418
Subject: Re: super fast divide-by-N
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 18 Aug 2005 11:30:24 +1200
Links: << >>  << T >>  << A >>
Thomas Magma wrote:
>  Let me give you a bit of back ground then. I am really pushed for space. 
> I need different clock frequencies thru-out my board. My highest frequency 
> is a Fox RFXO running around a GHz. I would like to derive all other clocks 
> from this one if possible. Next lowest frequency is around 80 MHz. Then a 
> few after that. I hate PLLs and I don't want a bunch a xtals on my board. So 
> I thought I would just divide down from my highest frequency. One chip 
> solution would be the best.
[.dsp removed. .fpga added]

  These RfXOs are interesting devices, sub ps jitter, and 600-1.25GHz 
clock out. Not cheap, but they do change the clock conventions.
  Normally, you'd use a 80MHz xtal, and an RF synthesiser to create the
GHz region clock.


  CPLDs can clock to some hundreds of MHz now, but none released can
get to > 600MHz.

  Perhaps there will be enough demand for this type of GHz LVDS clock-in,
that we will see FPGA, or even CPLD, with IP cells designed to divide this ?

  On present process, it is quite doable; you could not clock the FPGA 
fabric at 0.6-1.25GHz, but you could divide from that, and get a phase 
locked, low jitter FPGA clock(s) - if the IOcells were designed to 
support it ?

-jg




Article: 88419
Subject: Re: Chipscope pro : timing constraint?
From: Ed McGettigan <mcgett@pacbell.net>
Date: Wed, 17 Aug 2005 23:31:12 GMT
Links: << >>  << T >>  << A >>
Pasacco,

Your code is doing exactly what you asked it to do.  Your IF
statements do this.

   1) If en=0  then count=0
   2) If rst=1 then count=0
   3) If count < 3 then count = count + 1
   4) Else nothing

So when count=4 that's the end of the game.

Ed


Pasacco wrote:
> Cycle accurate sampling can not be seen in VIO. That's was not a
> problematic one. Thankyou for comment.
> 
> BTW, in the code below, I can not see the expected behavior of signal
> 'counter' in ILA.
> 
> Problem is that I only see : 4 4 4 4 .........
> 
> When rst = 0, en = 1, the signal change "0 1 2 3 4 " should be seen in
> ILA waveform.
> But actually so signal change can be seen.
> 
> What is the problem?
> By the way, Is this problem?
> 
> Thankyou.
> 
> ------------------------------------------------------------------------
> -- Expected signal 'counter' behavior :  0 1 2 3 4 4 4 4 .....
> ------------------------------------------------------------------------
> entity top is
> port
> (  clk : in std_logic;
>    cnt : out std_logic_vector(3 downto 0)  );
> end top;
> 
> architecture behave of top is
> signal counter : std_logic_vector(3 downto 0):=(others=>'0');
> 
> signal rst, en: std_logic;            -- In VIO, reset=0, enable=1
> 
> begin
>   process(en,rst,clk,counter)
>   begin
>    if en='0' then
>        counter <= (others => '0');
>    elsif rst='1' then
>      counter <= (others => '0');
>    elsif counter <= "0011" then
>      if ( clk'event and clk = '1') then
>         counter <= counter + 1;
>      end if;
>    end if;     
>   end process;
>   cnt <= counter(3 downto 0);
> end behave;
> 

Article: 88420
Subject: Re: Spartan-3 configuration -- peculiar problem
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Wed, 17 Aug 2005 16:50:10 -0700
Links: << >>  << T >>  << A >>
On 16 Aug 2005 22:40:59 -0700, "Peter Alfke" <alfke@sbcglobal.net>
wrote:

>500 MHz (reduced further by the probe) may no longer be sufficient for
>analyzing such problems.
>You mentioned that the probe eliminated the problem. That indicates a
>substantial capacitance.

No, a regular passive probe fixed it. The fet probe didn't, but it
showed a nice waveform.


>"Slow CMOS chips" are not really slow anymore...

It's an MC68332, and they're *still* slow!

>My question is: How many design are out there in the world, functioning
>with minimal margins?

Well, tons. In this case, a 10 pF cap fixed it solid, so we went with
33 for luck.

>Attention to Signal Integrity is important like it has never been
>before.

Couldn't agree more.

John



Article: 88421
Subject: Re: Spartan-3 configuration -- peculiar problem
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Wed, 17 Aug 2005 16:53:12 -0700
Links: << >>  << T >>  << A >>
On 16 Aug 2005 15:34:28 -0700, ScreamingFPGA@yahoo.com wrote:


>
>Thanks All
>
>  For your considerations and patience.
>
>  Problem solved. Mea Culpa. IIFI. A comedy of errors:
>
>  Configuration worked perfectly from the get-go. I was convinced
>there was a config problem because my little 'hello world' LED-
>BLINKY-THINGY that I had dropped into the top level of the design
>wasn't causing the LED to blink.
>
> I noticed the INIT line was low and became convinced I had a
>configuration problem. I chased that for a couple of days.
>
> By chance I left the proto powered for a couple of hours and noticed
>the LED had turned on. Checked the design and noticed I had
>miscalculated the clock divisor for the LED blinker by a few
>orders of magnitude and it was blinking once every 4 hours, instead
>of once every second. DOH!
>
> By then I had fixated on the INIT line being low, and was ensconced
>in my theory that the config logic was driving it there, as it
>'shoudn't' have been low, by design.
>
> My post-config use of the INIT pin was as an input. However my design
>wasn't using this particular input at this stage of the proto. The
>synthesis tool re-defined it as an unused pin.
>
> I had asked bitgen to pull unused pins low.
>
> It all makes sense now.
> 
>Thanks again all for humoring me.
>
>-Scott


We put a SOT-23 green LED on the DONE pin of all Xilinx chips. It
always gives me a warm feeling to see them all light up in sequence at
powerup.

John


Article: 88422
Subject: Re: Cypress CY7B923/33 models
From: "ernie" <ernielin@gmail.com>
Date: 17 Aug 2005 17:30:50 -0700
Links: << >>  << T >>  << A >>
Hi Mike,

I'm writing VHDL that is supposed to talk to the Hotlink chips on the
PCB that we are making.  I'm not sure how to make sure that my code
works except to find a VHDL model and instantiate it in my testbench.


Cheers,
Ernie


Article: 88423
Subject: Re: super fast divide-by-N
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 17 Aug 2005 17:44:37 -0700
Links: << >>  << T >>  << A >>
I have been told that Virtex ( II to 4) the DCMs can divide down from a
GHz, if you use the divide-by-two prescle option in the DCM. That means
the DCM really runs on 500 MHz, which it is specified to do.
Division ( even combined multiply/divide) with numbers up to 32 is no
problem. You can multiply 500 MHz by 7 and divide by 27 (if those are
your numbers). The virtual 3.5 GHz are not really being generated, it's
all mathematical trickery. :-)
For finer granularity, you can use DDS phase accumulators which,
however, generate som jitter (+ or - half a clock period).
Peter Alfke, Xilinx Applications


Article: 88424
Subject: Re: Spartan-3 configuration -- peculiar problem
From: ScreamingFPGA@yahoo.com
Date: 17 Aug 2005 18:24:20 -0700
Links: << >>  << T >>  << A >>
John Larkin wrote:
> On 16 Aug 2005 15:34:28 -0700, ScreamingFPGA@yahoo.com wrote:
>
>
> >
> >Thanks All
> >
> >  For your considerations and patience.
> >
> >  Problem solved. Mea Culpa. IIFI. A comedy of errors:
> >
> >  Configuration worked perfectly from the get-go. I was convinced
> >there was a config problem because my little 'hello world' LED-
> >BLINKY-THINGY that I had dropped into the top level of the design
> >wasn't causing the LED to blink.
> >
> > I noticed the INIT line was low and became convinced I had a
> >configuration problem. I chased that for a couple of days.
> >
> > By chance I left the proto powered for a couple of hours and noticed
> >the LED had turned on. Checked the design and noticed I had
> >miscalculated the clock divisor for the LED blinker by a few
> >orders of magnitude and it was blinking once every 4 hours, instead
> >of once every second. DOH!
> >
> > By then I had fixated on the INIT line being low, and was ensconced
> >in my theory that the config logic was driving it there, as it
> >'shoudn't' have been low, by design.
> >
> > My post-config use of the INIT pin was as an input. However my design
> >wasn't using this particular input at this stage of the proto. The
> >synthesis tool re-defined it as an unused pin.
> >
> > I had asked bitgen to pull unused pins low.
> >
> > It all makes sense now.
> >
> >Thanks again all for humoring me.
> >
> >-Scott
>
>
> We put a SOT-23 green LED on the DONE pin of all Xilinx chips. It
> always gives me a warm feeling to see them all light up in sequence at
> powerup.
>
> John

 Yep.

 Isn't that the first rule of product design, that you can never
have too many LED's? ;)

 The old Volvo 240's had a 'Bulb Failure Warning Light' on the
dashboard. But what about the case where that bulb failed? Oh no!
Infinite recursion...

-Scott




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