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hello friends,
i am new to leonardo spectrum, but i known vhdl..
in my part of coding given below
signal pnct_indx : integer range 0 to 200;
signal cnvenc_indx : integer range 0 to 300;
ln.no process(clk,rst)
1 if rst = '1' then
2 punct_data <= (others => '0');
3 punct_full ,= '0';
4 elsif clk'event and clk = '1' then
5 if count = 6 and pnct_indx < 192 and cnvenc_indx < 288 then
6 punct_data(pnct_indx to pnct_indx+3) <=
cnvenc_data(cnvenc_indx)
&cnvenc_data(cnvenc_indx+1)&cnvenc_data(cnvenc_indx+2)&cnvenc_data
(cnvenc_indx+5)
pnct_indx <= pnct_indx +4;
cnvenc_indx <= cnvenc_indx + 6;
elsif pnct_indx = 192 then
punct_full <= '1';
end if
end if
end process
when i apply this coding to leonardo spectrum level 3, i found one
error named as left bound of range doesn't evaluate to a constant at
line no. 6..
pls help me and i also got some sort warnings as
suppose this file have entity name as punctdata and rtl as
architecture name
warning is replacing punctdata in hdl libraray work.
and replacing rtl of entity punctdata...
expecting ur reply eagerly
Senthil.R
Article: 66901Mahim Mishra wrote: > iMPACT reports "Programming stopped: Done did not > go high". Try changing the mode of your parallel port from the BIOS. If forget which one works, I think it's ECP. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 66902
William Wallace wrote: > He didn't say how many frequencies he was going to use, or what kind > of FPGA, or how many bits in the samples. A few frequencies. Not enough data yet. Samples can be up to 16 bits wide x 3 (RGB image processing). Virtex 2V1000. Had to put the project on the shelf for a few days. I'm very tempted to run the whole thing at the highest possible frequency (in the context of what needs to be done, not the highest attainable by the FPGA) and use clock enables. It would seem to me that this is the easiest way to stay out of trouble. I like that. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 66903
In comp.arch.embedded Shiraz Kaleel <shirazkh@comcast.net> wrote: > I am surprised nobody really answered to the point! That was because there really *was* no point to the original posting. > Software is when sequencing through the algorithm is done using INSTRUCTION > power > Hardware is when sequencing through the algorithm is done using LOGIC > power...!!! And since "INSTRUCTION power" is just a special type of "LOGIC power", we've come full circle back to the original question. -- Hans-Bernhard Broeker (broeker@physik.rwth-aachen.de) Even if all the snow were burnt, ashes would remain.Article: 66904
On Wed, 25 Feb 2004 23:39:28 GMT, Andrew Reilly wrote: >> What is the difference between a hardware implementation of an >> algorithm and a software one. > >It's all hardware. If it's not hardware, it's not doing >anything (see question below). So, if the software isn't doing anything, then the hardware should perform identically if we remove it, yes? >> How do you say an algorithm is faster in one and slower in other.. if >> it's based on timing how do you do that?? What makes it faster in one >> and not in other?? > >The faster one is the one that takes less time to do whatever >it was that you wanted done. This involves actually doing >the thing in question. Only hardware actually does stuff, What kind of "stuff" does a PC do without any software? It's a reliable paperweight, but not much else. No hardware will do anything at all unless it's instructed to do so. Whether such instruction comes from software, firmware, or liveware doesn't alter that. This all reminds me of some "definitions" from way back in the '80s: If you can see it, and you can touch it, then it's Real. If you can touch it, but you can't see it, then it's Logical. If you can see it, but you can't touch it, then it's Virtual. If you can't see it, nor touch it, then it's Gone. -- MaxArticle: 66905
Hi, friends,
I'm following Altera Nios hardware tutorial for apex development board. I
cannot run the hello_nios.srec SDK display:
nios-run: Ready to download hello_nios.srec over COM1: at 115200 bps
: Press CPU Reset (or CLEAR) on target board to begin download
: Type Control-C to exit the program
: Waiting for target.....
Did anybody meet this problem?
Thanks!
Chi
Huageng dot Chi at vtt dot com
Article: 66906No, but I'd like to know the results on the AMD 64. I spead up my 3.2GHz P4 compliles by 20% by making sure my memory was running at dual channel 400MHz. Turned out it was running dual channel 333MHz. I had to actually downgrade my memory slightly, because my motherboard saw cas2 DDR and dropped to 333. With cas 2.5 it was confident to go to 400. YMMV, Ken "Pete Fraser" <pete@rgb.com> wrote in message news:103vj8jovcv761e@news.supernews.com... > We're currently running a 3 GHz Pentium with 2 GB > memory under Windows 2000. > > We hope to speed things up by 15-20%, by going > to AMD X86-64 and / or Linux. > > Has anybody tried this? > Any feedback? > >Article: 66907
Max wrote:
> On Wed, 25 Feb 2004 23:39:28 GMT, Andrew Reilly wrote:
>
>
>>>What is the difference between a hardware implementation of an
>>>algorithm and a software one.
>>
>>It's all hardware. If it's not hardware, it's not doing
>>anything (see question below).
>
>
> So, if the software isn't doing anything, then the hardware should
> perform identically if we remove it, yes?
As other posters have indicated, yes.
>>>How do you say an algorithm is faster in one and slower in other.. if
>>>it's based on timing how do you do that?? What makes it faster in one
>>>and not in other??
>>
>>The faster one is the one that takes less time to do whatever
>>it was that you wanted done. This involves actually doing
>>the thing in question. Only hardware actually does stuff,
>
>
> What kind of "stuff" does a PC do without any software? It's a
> reliable paperweight, but not much else.
Who was talking about a PC? The original poster was referring to "a
hardware implementation of an algorithm and a software one."
> No hardware will do anything at all unless it's instructed to do so.
> Whether such instruction comes from software, firmware, or liveware
> doesn't alter that.
I'm sure, among others, ASIC manufactures would beg to differ... there
are many hardware implementations (both within chips and as discrete
circuits) that require no "instructions" in order to power up and be
fully functional.
Have fun,
Marc
Article: 66908"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<SFk0c.18488$7N7.7707@newssvr29.news.prodigy.com>... > Try changing the mode of your parallel port from the BIOS. If forget which > one works, I think it's ECP. I am able to configure a design onto the FPGA if it does not use the PowerPC core, using the same tools and setup. I see this failure only if I try to use the PowerPC core in my design. I also checked the bitgen.ut that Xilinx ISE/Platform Studio produces for my design and it matches exactly the bitgen.ut that ISE generates for a project that does not use PowerPC and which I am able to download successfully, so it is also (probably) not some pin being pulled up or down wrong. Thanks, MahimArticle: 66909
johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0402280624.5fed26ec@posting.google.com>... > "khoa nguyen" <jeffn@ihug.com.au> wrote in message news:<c1p5k1$5sm$1@lust.ihug.co.nz>... > > I'd like to support the ARM and IA32 ISA on an FPGA. At the moment Im unsure > > if I can do this. So what I thought is that if only I have some small clean > > test bench of both ISA's, then I could start supporting those small set of > > instructions. Later on I would add in the rest. > > > > Im wondering if there's anyone that happens to have some small clean test > > benchs or even applications, then could you forward them to me. > > > > thanks heaps. > > About the time when Pentium 100 was introduced, there were a number of > authers that wrote books on optimising x86 code to run as fast as > possible. I have a few of these but in the office so I can't recall > names v books. > > The jist of one of these " ... Inner Loops ..." was that if you > limited yourself to certain ops, you could get x86 to perform very > well indeed ie 1 or 2 ops per cycle if paired right. He breaks the > instruction set down into many groups, the fastest, the oks, the > maybes, the never use ect, & the whatever. > > If you build a risc to execute those 1st 2-3 groups you would have a > risc that doesn't execute most x86 code since most compilers probably > generate some of the lesser codes from time to time. Also the risc > would suffer the same horrible design decisions that Intel made almost > 30yrs ago. IE var length byte encodings. > > Now as any AMD/Intel person would say, even though its horrible, those > wierd var length ops are understood, its possible to do in VLSI with > transister muxes very well so it becomes a minor headache. But FPGAs > are expensive to use muxes to the extent x86 needs them. > > The alternative is to use time based state machine to peel the ops > apart but that would be very slow. > > I would suggest staying away from x86 ISA as being the most complex > underpowered ISA around. > > I would suggest staying away from Arm as their lawyers are aggresive, > but it is a much easier target. > > > regards > > johnjakson_usa_com The short term goal of what Im trying to do is to be able to run IA32 and ARM instructions, and obtain some data; hence, the need for some test bench, which starts off simple and clean. I'd like to find out the problems of doing that. If it cant be done then i'd like to find out why ... the hard way! :) I'd like to thank you John for your advice about ARM's lawyers. But i do not know the ramifications you're implying. Could you explain it further if possible. Im not really interested in optimizing IA32 at the moment. But the book you mentioned might be a starting point for me to learn about IA32 optimization. Could you dig it up for me, and send me its title, author etc. If possible I'd like to support more ISA on FPGA. And be able to run codes on just a one machine. thanks john, khoa.Article: 66910
I beg to differ. Hardware need not be an instruction based processor, for
example one can create a circuit that does FIR filtering all day long
without any instructions. Software runs on a special hardware design that
combines some basic elements, such as registers and a fancy adder called an
arithmetic-logic-unit (ALU) arranged so that the function of the ALU and
steering of data through the collection is controlled by some logic codes.
The sequence of logic codes is a 'program' created to perform some series of
operations with the collection of hardware to produce a useful result. The
idea, of course is to create some set of hardware that can be controlled to
perform a series of elemental steps programmed by the user to be able to
compute solutions to a variety of problems. Hardware in general is not
designed in this fashion, only hardware that is meant to be programmed.
Hardware can just as easily be a set of dedicated circuits to perform only
one task, and wired permanently for a single application (and therefore
does not require any instructions). That type of hardware came long before
programmable sequential machines, and is still used where performance or
power dictate a dedicated solution.
Max wrote:
> No hardware will do anything at all unless it's instructed to do so.
> Whether such instruction comes from software, firmware, or liveware
> doesn't alter that.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 66911I am using Xilinx Core Generator (ISE 6.1 version) for creating memory modules for the Xilinx Virtex II pro family. I saw that in case the size of the memory is large such that 2 or more RAMBs are utilized, the resulting module is not RPMed even though the create RPM option in the CORE generator is checked. I have to go manually to the .edn file created by the generator and put the "RLOC" and "RPM_GRID" properties for the RAMB instances myself. Then after ngdbuild and map, the module is recognized as RPM. What is the reason for this? Is there any other solution other than what I just mentioned above? Also... I use the Xilinx Development System from the command line and like to use EMACS. What should I include in my .emacs file so as to enable syntax highlighting for UCF, XCF and other relavant files like in the Xilinx ISE editor? Eagerly awaiting replies... Thanks, Akshay.Article: 66912
Hi Chi, Make sure that you have programmed the APEX device with the pof file generated by the Quartus compile prior to downloading the srec file. When you program the device using the Quartus II Programmer, it should say that the device programmed successfully. If that does not happen check that the download cable is connected properly to the board and that you have followed the tutorial instructions correctly. - Subroto Datta Altera Corp. "chi" <huageng.chi@vtt.fi> wrote in message news:c1t4vs$idb$1@lilja.vtt.fi... > Hi, friends, > > I'm following Altera Nios hardware tutorial for apex development board. I > cannot run the hello_nios.srec SDK display: > > nios-run: Ready to download hello_nios.srec over COM1: at 115200 bps > : Press CPU Reset (or CLEAR) on target board to begin download > : Type Control-C to exit the program > : Waiting for target..... > > Did anybody meet this problem? > > Thanks! > > Chi > > Huageng dot Chi at vtt dot com > >Article: 66913
Chris Carlen wrote:
>
>
> Yes, of course. I appreciate your suggestions and if you want to
> constructively criticize my posts in the future, that is welcome too. I
> have noticed you are a very experienced poster here, so I will listen.
>
> The only reason I am doing these silly things is twofold: 1. I am just
> learning the language, and am on the chapters of "gate level modeling"
> and "structural" modeling in my Verilog text.
>
Is the book you are using called Verilog Digital System Design by
Zainalabedin Navabi?
It sounds like that because that book gets into boring stuff like
structural modeling.
> So rather than do the boring exercises in the book, especially when I
> have a real design that needs implementing, I decided to get comfortable
> with structural modeling by implementing my first Verilog project in
> mainly this way.
>
>
> So it appears you are hinting that it is wiser to code generically
> rather than invoke vendor libraries? I suppose this might make sense in
> the broader sense, for portability, huh? Something I hadn't really
> thought about until you prodded me.
>
Right, you probably should avoid using vendor specific features
if there is no benefit like performance gain or logic resources
reduction.
Otherwise, keeping the logic generic makes sense for portability
reasons.
> So even if I were determined to model in the structural style, might you
> suggest that I instead build the generic FDC using the code you have
> shown, and which I can understand enough. Put it in a module called
> FDC, then instantiate that?
I am personally sure how to answer this question, but even if
you are interested in modeling a FF, in Verilog "reg" is as simple as
things get.
That being said, if you are interested in instantiating a vendor
specific primitive like FDC from Xilinx's primitive library (Other firms
have a similar primitive with similar names.), you can do that, but, of
course, the code will become vendor specific.
>
>
> Well, it was kinda fun ;-) I am also learning digital logic design by
> gradual experience, having never taking a formal course in it. So I
> asked myself "how does one determine the equality of two binary words?"
> I proceeded to twiddle with bits and bytes and truth tables on paper,
> and came up with the above blob of gates. I proceeded to implement it
> structurally, again just to cement my comfortability with this
> inefficient coding style.
>
Because of synthesis tools, I haven't used truth tables for
years (Last time I did so in a college digital logic course.), however,
when I had to build timing critical logic, I ended up reverting back to
drawing gates on a paper (Really, equivalent of doing schematics.),
mapping those gates into 4-input LUTs (Look-Up Tables), convert the
paper schematics into Verilog assign statement equations using & (AND),
| (OR), ^ (XOR), and ~ (NOT), and finally, slapping "keep" attribute of
a synthesis tool (XST in my case.) to the wires coming out of assign
statements to prevent the synthesis tool from messing up the carefully
crafted equations I wrote (Still, XST ignored the keep attribute in some
cases, but 95% of the equations survived intact.).
What I just described is a really low level coding style, and I wish I
didn't have to do so, but I had no choice.
> Then I discovered on further perusing the Xilinx library that they had
> the same thing available to me already.
>
> In the interest of learning I also experimented with the following way
> in dataflow style:
>
> assign Q = & ( A ~^ B );
>
> which seemed to work fine. I also wondered if it was possible to write
> the operation in the way you show here:
>
>
> But actually, I wonder if you can do this:
>
> assign Q = (A == B); // ???
>
> Ok, thanks for the reply.
>
> Good day!
Yes, the above "assign Q = (A == B);" should work, however, I
usually like to specify the bit range, so that nothing unexpected
happens.
Generally speaking, Verilog is not a strict language, and lets to do
things like comparison without specifying the bit range, however, I
heard (I am not 100% sure.) that VHDL may not let you do that.
Kevin Brace
Article: 66914
Hi,
I am new in using the embeded device (VirtexII-Pro) to implement an
algorithm.
As I want to count the cpu time of the algorithm , I use the
XTime_GetTime(starttime) in the the xtime_l.h library.
Also I need to print out the result to a uart by using xil_printf. But the
result did not displayed successfully.
Please find the program as follows.
Is there any step missed?
Many thanks,
Terrence
#include "xgpio.h"
#include "xparameters.h"
#include "math.h"
#include "xtime_l.h"
main() {
XGpio gpio_reset, gpio_addr, gpio_data;
int i,j=0, count=0,k, site=0;
double likelihood[12], probability=0.0, lnL=0.0;
XTime *starttime, *endtime;
char *output;
xil_printf("start\n");
XTime_GetTime(starttime);
// Start computation
...
//End computation
XTime_GetTime(endtime);
//convert the long long to a string
sprintf(output, "%llu", *endtime);
//print the result
while(*output){
xil_printf("%c", *output);
++output;
}
}
Article: 66916Hi, In using Xilinx Virtex2 chip, I wonder what's teh general rule to instantiate a global timing buffer. If I use a DCM to do some clock divide and use the generated one to driver in-chip design, I should add a buffer to the DCM output. But how about my DCm i used to de-skew the clock, meaning clkin is in-chip clock, while clkfb is off-chip clock, and clk0 going off-chip again, it seems in this case, I do not have to add a buffer to clk0. but is there any rule here...Article: 66917
Hi Ray, > I'm not sure yet what it does to the arithmetic functions. There are two specific ways in which Stratix II improves on the arithmetic capabilities of our previous archiectures. First, a single ALM can implement the sum of two 4-LUTs provided they share two inputs f(a, b, c, d) + g(a, b, e, f). Second, it can implement a 3-input adder allowing you to reduce the number of ALMs and logic levels required for adder trees. Please see http://www.altera.com/products/devices/stratix2/features/architecture/st2-adder.html and Figures 2-11, 2-12, and 2-13 of the Stratix II databook for further details. > It makes the synthesis job a little harder since there are now even more ways to skin the cat In architecting Stratix II, we took into account the increased challenges for synthesis and place & route. We worked with and continue to work with our 3rd party synthesis providers to improve the quality of synthesis for this architecture. Using today's synthesis tools, Stratix II achieves a 25% logic density advantage over Stratix. And it's not hard to imagine that this will only get better with time. Regards, Paul Leventis Altera Corp.Article: 66918
> There are two specific ways in which Stratix II improves on the arithmetic > capabilities of our previous archiectures. First, a single ALM can > implement the sum of two 4-LUTs provided they share two inputs f(a, b, c, > d) + g(a, b, e, f). Second, it can implement a 3-input adder allowing you > to reduce the number of ALMs and logic levels required for adder trees. A quick correction -- I'm suffering from Vacation-Fried Brain Syndrome: Each ALM implements _two_ bits of arithemetic: sum0 = f0(a, b, c, e0) + g0(a, b, c, f0) sum1 = f1(a, b, d, e1) + g1(a, b, d, f1) Where f0, f1, g0, and g1 are each four-input functions. The simplest use of this is to set e[0..1] = A[0..1] and f[0..1] = B[0..1], make a, b, c, d all don't cares, and set f0, f1, g0, g1 to be "wire LUTs". This just gives you Sum[0..1] = A[0..1] + B[0..1]. There are other more powerful uses, such as user-controllable adder/subtractor, conditional operators, etc. An ALM can also implement _two bits_ of an 3-input adder . Regards, Paul Leventis Altera Corp.Article: 66919
What? "T. Irmen" <tirmen@gmx.net> wrote in message news:c1qp3p$dbi$1@online.de... > Hi, > > to everyone who thought about doing calculations with netlists . eg. > external pins, internal states are known (from reset state) to figure out > the remaining signals, lets say 100% visibility. > > Does anybody thought about that? > > kind regards, > thomas > >Article: 66920
Hi Austin, [To answer your technical/architectural questions] > I was unclear on just how a ALM is any different from drawing the box > differently around the components. I am still puzzled, but the block > diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it > was actually designed this way then that is simply what it is. A true 6 > LUT has 64 memory cells and the associated logic, and two of these seems > a bit excessive and would not require any other logic or muxes at all. > Combining existing 4 LUTs to deliver some of the possible terms of a 6 > LUT is a completely different matter. I would highly recommend looking at Figure 2-6 of the Stratix II databook to gain a better understanding of exactly what hardware there is in the ALM. The Stratix II ALM can implement all functions of 6 inputs, since it has 64 bits of LUT memory. It can also implement two independent 4-LUTs, a 5-LUT and 3-LUT, two 6-LUTs that share a LUT mask and 4 inputs, two 5-LUTs that share part of their LUT mask plus 2 inputs, a subset of 7-input LUTs, etc. Plus there are a variety of ways to combine this functionality with registers before, after, or independent of the logic, and some gunk for powerful arithmetic. First the simple question: How does a 6-LUT differ from 4 4-LUTs + 3 2:1 muxes (ala 2 slices, 2 f5 muxes and an f6 mux)? It is not just where you draw the boxes. The silicon area per logic function (or logic efficiency) is much better with a 6-LUT, and this is largely due to area for user-programmable routing. In a 4-LUT architecture, the LUTs are designed to be independent, thus there are 4 independently routable signals to each LUT. The fx muxes also require a control input, which for now we will assume is independently routed. Thus to implement a 6-input function using a 4-LUT architecture and fx muxes requires a total 19 independently routed signals. This implies 19 routing multiplexers which burn area and power. With a 6-LUT, obviously only 6 routing inputs would be required. So the potential area savings of a 6-LUT come not from a reduction in LUT mask RAM bits (both require 64) but from a reduction in user-configurable routing multiplexers. Of course, you can't take this argument to extremes. Working against larger LUTs is your ability to map designs into these larger functions. If most of your design maps into 4-input functions and you have a 6-LUT architecture, you'll be wasting a lot of silicon and a 4-LUT based product will be more efficient. For these reasons, there is a bottom to the curve -- a 25-LUT architecture would not be more area efficient than a 4-LUT architecture! Where that bottom is... well, there's lots of academic studies and we've got our own data. But the Stratix II ALM is more than a 6-LUT architecture. It targets the routing area efficiency gains of larger LUTs, while attempting to minimize the wastage that occurs when you need to implement small logic functions. It provides a few extra inputs (8 instead of 6) and one extra output (2 instead of 1), and is thus slightly less efficient than a true 6-LUT architecture for implementing 6-input functions. However, these inputs and outputs plus a few internal 2:1 muxes allow us to make use of the full ALM under a wide range of function sizes by allowing us to fracture the ALM into independent/semi-dependent functions. This allows us to greatly reduce the number of LUT mask bits that go unused, and allows us to highly utilize the available inputs and outputs of the ALM, resulting in little wasted silicon area for input/output routing. Why 8 inputs, 2 outputs, and all the little 2:1 muxes? Because our experiments in the end showed that this resulted in the best combination of area and performance, and I can assure you we believed there to be a substantial benefit over the Stratix ALE in order to commit the resources required to support a completely new logic fabric. On a performance front, larger input LUTs confer a benefit in terms of critical path delay by reducing the number of levels of logic and thus routing hops required to a implement a given cone of logic. But is an 6-LUT based ALM faster than 4-LUT based slices + fx muxes? A paper analysis will not answer this, since both implement 6-input functions (albeit at different area efficiencies). I could start arguing that smaller area turns into/gives area to be spent on better speed, or start counting transistors/gates in the path, but then we'd be getting into a very fuzzy realm full of a gazillion assumptions! > Regardless, it is enjoyable to hear about any radical or innovative new > architecture, as there are so many that now dot the landscape as dead > skeletons of past FPGAs. And I must say it was enjoyable to have worked on a radical, innovative architecture such as Stratix II. And given its enhancements over the successful Stratix architecture, I expect it to be flesh-covered and alive for a long while. Regards, Paul Leventis Altera Corp.Article: 66921
HELLO!! As part of my final year project, iam working on NCO design in VHDL. I will be very thankful if anyone can send me the code or any related links... I am working on ALTERA MAX+PLUSII. thankx in advance..Article: 66922
Is your "output" pointer pointing to a valid array of chars (in this code
it's pointing to somewhere in the memory).
Frank
"Terrence Mak" <stmak@se.cuhk.edu.hk> wrote in message
news:c1u8a3$24vn$2@justice.itsc.cuhk.edu.hk...
> Hi,
>
> I am new in using the embeded device (VirtexII-Pro) to implement an
> algorithm.
> As I want to count the cpu time of the algorithm , I use the
> XTime_GetTime(starttime) in the the xtime_l.h library.
> Also I need to print out the result to a uart by using xil_printf. But the
> result did not displayed successfully.
> Please find the program as follows.
>
> Is there any step missed?
>
> Many thanks,
> Terrence
>
> #include "xgpio.h"
> #include "xparameters.h"
> #include "math.h"
> #include "xtime_l.h"
>
>
>
> main() {
> XGpio gpio_reset, gpio_addr, gpio_data;
> int i,j=0, count=0,k, site=0;
> double likelihood[12], probability=0.0, lnL=0.0;
> XTime *starttime, *endtime;
> char *output;
>
>
> xil_printf("start\n");
> XTime_GetTime(starttime);
>
> // Start computation
>
> ...
>
> //End computation
>
> XTime_GetTime(endtime);
>
> //convert the long long to a string
> sprintf(output, "%llu", *endtime);
>
>
> //print the result
> while(*output){
> xil_printf("%c", *output);
> ++output;
> }
>
> }
>
>
>
>
Article: 66923Hi Mahim, as you're only using on of the PPCs you might also want to try instantiate the secod one as a dummy-PPC. Just copy it in the MHS-file. Maybe it helps.... Cheers, Martin Mahim Mishra wrote: > "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<SFk0c.18488$7N7.7707@newssvr29.news.prodigy.com>... > > >>Try changing the mode of your parallel port from the BIOS. If forget which >>one works, I think it's ECP. >> > > I am able to configure a design onto the FPGA if it does not use the > PowerPC core, using the same tools and setup. I see this failure only > if I try to use the PowerPC core in my design. > > I also checked the bitgen.ut that Xilinx ISE/Platform Studio produces > for my design and it matches exactly the bitgen.ut that ISE generates > for a project that does not use PowerPC and which I am able to > download successfully, so it is also (probably) not some pin being > pulled up or down wrong. > > Thanks, > Mahim >Article: 66924
I am using Win2K. Sumit -------------------- http://www.c-nit.net Marc Guardiani <marc@guardiani.com> wrote in message news:<wBd%b.5884$ax2.920@nwrdny03.gnilink.net>... > Which OS are you using? NT is no longer supported. > > Sumit Gupta wrote: > > I upgraded to webpack 6.1i from 4.2 and when I compile my design I get the > > following error. > > > > Loading device for application Xst from file 'v100.nph' in environment > > C:/Xilinx. > > FATAL_ERROR:DeviceResourceModel:basnpdevice.c:620:1.23 - bad nph file > > Process will terminate. To resolve this error, please consult the Answers > > Database and other online resources at http://support.xilinx.com. If you > > need further assistance, please open a Webcase by clicking on the "WebCase" > > link at http://support.xilinx.com > > > > I searched through answer database but did not find anything. Does anybody > > has any ideas ? > > > > Sumit > > -------------------- > > http://www.c-nit.net > > > >
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