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Messages from 75600

Article: 75600
Subject: Re: Xilinx Tshirts in football package.....
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 11 Nov 2004 12:21:49 +1300
Links: << >>  << T >>  << A >>
Bob Perlman wrote:
> On 10 Nov 2004 13:30:48 -0800, wpiman@aol.com (MS) wrote:
> 
> 
>>I just got one of these Xilinx V4 tshirts that must have been vacuumed
>>sealed into a small package in the shape of a football.  It was so
>>small I thought it was a notepad.  Well- I opened this thing up- and
>>it was more wrinkled than prune.  It seriously looks damaged it was
>>crinkled up so tight.
>>
>>I haven't tried washing it yet.  Has anyone managed to get all the
>>wrinkles out?
> 
> 
> Forgive me for asking, but if you object to wearing a free, wrinkled
> T-shirt, are you absolutely certain you're an engineer?

:) - gets my BRBF* award, probably for the quarter
                            [*Best Riposte, by far..]
-jg


Article: 75601
Subject: Re: Research Project Re: Graphics Processor
From: "Kryten" <kryten_droid_obfusticator@ntlworld.com>
Date: Wed, 10 Nov 2004 23:43:51 GMT
Links: << >>  << T >>  << A >>
INMOS made a 2-D image processing chip.
I still have the databook (1989!).

Essentially it was a digital signal processor fully implemented in hardware, 
as opposed to DSP chips that are just microprocessor architectures optimised 
for DSP in software.

It looks like it could be implemented in today's FPGA chips relatively 
easily.








Article: 75602
Subject: Re: FPGA configuration download - How is it done?
From: yah3142002@yahoo.ca (Anonymous)
Date: 10 Nov 2004 15:51:22 -0800
Links: << >>  << T >>  << A >>
n.campregher@gmail.com (Nick) wrote in message news:<4aa6a8b3.0411020412.9b8eeaf@posting.google.com>...

> 
> If there is any paper or article describing this, I'd be glad if
> anyone could point it out to me.

Try http://citeseer.ist.psu.edu/462507.html and
http://www.eecg.toronto.edu/~pc/research/publications/lego1.tvlsi99.pdf

Article: 75603
Subject: Re: Advice on Contemporary Low cost, Medium Density CPLDs
From: mikeandmax@aol.com (Mikeandmax)
Date: 11 Nov 2004 00:44:37 GMT
Links: << >>  << T >>  << A >>
> requires a 30 something Combinational
>> Logic Block CPLD with 20ns delay. In the good old days, I would have
>> done this using several 22V10s.
>> 

Well, since you asked - Lattice offers free tools,downloadable from our
website, and supports schem, abel, vhdl, verilog - incodes a free simulator as
well, and we do have distributors in NZ - TQFP and PLCC are available in the
various families -
voltage from 1.8v thru 5v - several different families to choose from - all are
JTAG programmable, and programming cables can be bought online ~$65 US -

hope this helps-
Mike Thomas
LSC FAE NY/NJ



Article: 75604
Subject: Re: VirtexII-Pro MGT: 8/10 coding bypass problems
From: herwin@ee.ucla.edu (Herwin)
Date: 10 Nov 2004 17:37:28 -0800
Links: << >>  << T >>  << A >>
"Josh Model" <model@ll.nospam.mit.edu> wrote in message news:<6aukd.43$1T1.20@llnews.ll.mit.edu>...

> Couple of questions to start off with...
> What's your receiver?  If you're receiving into another MGT in the same
> chip, does it use the same or independant clocking resources?
> 
> My guess is that you're exceeding jitter tolerance or frequency accuracy
> somewhere.  The REFCLK tolerance is pretty tight,
> 
> --Josh


Currently I am receiving onto another MGT on the same chip and clocked 
by the same reference clock.  The clock that I am using is rated as 
50MHz with stability of +/-50ppm.  This should give about 2ps of jitter 
which is way below the spec of 50ps.

Is it possible for noise on the power supply to have such a large influence?
I will try again with a higher quality power supply and see what comes up.

--Herwin

Article: 75605
Subject: DDR Mux - how does it work?
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 10 Nov 2004 20:04:53 -0600
Links: << >>  << T >>  << A >>
I'm looking at the IOB diagram for Spartan3.  The output
path has a block labled "DDR MUX" that seems like it should
do the obvious thing.

It's got two inputs - the data bits.

How does it know when to switch?  Does it get both clocks
too, through some path that isn't shown?

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 75606
Subject: Re: VirtexII-Pro MGT: 8/10 coding bypass problems
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 10 Nov 2004 20:06:52 -0600
Links: << >>  << T >>  << A >>
>Is it possible for noise on the power supply to have such a large influence?
>I will try again with a higher quality power supply and see what comes up.

I'd expect the bypassing on the board would be more important than
the actual power supply.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 75607
Subject: Re: Xilinx Tshirts in football package.....
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Thu, 11 Nov 2004 02:22:53 -0000
Links: << >>  << T >>  << A >>
"MS" <wpiman@aol.com> wrote in message 
news:f0ddfdfb.0411101330.59a4ccdd@posting.google.com...
>I just got one of these Xilinx V4 tshirts that must have been vacuumed
> sealed into a small package in the shape of a football.  It was so
> small I thought it was a notepad.  Well- I opened this thing up- and
> it was more wrinkled than prune.  It seriously looks damaged it was
> crinkled up so tight.
>
> I haven't tried washing it yet.  Has anyone managed to get all the
> wrinkles out?

I got an Altera Excalibur one at a seminar, compressed into a small cube. 
The wrinkles came out after I'd worn it (wrinkles and all) and washed it.

Leon 



Article: 75608
Subject: Xilinx Webpack, simulate with off-chip-connected-pins? (VHDL)
From: "vax, 9000" <vax9000@gmail.com>
Date: Wed, 10 Nov 2004 22:04:15 -0500
Links: << >>  << T >>  << A >>
  Hi group,
  Sorry to bother you again. I am developing code for a hobby project and I
need to simulate my design with some off-chip-connected-pins. For example,
I generate a secondary clock on chip, output it from a pin, and feed it
into another pin (dedicated clock pin). How do I simulate it? Where do I
tell the simulator that the two pins are connected? I guess one possible
place is the test bench vhdl source file, and another possible place is the
simulator command lines where I 'force' the input pins. I googled and it
seemed that I could not find a good combination of words to dig out the
answer. I am reluctant to rewrite the code and connect the signals on chip,
because I want to use the dedicated clock pin. 
  Thank you.

vax, 9000

Article: 75609
Subject: Re: Timing Issues in Quartus design
From: "Subroto Datta" <sdatta@altera.com>
Date: Thu, 11 Nov 2004 03:11:21 GMT
Links: << >>  << T >>  << A >>
If you have backannotated your placement assignments to labs, I would 
recommend removing them along with any Logic Lock regions that you may hae 
created and recompiliing the design. Also make sure that you have provided 
proper timing constraints for the critical paths in your design. You should 
try floorplanning only after you have completed the above two steps and your 
logic is frozen.

- Subroto Datta
Altera Corp.

"pjjones" <hjones1380@hotmail.com> wrote in message 
news:2e1d5e40.0411101135.71d53862@posting.google.com...
> I'm facing some timing problems and I'm not really sure how to
> proceed.
>
> In this design, there is a Nios processor, and a good bit of
> supporting components to interface with an external DSP (close to
> 9,000 LEs total).  There are two UART/fifo components (written
> in-house) to support communication between the DSP and some other
> components.  There were no problems until I added a third UART -- now
> there are lots of timing problems.  The timing report indicates slack
> times up to 30ns (on a clock that is 60Mhz).  The weird part is that
> after I deleted the additional component the timing problems still
> remain.  I even reverted back to the previous version from CVS, but
> the timing problems still remain (and I know the version checked into
> the CVS server had no timing problems two days ago).
>
> What are the best steps to take to iron out timing problems?  Is it
> worth doing some floorplanning?  or is there maybe something more
> obvious that I'm overlooking?
>
> thnx,
> -P 



Article: 75610
Subject: Re: VirtexII-Pro MGT: 8/10 coding bypass problems
From: mrand@my-deja.com (Marc Randolph)
Date: 10 Nov 2004 19:17:29 -0800
Links: << >>  << T >>  << A >>
herwin@ee.ucla.edu (Herwin) wrote in message news:<6314bb40.0411101033.43e00fd4@posting.google.com>...
[...]
> Here is the situation.  Using a 50Mhz oscillator I am trying to
> achieve a channel bit rate of 1Gbps in 8/10 bypass mode.  For every 20
> bits, I am transmitting 5 'ones' in random positions.  This should
> ensure that I have at least 1 transition every 20 bits and enough for
> the PLL to lock on to the clock.  What I am seeing is that the bit
> error rate is very high (>0.1).  This is the case even when I set the
> MGT to serial bypass mode.  What can be the cause of this since this
> configuration introduces no transmission losses?

Howdy Herwin,

I'm not sure what serial bypass mode is - did you mean 8b/10b bypass?

What are your results using serial loopback?  How about parallel
loopback?  If either has trouble, focus on that before trying to
traverse the PCB (remeber that serial loopback still requires
terminations on the _tx_ interface).  Also, with a 50 MHz clock, I
assume you have SERDES_10B set to its default "FALSE".

The CDR in the Rocket I/O can handle at least 75 consecutive identical
digits, so at least by itself, I doubt that is your problem.  But, if
you had termination problems, I could maybe see how consecutive digits
might influence BER like you have.

> The BER decreases as the number of 'ones' increase.  At 10 'ones', I
> am seeing BER of <10e-12.  Where should I start in trying to solve
> this problem?
> 
> I would appreciate any help that anyone can give me.

As the other responder mentioned, the jitter requirements are a little
on the tight side.  Another thing that could really throw a wrench
into the situation is using a PLL-based clock as the reference - some
fanout buffers, especially zero delay ones, use PLL's.  Where is the
reference clock coming from (including the original source, through
what device(s), into which pin, and across what nets on the FPGA)?

Good luck,

   Marc

Article: 75611
Subject: Re: Xilinx Webpack, simulate with off-chip-connected-pins? (VHDL)
From: "vax, 9000" <vax9000@gmail.com>
Date: Wed, 10 Nov 2004 22:35:47 -0500
Links: << >>  << T >>  << A >>
A somehow related question is, how do we simulate an interconnected two-chip
design in Xilinx Webpack? My design fits in two XC95144XL CPLD's and I'd
like to simulated the post-fit design. Thanks.

vax, 9000 wrote:

>   Hi group,
>   Sorry to bother you again. I am developing code for a hobby project and
>   I
> need to simulate my design with some off-chip-connected-pins. For example,
> I generate a secondary clock on chip, output it from a pin, and feed it
> into another pin (dedicated clock pin). How do I simulate it? Where do I
> tell the simulator that the two pins are connected? I guess one possible
> place is the test bench vhdl source file, and another possible place is
> the simulator command lines where I 'force' the input pins. I googled and
> it seemed that I could not find a good combination of words to dig out the
> answer. I am reluctant to rewrite the code and connect the signals on
> chip, because I want to use the dedicated clock pin.
>   Thank you.
> 
> vax, 9000


Article: 75612
Subject: Re: Research Project Re: Graphics Processor
From: DerekSimmons@FrontierNet.net (Derek Simmons)
Date: 10 Nov 2004 20:12:24 -0800
Links: << >>  << T >>  << A >>
What's the part number? I know about the G300 and its predecessors but
they were just a display controller (you could setup various
resolutions and color depths). If you are referring to the T4xx/T8xx
transputers they could be used as a display controller but it didn't
really contain any specialized instructions for displays or graphics.
The Intel i860 had instructions designed for computer graphics and
displays. SGI even used it in their Reality Engine and Reality Engine
2. It was later replaced in the Infinite Reality Engine with ASICs.

In the early 1980's NEC made the 7220 a graphic display processor
(GDP) capable of display 4096 x 4096 with as many colors as your video
DAC supported. It had functions for text, cursors and 2D operations.

In the late 1980's Intel came out with the 82786 Graphics Coprocessor.
I never worked with it so I can't comment on it.


"Kryten" <kryten_droid_obfusticator@ntlworld.com> wrote in message news:<XIxkd.2164$Uq5.563@newsfe3-win.ntli.net>...
> INMOS made a 2-D image processing chip.
> I still have the databook (1989!).
> 
> Essentially it was a digital signal processor fully implemented in hardware, 
> as opposed to DSP chips that are just microprocessor architectures optimised 
> for DSP in software.
> 
> It looks like it could be implemented in today's FPGA chips relatively 
> easily.

Article: 75613
Subject: Re: C Compiler for Picoblaze !!!!!
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Wed, 10 Nov 2004 20:35:25 -0800
Links: << >>  << T >>  << A >>
I would be interested in the compiler especially if the sorce code were
available.



Article: 75614
Subject: Re: Research Project Re: Graphics Processor
From: DerekSimmons@FrontierNet.net (Derek Simmons)
Date: 10 Nov 2004 21:03:02 -0800
Links: << >>  << T >>  << A >>
I'm also working on a similar project for my personal interest. I
found these website that might be of interest to you:

No source but very informative:
http://www.saarcor.de/

Not much going on with it at the moment. If I remember right they have
taken the project in a new direction.
http://icculus.org/manticore/links.php

This one is currently broken but it was an example of a graphics
pipeline and they included the source files. Hopefully it will be
fixed soon.
http://www.cs.unc.edu/~robbins/comp290-52/Project/index.html

It's in German but looks very impressive:
http://www.tu-harburg.de/ti6/lehre/soc/ws03/3dprojektkorr.html

If you find any interesting links I'd be interested hearing about
them.

Derek

Article: 75615
Subject: Re: Xilinx Tshirts in football package.....
From: Prasanth Kumar <lunix@comcast.net>
Date: Thu, 11 Nov 2004 05:19:45 GMT
Links: << >>  << T >>  << A >>
On Wed, 2004-11-10 at 13:30 -0800, MS wrote:
> I just got one of these Xilinx V4 tshirts that must have been vacuumed
> sealed into a small package in the shape of a football.  It was so
> small I thought it was a notepad.  Well- I opened this thing up- and
> it was more wrinkled than prune.  It seriously looks damaged it was
> crinkled up so tight.
> 
> I haven't tried washing it yet.  Has anyone managed to get all the
> wrinkles out?

It is okay after you wash it twice.



Article: 75616
Subject: Re: Xilinx Tshirts in football package.....
From: "starfire" <starfire151@cableone.net>
Date: Wed, 10 Nov 2004 22:23:29 -0700
Links: << >>  << T >>  << A >>
I love it!

Dave

"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message 
news:0j55p0hkvo3d5e8cvuq59v8c2tp141sk9u@4ax.com...
> On 10 Nov 2004 13:30:48 -0800, wpiman@aol.com (MS) wrote:
>
>>I just got one of these Xilinx V4 tshirts that must have been vacuumed
>>sealed into a small package in the shape of a football.  It was so
>>small I thought it was a notepad.  Well- I opened this thing up- and
>>it was more wrinkled than prune.  It seriously looks damaged it was
>>crinkled up so tight.
>>
>>I haven't tried washing it yet.  Has anyone managed to get all the
>>wrinkles out?
>
> Forgive me for asking, but if you object to wearing a free, wrinkled
> T-shirt, are you absolutely certain you're an engineer?
>
> Bob Perlman
> Cambrian Design Works
> 



Article: 75617
Subject: Re: VirtexII-Pro MGT: 8/10 coding bypass problems
From: "RobJ" <rsefton@abc.net>
Date: Wed, 10 Nov 2004 22:10:47 -0800
Links: << >>  << T >>  << A >>
"Herwin" <herwin@ee.ucla.edu> wrote in message 
news:6314bb40.0411101737.7fabcb9@posting.google.com...
>
> Currently I am receiving onto another MGT on the same chip and clocked
> by the same reference clock.  The clock that I am using is rated as
> 50MHz with stability of +/-50ppm.  This should give about 2ps of jitter
> which is way below the spec of 50ps.
>
> Is it possible for noise on the power supply to have such a large 
> influence?
> I will try again with a higher quality power supply and see what comes up.
>

Herwin -

+/-50ppm is an accuracy rating and has nothing to do with jitter. You'll 
have more than 2ps of jitter on that clock by the time it hits the MGT. Not 
saying jitter is your problem, just pointing out that you may want to take a 
closer look at it.

Rob 



Article: 75618
Subject: multiplexer / serdes
From: "Leroy Tanner" <ikeepthespiritalive@freenet.de>
Date: Thu, 11 Nov 2004 08:07:46 +0100
Links: << >>  << T >>  << A >>
Dear newsgroup readers,

I am currently working on a multiplexer design in VHDL. For the time being
the design should run on a Xilinx Virtex II FPGA but actually I am not
concerned about any target device later on. My question is more general.
What I want to do is multiplex four input signals into one output signal,
meaning that there are four parallel inputs that should merge into one
serial output. Therefore the output must be four times faster than the
input, right? I see problems in generating the faster clock out of the
master clock of the slower inputs, that means I HAVE TO provide the fast
clock for the serial output right away and then transform it back to the
slower to handle the input, is that right?
What's more I want to multiplex the signals byte-wise. How can that be
achieved WITHOUT wasting a great amount of registers? And how to manage the
data being transfered between the two clock domains?

Regards, Leroy



Article: 75619
Subject: Re: hostid for Actel Designer
From: georgevarughese@indiatimes.com (geoerge)
Date: 10 Nov 2004 23:11:40 -0800
Links: << >>  << T >>  << A >>
Hi Hans,

"Hans" <hansydelm@no-spam-ntlworld.com> wrote in message news:<Ummkd.56$Us1.52@newsfe5-win.ntli.net>...
> Did you manage to install Designer on Slackware? I tried it on my Gentoo 
> machine but it complained about the ksh interpreter,

  I got it working partially. designer pops up a gui and I was able to
start the compile session. But that was it, it crashed then. lmgrd
message says the designer was able to get the license.

  Later I decided to install RH9 and try it again. This time I faced
the same issue of ksh, but I copied it to where the install shell was
looking for it and got everything installed fine. I got designer
running all the way to place and route. One difficulty I had was that
I didn't had a synthesis software giving edif output suitable for
designer.

  First I tried icarus verilog, but the output lacked instantiated
pads. Also it adds some macros that are actel reserved ( like and2 etc
). Then I tried a simple hand written verilog netlist and got it
compiled, placed and routed. Everything went fine.

  It is sad that there is no license to run the software further. It
is not possible to program an fpga (download it to the chip ) with the
eval license  they are giving. Hope they will change the licensing
terms and let linux also get an years free license!!

On the sythesis side:

  I am hoping that the vhdl compiler that comes with Alliance vlsi
tools will be usable by designer. It gives out a vhdl netlist, and I
hope designer will accept it. Got to try it though. Probably one will
have to use some script to insert pads on the top level netlist before
feeding the synthesised netlist to designer. ( As for icarus, there is
only edif,xnf out but there is no verilog netlist output. I find
verilog output easy to hack :-) This is really sad.)

Thanks,
George

Article: 75620
Subject: VHDL is correct but when burn into chip is not correct. Help me to solve this problem please
From: suntthekid@gmail.com (suntthekid)
Date: 10 Nov 2004 23:12:08 -0800
Links: << >>  << T >>  << A >>
I simulate vhdl code in modelsim and then it is correct. but, when i
burn this code into FPGA chip (Stratix S25F672C6) it's wrong (i saw a
signal in signaltap and found it 's wrong)
   so i want everybody who know this problem help me to solve this
problem
                                           thank you

Article: 75621
Subject: Rocket IOs and Infiniband protocol
From: "Quinn Johnson" <quinn_the_esquimo@freenet.de>
Date: Thu, 11 Nov 2004 08:34:29 +0100
Links: << >>  << T >>  << A >>
Dear newsgroup readers,

I am currently trying to set up an Infiniband protocol on a Virtex 2 Pro.
Therefore I use the dedicated multi gigabit transceivers (Rocket I/O s). My
problem is that after finishing the link layer and testing the
implementation in serial loopback mode I always get the error message from
my testbench program that the synchronization gets lost.
I already worked on several "standard" implementations and I often
encountered false descriptions in the standard paper. Since the
implementation is exactly based on the  "Infiniband Architecture
Specification Release 1.1" I wonder if there is already a mistake in the
description? Or maybe there is another point that is not obvious I just
overlooked?
I would like to share my experience and knowledge with other developers who
are also familiar with the Infiniband protocoll and its implementation to
solve my problem. Any help is appreciated.

Regards, Quinn



Article: 75622
Subject: Re: Research Project Re: Graphics Processor
From: =?ISO-8859-1?Q?Jan_Vorbr=FCggen?= <jvorbrueggen-not@mediasec.de>
Date: Thu, 11 Nov 2004 10:06:05 +0100
Links: << >>  << T >>  << A >>
> What's the part number?

I think it was A100 and/or A110.

	Jan

Article: 75623
Subject: Re: Where to find very basic FPGAs
From: Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com>
Date: Thu, 11 Nov 2004 10:12:30 +0100
Links: << >>  << T >>  << A >>

What about the Avnet Virtex-4 kit ?

http://www.em.avnet.com/evk/home/0,4534,CID%253D16863%2526CCD%253DUSA%2526SID%253DNoNav%2526DID%253DDF2%2526LID%253D4746%2526BID%253DDF2%2526CTP%253DEVK,00.html


299$ For a virtex 4 sounds ok. It's only 3x the price of the spartan3 starter kit and has lots of stuff.



Sylvain

Article: 75624
Subject: Problem with PLL ?
From: ALuPin@web.de (ALuPin)
Date: 11 Nov 2004 02:11:07 -0800
Links: << >>  << T >>  << A >>
Hi newsgroups users,

maybe someone has experienced the following problem:


I have a HDL design in which a PLL is instantiated (QuartusII).

To test the functionality of the PLL I made a smaller design
containing exactly the same PLL. 
For the small design I have found out that the PLL does work.

When I compile my original design I can see that the PLL does not
work.

As I said the pin assignments and pll assignments are exactly the same.

Where could be the problem?

Unused pins are set to ground.
There are also defined input pins which are not used. Could it be
that the fitter does produce some strange combintation of
setting the unused input pins to ground so that some driver
conflict exists ?

Thank you for your help.

Kind regards

André



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2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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