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Antti Lukats wrote: > "Jedi" <me@aol.com> schrieb im Newsbeitrag > news:xn8ue.45$K76.41@read3.inet.fi... > > > jtag discovery tool? which one do you mean? > > the 0x0E is defenetly "the" USER instruction it should be 'Open' when device > is unconfigured.. Erased SPI config memory..now correctly showing: Detecting DR length for IR 0000001100 ... -1 Detecting DR length for IR 0000001110 ... -1 And both returning same preloaded 8-bit shift register: Device Id: 00000010000010000100000011011101 Manufacturer: Altera Part: EP1C20F400 Stepping: 0 Filename: /usr/local/share/jtag/altera/ep1c20f400/ep1c20f400 Setting TCK frequency to 2 Hz jtag> instruction IR1100 jtag> shift ir jtag> shift dr jtag> dr 01101111 jtag> instruction IR1110 jtag> shift ir jtag> shift dr jtag> dr 01101111 jtag> rickArticle: 86126
Ben Jones wrote: >>I don't think >>that FPGA would ever be the right choice for this type of volume >>applications. If I plan to sell one million of units, I don't care much if >>I have to spend one million dollars for ASIC setup, if then one chip will >>cost one dollar (ASIC) instead of ten (FPGA). > > > Look at the trend in the cost of ASIC setup. Compare that with > the trend in FPGA gates-per-dollar. Look five years ahead. Now > consider a choice between ASIC setup of $2M and an FPGA > costing $3. Which would you choose? Once you've had to do a > couple of re-spins because your design wasn't quite right first time, > your FPGA is looking very cheap. And that's before you factor in > the time-to-market advantage. > > Making chips is really hard, and is getting harder. More and more > companies are realizing that it makes good business sense to let > somone else take the hit on sub-micron design, qualification and > testing. This leaves their engineers more time for inventing things > that actually add value. > > Me? I think FPGAs will kill cell-based ASIC within ten years. > How's that for optimism? :-) A more interesting question, is when will we see the first MicroBlaze or Nios in FPGA silicon [not as a soft-cpu]? They are getting close to stable enough to do this. Or, when we will see a soft-boundary HardCopy - where you can move only PART of the total design into ASIC, and keep the rest as a smaller FPGA. -jgArticle: 86127
> A more interesting question, is when will we see the first MicroBlaze
> or Nios in FPGA silicon [not as a soft-cpu]?
> They are getting close to stable enough to do this.
True, although I don't see much value in that approach. Those architectures
were designed with FPGA as the target technology, so mapping them
straight to silicon might not give the best results. What's wrong with the
PowerPC core?
> Or, when we will see a soft-boundary HardCopy - where you can move
> only PART of the total design into ASIC, and keep the rest as a smaller
> FPGA.
Developing and testing your design in FPGA and then hardening it just before
putting it into mass production is rather like wearing a life-jacket in the
harbour
and then throwing it overboard as you set out to sea...
-Ben-
Article: 86128"Peter Alfke" <peter@xilinx.com> wrote in message news:1119388217.456102.160260@o13g2000cwo.googlegroups.com... > Symon, I sent you a lengthy private response. > If you want to share some of it, be my guest... > Peter Alfke > Peter, Much appreciated! For the record, I found the pertinent part of the response is :- Since the designer is not registering the output, there is no way to force the tool to use the T2 pin. If the designer was using the register then it would be possible to use one of the following BEL constraints to force the tools to use the T2. There is not BEL for the Asynch path so there is no way to constrain it. I do believe though, that the designer feels that the T2 pin is faster because of the location of the source. I believe if the designer were to change the placement of the source then he could get the faster path for the T1 pin. I did find a better placement for one instance of my design; only two instances left to analyse! The differences between the instances are because of the different combinations of IOBs used within the sets of four IOBs in each row in the FPGA array. Probably! Thanks again, Syms.Article: 86129
Ben Jones wrote: >> A more interesting question, is when will we see the first MicroBlaze >>or Nios in FPGA silicon [not as a soft-cpu]? >> They are getting close to stable enough to do this. > > > True, although I don't see much value in that approach. Those architectures > were designed with FPGA as the target technology, so mapping them > straight to silicon might not give the best results. They already license it for ASICs, so it's mainly a question of when it will appear, not if. eg Why do we have HW multipliers & DSP blocks now ? - because they are much faster, and lower power, than FPGA fabric solutions. > What's wrong with the PowerPC core? Let's see - Price, die area.... > >> Or, when we will see a soft-boundary HardCopy - where you can move >>only PART of the total design into ASIC, and keep the rest as a smaller >>FPGA. > > > Developing and testing your design in FPGA and then hardening it just before > putting it into mass production is rather like wearing a life-jacket in the > harbour and then throwing it overboard as you set out to sea... Which is why you might want move the proven stuff into HardCopy (or whatever), and keep the smaller, fluid portion, in FPGA. -jgArticle: 86130
Interesting!
> eg Why do we have HW multipliers & DSP blocks now ? - because they
> are much faster, and lower power, than FPGA fabric solutions.
They are also functions with a broad usefulness in a variety of
applications.
The "faster and lower power" argument can be applied to any piece of IP
you care to name; just for certain functions the transition to hard silicon
makes sense - multipliers, DSP, SERDES, Ethernet MACs, etc. I'm not
quite convinced (yet!) that this is true of MicroBlaze/Nios (yet!).
> > What's wrong with the PowerPC core?
> Let's see - Price, die area....
The price premium of FPGAs with hard processor IP is artificial and it
will be eroded in time. The efficiency of a hard microblaze/Nios in terms
of MIPS/mm^2 will surely, surely be much worse than that of a
processor core that was designed specifically for 90nm.
> > Developing and testing your design in FPGA and then hardening it just
before
> > putting it into mass production is rather like wearing a life-jacket in
the
> > harbour and then throwing it overboard as you set out to sea...
> Which is why you might want move the proven stuff into HardCopy (or
> whatever), and keep the smaller, fluid portion, in FPGA.
"Proven" has always been a relative term. By the time you've "proved" that
your design is perfect, it's most likely a bit late to be ordering mask
sets.
Was your "soft-boundary" idea intended to stay on a single die? That would
certainly be interesting, maybe even useful in limited contexts.
-Ben-
Article: 86131"Jon Elson" <jmelson@artsci.wustl.edu> wrote in message news:42B89AB2.5040006@artsci.wustl.edu... > > > Johnson Liuis wrote: > >>Does anybody have filter design experience with FPGA? I would like to know >>a general picture with recent FPGA technologies like XtremeDSP and others. >>I am also curious about the limitation of FPGA design on filter design, >>like the maximum center frequency and bandwidth of the filters that can be >>implemented with FPGA. Could anybody let me know if I am able to simulate >>a SAW (surface acoustic wave ) filter with 185MHz center frequency >> > Well, the Nyquist criteria indicates you will need an ADC operating at > above 370 Megasamples/second, Hmm, SAW filters are generally used in narrow bandpass applications. The Nyquist criterion says you need a sample rate double the bandwidth you're interested in. It may be that you can reduce the necessary sample rate considerably by only focussing on the band of interest. At the very least, once you've sampled the data, you could decimate considerably to concentrate your processing on the band of interest. I suggest reading about multirate DSP. Cheers, Syms.Article: 86132
Hello Guys, I am finding difficult in probing virtex 2pro using chipscope. I am using chipscope pro logic inserter. I have following doubts regarding it 1. In my top module (also netlist)i have any IP core which i have integrated and its black box IP(EDF netlist).I cannot see the black box IP in the TOP module in chipscope but its present in TOP module Netlist. I can view all the module except the netlist module . So i am not able to connect the signal of EDF IP to trigger signal. Why is it so?? 2. Can i not connect the IO port signal of TOP module to triggering signal of chipscope?. When i connected it gives error in implementation saying multiple drive. Is any other way to view the IO port signal along with the internal signal. Thanks and regards, WilliamsArticle: 86133
Hi All,
I am stuck with some JTAG interconnection tests on a board with 9 Xilinx
V2Pros and 2 Altera Stratixs.
I am using JTAG Technologies VIP Manager for the tests.
Somehow the tool / software is getting into errors as it sees 1's on the
GND net. I have digged into all possibilities as far as the software and
test generation is concerned but am unable to find the source. Maybe the
problem is on the hardware but the board works fine even if its failing the
JTAG Tests.
I know this is not the best place to put this question, but the support from
JTAG has been patchy ("you are not the only customers we have" kind of
response) and I feel that since a lot of you do board design and test, maybe
some of you can give me some pointers.
Thanks to all....
Adarsh Kumar Jain
CERN, Geneva
Article: 86134Hi All, can some one guide me setting ucf for DLLs.I am using clkx2,clkx4,clkx8.The board I am suing is spartan 2 FPGA,Xc2s200 PQ208.I got the below errors. ERROR:Place - Could not find an automatic placement for the following components: clock of type GCLK IOB is placed at GCLKPAD3 dll2x of type DLL is unplaced clk2xg of type GCLK BUFFER is unplaced dll4x of type DLL is unplaced clk4xg of type GCLK BUFFER is unplaced dll8x of type DLL is unplaced clk8xg of type GCLK BUFFER is unplaced Xilinx requires using locate constraints to preplace such connected GCLK/GCLKIO/DLL components. Best Regards, SriArticle: 86135
Did you search the Xilinx answer database? I guess you didn't find answer record 9469. ;-) Cheers, Syms. "sri" <sri_poddaturu@yahoo.com.au> wrote in message news:ee8f2c4.-1@webx.sUN8CHnE... > Hi All, > > can some one guide me setting ucf for DLLs.I am using > clkx2,clkx4,clkx8.The board I am suing is spartan 2 FPGA,Xc2s200 PQ208.I > got the below errors. > > ERROR:Place - Could not find an automatic placement for the following > components: clock of type GCLK IOB is placed at GCLKPAD3 dll2x of type DLL > is unplaced clk2xg of type GCLK BUFFER is unplaced dll4x of type DLL is > unplaced clk4xg of type GCLK BUFFER is unplaced dll8x of type DLL is > unplaced clk8xg of type GCLK BUFFER is unplaced Xilinx requires using > locate constraints to preplace such connected GCLK/GCLKIO/DLL components. > > Best Regards, SriArticle: 86136
Hi all, Iam using ml310 board and in my design Iam using two PPC 's. To my needs I want to collect the addresses of the instructions executed on PPC 1. I run application on PPC1 and collects Program counter data and writes to FIFO. Later I want to put halt (execution break) to PPC1 and through PPC2 I want to collect these data from FIFO. to place PPC1 in halt mode I raised pin called DBGC405BEBUGHALT to 1....but I found PPC never stops execution...its continuing normally. Later I tested by raising pin DBGC405UNCONDDEBUGEVENT ...then also I observe the same. do someone of you kindly suggest me why it happens? and how can I place PPC in halt mode. is it possible to trace Program counter by some other means? thank you for your time and consideration. regards JagguArticle: 86137
Is this your top entity? If not, you have to use the full path, i think this is called "traversing hierarchy" in XST manual. Also, this instance may be optimized away from the design during synthesis Vladislav "P. Royla" <Nightstorm@gmx.ch> wrote in message news:d9b50a$uhh$1@hermes1.rz.hs-bremen.de... > Hello, > > I made an Entity with an Process using Xilinx 7.1 . > > Then made: > > GEN_A : GenInt > port Map ( > clk_prg_i => clk_prg_i , > res_i => res, > high_o => high_Gen, > low_o => low_Gen); > > > In UCF-File: > > inst "GEN_A" AREA_GROUP=Group_A; > AREA_GROUP "Group_A" RANGE=SLICE_X3Y1:SLICE_X33Y33; > > > and became the following error: > > NgdBuild:753 - Line 41 in 'LFSR_CS_Test.ucf': Could not find instance(s) > GEN_A' in the design. To suppress this error specify the correct instance > name or remove the constraint. > > I need Help with this Error. > > Thanks > > Peer > > >Article: 86138
"Jedi" <me@aol.com> schrieb im Newsbeitrag news:hK9ue.71$K76.70@read3.inet.fi... > Antti Lukats wrote: > > "Jedi" <me@aol.com> schrieb im Newsbeitrag > > news:xn8ue.45$K76.41@read3.inet.fi... > > > > > > jtag discovery tool? which one do you mean? > > > > the 0x0E is defenetly "the" USER instruction it should be 'Open' when device > > is unconfigured.. > > Erased SPI config memory..now correctly showing: > > Detecting DR length for IR 0000001100 ... -1 > Detecting DR length for IR 0000001110 ... -1 > > And both returning same preloaded 8-bit shift register: > > Device Id: 00000010000010000100000011011101 > Manufacturer: Altera > Part: EP1C20F400 > Stepping: 0 > Filename: /usr/local/share/jtag/altera/ep1c20f400/ep1c20f400 > Setting TCK frequency to 2 Hz > jtag> instruction IR1100 > jtag> shift ir > jtag> shift dr > jtag> dr > 01101111 > jtag> instruction IR1110 > jtag> shift ir > jtag> shift dr > jtag> dr > 01101111 > jtag> > > > rick look in MAX2 datasheet there are USER0 and USER1 defined !! I did not know ! AnttiArticle: 86139
Well I would say for their time the 8086, Z8000, 68k were all reasonably well crafted as VLSIs go, but all in different ways, I know this for a fact since I got to reverse engineer them transister by transister at least for the more repeated or interesting blocks and all very different styles of circuit and logic design too. At the time Intel had a budget of around 17K devices, Motorola on the other hand budgeted around 60k or so though alot of that was microcode rom. That also meant the 68k was bound to cost several times what the 8086 did which didn't matter much to workstation vendors at the time. As for architecture Intel was only upgrading the 8080 to a 16bit arch, it was not intended to be the entire future of the world computing as it presently is, blame IBM for that, but then no one sees much further than 2-3 years do they. Intel was aiming the 432 for that purpose. The 68K had the luxury of not being backwards compatible with anything and had a fair bit of clean design. Remarkably all these design teams had very little CAD available to them for most of the general designs except for spice for absolutely critical cells, and layout digitizing. Today a novice designing an FPGA cpu could do billions of times more logic & arch simulations. Thats why those designs had 200 man years in them. johnjakson at usa dot comArticle: 86140
hi Altera is the one that likes to claim many things, one of those was that Altera was the first PLD vendor supporing IEEE 1532 That was new Loong time ago already, as of today, as of Altera web info: IEEE1532 enabled devices are: *MAX7k *EPC8 thats about it. in MAX2 datasheet there is mere notice that the ISC instruction codes for MAX2 ieee1532 programming will be published on altera website (as part of downloadable BSDL files) checked today, the BSDL files are available but they do not support IEEE1532 so Altera has been simple BS the customers - or maybe there is a secret place for MAX2 IEEE1532 information ??? AnttiArticle: 86141
Hallo, I followed what you said. I have made a for cicle to write to video the addresses and sequential addreesses are, in example (decimals -> hex): 1998595456 -> 77200000 1998605056 -> 77202580 How is it possible? Second should be 77200001, I think. I have tried also to copy data into one address: (*display)[y][x] = 0xFF; But when I print to video (*display)[y][x] I see 0, not 255. How is it possible? Many Thanks MarcoArticle: 86142
On the xilinx's site I get 0 results when browsing the section of boards :( Any other propositions ?Article: 86143
Hi, I have some questions regarding the following piece of code... In the AHDL code, the following variable is declared as below: HDET_REG : DFF; Its been used in the code as follows: HDET_REG.CLK = DIGRESET; HDET_REG.D = VCC; HDET.REG.CLRN = !HDET; My question is that....how does this DFF work How does CLRN affect the output HDET_REG.Q Any help is greatly appreciated. Thank you, MethiArticle: 86144
Typically, program counter information is collected by external tools through the processor's trace port. The ML310 has such a trace port and tools can be bought from 3rd parties, for example RiscWatch from IBM. Asserting DBGC405BEBUGHALT does halt the processor. You might want to check the logic you are using. Other methods to stop the processor are writing a 1 to MSR[WE] from software or through an external debugger. However, for the first method you will need an interrupt to get the processor out of sleep mode. - Peter jaggu wrote: > Hi all, Iam using ml310 board and in my design Iam using two PPC 's. To my needs I want to collect the addresses of the instructions executed on PPC 1. I run application on PPC1 and collects Program counter data and writes to FIFO. Later I want to put halt (execution break) to PPC1 and through PPC2 I want to collect these data from FIFO. > > to place PPC1 in halt mode I raised pin called DBGC405BEBUGHALT to 1....but I found PPC never stops execution...its continuing normally. Later I tested by raising pin DBGC405UNCONDDEBUGEVENT ...then also I observe the same. > > do someone of you kindly suggest me why it happens? and how can I place PPC in halt mode. > > is it possible to trace Program counter by some other means? > > thank you for your time and consideration. > > regards JagguArticle: 86145
>What do people in this forum see is the future of FPGA 4 to 5 years down the line? I see FPGAs displacing processors: http://www.fhpca.org/ http://www.celoxica.com/ http://fpgajournal.com/articles_2005/20050118_lang.htm >What are the applications it is most widely used right now, and what will be the applications that it will be highly used in a near future? Moving from parallel processing and custom control logic towards custom embedded applications; I do not mean software running on a soft/hard embedded processor but the actual application in its gate level representation (a gate level packet sorting and forwarding app _WITHOUT_ the RTOS overhead, etc.) >power and clock speed as major bottlenecks? I believe Moore's law has proven that processes and design methodologies have kept u:, I have very high expectations on the EDA/CAD vendors to continue providing ways to manage these. My $0.02, *** AlfredoArticle: 86146
Hi, I am trying to use MXE-III to simulate a design (Target V4-FX12) including a block memory core generated by Coregen (EBKMEMDP_V6_2). ModelSim DOES NOT initialize memory's value defined in generated "XXX.mif" file. Can anyone give some clues? This issue bother me 2 days. Thanks. AlphaArticle: 86147
In my project, which uses an Altera Cyclone EP1C12, I need to generate a lot of different frequencies, such as f=10Mhz, 1MHz, 2.5MHz, 250kHz, etc. I used counters but quartus' design assistant complains that I'm using gated clocks. Are there better solutions than counters to achieve what I need? Or better ways to implement frequency divisors? Thank you in advance, BQArticle: 86148
Hi, I have some questions regarding the following piece of code... In the AHDL code, the following variable is declared as below: HDET_REG : DFF; Its been used in the code as follows: HDET_REG.CLK = DIGRESET; HDET_REG.D = VCC; HDET.REG.CLRN = !HDET; My question is that....how does this DFF work How does CLRN affect the output HDET_REG.Q Any help is greatly appreciated. Thank you, MethiArticle: 86149
Philip Martel wrote:
> Yes, but it might be nice if most of these files were put into a
> subdirectory so they don't clutter up the project directory.
>
I agree that Xilinx should do this by default. On the other hand, it is
easy to set up your project so that this is done. For example, I have
the folder structure:
range_fpga -
|-range_hdl
|
|-range_ise
|
|-...
The range_ise folder contains the range_ise.npl project file, and all
the generated files.
When adding hdl files to the project, navigate to the *_hdl directory,
and add them. This results in entries in the *.npl file that look like:
SOURCE ../range_hdl/range_pkg.vhd
SOURCE ../range_hdl/ref_pkg.vhd
...
That keeps everything nicely separated.
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