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"Joseph Samson" <user@example.net> wrote in message
news:41aJf.33587$H71.19736@newssvr13.news.prodigy.com...
>
> GPIO outputs can drive internal logic. Sometimes it's easier than
> building an IPIF interface. I'm going to take a guess and say that you
> connected your internal logic input to the IOB instead of to the GPIO.
>
> Post the code if you want someone to figure it out.
Here it goes (with most of the unrelated stuff deleted):
entity top is
Port (
Led : out std_logic_vector(12 downto 1);
);
end top;
architecture top_rtl of top is
component system_stub is
port (
-- skip --
fpga_0_GPIO_LED_d_out_pin : out std_logic_vector(0 to 19);
-- skip --
);
end component;
signal gpio_leds : std_logic_vector(0 to 19);
signal led_tick : std_logic;
begin
PPC_INST: system_stub port map (
-- skip --
fpga_0_GPIO_LED_d_out_pin => gpio_leds,
-- skip --
);
LED_GEN:
for i in 0 to 7 generate
Led(i+1) <= gpio_leds(2*i) or (gpio_leds(2*1+1) and led_tick);
end generate;
end top_rtl;
Article: 97151Roggey schrieb: > My question is now how can i send data using the mac-layer only from a > c++ programm. That is a good question. I know what you are looking for. Normally people use the IP stack and every OS has its own implementation of that. I would be interested in that too, how to send data over the Ethernet. At least the people who implemented the IP stack had to know how to do it :) GuenterArticle: 97152
Hi, I do not want to SPAM all FPGA users, so I am posting this here. Xilinx's marketing department would like to have as much feedback on ESL (Electronic System Level) requirements from designers. Please let me know by next Tuesday, I am meeting Xilinx on Wednesday. Thanks, -- *** Alfredo.Article: 97153
On 17 Feb 2006 08:05:46 -0800, "GHEDWHCVEAIS@spammotel.com" <GHEDWHCVEAIS@spammotel.com> wrote: >Roggey schrieb: > >> My question is now how can i send data using the mac-layer only from a >> c++ programm. > >That is a good question. I know what you are looking for. > >Normally people use the IP stack and every OS has its own >implementation of that. > >I would be interested in that too, how to send data over the Ethernet. >At least the people who implemented the IP stack had to know how to do >it :) > >Guenter I think what you are looking for is a DLL which allows raw ethernet frames to be sent - I'm sure it must be possible, but may need to talk to the card at a low level and may be card-specific. It would also need to fight of Windows' own attempts to use it. This looks promising : http://www.rawether.net/Article: 97154
I couldn't find my notes quickly so I'll just ask the question: Are you certain that the dob_i and doa_i signals from the dual-port CLB SelectRAM - DPO and SPO, respectively - are on the correct pins (I1/I0) for the MUXF5? You could just try swapping I1/I0 for a quick check to see if the orientation is inverted from what you expect. "Sylvain Munaut" <com.246tNt@tnt> wrote in message news:43f5c215$0$19097$ba620e4c@news.skynet.be... > Hello, > > I'm trying to pack something into two SLICEs and the tools don't get it > ... I get map error. And it should be possible to do what I want since I > can "draw" it in the FPGA editor. > (I'm using ISE7.1 sp4 and I target spartan 3) > > What I'm trying to pack a a dualport distributedram (RAM16X1D) and a 5:1 > mux in two slicesM, one above the other. > > On the first slice (top one) is the classic RAM16x1D stuff. On this same > slice, I want to place a F5Mux between the two output of the DRAM, > commanded by BX (actually, BX will be forced to 1, I just want the > second output of the distributed ram on the F5 output pin). > > On the second slice (bottom one), I get a 4:1 mux done with the two LUTs > + the F5 on the slice. And on the same slice, I want to use the FX mux > to mux between either the output of the F5 of this slice, or the F5 out > pin of the slice above. > > > The VHDL code I write as test is givent at the end of the post and also > available there : http://pastebin.com/559361 > > > The error I get : > > --- > ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=reg, > RLOC=X0Y1) > which require the combination of the following symbols into a single > SLICEM > component: > RAMDP symbol "memcell_I" (Output Signal = dob_i) > MUXF5 symbol "f5_I" (Output Signal = fxb) > The function generator memcell_I is unable to be placed in the G > position > because the output signal doesn't match other symbols' use of the G > signal. > The signal dob_i already uses G. Please correct the design constraints > accordingly. > ---- > > > Any idea how to make the tool understand ??? > > > Sylvain > > > > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > > library unisim; > use unisim.vcomponents.all; > > > entity reg_cell is > port ( > di : in std_logic; > we : in std_logic; > doa : out std_logic; > dob : out std_logic; > addr_a : in std_logic_vector(3 downto 0); > addr_b : in std_logic_vector(3 downto 0); > imm : in std_logic_vector(3 downto 0); > sel_imm : in std_logic_vector(1 downto 0); > sel_ad : in std_logic; > sel_op : in std_logic; > clk : in std_logic > ); > end reg_cell; > > architecture rtl of reg_cell is > > signal doa_i : std_logic; > signal dob_i : std_logic; > signal fxa : std_logic; > signal fxb : std_logic; > > attribute U_SET : string; > attribute RLOC : string; > > attribute U_SET of memcell_I : label is "reg"; > attribute U_SET of f5_I : label is "reg"; > attribute U_SET of f6_I : label is "reg"; > > attribute RLOC of f6_I : label is "X0Y0"; > attribute RLOC of f5_I : label is "X0Y1"; > attribute RLOC of memcell_I : label is "X0Y1"; > > begin > > with sel_imm select > fxa <= imm(0) when "00", > imm(1) when "01", > imm(2) when "10", > imm(3) when "11", > '-' when others; > > doa <= doa_i; > > memcell_I: RAM16X1D > port map ( > DPO => dob_i, > SPO => doa_i, > A0 => addr_a(0), > A1 => addr_a(1), > A2 => addr_a(2), > A3 => addr_a(3), > D => di, > DPRA0 => addr_b(0), > DPRA1 => addr_b(1), > DPRA2 => addr_b(2), > DPRA3 => addr_b(3), > WCLK => clk, > WE => we > ); > > f5_i: MUXF5 > port map ( > O => fxb, > I0 => dob_i, > I1 => doa_i, > S => sel_ad > ); > > f6_i: MUXF6 > port map ( > O => dob, > I0 => fxb, > I1 => fxa, > S => sel_op > ); > > end rtl;Article: 97155
I am using the Core Generator to create memories. I used the COE file to initialize them and I simulate behaviour. When I tried to Post-Place & Route, it seems that the memory does not get initialized with the same values as on the behaviour simulation. Any idea was is not going OK? In other words, is there a way (in Xilinx ISE) to initialize CoreGen created memories for synthesis (NOT simulation). And if yes, how exactly? Thanks.Article: 97156
Alfredo, Nortel has the email address to spam _every_ FPGA user? Wow, what spyware do you guys put in those routers of yours? Who'd've thought Canadians would be so tricky. Eh? Cheers, Syms. p.s. Warning. Post may contain sarcasm! ;-) p.p.s. Seriously Alfredo, have you got any good links so I can read more about ESL? It seems to be in its infancy, but sounds interesting. "Alfredo" <alherrer@nortelnetworks.com> wrote in message news:dt4t6e$od4$1@zcars129.ca.nortel.com... > Hi, > I do not want to SPAM all FPGA users, so I am posting this here. Xilinx's > marketing department would like to have as much feedback on ESL > (Electronic > System Level) requirements from designers. > > Please let me know by next Tuesday, I am meeting Xilinx on Wednesday. > > Thanks, > -- > *** > Alfredo. > >Article: 97157
"Alfredo" <alherrer@nortelnetworks.com> wrote in message news:dt4t6e$od4$1@zcars129.ca.nortel.com... > Hi, > I do not want to SPAM all FPGA users, so I am posting this here. Xilinx's > marketing department would like to have as much feedback on ESL > (Electronic > System Level) requirements from designers. > > Please let me know by next Tuesday, I am meeting Xilinx on Wednesday. > > Thanks, > -- > *** > Alfredo. What do you consider "Electronic System Level" flow to be? It sounds like you're asking for something generic but I'm not familiar with the terminology.Article: 97158
On 17 Feb 2006 08:05:46 -0800, "GHEDWHCVEAIS@spammotel.com" <GHEDWHCVEAIS@spammotel.com> wrote: >Roggey schrieb: > >> My question is now how can i send data using the mac-layer only from a >> c++ programm. > >That is a good question. I know what you are looking for. > >Normally people use the IP stack and every OS has its own >implementation of that. > >I would be interested in that too, how to send data over the Ethernet. >At least the people who implemented the IP stack had to know how to do >it :) > >Guenter Actually all the source is out there but alas not in a very accessible form. One can go to the linux source and grab the driver for the specific network card in question and also use the linux ethernet driver at the bottom of the ip stack (eth_drv.c I think).Article: 97159
John_H wrote: > I couldn't find my notes quickly so I'll just ask the question: > > Are you certain that the dob_i and doa_i signals from the dual-port CLB > SelectRAM - DPO and SPO, respectively - are on the correct pins (I1/I0) for > the MUXF5? You could just try swapping I1/I0 for a quick check to see if > the orientation is inverted from what you expect. > No I'm not sure it's correct in the version I gave (I think so though), but I did try different swapping of the pins for the MUXF5 and MUXF6, none worked. Sylvain > > "Sylvain Munaut" <com.246tNt@tnt> wrote in message > news:43f5c215$0$19097$ba620e4c@news.skynet.be... > >>Hello, >> >>I'm trying to pack something into two SLICEs and the tools don't get it >>... I get map error. And it should be possible to do what I want since I >>can "draw" it in the FPGA editor. >>(I'm using ISE7.1 sp4 and I target spartan 3) >> >>What I'm trying to pack a a dualport distributedram (RAM16X1D) and a 5:1 >>mux in two slicesM, one above the other. >> >>On the first slice (top one) is the classic RAM16x1D stuff. On this same >>slice, I want to place a F5Mux between the two output of the DRAM, >>commanded by BX (actually, BX will be forced to 1, I just want the >>second output of the distributed ram on the F5 output pin). >> >>On the second slice (bottom one), I get a 4:1 mux done with the two LUTs >>+ the F5 on the slice. And on the same slice, I want to use the FX mux >>to mux between either the output of the F5 of this slice, or the F5 out >>pin of the slice above. >> >> >>The VHDL code I write as test is givent at the end of the post and also >>available there : http://pastebin.com/559361 >> >> >>The error I get : >> >>--- >>ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=reg, >>RLOC=X0Y1) >> which require the combination of the following symbols into a single >>SLICEM >> component: >> RAMDP symbol "memcell_I" (Output Signal = dob_i) >> MUXF5 symbol "f5_I" (Output Signal = fxb) >> The function generator memcell_I is unable to be placed in the G >>position >> because the output signal doesn't match other symbols' use of the G >>signal. >> The signal dob_i already uses G. Please correct the design constraints >> accordingly. >>---- >> >> >>Any idea how to make the tool understand ??? >> >> >>Sylvain >> >> >> >>library ieee; >>use ieee.std_logic_1164.all; >>use ieee.std_logic_arith.all; >>use ieee.std_logic_unsigned.all; >> >>library unisim; >>use unisim.vcomponents.all; >> >> >>entity reg_cell is >> port ( >> di : in std_logic; >> we : in std_logic; >> doa : out std_logic; >> dob : out std_logic; >> addr_a : in std_logic_vector(3 downto 0); >> addr_b : in std_logic_vector(3 downto 0); >> imm : in std_logic_vector(3 downto 0); >> sel_imm : in std_logic_vector(1 downto 0); >> sel_ad : in std_logic; >> sel_op : in std_logic; >> clk : in std_logic >> ); >>end reg_cell; >> >>architecture rtl of reg_cell is >> >> signal doa_i : std_logic; >> signal dob_i : std_logic; >> signal fxa : std_logic; >> signal fxb : std_logic; >> >> attribute U_SET : string; >> attribute RLOC : string; >> >> attribute U_SET of memcell_I : label is "reg"; >> attribute U_SET of f5_I : label is "reg"; >> attribute U_SET of f6_I : label is "reg"; >> >> attribute RLOC of f6_I : label is "X0Y0"; >> attribute RLOC of f5_I : label is "X0Y1"; >> attribute RLOC of memcell_I : label is "X0Y1"; >> >>begin >> >> with sel_imm select >> fxa <= imm(0) when "00", >> imm(1) when "01", >> imm(2) when "10", >> imm(3) when "11", >> '-' when others; >> >> doa <= doa_i; >> >> memcell_I: RAM16X1D >> port map ( >> DPO => dob_i, >> SPO => doa_i, >> A0 => addr_a(0), >> A1 => addr_a(1), >> A2 => addr_a(2), >> A3 => addr_a(3), >> D => di, >> DPRA0 => addr_b(0), >> DPRA1 => addr_b(1), >> DPRA2 => addr_b(2), >> DPRA3 => addr_b(3), >> WCLK => clk, >> WE => we >> ); >> >> f5_i: MUXF5 >> port map ( >> O => fxb, >> I0 => dob_i, >> I1 => doa_i, >> S => sel_ad >> ); >> >> f6_i: MUXF6 >> port map ( >> O => dob, >> I0 => fxb, >> I1 => fxa, >> S => sel_op >> ); >> >>end rtl; > > >Article: 97160
http://fpgajournal.com/articles_2005/20050621_esl.htm http://www.mentor.com/products/fpga_pld/hdl_design/index.cfm afaik: the defacto ESL flow: Matlab to FPGA: http://www.mathworks.com/matlabcentral/fileexchange/loadFile.do?objectId=9565&objectType=file http://www.mathworks.com/company/user_stories/userstory10995.html?by=company The usual suspects: www.coware.com www.celoxica.com www.impulsec.com www.systemc.org Food for though: http://fpgajournal.com/articles_2006/20060207_cray.htm http://www.fhpca.org/ http://www.openfpga.org/ http://www.cs.colostate.edu/cameron/ -- *** Alfredo.Article: 97161
I have a design with an Aurora RocketIO core and in the UCF file I've added the following lines: INST Inst_rio0_top/Inst_rio0/lane_0_phase_align_i/phase_align_flops_r* AREA_GROUP="PHASE_ALIGN_0_GRP"; # Place RIO0 lane_0_mgt_i at location X0Y1 INST Inst_rio0_top/Inst_rio0/lane_0_mgt_i LOC=GT_X0Y1; AREA_GROUP "PHASE_ALIGN_0_GRP" RANGE=SLICE_X14Y152:SLICE_X15Y153; When I use PACE to modify a pin assignment or something equally trivial and save the UCF, the AREA_GROUP "PHASE_ ..........;" line has disappeared. Although the Aurora core does still seem to work, I thought that the placement of the phase alignment FFs was important and was explicitly indicated for good reason. Can anyone tell me what's going on here please? Even if there's some setting somewhere that's telling the PAR to ignore this type of constraint, why does it disappear? Is it something to do with the fact that except for the pin assignments, all the UCF file has been added textually i.e. not via PACE or the Constraints Editor? TIA, Rog.Article: 97162
Peter Alfke wrote: > I think the employment picture is improving, and companies actually > like to hire New College Grads. You are a notch above that, with an > MSEE. Good luck! > One advice: > Make sure that your resume is free of typos. You had nine of them in > your short posting, and you better be more careful in a real > application. Which I am sure you will be. > To many potential employers, a typo indicates lack of seriousness or > attention to detail. Whether that is justified or not is irrelevant. > Just avoid the potential problem... > Peter Alfke Thanks Peter Alfke for taking time to answer. Yes for the real application, i do check and double check the spelling. But i think that the fact of being new grad doesn't help me.Article: 97163
Thank you very much Mr. Tim Wescott, I really appreciate your time. Your advices are very helpful, some ideas that you did bring I had them in mind but wasn't sure like I do now after reading you answer to my posting. But still the new grad person should start somewhere to be an experienced employee. They don't born experienced like that. I only hope that companies are conscious about it. Thank you again. Thomas.Article: 97164
In a start-up company, being a new grad would often be a disadvantage. The small company needs to succeed fast, so they rather hire somebody with a proven track record. (When Xilinx was very small (<100 engineers) almost everyone had >10 or 20 years experience) In a larger company, it is much easier to "absorb and train" neg grads, whereas it may be more difficult to fit very experienced engineers into the existing structure. These are gross oversimplifications, but I think you would be best off looking for an established company with multiple hundred employees. You also might be able to learn more different things there, for a while, whereas in a small company you have to pull your weight from day 1. Do not get discouraged. This is still an exciting field in which you can become very successful. Peter AlfkeArticle: 97165
Hi Isaac Bosompem and thank you for your participation in this posting. My self I am from Montreal and as i was looking for job for more then year, I can tell that in general, in Canada the jobs are mainly in Toronto and Ottawa areas, some in Vancouver BC and then a few in Quebec. So you're lucky you live already in Toronto and the employment picture is improving so don't be discouraged. Currently I am in California next to Silicon Valley looking for job. Down here you need a sponsorship from the employer to get TN visa so you can work in the US if you are Canadian. So if you are new grad there is no much employer that will be ready to do that for you. My question is : was your uncle experienced when he applied for job here? Thank you. Thomas.Article: 97166
"Antti" <Antti.Lukats@xilant.com> schrieb im Newsbeitrag news:1140004004.835579.16060@g47g2000cwa.googlegroups.com... > News from Embedded World News, Nurnberg 14.02.2006 > some fixes updates to my onw posting > Lattice > ======= > ECP2 pricing is 50% of ECP, so smallest ECP2 > has an pricetag of 3 USD. Smallest members > of ECP2 family are however last on the roadmap > the first member to be available is the largest > ECP2-70 with smallest ones following. fix: ECP2-50 is first device, ECP2-12 follows with all members expected to be sampling in Q2 > SiLabs > ====== > 5) CP2201 Evalution Kit, no info ??? what is it? CP2201 is Ethernet MAC+PHY, packaged in QFN28, TQFP32 2 different parallel interfaces, will be officially launched on March 6th. > Xilinx > ====== > To have a rest I did sit down for a live [snip] if my commentary about Xilinx presentation has been qualified as funny in bad sense, well I have been a REAL PAIN IN THE ASS all my life at all presentations. The few small errors the Xilinx speaker did during the presentation, well we all do mistakes. And as I said I was never been good at simple math, and have done mistakes a la 1 + 1 = 2 in the math class, so the 3 x 17 error at the Xilinx presentation I should not have pushed onto it. That I did not find anything new for me at the Xilinx booth that is also quite understandeable from simple reason that I already did know everything, and there was nothing that Xilinx announced specially at Embedded as some other companies did. It doesnt mean that I did not find nice Xilinx products at other booths the Zefant S3e modules are pretty cool, and PLDA had working 4 lane PCIe demo with FX60 to name a few. AnttiArticle: 97167
I am designing a data aqu system using an fpga and adc sampling at 250MHz. I want to use equivalent time sampling to increase the sampling rate to a few GHz for repetative signals. I am not sure how to go about implementing it though. Any info would be welcome, thanks. JonArticle: 97168
"maxascent" <maxascent@yahoo.co.uk> wrote in message news:kYydnaQMQMIAzmveRVn_vQ@giganews.com... >I am designing a data aqu system using an fpga and adc sampling at 250MHz. > I want to use equivalent time sampling to increase the sampling rate to a > few GHz for repetative signals. I am not sure how to go about implementing > it though. > > Any info would be welcome, thanks. > > Jon Are the aquisition triggers deterministic? You have different requirements for a general purpose piece of test equipment versus an eye-diagram analyzer. A general purpose piece of test equipment would tend to continuously acquire data and decide which "bins" to put the samples in based on where the trigger actually occurs within the acquisition clock period. This provides the ability to "bin" as precisely as one can determine where in the period the trigger occurs. A dedicated piece of equipment with known trigger points such as a telecom analyzer can slave the sampling clock to the waveform being sampled and "force" the alignment relative to the sample clock period (or conversely align the sample clock to the bins). PLLs and DDS work beautifully here. So - do you want general purpose? Do you just want data 20 ns after the trigger and later only? Do you want large pretriggers? I've seen equivalent time equipment (no real time permitted) where the samples were 1 point per trigger with the data 10 ns or more after the trigger. In this case, the single sample event could be delayed from the trigger event precisely on a point-by-point basis. Since the trigger is usually the point of interest, that test equipment used a high fidelity delay line to sample the delayed channel a precise delay after the trigger allowing a small pre-trigger. There are many ways to skin this cat. Engineering tradeoffs can't yet be made with the information supplied.Article: 97169
Hi All, This post pertains to a DDR SDRAM controller that works perfectly for 95% of DIMMS used, and is part of a test system that contains a 2+ GHz oscilloscope monitoring the clock, command, and dqs signals at the DIMM pins. Several DIMMs seem to operate incorrectly only occassional (possibly temperature dependent), and I suspect that the issue is some type of timing requirement that is on the edge of met and violated. When the incorrect behavior is seen the scope verifies that write cylces are operating correctly but that the read cycles are not operating correctly. Durring the read cycles the active command is issued, then the read command (satisfying Trcd) and accordingly the DQS signals are provided by the DIMM. Here is the catch; bursts of 8 was specified durring initialization and the DQS signals durring correct operation correspond to this choice; however, but durring the failing read cycles I will see sometimes 1 DQS rising edge, sometimes 2 and sometimes even 5 rising edges! My questions are as follows: 1) Has anyone with DRAM exprience seen any behavior like this before? 2) ** What might cause a DDR module to provide a varying number of DQS strobes? ** Recall that the design has no blatent errors since for most DIMMs no errors are ever seen. Thanks for any thoughts, Brendan IllingworthArticle: 97170
http://www.rawether.net/Article: 97171
I am just guessing here. Are your constraints by any chance included in between the following lines? #PACE: Start of Constraints generated by PACE ..... #PACE: End of Constraints generated by PACE I would expect PACE to respect only whatever is outside of these lines... But I don't really know how it works in practice... /Mikhail "Roger" <enquiries@rwconcepts.co.uk> wrote in message news:TAoJf.39670$K42.16607@newsfe7-win.ntli.net... > I have a design with an Aurora RocketIO core and in the UCF file I've added > the following lines: > > INST Inst_rio0_top/Inst_rio0/lane_0_phase_align_i/phase_align_flops_r* > AREA_GROUP="PHASE_ALIGN_0_GRP"; > > # Place RIO0 lane_0_mgt_i at location X0Y1 > INST Inst_rio0_top/Inst_rio0/lane_0_mgt_i LOC=GT_X0Y1; > > AREA_GROUP "PHASE_ALIGN_0_GRP" RANGE=SLICE_X14Y152:SLICE_X15Y153; > > When I use PACE to modify a pin assignment or something equally trivial and > save the UCF, the AREA_GROUP "PHASE_ ..........;" line has disappeared. > Although the Aurora core does still seem to work, I thought that the > placement of the phase alignment FFs was important and was explicitly > indicated for good reason. Can anyone tell me what's going on here please? > Even if there's some setting somewhere that's telling the PAR to ignore this > type of constraint, why does it disappear? Is it something to do with the > fact that except for the pin assignments, all the UCF file has been added > textually i.e. not via PACE or the Constraints Editor? > > TIA, > > Rog. > >Article: 97172
ML wrote: > Can someone please explain to me what the 1QN and 2QN formats are as used in > the input and outputs of the Xilinx CORDIC IP? Especially for the case of > polar to rectangular conversion aka Vector Rotation mode. And how do I > convert between them and two's complement format ? > > Thank you for any insights. > ML > > Those are two's complement fractional notation where there is an implied radix point. Put another way, those formats are 2's complement integers with an implied power of 2 scale factor so that with the implied scale factor they represent values that have a fractional part. 1QN means there is 1 bit to the left of the radix point, and N bits to the right. 2QN means 2 bits left of the radix point and N fractional bits. Of course, you can apply any power of 2's scaling to that you want to. What this notation does for you is tells you the relative weighting of the inputs and outputs.Article: 97173
What is the price for ISE Simulator? There is no mention of it in Xilinx Online Store. How does it compare to ModelSim Xilinx Edition III? HendraArticle: 97174
Check out this link for some ideas: http://www.fpga4fun.com/10BASE-T.html
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