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On 21 Jan 2006 05:35:40 -0800, "GaLaKtIkUs™" <taileb.mehdi@gmail.com> wrote: >I read from the file >http://www.xilinx.com/company/press/kits/ise81i/8_1i_faq.pdf the >following: > >--BEGIN-- >14. What happened to the ISE BaseX configuration? >.... skipped text .... >All in-maintenance ISE BaseX customers are receiving a copy of ISE >Foundation at no extra cost with the ISE 8.1i release. >--END-- > >I'm an in maintenance BaseX customer. Does it mean that I can get full >ISE foundation? > >Mehdi. Yes, it's free. I just costs twice as much. JohnArticle: 95426
Antti Lukats wrote: > >> Hello Group, > >> > >> I'm having difficulty convincing Xilinx ISE (8.1SP1 WebPack) PAR to pack > >> some of my signals into the IOBs of an XC4LVX25-FF668. A simple > >> demonstration case is the MIG 1.4 dimm72 VHDL design for the ML461 > >> memory eval board. The FPGA editor shows that most of the DDR command > >> bus outputs correctly push their registers into the IOBs; however the > >> DDR_CS and DDR_ODT output get registered within the fabric. The > >> resulting skew between DDR_CS and the rest of the command bus outputs > >> becomes fatal when generating cores for DDR systems with multiple ranks > >> (chip-selects). The skew of 2ns or so is clearly visible in timing > >> simulations, and my DDR2 model throws a tantrum about invalid setup time > >> on DDR_CS. > >> > >> I have tried seducing ISE into pushing the DDR_CS registers to the IOBs > >> by setting XST "Pack I/O Registers into IOBs" to both "Auto" and "Yes". > >> I have set XST register balancing to "No" and to "Yes" with Move > >> First/Last Flip-Flop Stage disabled. I am also enabling the MAP option > >> to Pack I/O Registers/Latches into IOBs. I am new to Xilinx FPGAs. > >> With Altera I would enable Fast Inputs/Outputs in Quartus, and all the > >> registered I/O would get pushed to the pads. Am I missing something > >> obvious? > >> > >> One thing I did notice: DDR_CS (and ODT) is different from the rest of > >> the command bus in that it is directly fed a combinatorial term, whereas > >> the rest of the command outputs are just relatches of signals registered > >> on previous clocks. Should this make a difference? It seems to me > >> that a combinatorial term could be routed from a slice to an I/O > >> register, just as easily as a registered signal could... > >> > >> Any thoughts or meditations are appreciated, > >> > >> -Peter > > > Hi Peter > > it seems that you need to ask mr Lakshmi Gopalakrishnan what the means with > his comment: > > // added for deep designs " > > the CS FF could be in IOB only if registers are duplicated, otherwise > defenetly not as the outputs of those regs are used again in the design as > inputs. as long as register duplication does not work there is no hope to > see the CS output flops in IOBs > Yes this may shed some light on the problem. If you have feedback from an output signal, ISE sill not pack the register into the IOB, because feedback through the pin is much slower. If you can find the feedback path and create a duplicate signal in the design for feedback, you may get lucky and have the register pushed into the IOB. This only works if the duplicate register isn't optimised away during synthesis. You may need to change some settings for this, or another approach is to make the "duplicate" signal not exactly the same by providing a different async reset term than the original. > > > > -- > Antti Lukats > http://www.xilant.comArticle: 95427
Thanks Austin, I'll consider both inputs and outputs the same way to compute how many Vcco I need to connect, ok? MarcoArticle: 95428
Toys, Relax. Is it fraud to not tell you that operating your vehicle at 115 mph might lead to death? Is it fraud to not tell you that placing a cardboard box on your stove might lead to a fire? We provide programmable resources. The data sheets provide exact tables for those who care as to the total numbers of everything. If all you read is the top sheet, then you have just "scratched the surface" are are subject to the 'promotional' side of the presentation: all of the elements that we think are new and exciting, and different. Sure, go ahead and toggle every single flip flop and IO simultaneously at max frequency, and I will assure you that you will not like the result. But that is not what our customers do: rather, we provide devices that are programmed by them to solve problems. If the device chosen has too few resources, then they can (and do) go to the next larger device. If the device chosen gets too hot, they can (and do) use better heatsinks, or change their design. It is called engineering. AustinArticle: 95429
Robin Bruce wrote: > Brian Davis wrote: > > Symon wrote: > > > > > > As penance, I'll still get the dessert AND write a little article about it > > > for the FAQ. (The fpga-org.com FAQ that is!) > > > > > Probably a bit OT for comp.arch.fpga; might I suggest instead the > > FAQ at schwarzwaldkirschtortemitschlagsahne.org > > > > Brian > > For the hard of German, I make that "Black Forest Cherry Cake with > Whipped Cream". > Incredibly, the domain has not yet been snapped up... > > Robin Kirsch could sometimes refer to Kirschwasser (an ardent spirit). Getting back on topic, though, I would guess that a lot of objectional posts get here through the Google portal. Is there a way to post a link to the FAQ there?Article: 95430
"Aurelian Lazarut" <aurash@xilinx.com> schrieb im Newsbeitrag news:dr2v1k$in82@cliff.xsj.xilinx.com... > luigi wrote: >> Hi >> We work with a XCF01S and a Spartan 3 XC3S200. >> JTAG works with 2.5V, Spartan Vcco (INIT_B and DIN/D0) has 3.3V. The >> connections between XCF and Spartan are according the application note >> for 3.3V output (INIT_B) to 2.5V input CE/RES. >> >> Programming the Flash and booting from Flash works fine. >> Programming the FPGA works only, when we have the same code in the >> Flash. >> When we try to load a different code (as is in the Flash) per JTAG to >> the FPGA, the FPGA doesn't start up. >> >> Does anybody know what's going wrong? >> >> Luigi >> > Change the mode pins on the FPGA > Aurash typish Xilinx ! for many many PCB boards where mode pins are hard wired under BGA this is not an option. In all Xilinx documents its clearly written that JTAG configuration over-rides any other modes. Still there are several scenarios where this is not entirely true, eg the restart of non JTAG configurtion if valid signature is present at some time slot will make the JTAG configuration to fail. I have had that fight many many many times. AnttiArticle: 95431
"Austin Lesea" <austin@xilinx.com> wrote in message news:dr2vgc$bv19@xco-news.xilinx.com... > > There is something called SSI, simultaneously switching inputs. If the > inputs have overshoot or undershoot, or some small ringing (as they all do > unless perfectly matched), then there will be currents flowing which will > create ground/Vcco bounce. > Hi Austin, Where do these currents flow? Through the protection diodes? Thanks, Syms.Article: 95432
"Marco" <marco@marylon.com> wrote in message news:1138029909.668784.206360@o13g2000cwo.googlegroups.com... > Hi, on xapp623 on PDS there are all the step to define the number and > the values of decoupling capacitors. This number depends on how many > Vcco you need to connect for each bank, and the latter is function of > the outputs implemented. But, if I use all the I/O pins of a bank as > input, how many Vcco pins should I use? > Thanks, Marco Marco, I'm a bit confused: are you considering not hooking up all the Vcco pins? You want to supply power through a limited subset of the available power pins?Article: 95433
On Mon, 23 Jan 2006 15:29:03 +0100, the renowned "Frank Bemelman" <f.bemelmanq@xs4all.invalid.nl> wrote: >"Spehro Pefhany" <speffSNIP@interlogDOTyou.knowwhat> schreef in bericht >news:5uj9t1dkjk5q89v8t977rqi4ts3bag7n6a@4ax.com... >> On Mon, 23 Jan 2006 09:46:44 +0100, the renowned "Frank Bemelman" >> <f.bemelmanq@xs4all.invalid.nl> wrote: >> >> ><bill.sloman@ieee.org> schreef in bericht >> >news:1137987045.839508.7650@o13g2000cwo.googlegroups.com... >> >> >> >> Good for Slovenia! The Netherlands is acquiring a culture of eating >> >> well - we now have three restaurants with three Michelin stars - but >> >> there is a long way to go. It a Dutch person recommends a restaurant to >> >> you, you can be fairly sure that the decor, ambience and service will >> >> all be okay, but the food can be total rubbish. >> > >> >It is indeed a long way to go, if the goal is three Michelin star food >> >for everyone, everyday. >> > >> >Sheesh! >> > >> >;) >> >> Doesn't sound like a bad goal. Instead of food insecurity you'd have >> to worry about the prevalence of gout. > >I'm getting more worried about my wallet, and what's in it. Bill is a >snob of course, as most Michelin star restaurants customers are. Last >friday I had the pleasure of a dinner at Ron Blaauw's Palazzo, in >Amsterdam. http://www.egol.de/palazzo/amsterdam/gaenge/e_gaenge_8_a.php >Ron Blaauw is good for 1 star, so the food was excellent. But at this level, >the amount of joy has not much to do with the food. It's a sum of everything >that surrounds it, and probably the most important ingredient of any good >dinner is how you and your guests are feeling themselves. Now that looks like a good spot for nice meal. Is the presentation really like in the photos? Unagi (err... smoked eel) and split pea is intriguing, as is the fish. You'd probably enjoy either of these if you ever get out this way: http://www.north44restaurant.com/ (sound and swf) http://www.canoerestaurant.com/02frsetdin.htm >Most of the better restaurants here charge 20-25 euro for a main dish, >and you can expect excellent food for that. Entrees and desserts for >10-12 euro. A bottle of good wine, 30-35 euro. Paying double or triple >get's you into the Michelin star places, but gives diminishing returns. >Of course you can spend all evening there trying to find something you >can complain about, such as a tiny spot on the table ware, the wine >being 2 degrees too cold, the haricots verts too long or too short and >what have you, and you will not be able to find anything wrong. But >that is not my definition of a perfect dinner ;) As you can see, the prices are not very different. (1.4 C$ = 1 EUR), but you have to expect the final price will be about 1/3 higher with taxes and tip. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.comArticle: 95434
Symon, Through the substrate diodes that are intrinsic to the IO output devices. The output stack acts as the "protection" for inputs. This is the foundry standard "self-protecting" IO design that we changed to starting with Virtex II. Prior to that we had various proprietary ESD protection structures (that caused us immense headaches). SSI is not as much as SSO, but it should not be ignored! Austin Symon wrote: > "Austin Lesea" <austin@xilinx.com> wrote in message > news:dr2vgc$bv19@xco-news.xilinx.com... > >>There is something called SSI, simultaneously switching inputs. If the >>inputs have overshoot or undershoot, or some small ringing (as they all do >>unless perfectly matched), then there will be currents flowing which will >>create ground/Vcco bounce. >> > > Hi Austin, > Where do these currents flow? Through the protection diodes? > Thanks, Syms. > >Article: 95435
Joerg, The first step to getting a PE is to take the FE exam which, if passed will get you your EIT. You don't need any PE signatures to take that exam. Without that exam, there is no point even pondering the PE as it is the first requirement you need to meet. The FE exam probably easiest to take when you are fresh out of school, because it requires fairly detailed knowledge across a broad spectrum of disciplines, and presumably most of that material is covered in your undergrad studies. If you delay taking the FE exam, you have that much more studying to do to brush up on it. It isn't a big deal to take, but does require preparation just like any other knowledge test. My take on your strong objections to licensure is that you are afraid of the process, either the tests or the application process. If you are competant, you should have little trouble navigating the application process. The tests do require you to study up on areas that are outside of your immediate expertise, but there are enough different subject areas (and generally you only need to complete questions in a few areas) that you should be able to find some combination of subject areas for which a little bit of study combined with your experience in your niche will get you through the PE test with flying colors. You can get a PE with a foreign school degree. If you have 20 years experience, you can get it with no degree. The obstacles may be a little higher, but it is possible. The point here is that they want you to meet a certain level of demonstrated proficiency, which is why they want an accredited degree. There is no reason, for example that a foriegn student couldn't either finish up his degree at an accredited school and transfer credits in, or get an advanced degree at an accredited school. One of a student's responsibilities in selecting a school is to make sure the school has the credentials to make his intended degree worth something. I don't expect anyone, much less a licensing board to accept a paper degree from an off shore school with no credentials to back up the quality of education any more than I expect them to accept one of the diplomas offered in those email scams. The PEs who provide your references do not have to be in the same discipline, nor do they need to have any expertise in your area of work. They are basically vouching for you by stating that your work is worthy of a professional and that you are moral and ethical in your work. It doesn't mean they have to be a co-worker or know the intimate details of your work. Yes, it can be a little bit of a hassle finding the PE references if you are not in construction, but it is not impossible. Every state publishes a list of the registered engineers in the state, and many are willing to help you along in your certification. I tried to point out to you that there are likely people you've come in contact with that have a PE license, but you dismissed that out of hand. As I stated, if you are motivated to do so, you can certainly find PEs that will do what they can to help out. I'm sure your NSPE chapter would be glad to have you as a guest at their meetings even if you aren't a member, that is unless you are a rude arrogant SOB (in which case you would still probably be invited the first time, just not invited back). California, as with other states, does have an exemption for the license for industrial/manufacturing. However, I think if you check the chapter and verse of the law, you'll find that it does not include independent consultants offering engineering services to manufacturing concerns or other firms. That is certainly the case in a number of the states I have done business in. It also does not allow you to call yourself an engineering consultant, and is in fact pretty specific about that. Some states will take that as far as if the find both the words "engineer" and "consult" anywhere in your advertising (websites, brochures, business cards) even though they are not together, they will serve you with a cease and desist order, and possibly a fine. As far as liability insurance goes, no, having a PE does not require nor obligate you to carry liability insurance under any stretch of the definition. I do carry it, but it is not required. Some of the firms I do business with wanted to see it, and I have assets I wish to protect should something arise. You can get coverage, even for involvement with medical devices. It isn't cheap, but you can buy coverage, and having a PE makes it easier to find it. One insurer that provides it is Evanston. Ahh, but you do offer your services to the public. Offering services to a company that you are not on the direct payroll for is offering services to the public. Merely having a website or other advertising for your services is considered bona-fide proof of you offering your services to the public. Your website says "Consulting Services to Industry", which is both offering services to the public, and also violates the provision in the law that reserves the term consulting engineer to those who hold a PE license. As for those engineers working for the utilities, you can bet that their work has to be signed off by a PE before it can be fielded. That PE may not be sitting in the office with those engineers, but I am dead certain a PE stamp has to show up on the drawings before it is fielded. To me, it sounds like you are mostly coming up with excuses rather than seriously looking at it. Joerg wrote: > Hello Ray, > >> >> > Which leave out anyone with a degree from a foreign school. 20+ years > ago government bodies told students it would be good to gain overseas > experience and even study there. So, what do we tell them now? That they > shot themselves in the foot and shouldn't have listened? > > >>> > > Never met a single one. In 20 years. > > >> ... If you have outside consultants doing work >> (not contractors, consultants) for your company, one or more of them >> will likely have a P.E. As a last resort, there is nothing stopping >> you from joining the local chapter of NSPE and getting friendly with >> the members. Many would be very interested in hearing about your work. >> They really are a likeable lot. :-) >> > > If remembering correctly NSPE requires at least EIT status to join. > Neither I nor any of my peers have that. > > > > California doesn't if you only provide services to industry. We have an > industry exemption. > > Other states don't, and I sure won't ever live there. > > >>> > > They can only do that if you have knowingly pretended to be a PE but > don't have a license. Anything else would get them inundated in litigation. > > > > > I have never encountered that. We live by standards such as UL2601, FDA > regulations and so on. > > > > > None of them I was involved in had one. And I did ask. The only person I > found in that direction (and that was one lone case in 20 years) had > passed the FE test a long time ago and was thus an EIT. She never took > the final test for PE because there really wasn't a need for it. > > As I replied to Chris before a PE license can oblige you to mandatory PL > coverage. Just for the fun go out and try to find an underwriter. I did, > until I had blisters from dialing. Zilch. Nada. > >> > That's why I do not offer services to the public ;-) > > Heck, I have met a whole lot of power engineers working for utilities. > They certainly provide direct services to the public. None of them was a > PE. > > Regards, Joerg > > http://www.analogconsultants.comArticle: 95436
Austin Lesea wrote: > We provide programmable resources. The data sheets provide exact tables > for those who care as to the total numbers of everything. Uhh, Austin, in case you did not read the initial posts, the misleading data sheet numbers is what this thread is about. I searched the Spartan 3 data sheet for LC and Logic Cell. The only mention I see of the counts is on the first page in the table that has the "Equivalent" count which is exactly what this thread is about. > If all you read is the top sheet, then you have just "scratched the > surface" are are subject to the 'promotional' side of the presentation: > all of the elements that we think are new and exciting, and different. So where is the accurate information you are talking about? "Equivalent" logic cell counts are clearly not "new", so are they "exciting" or just "different"? > But that is not what our customers do: rather, we provide devices that > are programmed by them to solve problems. If the device chosen has too > few resources, then they can (and do) go to the next larger device. If > the device chosen gets too hot, they can (and do) use better heatsinks, > or change their design. If that is the way your company looks at it, why don't they put the *actual* logic cell counts into the data sheet table rather than the marketing "Equivalent" counts? > It is called engineering. But the way Xilinx does it, it's called marketing. > Austin I have no beef with either you or Peter. But please don't insult our intelligence by trying to defend marketing numbers in a data sheet.Article: 95437
"Spehro Pefhany" <speffSNIP@interlogDOTyou.knowwhat> schreef in bericht news:h12at1l5o5pt5ufml6oh9k8d081i49hj4o@4ax.com... > On Mon, 23 Jan 2006 15:29:03 +0100, the renowned "Frank Bemelman" > <f.bemelmanq@xs4all.invalid.nl> wrote: > > >"Spehro Pefhany" <speffSNIP@interlogDOTyou.knowwhat> schreef in bericht > >news:5uj9t1dkjk5q89v8t977rqi4ts3bag7n6a@4ax.com... > >> > >> Doesn't sound like a bad goal. Instead of food insecurity you'd have > >> to worry about the prevalence of gout. > > > >I'm getting more worried about my wallet, and what's in it. Bill is a > >snob of course, as most Michelin star restaurants customers are. Last > >friday I had the pleasure of a dinner at Ron Blaauw's Palazzo, in > >Amsterdam. http://www.egol.de/palazzo/amsterdam/gaenge/e_gaenge_8_a.php > >Ron Blaauw is good for 1 star, so the food was excellent. But at this level, > >the amount of joy has not much to do with the food. It's a sum of everything > >that surrounds it, and probably the most important ingredient of any good > >dinner is how you and your guests are feeling themselves. > > Now that looks like a good spot for nice meal. Is the presentation > really like in the photos? Unagi (err... smoked eel) and split pea is > intriguing, as is the fish. Yes, more or less. Except for some of the stuff in the backgrounds and the fish, which is served on a plate rather than an entire raw cod fish. > You'd probably enjoy either of these if you ever get out this way: > http://www.north44restaurant.com/ (sound and swf) > http://www.canoerestaurant.com/02frsetdin.htm Smoke free, what a shame ;) > >Most of the better restaurants here charge 20-25 euro for a main dish, > >and you can expect excellent food for that. Entrees and desserts for > >10-12 euro. A bottle of good wine, 30-35 euro. Paying double or triple > >get's you into the Michelin star places, but gives diminishing returns. > >Of course you can spend all evening there trying to find something you > >can complain about, such as a tiny spot on the table ware, the wine > >being 2 degrees too cold, the haricots verts too long or too short and > >what have you, and you will not be able to find anything wrong. But > >that is not my definition of a perfect dinner ;) > > As you can see, the prices are not very different. (1.4 C$ = 1 EUR), > but you have to expect the final price will be about 1/3 higher with > taxes and tip. Taxes are included here, and tip is to decide yourself. Dutch travel guides advise to give 15% but nobody does - 5 to 10% is more like it. -- Thanks, Frank. (remove 'q' and '.invalid' when replying by email)Article: 95438
"Steve at fivetrees" <steve@NOSPAMTAfivetrees.com> schreef in bericht news:N9OdnbT8nt5qnkjeRVnyhw@pipex.net... > > I find it odd that grown men, and no doubt entirely mature and sensible > grown men, revert to kindergarten tactics when arguing via this protective > barrier we call the Internet. To say "it's the nature of usenet" doesn't cut > it - we're still people, no matter what the medium. Is dignity disposable? Yes, that's all very true, except that JT is not a grown man but just a piece of filthy shit. -- Thanks, Frank. (remove 'q' and '.invalid' when replying by email)Article: 95439
The PE license for electrical engineering is the same for all facets of electrical engineering. The code of ethics is what limits you to your specific field, not the license itself. My EE PE is the same as someone who designs power plants even though I don't know squat about power engineering a power engineer likely doesn't know squat about digital design. The test has different subject areas, of which you only have to answer questions from a limited number of areas of your choice. Those areas include one on digital logic, and another on computers. So while there is not a PE in digital design or software engineering, those disciplines are covered under the broader PE license for electrical engineering. > Bryan Hackney wrote: > > I'm unaware of digital design and software being areas of expertise > where a PE can be registered in Texas. Maybe that's changed, but I > doubt it. So that point is probably moot. > >Article: 95440
Hi Guys, I've got an V2PRO RPM that uses only FFs in slices. How do I prevent ISE7.1 from placing the RPM so that it straddles a BlockRAM/Mulitplier column? When this straddling happens, the routing across the column takes a 300ps hit that I'd rather not have. I've looked at RPM_GRID; it doesn't seem to help. TIA, Syms.Article: 95441
Symon wrote: > Hi Guys, > I've got an V2PRO RPM that uses only FFs in slices. How do I prevent ISE7.1 > from placing the RPM so that it straddles a BlockRAM/Mulitplier column? When > this straddling happens, the routing across the column takes a 300ps hit > that I'd rather not have. > I've looked at RPM_GRID; it doesn't seem to help. > TIA, Syms. > > Either place it with an RLOC_ORIGIN, or use an area contraint to restrict it to certain columns. You have to be careful of that straddling for V4 if you have memories in your RPM, the mapper has a bug in it where it counts the BRAM/DSP48 column when figuring out if the placement puts a memory column of your RPM into a non-memory slice column.Article: 95442
Good morning, I've designed with statecad a state machine and tested with statebhench all seems to be OK, now I want to automatically generate the sequential circuit associated, how I could do this ?? Thanks Antonio D'Ottavio www.etantonio.it/en/Article: 95443
Rick, OK. So I download: http://direct.xilinx.com/bvdocs/publications/ds099.pdf And I see immediately when I search for LUT, the issue. Then, I continue. And, I see no more references to LUT. OK, so S3 has not provided a count? Yup. I get it. But, they do have total CLB's, and the comment that has the dreaded 1.125 multiplier in it. So, I take number of CLBs, and multiply by LUTs per CLB. That wasn't too hard. But I agree, it seems odd not to have the basic numbers there, without multipliers for "effectiveness." Before I finish, though, I go off to Virtex 4's data sheet: http://direct.xilinx.com/bvdocs/publications/ds112.pdf And I immediately see two different numbers: 178,176 LUTs in the LX200, and 200,448 "Logic Cells." No footnote. But there are 89,088 slices, so I multiply by 2 LUTs/Slice, and I get 178,176. OK, so far so good. So, at least S3 had a footnote to explain the "magic," wheras V4 did not even have that. But V4 did have the basic count up front (for the largest part) to help with decoding... Is this really such an issue? Perhaps since I know LUT/slice slice/CLB for each family (at least I can always look it up), it isn't as if this is an ordeal to keep track of. Would I rather that Marketing was not responsible for the data sheet? Heavens No! My paycheck depends on their abilities! So, the tables do have exact numbers, they just require some investigation to remove the "effectiveness factor" for those who like to count. By the way, I love to count. In fact, my father was from Transylvania, and as you all know, a role model for two generations now for all Transylvanians has been Sesame Street's 'The Count'. "Ah Ha Ha! One, Two, Three.... I Love to Count..." So, for anyone confused, and unable to count, just drop me an email, and I will be happy to provide any details. And, I will continue to work with Marketing so that the numbers are at least there in some form in the tables. AustinArticle: 95444
"Ray Andraka" <ray@andraka.com> wrote in message news:YA8Bf.9673$bF.5284@dukeread07... > > Either place it with an RLOC_ORIGIN, or use an area contraint to restrict > it to certain columns. > > You have to be careful of that straddling for V4 if you have memories in > your RPM, the mapper has a bug in it where it counts the BRAM/DSP48 column > when figuring out if the placement puts a memory column of your RPM into a > non-memory slice column. > Many thanks, Syms.Article: 95445
Pooh Bear <rabbitsfriendsandrelations@hotmail.com> writes: > "Everett M. Greene" wrote: > > Pooh Bear <rabbitsfriendsandrelations@hotmail.com> writes: > > > "Everett M. Greene" wrote: > > > > Jim Thompson <To-Email-Use-The-Envelope-Icon@My-Web-Site.com> writes: > > > > > > > > > You know not of what you speak. The breakfast buffet at the hotel was > > > > > fabulous! In fact all the inns in Bühlertal had great breakfasts. > > > > > > > > When I was there, the Nazi-era laws forbade anyone starting > > > > work early enough to get the makings for a good breakfast > > > > prepared. > > > > > > Could you elaborate on these " Nazi-era laws " ? > > > > No. > > > > It was simply what I heard or read as being the reason why > > the first breakfast available at hotels was so limited. > > Someone was pulling your leg. If so, there was a lot of collusion then because every place I went in northern Germany it was the same. Maybe it is/was different in Bavaria and other states.Article: 95446
How does one properly synthesize and simulate a bidirectional
port on the Virtex-4 using ISE 7.1i.
I drafted code from an earlier Spartan 3 design, which synthesized
nicely. On the Virtex-4, the T signals is not registered although
the block diagram indicates that it could be.
Also, the ISE simulator does not show any output values on the
inout ports.
Thanks,
Brad Smallridge
sram_tristate_process:process(sram_clk)
begin
if( sram_clk'event and sram_clk='1') then
if( sram_cam_en_2='1' ) then
sram_flash_data <= sram_write_data;
else
sram_flash_data <= (others=>'Z');
end if;
end if;
end process;
sram_read_data_process:process(sram_clk)
begin
if(sram_clk'event and sram_clk='1') then
sram_read_data <= sram_flash_data; -- 36 bit
end if;
end process;
Article: 95447
On Mon, 23 Jan 2006 10:18:15 PST, mojaveg@mojaveg.iwvisp.com (Everett
M. Greene) wrote:
>Pooh Bear <rabbitsfriendsandrelations@hotmail.com> writes:
>> "Everett M. Greene" wrote:
>> > Pooh Bear <rabbitsfriendsandrelations@hotmail.com> writes:
>> > > "Everett M. Greene" wrote:
>> > > > Jim Thompson <To-Email-Use-The-Envelope-Icon@My-Web-Site.com> writes:
>> > > >
>> > > > > You know not of what you speak. The breakfast buffet at the hotel was
>> > > > > fabulous! In fact all the inns in Bühlertal had great breakfasts.
>> > > >
>> > > > When I was there, the Nazi-era laws forbade anyone starting
>> > > > work early enough to get the makings for a good breakfast
>> > > > prepared.
>> > >
>> > > Could you elaborate on these " Nazi-era laws " ?
>> >
>> > No.
>> >
>> > It was simply what I heard or read as being the reason why
>> > the first breakfast available at hotels was so limited.
>>
>> Someone was pulling your leg.
>
>If so, there was a lot of collusion then because every place
>I went in northern Germany it was the same. Maybe it is/was
>different in Bavaria and other states.
I recall some kind of requirement to be closed one day per week, but I
don't know of any "early" rule.
In fact one inn put a breakfast out for me personally when I had a
4:00AM departure... I had to drive to Frankfurt to catch an early
flight.
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
It's what you learn, after you know it all, that counts.
Article: 95448Hi Peter, Thank you very much for the reply. In case i use D as Clock and E as direction (say i convert D and E according to your set and reset) the program might look like the code below. what clock (??? in the program below) shud i use for trigger (the processor/bus clk?) ------------------------------------------------------ E program will look like::: ============================ if(???'high and ???= '1') then if(QEP0 = '1' and QEP1='1') then E <= '1'; elsif (QEP0='0' and QEP1='0') then E <= '0'; end if; end if; ------------------------------------------------------------------------- and the D program will look like ::: ==================================== if(???'high and ???= '1') then if(QEP0 = '0' and QEP1='1') then D <= '1'; elsif (QEP0 ='1' and QEP1='0') then D <= '0'; end if; end if; ===================================== Also quote "The clock frequency should be higher than 1 MHz to operate reliably, even when the mechanical action is very fast, perhaps spring-loaded..." unquote. which Clock are you mentioning here? the QEP0-QEP1 or the system/bus clock?Article: 95449
Thank you Gabor/Antti, You hit the nail on the head. The DDR_CS term was being used to generate the DDR_ODT (On-Die Termination) output. I edited the MIG-generated source to explicitly duplicate registers, and now all my outputs are registered in the IOB's. I opened a tech-support case to inform Xilinx of the issue. Thanks again, -Peter
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