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I have a problem width my CPLD-SPI_flash configuration system. I have made a configuration interface for my Spartan 3 FPGA involving a CPLD (CoolRunner 2) and SPI flash (M25P32). My FPGA is set up to serial master configuration mode. The FPGA is generating the clock for the CPLD and the CPLD transfers the data from the SPI flash to the DIN pin on the FPGA. I use the application notes and source code xapp800 from Xilinx. I monitor the CPLD and it steps through states (1-4): 1 STATE_RESET 2 LOAD_READ_OPCODE 3 LOAD_READ_ADDRESS 4 READ_DATA 5 WAIT_STATE The CPLD stays in state 4 where it waits for the FPGA to indicate configuration done by pulling the DONE pin high. The hardware seams to work. I can see the data on the DIN pin of the FPGA but the FPGA never indicates configuration done by pulling the DONE pin high. I think the problem may be the process of converting the .bit file to a format that can be written to the serial flash. Anyone that have any suggestions on how to find the problem? Andreas Beier Computer Systems EngineerArticle: 97076
I'm Xilinx user, but interestingly to hear Altera users too. Everybody knows what WebPACK is free. How long does it free? I see followng in the license when I install W.P.: "4.Term... this License is effective for one (1) year ... If you wish to extend this License, you must contact XILINX ... to determine the additional fees, terms and conditions ..." What I need to do after one year? Ask Xilinx to extend free license? Does anybody ask Xilinx to extend WebPACK free license? Is there anybody who can't extend license?Article: 97077
For all of you that attended our seminars recently, and those that didn't, an updated version of the Raggedstone1 based EDK lab is now available on our website. Link is off our Raggedstone1 webpage. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan-3 Development Board. http://www.enterpoint.co.ukArticle: 97078
zlyh wrote: > I'm Xilinx user, but interestingly to hear Altera users too. > > Everybody knows what WebPACK is free. How long does it free? I see > followng in the license when I install W.P.: > "4.Term... this License is effective for one (1) year ... If you wish > to extend this License, you must contact XILINX ... to determine the > additional fees, terms and conditions ..." > > What I need to do after one year? Ask Xilinx to extend free license? > Does anybody ask Xilinx to extend WebPACK free license? Is there > anybody who can't extend license? > I've had no problems at all renewing Altera web-edition licences. I'm sure the X&A members of this group can clarify better, but to my understanding the rationale behind the free editions is simply to remove a cost associated with people working with the smaller devices, and thus help people on shoestring budgets to stay with their products. Obviously they get their pound of flesh later on when you buy the parts for your product. If you're looking at using one of the more sophisticated/larger devices these might not be supported bt the web-edition, but if you're looking at designing onto those higher cost chips then the couple of thousand euro/dollars for the full edition tool is not a big part of the overall development cost anyhow. Also in the Quartus case for sure the web-edition doesn't give you SignalTap (built-in logic analyser) and I don't think it gives you ModelSim (could be wrong on that), so your ability to verify complex logic is somewhat diminished.Article: 97079
"Brian Davis" <brimdavis@aol.com> wrote in message news:1140059573.932785.146270@g44g2000cwa.googlegroups.com... > Following up on John Providenza's question about the DIFF_OUT > buffer feature, I've put together a small example which builds a > complementary clock input buffer out of two normal IBUFGDS's. > > Also for reference, I've copied my original notes about this handy > feature of the V2 & S3 families. > > Brian > Hi Brian, I'm struggling a little to see why I'd require a complementary clock. The DDR output IOBs have inversion control on both clock inputs, so why not just connect the normal clock to both pins and invert the appropriate one? Are you saying that a local inversion affects the skew? I have seen big clock nets' mark/space get affected by a lot of loads, is this the problem you're addressing? IFAIK, all the clocked resources have programmable inversion so what am I missing? Cheers, Syms.Article: 97080
I want to use the output of a R-C integrator as a delayed input to CPLD (inside there is a XOR gate and counter logic). It worked OK when I use discrete XOR IC 4070. But for same R-C values it doesn't works with CPLD. Is is due to the fact that analog input (sawtooth from integrator) has given to CPLD? Is comparator after integrator is one of the solution? Suggest other methods for creating delays inside CPLD. That will elliminate need of integrator. Here delay required is 1.1us.Article: 97081
SignalTap II will be enabled if you open the TalkBack backdoor...Article: 97082
Symon wrote: > > I'm struggling a little to see why I'd require a complementary clock. The > DDR output IOBs have inversion control on both clock inputs, so why not just > connect the normal clock to both pins and invert the appropriate one? Are > you saying that a local inversion affects the skew? > Exactly, the local inversion feature introduces quite a bit of skew, which can be avoided by using complementary internal clocks. (excluding from this discussion V4 with internal diff clock nets) The DIFF_OUT feature lets you get a low jitter complementary DDR clock on-board without needing a DCM (with its inherent jitter) It also can be used to invert a differential input right at the pad, which I didn't show in the example, but that same input net swap trick works with IBUFDS buffers too. From my past measurements of internal clocks (using clock forwarding) it looks like the internal clock net rise/fall is quite asymmetric; so, it's best to use the same edge sense of complementary clock phases. If you use a DCM with duty cycle correction, it pre-skews the driver so that both the threshold crossings line up again near 50%, but now you're stuck with the DCM jitter and other baggage ( and at higher input frequencies, eventually the duty cycle correction makes the clock pulse sallying forth from the driver extremely narrow ) > > I have seen big clock nets' mark/space get affected by a lot of loads, > is this the problem you're addressing? > Yes, that too; the other trick shown in the example is how to keep the two IOB DDR clock nets identically loaded by splitting the internal logic clock loads out onto another BUFG net. BrianArticle: 97083
Symon wrote > I'm struggling a little to see why I'd require a complementary clock. The > DDR output IOBs have inversion control on both clock inputs, so why not > just connect the normal clock to both pins and invert the appropriate one? > Are you saying that a local inversion affects the skew? from XAPP462, page 37: The CLKx clock signal precisely triggers the DDR flip-flop's C0 input at the start of the clock period. Similarly, the CLKx180 clock signal precisely triggers the DDR flip-flop's C1 input halfway through the clock period. The cost of this approach is an additional global buffer and global clock line, but it potentially reduces the potential duty-cycle distortion by approximately 300 ps..Article: 97084
"Brian Davis" <brimdavis@aol.com> wrote in message news:1140093044.468490.200370@z14g2000cwz.googlegroups.com... > Exactly, the local inversion feature introduces quite a bit of skew, > which can be avoided by using complementary internal clocks. > (excluding from this discussion V4 with internal diff clock nets) > > The DIFF_OUT feature lets you get a low jitter complementary > DDR clock on-board without needing a DCM (with its inherent jitter) > > It also can be used to invert a differential input right at the pad, > which I didn't show in the example, but that same input net swap > trick works with IBUFDS buffers too. > > From my past measurements of internal clocks (using clock forwarding) > it looks like the internal clock net rise/fall is quite asymmetric; so, > it's best to use the same edge sense of complementary clock phases. > > If you use a DCM with duty cycle correction, it pre-skews the driver > so that both the threshold crossings line up again near 50%, but now > you're stuck with the DCM jitter and other baggage ( and at higher > input frequencies, eventually the duty cycle correction makes the > clock pulse sallying forth from the driver extremely narrow ) > >> >> I have seen big clock nets' mark/space get affected by a lot of loads, >> is this the problem you're addressing? >> > Yes, that too; the other trick shown in the example is how to keep > the two IOB DDR clock nets identically loaded by splitting the internal > logic clock loads out onto another BUFG net. > > Brian > Thanks Brian, that makes sense. I've seen similar clock skew effects before, but never bad enough yet to need separate clocks. If I do, I'll remember your neat solution! In fact, I've just remembered something that I had to fix with a DCM doubler, I'll try this on it when I get time. BTW, as it comes for free, I guess it's a complimentary complementary clock! I'll get me coat... Cheers, Syms.Article: 97085
Hi all Does anyone know whether the ac coupling caps for PCIExpress should be located at the gold fingers or at the bridge chip. I have a layout in front of me and putting the caps next to the gold fingers would make the discontinuity just a little bit bigger, but putting them next to the bga adds another seperate discontinuity. The only advice that I've found says that they should go at the bridge but doesn't say why. Any pointers appreciated. ColinArticle: 97086
Brian Davis wrote: > I just tried downloading 8.1i SP2, after Xilinx recently > 'improved' their download page. > > I ended up in an endless loop of : > 1) click on download link > 2) allow script (IE6 SP2 message). > 3) back to starting page with no download > > I'd normally right click->save as to get around this, but > the new Xilinx download page uses scripts instead of > direct links to the files, which prevents one from right > clicking to get the complete .exe > > It took numerous tries of changing cookie/popup/script > settings before I found the right one: > > my original IE6 SP2 settings: > Internet Options->Security->Default Level at "medium" > > required change: > Internet Options->Security->Custom Level-> Downloads-> > automatic prompting for file downloads to "enable" You can also do "View source" and then cut and paste the link to the executable directly into the address bar. Cheers, JonArticle: 97087
"Tim" <tim@rockylogiccom.noooospam.com> wrote in message news:dt1sdk$pll$1$8300dec7@news.demon.co.uk... > from XAPP462, page 37: > > The CLKx clock signal precisely triggers the DDR flip-flop's C0 input at > the start of the clock period. Similarly, the CLKx180 clock signal > precisely triggers the DDR flip-flop's C1 input halfway through the clock > period. The cost of this approach is an additional global buffer and > global clock line, but it potentially reduces the potential duty-cycle > distortion by approximately 300 ps.. > Hi Tim, OK, I guess that's why I've not had problems with using just one clock. Even at >600Mbps I've got enough slack in my timing budget to cope with 300ps. Thanks for the reference! Cheers, Syms.Article: 97088
Hi there, unfortunately I have problems with DDR SDRAM Controller. I have an Avnet board with Xilinx Virtex-II FPGA (xc2v4000-ff1152)and Micron DDR SDRAM DIMM (MT4VDDT1664HG). I am using opencores DDR SDRAM controller. I have already adapted it and simulation with ModelSim works fine but I have real problems with the board. I synthesize and implement my design with Xilix Project Navigator 7.1 and upload it to my FPGA, also I used ChipScope to track signals. The controller just does not work. All signals seem to drive as they should during writing. During reading I see all zeros or just rubbish on data bus. I tried to change timing parameters but they don't affect. Any suggestions as to what I might have missed? Best, AdaArticle: 97089
One more question ^) Does it allowed to use (for private person or organization)Xilinx ISE WebPack for developing commercial projects ?Article: 97090
Dear MIrgorodsky:
After many experiments, I think the back-annotation command will copy
the pin/LE/memory/PLL placements into the .qsf file as the location
assignments, so after that you can see many location assignments in the
Assignment Editor. Then if you re-compile the project, the location
constraints will work and the Placement result will be the same.
For Incremental Compilation, the pro-fitting or pro-synthesis netlist will
be kept so there is no need to back-annotate the assignments. But you can
still use back-annotation with LogicLock feature, because LogicLock feature
can not preserve the netlist or Fitting result.
Regards,
<v_mirgorodsky@yahoo.com>
??????:1140002958.853166.259940@o13g2000cwo.googlegroups.com...
>I think I have sufficient knowledge in English, but still had troubles
> understanding what back-annotation is used for in Quartus II software.
> I have an assumption, that feature is designed to allow designer to
> compile certain piece of project the same way many times, even if you
> add some more functionality to the project.
>
> Let's say, you created a module with very tight margins on setup/hold
> timings, frequencies, etc. Adding more functionality will definitely
> change the layout of the whole chip and may affect your critical block
> timings. To protect your critical part of design you may create a
> back-annotation file, which will guide Quartus II about exact way how
> to layout the module to achieve the same performance during next
> builds.
>
> During my experiments I failed to get it work properly. Maybe I don't
> know how to read, or Quartus II help system omits some critical
> rules/restrictions. Don't understand the difference between this
> feature and LogicLock feature. For me, both are doing the same.
>
> To Alan Myler: always hate people, who respond your way to the
> questions in the news-group. If you don't have to say anything about
> the topic, just ignore the post. You don't have to respond in the
> group if you don't like the question, neither obligated offend
> original poster.
>
> With best regards,
> Vladimir S. MIrgorodsky
>
> Alan Myler wrote:
>> Try using the Help menu, select index, search for back annotation.
>>
>> Hope that gets you going in the right direction.
>>
>> Alan
>>
>>
>> Sophie Liu wrote:
>>
>> > Hi, Dears:
>> >
>> > I am using QuartusII now. I am not clear to back-annotate. What is
>> > back_annotate? and what's the use of back-annotate?
>> >
>> > Thank you!
>> >
>> >
>> >
>> > Jude
>> >
>
Article: 97091Tim wrote: > > from XAPP462, page 37: ><snip> >The cost of this approach is an additional global buffer and global > clock line, but it potentially reduces the potential duty-cycle distortion > by approximately 300 ps.. > Thanks for pointing out that link. One caution on XAPP462 v1.1 : the novice at Xilinx who wrote the "Skew Adjustment" section (pp 32-34) got the descriptions and figures completely backwards, and confused the terms 'skew' and 'delay'. Pages 4-5 of XAPP259 give a much better description of the delay element. ------ DESKEW_ADJUST = SYSTEM_SYNCHRONOUS : Inserts a delay into the DCM FEEDBACK path, which makes the output clock happen EARLIER. ( not later, as depicted in XAPP462 ) This increases setup, guarantees zero hold, and adds a temp and VCCAUX affected delay element into the DCM deskew path. DESKEW_ADJUST = SOURCE_SYNCHRONOUS : Removes delay element from the DCM FEEDBACK path, which makes the output clock happen LATER. ( not earlier, as depicted in XAPP462 ) This reduces setup time, increases hold time, but results in a smaller overall input sampling window. ------ For DDR input applications, or for cascaded DCM's, you generally want to be in SOURCE_SYNCHRONOUS mode (the latest few revisions may do that automatically for DCM cascades) See also Answer Records 12406, 18079 BrianArticle: 97092
Hey Peter, While I agree that the Xilinx and Altera peeps that lurk on these boards with us are helpful, I was more referring to their companies, with constant updates and poorly tested releases. I think the FAEs and such who explain all of these downfalls to us are just as much a victim to the problem as the rest of us. But hey, I'm just a dumb kid trying to make my way. I'll muddle through the EDK regardless. Why? Because I have to. See ya. ChrisArticle: 97093
nospam wrote: > David Brown <david@westcontrol.removethisbit.com> wrote: > >> nospam wrote: >>> Luc <bnl_rsm.lscc@telenet.be> wrote: >>> >>>> May I remind you that that the leadfree, RoHS and Green stuff started >>>> in Japan, not in Europe. >>> You may and I have heard the claim before, but when I look I find no >>> evidence that is it true. >>> >> As far as I understand it, Japan has had a number of restrictions such >> as lead-free (or at least, reduced lead), for many years. However, the >> restrictions are not as strict as the new EU directives. I couldn't >> give you any more details or pointers, however, nor can I remember where >> I read about it. > > From my limited browsing on the subject Japan has no 'lead free' > legislation. Early on some Japanese companies went lead free on certain > products so they could stick green labels on them and claim a marketing > advantage. > > When forthcoming Euro legislation was announced the Japanese (being > Japanese) recognised the potential of gaining an advantage over their > competitors by going lead free faster and better and that is what they have > been doing. Euro legislation was the driving force behind Japanese lead > free production but once started the green label marketing aspect became > more important making lead free production for domestic markets more or > less mandatory. > Thanks for that explanation! mvh., DavidArticle: 97094
ada wrote: > Hi there, > > unfortunately I have problems with DDR SDRAM Controller. I have an Avnet > board with Xilinx Virtex-II FPGA (xc2v4000-ff1152)and Micron DDR SDRAM > DIMM (MT4VDDT1664HG). I am using opencores DDR SDRAM controller. I have > already adapted it and simulation with ModelSim works fine but I have real > problems with the board. I synthesize and implement my design with Xilix > Project Navigator 7.1 and upload it to my FPGA, also I used ChipScope to > track signals. The controller just does not work. All signals seem to > drive as they should during writing. During reading I see all zeros or > just rubbish on data bus. > I tried to change timing parameters but they don't affect. > > Any suggestions as to what I might have missed? > > Best, > Ada The first thing I would check is your clock distribution. Make sure the clock to the DIMM and the FPGA have the same phase. Use a scope. Chipscope is O.K. for FPGA internals debug, but a real oscilloscope is the only way to make sure your signals reach the external parts as expected. Also make sure your FPGA pinout matches the Avnet board. Are you using a UCF file provided with the board? Also, the Micron models don't all check the initialization sequence required to start up the memory. Be sure your code provides the correct warm up period before your initial SDRAM access. This is especially important if the FPGA is driving the clock to the SDRAMs.Article: 97095
I don't see why it would matter where the caps go. At the frequencies of the link they look pretty much like wires anyway. This is not the same as a series termination resistor. The important thing is to use small parts that don't present a large bump in the Zo of the transmission lines. I'm assuming this is the discontinuity you speak of. If this gets large, then it makes sense to keep it close to the driving end of the runs. colin wrote: > Hi all > > Does anyone know whether the ac coupling caps for PCIExpress should be > located at the gold fingers or at the bridge chip. I have a layout in > front of me and putting the caps next to the gold fingers would make > the discontinuity just a little bit bigger, but putting them next to > the bga adds another seperate discontinuity. The only advice that I've > found says that they should go at the bridge but doesn't say why. > > Any pointers appreciated. > > ColinArticle: 97096
jboothbee@gmail.com wrote:
> Can anyone reccomend a text that will be good for transisiton
> between 7400 and VHDL ?
Here are some examples to get you started:
http://home.comcast.net/~mike_treseler/
-- Mike Treseler
Article: 97097Thats what i have found out, as for the caps the spec i have seen says that they should be no bigger than 0603 and between 75nF to 200nF, if that is of any help. REGARDS IAN. Home of the Low cost development board: RAGGEDSTONE1. WEB: www.enterpoint.co.uk "Gabor" <gabor@alacron.com> wrote in message news:1140102928.214073.71870@g44g2000cwa.googlegroups.com... >I don't see why it would matter where the caps go. At the frequencies > of > the link they look pretty much like wires anyway. This is not the same > as > a series termination resistor. > > The important thing is to use small parts that don't present a large > bump in the Zo of the transmission lines. I'm assuming this is > the discontinuity you speak of. If this gets large, then it makes > sense to keep it close to the driving end of the runs. > > colin wrote: >> Hi all >> >> Does anyone know whether the ac coupling caps for PCIExpress should be >> located at the gold fingers or at the bridge chip. I have a layout in >> front of me and putting the caps next to the gold fingers would make >> the discontinuity just a little bit bigger, but putting them next to >> the bga adds another seperate discontinuity. The only advice that I've >> found says that they should go at the bridge but doesn't say why. >> >> Any pointers appreciated. >> >> Colin >Article: 97098
hi, ive completed a introductory book on vhdl, but not mature enough to do a real world complex designs using vhdl. i've been serching for tutorial guids to learn advanced vhdl, preferebly with case studies, but found non. most of the books on vhdl are introductory level. Some advanced vhdl books such as "The Designer's Guide to VHDL" does not consider sysnthesis aspect much. beacause of this lack of resources, im planning to shift from VHDL to verilog. The book "Advanced Digital Design with the Verilog" seems to cover what im looking for and has a good rating with amazon. i need to know whther there are books such as this one for vhdl language. and a little comparison between vhdl and verilog based on the popularity for developing advanced deigital systems and support given by various software tools ( such as xilinx tools, modelSIM, etc) and any comments on the verilog book im talking about. thank youArticle: 97099
Sonali wrote: > I want to use the output of a R-C integrator as a delayed input to CPLD > (inside there is a XOR gate and counter logic). It worked OK when I use > discrete XOR IC 4070. But for same R-C values it doesn't works with > CPLD. > Is is due to the fact that analog input (sawtooth from integrator) has > given to CPLD? Yes. It probably only worked in the CMOS version because the parts are very slow as well as having a high threshold level. You should not normally provide slowly transitioning signals to digital logic unless the logic inputs have hysteresis (Schmitt triggers). > Is comparator after integrator is one of the solution? As long as the comparator has a fast enough edge rate for the CPLD. > Suggest other methods for creating delays inside CPLD. That will > elliminate need of integrator. Here delay required is 1.1us. This depends on your tolerance for delay jitter. For example if you had a 10 MHz clock you could use a shift register to delay 1.1uS +/- 0.1uS Depending on the CPLD, you may have inputs with hysteresis that would work like your original CMOS circuit. The R-C values may need to change to make up for the difference in threshold voltage.
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Compare FPGA features and resources
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