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The 8.1i version of webpack includes core generator. (don't know about MIG) I got burnt with a space in the install path name - core generator wouldn't run. Well thats not quite true, core gen would run but nothing would get generated, or I got a particular error message. It was covered by a Xilinx answer record. I posted the link to it in a recent post to this newsgroup. Regards Andrew maxascent wrote: > I am using ISE 8.1.02i webedition and have just installed the MIG 1.5 > coregen. When I try to use it nothing is generated. Do I need the full > version of ISE or should it work in the webedition? > > Thanks > > JonArticle: 99751
Hello all, I'm new with using Chipscope Pro 7.1 and need some help in how to use it correctly. I have a Virtex-2 Multimedia Board and EDK version 7.1 connected to it. The project contains MB processor and 2bit LED peripheral and includes a simple application program that switches LEDs on and off. I would like to get the exact trace of the waveform of the program, so I'm using Chipscope 7.1i to analyze the OPB bus. I placed the data and instruction memory on 2 BRAM blocks and connected them to the OPB bus. I also connected the chipscope ICON and OPB-IBA core. However, I don't know how to set the trigger correctly so to see the entire trace of the program on the bus. I tried using triggers: 1. OPB_ABUS <> 0 2. OPB_ABUS > 0 && OPB_ABUS < 0000 00C0 If the program has an infinite loop (LEDs on and off always), I see only the loop. If the program is short (LEDs on only once, with or without the use of an exit(1) command), all I see is 2 repeating commands on addresses 0x000000c0 and 0x000000c8 (the diodes are already lit, and the same instruction is read over and over again). Any comments and suggestions would be greatly appreciated! Thank you in advance! InesArticle: 99752
> Again, I don't see how writing always blocks is "unmaintainable." Maybe I haven't had enough experience Let met explain then. Here is the "proper RTL" as some other might right it : wire [31:0] a ; wire [31:0] b ; reg [32:0] result ; always @(posedge clk) result <= a + b ; Here is what you will find in many high end synthesizable RTL coding standard examples : wire[31:0] a ; wire[31:0] b ; wire[32:0] a_plus_b ; assign a_plus_b = a + b ; my_dff #(33) a_plus_b_32_0 ( .out( result ), .clk(clk), .in(a_plus_b) ) ; My simple assertion is that the added layer of indirection provided by the "my_dff" construct, and the seperate wire containing the result, gives me things easily, that would require RTL changes in the above example. Lets say I want to simulate my design and initialize all registers to a non-X state, just for simulations, just to see what would happen. I would swap in a different my_dff with the attribute that I want, it would change my compile script, but not my source code. There are plenty of other transformations that I may want to do on the code. If you don't ever do transformations on your code, and it all fits in a FPGA that you can plug into your real system and test, then you don't need this coding style. But if you pay millions of dollars per churn of an ASIC, you want to be able to have the flexibility in your Simulation testbench. Now to your point that you think it is easier to read the first examples. My only response is, "sure because you are used to it". If you worked in high end retargetable ASIC designs you would be used to writing the other way, and it would be just as easy to read. -ArtArticle: 99753
>Do you need to provide both clock and data, or just a >data stream, to the TX optical interface? Its just a data stream(8b/10b coded). The clock is embedded in the data as it were. Hence the need for a DPLL at the far end to recover the clock. >>If you need to provide the clock, can that portion of the >>optical interface be modified to accept an 8.192 MHz clock >>with 16.384 Mbps DDR data? I think I finally get the DDR idea. You are saying clock the DDR IOB with 8M, and the IOB will clock data out on +ve and -ve clock edges because its a DDR IOB. Which effectively has doubled the data rate. Without going too deeply into it, yes I think this could work. Quite like it actually... >>Is the jitter performance of the 8.192 MHz clock sufficient for >>your system link budget at a 2x data rate? Don't know is the short answer. >>Is the 8.192 Mhz clock close to 50% duty cycle? I would have thought so, but it is not specified. >>Is the chipset datsheet available online? No, we have it under NDA.Article: 99754
The code for Viterbi decoder that i have written, is not giving ERRORS during synthesis but is having like 100 warnings of some ports being disconnected. Is that possible that ,this is possible reason why the outputs on hardware FPGA Spartan stater kit not working? iMPACT is showing that the programming succeeded but the outputs are bad, nothing toggling. I used LEDS for O/Ps and switches for Inputs. But, i have Locked one switch for CLOCK on the kit itself and try to toggle the clock by hand. Would this sort of clock giving work?? OR is this bad because of frequency mismatch and low frequency. Please guide.Article: 99755
Please help! The code for Viterbi decoder that i have written, is not giving ERRORS during synthesis but is having like 100 warnings of some ports being disconnected. Is that possible that ,this is possible reason why the outputs on hardware FPGA Spartan stater kit not working? iMPACT is showing that the programming succeeded but the outputs are bad, nothing toggling. I used LEDS for O/Ps and switches for Inputs. But, i have Locked one switch for CLOCK on the kit itself and try to toggle the clock by hand. Would this sort of clock giving work?? OR is this bad because of frequency mismatch and low frequency. How can i actually give the clock and synchronise the inputs with pos edge of clock to see the outputs. Please guide. PreetArticle: 99756
"hongyan" <hy34@njit.edu> wrote in message news:1143591454.616221.68380@u72g2000cwu.googlegroups.com... > > Then when I do the synthesis, I got 33 logic levels (For another bigger > design including the adder, an even smaller number, ex 27) in the > critical path with Propagation time 5.043. I don't understand why the > number of logic level is less than the ALU alone. I suppose they should > be higher by adding the logic numbers. I am using synplifypro 8.1 for > the synthesis. > Hi, If this is a Xilinx design, try looking at the design in the timing analyser tool. It will show the logic levels, and you should be able to work out what's going on. HTH, and good luck, Syms.Article: 99757
Having just realized that ISE WebPack support ends at an XC3S1500 I set out to locate a Cyclone II EP2C70 based dev kit, but found nothing. I thought these parts were launched quite a while ago, what happend? (The XC3S5000 based Zefant DDR looked great until I was reminded of the lack of WebPack support. My budget cannot stretch to the full ISE.) Thanks, Tommy -- fpga (at) numba-tu.comArticle: 99758
Hello Guido,
A short piece od HDL is shown below to explain this:
module simple_bidir( clk, oe, bidir_pin, in_pin, out_pin );
input clk;
inout bidir_pin;
input oe;
input in_pin;
output out_pin;
reg in_reg, out_reg;
assign bidir_pin = oe ? in_reg : 1'bZ ;
always @ (posedge clk)
begin
in_reg <= in_pin;
out_reg <= bidir_pin;
end
assign out_pin = out_reg;
endmodule
A short answer is that three nodes, one data input, oe control line and one
data output, are required to acquire the signal activities on one bidir pin.
In the pre-synthesis node set, the bidir pin name is marked as tappable.
The connection is made only on the input side. The output direction needs
to be tapped on the driver to this pin. In the example above, you will need
to tap on the following nodes:
|simple_bidir|bidir_pin <- This will be the input direction.
|simple_bidir|in_reg <- This will be the output direction.
|simple_bidir|oe <- This is the oe control signal to indicate
the direction to pick.
In the post-fitting node set, the bidir pin name represents the IO pad,
which is not tappable. Nonetheless, the same principle applies. You will
need to find the names of the three nodes to tap. First, find the IO and
figure out the names affiliated to the input (DATAIN and OE) and output
(COMBOUT) ports of the IO cell. One easy and visual way to find the node
names, I found, is to use Resource Property Editor. In the connectivity
view of the IO cell, the signal names are listed. Depending on your version
of Quartus you can drag-and-drop the name into SignalTap II editor. In this
example, the node names are:
|simple_bidir|bidir_pin~1 <- This will be the input direction.
|simple_bidir|in_reg <- This will be the output direction.
|simple_bidir|oe <- This is the oe control signal to indicate
the direction to pick.
Hope this helps,
Subroto Datta
Altera Corp
"Guido" <gvaglia@gmail.com> wrote in message
news:1143537651.051352.64800@i39g2000cwa.googlegroups.com...
> Dear all,
> I am trying to using SignalTap to debug a design in which I have some
> bidirectional ports.
> Using both Pre-synthesis and Post-fitting (while using incremental
> routing) Signal-Tap signals I am not able to find the IO port in order
> to include it in the acquisition.
> I tried to find some answer in Altera website or in the manual but I
> found nowhere any reference to bidirectional ports and signaltap.
> Is it a limitation of the software?
> Is there a way to overcome it? Apart from introducing two more Input
> and Output port for watching the signal in both phases?
>
> Thank you all
>
> Guido
>
Article: 99759Peter Alfke wrote: > PLCC stands for Plastic Leadless Chip Carrier PLCC stands for Plastic *Leaded* Chip Carrier. It has J-leads, like an SOJ, but around a square package rather than down two parallel sides. > it is NOT through-hole. True.Article: 99760
Sorry, you are right, of course. Really ambarrassing... But it does not change the fact that they are NOT through-hole. Peter AlfkeArticle: 99761
Tommy, Lattice is shipping a 50k LUT fpga in our ECP2 family. Let me know where you are located and I'll push to get you hooked up with SW. Our ECP2 family has built in DQS support for both DDR1 & DDR2. Email me at ted.marena@latticesemi.comArticle: 99762
Andrew FPGA wrote:
>
> Its just a data stream(8b/10b coded). The clock is embedded in the data
> as it were.
>
OK; so if the 8.192 MHz input clock has decent duty cycle and jitter,
then using the DDR I/O should work for you since you don't need to
actually create an external 2x clock.
>
> I think I finally get the DDR idea. You are saying clock the DDR IOB
> with 8M, and the IOB will clock data out on +ve and -ve clock edges
> because its a DDR IOB. Which effectively has doubled the data rate.
> Without going too deeply into it, yes I think this could work. Quite
> like it actually...
>
Right, the Spartan-3's have the dual edge I/O, like Ralf described,
already built in to the IOBs.
If you're unfamiliar with those I/O features, I've included some
pointers to documentation and examples below.
>
> >>Is the jitter performance of the 8.192 MHz clock sufficient for
> >>your system link budget at a 2x data rate?
> Don't know is the short answer.
>
> >>Is the 8.192 Mhz clock close to 50% duty cycle?
> I would have thought so, but it is not specified.
>
OK; if the link already works for you at 8.192 MHz, that's a start;
I'd ask the manufacturer for more info, and measure it yourself.
Brian
Spartan3 Dual Data Rate I/O information:
- Spartan3 datasheet, Section 2: Functional Description
DS099-2 (v1.4) pages 2-4, Double-Data-Rate Transmission
- local clock DDR inversion
XAPP462 (v1.1) figure 28
- Libraries Guide, DDR output components
OFDDRCPE, OFDDRRSE, OFDDRTCPE, OFDDRTRSE
- DDR serializer app. note example
XAPP514 (v2.0) figure 2-6, page 40
- DDR clock forwarding example using DIFF_OUT clock buffer
(which would be overkill at 8.192 MHz )
http://groups.google.com/group/comp.arch.fpga/msg/90e445167a1fb49a
Additional Cheap Clock Multiplier Suggestions:
If you do eventually need to create an external multiplied clock,
besides the PLL and frequency doubler suggestions already made,
at these clock rates you can also build simple x5 harmonic
multipliers out of CMOS gates and a few discretes, see:
http://www.wenzel.com/pdffiles/hcmos.pdf
A divide-by-two times five would get you to 20.48 MHz, with no
worries about input duty cycle. Make sure you treat the gates
in such a harmonic multiplier as precision analog parts, using
good bypass and layout practices.
Article: 99763> OK; if the link already works for you at 8.192 MHz, that's a start; > I'd ask the manufacturer for more info, and measure it yourself. PCB is being routed as we speak so can't measure it right now. But, even if I could measure it, and even if I got some jitter transfer function info from the manufacturer, I expect the 8M jitter will still be pretty dependent on the upstream DSL equipment, HDSL link quality etc.... At the end of the day, the xDSL signal can't be jittered so badly that the xDSL framer can't sync up and recover data.... Brian Davis wrote: > Andrew FPGA wrote: > > > > Its just a data stream(8b/10b coded). The clock is embedded in the data > > as it were. > > > OK; so if the 8.192 MHz input clock has decent duty cycle and jitter, > then using the DDR I/O should work for you since you don't need to > actually create an external 2x clock. > > > > > I think I finally get the DDR idea. You are saying clock the DDR IOB > > with 8M, and the IOB will clock data out on +ve and -ve clock edges > > because its a DDR IOB. Which effectively has doubled the data rate. > > Without going too deeply into it, yes I think this could work. Quite > > like it actually... > > > Right, the Spartan-3's have the dual edge I/O, like Ralf described, > already built in to the IOBs. > > If you're unfamiliar with those I/O features, I've included some > pointers to documentation and examples below. > > > > > >>Is the jitter performance of the 8.192 MHz clock sufficient for > > >>your system link budget at a 2x data rate? > > Don't know is the short answer. > > > > >>Is the 8.192 Mhz clock close to 50% duty cycle? > > I would have thought so, but it is not specified. > > > OK; if the link already works for you at 8.192 MHz, that's a start; > I'd ask the manufacturer for more info, and measure it yourself. > > Brian > > Spartan3 Dual Data Rate I/O information: > > - Spartan3 datasheet, Section 2: Functional Description > DS099-2 (v1.4) pages 2-4, Double-Data-Rate Transmission > > - local clock DDR inversion > XAPP462 (v1.1) figure 28 > > - Libraries Guide, DDR output components > OFDDRCPE, OFDDRRSE, OFDDRTCPE, OFDDRTRSE > > - DDR serializer app. note example > XAPP514 (v2.0) figure 2-6, page 40 > > - DDR clock forwarding example using DIFF_OUT clock buffer > (which would be overkill at 8.192 MHz ) > http://groups.google.com/group/comp.arch.fpga/msg/90e445167a1fb49a > > > Additional Cheap Clock Multiplier Suggestions: > > If you do eventually need to create an external multiplied clock, > besides the PLL and frequency doubler suggestions already made, > at these clock rates you can also build simple x5 harmonic > multipliers out of CMOS gates and a few discretes, see: > > http://www.wenzel.com/pdffiles/hcmos.pdf > > A divide-by-two times five would get you to 20.48 MHz, with no > worries about input duty cycle. Make sure you treat the gates > in such a harmonic multiplier as precision analog parts, using > good bypass and layout practices.Article: 99764
Have you simulated this design? The xilinx tools come with a free version of Modelsim(a simulator). Write a testbench in VHDL/verilog to generate stimulus for your design, then have a look in the waveform window to see if the outputs and internal signals are as you were expecting. Using a switch as a clock is like lending your wife the credit card. Anything could happen. Get a scope and have a look at the switch output when you press the switch. Most likely you will see it glitch up and down quickly as you depress the switch. Get it working in the simulator first, then think about getting it to work on real hardware.Article: 99765
Manpreet schrieb: > Please help! > > The code for Viterbi decoder that i have written, is not giving ERRORS during synthesis but is having like 100 warnings of some ports being disconnected. > > Is that possible that ,this is possible reason why the outputs on hardware FPGA Spartan stater kit not working? > > iMPACT is showing that the programming succeeded but the outputs are bad, nothing toggling. I used LEDS for O/Ps and switches for Inputs. But, i have Locked one switch for CLOCK on the kit itself and try to toggle the clock by hand. > > Would this sort of clock giving work?? OR is this bad because of frequency mismatch and low frequency. > > How can i actually give the clock and synchronise the inputs with pos edge of clock to see the outputs. > > Please guide. > > Preet Hi Preet, have you provided any debouncing circuitry for your clock (and inputs)? Otherwise, every press and release of the clock button results in an unknown number of clock pulses. (Keep in mind that a debouncing circuit needs to be clocked with less than 100 Hz!) For the disconnected ports: Do a simulation! Does it work? Do the outputs toggle? Check your synthesis report. Is there a warning about some signals (preferably Enables) becoming tied to VCC or GND? This causes XST to eliminate the following circuits for their outputs will remain constant as well. And because the other inputs of these circuits are not used anymore they become disconnected. Do you feed the clock into a DLL/DCM? This might not work with a manual clock. At least DLLs need a minimum Clock frequency! Have a nice synthesis EilertArticle: 99766
Hi, Here is the trace when using the kernel 2.4 devel Xilinx Virtex-II Pro port (C) 2002 MontaVista Software, Inc. (source@mvista.com) On node 0 totalpages: 16384 zone(0): 16384 pages. zone(1): 0 pages. zone(2): 0 pages. Kernel command line: console=ttyS0,9600 root=/dev/xsysace/disc0/part3 rw Xilinx INTC #0 at 0x41200000 mapped to 0xFDFFE000 Calibrating delay loop... 99.73 BogoMIPS Oops: kernel access of bad area, sig: 11 NIP: 00000000 XER: 0000005E LR: 00000000 SP: C0182E50 REGS: c0182da0 TRAP: 0400 Not tainted MSR: 00001030 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 11 TASK = c0181020[0] 'swapper' Last syscall: 0 last math 00000000 last altivec 00000000 GPR00: 00000000 C0182E50 C0181020 C0181020 00000000 00000001 C0181120 00000048 GPR08: 00000048 00000000 00000000 00000017 24000022 0000CC60 00000000 00000000 GPR16: 00000000 00000000 00000000 00000000 00001032 00182ED0 00000000 C0000000 GPR24: C019DDB0 00000001 C01A0000 C01A0000 044AA234 00000001 00000000 C0181020 Call backtrace: 00000000 C001C27C C0005F30 C00047C0 C0196064 C01943B8 C019154C C0002328 Kernel panic: Aiee, killing interrupt handler! In interrupt handler - not syncing <0>Rebooting in 180 seconds.. I have also just tried to use xmon in the kernel which indicates a kernel stack overflow (?!?). If this can be of any help understanding the problem. Best regards, JF HassonArticle: 99767
Symon schrieb: > "hongyan" <hy34@njit.edu> wrote in message > news:1143591454.616221.68380@u72g2000cwu.googlegroups.com... >> Then when I do the synthesis, I got 33 logic levels (For another bigger >> design including the adder, an even smaller number, ex 27) in the >> critical path with Propagation time 5.043. I don't understand why the >> number of logic level is less than the ALU alone. I suppose they should >> be higher by adding the logic numbers. I am using synplifypro 8.1 for >> the synthesis. >> > Hi, > If this is a Xilinx design, try looking at the design in the timing analyser > tool. It will show the logic levels, and you should be able to work out > what's going on. > HTH, and good luck, Syms. > > Hi Symon two more tips: 1) How about the wire delays at the inputs? Are they reduced when you use registers? 2) Is your tool performing some sort of register balancing for timing improvement? This may cause portions of the adder to be placed before the registers thus reducing the logic levels of the adder itself. have a nice synthesis EilertArticle: 99768
Thats pretty cool as long as synthesis tool correctly translates it.!!!! I have been using this function for indexing the std_logic arrays and as memory pointers.....Article: 99769
I hope this will work
wire [31:0] a;
reg [7:0] b [31:0];
reg [2:0] bit;
genvar i;
generate
for( i=0; i<32; i=i+1 )
begin : A
a[i] = b[i][bit];
end
endgenerate
>XST burps up "Unexpected event in always block sensitivity list." with
>that syntax.
Also observed similar problem. Problem is that the Xilinx ISE is not
accepting multidimnsional array in the sensitivity list. But it will
work with synplify.
Article: 99770inesviskic@gmail.com wrote: > Hello all, > I'm new with using Chipscope Pro 7.1 and need some help in how to use > it correctly. > I have a Virtex-2 Multimedia Board and EDK version 7.1 connected to it. > The project contains MB processor and 2bit LED peripheral and includes > a simple application program that switches LEDs on and off. I would > like to get the exact trace of the waveform of the program, so I'm > using Chipscope 7.1i to analyze the OPB bus. > I placed the data and instruction memory on 2 BRAM blocks and connected > them to the OPB bus. I also connected the chipscope ICON and OPB-IBA > core. > However, I don't know how to set the trigger correctly so to see the > entire trace of the program on the bus. I tried using triggers: > 1. OPB_ABUS <> 0 > 2. OPB_ABUS > 0 && OPB_ABUS < 0000 00C0 > If the program has an infinite loop (LEDs on and off always), I see > only the loop. If the program is short (LEDs on only once, with or > without the use of an exit(1) command), all I see is 2 repeating > commands on addresses 0x000000c0 and 0x000000c8 (the diodes are already > lit, and the same instruction is read over and over again). > Any comments and suggestions would be greatly appreciated! > Thank you in advance! > Ines > It depends on how your application execute. Do a "mb-objdump -S" and look at the code. What program is initialized into the BRAM in the bitstream? Do you download your program using XMD and then execute it? GöranArticle: 99771
Tommy Thorn schreef: > Having just realized that ISE WebPack support ends at an XC3S1500 I set > out to locate a Cyclone II EP2C70 based dev kit, but found nothing. I > thought these parts were launched quite a while ago, what happend? > > (The XC3S5000 based Zefant DDR looked great until I was reminded of the > lack of WebPack support. My budget cannot stretch to the full ISE.) > > Thanks, > Tommy -- fpga (at) numba-tu.com Look at the EP2C35F672 based development kits and swap the device. You will loose around 50 I/O's on the EP2C70 but if you are lucky the DDR interfaces remain OK (did not check this) Happy soldering ! Karl.Article: 99772
Hallo, I' developing a microcontroller based on powerpc. the only way I know to store some variables into a specific region of memory is instantiating them directly using the command: unsigned char (*variable_name) = (unsigned char(*))XPAR_PERIPHERAL_BASEADDR; There are other ways? If use use the linker script there is a way to "choose" which variables store into a certain region of memory? Many Thanks MarcoArticle: 99773
Karl wrote: > Look at the EP2C35F672 based development kits and swap the device. You > will loose around 50 I/O's on the EP2C70 but if you are lucky the DDR > interfaces remain OK (did not check this) > > Happy soldering ! > > Karl. I checked... The Altera DSP development kit is made for 2C35 2C50 and 2C70. The additional I/O's on the 2C35 and 2C50 are not used and you should be able to do this trick. Karl.Article: 99774
> C-people are hardly all the same cookie cutter experience levels > [...] > Such blind generalizations are .... no offense intended - I don't know the OP and his skills It is my personal experience with "software" colleagues and students trying to start with FPGA projects ... It just takes some time to get familiar with those concepts and workflows ... if you know how to think in hardware, then VHDL should not be the big problem. bye, Michael
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