Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 99600

Article: 99600
Subject: Re: Altera IP address?
From: "Nial Stewart" <nial@nialstewartdevelopments.co.uk>
Date: Mon, 27 Mar 2006 12:04:33 +0100
Links: << >>  << T >>  << A >>
> There's no point having an IP address because the site doesn't
> respond, even when you have one.

Oh aye, I thought it was just DNS issues.

As you say, for a company like Altera ...

> it's a rather comical way to operate in 2006.

Unbelieveable.


Nial.



Article: 99601
Subject: Re: Altera web site inaccessible
From: Jan Panteltje <pNaonStpealmtje@yahoo.com>
Date: Mon, 27 Mar 2006 11:05:41 GMT
Links: << >>  << T >>  << A >>
On a sunny day (Mon, 27 Mar 2006 11:02:41 +0200) it happened Petter Gustad
<newsmailcomp6@gustad.com> wrote in
<87mzfc9s5q.fsf@filestore.home.gustad.com>:

>"Antti" <Antti.Lukats@xilant.com> writes:
>
>> you right, from germany web browser says that it cant find DNS lookup
>
>I have no problems:
>
>$dig www.altera.com | grep ^www.altera.com
>www.altera.com.         511     IN      A       66.35.227.20
>$wget http://www.altera.com/literature/hb/stx2gx/stxiigx_handbook.pdf
>
>Gives me the Stratix IIGX handbook without problems. BTW I'm located
>in Oslo, Norway.
>
>Petter

Altera (HELLO!!!!) still does not work from the Netherlands today (monday),
it did not work sunday either.
Neither does the IP 66.35.227.20 directly



Article: 99602
Subject: Re: Altera web site inaccessible
From: Jim Granville <no.spam@designtools.co.nz>
Date: Mon, 27 Mar 2006 23:32:12 +1200
Links: << >>  << T >>  << A >>
tcollera@altera.com wrote:

> All,
> 
> I can assure you that the site is up, but we are having technical
> problems that are being worked as I type. I can not give an ETA to
> normal operation at this time.
> 
> Tim Colleran
> Altera Corp.

Well Up in Ireland, and Norway, but not in many other places it seems ?

-jg



Article: 99603
Subject: Re: Clock multiplication without using the Xilinx DCM's
From: "Brian Davis" <brimdavis@aol.com>
Date: 27 Mar 2006 04:31:24 -0800
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> Brian, if you start with sn 8 MHz signal with a duty cycle significntly
> different from 50%, there is no way (in hell) to generate a low-jitter
> 16 MHz output, without using a DLL or PLL or other complicated timing
> circuit. That's really basic.

 Did you bother with the basic step of actually reading my
first post before composing that silly dig at me?

The very first line of my very first post on the thread said:
>
> If the 8.192 clock were differential, and the duty cycle good,
>

 Andrew didn't reference the exact spec sheet to determine
the output duty cycle, but his concern was not that the jitter
was too bad to generate the output data stream data, but
rather that it exceeded the input jitter specs of your DCM's.

 So I suggested using DDR I/O, with no DCM, to generate
a 2x output data stream- a perfectly valid notion if the
input duty cycle is OK at the slow 8.192 MHz clock rate.

Brian

  p.s. And as for your claim that "there's no way in hell", if the
fundamental is clean but just has poor duty cycle, a simple filter
and doubler would work fine to generate a 2x clock


Article: 99604
Subject: Re: Altera web site inaccessible
From: pbdelete@spamnuke.ludd.luthdelete.se.invalid
Date: 27 Mar 2006 12:53:07 GMT
Links: << >>  << T >>  << A >>
MikeShepherd564@btinternet.com wrote:

>The Altera web site has been inaccessible now for over 48 hours.

>Further investigation this evening shows that only certain clients are
>blocked.  (I can see their home page via a proxy, but that proxy won't
>let me download large documents).  A "tracert" reaches somewhere in
>Santa Clara.

>From consultation with another, at least two large ISPs in the UK are
>blocked.

>Does anyone know why they do this?  I wanted to download one of their
>PDF documents, but the site don't respond (even to pings).

>I'm still at the development kit stage and everything I've seen of
>Altera so far makes me think "Surely Xilinx can't be as bad as this?".
>It's difficult to see how we can ever use Altera products when they
>block our access to their site.

I don't think it's a block. It sounds like a messed up BGP announcement.


Article: 99605
Subject: Re: Memory leaks with ISE 8.1
From: "typhon62" <typhon62@comcast.net>
Date: 27 Mar 2006 04:57:05 -0800
Links: << >>  << T >>  << A >>

You don't need a project at all, just start ISE then close it 10 or so
times.  You'll notice that every time you do this the system has a bit
less memory.  I looked one day after using ISE my system was using
1.5Gig of memory and NOTHING was running.

As far as entering a webcase, I've no energy to deal with Xilinx's tech
support any more.  Since Xmas I've entered 4 cases (not under this name
in case you look).  I had a very serious problem with BLVDS in a
Spartan3E and it took me WEEKS just to get Xilinx to reproduce the
problem.  Most of my cases were sent to someone in China for support
and that gives you about 1 email a day to work things out.  My problem
was 100% reproducible but it took them weeks to reproduce it because
they did not have a Spartan3E board!!!

It is much less painful for me to re-boot my system every day when it
starts to bog down than it is to go through another web case.  My FAE
knows of this and said he was going to enter a case on this soon.  Last
week I found a test bench generator bug that need to be looked into
also.  I would gladly go back to 7.1, but 7.1's bitgen screws up BLVDS
for the Spartan3E, which is what I'm presently working on.

Sorry for the rant, but I'm a bit tender when Xilinx tech support comes
up lately...


Article: 99606
Subject: Re: Problem with LwIP and MicroBlaze
From: "Anonymous" <someone@microsoft.com>
Date: Mon, 27 Mar 2006 13:15:52 GMT
Links: << >>  << T >>  << A >>
I'm sure it can run stand alone. If you go to http://www.em.avnet.com/ and
then to the design resource center there is an example application under the
Xilinx v4fx12 mini-module called something TEMAC example. It is an embedded
webserver that is run from scratch on top of lwip. I've just tried it today
on my evm.

-Clark

"Raymond" <raybakk@yahoo.no> wrote in message
news:1143448036.860356.267840@j33g2000cwa.googlegroups.com...
> Hi Marco.
>
> I tought that I could use LwIP without any OS. Think I have read that
> someplace but could not find it again now.
> I don't know yet what the error is, but it might be that LwIP needs the
> xilkernel (I don't know yet).
> I have some interrupt in my work now and I am going to have to take up
> the thread again in the next week.
>
> Do you know if the LwIP needs an OS of any kind (as spoken, I thought
> that it supported OSless systems).
> My system is now without OS. If it needs an OS I will maybe consider
> Linux instead of xilkernel.
>
> Raymond
>



Article: 99607
Subject: Re: Linux on ml403
From: "Anonymous" <someone@microsoft.com>
Date: Mon, 27 Mar 2006 13:19:24 GMT
Links: << >>  << T >>  << A >>
Can you post your boot messages?

"jfh" <jean-francois.hasson@fr.thalesgroup.com> wrote in message
news:1143440508.866449.128480@z34g2000cwc.googlegroups.com...
> Hi,
>
> I have been trying to port Linux on the ML403 board using the 2.4 devel
> tree downloaded from montavista site using rsync.The compilation goes
> fine with the modifications of some source files and makefiles after
> copying the BSP generated from EDK 7.1 (I used some BYU website advice
> about porting Linux on XUV2P board). I manage to download the Linux
> kernel via xmd, the kernel boots but it has a problem and an exception
> 0400 seems to occur. Did anyone try the same method and managed it
> correctly ? Does anyone have an idea as to why I have this exception ?
> How could I investigate this issue not being an expert in  Linux but
> just trying to understanding what is going on ?
>
> Best regards,
>
> JF
>



Article: 99608
Subject: Verilog, PSL or SystemVerilog of OVL?
From: "Davy" <zhushenli@gmail.com>
Date: 27 Mar 2006 06:09:10 -0800
Links: << >>  << T >>  << A >>
Hi all,

I am a Verilog user.
I want to use assertion based verification in my project. And I found
OVL(Open Verification library).

Do you think which one of the OVL is better? Verilog, PSL or
SystemVerilog?

And I heard SystemVerilog have the ABV feature? Why OVL supply ABV in
SystemVerilog again?

Best regards,
Davy


Article: 99609
Subject: Re: OpenSPARC released
From: "Sandro" <sdroamt@netscape.net>
Date: 27 Mar 2006 06:14:16 -0800
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> I wonder if there is any reason why it would be useful to compile the
> verilog for a FPGA?

I don't understand...
What You mean?
 - Verilog is the problem (VHDL is better) or
 - "openSparc Verilog" is the problem (better other "soft-cpu") ?

Sandro


Article: 99610
Subject: Re: Clock multiplication without using the Xilinx DCM's
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Mon, 27 Mar 2006 16:48:34 +0200
Links: << >>  << T >>  << A >>
Andrew FPGA schrieb:

> Does anyone have any hints of practicle FPGA techniques for generating
> a higher clock? A doubling of the clock frequency would be enough. Just
> the name of a technique would be enough to get me googling...

It depends on your output jitter requirements. Some time ago, I did a 
DPLL inside a Spartan 3, generation a 8192 kHz signal locked to a 8 kHz 
reference clock (we are telecom guys, are we ;-)
This DPLL was running at 131.072 MHz (4x 32.768 MHz). As you can easy 
see, this results in a jitter of about 0.12 UI.
If you generate twice the frequncy, you will get 0.24 UI jitter, pretty 
much right now.
This DPLL can be pushed up to 200MHz, with some tricks maybe to 300-400 
(effective clock rate using DDR stuff).

But the question is, is this really worth it? At 16 Mhz, even the good 
old 4046 will work and give you much less then 0.1 UI jitter. For a dollar.

Regards
Falk

Article: 99611
Subject: Re: Clock multiplication without using the Xilinx DCM's
From: Ralf Hildebrandt <Ralf-Hildebrandt@gmx.de>
Date: Mon, 27 Mar 2006 16:51:35 +0200
Links: << >>  << T >>  << A >>
Andrew FPGA wrote:
> Hi,
> We are developing a product that passes data between an xDSL interface
> and a proprietory optical interface. We are using a Spartan 3 FPGA. The
> xDSL chipset generates an 8.192MHz clock that is recovered from the DSL
> line. (The xDSL chipset uses a digital phase locked loop for this). The
> current FPGA design uses this clock internally, and uses it to clock
> the optical interface also. Single clock domain, nice.
...
> A doubling of the clock frequency would be enough. Just
> the name of a technique would be enough to get me googling...

If you don't need the doubled clock as an output, but want to operate at 
the doubled frequency, you could use both clock edges. A way to get 
fully synthesizable dual-edge behavior I've described in 
<http://www.ralf-hildebrandt.de/publication/pdf_dff/pde_dff.pdf>. This 
idea is not limited to just flipflops. You may also extend it easily to 
dual-edge state machines.


> The xdsl chipset also has a local oscillator at 22MHz - but it just
> free runs of course...I could invisage a plesiosynchronous scheme where
> the optical link runs at 22MHz and I bit stuff to get the required data
> rate. But it feels too complex, overkill. And then I have to think more
> carefully about the optical link clock recovery at the far end.

Does this oscillator run fixed at 22MHz or is it it's maximum and it is 
modified by the PLL? If it is modified by the PLL, would it be an option 
to let the PLL generate the doubled clock, divide it by two, feed it 
back and synchronize this divided clock?


Ralf

Article: 99612
Subject: Re: OpenSPARC released
From: Allan Herriman <allanherriman@hotmail.com>
Date: Tue, 28 Mar 2006 00:55:39 +1000
Links: << >>  << T >>  << A >>
On 27 Mar 2006 06:14:16 -0800, "Sandro" <sdroamt@netscape.net> wrote:

>Austin Lesea wrote:
>> I wonder if there is any reason why it would be useful to compile the
>> verilog for a FPGA?
>
>I don't understand...
>What You mean?
> - Verilog is the problem (VHDL is better) or
> - "openSparc Verilog" is the problem (better other "soft-cpu") ?

It appears openSparc Verilog is written to target an ASIC, not an
FPGA.  Whilst it might be possible to get it to compile and even fit
into an FPGA, the performance would probably not be stunning.

In that sense, a different soft-cpu designed to be used on an FPGA
would probably be better.

Regards,
Allan

Article: 99613
Subject: Re: Memory leaks with ISE 8.1
From: "Mike Treseler" <mike_treseler@comcast.net>
Date: Mon, 27 Mar 2006 07:01:16 -0800
Links: << >>  << T >>  << A >>
typhon62 wrote:
> Yes, I've seen thit too.  It's not as bad since SP2, but its still
> there.
> I used to bitch about Quartus all of the time, since 8.x came out all I
> do is bitch about ISE.
> 

Neither ISE or Quartus are good environments for design
entry or validation. I prefer a text editor and
HDL simulator for that purpose. However, both ISE and Quartus
do a credible job at synthesis and place+route
if you start with known-good HDL files.

           -- Mike Treseler

Article: 99614
Subject: Re: spartan FPGA with PLCC package
From: "Leon" <leon.heller@bulldoghome.com>
Date: 27 Mar 2006 07:07:20 -0800
Links: << >>  << T >>  << A >>

kulkarku@math.net wrote:
> Hi,
> is any spartan FPGA is in PLCC package?also its availabilty ?
> I want to use spartan series FPGA & not the any other spartan seris
> like spartan 2e etc.
> which sprom should be used?

I've got some Spartan XL chips in PLCC somewhere. They are probably
still available from Farnell, as well as the configuration devices.

Leon.


Article: 99615
Subject: Re: Lattice FPGA
From: "Paul Leventis" <paul.leventis@gmail.com>
Date: 27 Mar 2006 07:11:12 -0800
Links: << >>  << T >>  << A >>
Hi Austin,

You will be happy to know that Stratix II GX is real and exceeding our
expecations on HSSI performance.  See
http://ca.us.biz.yahoo.com/prnews/060327/sfm015.html?.v=46

Regards,

- Paul


Article: 99616
Subject: Re: Memory leaks with ISE 8.1
From: "Paul Leventis" <paul.leventis@gmail.com>
Date: 27 Mar 2006 07:17:40 -0800
Links: << >>  << T >>  << A >>
Hi Mike,

Quartus isn't a bad entry tool for HDL.  It used to be until a few
years ago, but the HDL parsing and synthesis have improved
substantially.  It gives you good error messages that locate you back
to the offending bit of code.  3rd party synthesis tools offer a lot of
value, but I wouldn't go so far as to say that you need "known-good HDL
files" to use Quartus!

And Quartus doesn't leak any memory ;-)

Regards,

Paul Leventis
Altera Corp.


Article: 99617
Subject: Re: Altera web site inaccessible
From: Ray Andraka <ray@andraka.com>
Date: Mon, 27 Mar 2006 10:44:45 -0500
Links: << >>  << T >>  << A >>
pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote:
> MikeShepherd564@btinternet.com wrote:
> 
> 
>>The Altera web site has been inaccessible now for over 48 hours.
> 
> 
>>Further investigation this evening shows that only certain clients are
>>blocked.  (I can see their home page via a proxy, but that proxy won't
>>let me download large documents).  A "tracert" reaches somewhere in
>>Santa Clara.
> 
> 
>>From consultation with another, at least two large ISPs in the UK are
> 
>>blocked.
> 
> 
>>Does anyone know why they do this?  I wanted to download one of their
>>PDF documents, but the site don't respond (even to pings).
> 
> 
>>I'm still at the development kit stage and everything I've seen of
>>Altera so far makes me think "Surely Xilinx can't be as bad as this?".
>>It's difficult to see how we can ever use Altera products when they
>>block our access to their site.
> 
> 
> I don't think it's a block. It sounds like a messed up BGP announcement.
> 
It's working fine here in the NorthEast USA, and was fine Sunday as well.

Article: 99618
Subject: Re: Lattice FPGA
From: Austin Lesea <austin@xilinx.com>
Date: Mon, 27 Mar 2006 08:16:05 -0800
Links: << >>  << T >>  << A >>
Paul,

Congratulations.  I have read the press announcement.

Stratix II GX is shipping(now), along with the eval pcb.

Good luck,

Austin

Paul Leventis wrote:

> Hi Austin,
> 
> You will be happy to know that Stratix II GX is real and exceeding our
> expecations on HSSI performance.  See
> http://ca.us.biz.yahoo.com/prnews/060327/sfm015.html?.v=46
> 
> Regards,
> 
> - Paul
> 

Article: 99619
Subject: Variable Bus Input/Output Fifo
From: "Dominic" <dominicwalkes@yahoo.com>
Date: 27 Mar 2006 08:24:57 -0800
Links: << >>  << T >>  << A >>
Has anyone ever written a variable width fifo?  I would like to have a
fifo that accepts a 32-bit input and reads out a 16 bit output.


Article: 99620
Subject: Re: Memory leaks with ISE 8.1
From: "Mike Treseler" <mike_treseler@comcast.net>
Date: Mon, 27 Mar 2006 08:58:15 -0800
Links: << >>  << T >>  << A >>
Paul Leventis wrote:

> Quartus isn't a bad entry tool for HDL.

I didn't say bad, I said not good for design entry.
I guess I could spin that up to adequate for you.
And outside of design entry it *is* good.
Your static timing analyzer and RTL viewer
are the best I've see for FPGAs.

My main knock against ISE and Quartus is that
these tools foster dependence on vendor-specific
wizards and core generators. I would like to
see support at design entry for HDL inference
of the same structures, and RTL instead of
netlist based simulation.

       -- Mike Treseler

Article: 99621
Subject: Re: Spartan 3e Starter Kit finally available? No, not really.
From: Tommy Thorn <foobar@nowhere.void>
Date: Mon, 27 Mar 2006 09:02:30 -0800
Links: << >>  << T >>  << A >>
John Adair wrote:
> Well we might beat them out with Tarfessock1 after all then.
> 
> John Adair
> Enterpoint Ltd. - Soon to be Home of Tarfessock1. The PCMCIA Spartan-3E 
> Development Board.

Can you share a bit of the specs?  If it has an XC3S1600E and megabytes 
of external storage then I'm interested.

Tommy

Article: 99622
Subject: Re: Variable Bus Input/Output Fifo
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Mon, 27 Mar 2006 18:10:28 +0100
Links: << >>  << T >>  << A >>
Yes

The blockrams in Xilinx architectures lend themselves nicely to doing this. 
In your case you need to count in words the amount you have stored. Index 
addressing used to access the ram for input and output should differ in size 
by one bit more on the 16bit side than the 32bit side.

John Adair
Enterpoint Ltd. - Home of Broaddown4. The Ultimate Virtex-4 Development 
Board.
http://www.enterpoint.co.uk


"Dominic" <dominicwalkes@yahoo.com> wrote in message 
news:1143476696.958566.299750@u72g2000cwu.googlegroups.com...
> Has anyone ever written a variable width fifo?  I would like to have a
> fifo that accepts a 32-bit input and reads out a 16 bit output.
> 



Article: 99623
Subject: Re: Xilinx Square Root Unit
From: "Brannon" <brannonking@yahoo.com>
Date: 27 Mar 2006 09:10:59 -0800
Links: << >>  << T >>  << A >>
I just compiled the single-prec version of it at 150MHz on a V2 part
speed -4. 166MHz just barely fails. I show it uses 490-522 slices (275
of which include LUT usage) depending on mapper settings and not
counting registers on each end. It has a pipelength of 17 clock cycles:
two bits per clock cycle plus a few for the left justification. For
comparison, the double-prec version runs at the same speed and uses apx
1940 slices. In both cases, there are more than twice as many registers
used as LUTs. The double-prec has a pipelength of 31 clock cycles.


Article: 99624
Subject: Opb Spi Controller Trouble
From: "Marco T." <marc@blabla.com>
Date: Mon, 27 Mar 2006 19:19:46 +0200
Links: << >>  << T >>  << A >>
Hallo,
I have added opb_spi 1.00.d to my design. It is a microcontroller based on 
powerpc.

I have connected the ports: sck, miso, mosi, ss<0> as external ports.
The controller is a master. The external peripheral, a DAC, is the slave.

I have connected spisel to net_vcc and freeze to net_gnd.
I have also tried leaving them not connected.

From the output pins of the fpga I don't see the SPI Clock signal.

I have configured the peripheral as:
Fifo: True
clock Ratio: 128
spi_slave_only: 0
offchip_ss_bits: 0
ss_bits: 1
dev_block_id: 4
dev_mir_enable: 0
interrupt_present: 0
ip_reg_bar_offset: 0x00000060

Has someone had the same trouble?

Many Thanks
Marco 





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search