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Hi, I am a beginner in the vlsi industry.I am having a doubt.Whenever we are starting soem project work,how can we decide how much gates,logic will be required to implement the design?and which family should be used? Beacuse how can we come to know this information before actual starting the design phase?Article: 98126
Hallo, Simon Peacock schrieb: > There is also the issue that FPGA's configuration data is stored in external > FLASH where as CPLD's are programmed. > It is actually quite easy to reprogram a FPGA on the fly and field update > the external memory while the FPGA is still running. No special hardware or > algorithms are required. Downloading a CPLD is usually done from a PC via a > JTAG cable or via a External Chip Programmer This is wrong. At least if you accept other fpga vendors beside Xilinx *g*Article: 98127
OK.. I admit there are a few minor players who have flash based or fuse based FPGA's.. but then they aren't by definition field Programmable are they? They are in fact very large CPLD's as a FPGA is a Field Programmable Gate Array and Fuse devices aren't field programmable (or at least are only one-shot) FLASH devices could be considered field programmable... but some can't be used while a new program is getting uploaded. So that excludes them from what I would call Field Programmable. Although some people might disagree.. I believe that A&X do hold the lions share of the market so RAM based rocks for now... until nano-tube becomes the fad. Simon "Thomas Stanka" <usenet_10@stanka-web.de> wrote in message news:1141631210.694896.38720@u72g2000cwu.googlegroups.com... > Hallo, > > Simon Peacock schrieb: > > > There is also the issue that FPGA's configuration data is stored in external > > FLASH where as CPLD's are programmed. > > It is actually quite easy to reprogram a FPGA on the fly and field update > > the external memory while the FPGA is still running. No special hardware or > > algorithms are required. Downloading a CPLD is usually done from a PC via a > > JTAG cable or via a External Chip Programmer > > This is wrong. At least if you accept other fpga vendors beside Xilinx > *g* >Article: 98128
It really depends on just what you want to do with your gates. I use a P4 2.6G and am very happy with it. Screen is 1280x1024. I wouldn't consider less these days. There has been talk of Dual processors being the best bet but their best feature is the ability to do something else while the FPGA tools are busy. If you really want to do FPGA's then first ditch the laptop. You will need RAM and horses. 512M RAM minimum 1G better Simon "Hendra" <u1000393@email.sjsu.edu> wrote in message news:1141550646.096460.327320@i39g2000cwa.googlegroups.com... > I own a notebook 700 MHz PIII / 256 MB / 10.4" / 1024*768. I am > thinking of upgrading because ISE 6.3i runs very slooooowwwww with this > notebook. Not to mention that at 1024*768, nothing much that I can see > on the screen. I need higher resolution and faster CPU. > 1. What screen resolution is the ideal one for ISE? > 2. Which screen resolution that you usually use at work? > 3. What is the ideal CPU speed and RAM if I limited my self to an FPGA > less than 1.5 M gates with little constraint in the design. > > Hendra >Article: 98129
Sean Durkin wrote: > Ivan wrote: >> Hi, Hi Sean, >> >> your comments reveal that you are very annoyed about PR. > Yes... I did my diploma thesis on it, i.e. on dynamic partial > reconfiguration using the ICAP in Virtex-II Pro devices. The idea was to > use the embedded PowerPC or a Microblaze to reconfigure other parts of > the FPGA doing e.g. image processing. The next step would've been > reconfiguring components of the SoC On-the-Fly. Like you load/unload > Linux kernel modules, you were supposed to be able to load/unload > peripherals for the processor. > > The end result was more or less: Yes, it's possible, but there are so > many restrictions and so many problems with the tools that there really > isn't a single application that is worth the immense extra effort you > have to put in simply to make it work somehow. Instead, just get a > bigger FPGA, cram it all in and be done with it. Your diploma thesis looked for the same goal than my PhD. Thesis. I was working with MicroBlaze in Spartan-3 (there is not ICAP, but it is possible the self-reconfiguration too). I know another student working with OpenRISC is Virtex-II. PR works reasonably well in these two systems. I succeed in obtaining PR coprocessors. Regards, IvanArticle: 98130
kulkarku@math.net wrote: > Hi, > I am a beginner in the vlsi industry.I am having a doubt.Whenever we > are starting soem project work,how can we decide how much gates,logic > will be required to implement the design?and which family should be > used? > Beacuse how can we come to know this information before actual starting > the design phase? > Actually, you cannot, except in very trivial cases. You need to know the tools anyway, so get them, test them and from them get some estimate on how many macrocells you need. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 98131
Steve Lass wrote: > I am responsible for the partial reconfiguration software. Let me try > to answer all of the questions posted: Hi Steve, thanks for your answers. > > Q: How do I get this software? > A: Contact your local FAE. If you're at a university, contact the > university program. Our Xilinx Labs research department is supporting > the universities. Yes... I am working on it ;) Regards, IvanArticle: 98132
I'm trying to create a project in ISE webpack 8.1i. Whenever I try and add Picoblaze vhdl into the project it freezes no matter how i add the files. my processor cpu usage doesnt say its hard at work or anything. im trying to add the file kcpsm3.vhdArticle: 98133
Hi all, sorry for keeping silence. I tried Post-Synthesis simulation with ModelSim but I had an error: # ** Error: Timing Violation Error : RST on instance * must be asserted for 3 CLKIN clock cycles. # Time: 8100 ps Iteration: 1 Process: /tbx_top/i_top/i_ddr_sdr/dcm0/dcm_inst1/check_rst_width File: C:/Programs/Xilinx/vhdl/src/unisims/unisim_VITAL.vhd This problem is caused due to Xilinx libraries. In the testbench, the DCM Reset is initially defined as "x",then it changes to "1". This initial transition is evaluated as a valid transition, and starts the DCM Reset lenght check from this transition, therefore causing the ERROR. So Xilinx proposes to update the software libraries. I did it but it did not help. Does anyone have an idea how to fix it? Any case I do not think I have to spend too much effort in order to bring the simulation to work because it's just a simulation. Nobody could guarantee that even if simulation works it would work with the real board. So I have to concentrate on a real board. I asked AVNET about connecting an oscilloscope to the board but no answer till now. And I have not found anything related to their boards and osci connections in Internet. Does anyone have a working DDR SDRAM controller example? Or some other ideas related to my problem? I would really appreciate it. And one more question. I am using 125MHz FPGA clock and I am giving clocks with the same frequency (generated with DCM primitives ) to the DDR SDRAM. I think it's ok but maybe I am mistaken. Does someone have other suggestions? Best, AdaArticle: 98134
ok,that's right. but whenever we are making some project proposal,we don't know how complex will this design/code?then what r the steps to identify the proper CPLD/FPGA?Article: 98135
bjzhangwn schrieb: > I want to know the default pio mode when device reset and powup,and if > the udma mode is surported when device reset and power up!thanks! page 374 of the t13 spec/1410D revision 3b ... chapter 10.2.1 "Peripherals reporting support for PIO mode 3 or 4 shall power-up in PIO mode 0, 1 or 2." as the PIO timings are minimum I would assume worst case ... this is power up in PIO mode 0 I could not find any definition for UDMA you should set the UDMA mode after each power up bye, MichaelArticle: 98136
Hi, I have a custom ASIC and I would like to interface this with my XUP V2P (Xilinx VII Pro) board. I am new to using the Xilinx boards. Please suggest a simple way to generate a clock from the FPGA and few synchronised control signals with this clock. I have to feed the clock and the control signals to ASIC. Basically the FPGA is acting as a controller for the ASIC (The ASIC is on a simple PCB, The ASIC is implemented using 0.12 micron libraries and run at 1.2 V). Here is how my perceived test setup looks like. FPGA XUP V2P --> Clk and Control Signals for ASIC --> ASIC | --> Oscilloscope for tracking signals Please suggest a simpler method as I am just starting a project with the FPGA. I would be very thankful for any help.Article: 98137
Hello All, I want to use Xilinx v2p or v4 rocket IOs in one of my designs. right now I am using Xilinx webpack 8.1 and modelsim se/pe. can any body tell me that if I generate a rocket IO instance (without 8b10b and crc) as a simple serdes How do I simulate it...? Does the Rocket IO Instance has any output pins for PLL Locked signals...? I am trying to simulate a transmitter by a simple test bench as to provide reset, clock and 8-bit parallel data, but nothing is coming out on serial tx pin. Please guide me . Thanks in advance. Regards, KedarArticle: 98138
Hi, i think u should clkout pin for verification.Article: 98139
Hi ada, >This problem is caused due to Xilinx libraries. In the testbench, the DCM >Reset is initially defined as "x",then it changes to "1". This initial >transition is evaluated as a valid transition, and starts the DCM Reset >lenght check from this transition, therefore causing the ERROR. How do you generate the Reset, do you you generate it in the testbench ? Rgds Andr=E9Article: 98140
>Any case I do not think I have to spend too much effort in order to bring >the simulation to work because it's just a simulation. Nobody could >guarantee that even if simulation works it would work with the real board. >So I have to concentrate on a real board. Yes, you are right. But performing a timing simulation you can at least say that your FPGA generates the timings correctly. For that purpose I think it could be an advantage to use a simple test case, for writing data to DDR memory and reading it back (simplified data path) Once proved you can concentrate on functional simulation and static timing analysis. Rgds Andr=E9Article: 98141
Hi, I have my VHDL modules which access the processor bus. I have one more third party core wher in at also uses the processor bus , now i have no access to their source code. Now my doubt is how to go about integrating these two since the tristaing of the processor bus should happen at only one place. Any innovative soultion?? OR is it really possible or not. Regards, PravArticle: 98142
<sharp@cadence.com> escribió en el mensaje news:1141523014.743932.130460@e56g2000cwe.googlegroups.com... > > Or perhaps what you are missing is that each of these RAMs has a read > port and a write port, which can be used simultaneously with > independent addresses. This was one of the components that was > described as being available. So PortB can be reading address 17 of > RAM1 at the same time PortA is writing address 22 of RAM1. > After reading your post I went back to the OP, and it was _clearly_ stated the availability of such a component. Thank you for pointing it out.Article: 98143
Simon Peacock wrote: > > I own a notebook 700 MHz PIII / 256 MB / 10.4" / 1024*768. I am > > It really depends on just what you want to do with your gates. > > I use a P4 2.6G and am very happy with it. Screen is 1280x1024. I wouldn't > consider less these days. There has been talk of Dual processors being the > best bet but their best feature is the ability to do something else while > the FPGA tools are busy. > > If you really want to do FPGA's then first ditch the laptop. You will need > RAM and horses. 512M RAM minimum 1G better Howdy Simon, I'm not sure if you are talking about laptops in general, or just his laptop. His laptop is obviously too slow for medium to large designs, but more modern ones, with Pentium M processors, are faster than many P4's, including the 2.6 GHz unit in your machine. And that is despite the Pentium M being based on the Pentium III design! http://www.tomshardware.com/2005/05/25/dothan_over_netburst/page16.html Basicly, the MHz race is dieing: http://www.tomshardware.com/2005/11/21/the_mother_of_all_cpu_charts_2005/ Both vendors are transitioning to meaningless numbers and letters (Intel's Pentium D "900", AMD's FX series) and to multiple cores. I don't think the race is dieing in just processors, either. ObFPGA: Anyone notice how only the embedded stuff (DSP block and 405) in lowest speed grade of the V4 got noticeably faster over V2Pro? Have fun, MarcArticle: 98144
Hi. For the begining, the approach you described is fine (later you might want to read out the signals from your asic to the fpga, process them, etc.). From engineering point of view, just be careful with signal driving. I.e. use dedicated pins for clocks (check the xilinx manual), check the impidance of the connection path (in some cases you might want to place a pulling resistor, etc. etc.). Regards Alex > Hi, > I have a custom ASIC and I would like to interface this with my XUP V2P > (Xilinx > VII Pro) board. I am new to using the Xilinx boards. Please suggest a > simple > way to generate a clock from the FPGA and few synchronised control > signals > with > this clock. I have to feed the clock and the control signals to ASIC. > Basically > the FPGA is acting as a controller for the ASIC (The ASIC is on a simple > PCB, The ASIC is implemented using 0.12 micron libraries and run at 1.2 > V). > > Here is how my perceived test setup looks like. > > FPGA XUP V2P --> Clk and Control Signals for ASIC --> ASIC | --> > Oscilloscope for tracking signals > > Please suggest a simpler method as I am just starting a project with the > FPGA. > I would be very thankful for any help. > >Article: 98145
If you are making a project proposal then take your best guess based upon experience and bias the guess high. If you have not experience to draw from, well then you have a problem. If this isn't good enough and you require an exact answer then you will probably have to go ahead and implement the logic in the tools and see what size devices it requires. Unfortunately, I know of no magic to tell you how many gates you are going to require. Regarding CPLD / FPGA, in generall FPGAs are a lot larger than CPLDs and can have a lot higher density per dollar. CPLDs, however are usually flash based so that they don't require a bootup time / sequence and a configuration method. Lastly, CPLDs tend to be more of an AND/OR array strucutre while FPGAs utilize a ram lookup with a mux architecture. Consequently one may take more or less resources based upon the design.Article: 98146
Hi John, Thanks a lot for your suggestion. And I tried not to add any constraints on it. But it didn't work.and It seems there are enough SLICEMs. Because it show in report and FPGA editor graph that all the SLICELS are used up, and only 1% SLCEMs are used. The par error comes from there are not enough SLICELS to place register bit. I don't konw why the tools can't place them into SLICEMS. Is there any contraints in default? And It is strange Slices number from x0 to x 72 are all SLICELS, and from X74 to X102 are half SLCIEMs and half SLCIELS. It is not the same as Spartan datasheet said. What I used is x3s1500.Article: 98147
Hi, Spartan3 does have internal pullup and pulldown resistors on all its I/O. I'll work with LVCMOS33. I have to communicate with a DSP in a serial mode both during configuration (master serial) and while working after the FPGA has been programmed. I was supposed to bring the CCLK (clock during configuration) and the serial_clock signals from the FPGA on an AND port in order to use the same pin of the DSP for the clock in the 2 situations. Could I set low the HSWAP_EN during configuration to pullup the serial_clock (which is on a user pin, global clock) and then, after its completition, bring the CCLK at a high logic level with the CclkPin Bitstream option? Do these setting use internal pullups? When can I use a internal pullup and when should I place an external one? Thanks, MarcoArticle: 98148
Maybe a carry chain that's too long ? (does the tools cut it automatically ?)Article: 98149
Marco wrote: > Hi, Spartan3 does have internal pullup and pulldown resistors on all > its I/O. I'll work with LVCMOS33. I have to communicate with a DSP in a > serial mode both during configuration (master serial) and while working > after the FPGA has been programmed. I was supposed to bring the CCLK > (clock during configuration) and the serial_clock signals from the FPGA > on an AND port in order to use the same pin of the DSP for the clock in > the 2 situations. Could I set low the HSWAP_EN during configuration to > pullup the serial_clock (which is on a user pin, global clock) and > then, after its completition, bring the CCLK at a high logic level with > the CclkPin Bitstream option? Do these setting use internal pullups? > When can I use a internal pullup and when should I place an external > one? > Thanks, Marco Generally it's better to use an external pullup resistor when you need to be sure of the logic value external to the FPGA. The internal pullups are normally just strong enough to guarantee the state of a non- connected pin. That being said I've noticed that the pullups at least on Virtex 2 can be quite strong, enough to pull up an external net to other CMOS loads. The HSWAP_EN pin only controls the pullup on CCLK until the configuration starts. The bitstream option normally takes over as soon as the value is read in near the beginning of the bitstream. I'm assuming that by this point something should be driving the CCLK pin if you use serial configuration, either the FPGA itself in master serial mode or some external source in slave serial mode, so the pullup option for CCLK in this case really takes effect when configuration is complete. If you use the master configuration mode you need to look into the final state of the CCLK pin at the end of configuration. The diagrams in the datasheet don't show this, but if the CCLK in fact ends in a low state, you will have a very slow rising clock edge when the CCLK pin reverts to tristate with a weak pullup.
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