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Hi David, I have a similar project - Camera on Virtex4FX12. I have Memec's FX12 MiniModule and TEMAC reference design uses hard LL_TEMAC core (which has a large FIFO - about 50% of FX12's BRAMs) and an open source lwIP stack version 1.01.a (some kind of workaround to work with TEMAC). I did not test the performance of this system, but I believe It could be equal to your design. I don't like my design because it uses too much BRAM and it cannot make it work in EDK 8.1 (for now). I also wanted to add ChipScope core to it, but there was simply not enough BRAM :( GRRRR. I took a look at the xapp807 (UC-II) but I don't know how to add other peripherals (which I have a lot) and FIFO's are only 1 BRAM block deep - resulting in poor performance (reported 50 Mbps). Hard TEMAC with sizable FIFO's would be very handy solution with open source lwIP stack. How do you stream the data to the processor? I am trying to make OPB master peripheral to write data to OPB DDR and then processor can access this data (maybe not suitable for real time streaming but necessary to get all of the 100-200 frames needed). I would like to get any solution for this problem, so HELP WANTED! GuruArticle: 100326
Hi everyone, I am trying to write obout 66MB/s of data to DDR memory (which is connected to OPB bus) conneted to Virtex4FX12. For that purpose I tried to build an OPB peripheral with master support using EDK's Import/Create peripheral wizard. The slave registers work OK, but master support doesn't work as it should. If DMA is enabled in IPIF then local master access doesn't work at all. With no DMA local master works but there is no way to control source and destination address increment (IP2BUS or IP2IP). The most problematic is that IPIF address increment doesn't work properly (sequence is reg0,reg0,reg1,reg2...). That "first increment" problem appears also at DMA transfer grater than 8 words. I am getting really desperate on this issue :( Does anyone has any solution for my troubles - maybe different approach or maybe a reference design to learn from. Cheers, GuruArticle: 100327
Anonymous wrote: > "Andy Peters" <Bassman59a@yahoo.com> wrote in message > news:1144276764.165125.290340@z34g2000cwc.googlegroups.com... > > Anonymous wrote: > > > Dumb question: Since USB is just a two wire serial interface and all the > USB > > > solutions I've seen are simple, though speedy, microcontrollers why > can't > > > the USB be inside the fpga? Seems like you can instantiate a small micro > > > running at 50 mhz or so with code in a couple block rams to do what the > fx2, > > > for example, does. Apparently, doesn't exist so there must be some > reason? > > > > It's a little more complex than simply two wires between two devices. > > > > USB signalling is half-duplex differential, and high-speed signalling > > is different than full-speed and low-speed. Also, there are some > > instances where single-ended signalling is used and the driver must be > > capable of doing this and the receiver has to be able to detect these > > states. > > > > -a > > > > I agree the software is complicated. (Way too complicated in my opinion.) Where did I say anything about SOFTWARE? I pointed out that the hardware interface is more than simply two wires. > But all the solutions out there seem to be built around a little 8-bit > micro. You don't think it's silly to have a 10 million gate FPGA sitting > next to an 8051? > > There must be a real reason for it. Maybe I'll try it when I get some time. You could get a PHY and put that next to your FPGA. -aArticle: 100328
Hello all, I am currently working on a xilinx Spartan 3 XC3s400 FPGA. (Using ISE Project navigator to design the FPGA). My question is the following: In schematic edition, to make a net take on the property of the GSR net, do you simply just rename it to "GSR"? or does it have to be tapped from a module ? or is the GSR net always tapped from an IO pad? I tried it (it==remaming it to "GSR") and the schematic editor just sees it as any other net. The datasheet refers to a global GSR network, but does explain how do the knitty-gritty...I.E if the net has to be named "glbl.gsr" or some other reserved name. Please advise -Roger BourneArticle: 100329
>>...... is there a Quartus option "Connect Unassigned Top-level Signals to Random Device Pins Without Asking Me"
>This is not an option but the default. Top level pins are device pins
>and when they are unassigned Altera tools select the "best" location
>for them. After all they have to go to some where. Sometimes this is
>useful at the very start of the project where you really don't care
>where the pins get assigned. You should just assign them to some safe
>locations if you don't want this to happen.
Why do they "have to go somewhere"? Surely they could go nowhere?
If Quartus does assign an output itself, I'd at least like a warning.
After all, it's easy to forget to assign at least one signal. It
could be in conflict with another device. In my case, it looks like
it was in conflict enough to cause a malfunction. Instead, there's
just an "info" message (lost among all the other green messages).
If Quartus does assign a pin, where do I see which pin it allocated? I
don't see anything in the pin assignments. What's the use of
allocating a pin ("best" or otherwise) if it doesn't tell me where it
is?
Mike
Article: 100330Anonymous wrote: > I agree the software is complicated. (Way too complicated in my opinion.) > But all the solutions out there seem to be built around a little 8-bit > micro. You don't think it's silly to have a 10 million gate FPGA sitting > next to an 8051? That depends on your mindset. If you really want a single chip "at all costs", then yes, pull the USB into the FPGA - the FPGA vendors will love you :) but if you want a reliable, cheap, easy to fault-find system then a little distributed intelligence can be a very good thing. Keep the expensive FPGA fabric for what it best at..... > > There must be a real reason for it. Maybe I'll try it when I get some time. Try this : The USB uC's out there can directly, and correctly, drive the USB cable, and are proven to do so. -jgArticle: 100331
Mike Treseler wrote: > mk wrote: > >> Do you have a reference for this ? > > > My only reference is a vivid memory > of a sore experience. But since I made > a big deal out of it, I fired up Quartus 5.1 to check. > The default for unused pins is now > /As output driving GND/ > which could still be a rude surprise > when powering up an new prototype. yes, and you _think_ you are being carefull by bringing up a design a little at a time.... :( Why would they do this, do they not have a low-cost safe pin default ? -jgArticle: 100332
Hi, I would say yes since if your xilinx demonstration board was provided with some linux flavor (ML300 reference design is provided with a working Monta Vista Linux demo for example, which has the required drivers for the on chip peripherals). The main issue I can see is perhaps a compatibility problem between your ethernet MAC and the ethernet PHY used on the board for example. Regards, Manu prakash.na@gmail.com a écrit : > Hi > Iam planning to port leon (open-source processor) in xilinx virtex-II > chip, bypassing power PC. Still May it be possible to use the resources > like ethernet transciever, audio codec available in the board. Can I > use my own tool chain with rtos like uclinux, sparc-linux-gcc etc and > run the code in leon ported in xilinx chip, development board. > Prakash >Article: 100333
Austin Lesea wrote: > All, > > When we recently did a USB interface to the FPGA, we looked at the USB > interface parts that were out there, their features, and their costs. > > We decided on a complete module (connector, and all) just because it was > - 1. incredibly cheap, 2. useful (it has its own 8 bit uP to take > care of everything we would ever need), and 3. it is done, and working > (one less thing to do). > > Tightly integrating the USB into the FPGA has about 0 benefit. It is > not like having an ethernet port, or a 6.25 Gbs serial link, or PCI > express, or any of a number of high bandwidth interfaces where tight > coupling just makes sense. True, tho I'd say that Ethernet is moving into the same category as you have placed USB. Not GBit ethernet, but certainly vanilla 10/100, where there are smarter/cheaper PHY included options to choose from. -jgArticle: 100334
Hi Roger, Roger Bourne wrote: > Hello all, > > I am currently working on a xilinx Spartan 3 XC3s400 FPGA. (Using ISE > Project navigator to design the FPGA). My question is the following: > > In schematic edition, to make a net take on the property of the GSR > net, do you simply just rename it to "GSR"? or does it have to be > tapped from a module ? or is the GSR net always tapped from an IO pad? > I tried it (it==remaming it to "GSR") and the schematic editor just > sees it as any other net. > The datasheet refers to a global GSR network, but does explain how do > the knitty-gritty...I.E if the net has to be named "glbl.gsr" or some > other reserved name. > > Please advise > -Roger Bourne The GSR signal connects to a design element called a STARTUP_SPARTAN3. There is a description on PDF page 1,097 in the Libraries Guide. http://toolbox.xilinx.com/docsan/xilinx8/books/docs/lib/lib.pdf For the schematic editor, just look for the symbol called STARTUP_SPARTAN3. For HDLs, you would need to instantiate the STARTUP_SPARTAN3 primitive and then connect to it. Sorry for the confusion. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 100335
David wrote: > Hi > > I'm evaluating one Gigabit Ethernet design who use the hard Temac embedded in the Virtex-4 FX (ML403 evaluation board) for fast image transmision. > > The GSRD reference design (xapp546) is my best option, but have a 79% of occupied slices and I need more space for more components and the Treck TCP/IP used is a evaluation versión. It exist the option of the TEMAC UltraController-II but it seem that the PowerPC processor of the Virtex-4 can't be used for others issues and I don't know if the uIP TCP/IP stack used in this design supports Jumbo frames like Treck stack. This jumbo frames are needed for maximum performance at gigabit ethernet. > > Somebody have a easy solution to this problem? Another design? > > Thank you very much. I'm personnaly working an a project where we need to send a >300 Mbps dataflow to the FPGA and also retrieve some data. The solution I'm using right now is a PC connected point to point to the virtex4 using a 1000Base-T cat6e cable. The communication is then done at 1Gbps full duplex (other modes are not supported). The application on the PC just sends the data as fast as possible using raw ethernet frames (not even udp, just the mac header and then directly the payload, with just a seq number so that I can at least spot missing data). On the FPGA side, I use the hardemac alone with just some custom logic (very simple), to push the incoming data into à 16 kb FIFO (8 BRAMs). To prevent the FIFO ever being full (and thus a need to handle quite frequent retramsimission & co), as soon as the FIFO hits the 3/4, the logic transmits PAUSE frame continuously with a maximum pause time. As soon as the FIFO is not half full anymore, it transmits 1 PAUSE frame with a zero pause time to allow the PC to resume the xfer. Since this flow control is done in "hardware", that work quite nice and my FIFO never overflows. Of course that is not "real" tcp-ip and I can't establish connection and co ... just send a datastream. It all depends of what you need ... SylvainArticle: 100336
John_H wrote: > Brian Davis wrote: > > - the strangely low SSO limit (4) for the current mode drivers has > > reappeared for some of the S3E family, after improving in the > > latest S3 family SSO tables > > I noticed the SSO numbers but they don't affect me this round. The > specs are "per power/ground pair" which is ample on the BGA packages (7 > effective pairs per bank?) but still allows 8 SSOs on the wireframe > parts (2 pairs ber bank). I interpreted that as LVDS pairs, so 16 > signal lines per bank. > > Oops. > > I just remembered - there are only 4 banks on the Spartan3E. Yikes! > The pairs per bank are 1.4x-2x the Spartan3 values so it looks like they > may be legit. > > I sure hope those SSOs get changed!!! Which package did you plan to use and how many LVDS output pairs are required? The different SSO numbers on the quad-flat packages are purposely lower due to their merely average signal integrity. The BGA packages have superior signal integrity. Here's how you would calculate the recommended limit using the data sheet values. http://www.xilinx.com/bvdocs/publications/ds312.pdf Let's assume that you're using the TQ144 package, which has the equivalent of 2 VCC/GND pairs per bank (Table 92, page 133). Then, go to the LVDS_25 section in Table 93 (on page 134), indicating that you can have 4 LVDS _output pairs_ (emphasis included) per power ground pair. Multiply the values together to arrive at 8 LVDS _output pairs_ on a bank in the TQ144 package. Again, the SSOs are a recommendation, but let's keep it to 8 pairs, which equations to 16 I/O pins. There are only ~23 I/O on a package edge in the TQ144. The Input-only pins are not available as outputs. Also, SSOs are only for outputs. You can have as many LVDS inputs that will fit in an I/O bank. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 100337
Hi, did you try to make it run at a lower speed ? I encoutered the same kind of problem in a design and the problem was due to a timing issue within the IPIF which was not "clearly" reported by EDK during H/W generation. This was with version 7.1 of EDK, I don't k,ow if it is still the case in version 8.1. BTW, why don't you use the memory controler IP provided by xilinx EDK ? I use the PLB one and it works correctly on a Virtex2pro at this speed. Regards, Manu Guru a écrit : > Hi everyone, > > I am trying to write obout 66MB/s of data to DDR memory (which is > connected to OPB bus) conneted to Virtex4FX12. For that purpose I tried > to build an OPB peripheral with master support using EDK's > Import/Create peripheral wizard. The slave registers work OK, but > master support doesn't work as it should. If DMA is enabled in IPIF > then local master access doesn't work at all. With no DMA local master > works but there is no way to control source and destination address > increment (IP2BUS or IP2IP). The most problematic is that IPIF address > increment doesn't work properly (sequence is reg0,reg0,reg1,reg2...). > That "first increment" problem appears also at DMA transfer grater than > 8 words. I am getting really desperate on this issue :( > > Does anyone has any solution for my troubles - maybe different approach > or maybe a reference design to learn from. > > Cheers, Guru >Article: 100338
>Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote: > Hi Roger, > > Roger Bourne wrote: > > Hello all, > > > > I am currently working on a xilinx Spartan 3 XC3s400 FPGA. (Using ISE > > Project navigator to design the FPGA). My question is the following: > > > > In schematic edition, to make a net take on the property of the GSR > > net, do you simply just rename it to "GSR"? or does it have to be > > tapped from a module ? or is the GSR net always tapped from an IO pad? > > I tried it (it==remaming it to "GSR") and the schematic editor just > > sees it as any other net. > > The datasheet refers to a global GSR network, but does explain how do > > the knitty-gritty...I.E if the net has to be named "glbl.gsr" or some > > other reserved name. > > > > Please advise > > -Roger Bourne > > The GSR signal connects to a design element called a STARTUP_SPARTAN3. > There is a description on PDF page 1,097 in the Libraries Guide. > http://toolbox.xilinx.com/docsan/xilinx8/books/docs/lib/lib.pdf > > For the schematic editor, just look for the symbol called > STARTUP_SPARTAN3. > > For HDLs, you would need to instantiate the STARTUP_SPARTAN3 primitive > and then connect to it. > > Sorry for the confusion. > > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/-3E FPGAs > http://www.xilinx.com/spartan3e > --------------------------------- > The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs. Thank you Steve. I had tried that before but I was confused as the STARTUP_SPARTAN3 module had both GSRin and GSRout pins. I had assumed that the module was only for simulation purposes. ( At least I think it was the STARTUP_SPARTAN3 module. There were only 2 modules that had began with the wotd "startup", and I had tried them both. They were identical.) .... So just to be clear, if I were to tap the GSR signal from the GSRout pin of the STARTUP_SPARTAN3 module AND leave the GSRin pin floating, will the FPGA will generate a GSR signal ? P.S. The symbol of the STARTUP_SPARTAN3 module drawn in the datasheet does not resemble the one obtained from the symbol library. The one in the datasheet has 3 pins as opposed to the one from the symbol library has 5 pins. Please advise -RogerArticle: 100339
On 2006-04-06, aiiadict@gmail.com <aiiadict@gmail.com> wrote: > anyone played with connecting GB camera to > an FPGA? There are lots of sites out there with information about it. I even bought a couple off of ebay a long time ago but I never got around to hooking them up. As I recall it's a simple protocol of starting a capture and then clocking out the data. People were doing it with PICs to serial... -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 100340
Look in the compilation reports under:
compilation report=>Fitter=> Pin-out File
You'll find an ascii listing of the assigned pins there, including a
column with Y's and N's indicating whether the pins were assigned by
you or automatically by the tool. You can also use the pin planner to
see a graphic representation of where the pins are as you assign them.
> If Quartus does assign a pin, where do I see which pin it allocated? I
> don't see anything in the pin assignments. What's the use of
> allocating a pin ("best" or otherwise) if it doesn't tell me where it
> is?
>
> Mike
Article: 100341On 2006-04-07, Ben Jackson <ben@ben.com> wrote: > On 2006-04-06, aiiadict@gmail.com <aiiadict@gmail.com> wrote: >> anyone played with connecting GB camera to >> an FPGA? > > There are lots of sites out there with information about it. Now that I'm at home with my bookmarks: http://pages.zoom.co.uk/andyc/camera.htm http://geocities.com/vjkemp/gbcam.htm http://www.seattlerobotics.org/encoder/200205/gbcam.html None FPGA based, but at least you can learn the pinout/protocol. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 100342
Ira Thorpe wrote: > Hello, > I'm working on an FPGA implementation of a digital reciever. I > decided to use Xilinx's Systen Generator for MATLAB Simulink since I > have little experience programming FPGAs and just want to get something > working. In my design, I used the Xilinx FIR block, which implements a > distributed arithmetic filter, for a couple of low-pass filters with 16 > to 64 taps. The design simulates well but I seem to be utilizing a ton > of FPGA resources and want to trim the design down a bit. What is the > most efficient implementation of a FIR for this application? The part > is an XC2VP50 running with a 100MHz clock rate. I'd like to keep the > sample rate at 100MHz as well. One thing I noticed is that the input > data type is 32.30 but the output data type is 50.47, which I then cast > back down as a 32.30. Obviously this seems like a waste of resources > but I don't see anywhere to specify the interal precision for the > accumulators/multipliers. Thanks for your time, > -Ira Thorpe > UF Physics > If you have 100 Mhz clock rate and 100 Mhz sample rate, then won't every FIR tap will require its own hardware multiplier and adder, plus lots of pipelining? Sounds like a ton of resources to me. What numbers are you seeing? If you can clock at X * sample rate then theoretically at least, you would only need 1/X that many multipliers. Ray Andraka's web site has stuff you may be interested in: http://www.andraka.com/papers.htm -JeffArticle: 100343
Environment in which system works: Microblaze softcore processor on spartan 3 fpga board compact flash, acting as a mass storage. How to access the compact flash in embedded applications write to and read from the compact flash? how to access the FAT table? to which sector i need to write, which address? which mode of addressing is easy way out CHS or LBA?? I got no clue how to access, it would be great help if i could understand in and out of doing tht becoz i need to write a code in C Thanks in advanceArticle: 100344
How do i know how many cylinders, drives and sectors a particularr compact flash has?????? i have a 256mb sandisk compact flashArticle: 100345
Hello, sachink321@gmail.com wrote: > Microblaze softcore processor on spartan 3 fpga board > compact flash, acting as a mass storage. > > How to access the compact flash in embedded applications > write to and read from the compact flash? how to access the FAT table? > to which sector i need to write, which address? There is sample code in the Xilinx ML40x reference designs, under software applications. In particular, there is an example program for MicroBlaze that shows how to read and write files from the DOS partition on the compact flash card. I don't think you have to worry about partitions and all that, it's handled by some Xilinx FAT filesystem code. Regards, JohnArticle: 100346
"David" <david.quinones@imagsa.com> wrote in message news:ee99d36.-1@webx.sUN8CHnE... > Hi > > I'm evaluating one Gigabit Ethernet design who use the hard Temac embedded > in the Virtex-4 FX (ML403 evaluation board) for fast image transmision. > > The GSRD reference design (xapp546) is my best option, but have a 79% of > occupied slices and I need more space for more components and the Treck > TCP/IP used is a evaluation versión. It exist the option of the TEMAC > UltraController-II but it seem that the PowerPC processor of the Virtex-4 > can't be used for others issues and I don't know if the uIP TCP/IP stack > used in this design supports Jumbo frames like Treck stack. This jumbo > frames are needed for maximum performance at gigabit ethernet. > > Somebody have a easy solution to this problem? Another design? > > Thank you very much. I have a similar trouble. Xilinx should provide a plb_temac with lwip support into next release of edk service pack 2. Memec webserver reference desing is not 100% compatble with edk 8.1i. I have contacted reference design center and they have released a fully compatible version. Now you can download a new version of the design from avnet reference design center. Then you can make some changes into lwip to make it compatible with edk 8.1i. I already made it. It is quite simple. You should change directory structure and .mld file. Use the netlist of ll_temac. It works well. Don't re-synthetize, into my system doesn't work. I have also tried to lower the number of bram, but I wasn't able. It seems that Memec has released the core without some files needed to open fifos into core generator. If you would try, please check the gemac_common. The core is made by ll_temac and gemac_common. Marco ToschiArticle: 100347
Altera would like to track customers using Stratix II GX to ensure we provide the latest updates on documentation. Altera is also making significant enhancements to the Stratix II GX functionality with each Quartus II release - therefore knowing which customers are designing with this family ensures we can highlight these important updates. This can either be done by requesting a license file through the FAE (which can take a day or 2) or by enabling TalkBack (which is immediate). Details on TalkBack (i.e. it is off by default in subscription products, it does not forward designs, and designers can view the exact XML information at any time) are provided at http://www.altera.com/support/kdb/talkbackfaq.html. Dave Greenfield Altera Mike Treseler wrote: > lecroy7200@chek.com wrote: > > I have the full license for Quartus and can't compile a simple project > > targeting the GX device until I enable the talkback feature. What > > gives? Suppose the PC is not on the internet, you can't use the GX > > parts? > > Try it and see. > Section 9 of the License Agreement says > that it stores the xml files on disk > in that case. It doesn't say it stops working. > > -- Mike TreselerArticle: 100348
fifo_8bit_32deep Sync_Fifo ( > .clk(clk), > .sinit(reset), > .din(d_in), > .wr_en(wr_en), > .rd_en(rd_en), > .dout(data_out) > ); You connect d_in to the input of the FIFO and at the same time you define it as OUTPUT of your whole module ? Rgds Andr=E9Article: 100349
Alain wrote: > Unfortunately, even OC-192 is excluded form Virtex- 4 (ug076.pdf : > "Payload compatible only"), so no hope for OTU-2 I think. > We have to wait Virtex-5 family ? > I have seen that note as well. Can someone explain what "Payload compatible only" means?
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