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>> I'm wondering why there are so few messages about LEON [1] >> in this group. LEON looks like a very solid design (used >> by the ESA) and it is available in a GPL version. >> Could be a vendor independent replacement of NIOS/MicroBlaze >> with a path to an ASIC. >> The configuration is done via a simple Tcl/Tk script and >> the Makefile contains several targets. Works out-of-the-box >> for available tragets. Adaption to a new FPGA board [2] took >> me a few (some) hours - not so bad. >> >> What's your experience? >> >> Martin >> > > 2 hours is correct, that what it usually takes to port LEON to new hardware. > than you are way smarter than me ;-) > and the best thing is the LEON system can run FULL MMU enabled linux > in spartan3 or any other low cost FPGA! Do you know the minimum amount of RAM one needs to run Linux or eCos? MartinArticle: 98576
I tried compiling an example code both with -g and without and then I run the "objdump -S" and I saw that the result looked almost the same for both resultant .elf files. It was actually the file without the -g option that had some more lines... how can it be so ? I expected the file with the -g option to be bigger and more specified, can someone please advise? maybe I need to use more switches for the objdump in order to see the debug symbols ? Thanks, Mordehay.Article: 98577
hi folks, can you recommend a book on FPGA design implementation, that touches the following issues: -floorplanning (methodologies, tools) -p&r -clocking tree synthesis -test thanks in advance. regards, dominikArticle: 98578
me_2003@walla.co.il wrote: > I tried compiling an example code both with -g and without and > then I run the "objdump -S" and I saw that the result looked almost the > > same for both resultant .elf files. It was actually the file without > the -g option that had some more lines... how can it be so ? I expected > > the file with the -g option to be bigger and more specified, can > someone please advise? maybe I need to use more switches for the > objdump in order to see the debug symbols ? > Thanks, Mordehay. > The -g option doesn't change the code. It adds symbol tables so that data addresses and instruction address points to the source and names within the source code. The .elf files becomes much larger due to this but the objdump -S should stay the same. This is from the gcc manual > -g > Produce debugging information in the operating system's native format (stabs, COFF, XCOFF, or DWARF 2). GDB can work with this debugging information. > On most systems that use stabs format, -g enables use of extra debugging information that only GDB can use; this extra information makes debugging work better in GDB but will probably make other debuggers crash or refuse to read the program. If you want to control for certain whether to generate the extra information, use -gstabs+, -gstabs, -gxcoff+, -gxcoff, or -gvms (see below). > > GCC allows you to use -g with -O. The shortcuts taken by optimized code may occasionally produce surprising results: some variables you declared may not exist at all; flow of control may briefly move where you did not expect it; some statements may not be executed because they compute constant results or their values were already at hand; some statements may execute in different places because they were moved out of loops. > > Nevertheless it proves possible to debug optimized output. This makes it reasonable to use the optimizer for programs that might have bugs. Göran BilskiArticle: 98579
Hi G=F6ran, When using the powerpc-eabi-size on the executable.elf - the size remains the same (with and without -g option) so can I assume that the size of my program will occupy in memory (BRAM used space) remains the same with and without the -g option ? and if so I can leave it even after the debug stage is done (final version) dont I ? Thanks, Mordehay.Article: 98580
In the 9th page of VirtexE user guide ds022.pdf it is said that the VirtexE LUTs can be used as 16x1 RAM. How can an LUT be used as RAM. I think the content of the LUT is written at the time of burning the FPGA. Is this an error or is there any way we can change the configuration of the LUT dynamically. regards Sumesh V SArticle: 98581
To fpga,
Do you have any relationship with GN,pheonix. If no sorry for the
trouble.
Article: 98582On 13 Mar 2006 06:18:28 -0800, "vssumesh" <vssumesh_asic@yahoo.com> wrote: >In the 9th page of VirtexE user guide ds022.pdf it is said that the >VirtexE LUTs can be used as 16x1 RAM. How can an LUT be used as RAM. I >think the content of the LUT is written at the time of burning the >FPGA. Is this an error or is there any way we can change the >configuration of the LUT dynamically. This is not an error. The four input LUT consists of 16 memory locations, the value of which is loaded from the configuration bitstream. It can be configured in a number of modes: - LUT. This is like a 16 entry ROM. - RAM. Like the LUT, but with the ability to write a bit to a location. - SRL. This turns the 16 memory locations into a 16 bit shift register. The mode of the LUT can't change without reconfiguring the FPGA. The contents of the LUT can be changed any time if in RAM or SRL modes. Regards, AllanArticle: 98583
me_2003@walla.co.il wrote: > Hi Göran, > When using the powerpc-eabi-size on the executable.elf - the size > remains the same (with and without -g option) so can I assume that the > size of my program will occupy in memory (BRAM used space) remains the > same with and without the -g option ? and if so I can leave it even > after the debug stage is done (final version) dont I ? > Thanks, Mordehay. > Hi Mordehay, Since the debug symbol tables isn't downloaded or initiated in the memory, your BRAM usage will be the same. The symbol table is only needed for the debugger to show the user what addresses correspond to in the source code. Göran BilskiArticle: 98584
Thanks G=F6ran ....=20 MordehayArticle: 98585
Made a little web page: http://panteltje.com/panteltje/fpga/index.html With some remarks how I installed webpack on grml Linux. It also holds a simple example script to configure a Digilent Digilab D2 with webpack-8.1i without GUI.Article: 98586
Is there some internal Xilinx conspiracy against source code management
like SVN (subversion) and CVS? Or is it that the Xilinx guys don't use
version control to understand the goals?
ISE 6.x used ".npl" files to contain the project information. These
were text-based making them at least somewhat SCM-friendly, but they
changed each and every time you saved the project even if nothing
changed. Some date code changed. Thus requiring an update...
ISE 7.x came along and, even when the rest of the world was switching to
XML because of all the problems with binary config files, Xilinx decided
to move to a binary format ".ise" from it's .npl files. Now, each SCM
checkin required the whole binary file to be checked in each time rather
than just diffs (like the ISE 6.x days).
ISE 8.x came along and the conspiracy became clearer. Xilinx held on to
its binary format but has apparently added a LOT more to the file. Now,
it's almost 1 MB!!! This means that my SCM repository grows by 1 MB
EACH TIME I do a checkin if I include the ISE file. That's ridiculous!
PLEASE Xilinx, be learn about CVS, SVN, and others, and how to design
file formats for SCM. Also, place all temporary files in a temp
directory and stop spamming my project directory. Oh, and one more
thing -- it would be nice to know which files from a CORE are necessary
to the project. Each CORE generates almost a dozen files and I'd rather
not add all of them to SCM.
Jake
Article: 98587Hi, I'm very new to fpga, just came interrested in these things. The only problem I think I will have is the soldering. How to solder fpga's on the boards? I'm a student so I don't have money for very expensive machines. I want to be able to solder the whole range of packages of Xilinx spartan 3e, will that be possible with not to expensive tools? Package types: Table 121: Xilinx Package Mechanical Drawings Package Web Link (URL) VQ100 / VQG100: http://www.xilinx.com/bvdocs/packages/vq100.pdf CP132 / CPG132: http://www.xilinx.com/bvdocs/packages/cp132.pdf TQ144 / TQG144: http://www.xilinx.com/bvdocs/packages/tq144.pdf PQ208 / PQG208: http://www.xilinx.com/bvdocs/packages/pq208.pdf FT256 / FTG256: http://www.xilinx.com/bvdocs/packages/ft256.pdf FG320 / FGG320: http://www.xilinx.com/bvdocs/packages/fg320.pdf FG400 / FGG400: http://www.xilinx.com/bvdocs/packages/fg400.pdf FG484 / FGG484: http://www.xilinx.com/bvdocs/packages/fg484.pdfArticle: 98588
Paul van der Linden wrote: > Hi, > I'm very new to fpga, just came interrested in these things. > The only problem I think I will have is the soldering. > How to solder fpga's on the boards? I'm a student so I don't have money > for very expensive machines. > I want to be able to solder the whole range of packages of Xilinx > spartan 3e, will that be possible with not to expensive tools? > > Package types: > Table 121: Xilinx Package Mechanical Drawings > Package Web Link (URL) > VQ100 / VQG100: http://www.xilinx.com/bvdocs/packages/vq100.pdf > CP132 / CPG132: http://www.xilinx.com/bvdocs/packages/cp132.pdf > TQ144 / TQG144: http://www.xilinx.com/bvdocs/packages/tq144.pdf > PQ208 / PQG208: http://www.xilinx.com/bvdocs/packages/pq208.pdf > FT256 / FTG256: http://www.xilinx.com/bvdocs/packages/ft256.pdf > FG320 / FGG320: http://www.xilinx.com/bvdocs/packages/fg320.pdf > FG400 / FGG400: http://www.xilinx.com/bvdocs/packages/fg400.pdf > FG484 / FGG484: http://www.xilinx.com/bvdocs/packages/fg484.pdf The QFP devices (VQ100, TQ144 and PQ208) are do-able with some practice with a standard soldering iron and some wick. Occe you get the corners soldered and all the pins aligned, you can solder the others easily. Dont worry about solder bridges, they are easy to pull off with the solder wick. The BGA parts will probably not be within your capabilities. I have baked my own chips on before, but be prepared to ruin a few chips. Your best best is to get a development board to experiment. If you need a standard alone module check out the Avnet Virtex 4 Mini module or the devices from Xess. -EliArticle: 98589
Jake Janovetz wrote: > Is there some internal Xilinx conspiracy against source code management > like SVN (subversion) and CVS? Or is it that the Xilinx guys don't use > version control to understand the goals? > > ISE 6.x used ".npl" files to contain the project information. These > were text-based making them at least somewhat SCM-friendly, but they > changed each and every time you saved the project even if nothing > changed. Some date code changed. Thus requiring an update... > > ISE 7.x came along and, even when the rest of the world was switching to > XML because of all the problems with binary config files, Xilinx decided > to move to a binary format ".ise" from it's .npl files. Now, each SCM > checkin required the whole binary file to be checked in each time rather > than just diffs (like the ISE 6.x days). > > ISE 8.x came along and the conspiracy became clearer. Xilinx held on to > its binary format but has apparently added a LOT more to the file. Now, > it's almost 1 MB!!! This means that my SCM repository grows by 1 MB > EACH TIME I do a checkin if I include the ISE file. That's ridiculous! > > > PLEASE Xilinx, be learn about CVS, SVN, and others, and how to design > file formats for SCM. Also, place all temporary files in a temp > directory and stop spamming my project directory. Oh, and one more > thing -- it would be nice to know which files from a CORE are necessary > to the project. Each CORE generates almost a dozen files and I'd rather > not add all of them to SCM. > > Jake I don't know if it's possible with the 8.x tools, but I detest IDE's so I figured out how to do it all with the command line tools. Thus, no npl files, no weirdo unexpected file changes, clean checkins, etc., etc., etc. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/Article: 98590
>The BGA parts will probably not be within your capabilities. I have >baked my own chips on before, but be prepared to ruin a few chips. May I ask wether you ruin a few chips "per run" or up until one get used to the process? What kind of oven are you using? MarkusArticle: 98591
hi im using digilab XCR development board which has Xilinx XCR3064 CPLD. I/O pins in this CPLD are said to be tristate. but when im trying to use them as tristate its not working as one? i mean i want one of the I/O pin to go high impedance but its not? can any one tell me how can i make I/O pin in CPLD high impedance?Article: 98592
Hi Paul, You might manage the flat pack stuff with a tiny soldering iron and a bit of luck, but the bgas are a different story. Even the 'professionals' mess up when soldering these. - aligning the BGA almost perfectly to the grid on the PCB is tricky - Soldering these needs an oven with a compatible heat-curve, which changes from lead-free to leaded components. Just last week I had two s2 200s that had to go to be x-rayed, turned out they weren't soldered at the right temperature... So I wonder what your motivation is for this? If you're starting out, try and get your hands on some starter kits, they're really good value, and you can learn loads from them. If you're a student then go nag the electronics department, they should be pleased you're taking an interest, and might have some stuff lying around, plus if you could get some university-modules under your belt it would look nice on your CV. Mind you, there's so much to be said for just doing things as you become interested. I have to be honest and say that one of the big things that these Xilinx and Altera chaps are missing out on is the hobbyist engineer-type. If only they had that in mind when they built some of these starter kits, they'd sell them by the shed-load. Ok, just my 2p. Ben "Paul van der Linden" <msn@paultjuh.org> wrote in message news:44159b38$0$2337$2e0edba0@news.tweakdsl.nl... > Hi, > I'm very new to fpga, just came interrested in these things. > The only problem I think I will have is the soldering. > How to solder fpga's on the boards? I'm a student so I don't have money > for very expensive machines. > I want to be able to solder the whole range of packages of Xilinx > spartan 3e, will that be possible with not to expensive tools? > > Package types: > Table 121: Xilinx Package Mechanical Drawings > Package Web Link (URL) > VQ100 / VQG100: http://www.xilinx.com/bvdocs/packages/vq100.pdf > CP132 / CPG132: http://www.xilinx.com/bvdocs/packages/cp132.pdf > TQ144 / TQG144: http://www.xilinx.com/bvdocs/packages/tq144.pdf > PQ208 / PQG208: http://www.xilinx.com/bvdocs/packages/pq208.pdf > FT256 / FTG256: http://www.xilinx.com/bvdocs/packages/ft256.pdf > FG320 / FGG320: http://www.xilinx.com/bvdocs/packages/fg320.pdf > FG400 / FGG400: http://www.xilinx.com/bvdocs/packages/fg400.pdf > FG484 / FGG484: http://www.xilinx.com/bvdocs/packages/fg484.pdfArticle: 98593
Post the code that drives the outputs... And what does the synthesiser say? B <sachink321@gmail.com> wrote in message news:1142270059.172147.157840@z34g2000cwc.googlegroups.com... > hi > im using digilab XCR development board which has Xilinx XCR3064 > CPLD. > I/O pins in this CPLD are said to be tristate. > but when im trying to use them as tristate > its not working as one? > i mean i want one of the I/O pin to go high impedance but its not? > can any one tell me how can i make I/O pin in CPLD high impedance? >Article: 98594
sachink321@gmail.com wrote: > hi > im using digilab XCR development board which has Xilinx XCR3064 > CPLD. > I/O pins in this CPLD are said to be tristate. > but when im trying to use them as tristate > its not working as one? > i mean i want one of the I/O pin to go high impedance but its not? > can any one tell me how can i make I/O pin in CPLD high impedance? Using VHDL: io_pin <= some_data when output_enable = '1' else 'Z'; If your output is a bus rather than a single pin: io_bus <= some_data_bus when output_enable = '1' else (others => 'Z'); 'Z' means that the pin(s) are set to high impedance. HTH -Dave PollumArticle: 98595
No. :)Article: 98596
thers no problem with synthesizer nor simulation results infact simulation results show the output in high impedance but when i check(using logic probe) that on hardware its not in high impedance code is simple 2 inputs ( switches) 1 output (I/O pin) dout <= din when cnt = '1' else 'Z'; Benjamin Todd wrote: > Post the code that drives the outputs... > And what does the synthesiser say? > B > > <sachink321@gmail.com> wrote in message > news:1142270059.172147.157840@z34g2000cwc.googlegroups.com... > > hi > > im using digilab XCR development board which has Xilinx XCR3064 > > CPLD. > > I/O pins in this CPLD are said to be tristate. > > but when im trying to use them as tristate > > its not working as one? > > i mean i want one of the I/O pin to go high impedance but its not? > > can any one tell me how can i make I/O pin in CPLD high impedance? > >Article: 98597
On Mon, 13 Mar 2006 09:09:33 -0800, Tim Wescott <tim@seemywebsite.com> wrote: >Jake Janovetz wrote: > >> Is there some internal Xilinx conspiracy against source code management >> like SVN (subversion) and CVS? Or is it that the Xilinx guys don't use >> version control to understand the goals? >> >> ISE 6.x used ".npl" files to contain the project information. These >> were text-based making them at least somewhat SCM-friendly, but they >> changed each and every time you saved the project even if nothing >> changed. Some date code changed. Thus requiring an update... >> >> ISE 7.x came along and, even when the rest of the world was switching to >> XML because of all the problems with binary config files, Xilinx decided >> to move to a binary format ".ise" from it's .npl files. Now, each SCM >> checkin required the whole binary file to be checked in each time rather >> than just diffs (like the ISE 6.x days). >> >> ISE 8.x came along and the conspiracy became clearer. Xilinx held on to >> its binary format but has apparently added a LOT more to the file. Now, >> it's almost 1 MB!!! This means that my SCM repository grows by 1 MB >> EACH TIME I do a checkin if I include the ISE file. That's ridiculous! >> >> >> PLEASE Xilinx, be learn about CVS, SVN, and others, and how to design >> file formats for SCM. Also, place all temporary files in a temp >> directory and stop spamming my project directory. Oh, and one more >> thing -- it would be nice to know which files from a CORE are necessary >> to the project. Each CORE generates almost a dozen files and I'd rather >> not add all of them to SCM. >> >> Jake > >I don't know if it's possible with the 8.x tools, but I detest IDE's so >I figured out how to do it all with the command line tools. Thus, no >npl files, no weirdo unexpected file changes, clean checkins, etc., >etc., etc. I agree: I use the command line tools, which leaves me free to use any source control system I want. A question for the many folks who use the IDE: what does it really buy you that the command tools don't? Bob Perlman Cambrian Design WorksArticle: 98598
We are doing our best to patch that hobbiest hole. We we get some more time there will be some more products coming for that market. John Adair Enterpoint Ltd. - Home of Raggedstone1. The low Cost Spartan-3 Development Board. http://www.enterpoint.co.uk "Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> wrote in message news:dv49cf$s2f$1@sunnews.cern.ch... > Hi Paul, > > You might manage the flat pack stuff with a tiny soldering iron and a bit > of luck, but the bgas are a different story. Even the 'professionals' > mess up when soldering these. > - aligning the BGA almost perfectly to the grid on the PCB is tricky > - Soldering these needs an oven with a compatible heat-curve, which > changes from lead-free to leaded components. > > Just last week I had two s2 200s that had to go to be x-rayed, turned out > they weren't soldered at the right temperature... > > So I wonder what your motivation is for this? If you're starting out, try > and get your hands on some starter kits, they're really good value, and > you can learn loads from them. > > If you're a student then go nag the electronics department, they should be > pleased you're taking an interest, and might have some stuff lying around, > plus if you could get some university-modules under your belt it would > look nice on your CV. > > Mind you, there's so much to be said for just doing things as you become > interested. > > I have to be honest and say that one of the big things that these Xilinx > and Altera chaps are missing out on is the hobbyist engineer-type. If > only they had that in mind when they built some of these starter kits, > they'd sell them by the shed-load. > > Ok, just my 2p. > Ben > > "Paul van der Linden" <msn@paultjuh.org> wrote in message > news:44159b38$0$2337$2e0edba0@news.tweakdsl.nl... >> Hi, >> I'm very new to fpga, just came interrested in these things. >> The only problem I think I will have is the soldering. >> How to solder fpga's on the boards? I'm a student so I don't have money >> for very expensive machines. >> I want to be able to solder the whole range of packages of Xilinx >> spartan 3e, will that be possible with not to expensive tools? >> >> Package types: >> Table 121: Xilinx Package Mechanical Drawings >> Package Web Link (URL) >> VQ100 / VQG100: http://www.xilinx.com/bvdocs/packages/vq100.pdf >> CP132 / CPG132: http://www.xilinx.com/bvdocs/packages/cp132.pdf >> TQ144 / TQG144: http://www.xilinx.com/bvdocs/packages/tq144.pdf >> PQ208 / PQG208: http://www.xilinx.com/bvdocs/packages/pq208.pdf >> FT256 / FTG256: http://www.xilinx.com/bvdocs/packages/ft256.pdf >> FG320 / FGG320: http://www.xilinx.com/bvdocs/packages/fg320.pdf >> FG400 / FGG400: http://www.xilinx.com/bvdocs/packages/fg400.pdf >> FG484 / FGG484: http://www.xilinx.com/bvdocs/packages/fg484.pdf > >Article: 98599
Thank you very much for the clever solution, John. But I think the 9 dual-port RAM configuration can only give me 3 rd/wr ports. Where the other read port comes from ? I think the configuration for the 9 dual-port RAM is like this: form ram0 to ram8. Port A write to RAM0,1,2 and read from 0,3,6; portB write to RAM3,4,5 and read from RAM1,4,7; PortC write to RAM6,7,8 and read from RAM2,5,8. Then all the ports of the dual port RAM has been used and we got 3 rd/wd portA,B,C. Where can I put the other read port? Did I miss something? Thanks a lot.
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