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On 23 Nov 2000 00:14:42 GMT, gah@ugcs.caltech.edu (glen herrmannsfeldt) wrote: >Someone else probably knows the details better, but as I understand >it the lumped capacitance model didn't work as of about 0.3 micron >technology. The problem is that the resistance of the lines is >much more significant than the source impedance of the driver. >(The metal gets thinner and narowwer, so the resistance increases >with the square of the scale factor. Capacitance decreases linearly.) This isn't my area, but I got this info a few years ago from someone involved in a Neocad rewrite: 1) Neocad's algorithm treated the routing path as a lumped RC element. This worked Ok for >= 0.5um, at 'slower' clock speeds. 2) To do better, you have to go to a distributed timing model, taking into account the non-linear behaviour of multiple switch transistors in the route, along with the distributed R&C of the individual routing segments. If you assume zero resistance, you can get down close to 0.3um. 3) If you take into account the metal resistance, you should be Ok at 0.3um. Of course, current technologies are much smaller than this, the Physics is less well understood, and you'd have to do something pretty clever in a timing estimator for a 0.1x um device. I don't think 'Dr.' Johnson's PCB rule-of-thumbs are going to be up to the job. In answer to the original question, I personally am pretty sure that Xilinx does know what it's doing. This doesn't mean that you can't put clocks on general routing resources - just that you have to hand-place everything relevant, and use the timing analyser, preferably from FPGA editor. EvanArticle: 27476
If I want to use the parallel eprom (XC18V00) to configure a single Virtex device in selectman mode using an external clock source, do I need to instantiate the VIRTEX_STARTUP block in my code? If so, can I use the cclk pin as an input to the PROM & FPGA and will the P&R tool be happy with this. Cheers David Gilchrist -- To reply replace NOSPAM with BAESYSTEMS __________________________________ David Gilchrist Development Engineer BAE SYSTEMSArticle: 27477
In article <Pine.GSO.4.02.10011221458100.4926-100000@rock>, Christian Werner <cwerner@informatik.hu-berlin.de> wrote: > Hi! > > I'm looking for Virtex prototyping boards with a PCI-interface. > > The PCI-interface shold be controlled by a seperate chip, so that the FPGA > does not need to provide the functionality for the PCI-Bus. > > Is there anybody who has some (good or bad) experiences with such a board > and can give me any hints which board I should buy? > > As I don't know much about PCI-programming I would appreciate a board > that is shipped with ready-to-use PCI-drivers for Linux and/or Windows and > some examples how to use them. > > Thanks in advance, > > Christian Werner > > The ADM-XRC from Alpha Data uses a PLX9080 for the PCI bus and supports V400 upto V2000E as the target. I think it has drivers for WINNT and Linux. The PLX usually gives 100MB/s + performance with DMA. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27478
Hi, This isn't quite on topic for this thread, but I've seen trce report skew on Virtex-e "low skew" bufg outputs almost as high as 0.5 ns. It's worst if the path crosses between two of the major clock distribution "backbones". I'm considering using placement constraints to make sure that this doesn't happen on critical paths, as in some designs, 0.5ns represents a significant fraction of the clock period being wasted. [speed files from Alliance 3.2i, SP5] Regards, Allan. -- Allan Herriman mailto:allan_herriman.hates.spam@agilent.com Agilent Technologies Voice: +61 3 9210 5527 Advanced Networks Division Fax: +61 3 9210 5550 347 Burwood Highway Forest Hill 3131 AustraliaArticle: 27479
Hy, i'am the kit FPGA from kanda systems ltd. I'am the book "get going with..." from kanda. I'm tested the sample from the book, and have big problems with any examples using more one Flip-Flop or similar. The sample AN3 using one counter generated with one macro, d'ont work... the counter count randomly... I'm read other book speaking of VHDL, and if use more than one FLIP-FLOP, the result is very strange... After somme hour of research, i'm d'ont find who is the error. The only error was the button "manual clock" send more glitch.. i'am replaced this by one external "clean" clock generator. I'm find other user of the kit, for looking if have the samme problems and for change idee. Thanks alain.argand@sig-ge.ch (sorry for my english...) Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27480
In article <ys2olmul81uc.fsf@pcep-jamie.cern.ch>, Jamie Lokier
<spamfilter.nov2000@tantalophile.demon.co.uk> writes
>Ron Proveniers writes:
>> I see al these nice job opportunities the US. Are there any possibilities
>> for remote work???.
>
>A clearing house that offers short term remote contracts would be
>great. Wouldn't mind doing a few extra FPGAs on the side :-)
>
>-- Jamie
I might have some time to put a *basic* web site together for that if
there was enough interest. Something that just involved e-mailing me
resumes and availability for instance...
If it became useful, I will probably have enough time in first 1/4 2001
to tart it up
If anyone is interested, e-mail me at
mailto:contract_web_site@p2cl.demon.co.uk
--
Steve Goodwin... e-mail steve.ng@p2cl.demon.co.uk
Article: 27481Well, I think I got my answers :) Just to answer a few points: 1) The receivers are somewhat close, but they do have different clock paths to them, and therefore could have this skew we're talking about 2) I am forced to use local routing for one of my nets, as I have 5 clocking domains in my Virtex-E 3) I used FR4 as an example, because I have no idea what the signal speed on an FPGA die would be, I doubled FR4 speed to pad the equation a bit. 4) I looked up the equation in Howard Johnson's book, and I believe it is correct (the equation I mean, not necessarily my numbers) To sum up (at least for me), I have no doubt that Xilinx knows what they're talking about. I just needed a snappy title for this message thread. I just wanted some better explaination of what was happening, which I didn't get from Xilinx, but I did get here. Thanks again, WallyArticle: 27482
walter haas wrote: > 2) I am forced to use local routing for one of my nets, as I have 5 clocking domains in my Virtex-E Something to perhaps avoid if you can. If one (or more) of your clocks is at a lower frequency (clkL), perhaps you can synchronize it to a higher rate clock (clkH), produce a one clkH long pulse once a clkL period, and use this as a clock enable for the clkL registers, which are clocked by clkH? -- Phil HaysArticle: 27483
Hi. Does anyone have any clue or ready design for making a dram, two-devide ide controller (cdrom and harddrive) and interface for a ISA-device (Cirrus Logic CS8900). The design is intended for use with an Intel Strongarm SA-1100 processor. The reason I don't want to directly connect the devices to the pcmcia port of the SA-1100 is that I won't be able to use DMA then. /Daniel NilssonArticle: 27484
In article <ee6ec96.15@WebX.sUN8CHnE>, "walter haas" <walter_haas@pmc-sierra.com> wrote: (snip) > > 2) I am forced to use local routing for one of my nets, as I have 5 clocking domains in my Virtex-E > (snip) Do you really have five unrelated clock sources? If one clock is derived from another clock (maybe from a divider), then you can use the fast clock for both domains, and use the divider output to control flip- flop CE in the slower domain. Also, if any clock does not connect to series-connected flip-flops in the same clock domain, then skew is not an issue. An example of this is an address latch enable, which is only used to parallel-load an address into a register. In this case you can safely use local routing resources. Sometimes all I need is a binary divider, but I don't want to waste a global clock. In this case I will use a ripple counter (Q connects to clock at the next stage). You treat the output of the ripple counter as an asynchronous signal if feeding it into other logic. Ripple counters make some engineers cringe, but this is reliable and you don't have to worry about hold-time violations in the counter. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27485
"walter haas" <walter_haas@pmc-sierra.com> writes: > Well, I think I got my answers :) > > Just to answer a few points: > > 1) The receivers are somewhat close, but they do have different clock paths to them, and therefore could have this skew we're talking about > > 2) I am forced to use local routing for one of my nets, as I have 5 clocking domains in my Virtex-E [snippety, snip, snip] Walter, I don't about the clocks you are using, but four of them shold route OK, right? Now, the fifth one. Have you tried using the "secondary clock resources"? It's two dozen of lines on the top and bottom. If one of the clocks are from an I/O on the top and/or bottom, and you are using to just a few receivers, you might get this to work. I played with it once, but I can't quite remember the result. Better than "general" routing. I think I had constraints on Tsetup an Thold from an external I/O. I was using 2.1i, and I don't think there was anyway to force the tool to use these resources. If you had dense routing, that wouldn't help. I think you could coerce the tool with just the right constraints. So, what are the clock speeds, and what is the max skew you want? Perhaps I can help you? Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 27486
eml@riverside-machines.com.NOSPAM wrote: > In answer to the original question, I personally am pretty sure that > Xilinx does know what it's doing. This doesn't mean that you can't put > clocks on general routing resources - just that you have to hand-place > everything relevant, and use the timing analyser, preferably from FPGA > editor. > > Evan I agree with both Greg's assertion that using local routing resources for clocks is generally a bad idea and also that Xilinx know what they're doing *but* o Virtex devices have only 4 global clock networks no matter what the device size which is pretty poor for large devices. Therefore you are frequently forced, as I'm about to be right now, into the position of using non-global resources. The first port of call must be the secondary lines but (i) what were the poor users of F1.5i s/w supposed to do since these resources were not accessible, (ii) In 2.1i there was the ludicrous ``MAXSKEW'' parameter, (iii) In 3.1i they *still* haven't done the obvious thing and added a primitive you can instantiate in your HDL code but now rely on another UCF/PCF parameter. Instead of making snotty remarks to the original poster maybe they could address this issue. Of course using the secondary clocks is even worse than this since, at least if the clock source is from a pin, you have to put it in the right place [top or bottom of the die I think] which is not AFAIK described anywhere. I'd say that the secondary resources are long overdue for an APPS note. o Xilinx may know what they're doing but they *don't* know what I want to do. They may have to insist on unrealistic worst case analysis to cover their legal asses but I don't. In reply to the orignal poster: There is of course a way of handling clocks on local resources and avoid hold time problems, at least for simple situations you can arrange that the clock arrives at the receiver before it arrives at the driver. This will work as long as there's no feedback. Even with feedback this can be made to work by breaking the loop at some point with a clock enable. O.k this will need handrouting but desperate situations need extreme solutions - and I assume things have got pretty bad if you have to put more than a trivial amount of logic onto locally routed clocks. Question for Xilinx: Is the timing analyser sufficiently subtle to detect this and not complain ?Article: 27487
"Steven Derrien" <sderrien@irisa.fr> wrote in message news:3A1BF9E0.3188B6A3@irisa.fr... > PCI performance are not great (at most 40Mb/sec on slave DMA) but as far > as i heard it is not much worse than for wildforce and co. For comparison's sake... with a PLX 9504 chip, we were getting ~26.5MBps for slave write access and ~5.5MBps for slave read access. It's just atrocious; PCI is not designed for high speed access other than via busmaster DMA. With busmaster DMA, we get ~115MBps, which I consider quite respectable. The motherboard we did these tests on had an Intel i810 chipset under Win2K, BTW; from talking with others I've heard the north bridge (which IC and what its programmed settings are) can significantly influence these rates. I think it's safe to say that if you think your board would have worked OK on an ISA bus, it's OK to skip busmaster DMA support, otherwise you really, really need it with PCI. Actually, the worst thing about not having busmaster DMA is that you're taking, e.g., 1 GHz CPU and running it at all of 33MHz or so -- the 26.5MBps quoted above was with 100% CPU utilization, whereas with busmaster DMA there's ~15% CPU utilization continuously setting up the transfers at 115MBps (all the scatther-gather lists -- NT seems to _almost never_ stick data in contiguous physical memory...). That's on a 500MHz Celeron. ---Joel KolstadArticle: 27488
"Akito" <..@no.com> wrote in message news:IL2T5.23509$n9.1638114@newsread2.prod.itd.earthlink.net... > Greetings, I've been wondering for some time now what the different > "speed grade" versions really mean. The different speed grades really do correspond to different internal delays inside the IC (e.g., 'flop setup, hold, LUT propagation delay, routing delays, etc.). These used to be listed in great detail in the data sheets, but for newer Xilinx families there's less in the data sheets (presumably, in part, due to the fact that there are even more timing parameters to worry about) and you're referred to the Trace (trce) tool to get actual timing numbers for your design. > I'll compile a design for a XC4005XL-3C and it may run as fast as 80MHz. > From some semi-ambiguous graphs on Xilinx's site, 3C is only supposed to do > about 40MHz... The 40MHz number is for "some average design," e.g., a 32 bit counter or something. You could probably get a single 'flop to toggle at 120MHz, for instance -- the FPGA's overall speed just depends on how much logic you have inbetween the 'flops. But, for the 4K series parts, lower speed grades are always, always faster parts for most any given design. You can play around in Trace and see just how much faster or slower _your design_ would get in the various speed grades. ---Joel KolstadArticle: 27489
"Frank Z.F Xie" <frank.xie@latticesemi.com> writes: > Hi, there > > Currently I'm doing a design with VirtexE, but have problem to achieve Tco > performance: > > AD is a bidi bus with oe control > AD <= D_OUT when OE = '1' else "ZZZZ"; > > here D_OUT is a registered internal signal, and also used somewhere else in > the design. > > When I run it in Foundation ISE 3.1i + SP5, the SW keeps implement the > tristate with internal tristate bus(BUFT), which will add more delay, and > the Tco is as long as 10ns. Is there anyway to disable the internal tristate > in the SW? How to? Are you saying that the tristate isn't done in your I/O buffer? In that case, the design wont do what you want. Then, I suggest to make the OE registered (can't tell if it is), then duplicate it so that the tool can put the FF directly in the I/O buffer. You are posting with a Lattice address? Are you setting us up to show how this can easily be done in a 2032VE? :-) Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 27490
"walter haas" <walter_haas@pmc-sierra.com> wrote in message news:ee6ec96.15@WebX.sUN8CHnE... > I just needed a snappy title for this message thread. > Wally, I like your style. If I was using local routing for clocks in what appears to be your situation _and_ the rate wasn't too high I'd be inclined to impliment using master-slave FF structures (as long as it was only for small blocks :) . Dull but effective. Do I get any points for not changing the subject to: "How could you be so STUPID!!!!!!!!" or "How dare you use 5 clocks!" Best regards, DaveArticle: 27491
Frank Z.F Xie a écrit dans le message <8viiam$5si$1@info.sta.net.cn>...
Hi Frank
>Hi, there
>
>Currently I'm doing a design with VirtexE, but have problem to achieve Tco
>performance:
>
>AD is a bidi bus with oe control
>AD <= D_OUT when OE = '1' else "ZZZZ";
>
>here D_OUT is a registered internal signal, and also used somewhere else in
>the design.
>
>When I run it in Foundation ISE 3.1i + SP5, the SW keeps implement the
>tristate with internal tristate bus(BUFT), which will add more delay, and
>the Tco is as long as 10ns. Is there anyway to disable the internal
tristate
>in the SW? How to?
>
There are several things that you should do.
First, you should try use both the OUTFF and the ENBFF.
Therefore, set the option map - pr b, and set the option use I/O reg = true
in FPGA Express.
But it's not enough, your description must be able to fit in these FFs.
You should duplicate your output enable signal to get one OE per output bit
and use an active low output enable :
(signal nOE : STD_LOGIC_VECTOR(D_OUT'left downto D_OUT'right); )
You should be sure that these signals are registered and used only for the
tri-stating your pads .
You should be sure D_OUT is registered and used only for output, duplicate
the signals if necessary.
You should be sure that you use the same clock for D_OUT and for nOE. ;-)))
Then you can write :
for i in D_OUT range loop
if nOE(i) = '0' then
AD(i) <= D_OUT(i);
else
AD(i) <= 'Z';
end if;
end loop;
and it should work.
--
J-P GOGLIO
GETRIS S.A.
13 Chemin des Prés
38240 Meylan
France
Tel : (+33) 4 76 18 52 10
E-mail : goglio@getris.com
Article: 27492"Frank Z.F Xie" wrote: > Hi, there > > Currently I'm doing a design with VirtexE, but have problem to achieve Tco > performance: > > AD is a bidi bus with oe control > AD <= D_OUT when OE = '1' else "ZZZZ"; > > here D_OUT is a registered internal signal, and also used somewhere else in > the design. > > When I run it in Foundation ISE 3.1i + SP5, the SW keeps implement the > tristate with internal tristate bus(BUFT), which will add more delay, and > the Tco is as long as 10ns. Is there anyway to disable the internal tristate > in the SW? How to? > > Thanks > > Frank To achieve the best performance here you need to make sure that the tri-state buffer and register are mapped into the IOB. To do this on your code sample above: o You might have a problem with your synthesis tool which should be implementing an OBUFE [=OBUFT primitive with an inverter on the control signal]. Try changing the output enable polarity to active low. o The register feeding the output cannot drive any other logic in the design. If you need this then you will have to have a duplicate register to feed the internal stuff. [Not quite true since if AD is only a tri-state output you *could* define the ``AD'' as bi-dir and use pin feedback but this is ugly, slow and unnecessary -Xilinx parts have plenty of registers].Article: 27493
Rick Filipkiewicz <rick@algor.co.uk> writes: > o The register feeding the output cannot drive any other logic in the design. If > you need this then you will have to have a duplicate register to feed the > internal stuff. > [Not quite true since if AD is only a tri-state output you *could* define the > ``AD'' as bi-dir and use pin feedback but this is ugly, slow and unnecessary > -Xilinx parts have plenty of registers]. If he's having a tri-state buss called AD, a good guess would be that he wants pin feedback sooner or later. :-) Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 27494
In article <3A075EA1.82E@designtools.co.nz>, jim.granville@designtools.co.nz wrote: > If you can work with a PTerm Fan-in of 80 look at the ATMEL > ATF1504AS family > > Some minor edits of the XPLA.pla file, and you can feed it into > an Atmel fitter - pinouts I think are the same. > We have ported XCR5032 -> ATF1502. > The ATF1504 has lower static Idd then XCR, but a higher mA/MHz slope. Interesting. I'll look into that, since it would avoid having to spend a long time redoing a 'finished' product. Thanks! > > Since I wasn't sure I was reading the datasheet correctly, > > I asked a very direct question about this to Xilinx. The > > only answer I got was "Don't worry about that. Give us > > your code and we'll make it fit." > > And did they ? I never gave it to them. I have issues about sending my IP out to be floating about. From the pointers I did get, I'm fairly sure they wouldn't have had any luck. On a different subject, anyone know why the power-down pins were removed from Spartan II? P Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27495
Jean-Paul GOGLIO wrote: > Frank Z.F Xie a écrit dans le message <8viiam$5si$1@info.sta.net.cn>... > > Hi Frank > There are several things that you should do. > > First, you should try use both the OUTFF and the ENBFF. > Therefore, set the option map - pr b, and set the option use I/O reg = true > in FPGA Express. > But it's not enough, your description must be able to fit in these FFs. > You should duplicate your output enable signal to get one OE per output bit > and use an active low output enable : > (signal nOE : STD_LOGIC_VECTOR(D_OUT'left downto D_OUT'right); ) > You should be sure that these signals are registered and used only for the > tri-stating your pads . This is not necessary - its perfectly o.k. to use a single combinatorial OE control from inside the CLB matrix. Its just slower, which won't matter if clock period is relaxed. The registered tri-state FF is really only required for very high clock rates or for situations where one driver is being turned off and another turned on in the same clock period and you are not worried by 1 or 2nsec of contention.Article: 27496
Theron Hicks wrote:
>
> Jurjen Boss wrote:
>
> > Hi,
> >
> > We want to implement a Xilinx Spartan-II FPGA, type XC2S50, in our
> > (excisting) application. I'm trying to estimate the current supply of this
> > device by using the datasheets ("Spartan-II 2.5V FPGA Family: DC and
> > Switching Charateristics"). From this datasheet I get the following
> > information:
> > - Iccintq = 50mA; (supply current internal part)
> > - Iccoq = 2mA; (supply current I/O-part)
> > - Iccpo=500mA; (ramp rate 2ms)
> >
> > Does this FPGA needs so much current at power-up? How can this ramp rate be
> > adjusted? I just can't imagine that this FPGA needs 500mA at power-up. I
> > thought these devices where low-power!?! Is there some information available
> > on this subject?
> >
> > Regards,
> >
> > Jurjen
>
> If you consider that the device is being programmed very rapidly the 500mA is
> quite reasonable. There are millions of CMOS gates being turned on and off at
> once so 500mA is quite reasonable. More to the point... They do indeed require
> a high current a programming. That is why Xilinx says so. You had better
> design for it or you will be sorry. Note that this is a transient state and
> thus the total energy (V*I* time product) required is quite small. After
> programming they are much like any other CMOS device. namely ... Fast clock
> speed means high power. Zero clock speed means very low power. Obviously all
> sections of the device do not clock at the same rate so you take a summation
> over the whole device and integrate over time.
Sorry if I sound like a doubting Thomas, but I don't buy this "millions
of gates being turned on and off at the same time" explanation. I
checked the data sheet for non-Xilinx parts and I do not see a similar
requirement. Heck, lots of chips have millions of gates and don't have
such a large current spike at power up. Xilinx is doing something
unusual in their internal construction so that these parts look like a
near short for a few milliseconds during power supply ramp up. They even
warn you not to use foldback current limiting in your supply or you may
latch into a low voltage power supply state.
Take a look at the Lucent OR3 or OR2 data sheets. They licenced the
Xilinx XC4000 technology, but when they implemented it, they did not end
up with these heavy start up currents.
I do agree that you need to plan for the start up currents or you will
be sorry. I also have not been able to find a way to delay the current
so that I am not hit with N x 0.5 A with the multiple chips I want to
put on my board. But then since I can't seem to buy any of the Spartan
II chips, I don't know if it will be a problem.
I am changing my power supply spec to provide the required current as if
it could be delivered continuously. I have been told that "the caps can
provide this short burst of current". But power supply ramp ups are
normally required to be monotonic. If the filter caps are sourcing
current to the load, the ramp up voltage will have a back track or
droop. This can be very bad for the rest of the logic on the board.
Especially at the critical threshold voltage that the Xilinx chips spike
their current draw.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design
Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX
URL http://www.arius.com
Article: 27497fred wrote: > > "walter haas" <walter_haas@pmc-sierra.com> wrote in message > news:ee6ec96.15@WebX.sUN8CHnE... > > I just needed a snappy title for this message thread. > > > Wally, I like your style. > > If I was using local routing for clocks in what appears to > be your situation _and_ the rate wasn't too high I'd be > inclined to impliment using master-slave FF structures (as > long as it was only for small blocks :) . Dull but > effective. A simple solution is to, as long as the frequency isn't too high and the duty cycle not too bad, simply have the flip-flops that are sequentially adjacent be clocked off opposite edges of the high-skew clock. A bit more expensive in terms of gates than above, but easier to do and verify - and in the large devices gates are generally fairly cheap. If one wishes to make flip-flops, then you can do something similar with transparent latches and a two-phase non-overlapping clock. Neither of these requires extremely precise timing analysis - and total faith in the tools. rkArticle: 27498
Hi Please, anybody can explain to me this warning ? and how can i repair !? i use FPGA Express to synthetise VHDL files. HDL-307 (6 Occurrences) Warning: Latch inferred in design 'MAX532' read with 'hdlin_check_no_latch'. Warning: Latch inferred in design 'FLUCTUATION' read with 'hdlin_check_no_latch'. Warning: Latch inferred in design 'COURANT' read with 'hdlin_check_no_latch'. Warning: Latch inferred in design 'CLK_GENERATION' read with 'hdlin_check_no_latch'. Warning: Latch inferred in design 'SUPERVISEUR' read with 'hdlin_check_no_latch'. Warning: Latch inferred in design 'IMPULSION' read with 'hdlin_check_no_latch'. Thank's a lot Philippe CHAGNYArticle: 27499
Philippe Chagny wrote: > > Hi > Please, anybody can explain to me this warning ? and how can i > repair !? > > i use FPGA Express to synthetise VHDL files. > > HDL-307 (6 Occurrences) > Warning: Latch inferred in design 'MAX532' read with > 'hdlin_check_no_latch'. > Warning: Latch inferred in design 'FLUCTUATION' read with > 'hdlin_check_no_latch'. > Warning: Latch inferred in design 'COURANT' read with > 'hdlin_check_no_latch'. > Warning: Latch inferred in design 'CLK_GENERATION' read with > 'hdlin_check_no_latch'. > Warning: Latch inferred in design 'SUPERVISEUR' read with > 'hdlin_check_no_latch'. > Warning: Latch inferred in design 'IMPULSION' read with > 'hdlin_check_no_latch'. Hi This means that you have conditionnal signals that are not assigned a value for every possible case (such as an if without else, or a case that doesn't cover all the possible values) -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 00 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/
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