Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 59075

Article: 59075
Subject: Re: Gates Counting?
From: Tom Kirsch <tkirsch@lucent.com>
Date: Thu, 07 Aug 2003 16:58:04 -0400
Links: << >>  << T >>  << A >>

Just a quick rule of thumb?  About a 10:1 ratio of FPGAs to ASIC.

To get a better estimate, size the FPGA(s) based on how many flip-
flops, RAM, and I/O you need; forget about counting gates, that
gets ridiculous.


Jay wrote:

> Hi all,
>
> I'm doing prototyping for ASICs. Before I start my work, I have to estimate
> the gates the FPGA or CPLD would use.
> I know it's hard to get a precise result. I just want some common answer,
> 1:3 between ASIC and FPGA/CPLD gate count?(not consider the memory, just
> logic)
> Please tell me your experience.
>
> Thanks,
> Jay


Article: 59076
Subject: Re: Size does matter
From: Jay <se10110@yahoo.com>
Date: Thu, 7 Aug 2003 16:00:04 -0500
Links: << >>  << T >>  << A >>
Rob,

In article <3F2E0028.A07801D3@ob-wan.com>, judd@ob-wan.com says...
> Add to that the need for an expensive IAR compiler for the AVR core and
> it's pretty average. It's difficult to do a meaningful feature
> comparison though, owing to the different architectures. I do know that
> the EP1C6 and APA150 are very similar in price (when the config chip is
> added into the equation). May check out the Atmel too, just to be sure
> I'm not missing out on any bargains.

You have alternatives besides IAR.

The CodeVision compiler from http://www.hpinfotech.ro/ looks good, I 
have associates who used it and didn't have anything unpleasant to say. 
There is a version of the compiler that also supports the FPSLIC too. It 
supports a number of optimizations and also includes pragmas so you can 
optimize for speed or size.

There is also ImageCraft (www.imagecraft.com). I test drove the 30-day 
eval and found it had functionality, but wasn't laid out (in my opinion)
as well as the above. Code produced looked OK I found CodeVision was 
better in some instances, but I didn't spend too much time trying to 
optimize for my test runs.

There is also AVR-GCC if you feel like dealing with GNU stuff...I have 
*major* problems with this toolchain since(among other issues) it does 
not support "dead code" removal which should rip out any pieces of 
compiled code that aren't referenced in your program. I have a small set 
of C routines that I use in many of my projects but often not all 
functions in the "common set" C file are used. GCC won't remove those 
(even if you mess around with the linker scripts).

Also, there aren't any pragmas for optimization (just your standard -o1 
-o2 -o3 switches) which means you have to segment code into seperate 
files to get it optimized the way you want (very sub-optimal). 

GCC just wasn't meant for 8-bit micros, and I found plenty of fault with 
the code it generates too.

Anyway, you have some alternatives.

-- Jay.


Article: 59077
Subject: Re: Error Generate Statement
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Thu, 07 Aug 2003 14:10:53 -0700
Links: << >>  << T >>  << A >>


Keith Williams wrote:
> In article <d9db536c.0308071105.115657b4@posting.google.com>, 
> smukthav@yahoo.com says...
> 
>>You cannot read the output ports. There are two ways you can solve
>>this....make the signals on the entity "Outputs" as type inout or
>>create an internal signal Outputs and assign the internal signal to
>>the Outputs. The second approach though is tedious doesnt actually
>>create anymore extra logic. The first approach sometime confuses the
>>synthesis tool when trying to resolve in/out and may infer tri-state
>>logic if it cannot figure out.
> 
> 
> You can also assign the entity "outputs" as type buffer.  I recommend 
> the internal signal method though.
> 

Consider the local variable method.
No need to clutter the name space and
slow down the sim with dummy signals.


-- Mike Treseler

-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; -- std_ulogic
use ieee.numeric_std.all;    -- SLL, unsigned

entity shifter is
    -- Mike Treseler Thu Aug  7 13:53:27 2003

    generic (length : positive := 8);

    port (clk : in  std_ulogic;
          rst : in  std_ulogic;
          si  : in  std_ulogic;                     -- serial in
          po  : out unsigned(length-1 downto 0)) ;  -- vector out

end entity shifter;

architecture synth of shifter is

begin  -- architecture sim
    sh : process (clk, rst) is
       variable po_v : unsigned(po'range);
    begin  -- process sh
       if rst = '1' then                 -- asynchronous reset (active high)
          po_v := (others => '0');
       elsif rising_edge(clk) then
          po_v    := po_v SLL 1;         -- shift left
          po_v(0) := si;                 -- right bit in
       end if;
       po <= po_v;                       -- shifted vec out
    end process sh;

end architecture synth;


Article: 59078
Subject: Re: Need help: getting 3.1i Coregen working on P4-system
From: marlboro <>
Date: Thu, 7 Aug 2003 14:37:15 -0700
Links: << >>  << T >>  << A >>
P4 = Pentium 4?

Article: 59079
Subject: Re: Patent granted for "system on a chip" framework?
From: brad@tinyboot.com (Brad Eckert)
Date: 7 Aug 2003 15:58:26 -0700
Links: << >>  << T >>  << A >>
Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F2FC028.85C217A@xilinx.com>...
> 
> I, too, have my doubts on this one.
> 
> Even though you may have used this prior to the patent, that would only
> allow you to continue using the technique without paying royalties.  If no
> one published or "disclosed" the technique, then the patent could be
> valid.  Hopefully you have a public published document prior to their
> "discovery"?  That would kill it immediately.
> 
Does a web site count as published? For example, are the cores at
Opencores.org considered publicly published because they reside there?

Article: 59080
Subject: Re: Size does matter
From: "<>" <>
Date: Thu, 07 Aug 2003 19:30:45 -0400
Links: << >>  << T >>  << A >>
On Sat, 02 Aug 2003 02:12:02 +1000, Rob Judd <judd@ob-wan.com> wrote:

>Nicholas,
>
>No, manufacturability is the main concern. I don't have easy access to
>high volume production machinery, which is almost guaranteed to be
>necessary for most of the newer packages. If I can plug it in, great. If
>not, I need to be able to hand-solder it with a standard Weller iron.
>
>Rob
>
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

if you are looking for plug in cabaliity as main criteria, then Rena
Electronics sell a board that is 15x15 PGA foot print with a
XC2S100-5VQFP onboard. get you 100k gates and nice prototyping plugin
capabilities.

You can also buy just the TQFP/VQFP to PGA adaptor board with no FPGA.

Also they will sell you an adaptor board and you send them the chip
and they will attach it. 

This will not give you small physical size but ease from soldering
fine pitch QFP packages. 

The only way I would attempt soldering BGA packages on a small scale
production is to use a hot plate and a lot of flux. Place the PCB,
should be FR4 min., on the hot plate at about 275C with BGA on board
aligned as close as possible. Use liquid flux and wait about 30
seconds. If the BGA is close to alignment, +/- half a ball width,
then it will align with the pads. Once it starts to float the remove
from the hot plate gently. Let cool and pray!

james
 
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>
>Nicholas C. Weaver wrote:
>> 
>> In article <3F2A4153.66C411AD@ob-wan.com>, Rob Judd  <judd@ob-wan.com> wrote:
>> >Hi,
>> >
>> >My application requires a lot of core but few physical i/o lines. Can
>> >anyone suggest a modern fpga that is delivered in a 68-pin plcc and/or
>> >80-pin pqfp package?
>> 
>> Is your concern board area?  Hand soldering?  Cost?
>> 
>> A small BGA package might be appropriate, as a .5mm spacing BGA for a
>> small pincount is really tiny, if the concerns are board area and
>> cost.
>> --
>> Nicholas C. Weaver                                 nweaver@cs.berkeley.edu


Article: 59081
Subject: Re: Patent granted for "system on a chip" framework?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Fri, 08 Aug 2003 11:31:03 +1200
Links: << >>  << T >>  << A >>
Brad Eckert wrote:
> 
> Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F2FC028.85C217A@xilinx.com>...
> >
> > I, too, have my doubts on this one.
> >
> > Even though you may have used this prior to the patent, that would only
> > allow you to continue using the technique without paying royalties.  If no
> > one published or "disclosed" the technique, then the patent could be
> > valid.  Hopefully you have a public published document prior to their
> > "discovery"?  That would kill it immediately.
> >
> Does a web site count as published? For example, are the cores at
> Opencores.org considered publicly published because they reside there?

 Yes, that is clearly in the public domain.
Like the patent above, all this is really just a 'feeding trough for
lawyers',
and prior art, and obvious to anyone experienced in the field, 
do not get much of a look-in.
 Bluster and Bluff, as seen in this patent case, are common revenue
tools.
Sometimes, however, it does backfire - Rambus is a good example.
-jg

Article: 59082
Subject: Re: Patent granted for "system on a chip" framework?
From: y_p_w@hotmail.com (y_p_w)
Date: 7 Aug 2003 16:50:33 -0700
Links: << >>  << T >>  << A >>
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<CavYa.85$zm3.9556171@newssvr14.news.prodigy.com>...
> "y_p_w" <y_p_w@hotmail.com> wrote in message
> news:591da479.0308070824.769ead96@posting.google.com...
> > "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
>  news:<4ofYa.15$BU7.2095256@newssvr14.news.prodigy.com>...
> > > No surprise to me.  Some guy out of MIT got a patent for the mechanics
>  of
> > > the human arm (actually, any articulation-muscle mechanism on any animal
>  on
> > > earth for the last several billion years).
> >
> > That actually makes some sense, if the purpose was to create a
> > mechanical replica - i.e. prosthetics or a robot arm.  This new
> > patent would seemingly describe a set of techniques that most
> > engineers would never thought of patenting because they were
> > (more or less) in the public domain.
> 
> Well, not in this case, at least in my opinion.  It describes something they
> call "series elastic" actuators.  Translation: store energy in a spring (or
> spring-like element) as opposed to having the motors directly drive the
> joint.  In other words, a tendon.  Using springs to store energy (or control
> force) has been in use for a long, long time, I think.

Your average desk lamp comes to mind.  Garage door mechanisms are
spring loaded too - the ones for solid garage door would seem to
be similar to this "arm" mechanism.

Article: 59083
Subject: Re: Offshore engineering
From: jhallen@TheWorld.com (Joseph H Allen)
Date: Fri, 8 Aug 2003 00:06:27 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <1060282483.98516@haldjas.folklore.ee>,
Sander Vesik  <sander@haldjas.folklore.ee> wrote:

>This cuts both ways... Why would non-technical jobs remain over time if all
>techincal ones have left?

Ultimately venture capitalists will invest their money offshore and get the
whole company for 1/10 the price.  The only thing left in the US might be
some sales people who actually have to meet the clients (i.e., to suck any
remaining wealth out).

Recently I've been thinking about our class system with respect to
off-shoring both white and blue-collar jobs.  I think that the really rich
people in this country support these policies because they think that wealth
is a zero sum game- if they could just decimate the middle class they will
be really really rich by comparison.

But don't worry, it can't go on forever: when this happened in France,
Robespierre guillotined all of the bastards.
-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Article: 59084
Subject: Post synthesis(PAR) Simln in Xilinx WEbPack 5.2: Port Mismatch error
From: machosri@yahoo.com (Sriram)
Date: 7 Aug 2003 17:40:42 -0700
Links: << >>  << T >>  << A >>
hi , 
I was able to do compile and do behavioral simulation of the matrix 
addition code. Then I synthesized it using Xilinx WebPack ISE 5 tools . 
Then when I try to use tbw (test bench waveform ) am unable to create 
one as my input matrices are "array of arrays" type . So I wrote my own 
testbench .
Using this I was able to do behav simln,
But when I tried to do post Place and route Simulation , I ran into 
errors . 
the Error messages I run into are : 
# WARNING[1] :types do not match for port a_mat
# WARNING[1]: matadd_Xilinx_tb.vhd(44): A use of this default binding 
for this component instantiation will result in an elaboration error.
 
My guess is that the synthesized output doesnt recognize matrix_type as 
a valid type and so the design's a_mat and the testbench' s a_mat dont 
match,resulting in the above port mismatch error.
 
I'm able to zero in on why the error is occuring , but since XILINX has 
hidden the synthesis and implementation processes , dont know how to 
rectify the above port mismatch problem.
 
If anybody in the group , has encountered a similar problem and know 
the fix to it , it would be immensely helpful .
 
thanks ,
Sriram 
 
 
 
My source code for design and testbench are : 
PACKAGE :
 
library ieee;
use ieee.std_logic_1164.all;
package matrix_types is
 constant matwidth : positive := 2; --Matrix Width
 TYPE matrix_type IS ARRAY (matwidth-1 DOWNTO 0) OF
                        STD_LOGIC_VECTOR(matwidth -1 DOWNTO 0); 
 end;
 
MAtrix addition design code : 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all ; 
use work.matrix_types.all;
ENTITY matrix_add IS
    PORT (
        RESET   : in STD_LOGIC;
        CLOCK   : in STD_LOGIC;
        A_mat   : in matrix_type;
        B_mat   : in matrix_type;
        Sum_mat : out matrix_type
    );
END matrix_add;
ARCHITECTURE behav OF matrix_add IS
    BEGIN
      -- matrix addition  
        behav_pr: process (A_mat,B_mat,clock,reset)
        begin 
              if (reset='1') then 
                Sum_mat <= (others => (others=>'0') );
              elsif(clock'event and clock ='1') then 
   for i in matwidth -1 downto 0 loop
            sum_mat(i) <= std_logic_vector (unsigned(A_mat(i)) +
                                   unsigned(B_mat(i))) ;  
              end loop ;      
              end if ;
        end process behav_pr;
end architecture behav ; 

My testbench : 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.matrix_types.all;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS 
 COMPONENT matrix_add
 PORT(
  reset : IN std_logic;
  clock : IN std_logic;
  a_mat : IN matrix_type; 
  b_mat : IN matrix_type;          
  sum_mat :OUT matrix_type
  );
 END COMPONENT;
 SIGNAL reset :  std_logic;
 SIGNAL clock :  std_logic;
 SIGNAL a_mat :  matrix_type;
 SIGNAL b_mat :  matrix_type;
 SIGNAL sum_mat :matrix_type;
BEGIN
 uut: matrix_add PORT MAP(
  reset => reset,
  clock => clock,
  a_mat => a_mat,
  b_mat => b_mat,
  sum_mat => sum_mat
 );

-- *** Test Bench - User Defined Section ***
rst_pr:process 
begin 
reset<='1'; 
wait for 4 ns ;
reset<='0';
wait ;
end process rst_pr ;
------------------------
-- clock process
-----------------------
clk_pr :process 
begin 
clock <='1';
wait for 10 ns ; 
clock <='0';
wait for 10 ns ; 
end process clk_pr ; 
------------------------
-- inputs process
-----------------------
inputs_pr:process 
begin 
a_mat <= ( ("00") ,("00") ) ;
b_mat <= ( ("11") ,("11") ) ;
wait for 35 ns ;
a_mat <= ( ("00") ,("01") ) ;
b_mat <= ( ("11") ,("01") ) ;
wait for 10 ns;
a_mat <= ( ("01") ,("00") ) ;
b_mat <= ( ("11") ,("00") ) ;
wait ;
end process inputs_pr; 
-- *** End Test Bench - User Defined Section ***
END;

Article: 59085
Subject: fast read, slow write memory
From: "Jimmy Zhang" <crackeur@comcast.net>
Date: Fri, 08 Aug 2003 01:41:07 GMT
Links: << >>  << T >>  << A >>
Hi, I am aware that using SRAM or block RAM, I get fast read and write. But
is there some kind of
solution that I can read very quickly in SRAM speed, but write performance
is less important. I am
asking this becasue the design I have in mind can get very resource
intensive, i.e, use lots of block RAM
so if I can using them in some operations where write is less important, or
not needed at all, I don't have to
use block RAM. I will probably save block ram for some other parts of teh
design.

Would it be possible to have some kind of high speed ROM on FPGA??

Jimmy



Article: 59086
Subject: Quartus II and fixing hold timing
From: kjaram_junk@cox.net (Ken Jaramillo)
Date: 7 Aug 2003 18:55:22 -0700
Links: << >>  << T >>  << A >>
I'm using Quartus II version 3.0 and am having trouble meeting setup
 and hold timing. This is a large PCI design in the 
Cyclone 12C device. The routing I'm getting is really bad so my
setup time violations are pretty bad. I can fix the setup times by
inserting 2 LCELL buffers on the PCI clock and placing the buffers
in such a way to get a lot of clock insertion (around 8 ns). If I synthesize the 
design without hold time fixing enabled then I can get Tsu and Tco
to pass (just barely). I have the PCI logic back annotated (placement
not routing). If I then synthesize while enabling hold time fixing 
Quartus fixes most of the hold time violations but breaks the setup 
timing even though the PCI logic is back annotated. I think Quartus
must be pretty dumb as far as fixing hold timing. If the worst 
case setup time is around 15 ns (8 ns clock insertion + 7 ns PCI setup
time requirement) then those worst case paths should have no problem
with hold times. If quartus just placed delays on the short paths
it could fix hold timing. But I suspect that it's placing the delays
around the pin and affecting both long and short paths.

Has anyone else seen this? Does anyone have any idea of how to fix hold
timing while not breaking the setup paths?

Ken Jaramillo

Article: 59087
Subject: Re: Size does matter
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 07 Aug 2003 22:37:33 -0400
Links: << >>  << T >>  << A >>
I am curious, as to why you care how many pins it has rather than the
size.  The 68 PLCC and 80 pin PQFP are two of the larger packages used
for FPGAs.  The VQFP 100 is one of the smallest, non-BGA packages used. 
What is wrong with the 100 VQFP?  

If you want, I will be happy to snip off a few IO pins to give you a 50
pin VQFP!  How many IOs do you want left?  


Rob Judd wrote:
> 
> Martin,
> 
> If it had about half the pins and 10x the LE I'd be interested.
> 
> Rob
> 
> Martin Schoeberl wrote:
> >
> > The Cyclone start with a 100 pin TQFT.
> >
> > Martin
> >
> > > Hi,
> > >
> > > My application requires a lot of core but few physical i/o lines. Can
> > > anyone suggest a modern fpga that is delivered in a 68-pin plcc and/or
> > > 80-pin pqfp package?
> > >
> > > Thanks,
> > >
> > > Rob

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 59088
Subject: Re: Size does matter
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 07 Aug 2003 22:51:03 -0400
Links: << >>  << T >>  << A >>
"Steven K. Knapp" wrote:
> 
> "Rob Judd" <judd@ob-wan.com> wrote in message
> news:3F2A4153.66C411AD@ob-wan.com...
> > Hi,
> >
> > My application requires a lot of core but few physical i/o lines. Can
> > anyone suggest a modern fpga that is delivered in a 68-pin plcc and/or
> > 80-pin pqfp package?
> >
> > Thanks,
> >
> > Rob
> 
> Sorry to act as a shill, but I believe the Xilinx Spartan-3 family provides
> the largest amount of logic with the fewest number of I/O pins.

...snip...


Well, all the marketing "stuff" aside, I have been thinking about this
the last few days, and I think marketing teams are missing some
opportunities.  I know that in some of my recent designs, I could have
used a small to medium FPGA instead of a CPLD if the FPGA were available
in a small package.  And contrary to what FAEs may tell you in this
newsgroup, FPGAs with Flash is not a bad idea either.  

If a 50K gate FPGA (1,536 logic cells in the XC3S for example) could be
put in a 48 pin TQFP, and include Flash on die, then that would be a
great product!  I know that the chip designers would have a hard time
figuring out how to do this, but it would be a CPLD killer!  I have
already replaced one of the larger CPLDs on my current board with an
FPGA.  I have a second CPLD that could easily be replaced by an FPGA
with flash.  Even if they had to go back to .25 micron process to get
the flash, would that be so bad?  A decent FPGA could easily be built at
those densities that would kick CPLD butt.  

Is Lattice the only company that thinks a decent sized FPGA with on die
flash is a good idea?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 59089
Subject: Re: Xilinx ISE WebPack 5.2 & VHDL : wait synthesis
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 07 Aug 2003 23:01:25 -0400
Links: << >>  << T >>  << A >>
"Amontec Team, Laurent Gauch" wrote:
> 
> max wrote:
> > I tried this source code:
> >
> > entity main is
> >     Port ( clk , en : in std_logic;
> >            sout : out std_logic);
> > end main;
> >
> > architecture Behavioral of main is
> > begin
> >   process
> >   variable a : std_logic;
> >   begin
> >     sout <= '0';
> >     a := '0';
> >     wait until rising_edge(en);
> >     while en = '1' loop
> > -- wait until rising_edge(clk);
> >       wait until clk'event and clk = '1';
> >       a := not a;
> >       sout <= a;
> >     end loop;
> >   end process;
> >
> > end Behavioral;
> >
> > and I obtain this error:
> >
> > Analyzing Entity <main> (Architecture <behavioral>).
> > ERROR:Xst:825 - C:/Lavori/menfis/prova_xilinx/prova_2/main.vhd line xx: Wait
> > statement in a procedure is not accepted.
> >
> > The question is: can I use wait or not?
> > I found a lot of manual on the internet (eg.
> > http://mikro.e-technik.uni-ulm.de/vhdl/anl-engl.syn/html/node8.html), and all of
> > them sais that 'wait' is allowed in synthesis.
> >
> > thanks
> >
> 
> Your code is NOT a synthesable code.
> 
> Don't use 'wait' for synthesis code, but use 'wait' for your testbench
> tester.
> 
> A synthesisable code will follow the rules:
> - reset signal can be asynchro. or synchro.
> - enable signal is ever synchro.
> - if possible use only signal (don't use variable for synthesable code)
> 
> LOOK:
> 
>   entity main is
>       Port ( clk , en : in std_ulogic;
>              sout : out std_ulogic);
>   end main;
> 
>   architecture Behavioral of main is
>   signal a : std_ulogic;
>   begin
>     process (clk)
>     begin
>       if rising_edge(clk) then
>         if en = '1' then
>           a <= not a;
>           sout <= a;
>         end if ;
>       end if;
>     end process;
> 
>   end Behavioral;
> 
> PS: 'wait' and 'variable' are GREAT for simulation
>      try http://www.amontec.com/vhdl_part.shtml
> 
> Laurent Gauch
> www.amontec.com

Yeah, I would second that opinion.  Reading your code it looks like you
are treating VHDL as a software language rather than a hardware
language.  To see what I mean, consider what you are trying to tell the
compiler to generate.  If you can't figure out what the hardware should
look like, how can you expect the software to figure it out?  I know
that I can't figure out what hardware you are trying to describe or what
could be built that would do what your software does.  It clearly does
not describe a FF with logic feeding the D input and a clock enable
signal.  There are too many waits for that.  

Take a look at some synthesis templates for FFs and other hardware items
that you might want to generate.  Don't think in terms of the language,
think in terms of the hardware you want to build.  Then you should get
synthesizable code. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 59090
Subject: Re: Size does matter
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Fri, 08 Aug 2003 15:08:33 +1200
Links: << >>  << T >>  << A >>
rickman wrote:
> 
> "Steven K. Knapp" wrote:
> >
> > "Rob Judd" <judd@ob-wan.com> wrote in message
> > news:3F2A4153.66C411AD@ob-wan.com...
> > > Hi,
> > >
> > > My application requires a lot of core but few physical i/o lines. Can
> > > anyone suggest a modern fpga that is delivered in a 68-pin plcc and/or
> > > 80-pin pqfp package?
> > >
> > > Thanks,
> > >
> > > Rob
> >
> > Sorry to act as a shill, but I believe the Xilinx Spartan-3 family provides
> > the largest amount of logic with the fewest number of I/O pins.
> 
> ...snip...
> 
> Well, all the marketing "stuff" aside, I have been thinking about this
> the last few days, and I think marketing teams are missing some
> opportunities.  I know that in some of my recent designs, I could have
> used a small to medium FPGA instead of a CPLD if the FPGA were available
> in a small package.  And contrary to what FAEs may tell you in this
> newsgroup, FPGAs with Flash is not a bad idea either.
> 
> If a 50K gate FPGA (1,536 logic cells in the XC3S for example) could be
> put in a 48 pin TQFP, and include Flash on die, then that would be a
> great product!  I know that the chip designers would have a hard time
> figuring out how to do this, but it would be a CPLD killer!  I have
> already replaced one of the larger CPLDs on my current board with an
> FPGA.  I have a second CPLD that could easily be replaced by an FPGA
> with flash.  Even if they had to go back to .25 micron process to get
> the flash, would that be so bad?  A decent FPGA could easily be built at
> those densities that would kick CPLD butt.

 Yes, and there is also a hole in the CPLD sector, around TQFP64.
CPLD started with PLCC68/PLCC84 pin devices, but never replaced them
with the move to SMD, so you have just 44/100 commonly.


> Is Lattice the only company that thinks a decent sized FPGA with on die
> flash is a good idea?

 Look at the FLASH ProASIC from Actel, that's quite close to what you
describe. Comes in TQFP100 and FBGA144. Getting to TQFP48 is a bigger
ask, as the market would be thinning a lot - how many Vcc/Gnd/Core/JTAG
pins do 
you loose ?

FBGA144 is not as nice to apply, but it is 13mm on an edge, so not much
larger than TQFP48.
No, you cannot deploy this on single sided PCB.
TQFP100 is 16mm / edge, and that is single sided possible.

Philips have pitched at this big core/small package (TQFP48) with their
first ARM uC variants.

-jg

Article: 59091
Subject: Re: Quartus II and fixing hold timing
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 07 Aug 2003 23:16:35 -0400
Links: << >>  << T >>  << A >>
Ken Jaramillo wrote:
> 
> I'm using Quartus II version 3.0 and am having trouble meeting setup
>  and hold timing. This is a large PCI design in the
> Cyclone 12C device. The routing I'm getting is really bad so my
> setup time violations are pretty bad. I can fix the setup times by
> inserting 2 LCELL buffers on the PCI clock and placing the buffers
> in such a way to get a lot of clock insertion (around 8 ns). If I synthesize the
> design without hold time fixing enabled then I can get Tsu and Tco
> to pass (just barely). I have the PCI logic back annotated (placement
> not routing). If I then synthesize while enabling hold time fixing
> Quartus fixes most of the hold time violations but breaks the setup
> timing even though the PCI logic is back annotated. I think Quartus
> must be pretty dumb as far as fixing hold timing. If the worst
> case setup time is around 15 ns (8 ns clock insertion + 7 ns PCI setup
> time requirement) then those worst case paths should have no problem
> with hold times. If quartus just placed delays on the short paths
> it could fix hold timing. But I suspect that it's placing the delays
> around the pin and affecting both long and short paths.
> 
> Has anyone else seen this? Does anyone have any idea of how to fix hold
> timing while not breaking the setup paths?

I think the best way to fix the setup and hold time problem is to fix
the routing.  The best way to fix the routing is to fix the placement to
permit the routing to be good.  

Even if you fix the timing by adjusting the relative clock delay, I
don't think buffers are the way to do it.  The delay from a buffer can
vary over a wide range.  So you may add a lot of delay max and very
little min.  The min delay will help with the hold time, but the large
max delay will detract a lot more from the setup!  Perhaps a DLL is what
you need?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 59092
Subject: Re: Quartus II and fixing hold timing
From: Mike Treseler <tres@tc.fluke.com>
Date: Thu, 07 Aug 2003 21:00:38 -0700
Links: << >>  << T >>  << A >>
Ken Jaramillo wrote:
> I'm using Quartus II version 3.0 and am having trouble meeting setup
>  and hold timing.

A hold violation is very rare on any FPGA if the design is synchronous
and the dedicated clock distribution is used.


     -- Mike Treseler


Article: 59093
Subject: Re: "ML300 Embedded" Mapping Help
From: hln01@uow.edu.au (Lan Nguyen)
Date: 7 Aug 2003 23:00:59 -0700
Links: << >>  << T >>  << A >>
thanks Peter, 

it's working :p

Peter Ryser <ryserp@xilinx.com> wrote in message news:<3F2FE7B1.3C47DABD@xilinx.com>...
> Hi Lan,
> 
> you should not need to do any of this. After opening a V2PDK shell (Windows) or sourcing
> v2pro_setup (Solaris) change into your project directory. After editing flow.cfg (if necessary)
> type "make synth". Synplify will open (if you didn't chose to add -batch in flow.cfg) and you can
> synthesize the design. After leaving synplify type "make fpga" to start the implementation
> followed by "make bit" to generate the bitstream.
> 
> - Peter
> 
> 
> Lan Nguyen wrote:
> 
> > Hi,
> >
> > I did the synthesis with Synplify 7.3 and got the output "top.edif".
> > Then I used "edif2ngd" to convert "top.edif" to "top.ngo". This is
> > where I got the problem. The "top.ngo" was not properly produced, so
> > the program stopped and popped up the error:
> >
> > "ERROR:XdmHelpers:828: File "top.ngo" is not in NGD or XDB format".
> >
> > I could not figure out what the problem is.
> >
> > Any help would be very appreciated.
> >
> > Lan
> >
> > Peter Ryser <ryserp@xilinx.com> wrote in message news:<3F276433.EFFC08BE@xilinx.com>...
> > > Lan,
> > >
> > > while XST is not supported for the ml300_embedded_* design shipping with ML300/V2PDK 1.5 it
> > > will work with the Verilog version but not work with VHDL. However, you will have to remove
> > > some peripherals from the system by modifying flow.cfg and changing the yes/no table at the
> > > end of the file.
> > >
> > > The default setup for the ml300_embedded_verilog design is the one that is part of the
> > > ML300 ACE files, ie. Linux will boot even if there are devices like AC97 and others that
> > > are not directly supported by Linux.
> > >
> > > flow.cfg is the central file for all configurations, tools, SW, peripherals, etc.
> > >
> > > - Peter
> > >
> > >
> > > Lan Nguyen wrote:
> > >
> > > > Hi Peter,
> > > >
> > > > I've got the Developer's Kit V2PDK VP4. I wanted to run the reference
> > > > designs and test the results via the serial port. I tried and got
> > > > nothing in the HyperTerminal.
> > > >
> > > > Does XST work for the synthesis ? If so, what modifications do I have
> > > > to make ?
> > > >
> > > > (I was told that the only way is to get Synplify synthesis tool)
> > > >
> > > > Thanks
> > > >
> > > > Lan
> > > >
> > > > Peter Ryser <ryserp@xilinx.com> wrote in message news:<3F1F1FE4.B2A8FCB1@xilinx.com>...
> > > > > Yes, it does. The reference design actually comes with the MLD (Microprocessor
> > > > > Library Definition) technology that allows you to automatically generate a BSP
> > > > > for Linux consisting of Xilinx layer 0 and 1 drivers according to the hardware
> > > > > definition (MHS). When you generate the libraries from the system_linux.xmp
> > > > > project file you will get this BSP.
> > > > >
> > > > > The BSP will also contain necessary patches to the Linux kernel to make the
> > > > > design work with MontaVista Linux 3.0 (FYI: the only thing that needs to be
> > > > > patched is the code for the Xilinx interrupt driver since the interrupt
> > > > > controller from V2PDK and EDK are different)
> > > > >
> > > > > - Peter
> > > > >
> > > > >
> > > > > tk wrote:
> > > > >
> > > > > > Hi Peter,
> > > > > >
> > > > > > I would like to ask if the reference design support
> > > > > > MontaVista Linux Pro 3.0 ?
> > > > > >
> > > > > > Thanks very much!
> > > > > >
> > > > > > tk
> > > > > >
> > > > > > Peter Ryser wrote:
> > > > > >
> > > > > > > Antti,
> > > > > > >
> > > > > > > the EDK reference design for ML300 contains
> > > > > > > - 1 PPC 405
> > > > > > > - 1 PLB DDR
> > > > > > > - 1 PLB bus with arbiter
> > > > > > > - 1 PLB2OPB bridge
> > > > > > > - 1 PLB BRAM controller with 32 KB BRAM attached
> > > > > > > - 1 OPB Uart
> > > > > > > - 2 OPB GPIO
> > > > > > > - 1 OPB 10/100 Ethernet (interrupt driven)
> > > > > > > - 1 OPB IIC
> > > > > > > - 1 OPB System ACE CF
> > > > > > >
> > > > > > > There is no touchscreen, PS/2, TFT, parallel port and AC97. Adding these
> > > > > > > peripherals to the design is planned for a later release that will most
> > > > > > > likely happen towards the end of the year.
> > > > > > >
> > > > > > > There is some documentation in the zip file that lists the peripherals and
> > > > > > > explains the design.
> > > > > > > Again, please contact your Xilinx FAE if you would like to get access to
> > > > > > > this design.
> > > > > > >
> > > > > > > Thanks,
> > > > > > > - Peter
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > Antti Lukats wrote:
> > > > > > >
> > > > > > >> Peter Ryser <ryserp@xilinx.com> wrote in message
> > > > > > >> news:<3F1846C0.776CD1F5@xilinx.com>...
> > > > > > >> >
> > > > > > >> > If you want to work with EDK please contact your FAE and ask him to get
> > > > > > >> > you access to the EDK reference design for ML300. He will be able to
> > > > > > >> > get you access to the design.
> > > > > > >>
> > > > > > >> Hi Peter,
> > > > > > >>
> > > > > > >> when we received the EDK + DDR project, I also asked to be notified
> > > > > > >> when a better EDK ref. design will be available, and so far have not
> > > > > > >> got any more info, could you please enlight us what additional cores
> > > > > > >> are available in the EDK ref. design you mentioned?
> > > > > > >>
> > > > > > >> ASFAIK TFT and Touchscreen are not implemented (or hopefully are now?)
> > > > > > >> I have still having trouble to get EDK to work correctly using the
> > > > > > >> obsoleted TFT ref. design - eg. display is looking in stripes 8 pixels
> > > > > > >> missing after 8 ok pixels - if the problem is fixed and ref design
> > > > > > >> availabl would be greate.
> > > > > > >>
> > > > > > >> antti

Article: 59094
Subject: Re: Spartan-IIE LVDS?
From: eric_usenet@yahoo.com (Eric)
Date: 7 Aug 2003 23:11:27 -0700
Links: << >>  << T >>  << A >>
> Eric wrote:
> > 
> > Hello! I'm trying to move 125 MB/sec bidirectionally off a daughter
> > card, for a total of 250 MB/sec. I worry that even if I double the 8
> > bit bus in each direction to 16-bits (32 data pins todal) I'll still
> > be pushing a single-ended signal across a connector at 62.5 MHz. I
> > can't go wider because I run out of pins on my QFP.
> > 
> > I've started looking at LVDS, but it seems that xilinx has very little
> > information on how to actually _use_ lvds in a project. National has
> > some great app notes, but they're largely targeted at the national
> > family of SERDES products. Can anyone offer any suggestions for
> > high-speed multi-board data transfer between FPGAs? Has anyone ever
> > tried building a SerDes in a spartan-IIE, and if so, what kinds of
> > speeds have you been able to get?
> > 
> > Thanks for the help!
> >                  ...Eric
Peter Alfke <peter@xilinx.com> wrote in message news:<3F32788A.4DDCA931@xilinx.com>...
> Eric, what makes you think that 62 MHz I/O transfer is a problem?
> You can easily go twice as fast...
> 
> Peter Alfke, Xilinx
> =========================


I'm too poor to buy an IBIS simulator :) I've been reading all sorts
of data sheets and app notes on LVDS that have made me worry about any
sort of single-ended signals  one can reliably send over a short bus.
I read that PCI has really tight timings and is evidently really hard
to design for; it's only 33 MHz. Sure, it's a bus with multiple cards,
but AGP is a single card in a single slot, and only runs at 66 MHz. I
feared that if "real" EEs (instead of us biologists that just play
them when we need equiment that doesn't exist) don't want to push a
card interconnect above 66 Mhz, there must be a good reason.

So I'm trying to figure out what I can reasonably expect from a
4-layer FR4 board and a 68-pin high-density mini-D connector. This is
my first high-speed interconnect project, and it may just be paranoia.
Are you suggesting I shouldn't lose too much sleep over a  ~125 MHz
single-ended bus covering a distance of 6" or so? or should I stick to
differential signaling for those types of speeds? I'd love to just
make my bus wider, but I run out of IOs on my Spartan-IIE PQFP and I
can't afford to have someone put down a BGA on a PCB.

Ahh, the joys of low-cost student design ! :) 

Thanks again for all the help,
               ...Eric

Article: 59095
Subject: Re: Size does matter
From: antti@case2000.com (Antti Lukats)
Date: 8 Aug 2003 01:01:55 -0700
Links: << >>  << T >>  << A >>
> Is Lattice the only company that thinks a decent sized FPGA with on die
> flash is a good idea?  

actel ProAsic+
and upcoming ProAsic will have not only flash configuration but user
BlockFlash cells :)

antti

Article: 59096
Subject: Upgrading OS or WebPack
From: Aart van Beuzekom <aart@westcontrol.com>
Date: Fri, 08 Aug 2003 11:35:05 +0200
Links: << >>  << T >>  << A >>
Hei,

I will start developing FPGA applications with WebPack. My problem is
that my OS is WinNT, which is not supported by WebPack 5.2i. I've got a
CD laying round here with WebPack version 4.2WP0.0. 

Can anybody tell me if the advantages of v. 5.2i are so much that
upgrading to Win2000 really is necessary?

My application will run on a Spartan-II device. Clock speed wil not be
an issue, but efficient use of logic cells might be.

Thanks,

Aart

Article: 59097
Subject: Clocking in a virtex 2 without using the clock trees : questions
From: jean-francois.hasson@fr.thalesgroup.com (jean-francois hasson)
Date: 8 Aug 2003 02:51:43 -0700
Links: << >>  << T >>  << A >>
Hi,

I have a serial bus coming in a Virtex II -5 in LVDS format at 80 MHZ
with 3 data in parallel. The data change on the falling edge of the
clock. The problem is that the clock is present only when data is
transmitted (no DCM possible) and the pads used for the clock does not
allow the use of a bufgp without an important routing delay. I am
using the MAXSKEW constraint on the received clock and the best I can
get is 450 ps (I can not use the local clock resources described in
xapp609). This clock goes to approximately 40 FFs. I have, on this
clock domain, among other things, a shift register so I have a FF to
FF path. When having the min skew of 450 ps parts of the shift
register are implemented in the same CLB so the output of a FF goes
through the local routing matrix of the CLB and back to the input of a
FF in the same CLB : I believe it must be the shortest and quickest
path to go from one FF to another. My problem is that I wonder if the
skew I have will always be smaller than the clock_to_out + prop_delay
: I believe the max values are ok but what about typical ?

Thank you.

J.F. Hasson

Article: 59098
Subject: I am new and I want to help
From: usrdr@yahoo.co.uk (serdar)
Date: 8 Aug 2003 03:39:25 -0700
Links: << >>  << T >>  << A >>
Hi,
I am new CPLD and FPGA. Should I start Xilinx devices or ALTERA
devices? and verilog or VHDL?
I think buy a CPLD starter board.(CoolRunner II Design Kit or MAX 7000
Quick Start Development Kit) Can you recommended any board for
starting?

Article: 59099
Subject: Compilation error
From: "YesMann" <waydak@hotmail.com>
Date: Fri, 8 Aug 2003 12:47:02 +0200
Links: << >>  << T >>  << A >>
Hello,
I have error in the process below;
My process is:

1. process(cycle)
2. begin
3.   case cycle is
4.
5.
6.      WHEN  "000000" | "000001" | "000010"     => REG <= "001000";
7.      WHEN  "000011" to "011101"                    => REG <= "000000";
8.      WHEN  "011110" | "011111" | "100000"     => REG <= "001010";
9.      WHEN  "100001"                                        => REG <=
"000010";
10.    WHEN  "100010" | "100011" | "100100"      => REG <= "001101";
11.    WHEN  "100101" to "101000"                     => REG <= "000101";
12.
13.      WHEN OTHERS    => REG     <="000000";
14.
15.   end case;
16. end process;

The  line 7 and 11 are considered as error : " Range must be a scalar type".
What can I specified the range  "000011" to "011101" in VHDL language ?

Thanks in advance





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search