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Hello Seung, If you have 100% hardware utilization, doesn't this present a problem if you make a change to the design?? Curious what is the # for your patent?? Clay "Seung" <kim.seung@sbcglobal.net> wrote in message news:fdf92243.0308131136.74aff961@posting.google.com... > Hello > > I have a patent and recently added one more on innovative FFT > algorithm and architecture. > If you're a business minded expert on FPGA with interests in DSP, this > is a great opportunity. Our FFT is 'the' optimal HW solution as > follows: > > 1. Minimum HW complexity: 100% HW utilization > 2. Suitable for super fast pipelined FFT: only local data flow - not > based on butterfly algorithm > 3. Minimum clock cycles: baseline architecture needs N clock for > N-point FFT > 4. Scalable to arbitrary large FFT size > 5. Multi-dimension extension: world's first 'intrinsic' > multi-dimensional FFT algorithm & architecture (not relay on 1-D FFTs) > : great for 2-D/3-D real-time medical imaging, SAR, etc. > > If you're interested in building a business together based on this > innovation, > please contact me with your resume. It'll be ideal if you have > contacts for potential customers. > > Any help on this matter from FPGA/DSP group members will be > appreciated. > > > Thanks. > > Seung P. Kim, Ph.D > Silicon Computing, Inc. > Mountain View, CAArticle: 59276
Remember that you need to adjust the end time and THEN create the vectors with a longer end time otherwise the simulator will think it has no more vectors to simulate and will finish. That said, the Quartus simulator is painful in comparison with some of the $$$ products. "Chris" <chris.bailes@myrealbox.com> wrote in message news:bc923adb.0308130056.50b1f5b@posting.google.com... > Hi guys, > > I'm trying to simulate a block-based design with Altera's Quartus II > V3.0 Web version, however I cannot seem to simulate beyond 100ns > irrespective of what end points I set for the default and for the > current project. > > I've also tried editing the vector waveform file timing parameters > after generation and Quartus disregards these and ends the simualtion > at 100ns. It seems far too controlled to be a bug so I can only > assume its a limitation of the free version. Can anyone confirm this? > > If it is a limitation of the free version are there any *reliable* > third party simulators for reasonable money? I'm sitting on my hands > as far as this project goes until I resolve this. > > Kindest regards, > Chris Bailes > (Design Engineer, Studio Systems Electronics LTD).Article: 59277
Hi, I am working on a design involving a virtex II -5. I read in a previous post that the skew one could expect from a clock tree is less than 100 ps. However when, on the design I am developping, I run the timing analyzer I get a skew for some clock on a clock tree of about 450 ps or 500 ps (using the 5.1i F23). How should I interpret this difference ? Any clue ? Which figure is the right one ? J.F. HassonArticle: 59278
J.F., The report by the tools is correct. Different sized parts will have different skews (delays) in the their clock trees due to size. Additionally, skew is a function of position on the tree, so from the top left corner down to the middle of a part all the way to the bottom left corner, the skew will be less than 130 ps for a 2V6000, wheras from the top left corner over towards the top middle over to the right corner, it will be about 450 ps for a 2V6000. Top to bottom: 130 ps. Right to left: 450 ps. Smallest in the middles, largest at the corners. For a 2V1000, these are all less than 100 ps. Thus if you wanted to make the highest speed wide parallel interface, I would use the left or right sides (least skew), rather than the top or bottom edges (for least skew between bits). If I had to use the top or bottom edges, I would try to group the IOs near the center, or near the left and right extremes. Again the timing reports and FPGA_Editor report the right (worst case) numbers. Hope this helps, Austin jean-francois hasson wrote: > Hi, > > I am working on a design involving a virtex II -5. I read in a previous post > that the skew one could expect from a clock tree is less than 100 ps. > However when, on the design I am developping, I run the timing analyzer I > get a skew for some clock on a clock tree of about 450 ps or 500 ps (using > the 5.1i F23). How should I interpret this difference ? Any clue ? Which > figure is the right one ? > > J.F. HassonArticle: 59279
chris.bailes@myrealbox.com (Chris) wrote in message news:<bc923adb.0308130056.50b1f5b@posting.google.com>... > Hi guys, > > I'm trying to simulate a block-based design with Altera's Quartus II > V3.0 Web version, however I cannot seem to simulate beyond 100ns > irrespective of what end points I set for the default and for the > current project. > > I've also tried editing the vector waveform file timing parameters > after generation and Quartus disregards these and ends the simualtion > at 100ns. It seems far too controlled to be a bug so I can only > assume its a limitation of the free version. Can anyone confirm this? > > If it is a limitation of the free version are there any *reliable* > third party simulators for reasonable money? I'm sitting on my hands > as far as this project goes until I resolve this. > > Kindest regards, > Chris Bailes > (Design Engineer, Studio Systems Electronics LTD). Hi Chris, There is no limit on the Simulation End Time in Quartus II 3.0 Web Edition product. Please make sure you do the following: 1. Open the waveform editor on your channel and use the Edit->End Time command to set the end time correctly. 2. Use the Assignment->Settings command and then choose Simulator Settings->Time/Vectors. Set the Simulation Period to Run Simulation until all vector stimuli are used. - Subroto Datta Altera Corp.Article: 59280
On 13 Aug 2003 15:13:57 -0700, sdatta@altera.com (Subroto Datta) wrote: >chris.bailes@myrealbox.com (Chris) wrote in message news:<bc923adb.0308130056.50b1f5b@posting.google.com>... >> Hi guys, >> >> I'm trying to simulate a block-based design with Altera's Quartus II >> V3.0 Web version, however I cannot seem to simulate beyond 100ns >> irrespective of what end points I set for the default and for the >> current project. >> >> I've also tried editing the vector waveform file timing parameters >> after generation and Quartus disregards these and ends the simualtion >> at 100ns. It seems far too controlled to be a bug so I can only >> assume its a limitation of the free version. Can anyone confirm this? >> >> If it is a limitation of the free version are there any *reliable* >> third party simulators for reasonable money? I'm sitting on my hands >> as far as this project goes until I resolve this. >> >> Kindest regards, >> Chris Bailes >> (Design Engineer, Studio Systems Electronics LTD). > >Hi Chris, > > There is no limit on the Simulation End Time in Quartus II 3.0 Web >Edition product. Please make sure you do the following: > >1. Open the waveform editor on your channel and use the Edit->End Time >command to set the end time correctly. >2. Use the Assignment->Settings command and then choose Simulator >Settings->Time/Vectors. Set the Simulation Period to Run Simulation >until all vector stimuli are used. > >- Subroto Datta >Altera Corp. Hi , is there a detailed list of the differences between the free web Quartus and the paid version ... I have not been able to find this ... it seems it must be available since Altera wants to sell the full version ... thanks for any help ... CBArticle: 59281
Hi Jon, Jon Masters wrote: > Hi, > > I have integrated various patches and the Xuartlite driver from John > Williams to get kernel 2.4.20 up and running on the development board. Good work! Glad the driver is useful - let me know if you find any bugs or improvements. > Although I have now done this I am interested to hear official board > support status from others. I have yet to hear back from Mind. Along this line - could you (or anybody else) maybe give us a run-down of the status of the various linux ports for the V2Pro PPC devices? I'm aware of the MontaVista commercial port, but am unsure about costs and licensing and access and so on. Someone suggested to me recently that the MontaVista V2Pro dev. env. was big $$$. Is it possible to work around this using free tools and so on? Then there's this "Mind" group you mention, what's that all about? I guess the reason I ask is that these "fringe ports" seem to languish outside the mainstream for a long time, making it difficult for people to pick them up and get started. For example, the NIOS port of uClinux was done 2 or 3 years ago, but even now is not fully integrated into the "official" uClinux source tree[1]. Further, the extent to which it is there seems mostly due to efforts by the uClinux maintainers, rather than Altera or Microtronix. I suppose you need some passionate users who are prepared to do the legwork to get this stuff integrated. Cheers, John [1] I'm doing my best to ensure that uclinux on microblaze doesn't suffer the same fate!Article: 59282
Hi Ken, > I'm new to the processor on FPGA world (been using Coldfire) and was only > lightly involved with the FPGA stuff on our previous designs. (added a > few features and fixed a few bugs in an Altera 7000MAX) > > Anyway, my question concerns your statement about "in the rest of the > FPGA". My understanding is/was that FPGA logic that is not specifically > tied to > together in the FPGA runs independently. For example I assume that I can > have two (or more) Nios processors running completely independently on the > same FPGA with little effect unless I choose to tie their logic together. You're absolutely right. The Cyclone devices allow you to have a comfortable number of separate clock trees (12, I remember from one device, maybe more). The Stratix devices even more. Indeed, if you don't have any communication between the separate NIOS cores, these could run at any supported speed. One could run at 50 MHz, and the other could run at 13.3333MHz. Or somesuch. As soon as these two (or more) of these need to communicate you're slightly f*cked because you'll need to write synchronization logic, but that would be the case with any design that has to cross clock boundaries. Then again, I've written some code that ties a 16MHz SJA1000 Can controller to a 50MHz NIOS CPU core. Both designs are externally clocked separately. It wasn't trivial, but not more than a day and a half of work (given a decent PC). It's not that hard. Best regards, BenArticle: 59283
Hi, I could use some help finding an eval/proto-board. I'm having trouble finding a board with multiple DDR SDRAM banks (3+) connected to a VirtexII with 1M+ system gates. The closest board I can find is the Sundance Multiprocessor Technology SMT351, which has 4 banks but no DDR (an inadequate data rate). Any leads? Thanks for any help you can lend.Article: 59284
[Please pardon an intrusion from a really casual FPGA/CPLD user] I have a collection of old Xilinx parts. XC2018, XC3020, XC3030, XC3064, XC4004A. I gave up years ago trying to find software for the XC2018 parts. But I assumed my software would do the XC30xx and XC40xx when I got around to using them. Now I notice that the Xilinx web page doesn't have spec sheets for the base XC30xx and XC40xx or XC40xxA parts. I also notice that me oldest software, Foundation Base 1.4 is too new to include these parts. (after casual browsing through Foundation Base 1.4, WebPack 4.2, WebPack 5.1i, Student 2.1i) So, my question is, am I missing someting? Or do I just need older software? Can I use XC3030A to create code for a XC3030? I'm guessing that I can't. What about the XC4004A? Can I use XC4003E or XC4003XL to create code for the XC4004A? I'm guessing not. If I need older software, does anyone have any old software they want to part with? I'm guessing old software falls into 3 catagories: 1. Better keep it in case we have to update this old stuff. 2. It is still here on the shelf because I couldn't bear to throw it away. 3. Threw it away years ago. Or should I just throw these old parts away and get some Spartan ot Virtex parts? -- Jeff Sampson http://tcrobots.org/members/jsamp.htmArticle: 59285
Hi all, I only have used xc9500 and coolrunnerII before, and we all know such CPLDs has so little FF resources. For my current applications I need to map some memorys and I think ispXPLD is what I'm looking for. But before I start my work on it, I'd like make something clear: 1.It sounds great that ispXPLD has plennty of memory resources, and that's what I want most. So what's the payoff compared with common CPLDs, cost? performance? 2.ispXPLD has a new architecture MFB which I'm not familiar with. From a designer's point of view, is there any difference between XPLD and CPLD? Do I need extra knowledges or skills? Thanks.Article: 59286
large devices multi platform support: windows,unix,linux "CB" <charleybrant@hotmail.com> wrote in message news:3f3aba54.6259646@news.compuserve.com... > On 13 Aug 2003 15:13:57 -0700, sdatta@altera.com (Subroto Datta) > wrote: > > >chris.bailes@myrealbox.com (Chris) wrote in message news:<bc923adb.0308130056.50b1f5b@posting.google.com>... > >> Hi guys, > >> > >> I'm trying to simulate a block-based design with Altera's Quartus II > >> V3.0 Web version, however I cannot seem to simulate beyond 100ns > >> irrespective of what end points I set for the default and for the > >> current project. > >> > >> I've also tried editing the vector waveform file timing parameters > >> after generation and Quartus disregards these and ends the simualtion > >> at 100ns. It seems far too controlled to be a bug so I can only > >> assume its a limitation of the free version. Can anyone confirm this? > >> > >> If it is a limitation of the free version are there any *reliable* > >> third party simulators for reasonable money? I'm sitting on my hands > >> as far as this project goes until I resolve this. > >> > >> Kindest regards, > >> Chris Bailes > >> (Design Engineer, Studio Systems Electronics LTD). > > > >Hi Chris, > > > > There is no limit on the Simulation End Time in Quartus II 3.0 Web > >Edition product. Please make sure you do the following: > > > >1. Open the waveform editor on your channel and use the Edit->End Time > >command to set the end time correctly. > >2. Use the Assignment->Settings command and then choose Simulator > >Settings->Time/Vectors. Set the Simulation Period to Run Simulation > >until all vector stimuli are used. > > > >- Subroto Datta > >Altera Corp. > > Hi , is there a detailed list of the differences between the free web > Quartus and the paid version ... I have not been able to find this ... > it seems it must be available since Altera wants to sell the full > version ... thanks for any help ... CB > > >Article: 59287
On Tue, 6 May 2003 14:50:23 +0400, "Mikhail" <kostkin@asicdesign.ru> wrote: >Could anyone recommend me flash-disk with IDE/ATA for "extremal" >application? Try <<http://www.adtron.com>>. They have both SCSI and ATA interfaces. KevinArticle: 59288
I am using VHDL and a Spartan IIe to receive clocked data. The setup and hold timing between clock and data signals is very tight (like 5ns), so I would like to force the IOB latch to capture the data. The input clock is asynchronous to my system clocks, and I can build a pipelined synchronizer to shift the clock domains, but I do not want to dedicate a global clock to this input signal (in some of my systems I might have 5 of these inputs, and there are not enough global clocks to go around). The data clock is about 1/4 the frequency of my system clock. Is there a way to instantiate an IOB as a VHDL "object" (macro?), and explicitly hook the IOB clock to the input clock signal, instead of using a global clock? In other words, I would like to have a black box which is the IOB, and not have to use "dataClock'event" in the VHDL. I am using Xilinx tools. Or is there another way to do this? KevinArticle: 59289
Can anyone tell me how the memory map in the Altera NIOS works (in software-C and hardware-VHDL)? I am not sure how the layout is and where to read and write data to user logic.Article: 59290
The FPGAs I have worked and do work with do not allow for a dual edged CLK.
Assuming your does and /or assuming the
synthesizer does some neat trick to allow this for your FPGA, maybe you
could specifiy rising clock edge if in the layer above
this entity, you had a faster clock divide by 2 to make this clock that you
are using here. I dont' know if that is a possibility, but
I do remember running into some odd synthesis problems once trying to make a
dual edged clock.
Also, it has been my experience to 'not' do a divided clock by using one of
the bits, but rather to use it as an enable to drive
something maintaining sync with the one and only true clock.
PROCESS abc (CLK, RESET) BEGIN
DIV_2_EN <= COUNTER(2); -- pick the bit off you want to use
DIV_2_EN_R <= DIV_2_EN; -- make another signal delayed by one (true) clk
value
END PROCESS abc
--outside of the CLK do this:
DIV2CLK <= '1' when DIV_2_EN ='1' and DIV_2_EN_R = '0' else '0'; -- this is
not a 50% duty cycle clock, but it has the correct freq. of CLK/2
-Kip
"Thomas" <tom3@_nostupidspam_protectedfromreality.com> wrote in message
news:oprtseo3y9g7nu3h@news3.news.adelphia.net...
>
>
> Completed process "Generate Post-Translate Simulation Model".
>
> ERROR: Hidden remap failed
> Reason:
>
> Launching Application for process "Simulate Post-Translate VHDL Model".
>
>
>
> not only the software's stupid enough to launch the GUI after the error,
> but there is not a single entry about this error in the xilinx database,
on
> the modelsim server or even in google (but me complaining about the same
> problem a month ago)
> The 'reason' field is as useful as usual :) this time they just didn't
> bother typing a message that makes no sense, they just left it empty.
>
> here's the code:
>
> process(Reset, MasterClock) is
> variable counter : std_logic_vector(2 downto 0);
> begin
> if(Reset = '1') then
> counter := "000";
> elsif(rising_edge(MasterClock)) then
> dividedclock <= counter(2);
> counter := counter + 1;
> end if;
> end process;
>
> so, all the calls to modelsim, regardless of the type (post translate,
post
> map, etc) fail the same way.
>
> then 'generated expected simulation results' yields another interesting
> problem:
>
> if, in the timing constraints, I select the clock to be rising edge only,
> it works; if I pick dual edge, it just 'skips' cycles every 30 or so in
the
> display and everything gets out of sync...
>
> Any ideas?
Article: 59291John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<bhefdn$q8g$1@bunyip.cc.uq.edu.au>... > Hi Jon, > > Jon Masters wrote: > > Hi, > > > > I have integrated various patches and the Xuartlite driver from John > > Williams to get kernel 2.4.20 up and running on the development board. [] > Along this line - could you (or anybody else) maybe give us a run-down > of the status of the various linux ports for the V2Pro PPC devices? I'm > aware of the MontaVista commercial port, but am unsure about costs and > licensing and access and so on. Someone suggested to me recently that > the MontaVista V2Pro dev. env. was big $$$. Is it possible to work > around this using free tools and so on? [] > Cheers, > > John Hi Jon and John, I also wanted to ask for clarification, because there is uLinux MB and ?? Linux for PPC V2Pro, I only guess that Jon referred a real PPC linux, not uLinux for MB running in V2Pro. as for Linux V2Pro - ELDK has been reported to work on V2Pro devices so a free linux for V2Pro already exists and has been verified on real V2Pro development boards. This report was from some avnet guy so his work is not public ASFAIK, but already the info that ELDK works on V2Pro (or is easy to get working) should help. I have only used ELDK to write some Hello.c applications and have run them in Mvista on ML300, so have not attempted kernel compile or boot image creation. anttiArticle: 59292
Antti Lukats wrote: > I also wanted to ask for clarification, because there is uLinux MB > and ?? Linux for PPC V2Pro, > I only guess that Jon referred a real PPC > linux, not uLinux for MB running in V2Pro. I share your interpretation! :) > as for Linux V2Pro - ELDK has been reported to work on V2Pro devices so > a free linux for V2Pro already exists and has been verified on real > V2Pro development boards. This report was from some avnet guy so his > work is not public ASFAIK, but already the info that ELDK works on V2Pro > (or is easy to get working) should help. Sounds good. Cheers, JohnArticle: 59293
I am looking at very helpful documents at http://www.xess.com/index.html regarding the use of a Spartan XCS10 frga chip on XS series boards from XESS corporation. I am using the Digilent XLA board with same chip. Can anyone telling me if there is significant difference. I want to know if I should persist with this helpful site to learn more about the about the board we use at college (XLA Digilent). Regards Dave (A subject would have helped - doh)Article: 59294
Hi Clay, Not at all. You just need to add more stages. My first patent on this is US5528736. The following patent number is to be issued within three months. If you are interested in more details, please send me an e-mail. Regards, Seung "Clay S. Turner" <physicsNOOOOSPPPPAMMMM@bellsouth.net> wrote in message news:<sVw_a.7804$_3.5732@fe02.atl2.webusenet.com>... > Hello Seung, > > If you have 100% hardware utilization, doesn't this present a problem if you > make a change to the design?? > > Curious what is the # for your patent?? > > Clay > > > > > "Seung" <kim.seung@sbcglobal.net> wrote in message > news:fdf92243.0308131136.74aff961@posting.google.com... > > Hello > > > > I have a patent and recently added one more on innovative FFT > > algorithm and architecture. > > If you're a business minded expert on FPGA with interests in DSP, this > > is a great opportunity. Our FFT is 'the' optimal HW solution as > > follows: > > > > 1. Minimum HW complexity: 100% HW utilization > > 2. Suitable for super fast pipelined FFT: only local data flow - not > > based on butterfly algorithm > > 3. Minimum clock cycles: baseline architecture needs N clock for > > N-point FFT > > 4. Scalable to arbitrary large FFT size > > 5. Multi-dimension extension: world's first 'intrinsic' > > multi-dimensional FFT algorithm & architecture (not relay on 1-D FFTs) > > : great for 2-D/3-D real-time medical imaging, SAR, etc. > > > > If you're interested in building a business together based on this > > innovation, > > please contact me with your resume. It'll be ideal if you have > > contacts for potential customers. > > > > Any help on this matter from FPGA/DSP group members will be > > appreciated. > > > > > > Thanks. > > > > Seung P. Kim, Ph.D > > Silicon Computing, Inc. > > Mountain View, CAArticle: 59295
sarahshen2003@yahoo.ca (sarah) wrote: > I have a problem when implementing PCI in Acte;l APA300. Does anybody > know the very datailed information about ACTEL cORE pci? Could you be more precise? The Actel PCI-core is very complex and supports different modi, maybe I could help you for simple questions, Actel support might also help.Article: 59296
Hi, Considering your answer does it imply that the chip (xc2v6000-5) is not fast enough for a 450 ps skew on the clock to be a problem ? J.F. Hasson Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F3AAE78.AF5F5717@xilinx.com>... > J.F., > > The report by the tools is correct. > > Different sized parts will have different skews (delays) in the their clock > trees due to size. > > Additionally, skew is a function of position on the tree, so from the top left > corner down to the middle of a part all the way to the bottom left corner, the > skew will be less than 130 ps for a 2V6000, wheras from the top left corner over > towards the top middle over to the right corner, it will be about 450 ps for a > 2V6000. > > Top to bottom: 130 ps. Right to left: 450 ps. Smallest in the middles, largest > at the corners. > > For a 2V1000, these are all less than 100 ps. > > Thus if you wanted to make the highest speed wide parallel interface, I would > use the left or right sides (least skew), rather than the top or bottom edges > (for least skew between bits). > > If I had to use the top or bottom edges, I would try to group the IOs near the > center, or near the left and right extremes. > > Again the timing reports and FPGA_Editor report the right (worst case) numbers. > > Hope this helps, > > Austin > > jean-francois hasson wrote: > > > Hi, > > > > I am working on a design involving a virtex II -5. I read in a previous post > > that the skew one could expect from a clock tree is less than 100 ps. > > However when, on the design I am developping, I run the timing analyzer I > > get a skew for some clock on a clock tree of about 450 ps or 500 ps (using > > the 5.1i F23). How should I interpret this difference ? Any clue ? Which > > figure is the right one ? > > > > J.F. HassonArticle: 59297
Hi all, I am going to synthesize a large VHDL design (using Quartus II v. 2.2 + SP 2), composed by several modules (over 10), so I decided to follow LogicLock methodology. Each sub module has a hierachical structure, and some of theme instantiate ram/rom blocks. My aim is to compile each module and assign it to a fixed-size floating LogicLock region. After each module compiles properly and meets timing requirements I can export LogicLock region (.vqm and .esf files) to the top level project. In the top level project I have one VHDL file wich instantiates entities I assigned to LogicLock regions, and .vqm files (one for each entity). After importing LogicLock regions I can compile the top level file. I am new to LogicLock and I have several doubts: a. Could anyone confirm me if this approach is correct? b. Which are the most critical issues to compile a design following a LogicLock metholody? Thanks in advance, AndreaArticle: 59298
Hi Andrea, > ... > > I am new to LogicLock and I have several doubts: > a. Could anyone confirm me if this approach is correct? > b. Which are the most critical issues to compile a design following a > LogicLock metholody? Generally speaking, you want to make your life as a easy as possible. This means sticking to a flat push-button compile if it achieves your desired results. If doing so hits your timing requirements, then you're done. If you are having trouble hitting timing, LogicLock is one of a number of tools at your disposal to help you converge on better results, particularly in highly regular or data-path designs where providing strong hints to the fitter will help most. LogicLock is particularly useful when trying the eek the last bit of timing out of IO paths -- you can constrain an IO to a particular set of IOs, or make sure logic related to that IO is place (for example) within 4 LABs of it, etc. In Stratix/Cyclone, LogicLock doesn't often give big wins vs. push-button compile, as it's not that easy for a human to figure out the best approximate placement for a design. Even though your design logically has 10 modules, the best possible placement doesn't necessarily have each of the 10 modules placed as a clump. Your critical path may hop through the various modules, and that path may need to be crunched together while the rest of the logic doesn't really care to much about being pulled apart. In APEX-like families, LogicLock can get bigger wins as there are very clear boundaries where timing goes from good to bad, and a human can often figure out a good floorplan for a design. For example, ensuring that local logic stays within a MegaLAB. Application note AN297: Optimizing FPGA Performance Using the Quartus II Software (http://www.altera.com/literature/an/an297.pdf) provide further information on achieving desired fitting and performance in your design, including which steps to take first in increasing order of manual effort vs. potential reward. Application note AN161: Using the LogicLock Methodology in the Quartus II Software (http://www.altera.com/literature/an/an161.pdf) provides further information on LogicLock in particular. One feature that is particularly neat if you choose to go this route is the timing-closure floorplan. This shows you a delay map of the device, which is important for deciding how to constrain your logic for performance. One of the first things we do when a user sends in a design that is having trouble hitting timing is remove all location constraints and LogicLock regions from the design and go push the button. And this is often enough! Regards, Paul Leventis Altera Corp.Article: 59299
Hi I do answer mostly, but maybe I get some answer when I need some too problem Actel Libero (latest version) all installed, synplify/actel installed but when I launch synplify the "Run" button is disabled (also menu) menu "Compile only" is enabled but doesnt do anything :( licensing seems to be OK. and I have tried RTFM, but it all tells you what todo [when Run is enabled] its probably some real silly problem, but nowhere to look :( tnx antti
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