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Messages from 72150

Article: 72150
Subject: Re: LEGO mindstorms and FPGA
From: "Kelvin" <kelvin_xq@yahoo.com>
Date: Tue, 10 Aug 2004 09:49:10 +0800
Links: << >>  << T >>  << A >>
Martin, are you willing to share your Java processor codes? Got any website
on that?

Kelvin





"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message
news:z3uRc.57103$M72.9272@news.chello.at...
> > It depends how far you want to go w/ your robot. One of the LEGO
> > extension sets includes a Logitech USB Camera. Unfortunately, the
> camera
> > is connected to the PC via the USB cable (limiting the movemens of your
> > robot), then few pieces of information are sent back to the RCX for
> > robot control.
>
> Yes a camera module on the robot would be nice. I have a simple digital
> module (M4088 with OmniVision's image sensor OV5017) that I wanted to
> connect to the FPGA some time ago. I will probably do it now for the LEGO
> robot ;-)
>
> >
> > We can't call really it an autonomous agent, can't we? It would be a
> > better idea to handle the camera directly from the robot itself. You
> > would need a processor to handle the USB protocol stack, but an FPGA
> > would be nice to compute in real-time the images that you capture in
> > order to improve the robot capability to react to what it sees.
>
> The camera module I mentioned is far simpler to connect. You don't need
> an USB stack, just digital signals.
> >
> > In such a case, the processor would indeed offer more flexibility but
> > wouldn't be able to compute the huge amount of data so effiently.
> > Therefore, an approach incl. a processor + an FPGA would be nice.
> >
>
> As processor I will use my Java processor inside the FPGA, but the NIOS
> would also be fine.
>
> Martin
>
>
>



Article: 72151
Subject: Re: Carbon nanotubes
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Tue, 10 Aug 2004 02:48:46 GMT
Links: << >>  << T >>  << A >>
> Cavendish Kinetics is introducing its cantilevered-beam approach

I emailed them today.  I'll be in Amsterdam next month and might have an
opportunity to visit.  Sounds interesting.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



Article: 72152
Subject: Re: Now I am really confused!
From: "Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca>
Date: Tue, 10 Aug 2004 03:18:20 GMT
Links: << >>  << T >>  << A >>
> In the meantime, Altera has jumped on this bandwagon and they multiply
their
> ALE numbers by 1.25.

Jumping to our defense on this one, we clearly state the number of Adaptive
Logic Modules (ALMs) in our Stratix II literature, and a give a separate
"Equivalent Logic Element" count.  We use 2.5 LEs per ALM to provide our
customers with a way to easily compare the logic capacity of Stratix and
Stratix II devices.  This is not smoke and mirrors -- the Stratix II ALM is
a radically different logic structure.  The number of ALMs/LE will differ
from design to design, but over 100+ user designs we found that 2.5 was a
reasonable estimate.

Regards,

Paul Leventis
Altera Corp.





Article: 72153
Subject: Re: Altera Bidi ports, Tristate Buffers & Prop. Delay?
From: vbetz@altera.com (Vaughn Betz)
Date: 9 Aug 2004 21:09:42 -0700
Links: << >>  << T >>  << A >>
pinod01@sympatico.ca (Pino) wrote in message news:<b7ed9648.0408061906.79dd84ab@posting.google.com>...
> pinod01@sympatico.ca (Pino) wrote in message news:<b7ed9648.0407312040.783610f9@posting.google.com>...
> > mikeandmax@aol.com (Mikeandmax) wrote in message news:<20040730131548.23098.00002650@mb-m07.aol.com>...
> > > >
> > > >   I've discovered that there is some significant propagation delay
> > > >between the input and bidirectional pin & bidirectional pin to output
> > > >pin in my simulation.  I've compared the function LPM_BUSTRI within
> > > >Quartus, a construction made up from Tri-state buffers within Quartus
> > > 
> > > often prop delays in a tristate pin are due to OE performance - have you looked
> > > at the OE timinng numbers, or are you indeed looking at the prop delay of the
> > > in or out buffer.  Most modern FPGAs now have syncronous OE and data registers
> > > at the pin, which can give you much better timing through the I/O.
> > > 
> > > Mike Thomas
> > > Lattice fae
> > 
> > Thanks for the update on where to start looking.  After reading
> > further the specificatios in the delays within the Stratix IOE
> > structure, I've managed to compute the internal timing and external
> > timing for a given drive strength at the output for a bidirectional
> > pin:
> > 
> > Internal Timing:
> > =================
> > total prop. delay  = ip/op register clock-to-output delay + IOE data
> > input to combinatorial output + setup time + hold time + routing delay
> > 
> > In equation form I have this as:
> > 
> > tpd1 = tco_c + tpcombin2pin_c + tsu + th + tlocal
> > tpd1 = 0.171 + 3.357 + 0.080 + 0.068 + 0.345
> > tpd1 = 4.021 ns
> > 
> > External Timing (4mA drive strength LVTTL) :
> > ==========================================
> > 
> > total prop. delay = Setup time for bidi pin using column IOE registers
> > + Hold Time for bidi pin using column IOE registers + Clock-to-Output
> > Delay Bidi pin using column IOE registers
> > 
> > In equation form I have this as:
> > 
> > tpd2 = tinsu + tinh + toutco
> > tpd2 = 2.33 + 0 + 4.922
> > tpd2 = 7.252 ns
> > 
> > ** Hopefully I interpreted the specifications correctly?
> > 
> > If my interpretation is correct, the issue I have now is that I'm not
> > sure if I should take total prop. delay = tpd1 + tpd2 = 11.273 ns?  
> > Does anyone know if this is the correct thing to do?
> > 
> > My reasoning for combining both is that the internal one relates to
> > the IOE internal timing & the external timing is associated directly
> > to the output bidirectional pin.
> > 
> > Regards,
> > Pino

Hi Pino,

The equations above look wrong to me.  

It looks like what you're most worried about is the Tco of the output.
 That is given in the Stratix datasheet at
http://www.altera.com/literature/hb/stx/ch_4_vol_1.pdf

The parameter you want is Toutco.  Its precise value depends on:

1. The device you are using (e.g. 1S10 vs. 1S80)
2. The speed grade
3. Whether you are using a PLL or not.
4. What kind of global network you are using (if you're not using a
PLL).
5. The capacitive load on the IO (this is only an approximation of the
true board delay; better accuracy requires that you actually simulate
your board).
6. The IO standard, drive strength and slew rate you use.

Assuming you want an LVTTL IO, driving a 10 pF load, using fast slew
rate, and a 24 mA drive strength (this is the default IO setup), and
are using a global clock with no PLL:

Toutco = 4.71 ns in a 1S10 -5
Toutco = 5.777 ns in a 1S80 -5

If you use a 4 mA drive strength add 570 ps to the numbers above.

If you use a PLL, things speed up by approximately 3 ns.

While you can use the datasheet to answer these questions, I think
you'll find it easier to just do simple sample designs in Quartus and
look at the timing you achieve rather than doing manual timing
analysis of various timing paths.  The calculation I did above was
just the Tco of the output (generally the most challenging timing
parameter for this kind of design).  To see the delays of paths into
the IO input register and within the FPGA, it is easiest to just use
Quartus rather than trying to add all the right numbers from the
datasheet.

You can grab a free version from
https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp

Vaughn
Altera

Article: 72154
Subject: Newbie Xilinx Question: How to keep past designs?
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Mon, 9 Aug 2004 21:39:30 -0700
Links: << >>  << T >>  << A >>
So you have a pretty good design and you want to save it, start another
design. How to do that?  I clicked on New Design, new directory, went thru
the wizard, pasted the source form the old design into the new, (perhaps the
name should be something generic like mydesign and the design name or idea
is reflected in the directory), pasted the old constraint file into the new
constraint file, (is there anything else?), and started anew.  Is there a
faster way of doing this?



Article: 72155
Subject: Re: propagation delay
From: "Shahab47" <sinamdar@mail.usf.edu>
Date: Tue, 10 Aug 2004 00:47:01 -0400
Links: << >>  << T >>  << A >>
Chris.

I would love to do that...but actually i m in the middle of a comparative
study between altera maxplus2 and xilinx ise webpack....and i need to
compare these two softwares...so ihave to find a way in maxplus2 only...

can u provide me with some tip ?

thanks 
shahab


Article: 72156
Subject: Sync data between two clock domains
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Mon, 9 Aug 2004 21:47:27 -0700
Links: << >>  << T >>  << A >>
So how does one sync data between two non-synchonous clock domains?  Seems
like the domain accepting the data needs to turn off the clock of the
originating domain fopr at least one clock cycle.  How does one express that
in VHDL?




Article: 72157
Subject: Re: Sync data between two clock domains
From: hmurray@suespammers.org (Hal Murray)
Date: Tue, 10 Aug 2004 00:21:17 -0500
Links: << >>  << T >>  << A >>
>So how does one sync data between two non-synchonous clock domains?

Carefully.  google for metastability and/or check the FAQ.

>                                                                Seems
>like the domain accepting the data needs to turn off the clock of the
>originating domain fopr at least one clock cycle.  How does one express that
>in VHDL?

Turning off a clock from another clock domain has metastability
problems all by itself.


What sort of "data" are you interested in?

If it's just a single bit/flag, the usual approach is a pair of FFs
on the receiving clock.

If it's something like a packet, the usual approach is to use
a FIFO.  The Empty/Full (or almostEmpty) flags have to cross the
clock barrier.  See above, or hope the people who designed the FIFO
covered this case.

If it's just a single word of data, you can build your own FIFO
that's only 1 word deep.


-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 72158
Subject: XC4010E/XC2V1000 problem
From: my_free_em@msn.com (Peter Chen)
Date: 9 Aug 2004 22:25:41 -0700
Links: << >>  << T >>  << A >>
 I'm using Xilinx ISE4.1i schematic entry.  The target device is
XC4010E.  In my design, there are several independent parts ( macro
symbols ).  When I modified one symbol's logic ( add or delete some
gates/flip-flops ),  other symbols' outputs changed.  This problem
occurs frequently.  Someone tell me that reducing the used resource
will be OK.  So I download the design to XC2V1000 ( the used slices
are 1%), but the problem still exists.   Why  small changes can affect
other parts?  I can't figure it out.  Please help me. 

Article: 72159
Subject: Re: Now I am really confused!
From: Nicolas Matringe <nicolasmatringe001@numeri-cable.fr>
Date: Tue, 10 Aug 2004 08:19:32 +0200
Links: << >>  << T >>  << A >>
John_H a écrit:
> Oh... and remember years ago when Brand A illustrated 3 registers in their
> I/Os?

I do!
I'm still angry with them about that one (though they actually put 3 
registers in their latest chips)

-- 
  ____  _  __  ___
|  _  \_)/ _|/ _ \   Adresse de retour invalide: retirez le -
| | | | | (_| |_| |  Invalid return address: remove the -
|_| |_|_|\__|\___/


Article: 72160
Subject: Re: FAE Job opening
From: David <david@fpgaworld.com>
Date: Tue, 10 Aug 2004 02:28:30 -0700
Links: << >>  << T >>  << A >>
You can also post these kind of messages in the FPGAworld forum... 
www.FPGAworld.com 



Article: 72161
Subject: Re: Available: Open Source VHDL parser - for free
From: David <david@fpgaworld.com>
Date: Tue, 10 Aug 2004 02:35:34 -0700
Links: << >>  << T >>  << A >>
Maybe, we can add it to the 'Downloads' section at FPGAworld.com??



Article: 72162
Subject: Re: LEGO mindstorms and FPGA
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Tue, 10 Aug 2004 11:02:57 GMT
Links: << >>  << T >>  << A >>
Kelvin,

do you mean the processor itself or the Java code for the Lego robots?
The Java processor is available in VHDL at: http://www.jopdesign.com/

For the robot stuff I just started to build the interface to the sensors.
I have only a three liner in Java to read out the values, but I will put
the schematics and VHDL source on a webpage.

Martin

> Martin, are you willing to share your Java processor codes? Got any
website
> on that?
>
> Kelvin
>
>
>
>
>
> "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message
> news:z3uRc.57103$M72.9272@news.chello.at...
> > > It depends how far you want to go w/ your robot. One of the LEGO
> > > extension sets includes a Logitech USB Camera. Unfortunately, the
> > camera
> > > is connected to the PC via the USB cable (limiting the movemens of
your
> > > robot), then few pieces of information are sent back to the RCX for
> > > robot control.
> >
> > Yes a camera module on the robot would be nice. I have a simple
digital
> > module (M4088 with OmniVision's image sensor OV5017) that I wanted to
> > connect to the FPGA some time ago. I will probably do it now for the
LEGO
> > robot ;-)
> >
> > >
> > > We can't call really it an autonomous agent, can't we? It would be
a
> > > better idea to handle the camera directly from the robot itself.
You
> > > would need a processor to handle the USB protocol stack, but an
FPGA
> > > would be nice to compute in real-time the images that you capture
in
> > > order to improve the robot capability to react to what it sees.
> >
> > The camera module I mentioned is far simpler to connect. You don't
need
> > an USB stack, just digital signals.
> > >
> > > In such a case, the processor would indeed offer more flexibility
but
> > > wouldn't be able to compute the huge amount of data so effiently.
> > > Therefore, an approach incl. a processor + an FPGA would be nice.
> > >
> >
> > As processor I will use my Java processor inside the FPGA, but the
NIOS
> > would also be fine.
> >
> > Martin
> >
> >
> >
>
>



Article: 72163
Subject: Help wanted for ethernet on xilinx fpga Virtex2 multimedia demonstration board
From: ashishjindal76@yahoo.com (Ashish)
Date: 10 Aug 2004 04:57:34 -0700
Links: << >>  << T >>  << A >>
Hi all

I want to transfer the data feom the kit to the  PC using the 10/100
ethernet. Can any one tell me how it can be done and what are the
things required for that? how to configure that. I have an ethernet
lite IP core supplied by the Xilinx. If any one has some sample
regarding that It would be highly appriciated.

thanks in advance.

regards
Ashish

Article: 72164
Subject: let me have logic design for traffic light
From: byseid@yahoo.com
Date: 10 Aug 2004 05:07:08 -0700
Links: << >>  << T >>  << A >>
I am not new for logic design but I need help for designing a
sequential Logic circuit analysis and design.
I want to design a traffic light controller for crossroad(of four
direction) the controller at each direction say A,B,C,D detects the
number of cars on each then the line having more cars will get the
priority... for more details please mail me <byseid@yahoo.com>.

Article: 72165
Subject: Spartan III I/O robustness
From: lecroy7200@chek.com (lecroy)
Date: 10 Aug 2004 05:54:28 -0700
Links: << >>  << T >>  << A >>
I was not able to find a way to continue the old thread (too old??),
but my basic question was:

> I have spent the last 60 days trying to get an answer from Xilinx on
> their new S3 devices.  During a review, it was stated that the new S3s
> were very sensitive to transients on the I/O pins. Because they made a
> point to mention this during the review, I posed the following
> question to Xilinx:
>
> "If we look at the incident versus reflected energy and tune the stub
> (trace)
> for a worst case match is it possible the driver could be damaged or
> the
> chip lock up due to the reflected energy?"
>
> "The circuit would be as follows:
> Spartan III    Output  ------------------------------ Tunable Stub"
>
> I wonder if anyone in this group has asked this question and what was
> the responce from Xilinx?


Just do a search for reflected in the comp.arch.fpga group and you
should find the entire thread, or try:

http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&th=49df88f46d6fa0ff&rnum=2


I just got this information that may be of interest to some of you.  

>Subject: Spartan 3E / 4 information
>Apparently the problem with past parts was that the I/O was really
2.5V so when >boosting up to 3.3 already took away most of the
overshoot window.  This new
>revision should correct this. I believe this is preliminary info, but
yes this >is meant to resolve the reflected signal issue.  Apparently
this issue is also >in other parts, I believe the Virtex II.


What I find interesting is that after all the feedback from Xilinx on
this subject that they may change the technology to address this
concern.

Article: 72166
Subject: Re: LEGO mindstorms and FPGA
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Tue, 10 Aug 2004 13:09:02 GMT
Links: << >>  << T >>  << A >>
> days...). After building the first robot, I want to substitue the RCX
by
> an FPGA. Has anyone done this so far?
>

The LEGO sensor interface to the FPGA with a sigma-delta ADC is
completed. I've set up a web page with the schematic and the VHDL code:
http://www.jopdesign.com/lego/index.jsp

The motor control, camera input and hopefully a nice roboter example will
follow.

Comments and suggestions on this solution are welcome ;-)

Martin



Article: 72167
Subject: Re: Altera winner?
From: "Captain Bly" <Bobcrap@aol.com>
Date: Tue, 10 Aug 2004 13:15:10 GMT
Links: << >>  << T >>  << A >>
I got a tee shirt, I could only assume it's someone that works for Altera

"Jerry" <nospam@nowhere.com> wrote in message
news:10hg4i8oulqp5af@corp.supernews.com...
> Does anyone know who won the camera from Altera on that Cyclone 2 web
> presentation?
>
>
>



Article: 72168
Subject: Re: Now I am really confused!
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 10 Aug 2004 09:20:38 -0400
Links: << >>  << T >>  << A >>
"Paul Leventis (at home)" wrote:
> 
> > In the meantime, Altera has jumped on this bandwagon and they multiply
> their
> > ALE numbers by 1.25.
> 
> Jumping to our defense on this one, we clearly state the number of Adaptive
> Logic Modules (ALMs) in our Stratix II literature, and a give a separate
> "Equivalent Logic Element" count.  We use 2.5 LEs per ALM to provide our
> customers with a way to easily compare the logic capacity of Stratix and
> Stratix II devices.  This is not smoke and mirrors -- the Stratix II ALM is
> a radically different logic structure.  The number of ALMs/LE will differ
> from design to design, but over 100+ user designs we found that 2.5 was a
> reasonable estimate.

I'm not trying to take sides in this, but my original post was about how
the data sheet defined "Logic Cells" one way and then counted them
another.  If the data sheet clearly says that the numbers are "adjusted"
with some fudge factor, that is not so big a deal.  But if you define an
LC one way and count it another, that is just not honest.  

Every FPGA has extras in them which extend the capacity of the LUTs. 
But when I am trying to count LUTs in my block diagram to see how large
a part I will need, I already have all the "fudge factors" I can handle,
I don't need more from the data sheets! 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 72169
Subject: Re: let me have logic design for traffic light
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 10 Aug 2004 09:25:47 -0400
Links: << >>  << T >>  << A >>
byseid@yahoo.com wrote:
> 
> I am not new for logic design but I need help for designing a
> sequential Logic circuit analysis and design.
> I want to design a traffic light controller for crossroad(of four
> direction) the controller at each direction say A,B,C,D detects the
> number of cars on each then the line having more cars will get the
> priority... for more details please mail me <byseid@yahoo.com>.

I would love to help you with your homework.  Please contact me at the
phone number below and you can open an account for consulting services. 
I would be happy to teach you all you need for this problem.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 72170
Subject: Re: let me have logic design for traffic light
From: "Gregory C. Read" <readgc.invalid@hotmail.com.invalid>
Date: Tue, 10 Aug 2004 13:40:39 GMT
Links: << >>  << T >>  << A >>
How much are you willing to pay for someone to do your homework?

-- 
Greg
readgc.invalid@hotmail.com.invalid
(Remove the '.invalid' twice to send Email)


<byseid@yahoo.com> wrote in message
news:783d4d57.0408100407.68f1d8f6@posting.google.com...
> I am not new for logic design but I need help for designing a
> sequential Logic circuit analysis and design.
> I want to design a traffic light controller for crossroad(of four
> direction) the controller at each direction say A,B,C,D detects the
> number of cars on each then the line having more cars will get the
> priority... for more details please mail me <byseid@yahoo.com>.



Article: 72171
Subject: Re: Sync data between two clock domains
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 10 Aug 2004 09:42:21 -0400
Links: << >>  << T >>  << A >>
Brad Smallridge wrote:
> 
> So how does one sync data between two non-synchonous clock domains?  Seems
> like the domain accepting the data needs to turn off the clock of the
> originating domain fopr at least one clock cycle.  How does one express that
> in VHDL?

This is not a simple question with a simple answer.  How you synchronize
data between clock domains depends on your constraints.  In a general
case, you need to deal with metastability on both the data and the
control lines.  However, I have found that the vast majority of my
designs do not need extra circuitry on the data, only on the control. 
But that depends on your data rate relative to your clock speeds.  

Here is a google link 

http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&threadm=3F46B982.454C0D23%40yahoo.com&rnum=7&prev=/groups%3Fq%3D%2Bclock%2Bdomain%2Bgroup:comp.arch.fpga%2Bauthor:rickman%26hl%3Den%26lr%3D%26ie%3DUTF-8%26scoring%3Dd%26selm%3D3F46B982.454C0D23%2540yahoo.com%26rnum%3D7

http://tinyurl.com/5meq5

The circuit shown in this post will let your transfer a control signal
from one domain to the other while minimizing metastability and giving a
single pulse.  This is very useful for flagging a data transfer.  If you
need a handshake, you can add a FF on the right hand clock domain to the
feedback path which blocks the return signal until the data has been
received.  Very simple and very effective.  

If your data rate is higher, you need a FIFO in the data path.  The
control signals from the FIFO will do the hand shaking job, MT, Full,
etc.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 72172
Subject: Re: let me have logic design for traffic light
From: Wing Fong Wong <wing@tardonttarus.uspamwa.emedu.au>
Date: Tue, 10 Aug 2004 14:22:02 +0000 (UTC)
Links: << >>  << T >>  << A >>
Gregory C. Read <readgc.invalid@hotmail.com.invalid> wrote:
> How much are you willing to pay for someone to do your homework?
> 
If this person is anything like some of those who advertise on 2rentacoder,
I would suspect around $100.

-- 

Wing Wong.
Webpage: http://wing.ucc.asn.au

FAQs about me:
Are you looking for work and do you want to work for us?
Yes, but only if it pays.

Article: 72173
Subject: Re: Newbie Xilinx Question: How to keep past designs?
From: "kpatel -at- xilinx -dot- com" <"kpatel -at- xilinx -dot- com">
Date: Tue, 10 Aug 2004 08:53:55 -0600
Links: << >>  << T >>  << A >>
Brad,

If you are using the Xilinx ISE tool, there are two methods you can use, 
depending on exactly what you are trying to accomplish:

1.  If you are looking to create a new project with the same sources in 
a different location you can use the "File -> Save Project As" command 
found under the File Menu.
2.  If you are looking to capture the state of the project as it 
currently stands, and do not want a new project, you can use the 
Snapshot feature of ISE.

Both items are explained in more detail in the ISE Help Contents, which 
you can access under the Help Menu from ISE.

Hope this helps.

Regards,
Kamal Patel
Xilinx Apps

Brad Smallridge wrote:

>So you have a pretty good design and you want to save it, start another
>design. How to do that?  I clicked on New Design, new directory, went thru
>the wizard, pasted the source form the old design into the new, (perhaps the
>name should be something generic like mydesign and the design name or idea
>is reflected in the directory), pasted the old constraint file into the new
>constraint file, (is there anything else?), and started anew.  Is there a
>faster way of doing this?
>
>
>  
>

Article: 72174
Subject: Re: Sync data between two clock domains
From: Philip Freidin <philip@fliptronics.com>
Date: Tue, 10 Aug 2004 15:09:29 GMT
Links: << >>  << T >>  << A >>
On Mon, 9 Aug 2004 21:47:27 -0700, "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote:
>So how does one sync data between two non-synchonous clock domains?  Seems
>like the domain accepting the data needs to turn off the clock of the
>originating domain fopr at least one clock cycle.  How does one express that
>in VHDL?


There are several good links on exactly this subject at the end of
this page in the FAQ:

    http://www.fpga-faq.com/FAQ_Pages/0017_Tell_me_about_metastables.htm


One of them is a pointer to this article that came out about a week ago:

   http://www.chipdesignmag.com/display.php?articleId=32&issueId=5



===================
Philip Freidin
philip.freidin@fpga-faq.com
Host for WWW.FPGA-FAQ.COM



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