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Threads Starting Mar 2001
29610: 01/03/01: Vincenzo Liguori: VHDL to Verilog RTL translator available under GPL
29618: 01/03/01: Matthias Fuchs: throughput of SDRAM controller - xilinx appnote 134
29619: 01/03/01: PROCOM: * HOT JOBS * ASIC / FPGA / VLSI designers needed - Canada
29620: 01/03/01: "Chu, Fred": Re: Soldering and Unsoldering PQFP by hand ...
29621: 01/03/01: Falk Brunner: Re: Virtex DLLs
29624: 01/03/01: Peter Alfke: Re: Virtex DLLs
29622: 01/03/01: Juan M. Rivas: What about speed-grade?
29623: 01/03/01: Peter Alfke: Re: What about speed-grade?
29626: 01/03/02: Rick Filipkiewicz: Re: What about speed-grade?
29630: 01/03/02: Ray Andraka: Re: What about speed-grade?
29631: 01/03/02: Austin Lesea: Re: What about speed-grade?
29633: 01/03/02: Luke Roth: Re: What about speed-grade?
29635: 01/03/02: Ray Andraka: Re: What about speed-grade?
29628: 01/03/02: Jacqueline Linich: San Francisco bay Hardware engineers
29629: 01/03/02: Richard Rooney: [AD]: PIC-based Embedded Webserver/Webclient available.
29632: 01/03/02: thirumurugan: Netlis : Webpack Vs Foundation
29746: 01/03/07: Srinivasan Venkataramanan: Re: Netlis : Webpack Vs Foundation
29634: 01/03/02: <kode@bridgeport.edu>: Differences in VHDL coding for FPGA & CPLD
29637: 01/03/02: Rick Filipkiewicz: Re: Differences in VHDL coding for FPGA & CPLD
29638: 01/03/02: Mike Treseler: Re: Differences in VHDL coding for FPGA & CPLD
29641: 01/03/03: Peter Alfke: Re: Bad Xilinx bitstream=big bang?
29645: 01/03/03: eteam: Re: Bad Xilinx bitstream=big bang?
29650: 01/03/03: Peter Alfke: Re: Bad Xilinx bitstream=big bang?
29646: 01/03/03: Joel Kolstad: Re: Bad Xilinx bitstream=big bang?
29652: 01/03/03: Peter Alfke: Re: Bad Xilinx bitstream=big bang?
29655: 01/03/03: Eric Smith: Re: Bad Xilinx bitstream=big bang?
29659: 01/03/04: Peter Alfke: Re: Bad Xilinx bitstream=big bang?
29692: 01/03/05: Brian Drummond: Re: Bad Xilinx bitstream=big bang?
29695: 01/03/05: Keith R. Williams: Re: Bad Xilinx bitstream=big bang?
29729: 01/03/06: Brian Drummond: Re: Bad Xilinx bitstream=big bang?
29741: 01/03/06: Austin Lesea: Re: Bad Xilinx bitstream=big bang?
29696: 01/03/05: Eric Smith: Re: Bad Xilinx bitstream=big bang?
29744: 01/03/07: alfred fuchs: Re: Bad Xilinx bitstream=big bang?
29642: 01/03/03: V R: Metastability, Asynchronous Signals, & Asynchronous design
29647: 01/03/03: Hal Murray: Re: Metastability, Asynchronous Signals, & Asynchronous design
29649: 01/03/03: S. Ramirez: Re: Metastability, Asynchronous Signals, & Asynchronous design
29653: 01/03/03: Ray Andraka: Re: Metastability, Asynchronous Signals, & Asynchronous design
29654: 01/03/04: Magnus Homann: Re: Metastability
29656: 01/03/04: Muzaffer Kal: Re: Metastability
29688: 01/03/05: Rick Collins: Re: Metastability
29792: 01/03/10: Magnus Homann: Re: Metastability
29793: 01/03/10: Ray Andraka: Re: Metastability
29876: 01/03/15: Magnus Homann: Re: Metastability
29794: 01/03/10: Rick Collins: Re: Metastability
29798: 01/03/10: rk: Re: Metastability
29801: 01/03/11: Rick Filipkiewicz: Re: Metastability
29877: 01/03/15: Magnus Homann: Re: Metastability
29878: 01/03/15: Magnus Homann: Re: Metastability
29879: 01/03/15: Rick Filipkiewicz: Re: Metastability
29658: 01/03/04: S. Ramirez: Re: Metastability, Asynchronous Signals, & Asynchronous design
29667: 01/03/04: Ray Andraka: Re: Metastability, Asynchronous Signals, & Asynchronous design
29674: 01/03/05: S. Ramirez: Re: Metastability, Asynchronous Signals, & Asynchronous design
29671: 01/03/05: Jim Granville: Re: Metastability, Asynchronous Signals, & Asynchronous design
29672: 01/03/05: Peter Alfke: Re: Metastability, Asynchronous Signals, & Asynchronous design
29677: 01/03/05: Jim Granville: Re: Metastability, Asynchronous Signals, & Asynchronous design
29680: 01/03/05: Peter Alfke: Re: Metastability, Asynchronous Signals, & Asynchronous design
29682: 01/03/05: Hal Murray: Re: Metastability, Asynchronous Signals, & Asynchronous design
29683: 01/03/05: Peter Alfke: Re: Metastability, Asynchronous Signals, & Asynchronous design
29693: 01/03/05: Falk Brunner: Re: Metastability, Asynchronous Signals, & Asynchronous design
29710: 01/03/06: Jim Granville: Re: Metastability, Asynchronous Signals, & Asynchronous design
29700: 01/03/05: glen herrmannsfeldt: Re: Metastability, Asynchronous Signals, & Asynchronous design
29799: 01/03/10: rk: Re: Metastability, Asynchronous Signals, & Asynchronous design
29676: 01/03/05: Rick Filipkiewicz: Re: Metastability, Asynchronous Signals, & Asynchronous design
29679: 01/03/05: Ray Andraka: Re: Metastability, Asynchronous Signals, & Asynchronous design
29681: 01/03/05: Peter Alfke: Re: Metastability, Asynchronous Signals, & Asynchronous design
29707: 01/03/06: Rick Filipkiewicz: Re: Metastability, Asynchronous Signals, & Asynchronous design
29643: 01/03/03: Edi: Virtex-E Equivalent Power/Ground Pairs
29648: 01/03/03: Embedded Head: Full Time - No contractors
29664: 01/03/04: S. Ramirez: Re: Full Time - No contractors
29697: 01/03/05: Steve Rencontre: Re: Full Time - No contractors
29702: 01/03/05: Eric Braeden: Re: Full Time - No contractors
29708: 01/03/06: Embedded Head: Re: Full Time - No contractors
29728: 01/03/06: Steve Rencontre: Re: Full Time - No contractors
29740: 01/03/07: S. Ramirez: Re: Full Time - No contractors
29651: 01/03/03: <fpga@iee.org>: Help : Testing a Ethernet Repeater
29661: 01/03/04: Eric Smith: webpack ISE synthesis fails with exit code: 0002
29662: 01/03/04: S. Ramirez: Re: webpack ISE synthesis fails with exit code: 0002
29663: 01/03/04: Simon: Re: webpack ISE synthesis fails with exit code: 0002
29673: 01/03/04: Eric Smith: Re: webpack ISE synthesis fails with exit code: 0002
29691: 01/03/05: Andy Peters: Re: webpack ISE synthesis fails with exit code: 0002
29694: 01/03/05: Eric Smith: Re: webpack ISE synthesis fails with exit code: 0002
29684: 01/03/05: Peter Alfke: Re: Bad Xilinx bitstream=big bang?
29698: 01/03/05: Mike: Re: Bad Xilinx bitstream=big bang?
29685: 01/03/05: Marc Reinert: Parallel Port EPP
29686: 01/03/05: V R: Re: Parallel Port EPP
29745: 01/03/07: Marc Reinert: Re: Parallel Port EPP
29936: 01/03/19: Hal Murray: Re: Parallel Port EPP
29715: 01/03/06: Marc Battyani: Re: Parallel Port EPP
29734: 01/03/07: Jim Granville: Re: Parallel Port EPP
29759: 01/03/08: Richard Erlacher: Re: Parallel Port EPP
29935: 01/03/19: Hal Murray: Re: Parallel Port EPP
30113: 01/03/23: Richard Erlacher: Re: Parallel Port EPP
30331: 01/04/03: Hal Murray: Re: Parallel Port EPP
29687: 01/03/05: Ramanathan S: URGENT HELP REQ......
29699: 01/03/05: <vkode77@hotmail.com>: ROM-based FSM implementation
29709: 01/03/05: Balaji Krishnapuram: Re: ROM-based FSM implementation
29747: 01/03/07: Srinivasan Venkataramanan: Re: ROM-based FSM implementation
29701: 01/03/05: Brian Carruthersq: Spartan XL & Spartan II Slave Serial Configuration
29774: 01/03/08: Vikram Pasham: Re: Spartan XL & Spartan II Slave Serial Configuration
29703: 01/03/05: PROCOM: Jobs @ ASIC / FPGA / VLSI designers needed - Canada
29704: 01/03/05: <jschneider@cix.CEEOWE.EWEKAY>: Suggestions for I/O card
29705: 01/03/05: Dave Vanden Bout: Re: Suggestions for I/O card
29713: 01/03/06: Jaan Sirp: Re: Suggestions for I/O card
29714: 01/03/06: <jschneider@cix.CEEOWE.EWEKAY>: Re: Suggestions for I/O card
29717: 01/03/06: Jaan Sirp: Re: Suggestions for I/O card
29724: 01/03/06: Christian Plessl: Re: Suggestions for I/O card
29712: 01/03/06: =?iso-8859-1?Q?Pawe=B3?= J. Rajda: Virtex partial reconfig...
29723: 01/03/06: Phil James-Roxby: Re: Virtex partial reconfig...
29716: 01/03/06: Stephan Schirrmann: rising_edge() on virtex
29720: 01/03/06: Nicolas Matringe: Re: rising_edge() on virtex
29783: 01/03/09: Stephan Schirrmann: Re: rising_edge() on virtex
29718: 01/03/06: Magali Oudard: School project
29721: 01/03/06: Stephan Schirrmann: Re: School project
29735: 01/03/06: OCR Bee: Re: School project
29719: 01/03/06: Steven Sanders: order Xilinx FPGA`s in Benelux
29824: 01/03/12: Peter Alfke: Re: order Xilinx FPGA`s in Benelux
29730: 01/03/06: Shawn Aker: US-AZ-Senior ASIC/FPGA Designer - 3+ years experience
29731: 01/03/06: Shawn Aker: US-AZ-Principal ASIC Designer - 10+ years experience
29732: 01/03/06: Falk Brunner: Again Spartan II power
29742: 01/03/06: Austin Lesea: Re: Again Spartan II power
29811: 01/03/12: R Sefton: Re: Again Spartan II power
29821: 01/03/12: Andrej Jancura: Re: Again Spartan II power
29828: 01/03/12: Austin Lesea: Re: Again Spartan II power
29831: 01/03/13: R Sefton: Re: Again Spartan II power
29875: 01/03/14: Magnus Homann: Re: Again Spartan II power
29733: 01/03/06: Juan M. Rivas: Is there any Virtex-II Evaluation Board?
29743: 01/03/06: Austin Lesea: Re: Is there any Virtex-II Evaluation Board?
29749: 01/03/07: Jakab Tanko: Re: Is there any Virtex-II Evaluation Board?
29928: 01/03/18: Allan Cantle: Re: Is there any Virtex-II Evaluation Board?
29736: 01/03/06: Eric Smith: More detailed Spartan II CLB drawings?
29737: 01/03/06: Chris Dunlap: Re: More detailed Spartan II CLB drawings?
29757: 01/03/07: Eric Smith: Re: More detailed Spartan II CLB drawings?
29764: 01/03/08: Brian Davis: Re: More detailed Spartan II CLB drawings?
29949: 01/03/19: Kolja Sulimma: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
29951: 01/03/19: Ray Andraka: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
29959: 01/03/19: Kolja Sulimma: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
29974: 01/03/20: Ray Andraka: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
29993: 01/03/20: Simon Bacon: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
30004: 01/03/20: Ray Andraka: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
30012: 01/03/20: Eric Crabill: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
30016: 01/03/20: Kolja Sulimma: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
30018: 01/03/20: Eric Crabill: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
30031: 01/03/21: Kolja Sulimma: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
30019: 01/03/20: Philip Freidin: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
30023: 01/03/21: Rick Filipkiewicz: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
30030: 01/03/21: Kolja Sulimma: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
29755: 01/03/07: Neil Franklin: Re: More detailed Spartan II CLB drawings?
29775: 01/03/09: Kent Orthner: Re: More detailed Spartan II CLB drawings?
29776: 01/03/08: Eric Smith: JBits on Red Hat 7.0? (was Re: More detailed Spartan II CLB drawings?)
29806: 01/03/11: Neil Franklin: Re: More detailed Spartan II CLB drawings?
29751: 01/03/07: Seb C: ERROR in Xilinx softaware !
29753: 01/03/07: Tim Jaynes: Re: ERROR in Xilinx softaware !
29758: 01/03/07: Christof Paar: CHES 2001 registration!
29760: 01/03/08: Dan Rudolf: Spartan II: POWERDOWN MODE WAS DELETED!!!
29761: 01/03/08: Dave Vanden Bout: Re: Spartan II: POWERDOWN MODE WAS DELETED!!!
29762: 01/03/08: Ray Andraka: Re: Spartan II: POWERDOWN MODE WAS DELETED!!!
29765: 01/03/08: Dan Rudolf: Re: Spartan II: POWERDOWN MODE WAS DELETED!!!
29766: 01/03/08: news.pavilion.net: GSM Baseband Chipset??
29768: 01/03/08: Mike H.: Problem with Xilinx 3.3-sp7
29773: 01/03/08: Ray Andraka: Re: Problem with Xilinx 3.3-sp7
29780: 01/03/09: Mike H.: Re: Problem with Xilinx 3.3-sp7
29779: 01/03/09: Nicolas Matringe: Re: Problem with Xilinx 3.3-sp7
29769: 01/03/08: =?iso-8859-1?Q?Pawe=B3?= J. Rajda: Foundation RLOC - help!
29782: 01/03/09: Ivar: Re: Foundation RLOC - help!
29785: 01/03/09: =?iso-8859-1?Q?Pawe=B3?= J. Rajda: Re: Foundation RLOC - help!
29788: 01/03/09: Simon Bacon: Re: Foundation RLOC - help!
29770: 01/03/08: Eric Smith: Foundation ISE Evaluation Kit - how to order?
29771: 01/03/08: Eric Smith: Re: Foundation ISE Evaluation Kit - how to order?
29777: 01/03/08: Vikram Pasham: Re: Foundation ISE Evaluation Kit - how to order?
29772: 01/03/08: =?iso-8859-1?q?peter=20ritchie?=: Fanout
29778: 01/03/08: Austin Lesea: Re: Fanout
29781: 01/03/09: PROCOM: $HOT JOBS$ ASIC / FPGA / VLSI designers needed - Canada
29791: 01/03/10: S. Ramirez: Re: $HOT JOBS$ ASIC / FPGA / VLSI designers needed - Canada
29784: 01/03/09: Christian Plessl: Spartan-II Evaluation Board
29787: 01/03/09: Eric Smith: Re: Spartan-II Evaluation Board
29796: 01/03/10: llandre: Re: Spartan-II Evaluation Board
29797: 01/03/10: Simon: Re: Spartan-II Evaluation Board
29825: 01/03/12: Franck Pissotte: Re: Spartan-II Evaluation Board
29827: 01/03/12: Simon: Re: Spartan-II Evaluation Board
30062: 01/03/22: Alan Langman: Re: Spartan-II Evaluation Board
29786: 01/03/09: VhdlCohen: Snug presentation on verification in VHDL and Verilog
29789: 01/03/09: James Horn: Springboard design contest
29790: 01/03/09: Aldo Mastrosimone: Using LVDS I/O buffers on Virtex-II
29802: 01/03/11: Catalin Baetoniu: Re: Using LVDS I/O buffers on Virtex-II
29795: 01/03/10: llandre: Questions about Xilinx Web Pack ISE
29800: 01/03/11: Simon Bacon: Re: Questions about Xilinx Web Pack ISE
29840: 01/03/13: frederik: Re: Questions about Xilinx Web Pack ISE
29803: 01/03/11: Eric Smith: sample code for JTAG configuration of Virtex, Spartan II?
29836: 01/03/13: Jaan Sirp: Re: sample code for JTAG configuration of Virtex, Spartan II?
29843: 01/03/13: Tim Jaynes: Re: sample code for JTAG configuration of Virtex, Spartan II?
29804: 01/03/11: <jschneider@cix.CEEOWE.EWEKAY>: Configuration devices
29805: 01/03/11: Falk Brunner: Re: Configuration devices
29807: 01/03/12: Rick Filipkiewicz: Re: Configuration devices
29808: 01/03/12: Ray Andraka: Re: Configuration devices
29809: 01/03/12: M. Simon: Re: Configuration devices
29826: 01/03/12: Brian Goudy: Re: Configuration devices
29812: 01/03/12: kctang: __Cut and Paste C codes, you can have your hardware!
29813: 01/03/12: F.M. Fontaine: Parallel Port EPP (again)
29866: 01/03/14: John Chambers: Re: Parallel Port EPP (again)
29891: 01/03/15: Hoa Phan: Re: Parallel Port EPP (again)
29814: 01/03/12: Compilit: IP Cores, Megacores
29818: 01/03/12: Dennis Scott: Re: IP Cores, Megacores
29819: 01/03/12: Zimba: Re: IP Cores, Megacores
29886: 01/03/15: Compilit: Re: IP Cores, Megacores
29888: 01/03/15: Zimba: Re: IP Cores, Megacores
29895: 01/03/15: Compilit: Re: IP Cores, Megacores
29896: 01/03/16: Dennis Scott: Re: IP Cores, Megacores
29897: 01/03/16: Zimba: Re: IP Cores, Megacores
29903: 01/03/16: Compilit: Re: IP Cores, Megacores
29904: 01/03/16: Zimba: Re: IP Cores, Megacores
29817: 01/03/12: Harjo Otten: Leonardo 'renames' in- and outputs.
29839: 01/03/13: Rienk van der Scheer: Re: Leonardo 'renames' in- and outputs.
29829: 01/03/12: Theron Hicks (Terry): VirtexE LVPECL I/O Ports? experience?
29830: 01/03/13: Phil Hays: Re: VirtexE LVPECL I/O Ports? experience?
29832: 01/03/13: Peter Alfke: Re: VirtexE LVPECL I/O Ports? experience?
29833: 01/03/13: Hal Murray: Re: VirtexE LVPECL I/O Ports? experience?
29837: 01/03/13: Reinoud: Low volume users (was: Re: VirtexE LVPECL I/O Ports? experience?)
29863: 01/03/14: Brian Drummond: Re: Low volume users (was: Re: VirtexE LVPECL I/O Ports? experience?)
29889: 01/03/15: Jaan Sirp: Re: Low volume users (was: Re: VirtexE LVPECL I/O Ports? experience?)
29855: 01/03/14: Phil Hays: Re: Low volume production was VirtexE LVPECL I/O Ports? experience?
30970: 01/05/05: Quiet Desperation: Re: VirtexE LVPECL I/O Ports? experience?
30971: 01/05/06: Peter Alfke: Re: VirtexE LVPECL I/O Ports? experience?
29835: 01/03/13: Manfred Kraus: 64 simultan A/D Converters in an SPARTAN-II
29841: 01/03/13: Erik Widding: Re: 64 simultan A/D Converters in an SPARTAN-II
29844: 01/03/13: Peter Alfke: Re: 64 simultan A/D Converters in an SPARTAN-II
29845: 01/03/13: Erik Widding: Re: 64 simultan A/D Converters in an SPARTAN-II
29846: 01/03/13: Manfred Kraus: Re: 64 simultan A/D Converters in an SPARTAN-II
29847: 01/03/13: Peter Alfke: Re: 64 simultan A/D Converters in an SPARTAN-II
29851: 01/03/14: Jim Granville: Re: 64 simultan A/D Converters in an SPARTAN-II
29848: 01/03/13: Peter Alfke: Re: 64 simultan A/D Converters in an SPARTAN-II
29853: 01/03/13: Erik Widding: Re: 64 simultan A/D Converters in an SPARTAN-II
29856: 01/03/14: Peter Alfke: Re: 64 simultan A/D Converters in an SPARTAN-II
29857: 01/03/14: Erik Widding: Re: 64 simultan A/D Converters in an SPARTAN-II
29859: 01/03/14: Jim Granville: Re: 64 simultan A/D Converters in an SPARTAN-II
29864: 01/03/14: Simon Bacon: Re: 64 simultan A/D Converters in an SPARTAN-II
29838: 01/03/13: Laurent Gauch: Any advice about Visual IP
29842: 01/03/13: Simon Y. Foo: JBits drivers for XESS boards
29849: 01/03/13: Phil James-Roxby: Re: JBits drivers for XESS boards
29850: 01/03/13: Jerry English: bonding information
29852: 01/03/13: Simon Bacon: Re: bonding information
29867: 01/03/14: Ulises Hernandez: Re: bonding information
29854: 01/03/13: Mark: FPGA : Simple FD latch glitchs
29872: 01/03/14: Falk Brunner: Re: FPGA : Simple FD latch glitchs
29916: 01/03/16: Philip Freidin: Re: FPGA : Simple FD latch glitchs
29858: 01/03/13: goran: how to use both edges of clock
29861: 01/03/14: Felix Bertram: Re: how to use both edges of clock
29860: 01/03/13: Nicole Y. Chen: Programming CPLD and FPGA on XESS board for Ethernet.
29890: 01/03/15: Jaan Sirp: Re: Programming CPLD and FPGA on XESS board for Ethernet.
29862: 01/03/14: Marco Landert: NIOS 16-Bit
29869: 01/03/14: Nial Stewart: Re: NIOS 16-Bit
29871: 01/03/14: Marco Landert: Re: NIOS 16-Bit
29882: 01/03/15: Nial Stewart: Re: NIOS 16-Bit
29873: 01/03/14: Frank Ch. Eigler: Re: NIOS 16-Bit
29883: 01/03/15: Marco Landert: Re: NIOS 16-Bit
29880: 01/03/15: Vitaliy Tkachenko: Re: NIOS 16-Bit
29881: 01/03/15: Wolfgang Loewer: Re: NIOS 16-Bit
29884: 01/03/15: Rune Baeverrud: Re: NIOS 16-Bit
30145: 01/03/25: Compilit: Re: NIOS 16-Bit
29865: 01/03/14: Mark Anstice: Xilinx webpack supported pachages
29870: 01/03/14: Klaus Falser: Re: Xilinx webpack supported pachages
29868: 01/03/14: TomC: FLEX10 config with AT17xxx 8DIP device?
29874: 01/03/14: Danny Niewzwaag: VHDL capacity
29885: 01/03/15: Tom Van Uffelen: Using Virtex DLLs in Leonardo
29887: 01/03/15: Håkan Pettersson: Re: Using Virtex DLLs in Leonardo
29892: 01/03/15: A1A Computer Professionals: Archive of Electronic Engineering jobs incl: ASIC,DSP,VHDL,FPGA,RF etc..
29900: 01/03/16: Compilit: Re: Archive of Electronic Engineering jobs incl: ASIC,DSP,VHDL,FPGA,RF etc..
29893: 01/03/15: Danny Niewzwaag: International VHDL cooperation wanted
29894: 01/03/16: Hoa Phan: Looking for VHDL code or ABEL+schematic capture for interfacing parallel port in mode EPP
29898: 01/03/16: Heinrich Fonfara: RAM-based Shift Register
29905: 01/03/16: Peter Alfke: Re: RAM-based Shift Register
29915: 01/03/16: Falk Brunner: Re: RAM-based Shift Register
29938: 01/03/19: Heinrich Fonfara: Re: RAM-based Shift Register
29899: 01/03/16: Dave Glenton: Passing text strings to procedures in VHDL
29902: 01/03/16: Srinivasan Venkataramanan: Re: Passing text strings to procedures in VHDL
29901: 01/03/16: Mirek Klaczek: Xiilinx Web Pack error
29906: 01/03/16: Nicolas Matringe: xilinx Webpack missing speed grade
29921: 01/03/16: Eric Smith: Re: xilinx Webpack missing speed grade
29939: 01/03/19: Nicolas Matringe: Re: xilinx Webpack missing speed grade
29941: 01/03/19: Nicolas Matringe: Re: xilinx Webpack missing speed grade
29973: 01/03/19: Eric Smith: Re: xilinx Webpack missing speed grade
29985: 01/03/20: Nicolas Matringe: Re: xilinx Webpack missing speed grade
29907: 01/03/16: The PeopleWeb Inc.: Senior I/O Designer - Canada
29919: 01/03/16: Rick Filipkiewicz: Re: Senior I/O Designer - Canada
29924: 01/03/18: Tom Burgess: Re: Senior I/O Designer - Canada
30047: 01/03/21: Lee Iovino: Re: Senior I/O Designer - Canada
30053: 01/03/21: Andy Peters: Re: Senior I/O Designer - Canada
30099: 01/03/22: Lee I.: Re: Senior I/O Designer - Canada
30155: 01/03/26: Andy Peters: Re: Senior I/O Designer - Canada
30152: 01/03/26: John Chambers: Re: Senior I/O Designer - Canada
29908: 01/03/16: The PeopleWeb Inc.: ASIC Designer
29909: 01/03/16: The PeopleWeb Inc.: Graphics Board Design Engineers
29910: 01/03/16: The PeopleWeb Inc.: ASIC Continuation Engineer
29911: 01/03/16: The PeopleWeb Inc.: Senior Engineer, Process & Technology
29912: 01/03/16: The PeopleWeb Inc.: Senior Engineer, Physical Design
29913: 01/03/16: The PeopleWeb Inc.: Senior Memory IC Designer
29914: 01/03/16: The PeopleWeb Inc.: DV (Design Verification) Engineers
29917: 01/03/16: Krysti Shough: XACT 5.2.1 & Viewdraw 6.0
29918: 01/03/16: Vitit Kantabutra: SPECIAL SESSION ON LOW-POWER ELECTRONICS AT IECON 2001, DENVER
29920: 01/03/16: Tricia Dolkas, aka Technoyenta: Hardware Design Engineer Needed in Santa Clara, CA
29965: 01/03/19: Tom: Re: Hardware Design Engineer Needed in Santa Clara, CA
29922: 01/03/16: Manjunathan: about core generator
29923: 01/03/17: Peter Alfke: Re: about core generator
29925: 01/03/18: Rick Collins: FFT in FPGAs
29926: 01/03/18: Peter Alfke: Re: FFT in FPGAs
29929: 01/03/18: Rick Collins: Re: FFT in FPGAs
29933: 01/03/19: Peter Alfke: Re: FFT in FPGAs
29937: 01/03/19: Rick Collins: Re: FFT in FPGAs
29963: 01/03/19: Peter Alfke: Re: FFT in FPGAs
29981: 01/03/20: Rick Collins: Re: FFT in FPGAs
30006: 01/03/20: Erik Widding: Re: FFT in FPGAs
30010: 01/03/20: Rick Collins: Re: FFT in FPGAs
29957: 01/03/19: Falk Brunner: Re: FFT in FPGAs
29927: 01/03/18: Ray Andraka: Re: FFT in FPGAs
29930: 01/03/18: Rick Collins: Re: FFT in FPGAs
30014: 01/03/20: Chris Dick: Re: FFT in FPGAs
30049: 01/03/21: Tom Dillon: Re: FFT in FPGAs
29931: 01/03/18: David Nyarko: VHDL code required for a given decimator system
29953: 01/03/19: Brian Philofsky: Re: VHDL code required for a given decimator system
29932: 01/03/19: Neil Franklin: TBUFs in Virtex and later chips, going out of fashion, what instead
29943: 01/03/19: Jan Gray: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
29947: 01/03/19: Ray Andraka: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
29966: 01/03/19: Neil Franklin: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
29948: 01/03/19: Austin Franklin: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
29988: 01/03/20: Juri Kanevski: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30007: 01/03/20: Austin Lesea: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30009: 01/03/20: Rick Collins: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30013: 01/03/20: Kolja Sulimma: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30028: 01/03/21: Rick Collins: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30021: 01/03/20: Austin Lesea: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30024: 01/03/21: Ray Andraka: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30027: 01/03/20: Jan Gray: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30043: 01/03/21: Neil Franklin: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30060: 01/03/22: Hal Murray: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30067: 01/03/22: Ray Andraka: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30073: 01/03/22: Austin Lesea: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30072: 01/03/22: Austin Lesea: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30084: 01/03/22: Simon Bacon: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30090: 01/03/23: <muzaffer@dspia.com>: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30101: 01/03/23: Hal Murray: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
29940: 01/03/19: Frode Vatvedt Fjeld: video coding
29954: 01/03/19: Ron Proveniers: Re: video coding
29942: 01/03/19: =?iso-8859-1?Q?Pawe=B3?= J. Rajda: Virtex gate count...?
29944: 01/03/19: MANJUNATHAN: about placement and routing
29952: 01/03/19: Ray Andraka: Re: about placement and routing
29945: 01/03/19: Kolja Sulimma: Spartan-II VREF and VCCO
29950: 01/03/19: Austin Lesea: Re: Spartan-II VREF and VCCO
29962: 01/03/19: Kolja Sulimma: Re: Spartan-II VREF and VCCO
29970: 01/03/19: Austin Lesea: Re: Spartan-II VREF and VCCO
29977: 01/03/20: Hal Murray: Re: Spartan-II VREF and VCCO
29995: 01/03/20: Keith R. Williams: Re: Spartan-II VREF and VCCO
29955: 01/03/19: Qian: Cannot Export netlist from Synopsys
29956: 01/03/19: Michal Kvasnicka: TOA measurement
29960: 01/03/19: Kolja Sulimma: Re: TOA measurement
29967: 01/03/19: Michal Kvasnicka: Re: TOA measurement
29969: 01/03/19: Kolja Sulimma: Re: TOA measurement
29975: 01/03/20: Ray Andraka: Re: TOA measurement
29987: 01/03/20: Juri Kanevski: Re: TOA measurement
29989: 01/03/20: Michal Kvasnicka: Re: TOA measurement
30065: 01/03/22: Ray Andraka: Re: TOA measurement
29994: 01/03/20: Kolja Sulimma: Re: TOA measurement
29997: 01/03/20: Michal Kvasnicka: Re: TOA measurement
29998: 01/03/20: Ray Andraka: Re: TOA measurement
30003: 01/03/20: Michal Kvasnicka: Re: TOA measurement
30036: 01/03/21: Michal Kvasnicka: Re: TOA measurement
30044: 01/03/21: Jerry Avins: Re: TOA measurement
30046: 01/03/21: Michal Kvasnicka: Re: TOA measurement
30057: 01/03/22: Charles Lyttle: Re: TOA measurement
30063: 01/03/22: Michal Kvasnicka: Re: TOA measurement
30127: 01/03/24: Charles Lyttle: Re: TOA measurement
30074: 01/03/22: Jerry Avins: Re: TOA measurement
30051: 01/03/21: Ray Andraka: Re: TOA measurement
29980: 01/03/20: Michal Kvasnicka: Re: TOA measurement
29990: 01/03/20: <p.kootsookos@remove.ieee.org>: Re: TOA measurement
29991: 01/03/20: <p.kootsookos@remove.ieee.org>: Re: TOA measurement
29996: 01/03/20: Michal Kvasnicka: Re: TOA measurement
29971: 01/03/19: Ray Andraka: Re: TOA measurement
29979: 01/03/20: Kolja Sulimma: Re: TOA measurement
29999: 01/03/20: Ray Andraka: Re: TOA measurement
30005: 01/03/20: Michal Kvasnicka: Re: TOA measurement
30011: 01/03/20: Peter Alfke: Re: TOA measurement
30015: 01/03/20: Jerry Avins: Re: TOA measurement
30032: 01/03/21: Michal Kvasnicka: Re: TOA measurement
30094: 01/03/23: Charles Lyttle: Re: TOA measurement
29958: 01/03/19: Swift: Simulations in ModelSim...
29961: 01/03/19: Chris Ward: FPGA based Neural Networks
30192: 01/03/27: Tim Tyler: Re: FPGA based Neural Networks
31282: 01/05/16: Vivek Sood: Re: FPGA based Neural Networks
29964: 01/03/19: Shareef Jalloq: Altera Flex10K config
29968: 01/03/19: C.Schlehaus: Re: Altera Flex10K config
29972: 01/03/19: Shareef Jalloq: Re: Altera Flex10K config
29978: 01/03/20: C.Schlehaus: Re: Altera Flex10K config
29976: 01/03/20: Pratip Mukherjee: Do I need to tie unused CPLD pins to GND?
30008: 01/03/20: Arthur: Re: Do I need to tie unused CPLD pins to GND?
30029: 01/03/21: Klaus Falser: Re: Do I need to tie unused CPLD pins to GND?
30037: 01/03/21: Ray Andraka: Re: Do I need to tie unused CPLD pins to GND?
30042: 01/03/21: Peter Alfke: Re: Do I need to tie unused CPLD pins to GND?
30061: 01/03/22: Klaus Falser: Re: Do I need to tie unused CPLD pins to GND?
30122: 01/03/23: Mikeandmax: Re: Do I need to tie unused CPLD pins to GND?
30106: 01/03/23: Gil Golov: Re: Do I need to tie unused CPLD pins to GND?
29982: 01/03/20: Raintech Consulting Limited: Jobs....?
30034: 01/03/21: Hal Murray: Re: Jobs....?
30035: 01/03/21: Simon Bacon: Re: Jobs....?
29983: 01/03/20: Rainer Storn: Book on FPGA-Design with Xilinx chips
30000: 01/03/20: Ray Andraka: Re: Book on FPGA-Design with Xilinx chips
30002: 01/03/20: Austin Franklin: Re: Book on FPGA-Design with Xilinx chips
29984: 01/03/20: Rainer Storn: Packing density of Xilinx FPGAs
29992: 01/03/20: Simon Bacon: Re: Packing density of Xilinx FPGAs
30001: 01/03/20: Ray Andraka: Re: Packing density of Xilinx FPGAs
29986: 01/03/20: Andreas Wolf: virtex block ram
30017: 01/03/20: Adam Elbirt: RC5 implementations
30020: 01/03/20: Eric: XESS Prototyping boards - Is there a difference between...
30022: 01/03/20: Dave Vanden Bout: Re: XESS Prototyping boards - Is there a difference between...
30025: 01/03/20: Luke Roth: BG575 socket recommendation?
30076: 01/03/22: Ryan Laity: Re: BG575 socket recommendation?
30026: 01/03/21: Kent Orthner: Looking for Skew information
30033: 01/03/21: Magnus Homann: Re: Looking for Skew information
30038: 01/03/21: Benjamin Hoffman: Trouble with assigning output pins on Xilinx (foundation)
30040: 01/03/21: PeteD: Re: Trouble with assigning output pins on Xilinx (foundation)
30041: 01/03/21: Philip Freidin: Re: Trouble with assigning output pins on Xilinx (foundation)
30039: 01/03/21: luigi funes: backup FLEX10K
30045: 01/03/21: Erik Widding: Re: backup FLEX10K
30048: 01/03/21: Lee Iovino: implementing complex datacom protocols
30050: 01/03/21: Speedy Zero Two: Yet Another Newbie Question
30052: 01/03/21: Peter Alfke: Re: Yet Another Newbie Question
30054: 01/03/21: Pete Dudley: reduced precision floating point
30055: 01/03/22: Ray Andraka: Re: reduced precision floating point
30056: 01/03/22: Peter Alfke: Re: reduced precision floating point
30064: 01/03/22: Ray Andraka: Re: reduced precision floating point
30068: 01/03/22: Jan Gray: Re: reduced precision floating point
30110: 01/03/23: Steven Derrien: Re: reduced precision floating point
30058: 01/03/22: Austin Franklin: Is the carry logic for Virtex included in PAR timing report/check?
30066: 01/03/22: Ray Andraka: Re: Is the carry logic for Virtex included in PAR timing report/check?
30069: 01/03/22: Austin Franklin: Re: Is the carry logic for Virtex included in PAR timing report/check?
30081: 01/03/22: Peter Alfke: Re: Is the carry logic for Virtex included in PAR timing report/check?
30089: 01/03/22: Austin Franklin: Re: Is the carry logic for Virtex included in PAR timing report/check?
30093: 01/03/23: Peter Alfke: Re: Is the carry logic for Virtex included in PAR timing report/check?
30097: 01/03/22: Austin Franklin: Re: Is the carry logic for Virtex included in PAR timing report/check?
30070: 01/03/22: <comp@hotmail.com>: Nokia 8850 zu gewinnen 5859
30075: 01/03/22: Gaston Biessener: Looking for Processor Core info/advice
30080: 01/03/22: Tom Dillon: Re: Looking for Processor Core info/advice
30085: 01/03/22: Eric Smith: Re: Looking for Processor Core info/advice
30115: 01/03/23: Tom Dillon: Re: Looking for Processor Core info/advice
30096: 01/03/23: Phil Hays: Re: Looking for Processor Core info/advice
30098: 01/03/23: Kent Orthner: Re: Looking for Processor Core info/advice
30107: 01/03/23: Kolja Sulimma: Re: Looking for Processor Core info/advice
30077: 01/03/22: Ray Andraka: Virtex Em on a board?
30078: 01/03/22: Johan Ditmar: Re: Virtex Em on a board?
30088: 01/03/23: Ray Andraka: Re: Virtex Em on a board?
30109: 01/03/23: Ralph Weir: Re: Virtex Em on a board?
30082: 01/03/22: <muzaffer@dspia.com>: frequency measurement?
30086: 01/03/23: Jim Granville: Re: frequency measurement?
30087: 01/03/22: Ray Andraka: Re: frequency measurement?
30181: 01/03/27: <vt313@comsys.ntu-kpi.kiev.ua>: Re: frequency measurement?
30193: 01/03/27: glen herrmannsfeldt: Re: frequency measurement?
30197: 01/03/27: Ray Andraka: Re: frequency measurement?
30083: 01/03/22: Mesner: XS40 and XS95: Recommend books?
30092: 01/03/22: Dave Vanden Bout: Re: XS40 and XS95: Recommend books?
30091: 01/03/23: Daniel Nilsson: what to do with I/O pins during powerup or during jtag programming
30105: 01/03/23: Klaus Falser: Re: what to do with I/O pins during powerup or during jtag programming
30117: 01/03/23: PeteD: Re: what to do with I/O pins during powerup or during jtag programming
30095: 01/03/22: Guibert, Martin: Help! DLL Feedback in Virtex-E
30103: 01/03/23: David Nyarko: REQ. VHDL code for Single-pole IIR low-pass filter
30104: 01/03/22: Manjunathan: PLACE and ROUTE
30123: 01/03/23: tider: Re: PLACE and ROUTE
30108: 01/03/23: Manjunathan: Timing analysis after implementation
30140: 01/03/25: Vikram Pasham: Re: Timing analysis after implementation
30111: 01/03/23: Guy R. Paquet: Boundary Scan tools - price comparison
30112: 01/03/23: Ian McCarthy: Simplified ISP of XCR3256XL from BIF file fails
30156: 01/03/26: Jennifer Jenkins: Re: Simplified ISP of XCR3256XL from BIF file fails
30185: 01/03/27: Ian McCarthy: Re: Simplified ISP of XCR3256XL from BIF file fails
30114: 01/03/23: Vikram Nagia: Software Pundits ASIC/FPGA
30125: 01/03/23: Austin Franklin: Re: Software Pundits ASIC/FPGA
30116: 01/03/23: Christian Martin: Accumulator - Core in XC4K
30126: 01/03/24: Peter Alfke: Re: Accumulator - Core in XC4K
30137: 01/03/25: Ray Andraka: Re: Accumulator - Core in XC4K
30118: 01/03/23: catherina: speech
30121: 01/03/23: Falk Brunner: Re: speech
30200: 01/03/28: Victor Schutte: Re: speech
30202: 01/03/28: Michael Strothjohann: Re: speech
30208: 01/03/28: Ray Andraka: Re: speech
30119: 01/03/23: catherina: tst
30120: 01/03/23: catherina: tst
30124: 01/03/23: Brian Kane: Call For Papers - Boston Synopsys Users' Group
30128: 01/03/24: iPierre: config FPGA OK but nothing running !?
30129: 01/03/24: Peter Alfke: Re: config FPGA OK but nothing running !?
30134: 01/03/24: Peter Alfke: Re: config FPGA OK but nothing running !?
30130: 01/03/24: Mike Butts: How to find out where par placed things?
30131: 01/03/24: Kolja Sulimma: Re: How to find out where par placed things?
30132: 01/03/24: Eric Smith: Re: How to find out where par placed things?
30133: 01/03/24: Mike Butts: Re: How to find out where par placed things?
30135: 01/03/24: Eric Smith: Re: How to find out where par placed things?
30136: 01/03/24: Hobson Frater: Re: How to find out where par placed things?
30138: 01/03/25: Ray Andraka: Re: How to find out where par placed things?
30139: 01/03/24: Philip Freidin: Re: How to find out where par placed things?
30177: 01/03/26: Mike Butts: Re: How to find out where par placed things?
30141: 01/03/25: Kolja Sulimma: No inputs on XC9536XL
30142: 01/03/25: Falk Brunner: Re: No inputs on XC9536XL
30143: 01/03/25: Kolja Sulimma: Re: No inputs on XC9536XL
30144: 01/03/25: Falk Brunner: Re: No inputs on XC9536XL
30147: 01/03/26: Peter Alfke: Re: No inputs on XC9536XL
30205: 01/03/28: Kolja Sulimma: Re: No inputs on XC9536XL
30146: 01/03/26: Jim Granville: Re: No inputs on XC9536XL
30148: 01/03/26: Kent Orthner: Re: No inputs on XC9536XL
30150: 01/03/26: Magnus Homann: Re: No inputs on XC9536XL
30343: 01/04/03: Arthur: Re: No inputs on XC9536XL
30151: 01/03/26: <lyqin@cti.com.cn>: What's new in Synplify 6.20 than 6.13
30175: 01/03/27: Alan Nishioka: Re: What's new in Synplify 6.20 than 6.13
30191: 01/03/27: Magnus Homann: Re: What's new in Synplify 6.20 than 6.13
30153: 01/03/26: catherina: hybrid design entry
30157: 01/03/26: Falk Brunner: Re: hybrid design entry
30163: 01/03/26: catherina: Re: hybrid design entry
30194: 01/03/27: name: Re: hybrid design entry
30154: 01/03/26: Marcin Michalak: Asynchronus Mashine States
30158: 01/03/26: Falk Brunner: Re: Asynchronus Mashine States
30159: 01/03/26: Mike Treseler: Re: Asynchronus Mashine States
30160: 01/03/26: Ray Andraka: Re: Asynchronus Mashine States
30173: 01/03/27: Rick Filipkiewicz: Re: Asynchronus Mashine States
30182: 01/03/27: Simon Bacon: Re: Asynchronus Mashine States
30184: 01/03/27: Ray Andraka: Re: Asynchronus Mashine States
30442: 01/04/08: Robert Carney: Re: Asynchronus Mashine States
30449: 01/04/08: Rick Filipkiewicz: Re: Asynchronus Mashine States
30178: 01/03/27: David Miller: Re: Asynchronus Mashine States
30180: 01/03/27: Marcin Michalak: Re: Asynchronus Mashine States
30161: 01/03/26: tider: RAM read?
30165: 01/03/26: Peter Alfke: Re: RAM read?
30162: 01/03/26: Marc Battyani: Logic trimmed (XCS40 F3.1)
30168: 01/03/26: name: Re: Logic trimmed (XCS40 F3.1)
30170: 01/03/27: Marc Battyani: Re: Logic trimmed (XCS40 F3.1)
30183: 01/03/27: Nicolas Matringe: Re: Logic trimmed (XCS40 F3.1)
30164: 01/03/26: Dave Brown: Xilinx FPGA Config file sizes.
30166: 01/03/26: cyber_spook: Re: Xilinx FPGA Config file sizes.
30186: 01/03/27: Werner Dreher: Re: Xilinx FPGA Config file sizes.
30203: 01/03/28: Petter Gustad: Re: Xilinx FPGA Config file sizes.
30167: 01/03/26: Wade D. Peterson: Alternatives for Xilinx Spartan-II configuration PROM
30169: 01/03/26: John Grider: Re: Alternatives for Xilinx Spartan-II configuration PROM
30172: 01/03/27: Kent Orthner: Re: Alternatives for Xilinx Spartan-II configuration PROM
30188: 01/03/27: Werner Dreher: Re: Alternatives for Xilinx Spartan-II configuration PROM
30176: 01/03/27: Peter Alfke: Re: Alternatives for Xilinx Spartan-II configuration PROM
30171: 01/03/26: tider: Virtex II RLOC
30174: 01/03/27: Minh Nguyen: a newbie question
30179: 01/03/27: Matthias Fuchs: Xilinx Core generator with WebPack ISE
30187: 01/03/27: Chris Dunlap: Re: Xilinx Core generator with WebPack ISE
30253: 01/03/29: Kirk Saban: Re: Xilinx Core generator with WebPack ISE
30189: 01/03/27: david garnett: Powerup problems with XC9500XL
30190: 01/03/27: Austin Lesea: Re: Powerup problems with XC9500XL
30201: 01/03/28: Klaus Falser: Re: Powerup problems with XC9500XL
30195: 01/03/27: Cynthia Victor: Any Expert FPGA Engineers out there?
30196: 01/03/27: Tom Dillon: Re: Any Expert FPGA Engineers out there?
30249: 01/03/29: Tom: Re: Any Expert FPGA Engineers out there?
30198: 01/03/28: Phil Hays: Pinout tables
30215: 01/03/28: Simon Bacon: Re: Pinout tables
30218: 01/03/28: Vikram Pasham: Re: Pinout tables
30219: 01/03/28: Vikram Pasham: Re: Pinout tables
30221: 01/03/28: Simon Bacon: Re: Pinout tables
30222: 01/03/29: Rick Filipkiewicz: Re: Pinout tables
30225: 01/03/28: Vikram Pasham: Re: Pinout tables
30414: 01/04/06: Vikram Pasham: Re: Pinout tables
30420: 01/04/07: Phil Hays: Re: Pinout tables
30227: 01/03/29: Phil Hays: Re: Pinout tables
30546: 01/04/13: Vikram Pasham: Re: Pinout tables
30199: 01/03/28: Chris Briggs: PCI-X core
30212: 01/03/28: Chris Dunlap: Re: PCI-X core
30224: 01/03/29: Rick Filipkiewicz: Re: PCI-X core
30235: 01/03/28: Austin Franklin: Re: PCI-X core
30248: 01/03/29: Mark Korsloot: Re: PCI-X core
30258: 01/03/29: Jamie Sanderson: Re: PCI-X core
30286: 01/03/31: Rick Filipkiewicz: Re: PCI-X core
30374: 01/04/04: Richard Iachetta: Re: PCI-X core
30204: 01/03/28: Petter Gustad: Xilinx par -m
30207: 01/03/28: =?iso-8859-1?Q?J=F6rg?= Ritter: Re: Xilinx par -m
30214: 01/03/28: Brant Soudan: Re: Xilinx par -m
30206: 01/03/28: Frederic Darre: Please help a poor student with virtexe
30223: 01/03/28: Vikram Pasham: Re: Please help a poor student with virtexe
30336: 01/04/03: Frederic Darre: Re: Please help a poor student with virtexe
30260: 01/03/29: iPierre: Re: Please help a poor student with virtexe
30209: 01/03/28: Phil Martin: P4 vs Athlon
30211: 01/03/28: Muzaffer Kal: Re: P4 vs Athlon
30210: 01/03/28: Ronald Hecht: Problem with Virtex XCV1000BG560-4 ES
30213: 01/03/28: Matthias Fuchs: problem when printing from Xilinx FPGA editor
30216: 01/03/28: <tom_systek@msn.com>: Wanted: test vector generation software
30247: 01/03/29: Tom: Re: Wanted: test vector generation software
30217: 01/03/28: Emanuel Machado: JTAG Chain problem and Altera -- has anyone seen this before?
30220: 01/03/28: Jean-Marie Bussat: VHDL question
30228: 01/03/28: Jean-Marie Bussat: Re: VHDL question
30232: 01/03/29: Kent Orthner: Re: VHDL question
30231: 01/03/29: Kent Orthner: Re: VHDL question
30251: 01/03/29: Mark Korsloot: Re: VHDL question
30254: 01/03/29: Jean-Marie Bussat: Re: VHDL question
30226: 01/03/28: Compilit: Books for trade
30234: 01/03/29: Ray Andraka: Re: Books for trade
30237: 01/03/29: Compilit: Re: Books for trade
30322: 01/04/02: Compilit: Re: Books for trade
30434: 01/04/07: Compilit: Re: Books for trade
30229: 01/03/28: Mark Raviola: Recommended Oscillators for DLL's at 25 MHz
30233: 01/03/29: Jim Granville: Re: Recommended Oscillators for DLL's at 25 MHz
30236: 01/03/29: Kolja Sulimma: Re: Recommended Oscillators for DLL's at 25 MHz
30245: 01/03/29: Austin Lesea: Re: Recommended Oscillators for DLL's at 25 MHz
30230: 01/03/29: C.Schlehaus: Problems with NIC and FlexLM / W2K
30238: 01/03/29: Marko: Re: Problems with NIC and FlexLM / W2K
30262: 01/03/30: C.Schlehaus: Re: Problems with NIC and FlexLM / W2K
30239: 01/03/29: Ralf =?iso-8859-1?Q?Oberl=E4nder?=: Encryption Bitstrems
30243: 01/03/29: luigi funes: Re: Encryption Bitstrems
30246: 01/03/29: Peter Alfke: Re: Encryption Bitstrems
30240: 01/03/29: Harvey Twyman: Programmble Logic Sequencer
30242: 01/03/29: Austin Franklin: Re: Programmble Logic Sequencer
30244: 01/03/29: Michael Boehnel: Re: Programmble Logic Sequencer
30257: 01/03/29: Austin Franklin: Re: Programmble Logic Sequencer
30261: 01/03/29: Peter Alfke: Re: Programmble Logic Sequencer
30265: 01/03/30: Michael Boehnel: Re: Programmble Logic Sequencer
30273: 01/03/30: Austin Franklin: Re: Programmble Logic Sequencer
30241: 01/03/29: Paul Taylor: XC9500XL max, typ, min propagation delay values?
30250: 01/03/29: iPierre: VHDL Test bench
30263: 01/03/30: Srinivasan Venkataramanan: Re: VHDL Test bench
30252: 01/03/29: iPierre: CLK / STARTUP PB
30255: 01/03/29: Speedy Zero Two: FPGA V CPLD
30259: 01/03/29: Simon Bacon: Re: FPGA V CPLD
30287: 01/03/31: Rick Filipkiewicz: Re: FPGA V CPLD
30314: 01/04/02: Andy Peters: Re: FPGA V CPLD
30321: 01/04/02: Victor Schutte: Re: FPGA V CPLD
30266: 01/03/30: Victor Schutte: Re: FPGA V CPLD
30282: 01/03/31: Jonas Thor: Re: FPGA V CPLD
30296: 01/04/02: Victor Schutte: Re: FPGA V CPLD
30283: 01/03/30: Austin Lesea: Re: FPGA V CPLD
30317: 01/04/02: Speedy Zero Two: Re: FPGA V CPLD
30319: 01/04/02: Speedy Zero Two: Re: FPGA V CPLD
30364: 01/04/04: Compilit: Re: FPGA V CPLD
30256: 01/03/29: Ivar: 8279 keyboard controller in Verilog or VHDL ?
30264: 01/03/30: news.hinet.net: Re: 8279 keyboard controller in Verilog or VHDL ?
30267: 01/03/30: Rissa Tero: HAL-15
30268: 01/03/30: Kolja Sulimma: Re: HAL-15
30269: 01/03/30: Simon Bacon: Re: HAL-15
30270: 01/03/30: Rissa Tero: Re: HAL-15
30280: 01/03/30: Jean-Marie Bussat: Re: HAL-15
30271: 01/03/30: Steven Sanders: Reed/Solomon ENcoder
30281: 01/03/30: Eric Smith: Re: Reed/Solomon ENcoder
30285: 01/03/31: Meloun: Re: Reed/Solomon ENcoder
30323: 01/04/02: Eric Smith: Re: Reed/Solomon ENcoder
30362: 01/04/04: Steven Sanders: Re: Reed/Solomon ENcoder
30272: 01/03/30: Manjunathan: VIRTEX BLOCK RAM
30274: 01/03/30: Peter Alfke: Re: VIRTEX BLOCK RAM
30279: 01/03/30: Jan Gray: Re: VIRTEX BLOCK RAM
30275: 01/03/30: A1A Computer Professionals: Unlimited Jobs for Electronic Engineering jobs incl: ASIC,DSP,VHDL,FPGA,RF etc..
30278: 01/03/30: Fredrik Theander: Anadigms FPAA
30284: 01/03/31: Bertram Geiger: Re: Anadigms FPAA
30311: 01/04/02: ajd: Re: Anadigms FPAA
30288: 01/03/31: C.Schlehaus: Quartus in W2K System
30290: 01/03/31: Gonzalo Arana: Free VHDL PCI Interface?
30291: 01/03/31: bill: Student Foundation 1.5
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