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Threads Starting Jul 1998
10916: 98/07/01: <n4mwd@dont.spam.me.flinet.com>: Xlinx CPLD bitstream format
10917: 98/07/01: kash johal: ZERO NRE ASICs update
10918: 98/07/01: kash johal: ZER) NRE ASICS update
10923: 98/07/01: Botond Kardos: Power consumption question
10924: 98/07/01: Peter Alfke: Re: Power consumption question
10925: 98/07/01: Paul Taylor: Re: Power consumption question
10928: 98/07/03: Botond Kardos: Re: Power consumption question
10927: 98/07/02: Scott Paul Johnston: UPDATED ENGINEERING PAGE: Please Visit
10929: 98/07/04: <tiltonjones@my-dejanews.com>: Consultants
10930: 98/07/04: <msimon@tefbbs.com>: Re: Consultants
10945: 98/07/06: <jimmeans@my-dejanews.com>: Re: Consultants
10933: 98/07/04: APS: Re: Consultants
10937: 98/07/05: Steven K. Knapp: Re: Consultants
10951: 98/07/07: John: Re: Consultants
11021: 98/07/11: Austin Franklin: Re: Consultants
11034: 98/07/13: <pipjockey@my-dejanews.com>: Re: Consultants
10931: 98/07/04: Scott Paul Johnston: UPDATED ENGINEERING PAGE: Please Visit
10935: 98/07/05: C. R. Johnson: FPGA Programming Bitstream Compression
10936: 98/07/05: Alexander Sherstuk: Re: FPGA Bitstream Programming Compression
10939: 98/07/06: kash johal: FREE ASIC ESTIMATOR
10942: 98/07/06: Philip Freidin: Re: FREE ASIC ESTIMATOR
10940: 98/07/06: koh bongseok: Altera MAX+PLUS 8.1
10941: 98/07/06: koh bongseok: Altera MAX+PLUS 8.1
10952: 98/07/06: Steven K. Knapp: Re: Altera MAX+PLUS 8.1
10996: 98/07/09: Victor Levandovsky: Re: Altera MAX+PLUS 8.1 see in www.altera.com (nothing inside)
10943: 98/07/06: Walter Schweigart: How to download bitstream on a SUN ...
10944: 98/07/06: Paul Walker: Xilinx Foundation Frustartions
10954: 98/07/07: Peter: Re: Xilinx Foundation Frustartions
10970: 98/07/08: Rick Filipkiewicz: Re: Xilinx Foundation Frustartions
10979: 98/07/08: Peter: Re: Xilinx Foundation Frustartions
10982: 98/07/08: <pipjockey@my-dejanews.com>: Re: Xilinx Foundation Frustartions
10971: 98/07/07: Rickman: Re: Xilinx Foundation Frustartions
10976: 98/07/08: Paul Walker: Re: Xilinx Foundation Frustartions
10977: 98/07/08: Paul Walker: Re: Xilinx Foundation Frustartions
11005: 98/07/09: Nick Hartl: Re: Xilinx Foundation Frustartions
11007: 98/07/09: Ed McCauley: Re: Xilinx Foundation Frustartions
11011: 98/07/10: ems: Re: Xilinx Foundation Frustartions
11014: 98/07/10: Ed McCauley: Re: Xilinx Foundation Frustartions
10946: 98/07/06: <dfrevele@li.net>: Spartan S30 DOUT/SGCK4 pin
10974: 98/07/08: Philip Freidin: Re: Spartan S30 DOUT/SGCK4 pin
10991: 98/07/09: Allan Herriman: Re: Spartan S30 DOUT/SGCK4 pin
11001: 98/07/09: Philip Freidin: Re: Spartan S30 DOUT/SGCK4 pin
10947: 98/07/06: <dfrevele@li.net>: Configure with BIT file
10948: 98/07/06: Ed McCauley: Re: Configure with BIT file
10988: 98/07/08: Marcus Lankenau: Re: Configure with BIT file
10990: 98/07/08: Ed McCauley: Re: Configure with BIT file
11000: 98/07/09: Gareth Baron: Re: Configure with BIT file
11002: 98/07/09: Peter: Re: Configure with BIT file
11009: 98/07/10: Tony Cooper: Re: Configure with BIT file
11013: 98/07/10: Peter: Re: Configure with BIT file
10950: 98/07/07: Philip Freidin: Re: Configure with BIT file
10955: 98/07/07: Peter: Re: Configure with BIT file
10949: 98/07/06: Dominick Cafarelli: CRC's and PRBS in Paralell
10957: 98/07/07: Ed McCauley: Re: CRC's and PRBS in Paralell
11019: 98/07/11: Juan-Luis Lopez: Howto: CRC's and PRBS in Parallel
11035: 98/07/13: <jimmeans@my-dejanews.com>: Re: Howto: CRC's and PRBS in Parallel
11037: 98/07/14: <jhirbawi@yahoo.com>: Re: Howto: CRC's and PRBS in Parallel
10953: 98/07/07: Eugene Fleisher: Altera FPGA Downloader - ByteBlaster Replacement Works 1.8 - 5V
10956: 98/07/07: David Lin: Where to find gate-count information on some implementations?
10992: 98/07/09: <leslie.yip@asmpt.com>: Re: Where to find gate-count information on some implementations?
10958: 98/07/07: Bob Myers: Need to know Xilinx M1.4's routing times -- large(?) designs
10959: 98/07/07: Ray Andraka: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
10966: 98/07/07: Bob Myers: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
10960: 98/07/07: Ray Andraka: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
10961: 98/07/07: Ray Andraka: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
10962: 98/07/07: Ray Andraka: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
10963: 98/07/07: Ray Andraka: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
10964: 98/07/07: Ray Andraka: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
10965: 98/07/07: David Decker: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
10967: 98/07/07: Marc Boulais: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
10980: 98/07/08: Bob Myers: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
11020: 98/07/10: Thomas D. Tessier: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
11026: 98/07/12: Philip Freidin: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
11027: 98/07/12: Achim Gratz: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
11028: 98/07/12: Philip Freidin: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
11029: 98/07/13: Achim Gratz: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
10968: 98/07/07: Utku Ozcan: question on combinational logic synthesis for FPGA
10972: 98/07/07: Rickman: Re: question on combinational logic synthesis for FPGA
10975: 98/07/08: Paul Walker: Re: question on combinational logic synthesis for FPGA
10994: 98/07/09: Manfred Kraus: Re: question on combinational logic synthesis for FPGA
10998: 98/07/09: James Lee: Re: question on combinational logic synthesis for FPGA
11003: 98/07/09: Peter: Re: question on combinational logic synthesis for FPGA
11004: 98/07/09: Ed McCauley: Re: question on combinational logic synthesis for FPGA
10969: 98/07/07: David Brown: Xilinx 4085 FPGA Board
10973: 98/07/08: Erik de Castro Lopo: Orcad Express and Xilinx M1.4 TIMESPEC problems
10978: 98/07/08: Mike Lardner: SCSI Modeling
10981: 98/07/08: Milostnik: Simulation at powerup
10984: 98/07/08: Milostnik: Re: Simulation at powerup
10987: 98/07/08: Paul J. Menchini: Re: Simulation at powerup
10986: 98/07/08: Paul J. Menchini: Re: Simulation at powerup
10999: 98/07/09: ems: Re: Simulation at powerup
10983: 98/07/08: Jackie Meyer: papers sought, DRAM
10985: 98/07/08: Deependra Talla: Speed Vs Accuracy
10989: 98/07/08: <msimon@tefbbs.com>: Re: Speed Vs Accuracy
10995: 98/07/09: Keith Wootten: Xilinx 5200 pin swapping
10997: 98/07/09: Jordan Swartz: high-speed place and route
11006: 98/07/09: Rickman: Re: high-speed place and route
11008: 98/07/10: Tony Cooper: Re: high-speed place and route
11010: 98/07/10: Achim Gratz: Re: high-speed place and route
11049: 98/07/15: Jordan Swartz: Re: high-speed place and route
11050: 98/07/15: Jo Depreitere: Re: high-speed place and route
11052: 98/07/15: Jordan Swartz: Re: high-speed place and route
11059: 98/07/16: Jo Depreitere: Re: high-speed place and route
11017: 98/07/10: G. Herrmannsfeldt: Re: high-speed place and route
11046: 98/07/15: Philip Freidin: Re: high-speed place and route
11051: 98/07/15: Jordan Swartz: Re: high-speed place and route
11053: 98/07/15: Richard Iachetta: Re: high-speed place and route
11012: 98/07/10: Nabeel Shirazi: Research Position Available at Imperial College
11015: 98/07/10: Gabriel Margarit: is the code for XC4000E burned on it or in EEPROM ?
11016: 98/07/10: Ray Andraka: Re: is the code for XC4000E burned on it or in EEPROM ?
11018: 98/07/10: support: Xact 5.0xx and up speed file
11022: 98/07/11: <sharadm@my-dejanews.com>: 16550 UART model info req.
11023: 98/07/11: Gabriel Margarit: I need footprints for PCI & ISA (for Protel PCB)
11025: 98/07/11: Peter: Re: I need footprints for PCI & ISA (for Protel PCB)
11024: 98/07/12: Bill: $EARN MONEY FOR FREE$
11030: 98/07/13: Lev Razamat: Reed-Solomon encoding
11032: 98/07/13: Steven K. Knapp: Re: Reed-Solomon encoding
11038: 98/07/14: <notgetting@myaddress.com>: Re: Reed-Solomon encoding
11031: 98/07/13: Dave Sharples: PCB design @ half the cost
11033: 98/07/13: <richard_steinman@cmagroup.com>: Job- New York; Senior Engineer; Hardware, Imaging, Video, FPGA
11036: 98/07/13: Eric Ryherd: Dataio Chipwriter won't burn Altera EPC1 generated with Maxplus2 8.2 or greater???
11044: 98/07/14: Jerry Zdenek: Re: Dataio Chipwriter won't burn Altera EPC1 generated with Maxplus2 8.2 or greater???
11160: 98/07/21: TMItools: Re: Dataio Chipwriter won't burn Altera EPC1 generated with Maxplus2 8.2 or greater???
11190: 98/07/24: Nicolas Matringe: Re: Dataio Chipwriter won't burn Altera EPC1 generated with Maxplus2 8.2 or greater???
11039: 98/07/14: Yavuz Doganc: compile warning
11045: 98/07/15: Hans Lindkvist: Re: compile warning
11040: 98/07/14: Robert Myers: Found problem -> Re: Need to know Xilinx M1.4's routing times...
11041: 98/07/14: Stuart Clubb: Re: Found problem -> Re: Need to know Xilinx M1.4's routing times...
11048: 98/07/15: Bob Myers: Re: Found problem -> Re: Need to know Xilinx M1.4's routing times...
11042: 98/07/14: Doug Smith - Sun BOS Hardware: Quickturn users group
11043: 98/07/14: Khan Kibria: ASIC Design Service
11047: 98/07/15: <takanori_fujiki@usa.net>: Looking for useful "Shell Script" for HDL tools
11054: 98/07/15: Gareth Baron: Re: Shift Invarient Bit Transform
11055: 98/07/15: Brad Smallridge: Shift Invarient Bit Transform
11056: 98/07/15: Rickman: Re: Shift Invarient Bit Transform
11067: 98/07/16: Brad Smallridge: Re: Shift Invarient Bit Transform
11071: 98/07/16: Rickman: Re: Shift Invarient Bit Transform
11080: 98/07/17: Brad Smallridge: Re: Shift Invarient Bit Transform
11086: 98/07/18: <jhirbawi@yahoo.com>: Re: Shift Invarient Bit Transform
11090: 98/07/17: Rickman: Re: Shift Invarient Bit Transform
11107: 98/07/19: Brad Smallridge: Re: Shift Invarient Bit Transform
11110: 98/07/20: <jhirbawi@yahoo.com>: Re: Shift Invarient Bit Transform
11111: 98/07/19: Rickman: Re: Shift Invarient Bit Transform
11157: 98/07/21: Daniel Lang: Re: Shift Invarient Bit Transform
11161: 98/07/21: Jorge Jure Zaninovich: Re: Shift Invarient Bit Transform
11073: 98/07/17: Achim Gratz: Re: Shift Invarient Bit Transform
11075: 98/07/17: Koenraad Schelfhout VH14 8993: Re: Shift Invarient Bit Transform
11076: 98/07/17: Ray Andraka: Re: Shift Invarient Bit Transform
11057: 98/07/15: Ray Andraka: Re: Shift Invarient Bit Transform
11058: 98/07/15: Ray Andraka: Re: Shift Invarient Bit Transform
11062: 98/07/16: Ray Andraka: Re: Shift Invarient Bit Transform
11066: 98/07/16: Brian Drummond: Re: Shift Invarient Bit Transform
11222: 98/07/27: Thor Arne Johansen: Re: Shift Invarient Bit Transform
11060: 98/07/16: Pawel E. Tomaszewicz: Partial reprogramming
11087: 98/07/17: Ray Andraka: Re: Partial reprogramming
11121: 98/07/20: Don Husby: Re: Partial reprogramming
11124: 98/07/20: Ray Andraka: Re: Partial reprogramming
11125: 98/07/20: Tim Tyler: Re: Partial reprogramming
11150: 98/07/21: Steven K. Knapp: Re: Partial reprogramming
11151: 98/07/21: Pasquale Corsonello: Re: Partial reprogramming
11158: 98/07/21: Tim Tyler: Re: Partial reprogramming
11091: 98/07/17: Rickman: Re: Partial reprogramming
11061: 98/07/16: Andrew Phillips: ++ TMS320C6x DSP info website ++
11063: 98/07/16: Steven W Schlosser: Floorplanning Intro?
11065: 98/07/16: Ray Andraka: Re: Floorplanning Intro?
11069: 98/07/16: Carl Christensen: Re: Floorplanning Intro?
11072: 98/07/17: Ray Andraka: Re: Floorplanning Intro?
11082: 98/07/17: GTE news: Re: Floorplanning Intro?
11083: 98/07/17: Jan Gray: Re: Floorplanning Intro?
11085: 98/07/17: Ray Andraka: Re: Floorplanning Intro?
11088: 98/07/18: Austin Franklin: Re: Floorplanning Intro?....seems to be HDL v schematics sort of ;-)
11092: 98/07/17: Rickman: Re: Floorplanning Intro?....seems to be HDL v schematics sort of ;-)
11100: 98/07/18: John McCluskey: Re: Floorplanning Intro: Here's how I floorplan in VHDL
11104: 98/07/19: APS: Re: Floorplanning Intro?....seems to be HDL v schematics sort of ;-)
11105: 98/07/19: APS: Re: Floorplanning Intro?....seems to be HDL v schematics sort of ;-)
11102: 98/07/19: ems: Re: Floorplanning Intro?
11077: 98/07/17: Steve Gross: Re: Floorplanning Intro?
11070: 98/07/16: Steven W Schlosser: Re: Floorplanning Intro?
11064: 98/07/16: keiser anthony lynn: Bitfile for Xilinx PCI ping
11068: 98/07/16: rich katz: Registration for 1998 Military and Aerospace Applications of Programmable Devices and Technologies Conference
11074: 98/07/17: Greenwood Systems: VHDL contract company
11078: 98/07/17: mdisman: PLD Design Center
11079: 98/07/17: Lawrence Hau: FPAG -> Memory & CRC
11081: 98/07/17: The Employment Solution: FPGA Designers ?????
11084: 98/07/17: King ComputerSearch: Pre-IPO - Lead Hardware Engineer - Board Level/SONET - Marlborough, MA
11089: 98/07/18: Austin Franklin: Too much advertising in this news group?
11095: 98/07/18: Richard B. Katz: Re: Too much advertising in this news group?
11096: 98/07/18: Austin Franklin: Re: Too much advertising in this news group?
11101: 98/07/19: ems: Re: Too much advertising in this news group?
11106: 98/07/19: Jan Gray: Re: Too much advertising in this news group?
11109: 98/07/19: Gary Helbig: Re: Too much advertising in this news group?
11112: 98/07/20: Rickman: Re: Too much advertising in this news group?
11108: 98/07/20: Thomas A. Coonan: Re: Too much advertising in this news group?
11141: 98/07/21: Greenwood Systems: Re: Too much advertising in this news group?
11169: 98/07/22: Jamie Lokier: Re: Too much advertising in this news group?
11193: 98/07/24: Austin Franklin: Re: Too much advertising in this news group?
11093: 98/07/18: <takanori_fujiki@usa.net>: How can I do Gate Level Simulation by Verilog-XL after mapping by ALTERA MAX +plus II ?
11094: 98/07/18: The Employment Solution: FPGA Designer
11097: 98/07/18: George Pontis: Xilinx Dynatext and NTFS ?
11114: 98/07/20: Rudolf Muehlenbein: Re: Xilinx Dynatext and NTFS ?
11117: 98/07/20: Ray Andraka: Re: Xilinx Dynatext and NTFS ?
11200: 98/07/24: Terry Fraser: Re: Xilinx Dynatext and NTFS ?
11098: 98/07/18: <newtech@my-dejanews.com>: Jobs for FPGA Designers/Engineers
11099: 98/07/18: <newtech@my-dejanews.com>: Jobs for FPGA Hardware Designers/Engineers
11103: 98/07/19: APS: CRC Implementation
11115: 98/07/20: ems: Re: CRC Implementation
11130: 98/07/20: Gareth Baron: Re: CRC Implementation
11133: 98/07/21: David R Brooks: Re: CRC Implementation
11113: 98/07/20: <leslie.yip@asmpt.com>: How to write a VHDL counter of up & down
11132: 98/07/20: ems: Re: How to write a VHDL counter of up & down
11134: 98/07/20: Rickman: Re: How to write a VHDL counter of up & down
11148: 98/07/21: Ray Andraka: Re: How to write a VHDL counter of up & down
11162: 98/07/21: Rickman: Re: How to write a VHDL counter of up & down
11140: 98/07/21: M.Stekelenburg: Re: How to write a VHDL counter of up & down
11163: 98/07/22: Paul J. Menchini: Re: How to write a VHDL counter of up & down
11170: 98/07/22: Ray Andraka: Re: How to write a VHDL counter of up & down
11165: 98/07/22: <leslie.yip@asmpt.com>: Re:Add info-How to write a VHDL counter of up & down
11166: 98/07/22: <leslie.yip@asmpt.com>: Re:Add info-How to write a VHDL counter of up & down
11221: 98/07/27: Mark Purcell: Re: How to write a VHDL counter of up & down
11116: 98/07/20: Bob Myers: Need info -> implementing high-speed multipliers
11122: 98/07/20: Ray Andraka: Re: Need info -> implementing high-speed multipliers
11118: 98/07/20: Edward Pickering: Old Contace Information
11123: 98/07/20: Ray Andraka: Re: Old Contace Information
11127: 98/07/20: Rickman: Re: Old Contace Information
11129: 98/07/20: Philip Freidin: Re: Old Contace Information
11119: 98/07/20: Edward Pickering: Old Contace Information
11120: 98/07/20: Edward Pickering: Old Contace Information
11126: 98/07/20: Neil Carrington: Asynchronous FIFO's for XILINX PCI
11128: 98/07/20: Louis Zhang: Hierachical signal/port trace in Maxplus2 simulation
11135: 98/07/21: Paul Teagle: Re: Hierachical signal/port trace in Maxplus2 s
11131: 98/07/20: Reetinder P. S. Sidhu: XC6200 Behavioral Synthesis?
11232: 98/07/28: SUDHEESH MADHAVAN: Re: XC6200 Behavioral Synthesis?
11136: 98/07/21: <M.Vasilko@computer.org>: ANNOUNCE: Dynamically Reconfigurable Hardware WWW Library
11137: 98/07/21: <leslie.yip@asmpt.com>: Any VHDL counter with up & down functions
11138: 98/07/20: Rickman: Re: Any VHDL counter with up & down functions
11142: 98/07/21: ems: Re: Any VHDL counter with up & down functions
11180: 98/07/22: Bruce Nepple: Re: Any VHDL counter with up & down functions
11139: 98/07/21: Andrew Dyer: problems in SDF files from foundation 1.4?
11143: 98/07/21: ems: Re: problems in SDF files from foundation 1.4?
11152: 98/07/21: Andrew Dyer: Re: problems in SDF files from foundation 1.4?
11144: 98/07/21: John Nangreaves: Wanted: CPLD Primer
11149: 98/07/21: Steven K. Knapp: Re: Wanted: CPLD Primer
11159: 98/07/21: Dave Vanden Bout: Re: Wanted: CPLD Primer
11145: 98/07/21: Freiberger Wolfgang: EEPROM <> XC1700 ?
11146: 98/07/21: Wagner: Re: EEPROM <> XC1700 ?
11147: 98/07/21: Krzysztof Rozniak: Re: EEPROM <> XC1700 ?
11153: 98/07/21: Marcus Lankenau: problems with xilinx foundation
11154: 98/07/21: Flavio Miana de Paula: XC6200DS doubt/problem
11155: 98/07/21: <mbitzko@my-dejanews.com>: Symbol Generation from FPGA Compiler Reports
11156: 98/07/21: <mbitzko@my-dejanews.com>: Schematic Symbol Generation
11179: 98/07/22: Andy Peters: Re: Schematic Symbol Generation
11181: 98/07/22: Ray Andraka: Re: Schematic Symbol Generation
11185: 98/07/23: Gareth Baron: Re: Schematic Symbol Generation
11198: 98/07/24: Joe Brunsberger: Re: Schematic Symbol Generation
11194: 98/07/24: Austin Franklin: Re: Schematic Symbol Generation
11206: 98/07/25: Austin Franklin: Re: Schematic Symbol Generation
11211: 98/07/26: Hamish Moffatt: Re: Schematic Symbol Generation
11241: 98/07/29: Gareth Baron: Re: Schematic Symbol Generation
11258: 98/07/31: Austin Franklin: Re: Schematic Symbol Generation
11269: 98/07/31: Jamie Lokier: Re: Schematic Symbol Generation
11164: 98/07/21: MHB: Aldec's Active-VHDL Behavorial Simulator-Thanx
11167: 98/07/21: Steven K. Knapp: Re: Aldec's Active-VHDL Behavorial Simulator-Thanx
11177: 98/07/22: Stuart Clubb: Re: Aldec's Active-VHDL Behavorial Simulator-Thanx
11173: 98/07/22: <pipjockey@my-dejanews.com>: Re: Aldec's Active-VHDL Behavorial Simulator-Thanx
11183: 98/07/22: Rickman: Re: Aldec's Active-VHDL Behavorial Simulator-Thanx
11168: 98/07/22: Erik Lins: unknown speedgrade question
11171: 98/07/22: Ray Andraka: Re: unknown speedgrade question
11172: 98/07/22: Ray Andraka: Re: unknown speedgrade question
11175: 98/07/22: Philip Freidin: Re: unknown speedgrade question
11174: 98/07/22: Jonas Thor: FFT in Xilinx FPGA
11176: 98/07/22: Reetinder P. S. Sidhu: Re: FFT in Xilinx FPGA
11178: 98/07/23: Jim Hearne: Logic Lab Gal Programmer
11182: 98/07/23: ACS Tran: AD: Reading Secured Devices
11184: 98/07/23: <bonics@my-dejanews.com>: C- interface
11212: 98/07/26: APS: Re: C- interface
11186: 98/07/23: Ed Perez: IT Professionals - Join the NetVital Survey and make a difference
11187: 98/07/23: Vitit Kantabutra: High-radix division
11199: 98/07/24: Medical Electronics Lab: Re: High-radix division
11188: 98/07/24: Wade D. Peterson: Silicore VHDL 8-bit RISC uC core for FPGA
11195: 98/07/24: Austin Franklin: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11202: 98/07/25: jim granville: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11203: 98/07/24: Wade D. Peterson: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11316: 98/08/04: Eric Ryherd: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11329: 98/08/05: Hans: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11335: 98/08/05: Wade D. Peterson: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11339: 98/08/05: Hans: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11345: 98/08/05: Wade D. Peterson: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11354: 98/08/05: Richard B. Katz: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11357: 98/08/06: Stephen Maudsley: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11359: 98/08/06: Richard B. Katz: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11369: 98/08/07: Wade D. Peterson: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11372: 98/08/07: Richard B. Katz: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11385: 98/08/09: jim granville: Re: Radiation and Relaibility
11391: 98/08/09: Wade D. Peterson: Re: Radiation and Relaibility
11402: 98/08/10: rk: Re: Radiation and Relaibility
11375: 98/08/07: Austin Franklin: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11205: 98/07/25: Thomas A. Coonan: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11189: 98/07/24: <benjamin.carrion-schaefer@hl.siemens.de>: Interface
11191: 98/07/24: Eugene Fleisher: Altera FPGA/EPLD Downloader that works with any voltage (1.8 - 5 V)
11192: 98/07/24: iccra: [***] SRAM Controller
11196: 98/07/24: <vesta7x@earthling.net>: ORCAD 3
11197: 98/07/24: <benjamin.carrion-schaefer@hl.siemens.de>: FPGA board interface
11201: 98/07/24: J. Khatib: CPLD vs. FPGA
11216: 98/07/26: Steven K. Knapp: Re: CPLD vs. FPGA
11204: 98/07/24: A. Spanias: CALL FOR PAPERS - INDUSTRY DSP FORUM AT ICASSP -99
11207: 98/07/24: Dogma: Cheap FPGA...
11208: 98/07/25: <satish@my-dejanews.com>: Caluclation of gates in FPGA
11215: 98/07/26: <yhirbawi@my-dejanews.com>: Re: Caluclation of gates in FPGA
11240: 98/07/29: Philip Freidin: Re: Caluclation of gates in FPGA
11245: 98/07/30: Rickman: Re: Caluclation of gates in FPGA
11308: 98/08/03: Nick Hartl: Re: Caluclation of gates in FPGA
11315: 98/08/04: Brian Dipert: Re: Caluclation of gates in FPGA
11209: 98/07/26: Eddie Ng: Delay Element for async design.
11210: 98/07/26: YetAnotherLurker - Rickman: Re: Delay Element for async design.
11214: 98/07/26: Eddie Ng: Re: Delay Element for async design.
11247: 98/07/30: Douglas Beattie Jr.: Asynchronous Building Blocks?
11248: 98/07/30: Achim Gratz: Re: Asynchronous Building Blocks?
11213: 98/07/26: Wade D. Peterson: Re: Delay Element for async design.
11223: 98/07/27: Don Husby: Re: Delay Element for async design.
11268: 98/07/31: Bruce Nepple: Delay Element in XC4000XL (was Re: Delay Element for async design.)
11307: 98/08/03: Nick Hartl: Re: Delay Element for async design.
11310: 98/08/04: Andy McClelland: Re: Delay Element for async design.
11333: 98/08/05: ems: Re: Delay Element for async design.
11352: 98/08/06: Allan Herriman: Re: Delay Element for async design.
11368: 98/08/06: Rickman: Re: Delay Element for async design.
11370: 98/08/07: ems: Re: Delay Element for async design.
11377: 98/08/07: Peter Alfke: Re: Delay Element for async design.
11217: 98/07/27: <by_the_lake@jboat.com>: When did You last give Your wife a romantic holiday?
11218: 98/07/27: Philip Freidin: FloorPlanning with some examples
11219: 98/07/27: Tim Forcer: ANNOUNCE: Design Entry Workshop
11220: 98/07/27: Paul Oh: [Q] motor control onto an FPGA
11224: 98/07/28: Thomas A. Coonan: Re: [Q] motor control onto an FPGA
11231: 98/07/28: Andy Peters: Re: [Q] motor control onto an FPGA
11319: 98/08/04: Ray Andraka: Re: [Q] motor control onto an FPGA
11320: 98/08/04: Andy Peters: Re: [Q] motor control onto an FPGA
11337: 98/08/05: Ray Andraka: Re: [Q] motor control onto an FPGA
11355: 98/08/06: <leslie.yip@asmpt.com>: Re: [Q] motor control onto an FPGA
11321: 98/08/04: Steven J. Ackerman: Re: [Q] motor control onto an FPGA
11361: 98/08/06: <tronsmith@my-dejanews.com>: Re: [Q] motor control onto an FPGA
11225: 98/07/28: Masononyx: Get Rich now
11226: 98/07/28: GuiWoo,KIM: [Q]ALTERA DEVICE - EPF10K10LC84-4 ??
11227: 98/07/28: ems: Async design/minimum prop delays
11229: 98/07/28: Steven K. Knapp: Re: Async design/minimum prop delays
11384: 98/08/08: Simon Ramirez: Re: Async design/minimum prop delays
11228: 98/07/28: ADM: UK Graduate required as Sales Engineer
11230: 98/07/28: <bonics@my-dejanews.com>: leapfrog wavform
11264: 98/07/31: Loek Frederiks: Re: leapfrog wavform
11233: 98/07/29: Imanuddin Amril Account: TRISTATE in FPGA
11234: 98/07/29: Glenn Eng: Re: TRISTATE in FPGA
11237: 98/07/29: Ed McCauley: Re: TRISTATE in FPGA
11239: 98/07/29: Rickman: Re: TRISTATE in FPGA
11238: 98/07/29: Rickman: Re: TRISTATE in FPGA
11244: 98/07/29: Phil Hays: Re: TRISTATE in FPGA
11236: 98/07/29: Scherer Anton: Re: TRISTATE in FPGA
11256: 98/07/31: <leslie.yip@asmpt.com>: Re: TRISTATE in FPGA
11270: 98/07/31: Jamie Lokier: Re: TRISTATE in FPGA
11356: 98/08/06: Imanuddin Amril Account: Re: TRISTATE in FPGA
11235: 98/07/29: <andrew.nelson@cdott.com>: low power FPGAs
11250: 98/07/30: Peter: Re: low power FPGAs
11242: 98/07/29: Rupert: how much ? prices of Xilinx chips
11280: 98/08/01: Gerald Coe: Re: how much ? prices of Xilinx chips
11282: 98/08/01: Simon Ramirez: Re: how much ? prices of Xilinx chips
11284: 98/08/02: Wade D. Peterson: Re: how much ? prices of Xilinx chips
11317: 98/08/04: Jeff: Re: how much ? prices of Xilinx chips
11288: 98/08/02: Austin Franklin: Re: how much ? prices of Xilinx chips
11289: 98/08/02: Jacob W Janovetz: Re: how much ? prices of Xilinx chips
11290: 98/08/02: Steven K. Knapp: Re: how much ? prices of Xilinx chips
11294: 98/08/02: Ray Andraka: Re: how much ? prices of Xilinx chips
11318: 98/08/04: tom curran: Re: how much ? prices of Xilinx chips
11243: 98/07/29: Andy Peters: Re: How to connect my reset with GSR at Xilinx-FPGAs - response and Additional questions!
11246: 98/07/30: Rickman: Re: How to connect my reset with GSR at Xilinx-FPGAs - response and Additional questions!
11254: 98/07/30: Andy Peters: Re: How to connect my reset with GSR at Xilinx-FPGAs - response and Additional questions!
11274: 98/07/31: Rickman: Re: How to connect my reset with GSR at Xilinx-FPGAs - response and Additional questions!
11306: 98/08/03: Andy Peters: Re: How to connect my reset with GSR at Xilinx-FPGAs - response and Additional questions!
11252: 98/07/30: ems: Re: How to connect my reset with GSR at Xilinx-FPGAs - response and Additional questions!
11253: 98/07/30: Andy Peters: Re: How to connect my reset with GSR at Xilinx-FPGAs - response and Additional questions!
11255: 98/07/30: Rickman: Re: How to connect my reset with GSR at Xilinx-FPGAs - response and Additional questions!
11259: 98/07/31: Thomas Reinemann: Re: How to connect my reset with GSR at Xilinx-FPGAs - response and Additional questions!
11249: 98/07/30: <bonics@my-dejanews.com>: VHDL code
11251: 98/07/30: H. Ploog: On how to protect your IP
11257: 98/07/31: richard lee: How to use fpga do a programmable clock generator(50hz to 50k )
11263: 98/07/31: Leon Heller: Re: How to use fpga do a programmable clock generator(50hz to 50k )
11260: 98/07/31: iccra: [****] VHDL Compile Error ( +, & Operator )
11299: 98/08/03: Mark Purcell: Re: [****] VHDL Compile Error ( +, & Operator )
11301: 98/08/03: Jacob W Janovetz: Re: [****] VHDL Compile Error ( +, & Operator )
11325: 98/08/04: Rickman: Re: [****] VHDL Compile Error ( +, & Operator )
11261: 98/07/31: Mark: Symbols, design changes, pin changes
11265: 98/07/31: Ed Peterson: Re: Symbols, design changes, pin changes
11266: 98/07/31: Ed Peterson: Re: Symbols, design changes, pin changes
11267: 98/07/31: Ed Peterson: Re: Symbols, design changes, pin changes
11275: 98/07/31: Rickman: Re: Symbols, design changes, pin changes
11287: 98/08/02: Austin Franklin: Re: Symbols, design changes, pin changes
11292: 98/08/02: Philip Freidin: Re: Symbols, design changes, pin changes
11342: 98/08/05: Austin Franklin: Re: Symbols, design changes, pin changes
11295: 98/08/02: Richard B. Katz: Re: Symbols, design changes, pin changes
11296: 98/08/03: Alex Beynon: Re: Symbols, design changes, pin changes
11300: 98/08/03: Mark: Re: Symbols, design changes, pin changes
11324: 98/08/04: Rickman: Re: Symbols, design changes, pin changes
11262: 98/07/31: Jackie Meyer: register for IEEE memory workshop
11271: 98/07/31: Jamie Lokier: Altera tools on Linux
11273: 98/07/31: Uwe Bonnes: Re: Altera tools on Linux
11277: 98/08/01: Jamie Lokier: Re: Altera tools on Linux
11272: 98/07/31: Simon Ramirez: PCI Core In FPGA
11278: 98/08/01: Stuart Clubb: Re: PCI Core In FPGA
11286: 98/08/02: Austin Franklin: Re: PCI Core In FPGA
11293: 98/08/02: Simon Ramirez: Re: PCI Core In FPGA
11312: 98/08/04: Austin Franklin: Re: PCI Core In FPGA
11331: 98/08/05: John Chambers: Re: PCI Core In FPGA
11351: 98/08/06: Paul Teagle: Re: PCI Core In FPGA
11364: 98/08/06: alz: Re: PCI Core In FPGA
11365: 98/08/06: Austin Franklin: Re: PCI Core In FPGA
11367: 98/08/06: Al Zimmerman: Re: PCI Core In FPGA
11378: 98/08/07: Darrell Ray: Re: PCI Core In FPGA
11366: 98/08/06: Barry Brown: Re: PCI Core In FPGA
11323: 98/08/05: Zoltan Kocsi: Re: PCI Core In FPGA
11330: 98/08/05: Al Zimmerman: Re: PCI Core In FPGA
11341: 98/08/05: Austin Franklin: Re: PCI Core In FPGA
11346: 98/08/05: alz: Re: PCI Core In FPGA
11353: 98/08/06: Austin Franklin: Re: PCI Core In FPGA
11358: 98/08/06: ems: Re: PCI Core In FPGA
11363: 98/08/06: alz: Re: PCI Core In FPGA
11371: 98/08/07: ems: Re: PCI Core In FPGA
11376: 98/08/07: Al Zimmerman: Re: PCI Core In FPGA
11396: 98/08/10: ems: Re: PCI Core In FPGA
11379: 98/08/07: Austin Franklin: Re: PCI Core In FPGA
11395: 98/08/10: ems: Re: PCI Core In FPGA
11347: 98/08/05: alz: Re: PCI Core In FPGA
11348: 98/08/05: alz: Re: PCI Core In FPGA
11349: 98/08/05: alz: Re: PCI Core In FPGA
11350: 98/08/05: alz: Re: PCI Core In FPGA
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