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Threads Starting Nov 1996
4460: 96/11/01: Vincent Himpe: What is the fastest fpga for ...
4461: 96/11/01: Thomas J. Loftus: Re: What is the fastest fpga for ...
4464: 96/11/01: <waters@npss.enet.dec.com>: Re: What is the fastest fpga for ...
4466: 96/11/01: Joseph H Allen: Re: What is the fastest fpga for ...
4467: 96/11/01: Kevin D. Drucker: Re: What is the fastest fpga for ...
4472: 96/11/02: Philip Freidin: Re: What is the fastest fpga for ...
4468: 96/11/01: Austin Franklin: Re: What is the fastest fpga for ...
4496: 96/11/05: Lance Gin: Re: What is the fastest fpga for ...
4471: 96/11/01: Peter Alfke: Re: What is the fastest fpga for ...
4478: 96/11/03: Peter Alfke: Re: What is the fastest fpga for ...
4483: 96/11/04: Don Husby: Re: What is the fastest fpga for ...
4497: 96/11/06: Matthew Harding: Re: What is the fastest fpga for ...
4502: 96/11/06: bob elkind: Re: What is the fastest fpga for ...
4522: 96/11/08: David Emrich: Re: What is the fastest fpga for ...
4462: 96/11/01: RCI111: FPGA Demonstration Board
4463: 96/11/01: Eric Huber: Position Available - Programmable logic design
4469: 96/11/01: Scott Kroeger: XACT under WinNT is very slow
4475: 96/11/03: Peter - one extra v to stop junk mail: Re: XACT under WinNT is very slow
4476: 96/11/03: Scott Kroeger: Re: XACT under WinNT is very slow
4499: 96/11/06: Peter: Re: XACT under WinNT is very slow
4477: 96/11/03: Austin Franklin: Re: XACT under WinNT is very slow
4500: 96/11/06: Peter: Re: XACT under WinNT is very slow
4504: 96/11/06: Austin Franklin: Re: XACT under WinNT is very slow
4510: 96/11/07: Peter: Re: XACT under WinNT is very slow
4470: 96/11/02: <sbaker@best.com>: Online Panel - Users tell Vendors
4479: 96/11/03: 1997 International Symposium on Physical Design: CFP: 1997 Intl. Symp. on Physical Design, April 14-16, CA
4480: 96/11/04: Bert THOMPSON: FPGA references for beginner?
4485: 96/11/04: Amarpreet Singh Geadhoke: Re: FPGA references for beginner?
4481: 96/11/04: Craig Slorach: Info on FPGA Internal Architecture/ Programming
4491: 96/11/05: Rick Filipkiewicz: Re: Info on FPGA Internal Architecture/ Programming
4507: 96/11/06: Peter Alfke: Re: Info on FPGA Internal Architecture/ Programming
4513: 96/11/07: Don Husby: Re: Info on FPGA Internal Architecture/ Programming
4525: 96/11/08: Peter Alfke: Re: Info on FPGA Internal Architecture/ Programming
4530: 96/11/09: Mike Ciholas: Xilinx and cost of tools
4533: 96/11/10: Peter: Re: Xilinx and cost of tools
4534: 96/11/10: <timolmst@cyberramp.net>: Re: Xilinx and cost of tools
4535: 96/11/10: Erik Widding: Re: Xilinx and cost of tools
4551: 96/11/13: Peter: Re: Xilinx and cost of tools
4566: 96/11/14: Mike Ciholas: Re: Xilinx and cost of tools
4537: 96/11/10: Lance Gin: Re: Xilinx and cost of tools
4526: 96/11/08: Brad Taylor: Re: Info on FPGA Internal Architecture/ Programming
4521: 96/11/08: Tom Bowns: Re: Info on FPGA Internal Architecture/ Programming
4528: 96/11/08: Peter Alfke: Re: Info on FPGA Internal Architecture/ Programming
4540: 96/11/11: Jonathan Buller: Re: Info on FPGA Internal Architecture/ Programming
4505: 96/11/06: Don Husby: Re: Info on FPGA Internal Architecture/ Programming
4512: 96/11/07: Colin Carruthers: Re: Info on FPGA Internal Architecture/ Programming
4531: 96/11/10: Brian Drummond: Re: Info on FPGA Internal Architecture/ Programming
4532: 96/11/10: Zoltan Kocsi: Re: Info on FPGA Internal Architecture/ Programming
4482: 96/11/04: Aage Farstad: ORCA Configuration
4486: 96/11/05: Beau Schwabe: Fastest way to get started??
4487: 96/11/05: Piet du Toit: Re: XACT under WinNT is very slow
4490: 96/11/05: Scott Kroeger: Re: XACT under WinNT is very slow
4713: 96/12/05: Marc Baker: Re: XACT under WinNT is very slow
4723: 96/12/06: Scott Kroeger: Re: XACT under WinNT is very slow
4488: 96/11/05: Jens Weigle: UART FOR FPGAS
4493: 96/11/05: Peter Alfke: Re: UART FOR FPGAS
4494: 96/11/05: Brad Taylor: Re: UART FOR FPGAS
4511: 96/11/07: Peter: Re: UART FOR FPGAS
4539: 96/11/11: Burke Baumann: Re: UART FOR FPGAS
4545: 96/11/12: Peter: Re: UART FOR FPGAS
4547: 96/11/12: Jason T. Wright: Re: UART FOR FPGAS
4550: 96/11/13: Peter: Re: UART FOR FPGAS
4501: 96/11/06: Peter: Re: UART FOR FPGAS
4563: 96/11/13: Steven K. Knapp: Re: UART FOR FPGAS
4565: 96/11/14: Gareth Baron: Re: UART FOR FPGAS
4586: 96/11/18: <peter8888844@gggggserve.com>: Re: UART FOR FPGAS
4562: 96/11/13: Steven K. Knapp: Re: UART FOR FPGAS
4489: 96/11/05: Kimiko Nemoto: recent FPGA boards ?
4564: 96/11/13: Steven K. Knapp: Re: recent FPGA boards ?
4492: 96/11/05: Stephen Boltinghouse: Just try this, it will work
4572: 96/11/15: Roger Grondin: Re: Just try this, it will work
4495: 96/11/06: Jeffrey C. Marden: Actel Designer and Win NT 4.0
4520: 96/11/08: Tom Bowns: Re: Actel Designer and Win NT 4.0
4541: 96/11/11: Eric Pearson: Re: Actel Designer and Win NT 4.0
4498: 96/11/06: Manolis Stratakis: PCB Handling of chip packages greater than 100 pins?
4503: 96/11/06: K Goldman: Re: PCB Handling of chip packages greater than 100 pins?
4516: 96/11/08: Calum MacGregor: Re: PCB Handling of chip packages greater than 100 pins?
4523: 96/11/08: RSES: Re: PCB Handling of chip packages greater than 100 pins?
4506: 96/11/06: Keith E. Henry: References - FPGA to ASIC Conversion Vendors
4509: 96/11/06: Michael Holley: A new vendor for Xilinx parts.
4514: 96/11/07: Mike Kopp: VHDL synthesis tools?
4515: 96/11/08: Regina Steurer-Hall: Altera contract in Orange County
4517: 96/11/08: Saouter Yannick: Integration, the VLSI journal
4519: 96/11/08: Giunt: behavioural VHDL "BUS MATCHING"
4524: 96/11/08: Kevin T. Hawes: US FPGA Engineers
4527: 96/11/08: <richard_steinman@cmagroup.com>: Upstate NY; Senior Engineer Wanted; FPGA; High Speed Digital
4529: 96/11/08: Todd Peterson: Electronics/ Microcontroller On-Line Electronics Resource Directory
4536: 96/11/10: 1997 International Symposium on Physical Design: CFP: 1997 Intl. Symp. on Physical Design, April 14-16, CA
4542: 96/11/11: Nanda Katikaneni: Suggest an interesting but manageable undergrad project.
4544: 96/11/12: Steve Wiseman: Re: Suggest an interesting but manageable undergrad project.
4543: 96/11/12: Rick Filipkiewicz: Xilinx 9500 CPLDs
4546: 96/11/12: <sbaker@best.com>: Reconfig interactive report
4548: 96/11/13: Ketan Poladia: EDIF to BLIF format conversion.
4549: 96/11/13: Michael Ismert: AAL5 SAR Design?
4559: 96/11/13: Lawrence Butcher: Re: AAL5 SAR Design?
4560: 96/11/13: Brad Taylor: Re: AAL5 SAR Design?
4639: 96/11/25: alain arnaud: Re: AAL5 SAR Design?
4552: 96/11/13: Peter: Re: Digital PLL or Sample Rate Multiplier
4637: 96/11/24: Peter Alfke: Re: Digital PLL or Sample Rate Multiplier
4553: 96/11/13: Dean Dunnigan: Fast FPGA
4561: 96/11/13: Steven K. Knapp: Re: Fast FPGA
4569: 96/11/15: Julian Cox: Re: Fast FPGA
4592: 96/11/19: Rick Filipkiewicz: Re: Fast FPGA
4554: 96/11/13: Dave Ingram: Digital PLL or Sample Rate Multiplier
4555: 96/11/13: Vivek Sagdeo: (no subject)
4556: 96/11/13: Vivek Sagdeo: Re: (no subject) - Comprehensive Verilog Training Dec 3-5 and Jan 7-9 - Silicon Valley
4557: 96/11/13: Jackie Meyer: CFP Memory Workshop
4558: 96/11/13: Samuel Stammbach: Looking for a multiplier
4567: 96/11/15: Jason Tayles: Job Post 2 Hardware Engineers Needed VHDL, FPGA $80
4568: 96/11/15: Lindo St Angel: The best timing diagram editor/simulator?
4595: 96/11/19: David Pashley: Re: The best timing diagram editor/simulator?
4598: 96/11/19: David Fura: Re: The best timing diagram editor/simulator?
4570: 96/11/15: <richard_steinman@cmagroup.com>: Job; Upstate NY; Medical Imaging; FPGA; High Speed Digital; Altera
4571: 96/11/15: Vincent Rowley: VHDL code editor for Windows NT.
4578: 96/11/17: Crystal Harvey: Re: VHDL code editor for Windows NT.
4607: 96/11/20: Mike Harrison: Re: VHDL code editor for Windows NT.
4626: 96/11/22: Henning E. Larsen: Re: VHDL code editor for Windows NT.
4628: 96/11/22: VHDL Technology Group: Re: VHDL code editor for Windows NT.
4613: 96/11/21: Rynier van der Watt: Re: VHDL code editor for Windows NT.
4617: 96/11/21: John Maher: Re: VHDL code editor for Windows NT.
4649: 96/11/25: Kevin Steele: Re: VHDL code editor for Windows NT.
4573: 96/11/16: Chris Hart: VHDL adder: how do I get at the carry bit?
4580: 96/11/18: Austin Franklin: Re: VHDL adder: how do I get at the carry bit?
4582: 96/11/18: Andreas Wehr: Re: VHDL adder: how do I get at the carry b
4588: 96/11/18: John L. Smith: Re: VHDL adder: how do I get at the carry bit?
4672: 96/11/27: Chris Hart: Re: VHDL adder: how do I get at the carry bit?
4583: 96/11/18: Ted Boydston: Re: VHDL adder: how do I get at the carry bit?
4576: 96/11/16: Todd Peterson: Electronics Directory
4577: 96/11/16: Ketan Poladia: EDIF to BLIF
4579: 96/11/17: geof: Re: Just try this SCAM FOR $$$$
4581: 96/11/18: Steven Esau: Asymetrix Embraces KaiZenWare
4644: 96/11/25: Philip Freidin: Re: Asymetrix Embraces KaiZenWare
4584: 96/11/18: Markus Wannemacher: GEC Plessey, Toshiba, PlusLogic FPGAs?
4585: 96/11/18: Ray Andraka: Re: GEC Plessey, Toshiba, PlusLogic FPGAs?
4590: 96/11/19: P Nibbs: Advantage of third party software?
4597: 96/11/19: <timolmst@cyberramp.net>: Re: Advantage of third party software?
4604: 96/11/20: Stefan Doll: Re: Advantage of third party software?
4603: 96/11/20: David Pashley: Re: Advantage of third party software?
4593: 96/11/19: Brian P. Bailey: BREAKTHROUGH COMPUTER SYSTEM TO BE INTRODUCED ON DEC 2
4594: 96/11/19: David Decker: MatLab is Great for DSP test vectors
4596: 96/11/19: Steve Gross: Configuring Xilinx XC4000 device in Asynch. Peripheral Mode
4602: 96/11/20: Philip Freidin: Re: Configuring Xilinx XC4000 device in Asynch. Peripheral Mode
4599: 96/11/19: <love>: >>> ARE YOU READY FOR LOVE? <<<
4600: 96/11/20: P Nibbs: Course/fine grain netlists?
4629: 96/11/22: K Goldman: Re: Course/fine grain netlists?
4601: 96/11/20: <btr@trenet.com>: Be a Beta Tester!
4605: 96/11/20: alain arnaud: POSITION: VHDL ASIC Designer
4606: 96/11/20: Gordon McGregor: ViewLogic PRO series under win95
4619: 96/11/21: Rene Bakker: Re: ViewLogic PRO series under win95
4625: 96/11/22: Steve Wiseman: Re: ViewLogic PRO series under win95
4632: 96/11/22: Louis Piché: Re: ViewLogic PRO series under win95
4609: 96/11/20: Jeffrey Arnold: CFP: FCCM'97 IEEE Symp on Custom Computing Machines
4610: 96/11/20: <david@lowrance.com>: FPGA Gate Counts: No Truth in Advertising
4612: 96/11/20: Brad Taylor: Re: FPGA Gate Counts: No Truth in Advertising
4620: 96/11/21: <david@lowrance.com>: Re: FPGA Gate Counts: No Truth in Advertising
4631: 96/11/22: Ron Wilson: Re: FPGA Gate Counts: No Truth in Advertising
4634: 96/11/23: <peter8888844@gggggserve.com>: Re: FPGA Gate Counts: No Truth in Advertising
4621: 96/11/21: Tom Standley: Re: FPGA Gate Counts: No Truth in Advertising
4643: 96/11/25: Peter Alfke: Re: FPGA Gate Counts: No Truth in Advertising
4710: 96/12/04: John Vincent: Re: FPGA Gate Counts: No Truth in Advertising?
4630: 96/11/22: Andy Gulliver: Re: FPGA Gate Counts: No Truth in Advertising
4635: 96/11/23: Ross Swanson: Re: FPGA Gate Counts: No Truth in Advertising
4611: 96/11/20: Peter J. Rieck: Free Money
4614: 96/11/20: <jjfakas@erols.com>: FPGA TEST BOARDS
4655: 96/11/26: Andre Hergenhan: Re: FPGA TEST BOARDS
4668: 96/11/27: Gareth Baron: Re: FPGA TEST BOARDS
4670: 96/11/27: Richard Schwarz: Re: FPGA TEST BOARDS
4615: 96/11/21: Richard Staley: Lattice ISP Question
4618: 96/11/21: Wong Man Kit: Re: Lattice ISP Question
4624: 96/11/21: Ed Barrett: Re: Lattice ISP Question
4627: 96/11/22: Mika Iisakkila: Re: Lattice ISP Question
4633: 96/11/22: Leon Heller: Re: Lattice ISP Question
4650: 96/11/26: Richard Staley: Re: Lattice ISP Question
4616: 96/11/21: jorge: Which Mentor Graphics synthesis tool?
4651: 96/11/26: Andrew Morley: Re: Which Mentor Graphics synthesis tool?
4664: 96/11/27: Duncan Davis: Re: Which Mentor Graphics synthesis tool?
4623: 96/11/21: John Rinck: Electronics question
4657: 96/11/26: Gareth Baron: Re: Electronics question
4636: 96/11/23: derrick: flex 800 configuration
4638: 96/11/25: <sjadam@trog.dra.hmg.gb>: Moore vs Mealy state machines
4642: 96/11/25: Bob Sugar: Re: Moore vs Mealy state machines
4645: 96/11/26: Mike Treseler: Re: Moore vs Mealy state machines
4694: 96/12/01: Charlie Burns: Re: Moore vs Mealy state machines
4640: 96/11/25: Mark Sandstrom: How to utilize XC4000e IOB FFs in Synopsys?
4641: 96/11/25: Paul Dietrich: Re: How to utilize XC4000e IOB FFs in Synopsys?
4646: 96/11/25: Joe Samson: Re: How to utilize XC4000e IOB FFs in Synopsys?
4652: 96/11/26: Ted Boydston: Re: How to utilize XC4000e IOB FFs in Synopsys?
4654: 96/11/26: Joe Samson: Re: How to utilize XC4000e IOB FFs in Synopsys?
4661: 96/11/26: Hari Vattikota: Re: How to utilize XC4000e IOB FFs in Synopsys?
4666: 96/11/27: Paul Dietrich: Re: How to utilize XC4000e IOB FFs in Synopsys?
4701: 96/12/02: Hari Vattikota: Re: How to utilize XC4000e IOB FFs in Synopsys?
4674: 96/11/28: Jean Lachance: Re: How to utilize XC4000e IOB FFs in Synopsys?
4699: 96/12/02: Robert Seward: Re: How to utilize XC4000e IOB FFs in Synopsys?
4698: 96/12/02: Kate Meilicke: Re: How to utilize XC4000e IOB FFs in Synopsys?
4647: 96/11/26: Cong shiping: How to use Xilinx ?
4648: 96/11/26: Steve Wiseman: Re: How to use Xilinx ?
4653: 96/11/26: <timolmst@cyberramp.net>: Re: How to use Xilinx ?
4656: 96/11/26: Jerry English: Re: How to use Xilinx ?
4658: 96/11/26: Steve Wiseman: Re: How to use Xilinx ?
4671: 96/11/27: Martin d'Anjou: Re: How to use Xilinx ?
4679: 96/11/29: <vn5s-cng@asahi-net.or.jp>: Re: How to use Xilinx ?
4680: 96/11/29: Steve Wiseman: Re: How to use Xilinx ?
4706: 96/12/04: cong shiping: Re: How to use Xilinx ?
4783: 96/12/13: David Emrich: Re: How to use Xilinx ?
4827: 96/12/18: Andrew Papageorgiou: Re: How to use Xilinx ?
4659: 96/11/26: Gray Creager: ### Chipmaker URLs (almost 300!) and other resources for finding data sheets ###
4660: 96/11/26: Deborah Peel: WinEDA online eng. conf ends
4662: 96/11/26: 1997 International Symposium on Physical Design: CFP: 1997 Intl. Symp. on Physical Design, April 14-16, CA
4663: 96/11/27: Erwin Oertli: Programming the AT17C256
4665: 96/11/27: D. Hibbs: JEDEC file structure
4667: 96/11/27: Pasquale Corsonello: WVoffice and ACTEL Design Series
4669: 96/11/27: Pasquale Corsonello: Reconfigurable chip
4673: 96/11/28: Kevin Horton: SRAM Programming on the Altera NFX780
4685: 96/11/29: Rick Filipkiewicz: Re: SRAM Programming on the Altera NFX780
4675: 96/11/28: Ian Lazarus: Xilinx Foundation
4687: 96/11/29: Mike Forster: Re: Xilinx Foundation
4676: 96/11/28: John Maher: Free Evaluation VHDL Editor
4683: 96/11/29: Uwe Bonnes: Re: Free Evaluation VHDL Editor
4704: 96/12/03: John Maher: Re: Free Evaluation VHDL Editor
4677: 96/11/28: <mak@cromp.ernet.in>: Reconfigurable FPGAs in Networking
4686: 96/11/29: Gareth Baron: Re: Reconfigurable FPGAs in Networking
4689: 96/11/29: Ray Andraka: Re: Reconfigurable FPGAs in Networking
4678: 96/11/28: <trythis@money.com>: Please Help!!!
4681: 96/11/29: Hans Tiggeler: Cypress CPLD, pASIC380 Programmer
4707: 96/12/04: cong shiping: Re: Cypress CPLD, pASIC380 Programmer
4682: 96/11/29: TukryopKim: Addressbility.
4684: 96/11/29: Michael Quinlan: Re: Addressbility.
4702: 96/12/03: John Ahlstrom: Re: Addressbility.
4688: 96/11/29: Lloyd Miller: Re: Addressbility.
4696: 96/12/02: Tony Griffiths: Re: Addressbility.
4690: 96/11/30: Eric Holmberg: Altera Max+Plus
4750: 96/12/11: Krishna Mohan: Re: Altera Max+Plus
4691: 96/11/30: <(DogZ Software Center)>: Corel Draw 7.0! only costs US$40 ? Shopping Paradise
4692: 96/11/30: Lance Gin: In Search of Xilinx Routing Statistics
4693: 96/12/01: <timolmst@cyberramp.net>: Re: In Search of Xilinx Routing Statistics
4697: 96/12/02: Gerhard Hoffmann: Re: In Search of Xilinx Routing Statistics
4700: 96/12/02: Jon Harris: Re: In Search of Xilinx Routing Statistics
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
