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Threads Starting Aug 2002
45672: 02/08/01: Leon de Boer: tone detection...
45682: 02/08/01: sdrg: about amplify/synplify
45683: 02/08/01: Daryl: Re: about amplify/synplify
45701: 02/08/01: S. Ramirez: Re: about amplify/synplify
45685: 02/08/01: =?ISO-8859-1?Q?Stein_Kj=F8lstad?=: ICAP component in Virtex-II
45691: 02/08/01: Peter Baltazarovic: Safe design speed
45695: 02/08/01: Kevin Neilson: Re: Safe design speed
45707: 02/08/02: Lasse Langwadt Christensen: Re: Safe design speed
45708: 02/08/02: John_H: Re: Safe design speed
45751: 02/08/04: <hamish@cloud.net.au>: Re: Safe design speed
45709: 02/08/02: Jim Granville: Re: Safe design speed
45758: 02/08/05: Ray Andraka: Re: Safe design speed
45765: 02/08/05: Peter Baltazarovic: Re: Safe design speed
45692: 02/08/01: Rafael Antunes Nobrega: FPGA needed
45693: 02/08/01: Jee: Xilinx ISE 4.2: UCF file name
45694: 02/08/01: Alan Raphael: Re: Xilinx ISE 4.2: UCF file name
45705: 02/08/02: Lasse Langwadt Christensen: Re: Xilinx ISE 4.2: UCF file name
45697: 02/08/01: Yanick: Looking for VHDL clock generator with jitter control ?
45698: 02/08/01: Nicholas C. Weaver: Pricing on Virtex 2 pro XC2VP4?
45787: 02/08/06: ¼Õ±â¿µ: Re: Pricing on Virtex 2 pro XC2VP4?
45702: 02/08/01: Speedy Zero Two: PCI Interrupt latency
45735: 02/08/02: Kevin Brace: Re: PCI Interrupt latency
45750: 02/08/03: Austin Franklin: Re: PCI Interrupt latency
45706: 02/08/01: Jason Berringer: Division
45722: 02/08/02: Stefan Doll: Re: Division
45883: 02/08/08: Helmut Sennewald: Re: Division
45891: 02/08/09: Prashant: Re: Division
45904: 02/08/09: Ray Andraka: Re: Division
45964: 02/08/12: Jason Berringer: Re: Division
45966: 02/08/13: Ray Andraka: Re: Division
45710: 02/08/01: sf: clock timing
45714: 02/08/02: Eric Pearson: Re: clock timing
45788: 02/08/06: Ray Andraka: Re: clock timing
45711: 02/08/01: vb: inout constrain
45712: 02/08/01: Rudolf Usselmann: changing Vcco
45738: 02/08/02: Dan Kuechle: Re: changing Vcco
45713: 02/08/01: ery: vcs synplify
45715: 02/08/02: Muzaffer Kal: Re: vcs synplify
45718: 02/08/01: Anjan: timing with load
45719: 02/08/02: Elliot Mackenzie: Xilinx2.1i/Celoxica DK1.1 implementation error
45767: 02/08/05: Elliot Mackenzie: Re: Xilinx2.1i/Celoxica DK1.1 implementation error
45720: 02/08/02: Jonathan Bromley: Re: spiral / waterfall /watersluice : Which are your methods?
45721: 02/08/02: yanggg: a chip which can trans ethenet data through E1 interface
45739: 02/08/02: glen herrmannsfeldt: Re: a chip which can trans ethenet data through E1 interface
45754: 02/08/04: Marc Randolph: Re: a chip which can trans ethenet data through E1 interface
45762: 02/08/05: glen herrmannsfeldt: Re: a chip which can trans ethenet data through E1 interface
45723: 02/08/02: Mike Rosing: Re: Qn: Low Level Design
45724: 02/08/02: Mike Rosing: How to use distributed ram/luts ?
45742: 02/08/03: Mike Rosing: Re: How to use distributed ram/luts ?
45816: 02/08/06: Falk Brunner: Re: How to use distributed ram/luts ?
45820: 02/08/06: Alan Raphael: Re: How to use distributed ram/luts ?
45725: 02/08/02: Maciek: spartan i/o
45731: 02/08/02: John_H: Re: spartan i/o
45755: 02/08/05: Maciek: Re: spartan i/o
45726: 02/08/02: Andrzej Ekiert: Spartan II BlockRAM - inverting control signals
45733: 02/08/02: Falk: Re: Spartan II BlockRAM - inverting control signals
45734: 02/08/02: Andrzej Ekiert: Re: Spartan II BlockRAM - inverting control signals
45737: 02/08/02: Sylvain Yon: Re: Spartan II BlockRAM - inverting control signals
45747: 02/08/03: Falk: Re: Spartan II BlockRAM - inverting control signals
45749: 02/08/04: Andrzej Ekiert: Re: Spartan II BlockRAM - inverting control signals
45727: 02/08/02: Vincent JADOT: Which device equivalent
45732: 02/08/02: Falk: Re: Which device equivalent
45730: 02/08/02: Allan Herriman: GSR net skew
45736: 02/08/02: David Wentzlaff: Silicon Area for Xilinx FPGAs
45743: 02/08/03: Uwe Bonnes: Re: Silicon Area for Xilinx FPGAs
45740: 02/08/02: Prashant: Modelsim Fatal Error
45741: 02/08/02: Richard Auletta: CALL FOR PARTICIPATION 15th Annual IEEE International ASIC/SOC Conference
45748: 02/08/03: John_H: Re: About CMUcam Vision Sensor
45752: 02/08/04: Sandeep Grover: newbie ..
45753: 02/08/04: Ramakrishnan: Controller for a Architecture
45769: 02/08/05: Holger Kleinegraeber: Re: Controller for a Architecture
45789: 02/08/05: Ramakrishnan: Re: Controller for a Architecture
45805: 02/08/06: Ramakrishnan: Re: Controller for a Architecture
45808: 02/08/06: Holger Kleinegraeber: Re: Controller for a Architecture
45756: 02/08/05: Xanatos: Re: Gate level simulation in Quartus II
45772: 02/08/05: Prashant: Re: Gate level simulation in Quartus II
45775: 02/08/05: Xanatos: Re: Gate level simulation in Quartus II
45807: 02/08/06: Prashant: Re: Gate level simulation in Quartus II
45757: 02/08/04: Mike Rosing: VHDL primitives: what am I doing that's stupid?
45759: 02/08/04: Mike Rosing: Re: VHDL primitives: what am I doing that's stupid?
45760: 02/08/05: Mike Rosing: Re: VHDL primitives: what am I doing that's stupid?
45761: 02/08/05: Mike Rosing: Re: VHDL primitives: what am I doing that's stupid?
45862: 02/08/07: Mike Rosing: Re: VHDL primitives: what am I doing that's stupid?
45906: 02/08/09: Sylvain Yon: Re: VHDL primitives: what am I doing that's stupid?
45895: 02/08/09: Sylvain Yon: Re: VHDL primitives: what am I doing that's stupid?
45893: 02/08/09: Sylvain Yon: Re: VHDL primitives: what am I doing that's stupid?
47795: 02/10/04: Edoardo: Re: VHDL primitives: what am I doing that's stupid?
45766: 02/08/05: Reala: modelsim XE starter
45770: 02/08/05: Leon Heller: Re: modelsim XE starter
45779: 02/08/05: Kevin Brace: Re: modelsim XE starter
45783: 02/08/05: Jeff Cunningham: Re: modelsim XE starter
47794: 02/10/04: Edoardo: Re: modelsim XE starter
45768: 02/08/05: Maurizio Stefani: ATMEL GAL
45774: 02/08/05: Spam Hater: Re: ATMEL GAL
45782: 02/08/05: S. Ramirez: Re: ATMEL GAL
45771: 02/08/05: Tim Riemann: Soundchip?
45778: 02/08/05: Ray Andraka: Re: Soundchip?
45785: 02/08/06: Tim Riemann: Re: Soundchip?
45786: 02/08/05: Ray Andraka: Re: Soundchip?
45797: 02/08/06: Tim Riemann: Re: Soundchip?
45794: 02/08/06: KVLKCL: Re: Soundchip?
45796: 02/08/06: Tim Riemann: Re: Soundchip?
45781: 02/08/05: Neil Franklin: Re: Soundchip?
45784: 02/08/06: Tim Riemann: Re: Soundchip?
45776: 02/08/05: kkps: AES (rijndael) Ip core
45777: 02/08/05: Nicholas C. Weaver: Re: AES (rijndael) Ip core
45836: 02/08/07: Guerre: Re: AES (rijndael) Ip core
45886: 02/08/09: Andrew: Re: AES (rijndael) Ip core
45889: 02/08/09: Adam Elbirt: Re: AES (rijndael) Ip core
45980: 02/08/13: nustartup: Re: AES (rijndael) Ip core
45790: 02/08/06: Reala: IC design Tools
45792: 02/08/05: Morteza: Qn: Low Level Design
45827: 02/08/07: Neil Franklin: Re: Qn: Low Level Design
45795: 02/08/06: Daryl: Is it necessary to instantiate IPAD, OPAD, IBUF, OBUF...?
45832: 02/08/06: Assaf Sarfati: Re: Is it necessary to instantiate IPAD, OPAD, IBUF, OBUF...?
45834: 02/08/07: Daryl: Re: Is it necessary to instantiate IPAD, OPAD, IBUF, OBUF...?
45837: 02/08/07: Rick Filipkiewicz: Re: Is it necessary to instantiate IPAD, OPAD, IBUF, OBUF...?
45860: 02/08/07: Kevin Brace: Re: Is it necessary to instantiate IPAD, OPAD, IBUF, OBUF...?
45873: 02/08/08: Mike Treseler: Re: Is it necessary to instantiate IPAD, OPAD, IBUF, OBUF...?
45866: 02/08/07: Assaf Sarfati: Re: Is it necessary to instantiate IPAD, OPAD, IBUF, OBUF...?
45798: 02/08/06: John Jakson: Xilinx hiring practises
45804: 02/08/06: Austin Lesea: Re: Xilinx hiring practises
45814: 02/08/06: John Jakson: Re: Xilinx hiring practises
45841: 02/08/07: Ron Huizen: Re: Xilinx hiring practises
45855: 02/08/07: jakab tanko: Re: Xilinx hiring practises
45806: 02/08/06: Ray Andraka: Re: Xilinx hiring practises
45809: 02/08/06: Spam Hater: Re: Xilinx hiring practises
45880: 02/08/08: Jay: Re: Xilinx hiring practises
45799: 02/08/06: Felix Bertram: MicroBlaze bus config 1
45801: 02/08/06: Arash Salarian: how to mix singed and unsigned signals in verilog?
45802: 02/08/06: Shibu: Help Needed -- XESS Board question!
45815: 02/08/06: Dave Vanden Bout: Re: Help Needed -- XESS Board question!
45811: 02/08/06: Richard Schwarz: Standardized IO connectors for RocketIO 3GIO (ExpressPCI) LVDS
45812: 02/08/06: Richard Schwarz: New XILINX ISE not supporting 4000 series FPGAs?
45817: 02/08/06: Falk Brunner: Re: New XILINX ISE not supporting 4000 series FPGAs?
45818: 02/08/06: Kevin Brace: Re: New XILINX ISE not supporting 4000 series FPGAs?
45842: 02/08/07: <hamish@cloud.net.au>: Re: New XILINX ISE not supporting 4000 series FPGAs?
45819: 02/08/06: Nahum Barnea: parameterized / variable ucf
45825: 02/08/06: Rick Filipkiewicz: Re: parameterized / variable ucf
45843: 02/08/07: Francois Choquette: Re: parameterized / variable ucf
45821: 02/08/06: Mike Neuman: Asynchronous signals recommendations?
45876: 02/08/08: Jay: Re: Asynchronous signals recommendations?
45822: 02/08/06: Bob Woolley: CUPL S/N?
45823: 02/08/07: Jim Granville: Re: CUPL S/N?
45851: 02/08/07: Bob Woolley: Re: CUPL S/N?
45857: 02/08/08: Jim Granville: Re: CUPL S/N?
45824: 02/08/06: anonymous: fpga - pc
45826: 02/08/06: Prashant: Programming bits reverse engineering
45828: 02/08/06: Austin Lesea: Re: Programming bits reverse engineering
45838: 02/08/07: Rick Filipkiewicz: Re: Programming bits reverse engineering
45845: 02/08/07: Nicholas C. Weaver: Re: Programming bits reverse engineering
45850: 02/08/07: Keith R. Williams: Re: Programming bits reverse engineering
45846: 02/08/07: Prashant: Re: Programming bits reverse engineering
45848: 02/08/07: glen herrmannsfeldt: Re: Programming bits reverse engineering
45945: 02/08/12: jetmarc: Re: Programming bits reverse engineering
45847: 02/08/07: Austin Lesea: Re: Programming bits reverse engineering
45852: 02/08/07: Steve Casselman: Re: Programming bits reverse engineering
45859: 02/08/07: Kevin Brace: Re: Programming bits reverse engineering
45881: 02/08/08: Prashant: Re: Programming bits reverse engineering
45829: 02/08/06: Apollo: Xilinx TIG
45877: 02/08/08: Jay: Re: Xilinx TIG
45878: 02/08/08: Falk Brunner: Re: Xilinx TIG
45830: 02/08/07: Loi Tran: Lattice GAL22V10 and everything it entails . . . !
45853: 02/08/07: Bob Woolley: Re: Lattice GAL22V10 and everything it entails . . . !
46700: 02/09/06: en: Re: Lattice GAL22V10 and everything it entails . . . !
45831: 02/08/07: Scott L. Baker: Looking for behavioral Xilinx RAM model
45835: 02/08/07: Allan Herriman: Re: Looking for behavioral Xilinx RAM model
45833: 02/08/06: Nahum Barnea: xilinx: map -k
45839: 02/08/07: Rick Filipkiewicz: Re: xilinx: map -k
45840: 02/08/07: Rick Filipkiewicz: Re: xilinx: map -k
45871: 02/08/08: Francois Choquette: Re: xilinx: map -k
45924: 02/08/11: Rick Filipkiewicz: Re: xilinx: map -k
45844: 02/08/07: Peter Baltazarovic: Modelsim glbl.GTS problem
45868: 02/08/08: Peter Baltazarovic: Re: Modelsim glbl.GTS problem
45849: 02/08/07: Nicolas Matringe: Getting crazy: abnormal behavior (Xilinx Spartan2E)
45870: 02/08/08: Nicolas Matringe: Re: Getting crazy: abnormal behavior (Xilinx Spartan2E)
45854: 02/08/07: Nahum Barnea: xilinx RLOC usage
45912: 02/08/10: <hamish@cloud.net.au>: Re: xilinx RLOC usage
45923: 02/08/10: Nahum Barnea: Re: xilinx RLOC usage
45926: 02/08/11: <hamish@cloud.net.au>: Re: xilinx RLOC usage
45856: 02/08/07: Nicholas C. Weaver: Re: AES (rijndael) algorithm coding time
45863: 02/08/07: Mike Rosing: Re: articles about FPGA based DSP design
45864: 02/08/07: Mike Rosing: Re: changing width of array
45865: 02/08/08: Xanatos: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46598: 02/09/04: Prager Roman: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46643: 02/09/05: Pete Ormsby: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46649: 02/09/04: Kevin Brace: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46665: 02/09/05: Eric Smith: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46672: 02/09/05: Kevin Brace: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46644: 02/09/05: ds: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46654: 02/09/04: Kevin Brace: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46666: 02/09/05: Paul Baxter: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46698: 02/09/06: ds: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46701: 02/09/06: Paul Baxter: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46720: 02/09/06: Mike Treseler: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46747: 02/09/07: ds: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46749: 02/09/07: Hal Murray: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46780: 02/09/09: ds: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46949: 02/09/13: Ben Twijnstra: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46948: 02/09/12: Ben Twijnstra: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46950: 02/09/13: Jim Granville: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46955: 02/09/12: Kevin Brace: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46956: 02/09/12: Kevin Brace: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46999: 02/09/13: Ben Twijnstra: Re: QUARTUS II V2.1 LINUX (C) ALTERA
45867: 02/08/08: <furia1024@news.secom.com.pl>: Modelsim in ISE pack
45869: 02/08/08: Stefan Doll: Re: Modelsim in ISE pack
45872: 02/08/08: irum4: Spartan II IOBUF
45874: 02/08/08: Paul Smith: Xilinx XC2VP4 price/availability ?
45890: 02/08/09: Austin Lesea: Re: Xilinx XC2VP4 price/availability ?
45903: 02/08/09: Paul Smith: Re: Xilinx XC2VP4 price/availability ?
45905: 02/08/09: Austin Lesea: Re: Xilinx XC2VP4 price/availability ?
45875: 02/08/08: Jay: ... milk for free, Opencores?
45879: 02/08/08: Falk Brunner: Re: ... milk for free, Opencores?
45882: 02/08/08: John Eaton: Re: ... milk for free, Opencores?
45896: 02/08/09: Richard Iachetta: Re: ... milk for free, Opencores?
45902: 02/08/09: Ray Andraka: Re: ... milk for free, Opencores?
45911: 02/08/10: <hamish@cloud.net.au>: Re: ... milk for free, Opencores?
46961: 02/09/13: Hal Murray: Re: ... milk for free, Opencores?
47563: 02/09/28: Rudolf Usselmann: Re: ... milk for free, Opencores?
47608: 02/09/30: MikeJ: Re: ... milk for free, Opencores?
45884: 02/08/09: Reala: I would like to find some resource for IC layout
45897: 02/08/09: Vikash Rungta: Re: I would like to find some resource for IC layout
45887: 02/08/09: Philippe Bataille: RAM simlulation with WebPack4.2
45908: 02/08/10: David R Brooks: Re: RAM simlulation with WebPack4.2
45888: 02/08/09: S. Ramirez: How Fast FIFOs?
45892: 02/08/09: <fujiki@elf.coara.or.jp>: ia32 compatible IP core
45894: 02/08/09: Sleep Mode: BLUETOOTH newbie
45962: 02/08/12: Joe Maloney: Re: BLUETOOTH newbie
46018: 02/08/14: Sleep Mode: Re: BLUETOOTH newbie
46021: 02/08/14: Sleep Mode: Re: BLUETOOTH newbie
45898: 02/08/09: ben cohen: RMM 3rd Edition // Comments and recommendation
45899: 02/08/09: Mike Neufeld: Using Quartus with an EPC2 and a Flex 6000?
45900: 02/08/09: Prashant: ASIC conversion
45937: 02/08/11: Jay: Re: ASIC conversion
45901: 02/08/09: Mike Neufeld: Does Altera Jam work?
45909: 02/08/10: Xanatos: Re: Does Altera Jam work?
45907: 02/08/09: Vikram Chandrasekhar: Power saving with Clock gating
45938: 02/08/12: John Blaine: Re: Power saving with Clock gating
45951: 02/08/12: Vikram Chandrasekhar: Re: Power saving with Clock gating
45989: 02/08/13: John Blaine: Re: Power saving with Clock gating
45995: 02/08/13: Vikram Chandrasekhar: Re: Power saving with Clock gating
45910: 02/08/09: Mike Rosing: Re: Reed-Solomon polynom transform....
45921: 02/08/10: Mike Rosing: Re: Reed-Solomon polynom transform....
46058: 02/08/15: <samg@codenet.net>: Re: Reed-Solomon polynom transform....
46023: 02/08/15: <samg@codenet.net>: Re: Reed-Solomon polynom transform....
46032: 02/08/14: Eric Smith: Re: Reed-Solomon polynom transform....
45913: 02/08/10: Wesley J. Landaker: Re: EDIF and JHDL information
45914: 02/08/10: Damien: I seek a FPFA developer
45919: 02/08/11: Nicholas C. Weaver: Re: I seek a FPFA developer
45928: 02/08/11: reply in the newsgroup: Re: I seek a FPFA developer
45915: 02/08/10: Bill Diehls: Fun FPGA system
45961: 02/08/12: Achim Gratz: Re: Fun FPGA system
46162: 02/08/20: Jonathan O'Brien: Re: Fun FPGA system
46073: 02/08/16: Manfred Kraus: Re: Fun FPGA system
46081: 02/08/16: Nicholas C. Weaver: Re: Fun FPGA system
45916: 02/08/10: John Larkin: unloading a fast ADC
45917: 02/08/10: Ray Andraka: Re: unloading a fast ADC
45927: 02/08/11: Ray Andraka: Re: unloading a fast ADC
45977: 02/08/13: Pete Ormsby: Re: unloading a fast ADC
46004: 02/08/13: Ray Andraka: Re: unloading a fast ADC
45918: 02/08/10: Ben Twijnstra: Re: unloading a fast ADC
45993: 02/08/13: Paul Smith: Re: unloading a fast ADC
45920: 02/08/10: Yx jiang: comp.arch.fpga : How can I join the newsgroup?
45922: 02/08/11: Philip Freidin: Re: comp.arch.fpga : How can I join the newsgroup?
45929: 02/08/11: Hristo Stevic: articles about FPGA based DSP design
45930: 02/08/12: Jim Granville: Re: articles about FPGA based DSP design
45932: 02/08/12: Ray Andraka: Re: articles about FPGA based DSP design
45933: 02/08/11: Duane Perry: 485 core
45936: 02/08/12: Allan Herriman: Re: 485 core
45934: 02/08/11: Vikram Chandrasekhar: Advice regarding clock gating
45990: 02/08/13: John Blaine: Re: Advice regarding clock gating
45935: 02/08/12: Reala: Synthesis Verilog to ASIC
45950: 02/08/12: Spam Hater: Re: Synthesis Verilog to ASIC
45969: 02/08/13: Reala: Re: Synthesis Verilog to ASIC
45971: 02/08/13: Spam Hater: Re: Synthesis Verilog to ASIC
45982: 02/08/13: <samg@codenet.net>: Re: Synthesis Verilog to ASIC
46006: 02/08/14: Reala: Re: Synthesis Verilog to ASIC
46009: 02/08/14: whoami: Re: Synthesis Verilog to ASIC
46028: 02/08/15: Reala: Re: Synthesis Verilog to ASIC
45939: 02/08/12: maimuna: changing width of array
45965: 02/08/13: Daryl: Re: changing width of array
46041: 02/08/15: Peter Young: Re: changing width of array
45940: 02/08/12: Yx Jiang: What does the question lie in?
45941: 02/08/12: Rick Filipkiewicz: Re: What does the question lie in?
45976: 02/08/13: Yx Jiang: Re: What does the question lie in?
45942: 02/08/12: Børge Strand: ModelSim takes forever
45943: 02/08/12: Børge Strand: Re: ModelSim takes forever
45948: 02/08/12: VhdlCohen: Re: ModelSim takes forever
45952: 02/08/12: Kevin Brace: Re: ModelSim takes forever
45954: 02/08/12: Kevin Brace: Re: ModelSim takes forever
45946: 02/08/12: hristo: FPGA a promising platform for hardware design...need articles
45947: 02/08/12: Ramakrishnan: Reconfiguration in Xilinx FPGA
45949: 02/08/12: reply in the newsgroup: Re: Reconfiguration in Xilinx FPGA
45958: 02/08/12: Ramakrishnan: Re: Reconfiguration in Xilinx FPGA
45963: 02/08/12: reply in the newsgroup: Re: Reconfiguration in Xilinx FPGA
45981: 02/08/13: Ramakrishnan: Re: Reconfiguration in Xilinx FPGA
46007: 02/08/13: reply in the newsgroup: Re: Reconfiguration in Xilinx FPGA
46091: 02/08/17: Ramakrishnan: Re: Reconfiguration in Xilinx FPGA
45953: 02/08/12: Nicholas C. Weaver: Symplify Hacking/munging question...
45955: 02/08/12: Mike Treseler: Re: Symplify Hacking/munging question...
45960: 02/08/12: Nicholas C. Weaver: Re: Symplify Hacking/munging question...
45988: 02/08/13: Mike Treseler: Re: Symplify Hacking/munging question...
46000: 02/08/13: Ray Andraka: Re: Symplify Hacking/munging question...
45956: 02/08/12: Ray Andraka: Re: Symplify Hacking/munging question...
45959: 02/08/12: Nicholas C. Weaver: Re: Symplify Hacking/munging question...
45967: 02/08/13: Ray Andraka: Re: Symplify Hacking/munging question...
45957: 02/08/12: Yanick: Xilinx IBUFGDS with both inputs grounded ?
45968: 02/08/13: Ray Andraka: Re: Xilinx IBUFGDS with both inputs grounded ?
45998: 02/08/13: Yanick: Re: Xilinx IBUFGDS with both inputs grounded ?
45970: 02/08/12: Anjan: capacitance
45984: 02/08/13: John_H: Re: capacitance
45972: 02/08/13: Ulises Hernandez: RBT versus BIT file
45986: 02/08/13: Hal Murray: Re: RBT versus BIT file
46001: 02/08/14: Neil Franklin: Re: RBT versus BIT file
45973: 02/08/13: Bill: Hardware Software partition in FPGAs
45974: 02/08/13: Kolja Sulimma: Xilinx XST inferred Block-RAM Initialization
45985: 02/08/13: Falk Brunner: Re: Xilinx XST inferred Block-RAM Initialization
45991: 02/08/13: Mike Treseler: Re: Xilinx XST inferred Block-RAM Initialization
45999: 02/08/13: M. Randelzhofer: Re: Xilinx XST inferred Block-RAM Initialization
46003: 02/08/13: Ray Andraka: Re: Xilinx XST inferred Block-RAM Initialization
45975: 02/08/13: Daryl: "flip flop" and "register"
45979: 02/08/13: fred: Re: "flip flop" and "register"
46031: 02/08/14: Eric Smith: Re: "flip flop" and "register"
46130: 02/08/20: Daryl: Re: "flip flop" and "register"
46131: 02/08/20: Jim Granville: Re: "flip flop" and "register"
45994: 02/08/13: S. Ramirez: Re: "flip flop" and "register"
45978: 02/08/13: Buddy Smith: Academics vs 'real' FPGA use
45983: 02/08/13: Alan Raphael: Re: Academics vs 'real' FPGA use
46177: 02/08/21: Paul: Re: Academics vs 'real' FPGA use
46188: 02/08/21: Austin Lesea: Re: Academics vs 'real' FPGA use
46196: 02/08/21: Paul: Re: Academics vs 'real' FPGA use
46205: 02/08/21: Austin Lesea: Re: Academics vs 'real' FPGA use
46197: 02/08/21: Kevin Brace: Re: Academics vs 'real' FPGA use
46203: 02/08/21: Buddy Smith: Re: Academics vs 'real' FPGA use
45987: 02/08/13: ted: Altera Byteblaster MAX7k programming problem
46013: 02/08/14: Russell: Re: Altera Byteblaster MAX7k programming problem
46051: 02/08/15: ted: Re: Altera Byteblaster MAX7k programming problem
46050: 02/08/15: Steen Larsen: Re: Altera Byteblaster MAX7k programming problem
45992: 02/08/13: tomlih: About configuration of Virtex-e&Prom
45996: 02/08/13: Igor: Reed-Solomon polynom transform....
45997: 02/08/13: mikest: Divider in Xilinx System Generator
46002: 02/08/13: Ray Andraka: Re: Divider in Xilinx System Generator
46077: 02/08/16: JianyongNiu: Re: Divider in Xilinx System Generator
46082: 02/08/16: Ray Andraka: Re: Divider in Xilinx System Generator
46005: 02/08/14: Ogah: Testing the X2S_USB Spartan 2 board
46074: 02/08/16: Manfred Kraus: Re: Testing the X2S_USB Spartan 2 board
46010: 02/08/13: Hakon Lislebo: How to interpret the XILINX post layout timing report
46011: 02/08/14: =?ISO-8859-1?Q?L=E4hteenm=E4ki?= Jussi: Altera APEX clock problem
46014: 02/08/14: Paul Baxter: Re: Altera APEX clock problem
46015: 02/08/14: Matjaz Finc: Re: Altera APEX clock problem
46611: 02/09/04: Prager Roman: Re: Altera APEX clock problem
46614: 02/09/04: Paul Baxter: Re: Altera APEX clock problem
46012: 02/08/14: <hypi@gmx.net>: transputers
46017: 02/08/14: Leon Heller: Re: transputers
46054: 02/08/15: <hypi@gmx.net>: Re: transputers
46068: 02/08/16: Leon Heller: Re: transputers
46020: 02/08/14: Jan Gray: Re: transputers
46055: 02/08/15: <hypi@gmx.net>: Re: transputers
46071: 02/08/16: Holger Venus: Re: transputers
46016: 02/08/14: hristo: routing long line ressources
46019: 02/08/14: Ray Andraka: Re: routing long line ressources
46022: 02/08/15: John Williams: Modelsim VHDL problem
46033: 02/08/15: Michal Rutka: Re: Modelsim VHDL problem
46024: 02/08/14: Ryan: Xilinx tools: which one? Esp. schematic
46026: 02/08/15: Nicholas C. Weaver: Re: Xilinx tools: which one? Esp. schematic
46027: 02/08/15: Ray Andraka: Re: Xilinx tools: which one? Esp. schematic
46035: 02/08/15: Noddy: Re: Xilinx tools: which one? Esp. schematic
46038: 02/08/15: Leon Heller: Re: Xilinx tools: which one? Esp. schematic
46044: 02/08/15: Austin Franklin: Re: Xilinx tools: which one? Esp. schematic
46046: 02/08/15: Ray Andraka: Re: Xilinx tools: which one? Esp. schematic
46121: 02/08/19: Austin Franklin: Re: Xilinx tools: which one? Esp. schematic
46123: 02/08/20: Ray Andraka: Re: Xilinx tools: which one? Esp. schematic
46193: 02/08/21: Austin Franklin: Re: Xilinx tools: which one? Esp. schematic
46206: 02/08/21: Ray Andraka: Re: Xilinx tools: which one? Esp. schematic
46218: 02/08/21: Austin Franklin: Re: Xilinx tools: which one? Esp. schematic
46221: 02/08/22: Ray Andraka: Re: Xilinx tools: which one? Esp. schematic
46029: 02/08/14: Jan Gray: Re: Xilinx tools: which one? Esp. schematic
46034: 02/08/15: Kevin Brace: Re: Xilinx tools: which one? Esp. schematic
46057: 02/08/15: Ryan: Re: Xilinx tools: which one? Esp. schematic
46061: 02/08/15: Nicholas C. Weaver: Re: Xilinx tools: which one? Esp. schematic
46065: 02/08/15: Ryan: Re: Xilinx tools: which one? Esp. schematic
46066: 02/08/16: Nicholas C. Weaver: Re: Xilinx tools: which one? Esp. schematic
46084: 02/08/16: Ryan: Re: Xilinx tools: which one? Esp. schematic
46085: 02/08/16: Nicholas C. Weaver: Re: Xilinx tools: which one? Esp. schematic
46092: 02/08/17: Jan Gray: Re: Xilinx tools: which one? Esp. schematic
46103: 02/08/19: Achim Gratz: Re: Xilinx tools: which one? Esp. schematic
46049: 02/08/15: Børge Strand: Re: Xilinx tools: which one? Esp. schematic
46025: 02/08/14: tomlih: S.O.S
46030: 02/08/14: Mauricio Lange: XC4010 losses configuration
46036: 02/08/15: Alan Fitch: Re: Modelsim VHDL problem
46037: 02/08/15: phile: Re: Modelsim VHDL problem
46039: 02/08/15: Alan Fitch: Re: Modelsim VHDL problem
46063: 02/08/16: John Williams: Re: Modelsim VHDL problem
46040: 02/08/15: Heiko Timmer: Resetting Spartan II FPGA
46047: 02/08/15: John_H: Re: Resetting Spartan II FPGA
46042: 02/08/15: shay: rising_edge detector?
46064: 02/08/15: Mike Treseler: Re: rising_edge detector?
46067: 02/08/16: Loi Tran: Re: rising_edge detector?
46098: 02/08/19: Paul: Re: rising_edge detector?
46102: 02/08/19: Laurent Gauch: Re: rising_edge detector?
46115: 02/08/19: Peter Alfke: Re: rising_edge detector?
46118: 02/08/20: Tim: Re: rising_edge detector?
46119: 02/08/19: Peter Alfke: Re: rising_edge detector?
46234: 02/08/22: Phil Connor: Re: rising_edge detector?
46114: 02/08/19: lng: Re: rising_edge detector?
46043: 02/08/15: Deli Geng (David): I2C License
46126: 02/08/20: Austin Franklin: Re: I2C License
46134: 02/08/19: Eric Smith: Re: I2C License
46149: 02/08/20: Austin Franklin: Re: I2C License
46176: 02/08/21: Kolja Sulimma: Re: I2C License
46199: 02/08/21: Davis Moore: Re: I2C License
46214: 02/08/22: Jim Granville: Re: I2C License
46228: 02/08/22: Kolja Sulimma: Re: I2C License
46233: 02/08/22: Iwo Mergler: Re: I2C License
46238: 02/08/22: Austin Franklin: Re: I2C License
46263: 02/08/23: Iwo Mergler: Re: I2C License
46048: 02/08/15: Børge Strand: Problem with Xilinx mapper
46059: 02/08/15: Josh Model: Re: Problem with Xilinx mapper
46060: 02/08/15: Josh Model: oops
46062: 02/08/15: Austin Franklin: Re: Problem with Xilinx mapper
46072: 02/08/16: Børge Strand: Re: Problem with Xilinx mapper
46052: 02/08/15: Henry: 2 questions using Synplify Pro.
46053: 02/08/15: Austin Franklin: Re: 2 questions using Synplify Pro.
46069: 02/08/16: William Hall: Xilinx suppliers in UK
46070: 02/08/16: Holger Venus: MicroBlaze processor core
46080: 02/08/16: Goran Bilski: Re: MicroBlaze processor core
46545: 02/09/02: Jerry D. Harthcock: Re: MicroBlaze processor core
46075: 02/08/16: Kenneth: Phase shift in high frequency mode in VirtexII's DCM
46078: 02/08/16: Austin Lesea: Re: Phase shift in high frequency mode in VirtexII's DCM
46094: 02/08/19: Kenneth: Re: Phase shift in high frequency mode in VirtexII's DCM
46099: 02/08/19: Austin Lesea: Re: Phase shift in high frequency mode in VirtexII's DCM
46076: 02/08/16: Grog: Xilinx iMPACT/Parallel Port programming in Win XP soloution?
46079: 02/08/16: William Hall: Re: Xilinx iMPACT/Parallel Port programming in Win XP soloution?
46083: 02/08/16: Steve Casselman: Re: Xilinx iMPACT/Parallel Port programming in Win XP soloution?
46089: 02/08/18: al: Re: Xilinx iMPACT/Parallel Port programming in Win XP soloution?
46086: 02/08/16: Theron Hicks: CLOCK DLL IN SPARTAN2E Timing question
46087: 02/08/16: John_H: Re: CLOCK DLL IN SPARTAN2E Timing question
46113: 02/08/19: lng: Re: CLOCK DLL IN SPARTAN2E Timing question
46088: 02/08/17: William Hall: V2PRO PowerPC floating point
46090: 02/08/17: Ray Andraka: Re: V2PRO PowerPC floating point
46100: 02/08/19: Goran Bilski: Re: V2PRO PowerPC floating point
46106: 02/08/19: Ray Andraka: Re: V2PRO PowerPC floating point
46093: 02/08/19: Noddy: Polyphase filtering...
46117: 02/08/19: Tom Burgess: Re: Polyphase filtering...
46647: 02/09/04: rickman: Re: Polyphase filtering...
46791: 02/09/09: Noddy: Re: Polyphase filtering...
46808: 02/09/09: rickman: Re: Polyphase filtering...
46862: 02/09/10: Noddy: Re: Polyphase filtering...
46866: 02/09/10: rickman: Re: Polyphase filtering...
46903: 02/09/11: Noddy: Re: Polyphase filtering...
46917: 02/09/11: rickman: Re: Polyphase filtering...
46124: 02/08/20: Ray Andraka: Re: Polyphase filtering...
46136: 02/08/20: Noddy: Re: Polyphase filtering...
46137: 02/08/20: Noddy: Re: Polyphase filtering...
46646: 02/09/04: rickman: Re: Polyphase filtering...
46095: 02/08/19: Bernhard Rieder: Manipulating Altera SOF Files
46107: 02/08/19: Steve Casselman: Re: Manipulating Altera SOF Files
46096: 02/08/19: maimuna: to reduce the circuit design
46097: 02/08/19: Noddy: Re: to reduce the circuit design
46222: 02/08/21: maimuna: Re: to reduce the circuit design
46227: 02/08/22: Jim Granville: Re: to reduce the circuit design
46262: 02/08/23: maimuna: Re: to reduce the circuit design
46101: 02/08/19: Patrik Eriksson: BRAM simulation model error?
46116: 02/08/19: lng: Re: BRAM simulation model error?
46138: 02/08/20: Patrik Eriksson: Re: BRAM simulation model error?
46122: 02/08/20: Ray Andraka: Re: BRAM simulation model error?
46140: 02/08/20: Patrik Eriksson: Re: BRAM simulation model error?
46158: 02/08/20: Ray Andraka: Re: BRAM simulation model error?
46146: 02/08/20: lng: Re: BRAM simulation model error?
46156: 02/08/20: Goran Bilski: Re: BRAM simulation model error?
46172: 02/08/21: Allan Herriman: Re: BRAM simulation model error?
46173: 02/08/21: Ray Andraka: Re: BRAM simulation model error?
46175: 02/08/21: Allan Herriman: Re: BRAM simulation model error?
46182: 02/08/21: Ray Andraka: Re: BRAM simulation model error?
46104: 02/08/19: Ramakrishnan: onboard reconfiguration of Xilinx FPGA
46108: 02/08/19: Falk Brunner: Re: onboard reconfiguration of Xilinx FPGA
46236: 02/08/22: Ray Liang: Re: onboard reconfiguration of Xilinx FPGA
46237: 02/08/22: Falk Brunner: Re: onboard reconfiguration of Xilinx FPGA
46242: 02/08/22: emanuel stiebler: Re: onboard reconfiguration of Xilinx FPGA
46243: 02/08/22: Peter Alfke: Re: onboard reconfiguration of Xilinx FPGA
46109: 02/08/19: Phil James-Roxby: Re: onboard reconfiguration of Xilinx FPGA
46125: 02/08/19: Ramakrishnan: Re: onboard reconfiguration of Xilinx FPGA
46133: 02/08/20: John Williams: Re: onboard reconfiguration of Xilinx FPGA
46155: 02/08/20: Ramakrishnan: Re: onboard reconfiguration of Xilinx FPGA
46105: 02/08/19: Tom Loftus: Poor man's DSP/FPGA instructional tool?
46144: 02/08/20: default: Re: Poor man's DSP/FPGA instructional tool?
46326: 02/08/26: Tom Loftus: Re: Poor man's DSP/FPGA instructional tool?
46147: 02/08/20: Christopher Saunter: Re: Poor man's DSP/FPGA instructional tool?
46327: 02/08/26: Tom Loftus: Re: Poor man's DSP/FPGA instructional tool?
46152: 02/08/20: Austin Lesea: Re: Poor man's DSP/FPGA instructional tool?
46328: 02/08/26: Tom Loftus: Re: Poor man's DSP/FPGA instructional tool?
46333: 02/08/26: Christopher Saunter: Re: Poor man's DSP/FPGA instructional tool?
46329: 02/08/26: Tom Loftus: Re: Poor man's DSP/FPGA instructional tool?
46345: 02/08/27: Tony Burch: Re: Poor man's DSP/FPGA instructional tool?
46110: 02/08/19: Terry Herter: Stratix Experience
46385: 02/08/28: Jim Patterson: Re: Stratix Experience
46390: 02/08/28: Ray Andraka: Re: Stratix Experience
46111: 02/08/19: tom curran: xilinx pci troubles with flakey host initiator
46120: 02/08/19: Austin Franklin: Re: xilinx pci troubles with flakey host initiator
46129: 02/08/19: Kevin Brace: Re: xilinx pci troubles with flakey host initiator
46112: 02/08/19: Josh Model: Actel Proto Boards
46543: 02/09/02: Jerry D. Harthcock: Re: Actel Proto Boards
46544: 02/09/03: Jim Granville: Re: Actel Proto Boards
46567: 02/09/03: Jerry D. Harthcock: Re: Actel Proto Boards
46594: 02/09/04: Gregory C. Read: Re: Actel Proto Boards
46610: 02/09/04: Eric Braeden: Re: Actel Proto Boards
46617: 02/09/04: Gregory C. Read: Re: Actel Proto Boards
46620: 02/09/04: Jerry D. Harthcock: Re: Actel Proto Boards
46734: 02/09/06: John Eaton: Re: Actel Proto Boards
46748: 02/09/06: Jerry D. Harthcock: Re: Actel Proto Boards
46127: 02/08/20: Reala: INOUT port
46143: 02/08/20: ae: Re: INOUT port
46217: 02/08/22: Reala: Re: INOUT port
46185: 02/08/21: Mark Momcilovich: Re: INOUT port
46216: 02/08/22: Reala: Re: INOUT port
46128: 02/08/20: Reala: debug for internal node
46132: 02/08/19: JinSoo Kim: Good documentation on CPLD
46135: 02/08/20: Veli-Matti Karppinen: Re: Good documentation on CPLD
46139: 02/08/20: Jim Granville: Re: Good documentation on CPLD
46171: 02/08/20: Al Williams: Re: Good documentation on CPLD
46141: 02/08/20: RobertS: Xilinx FPGA start-up
46145: 02/08/20: Ray Andraka: Re: Xilinx FPGA start-up
46151: 02/08/20: Hal Murray: Re: Xilinx FPGA start-up
46168: 02/08/20: Allan Herriman: Re: Xilinx FPGA start-up
46142: 02/08/20: HenningB: Huge discrepanzcy between gate-array and standard cell synthesis
46154: 02/08/20: Alan Fitch: Re: Huge discrepanzcy between gate-array and standard cell synthesis
46202: 02/08/21: John Eaton: Re: Huge discrepanzcy between gate-array and standard cell synthesis
46224: 02/08/22: Muzaffer Kal: Re: Huge discrepanzcy between gate-array and standard cell synthesis
46148: 02/08/20: Schachinger Martin: need help with the JAM-Player from ALTERA
46167: 02/08/20: Alan Nishioka: Re: need help with the JAM-Player from ALTERA
46225: 02/08/22: Schachinger Martin: Re: need help with the JAM-Player from ALTERA
46150: 02/08/20: Jon Beniston: PS/2 Keyboard Interface in a Virtex-E
46157: 02/08/20: Laurent Gauch: Re: PS/2 Keyboard Interface in a Virtex-E
46165: 02/08/20: Kevin Brace: Re: Resume: HW Verification Consultant (Specman)
46159: 02/08/20: Kirk George: FREE 1/2 day tutorial: "The Xilinx Virtex II PRO - PowerPC 405 Architecture Familiarization"
46160: 02/08/20: Weifeng Xu: And detailed documentation about XDL format?
46163: 02/08/20: Steve Casselman: Re: And detailed documentation about XDL format?
46161: 02/08/20: Barry Brown: How to include Xilinx library for both ModelSim and Synplify?
46164: 02/08/20: Ray Andraka: Re: How to include Xilinx library for both ModelSim and Synplify?
46200: 02/08/21: Barry Brown: Re: How to include Xilinx library for both ModelSim and Synplify?
46204: 02/08/21: Ken McElvain: Re: How to include Xilinx library for both ModelSim and Synplify?
46209: 02/08/21: Ray Andraka: Re: How to include Xilinx library for both ModelSim and Synplify?
46215: 02/08/22: Ken McElvain: Re: How to include Xilinx library for both ModelSim and Synplify?
46220: 02/08/22: Ray Andraka: Re: How to include Xilinx library for both ModelSim and Synplify?
46208: 02/08/21: Ray Andraka: Re: How to include Xilinx library for both ModelSim and Synplify?
46230: 02/08/22: Patrick Loschmidt: Re: How to include Xilinx library for both ModelSim and Synplify?
46235: 02/08/22: Ray Andraka: Re: How to include Xilinx library for both ModelSim and Synplify?
46264: 02/08/23: Jeff Cunningham: Re: How to include Xilinx library for both ModelSim and Synplify?
46283: 02/08/24: <hamish@cloud.net.au>: Re: How to include Xilinx library for both ModelSim and Synplify?
46265: 02/08/23: Allan Herriman: Re: How to include Xilinx library for both ModelSim and Synplify?
46274: 02/08/23: Ray Andraka: Re: How to include Xilinx library for both ModelSim and Synplify?
46166: 02/08/20: John Larkin: TQFP 176 socket
46189: 02/08/21: Mike Treseler: Re: TQFP 176 socket
46169: 02/08/20: Kirk: QDR Controller
46170: 02/08/21: Khee Hue: Virtex-II LVPECL Inputs
46186: 02/08/21: Austin Lesea: Re: Virtex-II LVPECL Inputs
46174: 02/08/21: Leon Qin: What's wrong with clearLogic?
46211: 02/08/21: Pete Ormsby: Re: What's wrong with clearLogic?
46645: 02/09/04: rickman: Re: What's wrong with clearLogic?
46648: 02/09/04: Kevin Brace: Re: What's wrong with clearLogic?
46652: 02/09/05: Jim Granville: Re: What's wrong with clearLogic?
46689: 02/09/05: rickman: Re: What's wrong with clearLogic?
46697: 02/09/06: John_H: Re: What's wrong with clearLogic?
46724: 02/09/06: rickman: Re: What's wrong with clearLogic?
46655: 02/09/04: rickman: Re: What's wrong with clearLogic?
46651: 02/09/05: Jim Granville: Re: What's wrong with clearLogic?
46656: 02/09/04: rickman: Re: What's wrong with clearLogic?
46657: 02/09/04: Kevin Brace: Re: What's wrong with clearLogic?
46178: 02/08/21: Sebastian: Strathnuey xc2v1000
46179: 02/08/21: Din: Multiple Nios ...
46180: 02/08/21: Paul Baxter: Re: Multiple Nios ...
46181: 02/08/21: Georg Heinrich: "Tall Thin Engineer"
46183: 02/08/21: Alan Fitch: Re: "Tall Thin Engineer"
46184: 02/08/21: Ron Cline: Re: "Tall Thin Engineer"
46187: 02/08/21: John Larkin: Re: "Tall Thin Engineer"
46190: 02/08/21: Manuel Gericota: ERA60100 Data Sheet
46192: 02/08/21: Asif Siddiq: cdma code acquisition problem
46278: 02/08/23: wrightjt: Re: cdma code acquisition problem
46280: 02/08/23: wrightjt: Re: cdma code acquisition problem
46198: 02/08/21: Prashant: Logic Analyzers with an Altera Board
46201: 02/08/21: Mike Treseler: Re: Logic Analyzers with an Altera Board
46207: 02/08/21: Ray Andraka: Re: Logic Analyzers with an Altera Board
46213: 02/08/21: Austin Lesea: Re: Logic Analyzers not required with Xilinx Boards....
46219: 02/08/21: Paul: Re: Logic Analyzers with an Altera Board
46346: 02/08/27: MikeJ: Re: Logic Analyzers with an Altera Board
46210: 02/08/21: TED: Is this asynchronous design safe ?
46212: 02/08/21: Ray Andraka: Re: Is this asynchronous design safe ?
46223: 02/08/21: Michael Schmidl: combinatorial clocks
46240: 02/08/22: Falk Brunner: Re: combinatorial clocks
46244: 02/08/22: reply in the newsgroup: Re: combinatorial clocks
46256: 02/08/22: David Stevens: Re: combinatorial clocks
46226: 02/08/22: Tim Forcer: ANNOUNCE: Workshop on Educational ECAD for FPGAs
46229: 02/08/22: Anjan: X on bus
46231: 02/08/22: Alan Fitch: Re: X on bus
46258: 02/08/22: Anjan: Re: X on bus
46275: 02/08/23: Peng: Re: X on bus
46232: 02/08/22: dross: Want a most simple develop board's design example for Xilinx FPGA(SP-II)?
46239: 02/08/22: Falk Brunner: Re: Want a most simple develop board's design example for Xilinx FPGA(SP-II)?
46247: 02/08/22: ae: Re: Want a most simple develop board's design example for Xilinx FPGA(SP-II)?
46248: 02/08/22: Christopher Cole: Re: Want a most simple develop board's design example for Xilinx FPGA(SP-II)?
46251: 02/08/22: Helmut Sennewald: Re: Want a most simple develop board's design example for Xilinx FPGA(SP-II)?
46241: 02/08/22: Ramakrishnan: Downloading bit streams in Xilinx
46245: 02/08/22: Falk Brunner: Re: Downloading bit streams in Xilinx
46272: 02/08/23: Ramakrishnan: Re: Downloading bit streams in Xilinx
46342: 02/08/26: Caleb Hess: Re: Downloading bit streams in Xilinx
46246: 02/08/22: N.O.V.: Re: Downloading bit streams in Xilinx
46249: 02/08/22: Peter Alfke: Re: Downloading bit streams in Xilinx
46250: 02/08/22: Bryan: Re: Downloading bit streams in Xilinx
46252: 02/08/22: Austin Lesea: Re: Downloading bit streams in Xilinx
46253: 02/08/22: Bryan: Re: Downloading bit streams in Xilinx
46254: 02/08/22: Peter Alfke: Re: Downloading bit streams in Xilinx
46255: 02/08/22: Eric Smith: Re: Downloading bit streams in Xilinx
46257: 02/08/23: Daryl: FPGA speed level
46266: 02/08/23: Muthu: Re: FPGA speed level
46317: 02/08/25: Neeraj: Re: FPGA speed level
46352: 02/08/27: Daryl: Re: FPGA speed level
46358: 02/08/27: Peter Alfke: Re: FPGA speed level
46359: 02/08/27: Nicholas C. Weaver: Re: FPGA speed level
46364: 02/08/27: Hal Murray: Re: FPGA speed level
46371: 02/08/27: Ray Andraka: Re: FPGA speed level
46599: 02/09/04: Hal Murray: Re: FPGA speed level
46259: 02/08/22: suchitra: programming xc9536 xl
46267: 02/08/23: Falk Brunner: Re: programming xc9536 xl
46269: 02/08/23: Ryan Laity: Re: programming xc9536 xl
46260: 02/08/23: Andreas Kugel: Virtex-2Pro CPU to memory performance
46270: 02/08/23: Austin Lesea: Re: Virtex-2Pro CPU to memory performance
46261: 02/08/23: shujah: optimizied decimation filter design in VHDL
46268: 02/08/23: steve synakowski: XPLA3 coolrunner erased i/o state?
46271: 02/08/23: Stephan Neuhold: Re: XPLA3 coolrunner erased i/o state?
46273: 02/08/23: steve synakowski: Re: XPLA3 coolrunner erased i/o state?
46276: 02/08/23: cfk: Alliance VLSI software
46277: 02/08/23: BasePointer: Help for Schematic Components
46279: 02/08/23: cfk: Re: Help for Schematic Components
46287: 02/08/24: BasePointer: Re: Help for Schematic Components
46293: 02/08/24: John_H: Re: Help for Schematic Components
46295: 02/08/24: BasePointer: Re: Help for Schematic Components
46294: 02/08/24: cfk: Re: Help for Schematic Components
46281: 02/08/23: Theron Hicks: need cheap and dirty time delay for spartan2e
46284: 02/08/24: Helmut Sennewald: Re: need cheap and dirty time delay for spartan2e
46290: 02/08/24: Theron Hicks: Re: need cheap and dirty time delay for spartan2e
46291: 02/08/24: Helmut Sennewald: Re: need cheap and dirty time delay for spartan2e
46292: 02/08/24: Theron Hicks: Re: need cheap and dirty time delay for spartan2e
46338: 02/08/26: Peter Alfke: Re: need cheap and dirty time delay for spartan2e
46350: 02/08/27: Ray Andraka: Re: need cheap and dirty time delay for spartan2e
46363: 02/08/26: Eric Smith: Spartan-II inrush and other power suppy isues (was Re: need cheap and dirty time delay for spartan2e)
46372: 02/08/27: Austin Lesea: Re: Spartan-II inrush and other power suppy isues (was Re: need cheap
46476: 02/08/31: Eric Smith: Re: Spartan-II inrush and other power suppy isues (was Re: need cheap and dirty time delay for spartan2e)
46282: 02/08/23: Theron Hicks: done output signal drive levels? (spartan2e)
46285: 02/08/24: William LenihanIii: upgrade S/W -> timing worse
46286: 02/08/24: <hamish@cloud.net.au>: Re: upgrade S/W -> timing worse
46288: 02/08/24: Rick Filipkiewicz: Re: upgrade S/W -> timing worse
46297: 02/08/25: Ray Andraka: Re: upgrade S/W -> timing worse
46300: 02/08/25: <hamish@cloud.net.au>: Re: upgrade S/W -> timing worse
46306: 02/08/25: Ray Andraka: Re: upgrade S/W -> timing worse
46289: 02/08/24: S. Ramirez: Why Can't Engineers Be Like Doctors?
46298: 02/08/25: BasePointer: Can I directly connect XTAL to SpartanXL ?
46302: 02/08/25: Falk Brunner: Re: Can I directly connect XTAL to SpartanXL ?
46323: 02/08/26: BasePointer: Re: Can I directly connect XTAL to SpartanXL ?
46331: 02/08/26: Ray Andraka: Re: Can I directly connect XTAL to SpartanXL ?
46368: 02/08/27: BasePointer: Re: Can I directly connect XTAL to SpartanXL ?
46303: 02/08/25: Peter Alfke: Re: Can I directly connect XTAL to SpartanXL ?
46299: 02/08/25: SUDIP SAHA: I2C BUS
46301: 02/08/25: Jianyong Niu: Re: I2C BUS
46307: 02/08/25: Ray Andraka: Re: I2C BUS
46771: 02/09/08: Thomas Wambera: Re: I2C BUS
46304: 02/08/25: Big Swede: Floorplanning 101
46308: 02/08/25: Ray Andraka: Re: Floorplanning 101
46309: 02/08/25: Philip Freidin: Re: Floorplanning 101
46356: 02/08/26: Kevin Brace: Re: Floorplanning 101
46305: 02/08/25: cfk: sensing an oscillator
46310: 02/08/25: Peter Alfke: Re: sensing an oscillator
46313: 02/08/26: steve bessette: Re: sensing an oscillator
46315: 02/08/26: cfk: Re: sensing an oscillator
46319: 02/08/26: Ben Twijnstra: Re: sensing an oscillator
46339: 02/08/26: Peng: Re: sensing an oscillator
46435: 02/08/29: Marcel: Re: sensing an oscillator
46311: 02/08/25: =?ISO-8859-1?Q?Narc=EDs_Nadal?=: Any FSM optimizer?
46375: 02/08/27: =?ISO-8859-1?Q?Narc=EDs_Nadal?=: Re: Any FSM optimizer?
46376: 02/08/27: Peter Alfke: Re: Any FSM optimizer?
46386: 02/08/28: nospam: Re: Any FSM optimizer?
46432: 02/08/29: Falk Brunner: Re: Any FSM optimizer?
46389: 02/08/28: Ray Andraka: Re: Any FSM optimizer?
46391: 02/08/28: Hal Murray: Re: Any FSM optimizer?
46404: 02/08/28: Peter Alfke: Re: Any FSM optimizer?
46446: 02/08/30: Hal Murray: Re: Any FSM optimizer?
46377: 02/08/27: Dennis McCrohan: Re: Any FSM optimizer?
46383: 02/08/28: Jim Granville: Re: Any FSM optimizer?
46387: 02/08/28: Peter Alfke: Re: Any FSM optimizer?
46388: 02/08/28: Jim Granville: Re: Any FSM optimizer?
46409: 02/08/28: =?ISO-8859-1?Q?Narc=EDs_Nadal?=: Re: Any FSM optimizer?
46412: 02/08/28: Peter Alfke: Re: Any FSM optimizer?
46381: 02/08/27: John_H: Re: Any FSM optimizer?
46403: 02/08/28: Dennis McCrohan: Re: Any FSM optimizer?
46408: 02/08/29: Jim Granville: Re: Any FSM optimizer?
46411: 02/08/28: John_H: Re: Any FSM optimizer?
46312: 02/08/25: hristo: Virtex2 and Virtex-E speed performance
46314: 02/08/26: Ray Andraka: Re: Virtex2 and Virtex-E speed performance
46316: 02/08/25: Mike Rosing: Re: Question on Fast CPLDs
46320: 02/08/26: liran: writeing a synthesized vhdl code for "shifter "
46330: 02/08/26: Ray Andraka: Re: writeing a synthesized vhdl code for "shifter "
46321: 02/08/26: Børge Strand: Export from ModelSim to Excel?
46322: 02/08/26: Paul Baxter: Re: Export from ModelSim to Excel?
46324: 02/08/26: Børge Strand: Re: Export from ModelSim to Excel?
46337: 02/08/26: Davis Moore: Re: Export from ModelSim to Excel?
46370: 02/08/27: Utku Ozcan: Re: Export from ModelSim to Excel?
46325: 02/08/26: Sven Tejcka: Anyone already on QUARTUS II V2.1 ?
46354: 02/08/26: Kevin Brace: Re: Anyone already on QUARTUS II V2.1 ?
46355: 02/08/27: ds: Re: Anyone already on QUARTUS II V2.1 ?
46362: 02/08/27: Kevin Brace: Re: Anyone already on QUARTUS II V2.1 ?
46382: 02/08/27: ds: Re: Anyone already on QUARTUS II V2.1 ?
46441: 02/08/30: ds: Re: Anyone already on QUARTUS II V2.1 ?
46357: 02/08/27: Jim Granville: Re: Anyone already on QUARTUS II V2.1 ?
46384: 02/08/28: Jim Patterson: Re: Anyone already on QUARTUS II V2.1 ?
46332: 02/08/26: Jan Van Belle: Starting with VHDL
46334: 02/08/26: qdsn: help me with analogue FPGAs or FPAA (and TRAC, PSOC, ispPAC etc.)
46336: 02/08/26: jetmarc: Evaluation board recommendation?
46378: 02/08/27: Tom Loftus: Re: Evaluation board recommendation?
46340: 02/08/26: Martin E.: VirtexII: HSWAP_EN
46343: 02/08/26: Austin Lesea: Re: VirtexII: HSWAP_EN
46344: 02/08/26: Austin Lesea: Re: VirtexII: HSWAP_EN
46347: 02/08/26: Martin E.: Re: VirtexII: HSWAP_EN
46348: 02/08/27: Martin E.: Re: VirtexII: HSWAP_EN
46349: 02/08/26: Austin Lesea: Re: VirtexII: HSWAP_EN
46351: 02/08/27: Martin E.: Re: VirtexII: HSWAP_EN
46353: 02/08/26: Austin Lesea: Re: VirtexII: HSWAP_EN
46373: 02/08/27: Martin E.: Re: VirtexII: HSWAP_EN
46341: 02/08/26: Ewan D. Milne: Virtex2 Pro Device support in Webpack?
46423: 02/08/29: Chris Rutten: Virtex2 Pro Device support in Webpack?
46361: 02/08/26: =?ISO-8859-1?Q?Stein_Kj=F8lstad?=: Xilinx Virtex-II : ICAP?
46365: 02/08/27: ted: Altera Quartus II problems
46366: 02/08/27: Horst Trattnig: Re: Altera Quartus II problems
46379: 02/08/27: ted: Re: Altera Quartus II problems
46392: 02/08/27: Karl: Re: Altera Quartus II problems
46398: 02/08/28: ted: Re: Altera Quartus II problems
46399: 02/08/28: Horst Trattnig: Re: Altera Quartus II problems
46420: 02/08/28: Dennis: Re: Altera Quartus II problems
46424: 02/08/29: ted: Re: Altera Quartus II problems
46369: 02/08/27: Udo Weik: Virtex-IIpro Demo-Boards
46380: 02/08/27: Tom Loftus: Re: Virtex-IIpro Demo-Boards
46394: 02/08/28: Udo Weik: Re: Virtex-IIpro Demo-Boards
46395: 02/08/28: Grog: My SpartanII thinks it's a Virtex??
46400: 02/08/28: Ray Andraka: Re: My SpartanII thinks it's a Virtex??
46405: 02/08/28: Mark Momcilovich: Re: My SpartanII thinks it's a Virtex??
46407: 02/08/28: Nicholas C. Weaver: Re: My SpartanII thinks it's a Virtex??
46419: 02/08/29: ds: Re: My SpartanII thinks it's a Virtex??
46427: 02/08/29: Peter Alfke: Re: My SpartanII thinks it's a Virtex??
46396: 02/08/28: Petter Gustad: ISE 5.1 Linux?
47158: 02/09/19: Petter Gustad: Re: ISE 5.1 Linux?
47163: 02/09/19: Kamal Patel: Re: ISE 5.1 Linux?
47401: 02/09/24: Dan: Re: ISE 5.1 Linux?
47457: 02/09/25: Duane Clark: Re: ISE 5.1 Linux?
46397: 02/08/28: Petres, Zoltan: Neural hardware containing many neurons but very simple computation
46668: 02/09/05: Havatcha: Re: Neural hardware containing many neurons but very simple computation
46685: 02/09/05: reply in the newsgroup: Re: Neural hardware containing many neurons but very simple computation
46702: 02/09/06: Havatcha: Re: Neural hardware containing many neurons but very simple computation
46718: 02/09/06: Falk Brunner: Re: Neural hardware containing many neurons but very simple computation
46763: 02/09/07: =?ISO-8859-1?Q?Narc=EDs_Nadal?=: Re: Neural hardware containing many neurons but very simple computation
46401: 02/08/28: Thomas: Webpack : Order of compiling modules
46402: 02/08/28: Mike Treseler: Re: Webpack : Order of compiling modules
46410: 02/08/28: admin: discrepancies in Xilinx xapp253, DDR SDRAM controller.
46444: 02/08/29: Parry: Re: discrepancies in Xilinx xapp253, DDR SDRAM controller.
46413: 02/08/28: Josh Model: WebPack FSM woes...
46414: 02/08/29: Jim Granville: Re: WebPack FSM woes...
46415: 02/08/29: Helmut Sennewald: Re: WebPack FSM woes...
46416: 02/08/28: Mike Treseler: Re: WebPack FSM woes...
46417: 02/08/28: Jim Raynor: Problem: Spartan 2 E CCLK
46431: 02/08/29: Falk Brunner: Re: Problem: Spartan 2 E CCLK
46436: 02/08/29: lng: Re: Problem: Spartan 2 E CCLK
46418: 02/08/29: Russell: New xilinx tools
46421: 02/08/29: pramod kappagantula: Xilinx ISE , using Xpower for dynamic power determination
46422: 02/08/29: Charles Wagner: virtex target library
46425: 02/08/29: Christopher Saunter: LabVIEW -> FPGA
47006: 02/09/13: Brannon King: Re: LabVIEW -> FPGA
46426: 02/08/29: Xiang Gu: Is there any Development Board for developing a MIL-STD-1553B protocol chip?
46428: 02/08/29: Govind Kharbanda: Handel-C data widths
46448: 02/08/30: Neil Stainton: Re: Handel-C data widths
46453: 02/08/30: Dr. Andy Nisbet: Re: Handel-C data widths
46515: 02/09/02: Govind Kharbanda: Re: Handel-C data widths
46433: 02/08/29: Austin Lesea: Re: Use SSTL2_I or SSTL2_II for bidir?
46443: 02/08/30: Hal Murray: Re: Use SSTL2_I or SSTL2_II for bidir?
46430: 02/08/29: Hugo: Use SSTL2_I or SSTL2_II for bidir on VirtexII?
46437: 02/08/29: Denis Gleeson: gate the main FPGA clk
46438: 02/08/29: Peter Alfke: Re: gate the main FPGA clk
46473: 02/08/30: Denis Gleeson: Re: gate the main FPGA clk
46480: 02/08/31: Falk Brunner: Re: gate the main FPGA clk
46461: 02/08/30: Falk Brunner: Re: gate the main FPGA clk
46469: 02/08/30: Nicholas C. Weaver: Re: gate the main FPGA clk
46470: 02/08/30: Peter Alfke: Re: gate the main FPGA clk
46472: 02/08/30: Hal Murray: Silicon lifetime
46474: 02/08/30: Peter Alfke: Re: Silicon lifetime
47238: 02/09/20: rk: Re: Silicon lifetime
47249: 02/09/21: Uwe Bonnes: Re: Silicon lifetime
46495: 02/09/01: Denis Gleeson: Re: gate the main FPGA clk
46496: 02/09/01: Nicholas C. Weaver: Re: gate the main FPGA clk
46439: 02/08/29: Hul Tytus: Any FSM optimizer
46440: 02/08/29: spyng: sustainable rate for Random Read of DDR SDRAM
47007: 02/09/13: rickman: Re: sustainable rate for Random Read of DDR SDRAM
47009: 02/09/14: Paul Baxter: Re: sustainable rate for Random Read of DDR SDRAM
46442: 02/08/29: Anjan: tristate bus
46447: 02/08/30: Chris Rutten: tristate bus
46960: 02/09/13: Emil Blaschek: Re: tristate bus
46445: 02/08/30: Kenneth: Question on Fast CPLDs
46460: 02/08/30: Falk Brunner: Re: Question on Fast CPLDs
46486: 02/09/01: Kenneth: Re: Question on Fast CPLDs
47106: 02/09/17: Mark Korsloot: Re: Question on Fast CPLDs
46449: 02/08/30: Christian Kramer: Crashes while reading from memory with Nios
46467: 02/08/30: Jesse Kempa: Re: Crashes while reading from memory with Nios
46450: 02/08/30: Theo: Virtex-II partial reconfiguration flow diagram
46464: 02/08/30: Steve Casselman: Re: Virtex-II partial reconfiguration flow diagram
46451: 02/08/30: E. Napoli: XNF vs. EDIF
46459: 02/08/30: Vikram Pasham: Re: XNF vs. EDIF
46463: 02/08/30: Steve Casselman: Re: XNF vs. EDIF
46465: 02/08/30: Nicholas C. Weaver: Re: XNF vs. EDIF
46452: 02/08/30: Uwe Bonnes: Availability of Xilinx Coolrunner II
46454: 02/08/30: arvind: problem configration spartan2 with prom.
46455: 02/08/30: Nicolas Matringe: Re: problem configration spartan2 with prom.
46504: 02/09/01: David Colson: Re: problem configration spartan2 with prom.
46511: 02/09/02: Piotr Foryt: Re: problem configration spartan2 with prom.
46456: 02/08/30: Paul Baxter: SDRAM - is concurrent auto precharge common?
46458: 02/08/30: Spam Hater: Re: SDRAM - is concurrent auto precharge common?
46481: 02/08/31: Spam Hater: Re: SDRAM - is concurrent auto precharge common?
46457: 02/08/30: hugo: Max SSO in Virtex2 (Simultaneously Switching Out
46462: 02/08/30: Charles Wagner: RAM in CCC behavioral FPGA
46466: 02/08/30: Stephan Flock: Webpack 4.2 Schematic
46482: 02/08/31: Al Williams: Re: Webpack 4.2 Schematic
46483: 02/08/31: Frank Andreas de Groot: Re: Webpack 4.2 Schematic
46490: 02/09/01: Al Williams: Re: Webpack 4.2 Schematic
46491: 02/09/01: Al Williams: Re: Webpack 4.2 Schematic
46505: 02/09/02: Frank Andreas de Groot: Re: Webpack 4.2 Schematic
46641: 02/09/05: Ray Andraka: Re: Webpack 4.2 Schematic
46487: 02/09/01: Stephan Flock: Re: Webpack 4.2 Schematic
46574: 02/09/03: Al Williams: Re: Webpack 4.2 Schematic
46471: 02/08/30: Peter Alfke: The Prodigal Son
46475: 02/08/30: Tom Liehe: Re: The Prodigal Son
46477: 02/08/31: Paul Baxter: Re: The Prodigal Son
46589: 02/09/04: Neeraj Varma: Re: The Prodigal Son
46478: 02/08/31: Jianrong Wang: A little question
46479: 02/08/31: Falk Brunner: Re: A little question
46512: 02/09/02: Neeraj: Re: A little question
46524: 02/09/02: Falk Brunner: Re: A little question
46484: 02/08/31: Jan Gray: Virtex/E/2/2P area efficient addmux, reiterating PAR timing modeler enhancement request
46489: 02/09/01: Nicholas C. Weaver: Re: Virtex/E/2/2P area efficient addmux, reiterating PAR timing modeler enhancement request
46498: 02/09/01: John_H: Re: Virtex/E/2/2P area efficient addmux, reiterating PAR timing modeler enhancement request
46508: 02/09/01: Jan Gray: Re: Virtex/E/2/2P area efficient addmux, reiterating PAR timing modeler enhancement request
46913: 02/09/11: John_H: Re: Virtex/E/2/2P area efficient addmux, reiterating PAR timing modeler
46941: 02/09/12: Jan Gray: Re: Virtex/E/2/2P area efficient addmux, reiterating PAR timing modeler enhancement request
46485: 02/08/31: Masoud Naderi: Thermoelectric Controller by FPGAs
46488: 02/09/01: Janusz Raniszewski: Re: Thermoelectric Controller by FPGAs
46493: 02/09/01: Eric Braeden: Re: Thermoelectric Controller by FPGAs
46494: 02/09/01: Spehro Pefhany: Re: Thermoelectric Controller by FPGAs
46497: 02/09/01: Peter Alfke: Re: Thermoelectric Controller by FPGAs
46501: 02/09/01: Philip Freidin: Re: Thermoelectric Controller by FPGAs
46509: 02/09/02: Holger Venus: Re: Thermoelectric Controller by FPGAs
46513: 02/09/02: Spehro Pefhany: Re: Thermoelectric Controller by FPGAs
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