Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015Jan2015

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Threads Starting Nov 2008

136107: 08/11/01: Alessandro: timing issue with ISE10 SP3
    136108: 08/11/01: Gabor: Re: timing issue with ISE10 SP3
        136110: 08/11/02: Alessandro: Re: timing issue with ISE10 SP3
        136119: 08/11/02: Alessandro: Re: timing issue with ISE10 SP3
    136111: 08/11/02: Brian Drummond: Re: timing issue with ISE10 SP3
136117: 08/11/02: subbu instru: requesting solution for error:HDLParsers:810
    136122: 08/11/03: Brian Drummond: Re: requesting solution for error:HDLParsers:810
        136128: 08/11/03: Brian Drummond: Re: requesting solution for error:HDLParsers:810
            136129: 08/11/03: Sean Durkin: Re: requesting solution for error:HDLParsers:810
    136124: 08/11/02: subbu instru: Re: requesting solution for error:HDLParsers:810
136120: 08/11/02: Alessandro: blockram init file in spartan 3E
    136131: 08/11/03: Gabor: Re: blockram init file in spartan 3E
        136137: 08/11/03: Alessandro: Re: blockram init file in spartan 3E
            136152: 08/11/04: unknown: Re: blockram init file in spartan 3E
    136135: 08/11/03: unknown: Re: blockram init file in spartan 3E
136123: 08/11/03: Michael Dreschmann: 2D DCT algorithm
    136163: 08/11/04: Guenter Dannoritzer: Re: 2D DCT algorithm
        136261: 08/11/08: Michael Dreschmann: Re: 2D DCT algorithm
136125: 08/11/02: 500milesaway: needs help on CLOCK
    136126: 08/11/02: Thomas Stanka: Re: needs help on CLOCK
136127: 08/11/03: mikel: Altera simulation models performance
    136134: 08/11/03: Joseph H Allen: Re: Altera simulation models performance
    136201: 08/11/05: mikel: Re: Altera simulation models performance
136130: 08/11/03: Rob: Re: classic Spartan-3 DDR2 and IOBs
136138: 08/11/03: Allard: Testing ARM/FPGA with IAR EWARM and ModelSim (with Tcl Interface)
136139: 08/11/03: fl: Why does Nios cannot pass make?
    136140: 08/11/03: Allard: Re: Why does Nios cannot pass make?
        136143: 08/11/04: Mark McDougall: Re: Why does Nios cannot pass make?
            136150: 08/11/04: Mark McDougall: Re: Why does Nios cannot pass make?
    136141: 08/11/03: fl: Re: Why does Nios cannot pass make?
    136146: 08/11/03: fl: Re: Why does Nios cannot pass make?
    136151: 08/11/03: Muzaffer Kal: Re: Why does Nios cannot pass make?
    136159: 08/11/04: fl: Re: Why does Nios cannot pass make?
136144: 08/11/03: <y.tachwali@gmail.com>: How to move project files from ISE 7.1 to ISE 10.1
    136145: 08/11/03: LittleAlex: Re: How to move project files from ISE 7.1 to ISE 10.1
    136148: 08/11/03: <y.tachwali@gmail.com>: Re: How to move project files from ISE 7.1 to ISE 10.1
    136153: 08/11/04: Moazzam: Re: How to move project files from ISE 7.1 to ISE 10.1
    136157: 08/11/04: Brian Drummond: Re: How to move project files from ISE 7.1 to ISE 10.1
    136186: 08/11/05: <y.tachwali@gmail.com>: Re: How to move project files from ISE 7.1 to ISE 10.1
    136187: 08/11/05: <y.tachwali@gmail.com>: Re: How to move project files from ISE 7.1 to ISE 10.1
    136218: 08/11/06: LittleAlex: Re: How to move project files from ISE 7.1 to ISE 10.1
136154: 08/11/04: Mohamed: GRFPU SDF and simulation VHDL
136156: 08/11/04: ikki: RS-232 Bus controller design in VHDL
    136158: 08/11/04: Stef: Re: RS-232 Bus controller design in VHDL
        136160: 08/11/04: ikki: Re: RS-232 Bus controller design in VHDL
            136161: 08/11/04: Stef: Re: RS-232 Bus controller design in VHDL
            136162: 08/11/04: Stef: Re: RS-232 Bus controller design in VHDL
            136174: 08/11/04: Mike Treseler: Re: RS-232 Bus controller design in VHDL
            136220: 08/11/06: Glen Herrmannsfeldt: Re: RS-232 Bus controller design in VHDL
                136274: 08/11/09: ikki: Re: RS-232 Bus controller design in VHDL
                    136275: 08/11/09: Jonathan Bromley: Re: RS-232 Bus controller design in VHDL
                        136277: 08/11/09: Hal Murray: Re: RS-232 Bus controller design in VHDL
                            136278: 08/11/09: Jonathan Bromley: Re: RS-232 Bus controller design in VHDL
                                136280: 08/11/09: Mike Treseler: Re: RS-232 Bus controller design in VHDL
                                    136290: 08/11/10: Jonathan Bromley: Re: RS-232 Bus controller design in VHDL
                                        136303: 08/11/10: Mike Treseler: Re: RS-232 Bus controller design in VHDL
                        136292: 08/11/10: ikki: Re: RS-232 Bus controller design in VHDL
                            136307: 08/11/10: Mike Treseler: Re: RS-232 Bus controller design in VHDL
    136181: 08/11/04: mng: Re: RS-232 Bus controller design in VHDL
    136190: 08/11/05: <lomtikster@gmail.com>: Re: RS-232 Bus controller design in VHDL
    136192: 08/11/05: Gabor: Re: RS-232 Bus controller design in VHDL
    136197: 08/11/05: LittleAlex: Re: RS-232 Bus controller design in VHDL
136164: 08/11/04: Klaus: Critical Path
    136165: 08/11/04: Klaus: Re: Critical Path
        136167: 08/11/04: John_H: Re: Critical Path
            136168: 08/11/04: Klaus: Re: Critical Path
                136169: 08/11/04: Stephan van Beek: Re: Critical Path
                136173: 08/11/04: Muzaffer Kal: Re: Critical Path
                    136175: 08/11/04: Klaus: Re: Critical Path
                        136176: 08/11/04: Muzaffer Kal: Re: Critical Path
                            136196: 08/11/05: Klaus: Re: Critical Path
        136199: 08/11/05: KJ: Re: Critical Path
        136200: 08/11/05: John_H: Re: Critical Path
136166: 08/11/04: Eric: Tiny JTAG connector
    136171: 08/11/04: Nico Coesel: Re: Tiny JTAG connector
        136177: 08/11/04: BobW: Re: Tiny JTAG connector
    136172: 08/11/04: <Dave@x.com>: Re: Tiny JTAG connector
    136180: 08/11/04: Jon Elson: Re: Tiny JTAG connector
    136194: 08/11/05: Gabor: Re: Tiny JTAG connector
    136207: 08/11/05: Rob: Re: Tiny JTAG connector
    136208: 08/11/06: Symon: Re: Tiny JTAG connector
    136223: 08/11/07: John Adair: Re: Tiny JTAG connector
136170: 08/11/04: <terry@norpak.ca>: ALTERA ALT2GXB RECONFIG BLOCK
136182: 08/11/05: Claire: Learning programming an FPGAs
    136183: 08/11/04: John McCaskill: Re: Learning programming an FPGAs
    136205: 08/11/05: Stonethrower: Re: Learning programming an FPGAs
        136316: 08/11/11: MikeWhy: Re: Learning programming an FPGAs
136184: 08/11/04: knight: EDK 9.1, Lwip stack, Generate Library and BSPs error
136185: 08/11/04: Rayees: Help Me Plz
    136212: 08/11/07: RedskullDC: Re: Help Me Plz
136189: 08/11/05: <lomtikster@gmail.com>: Connecting TFT Controller's signals, Microblaze
136191: 08/11/05: <lomtikster@gmail.com>: Xilinx TFT controller
    136195: 08/11/05: Matthias Alles: Re: Xilinx TFT controller
    136294: 08/11/10: <lomtikster@gmail.com>: Re: Xilinx TFT controller
136198: 08/11/05: jammurao: Usage of Rocket IO GTP for 32 bit interface
136202: 08/11/05: James Harris: Xmos now shipping sillicon
    136203: 08/11/05: James Harris: Re: Xmos now shipping silicon
    136204: 08/11/05: Leon: Re: Xmos now shipping silicon
136209: 08/11/05: jacko: nibz processor new version
136211: 08/11/06: Rayees: How SPI Flash UserData is Accessed?
136213: 08/11/06: FP: TCP/IP 3 way handshake
    136214: 08/11/06: Stef: Re: TCP/IP 3 way handshake
    136215: 08/11/06: Jon Beniston: Re: TCP/IP 3 way handshake
    136216: 08/11/06: James Harris: Re: TCP/IP 3 way handshake
    136219: 08/11/06: Glen Herrmannsfeldt: Re: TCP/IP 3 way handshake
136217: 08/11/06: <1stderivative@gmail.com>: face recognition
    136221: 08/11/06: John_H: Re: face recognition
    136242: 08/11/07: Benjamin Couillard: Re: face recognition
    136260: 08/11/07: Francois Choquette: Re: face recognition
    136279: 08/11/09: Benjamin Couillard: Re: face recognition
136222: 08/11/07: mentari: Tilera multicore replaces FPGA?
    136228: 08/11/07: Jeff Cunningham: Re: Tilera multicore replaces FPGA?
    136229: 08/11/07: Leon: Re: Tilera multicore replaces FPGA?
    136231: 08/11/07: Benjamin Couillard: Re: Tilera multicore replaces FPGA?
        136256: 08/11/08: Jim Granville: Re: Tilera multicore replaces FPGA?
        136287: 08/11/10: Markus: Re: Tilera multicore replaces FPGA?
        136333: 08/11/11: Alex Colvin: Re: Tilera multicore replaces FPGA?
    136234: 08/11/07: Benjamin Couillard: Re: Tilera multicore replaces FPGA?
    136236: 08/11/07: Leon: Re: Tilera multicore replaces FPGA?
    136238: 08/11/07: Leon: Re: Tilera multicore replaces FPGA?
    136241: 08/11/07: mentari: Re: Tilera multicore replaces FPGA?
    136244: 08/11/07: Benjamin Couillard: Re: Tilera multicore replaces FPGA?
    136249: 08/11/07: Leon: Re: Tilera multicore replaces FPGA?
    136251: 08/11/07: Benjamin Couillard: Re: Tilera multicore replaces FPGA?
    136252: 08/11/07: Petter Gustad: Re: Tilera multicore replaces FPGA?
    136253: 08/11/07: Leon: Re: Tilera multicore replaces FPGA?
    136257: 08/11/07: John_H: Re: Tilera multicore replaces FPGA?
    136265: 08/11/07: mentari: Re: Tilera multicore replaces FPGA?
    136298: 08/11/10: Leon: Re: Tilera multicore replaces FPGA?
136224: 08/11/07: Felix Stocker: Xilinx Floorplaner X,y Coordinates
    136258: 08/11/07: John_H: Re: Xilinx Floorplaner X,y Coordinates
136225: 08/11/07: Dale: Setting FSM encoding in VHDL or in UCF for Xilinx
    136230: 08/11/07: Jeff Cunningham: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
        136262: 08/11/07: KJ: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
    136232: 08/11/07: Dale: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
    136235: 08/11/07: LittleAlex: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
    136237: 08/11/07: Dale: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
    136239: 08/11/07: Mike Treseler: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
    136243: 08/11/07: Dale: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
    136245: 08/11/07: Dale: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
    136246: 08/11/07: Dale: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
    136247: 08/11/07: KJ: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
    136248: 08/11/07: KJ: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
    136250: 08/11/07: Dale: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
    136254: 08/11/07: KJ: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
    136259: 08/11/07: Dale: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
136226: 08/11/07: <uraniumore238@gmail.com>: led programming
    136240: 08/11/07: <Dave@x.com>: Re: led programming
    136255: 08/11/07: Gabor: Re: led programming
136227: 08/11/07: timinganalyzer: request: sample vcd files for TimingAnalyzer
    136310: 08/11/10: Amal: Re: request: sample vcd files for TimingAnalyzer
        136319: 08/11/11: HT-Lab: Re: request: sample vcd files for TimingAnalyzer
    136314: 08/11/10: timinganalyzer: Re: request: sample vcd files for TimingAnalyzer
    136327: 08/11/11: timinganalyzer: Re: request: sample vcd files for TimingAnalyzer
136233: 08/11/07: Benjamin Krill: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
136263: 08/11/07: KJ: Data transfer between CPU and FPGA over PCI bus
    136270: 08/11/08: Andreas Ehliar: Re: Data transfer between CPU and FPGA over PCI bus
    136281: 08/11/09: beeraka@gmail.com: Re: Data transfer between CPU and FPGA over PCI bus
    136318: 08/11/11: Hal Murray: Re: Data transfer between CPU and FPGA over PCI bus
136264: 08/11/07: Leon: Altera Quartus II 8.1
    136266: 08/11/07: Leon: Re: Altera Quartus II 8.1
        136267: 08/11/07: guestuser1: Re: Altera Quartus II 8.1 (and Modelsim AE 6.3g)
136269: 08/11/07: guestuser1: Synplicity/Synplify and Systemverilog support?
    136271: 08/11/08: <filter001@desinformation.de>: Re: Synplicity/Synplify and Systemverilog support?
    136276: 08/11/09: cms: Re: Synplicity/Synplify and Systemverilog support?
        136420: 08/11/15: atass: Re: Synplicity/Synplify and Systemverilog support?
            136423: 08/11/15: Jonathan Bromley: Re: Synplicity/Synplify and Systemverilog support?
                136441: 08/11/17: Andreas Ehliar: Re: Synplicity/Synplify and Systemverilog support?
                    136448: 08/11/17: Jonathan Bromley: Re: Synplicity/Synplify and Systemverilog support?
                136457: 08/11/17: atass: Re: Synplicity/Synplify and Systemverilog support?
                    136619: 08/11/26: shalom: Re: Synplicity/Synplify and Systemverilog support?
        136450: 08/11/17: cms: Re: Synplicity/Synplify and Systemverilog support?
136282: 08/11/09: Jamie Morken: FIR filter in Quartus
136283: 08/11/10: Andreas Ehliar: Re: How to handle the problem "timing constraint not met"?
136286: 08/11/09: <atulm1@gmail.com>: Connect XST board with PC through USB
    136352: 08/11/12: Dave Pollum: Re: Connect XST board with PC through USB
136288: 08/11/09: mynewlifever@yahoo.com.cn: How to handle the problem "timing constraint not met"?
    136291: 08/11/10: Hal Murray: Re: How to handle the problem "timing constraint not met"?
        136317: 08/11/11: Hal Murray: Re: How to handle the problem "timing constraint not met"?
            136322: 08/11/11: Uwe Bonnes: Re: How to handle the problem "timing constraint not met"?
                136329: 08/11/11: Hal Murray: Re: How to handle the problem "timing constraint not met"?
                    136332: 08/11/11: Uwe Bonnes: Re: How to handle the problem "timing constraint not met"?
    136312: 08/11/10: mynewlifever@yahoo.com.cn: Re: How to handle the problem "timing constraint not met"?
    136313: 08/11/10: mynewlifever@yahoo.com.cn: Re: How to handle the problem "timing constraint not met"?
136295: 08/11/10: <lomtikster@gmail.com>: Register access over PLB2DCR bridge
    136321: 08/11/11: sundar: Re: Register access over PLB2DCR bridge
    136325: 08/11/11: <lomtikster@gmail.com>: Re: Register access over PLB2DCR bridge
    136337: 08/11/11: <lomtikster@gmail.com>: Re: Register access over PLB2DCR bridge
    136339: 08/11/11: <lomtikster@gmail.com>: Re: Register access over PLB2DCR bridge
    136389: 08/11/13: sundar: Re: Register access over PLB2DCR bridge
136296: 08/11/10: Roger: SPI Flash Verify problem
136297: 08/11/10: wallra: hi all
    136315: 08/11/10: wallra: Re: hi all
    136320: 08/11/11: shawn: Re: hi all
    136811: 08/12/06: wallra: Re: hi all
    136816: 08/12/06: Gabor: Re: hi all
136299: 08/11/10: Max: Silicon used for realising FPGA logic
    136304: 08/11/11: David R Brooks: Re: Silicon used for realising FPGA logic
136300: 08/11/10: jjlindula@hotmail.com: Altera Quartus DDR2 Megacore function: local_address input: row, col,
    136301: 08/11/10: jjlindula@hotmail.com: Re: Altera Quartus DDR2 Megacore function: local_address input: row,
        136308: 08/11/10: KJ: Re: Altera Quartus DDR2 Megacore function: local_address input: row, col, bank?
    136305: 08/11/10: jjlindula@hotmail.com: Re: Altera Quartus DDR2 Megacore function: local_address input: row,
    136306: 08/11/10: jjlindula@hotmail.com: Re: Altera Quartus DDR2 Megacore function: local_address input: row,
    136311: 08/11/10: jjlindula@hotmail.com: Re: Altera Quartus DDR2 Megacore function: local_address input: row,
136323: 08/11/11: <alancanniff@gmail.com>: Virtex2pro Dimm slot memory
136326: 08/11/11: John Adair: Polmaddie1 - VHDL and Verilog Training Board
    136347: 08/11/12: Brian Drummond: Re: Polmaddie1 - VHDL and Verilog Training Board
    136350: 08/11/12: John Adair: Re: Polmaddie1 - VHDL and Verilog Training Board
136328: 08/11/11: Uwe Bonnes: How to constrain time-multiplexed pathes
    136330: 08/11/11: Andrew FPGA: Re: How to constrain time-multiplexed pathes
        136331: 08/11/11: Uwe Bonnes: Re: How to constrain time-multiplexed pathes
        136367: 08/11/13: Gael Paul: Re: How to constrain time-multiplexed pathes
    136377: 08/11/13: Mike Treseler: Re: How to constrain time-multiplexed pathes
        136385: 08/11/13: Andrew FPGA: Re: How to constrain time-multiplexed pathes
            136386: 08/11/13: Mike Treseler: Re: How to constrain time-multiplexed pathes
136335: 08/11/11: Jim Flanagan: CPLD newbie questions
    136338: 08/11/11: Thomas Stanka: Re: CPLD newbie questions
136340: 08/11/12: <o0o0ozd@gmail.com>: clock problem
    136342: 08/11/12: Sean Durkin: Re: clock problem
        136344: 08/11/12: Sean Durkin: Re: clock problem
            136356: 08/11/12: Sean Durkin: Re: clock problem
            136371: 08/11/13: Brian Drummond: Re: clock problem
    136343: 08/11/12: <o0o0ozd@gmail.com>: Re: clock problem
    136351: 08/11/12: Stef: Re: clock problem
    136353: 08/11/12: <o0o0ozd@gmail.com>: Re: clock problem
    136354: 08/11/12: <o0o0ozd@gmail.com>: Re: clock problem
    136355: 08/11/12: vasu: Re: clock problem
    136366: 08/11/13: <o0o0ozd@gmail.com>: Re: clock problem
136345: 08/11/12: <1stderivative@gmail.com>: Bluespec
    136359: 08/11/12: Mike Treseler: Re: Bluespec
136357: 08/11/12: bish: platform cable usb II problem
    136383: 08/11/13: Paul Boven: Re: platform cable usb II problem
        136406: 08/11/14: MM: Re: platform cable usb II problem
    136395: 08/11/14: bish: Re: platform cable usb II problem
    136416: 08/11/15: bish: Re: platform cable usb II problem
    136417: 08/11/15: bish: Re: platform cable usb II problem
136358: 08/11/12: Jan: Using the FF @ Port pin
    136360: 08/11/12: Gabor: Re: Using the FF @ Port pin
    136361: 08/11/12: Andrew FPGA: Re: Using the FF @ Port pin
        136363: 08/11/13: Jan: Re: Using the FF @ Port pin
    136414: 08/11/14: Paul Urbanus: Re: Using the FF @ Port pin
136368: 08/11/13: Saul Bernstein: Virtex5 XC5VFX70T
    136369: 08/11/13: Jon Beniston: Re: Virtex5 XC5VFX70T
        136370: 08/11/13: Saul Bernstein: Re: Virtex5 XC5VFX70T
    136375: 08/11/13: Mike Treseler: Re: Virtex5 XC5VFX70T
136374: 08/11/13: fl: Why memory for this Nios II is still not enough
    136378: 08/11/13: fl: Re: Why memory for this Nios II is still not enough
    136379: 08/11/13: Frank Buss: Re: Why memory for this Nios II is still not enough
        136382: 08/11/13: Frank Buss: Re: Why memory for this Nios II is still not enough
        136392: 08/11/14: Bas Laarhoven: Re: Why memory for this Nios II is still not enough
    136381: 08/11/13: fl: Re: Why memory for this Nios II is still not enough
    136469: 08/11/18: <jeffjcannon@gmail.com>: Re: Why memory for this Nios II is still not enough
136380: 08/11/14: Michael Brown: Re: Efficient clock dividers
136384: 08/11/13: Andy Botterill: How to stop using a signed subtractor
    136387: 08/11/13: Gabor: Re: How to stop using a signed subtractor
        136390: 08/11/14: Andy Botterill: Re: How to stop using a signed subtractor
            136408: 08/11/14: Andy Botterill: Re: How to stop using a signed subtractor
        136401: 08/11/14: Gabor: Re: How to stop using a signed subtractor
    136388: 08/11/13: Mike Treseler: Re: How to stop using a signed subtractor
136391: 08/11/13: axalay: Number of GCLKs: 9 out of 8 112% (OVERMAPPED)
    136398: 08/11/14: KJ: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED)
        136413: 08/11/14: Paul Urbanus: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED)
        136445: 08/11/17: Brian Drummond: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED)
    136400: 08/11/14: LittleAlex: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED)
    136415: 08/11/14: LittleAlex: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED)
    136438: 08/11/17: axalay: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED)
    136439: 08/11/17: axalay: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED)
136393: 08/11/14: knight: MAC PHY Configuration
    136405: 08/11/14: MM: Re: MAC PHY Configuration
    136435: 08/11/16: Jeff Cunningham: Re: MAC PHY Configuration
136394: 08/11/14: KingCharles: Host driver
    136397: 08/11/14: Kolja Sulimma: Re: Host driver
136396: 08/11/14: Andreas Ehliar: Re: purpose of MULTAND
    136409: 08/11/14: Jan Bruns: Re: purpose of MULTAND
    136440: 08/11/17: Andreas Ehliar: Re: purpose of MULTAND
136399: 08/11/14: Jan Bruns: purpose of MULTAND
    136443: 08/11/17: Kolja Sulimma: Re: purpose of MULTAND
    136447: 08/11/17: Kolja Sulimma: Re: purpose of MULTAND
136402: 08/11/14: fl: How to generate downloadable Nios II cpu ?
    136403: 08/11/14: fl: Re: How to generate downloadable Nios II cpu ?
        136437: 08/11/17: David Brown: Re: How to generate downloadable Nios II cpu ?
136404: 08/11/14: Philipp Klaus Krause: What happened to the Cyclone IV?
    136407: 08/11/15: Jim Granville: Re: What happened to the Cyclone IV?
        136418: 08/11/15: Philipp Klaus Krause: Re: What happened to the Cyclone IV?
            136422: 08/11/15: Mike Treseler: Re: What happened to the Cyclone IV?
            136424: 08/11/16: Jim Granville: Re: What happened to the Cyclone IV?
        136427: 08/11/16: John Adair: Re: What happened to the Cyclone IV?
        136465: 08/11/18: Prevailing over Technology: Re: What happened to the Cyclone IV?
136410: 08/11/14: John Adair: Polmaddie Development Board Family
136411: 08/11/14: jleslie48: rank beginner here, need to know where to start to get RS232 comm's
    136412: 08/11/14: LittleAlex: Re: rank beginner here, need to know where to start to get RS232
    136419: 08/11/15: jleslie48: Re: rank beginner here, need to know where to start to get RS232
    136442: 08/11/17: Andreas Ehliar: Re: rank beginner here, need to know where to start to get RS232 comm's working, and ...
        136476: 08/11/18: Glen Herrmannsfeldt: Re: rank beginner here, need to know where to start to get RS232
    136455: 08/11/17: jleslie48: Re: rank beginner here, need to know where to start to get RS232
    136466: 08/11/18: jleslie48: Re: rank beginner here, need to know where to start to get RS232
    137514: 09/01/21: Andreas Ehliar: Re: rank beginner here, need to know where to start to get RS232 comm's working, and ...
        137564: 09/01/22: Hal Murray: Re: rank beginner here, need to know where to start to get RS232 comm's working, and ...
    137516: 09/01/21: jeffrey.johnson: Re: rank beginner here, need to know where to start to get RS232 comm's working, and ...
    137523: 09/01/21: jleslie48: Re: rank beginner here, need to know where to start to get RS232
    137529: 09/01/21: jleslie48: Re: rank beginner here, need to know where to start to get RS232
    137574: 09/01/22: jleslie48: Re: rank beginner here, need to know where to start to get RS232
136426: 08/11/15: deep: vga interfacing for image display
    136428: 08/11/16: Alessandro: Re: vga interfacing for image display
        136477: 08/11/18: Glen Herrmannsfeldt: Re: vga interfacing for image display
            136481: 08/11/19: Mark McDougall: Re: vga interfacing for image display
                136516: 08/11/19: Glen Herrmannsfeldt: Re: vga interfacing for image display
                    136532: 08/11/20: Glen Herrmannsfeldt: Re: vga interfacing for image display
    136502: 08/11/19: <ales.gorkic@gmail.com>: Re: vga interfacing for image display
    136531: 08/11/20: Tommy Thorn: Re: vga interfacing for image display
136430: 08/11/16: laserbeak43: Digilent Spartan3e starter kit, Not working.
    136431: 08/11/16: Hal Murray: Re: Digilent Spartan3e starter kit, Not working.
        136433: 08/11/16: Hal Murray: Re: Digilent Spartan3e starter kit, Not working.
    136432: 08/11/16: laserbeak43: Re: Digilent Spartan3e starter kit, Not working.
    136434: 08/11/16: Ben Jackson: Re: Digilent Spartan3e starter kit, Not working.
    136451: 08/11/18: Michael Brown: Re: Digilent Spartan3e starter kit, Not working.
    136452: 08/11/17: Gabor: Re: Digilent Spartan3e starter kit, Not working.
    136527: 08/11/20: laserbeak43: Re: [SOLVED]Digilent Spartan3e starter kit, Not working.
136436: 08/11/16: Eric Smith: Spartan-3E SDRAM interface
    136444: 08/11/17: John Adair: Re: Spartan-3E SDRAM interface
        136449: 08/11/17: Gabor: Re: Spartan-3E SDRAM interface
136446: 08/11/17: cpld-fpga-asic: Link for Joining the FPGA/CPLD Design Group on LinkedIn
136453: 08/11/17: JohnOD: Xilinx-3E Starter Kit - USB connection with Linux
    136456: 08/11/18: Michael Brown: Re: Xilinx-3E Starter Kit - USB connection with Linux
        136462: 08/11/18: h.e.: Re: Xilinx-3E Starter Kit - USB connection with Linux
    136461: 08/11/17: <blair.bonnett@gmail.com>: Re: Xilinx-3E Starter Kit - USB connection with Linux
    136467: 08/11/18: JohnOD: Re: Xilinx-3E Starter Kit - USB connection with Linux
136454: 08/11/17: Jonathan Bromley: Aligned PLL clocks in RTL simulation
    136458: 08/11/17: Uwe Bonnes: Re: Aligned PLL clocks in RTL simulation
    136459: 08/11/17: Mike Treseler: Re: Aligned PLL clocks in RTL simulation
        136464: 08/11/18: Andy: Re: Aligned PLL clocks in RTL simulation
            136468: 08/11/18: Jonathan Bromley: Re: Aligned PLL clocks in RTL simulation
                136470: 08/11/18: Symon: Re: Aligned PLL clocks in RTL simulation
        136482: 08/11/18: Brian Davis: Re: Aligned PLL clocks in RTL simulation
    136460: 08/11/18: Mark McDougall: Re: Aligned PLL clocks in RTL simulation
    136463: 08/11/18: Allan Herriman: Re: Aligned PLL clocks in RTL simulation
    136475: 08/11/18: Hal Murray: Re: Aligned PLL clocks in RTL simulation
    136480: 08/11/18: Jim Lewis: Re: Aligned PLL clocks in RTL simulation
    136485: 08/11/19: Kim Enkovaara: Re: Aligned PLL clocks in RTL simulation
        136504: 08/11/19: Jim Lewis: Re: Aligned PLL clocks in RTL simulation
136471: 08/11/18: denish: spartan 3A dsp fpga memory
    136474: 08/11/18: Gabor: Re: spartan 3A dsp fpga memory
136472: 08/11/18: <uraniumore238@gmail.com>: spartan specifications
    136473: 08/11/18: Gabor: Re: spartan specifications
136478: 08/11/18: abe: opinion about various code generators
    136479: 08/11/18: Glen Herrmannsfeldt: Re: opinion about various code generators
    136484: 08/11/18: Dave: Re: opinion about various code generators
    136486: 08/11/18: Thomas Stanka: Re: opinion about various code generators
    136505: 08/11/19: Mike Treseler: Re: opinion about various code generators
        136588: 08/11/24: David Brown: Re: opinion about various code generators
            136602: 08/11/24: Mike Treseler: Re: opinion about various code generators
    136512: 08/11/19: Andy: Re: opinion about various code generators
136483: 08/11/18: KJ: how to implement an application with external memory in ISE?
    136487: 08/11/19: Lorenz Kolb: Re: how to implement an application with external memory in ISE?
    136496: 08/11/19: Enes Erdin: Re: how to implement an application with external memory in ISE?
        136528: 08/11/20: Brian Drummond: Re: how to implement an application with external memory in ISE?
    136519: 08/11/19: KJ: Re: how to implement an application with external memory in ISE?
    136522: 08/11/20: Enes Erdin: Re: how to implement an application with external memory in ISE?
136488: 08/11/18: =?ISO-8859-2?Q?Pawe=B3?=: Quatech SPPXP-100
136490: 08/11/19: John Evans: USB JTAG
    136494: 08/11/19: Rich Webb: Re: USB JTAG
    136495: 08/11/19: abe: Re: USB JTAG
    136509: 08/11/19: Finn S. Nielsen: Re: USB JTAG
136491: 08/11/19: Jan Bruns: Spartan3 SRL16 + SliceFF, LUT stability
    136497: 08/11/19: Jan Bruns: Re: Spartan3 SRL16 + SliceFF, LUT stability
        136503: 08/11/19: Jan Bruns: Re: Spartan3 SRL16 + SliceFF, LUT stability
        136506: 08/11/19: Mike Treseler: Re: Spartan3 SRL16 + SliceFF, LUT stability
            136508: 08/11/19: Jan Bruns: Re: Spartan3 SRL16 + SliceFF, LUT stability
                136511: 08/11/19: Jan Bruns: Re: Spartan3 SRL16 + SliceFF, LUT stability
                    136524: 08/11/20: Jan Bruns: Re: Spartan3 SRL16 + SliceFF, LUT stability
                    136526: 08/11/20: Jan Bruns: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136500: 08/11/19: Gabor: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136501: 08/11/19: Gabor: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136507: 08/11/19: Gabor: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136510: 08/11/19: Gabor: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136514: 08/11/19: John_H: Re: Spartan3 SRL16 + SliceFF, LUT stability
        136515: 08/11/19: Jan Bruns: Re: Spartan3 SRL16 + SliceFF, LUT stability
            136517: 08/11/19: Jan Bruns: Re: Spartan3 SRL16 + SliceFF, LUT stability
                136530: 08/11/20: Jan Bruns: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136518: 08/11/19: Gabor: Re: Spartan3 SRL16 + SliceFF, LUT stability
    136529: 08/11/20: John_H: Re: Spartan3 SRL16 + SliceFF, LUT stability
136499: 08/11/19: fl: Is Atlantic Interface replaced by Avalon Streaming Interface?
136520: 08/11/19: deep: ip core connection
    136624: 08/11/27: Paul Boven: Re: ip core connection
136521: 08/11/20: Guy_FPGA: Altera DE3 - USB Bulk Transfer
    136533: 08/11/21: Mark McDougall: Re: Altera DE3 - USB Bulk Transfer
        136584: 08/11/24: Mark McDougall: Re: Altera DE3 - USB Bulk Transfer
            136585: 08/11/24: Mark McDougall: Re: Altera DE3 - USB Bulk Transfer
    136576: 08/11/22: Guy_FPGA: Re: Altera DE3 - USB Bulk Transfer
136523: 08/11/20: <bamboutcha9999@hotmail.com>: How could i play my SVF file correctly ?
136525: 08/11/20: Nial Stewart: Announce: HSMC General Purpose Interface Board for Altera Dev kits
    136539: 08/11/21: <nial@nialstewartdevelopments.co.uk>: Re: Announce: HSMC General Purpose Interface Board for Altera Dev
136534: 08/11/20: 500milesaway: how to display on LCD of FPGA board?
    136537: 08/11/21: Bryan: Re: how to display on LCD of FPGA board?
136535: 08/11/20: mentari: Picochip Wimax designs available to public?
136536: 08/11/21: Andreas Ehliar: Re: Student FPGAs
136538: 08/11/21: Philipp: Student FPGAs
    136542: 08/11/21: Mike Treseler: Re: Student FPGAs
    136544: 08/11/21: Rob Gaddi: Re: Student FPGAs
    136545: 08/11/21: John_H: Re: Student FPGAs
    136547: 08/11/21: beky4kr@gmail.com: Re: Student FPGAs
    136561: 08/11/22: John Adair: Re: Student FPGAs
    136565: 08/11/22: Lorenz Kolb: Re: Student FPGAs
136540: 08/11/21: rush2sami: Altera FPGA development board for high speed Video processing
    136847: 08/12/08: cwoodring: Re: Altera FPGA development board for high speed Video processing
136541: 08/11/21: Eric: Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell
    136543: 08/11/21: HT-Lab: Re: Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell
    136546: 08/11/21: John_H: Re: Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell
    136548: 08/11/21: Gabor: Re: Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell
    136550: 08/11/21: Eric Smith: Re: Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell
136549: 08/11/21: FP: Quartus error
136551: 08/11/21: Kappa: Generate sample rate ...
    136553: 08/11/21: Hal Murray: Re: Generate sample rate ...
        136555: 08/11/21: Kappa: Re: Generate sample rate ...
            136562: 08/11/22: Hal Murray: Re: Generate sample rate ...
    136554: 08/11/21: Jonathan Bromley: Re: Generate sample rate ...
        136557: 08/11/21: Kappa: Re: Generate sample rate ...
            136560: 08/11/22: Kappa: Re: Generate sample rate ...
                136563: 08/11/22: Hal Murray: Re: Generate sample rate ...
                    136569: 08/11/22: kadhiem_ayob: Re: Generate sample rate ...
                        136571: 08/11/22: Richard Head: Re: Generate sample rate ...
                            136572: 08/11/22: kadhiem_ayob: Re: Generate sample rate ...
                                136574: 08/11/22: Kappa: Re: Generate sample rate ...
                                    136577: 08/11/22: kadhiem_ayob: Re: Generate sample rate ...
                                        136578: 08/11/22: kadhiem_ayob: Re: Generate sample rate ...
                                            136579: 08/11/22: kadhiem_ayob: Re: Generate sample rate ...
                                        136580: 08/11/23: Kappa: Re: Generate sample rate ...
                                            136581: 08/11/23: kadhiem_ayob: Re: Generate sample rate ...
                        136573: 08/11/22: Kappa: Re: Generate sample rate ...
                            136575: 08/11/22: kadhiem_ayob: Re: Generate sample rate ...
    136556: 08/11/21: Gabor: Re: Generate sample rate ...
    136559: 08/11/21: Kolja Sulimma: Re: Generate sample rate ...
    136564: 08/11/22: <secureasm@gmail.com>: Re: Generate sample rate ...
    136590: 08/11/24: Kolja Sulimma: Re: Generate sample rate ...
136552: 08/11/21: HSeldon: Accessing bottom MGT of Virtex II Pro FPGA
136558: 08/11/21: John_H: Small adders in XST?
    136566: 08/11/22: Jonathan Bromley: Re: Small adders in XST?
        136567: 08/11/22: Jonathan Bromley: Re: Small adders in XST?
            136586: 08/11/24: Jan Bruns: Re: Small adders in XST?
    136568: 08/11/22: Jan Bruns: Re: Small adders in XST?
        136570: 08/11/22: Jan Bruns: Re: Small adders in XST?
136582: 08/11/23: wallra: hi need help in VHDL code For Input sequence Design
    136583: 08/11/23: KJ: Re: hi need help in VHDL code For Input sequence Design
    136589: 08/11/24: Allan Herriman: Re: hi need help in VHDL code For Input sequence Design
136587: 08/11/23: raj: distributed dual port RAM with asynchronous read in ACTEL Smartgen
    136604: 08/11/24: Thomas Stanka: Re: distributed dual port RAM with asynchronous read in ACTEL
    136609: 08/11/25: Mike Treseler: Re: distributed dual port RAM with asynchronous read in ACTEL Smartgen
        136610: 08/11/25: HT-Lab: Re: distributed dual port RAM with asynchronous read in ACTEL Smartgen
136591: 08/11/24: palvarez: FMC/VITA 57
    136593: 08/11/24: John Doe: Re: FMC/VITA 57
        136596: 08/11/24: John Doe: Re: FMC/VITA 57
        136642: 08/11/27: Mike Monett: Re: FMC/VITA 57
    136594: 08/11/24: paas: Re: FMC/VITA 57
    136601: 08/11/24: palvarez: Re: FMC/VITA 57
    136607: 08/11/25: Gabor: Re: FMC/VITA 57
    136622: 08/11/26: <nicmo92@yahoo.com>: Re: FMC/VITA 57
    136648: 08/11/27: colin: Re: FMC/VITA 57
        136657: 08/11/28: Mike Monett: Re: FMC/VITA 57
    136655: 08/11/28: palvarez: Re: FMC/VITA 57
    136677: 08/11/30: palvarez: Re: FMC/VITA 57
136592: 08/11/24: osquillar: opencores can core
    136634: 08/11/27: Jeremy Bennett: Re: opencores can core
136595: 08/11/25: Michael Brown: Re: Student FPGAs
136597: 08/11/24: Pinhas: Extracting data from a VCD waveform format.
    136599: 08/11/24: Gabor: Re: Extracting data from a VCD waveform format.
136598: 08/11/24: none: IDELAYCTRL for Xilinx virtex 5
    136600: 08/11/24: Gabor: Re: IDELAYCTRL for Xilinx virtex 5
    136617: 08/11/26: Sean Durkin: Re: IDELAYCTRL for Xilinx virtex 5
136603: 08/11/24: bish: timer interrupt problem: microblaze
    136605: 08/11/25: Matthias Alles: Re: timer interrupt problem: microblaze
    136608: 08/11/25: bish: Re: timer interrupt problem: microblaze
    136611: 08/11/25: Bryan: Re: timer interrupt problem: microblaze
    136613: 08/11/25: David: Re: timer interrupt problem: microblaze
    136615: 08/11/25: bish: Re: timer interrupt problem: microblaze
    136616: 08/11/25: bish: Re: timer interrupt problem: microblaze
    136625: 08/11/26: Bryan: Re: timer interrupt problem: microblaze
    136640: 08/11/27: bish: Re: timer interrupt problem: microblaze
    136641: 08/11/27: bish: Re: timer interrupt problem: microblaze
    136650: 08/11/28: Goran_Bilski: Re: timer interrupt problem: microblaze
    136651: 08/11/28: bish: Re: timer interrupt problem: microblaze
    136872: 08/12/10: SUMAN: Re: timer interrupt problem: microblaze
136606: 08/11/25: John Adair: Re: Student FPGAs
136612: 08/11/25: <reganireland@gmail.com>: Deserializing Camerlink on Spartan XC3s400
    136614: 08/11/26: backhus: Re: Deserializing Camerlink on Spartan XC3s400
    136618: 08/11/26: Gabor: Re: Deserializing Camerlink on Spartan XC3s400
    136623: 08/11/26: <reganireland@gmail.com>: Re: Deserializing Camerlink on Spartan XC3s400
    136683: 08/11/30: <reganireland@gmail.com>: Re: Deserializing Camerlink on Spartan XC3s400
136620: 08/11/26: palvarez: added jitter on FPGAs
    136621: 08/11/26: Jan Bruns: Re: added jitter on FPGAs
    136635: 08/11/27: Kolja Sulimma: Re: added jitter on FPGAs
        136639: 08/11/27: Symon: Re: added jitter on FPGAs
    136654: 08/11/28: palvarez: Re: added jitter on FPGAs
    139333: 09/03/26: John Larkin: Re: added jitter on FPGAs
        139335: 09/03/26: Andrew Holme: Re: added jitter on FPGAs
            139336: 09/03/26: John Larkin: Re: added jitter on FPGAs
                139410: 09/03/28: Joerg: Re: added jitter on FPGAs
                    139414: 09/03/28: John Larkin: Re: added jitter on FPGAs
                        139417: 09/03/28: John Larkin: Re: added jitter on FPGAs
                        139420: 09/03/28: Joerg: Re: added jitter on FPGAs
                            139423: 09/03/29: glen herrmannsfeldt: Re: added jitter on FPGAs
                                139428: 09/03/29: Joerg: Re: added jitter on FPGAs
                            139427: 09/03/29: Jan Panteltje: Re: added jitter on FPGAs
                                139429: 09/03/29: Joerg: Re: added jitter on FPGAs
                                    139430: 09/03/29: krw: Re: added jitter on FPGAs
                                        139433: 09/03/29: Joerg: Re: added jitter on FPGAs
                                            139440: 09/03/29: krw: Re: added jitter on FPGAs
                                                139441: 09/03/29: John Larkin: Re: added jitter on FPGAs
                                                    139447: 09/03/30: John Larkin: Re: added jitter on FPGAs
                                                    139460: 09/03/30: krw: Re: added jitter on FPGAs
                    139452: 09/03/30: rickman: Re: added jitter on FPGAs
                139416: 09/03/28: krw: Re: added jitter on FPGAs
            139418: 09/03/28: John Larkin: Re: added jitter on FPGAs
                139422: 09/03/29: Symon: Re: added jitter on FPGAs
                    139434: 09/03/29: John Larkin: Re: added jitter on FPGAs
                        139445: 09/03/30: Symon: Re: added jitter on FPGAs
                139455: 09/03/30: Joel Koltner: Re: added jitter on FPGAs
                    139456: 09/03/30: John Larkin: Re: added jitter on FPGAs
        139338: 09/03/26: Nico Coesel: Re: added jitter on FPGAs
            139339: 09/03/26: John Larkin: Re: added jitter on FPGAs
        139444: 09/03/30: Allan Herriman: Re: added jitter on FPGAs
    139415: 09/03/28: rickman: Re: added jitter on FPGAs
    139424: 09/03/29: Allan Herriman: Re: added jitter on FPGAs
136626: 08/11/26: <Sudhir.Singh@email.com>: Infer Dual Port Block ROM for Xilinx FPGA
    136628: 08/11/26: Mike Treseler: Re: Infer Dual Port Block ROM for Xilinx FPGA
    136630: 08/11/26: Pinhas: Re: Infer Dual Port Block ROM for Xilinx FPGA
    136633: 08/11/27: Uwe Bonnes: Re: Infer Dual Port Block ROM for Xilinx FPGA
    136646: 08/11/27: <Sudhir.Singh@email.com>: Re: Infer Dual Port Block ROM for Xilinx FPGA
    136649: 08/11/28: Alain: Re: Infer Dual Port Block ROM for Xilinx FPGA
136627: 08/11/27: Andreas Ehliar: Re: Problem with post-route simulation / timing simulation
    136684: 08/11/30: ikki: Re: Problem with post-route simulation / timing simulation
136629: 08/11/27: ikki: Problem with post-route simulation / timing simulation
    136631: 08/11/26: Mike Treseler: Re: Problem with post-route simulation / timing simulation
        136685: 08/11/30: ikki: Re: Problem with post-route simulation / timing simulation
136632: 08/11/27: Andreas Ehliar: Re: Caches & FPGAs
136636: 08/11/27: Robert: Caches & FPGAs
    136638: 08/11/27: Jon Beniston: Re: Caches & FPGAs
136637: 08/11/27: oopere: Altera ethernetblaster problem
136643: 08/11/27: <jinyinglu@gmail.com>: help! how to pipeline a non-restoring divider in verilog
    136644: 08/11/27: Muzaffer Kal: Re: help! how to pipeline a non-restoring divider in verilog
    136645: 08/11/27: <jinyinglu@gmail.com>: Re: help! how to pipeline a non-restoring divider in verilog
136647: 08/11/28: Martin Sauer: Dithering video signals
    136652: 08/11/28: Pete Fraser: Re: Dithering video signals
        136662: 08/11/29: Martin Sauer: Re: Dithering video signals
            136664: 08/11/29: Pete Fraser: Re: Dithering video signals
136653: 08/11/28: Tricky: EPLD - FPGA - Is there a difference
    136658: 08/11/29: Jim Granville: Re: EPLD - FPGA - Is there a difference
    136660: 08/11/28: Gabor: Re: EPLD - FPGA - Is there a difference
    136661: 08/11/28: Alan: Re: EPLD - FPGA - Is there a difference
136656: 08/11/28: Ed Prochak: Re: Gizmo invent Gizmo. The State of the Art in 1999, today and the
    136659: 08/11/28: Mel: Re: Gizmo invent Gizmo. The State of the Art in 1999, today and the future. submitted by Mr Ian Martin Ajzenszmidt
136663: 08/11/29: berte: How to write driver for xilinx spartan iie xc2s50e
    136665: 08/11/29: Mike Treseler: Re: How to write driver for xilinx spartan iie xc2s50e
    136688: 08/11/30: berte: Re: How to write driver for xilinx spartan iie xc2s50e
136666: 08/11/29: cid: How to evaluate program efficiency/functionality
    136668: 08/11/30: Allan Herriman: Re: How to evaluate program efficiency/functionality
        136675: 08/11/30: Mike Treseler: Re: How to evaluate program efficiency/functionality
        136676: 08/11/30: Hal Murray: Re: How to evaluate program efficiency/functionality
    136672: 08/11/30: cid: Re: How to evaluate program efficiency/functionality
136667: 08/11/30: H. Peter Anvin: Terasic DE1 board commentary
    136694: 08/12/01: Tommy Thorn: Re: Terasic DE1 board commentary
    136959: 08/12/15: radarman: Re: Terasic DE1 board commentary
        137152: 08/12/28: H. Peter Anvin: Re: Terasic DE1 board commentary
            137154: 08/12/28: H. Peter Anvin: Re: Terasic DE1 board commentary
        137153: 08/12/28: rickman: Re: Terasic DE1 board commentary
        137163: 08/12/29: rickman: Re: Terasic DE1 board commentary
136669: 08/11/30: Karl: make phone calls from fpga. is it possible?
    136670: 08/11/30: Leon: Re: make phone calls from fpga. is it possible?
    136671: 08/11/30: tim.....: Re: make phone calls from fpga. is it possible?
        136680: 08/11/30: H. Peter Anvin: Re: make phone calls from fpga. is it possible?
    136678: 08/11/30: Karl: Re: make phone calls from fpga. is it possible?
    136679: 08/11/30: Karl: Re: make phone calls from fpga. is it possible?
136673: 08/11/30: SUMAN: DDR2 SDRAM RELEATED PROBLEM IN SPARTAN 3A DSP 1800 + EDK 9.2i
    136681: 08/11/30: bish: Re: DDR2 SDRAM RELEATED PROBLEM IN SPARTAN 3A DSP 1800 + EDK 9.2i
    136692: 08/12/01: Bryan: Re: DDR2 SDRAM RELEATED PROBLEM IN SPARTAN 3A DSP 1800 + EDK 9.2i
    136693: 08/12/01: SUMAN: Re: DDR2 SDRAM RELEATED PROBLEM IN SPARTAN 3A DSP 1800 + EDK 9.2i
    136734: 08/12/03: SUMAN: Re: DDR2 SDRAM RELEATED PROBLEM IN SPARTAN 3A DSP 1800 + EDK 9.2i
136674: 08/11/30: FP: Jitter Management
136682: 08/11/30: J.Ram: simulation results is correct but synthesis result is not correct
    136689: 08/11/30: Thomas Stanka: Re: simulation results is correct but synthesis result is not correct
        136700: 08/12/02: Per: Re: simulation results is correct but synthesis result is not correct
    136690: 08/12/01: KJ: Re: simulation results is correct but synthesis result is not correct
    136695: 08/12/01: Nicolas Matringe: Re: simulation results is correct but synthesis result is not correct
    136701: 08/12/02: J.Ram: Re: simulation results is correct but synthesis result is not correct
    136703: 08/12/02: KJ: Re: simulation results is correct but synthesis result is not correct
    136723: 08/12/03: bish: Re: simulation results is correct but synthesis result is not correct


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015Jan2015

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search