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Authors (Z)

z:
    49149: 02/11/02: Re: Concepts: What is "Clock Edge"?
z master:
    152530: 11/09/06: Xilinx ISE Design - XPS won't start
z.karim:
    38388: 02/01/13: Re: FPGA configuration
    38502: 02/01/16: Re: FPGA : VHDL netlist for simulation
    38503: 02/01/16: Re: remainder
    38504: 02/01/16: Re: Synthesis in FPGA Express
    38505: 02/01/16: Re: Synthesis: Protel 99SE to XC2S200
    39307: 02/02/06: Re: Making Altera development quicker
    39445: 02/02/10: Re: Xlx simprim library
    39697: 02/02/16: Re: Xilinx Virtex XCV300
    39698: 02/02/16: Re: Xilinx Virtex XCV300
    39711: 02/02/17: Re: Handel-C, System-C, Formal verification ???
    40090: 02/02/27: Re: EEPROM simulation
    57898: 03/07/09: Re: std_logic_vector type port doesn't work after synthesis.
<z0rbaf@newsguy.com>:
    17508: 99/08/03: looking for software
    17598: 99/08/12: looking for info on programing XILINX 4000 series
<z80@digserv.com>:
    5006: 97/01/11: Re: DES Keysearch by FPGA: $10,000 prize
Zach Pfeffer:
    70962: 04/07/02: Re: Problems with a Virtex-II Engineering Sample
    71405: 04/07/17: Re: Problems with a Virtex-II Engineering Sample
Zach Stechly:
    152340: 11/08/10: Xilinx Coregen, command not found java error
    152364: 11/08/11: Re: Xilinx Coregen, command not found java error
Zack Hugh:
    41406: 02/03/27: Core Generator and Modelsim XE
    42453: 02/04/24: 256-point FFT with Xilinx 4.1 Core Generator
zaf:
    61482: 03/10/05: How To: 3-input NAND gate using ACTEL ACT 1 logic module
Zahid Hussain:
    10522: 98/05/27: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
Zahir Parpia:
    13041: 98/11/12: ZEN News, Nov. 10, 1998
<zahra.lak@gmail.com>:
    117450: 07/03/31: Static RAM implementation with VHDL
    117451: 07/03/31: Static RAM implementation with VHDL
zak:
    153225: 12/01/12: balancing IIR filter (after adding extra registers)
    153232: 12/01/14: Re: balancing IIR filter (after adding extra registers)
    153236: 12/01/15: Re: balancing IIR filter (after adding extra registers)
    153247: 12/01/16: Re: balancing IIR filter (after adding extra registers)
ZAK:
    79529: 05/02/20: Re: BACK to FPGA
Zak:
    62170: 03/10/21: bitstream compatibility
    62251: 03/10/23: Anyone with old Foundation?
    70546: 04/06/20: Re: compressing Xilinx bitstreams
Zak smith:
    40477: 02/03/07: Clamping Diode in the I/O !!!
    40699: 02/03/13: Pointer Processor for OC192
    40700: 02/03/13: Any data about SFI 4 interface ?
zakarialaskar:
    153885: 12/06/21: RE: ADC problem on spartan3E
Zakharko Y.:
    29397: 01/02/19: problem with pogrammer for serial EPROM
zalc:
    1564: 95/07/17: RFI: wavelet
    1581: 95/07/21: PREP data
Zalman Stern:
    12888: 98/11/03: Re: New free FPGA CPU
    17274: 99/07/15: Re: Alto in an FPGA (was CPU's directly executing HLL's)
zalzon:
    80944: 05/03/14: Question from Newbie about FPGAs
    82733: 05/04/17: FPGA/Embedded courses online or near Toronto
zanaticul:
    145174: 10/01/30: vhdl divider
Zara:
    88900: 05/08/31: Re: chipscope problems
    89111: 05/09/06: Re: Strange warning "WARNING:MapLib:701 - Signal P_GPIO_3 connected
    89237: 05/09/08: Microblaze and LMB
    89253: 05/09/09: Re: Microblaze and LMB
    89332: 05/09/13: Re: Which JTAG cable for Xilinx & Linux?
    89333: 05/09/13: Re: FFT implementation in Xilinx's Spartan 3
    89436: 05/09/15: Re: Microblaze & Memory DMA operation
    89487: 05/09/16: Re: DCM question
    89492: 05/09/16: Re: problem with programming avnet edk board over LPT
    89495: 05/09/16: Re: problem with programming avnet edk board over LPT
    89543: 05/09/18: Re: Microblaze & Memory DMA operation
    89595: 05/09/20: Re: SoC embedded FPGA
    89904: 05/09/30: Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if
    89938: 05/09/30: Re: Testbench using Modelsim/VHDL - simple signal generation problem
    89946: 05/09/30: Re: Testbench using Modelsim/VHDL - simple signal generation problem
    90026: 05/10/03: Re: More than one embedded system in ISE
    90027: 05/10/03: Re: ISE does not initialize the bitstream of a EDK project
    90116: 05/10/05: Re: I'm desperate... EDK project simulation
    90165: 05/10/06: Re: I'm desperate... EDK project simulation
    90229: 05/10/07: Re: I'm desperate... EDK project simulation
    90231: 05/10/07: Re: More than one embedded system in ISE
    90240: 05/10/07: Re: FPGA behaviour when its used resource is >90% ?
    90697: 05/10/19: Re: How to speed up the critical path (Xilinx)
    90914: 05/10/25: Re: OSD implementation in FPGA
    90917: 05/10/25: Re: OSD implementation in FPGA
    91134: 05/10/31: Re: Xilinx Microblaze prefill icache
    91233: 05/11/02: Re: Spartan IIE VHDL inout port bidirectional bus problem.
    91244: 05/11/02: Re: differential clock in EDK
    91518: 05/11/08: Re: Delay insertion in Xilinx Verilog
    91519: 05/11/08: Re: Easy Xilinx Platform Studio Question
    91964: 05/11/18: Re: Parallel Cable IV not detecting
    93048: 05/12/13: Re: Xilinx FPGA - Wrongly Translated Inputs
    93063: 05/12/13: Re: Xilinx FPGA - Wrongly Translated Inputs
    94391: 06/01/11: Re: Will ISE 8.1 work together with EDK 7.1?
    94395: 06/01/11: Re: Will ISE 8.1 work together with EDK 7.1?
    94471: 06/01/12: Re: Will ISE 8.1 work together with EDK 7.1?
    94730: 06/01/17: Re: PCI arbiter doubt
    94815: 06/01/18: Re: [RANT] Webpack 8.1 editor totally messed up ?
    94825: 06/01/18: Re: [RANT] Webpack 8.1 editor totally messed up ?
    94833: 06/01/18: Re: [RANT] Webpack 8.1 editor totally messed up ?
    94826: 06/01/18: Re: [RANT] Webpack 8.1 editor totally messed up ?
    94830: 06/01/18: Re: [RANT] Webpack 8.1 editor totally messed up ?
    95170: 06/01/21: Re: EDK 8.1, Finally!
    95189: 06/01/21: Re: EDK 8.1, Finally!
    95191: 06/01/21: Re: EDK 8.1, Finally!
    95185: 06/01/21: Re: EDK 8.1, Finally!
    95647: 06/01/25: Re: custom ip using EDK
    96700: 06/02/09: Re: Software reset for the MicroBlaze
    96770: 06/02/10: Re: EDK - PLB/OPB Bus questions.
    98282: 06/03/08: Re: DCM question
    99692: 06/03/28: Re: OPB monitor error
    100277: 06/04/06: Re: done pin didn't go high
    100361: 06/04/07: Re: OPB master
    101017: 06/04/24: Re: ISE 8.1 Sub module Synthesis
    101059: 06/04/25: Re: ISE 8.1 Sub module Synthesis
    101060: 06/04/25: Re: How to avoid this waring in ISE 8.1?
    101818: 06/05/07: Re: flashing a led
    102142: 06/05/11: Re: Xilinx ISE 8.1 Makefile
    103208: 06/05/29: Re: Peripheral connected to multiple OPB buses
    103265: 06/05/30: Re: Peripheral connected to multiple OPB buses
    103324: 06/05/31: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
    103346: 06/05/31: Re: combining state machines.
    103507: 06/06/05: Re: Driving two DCMs with BUFG?
    103528: 06/06/05: Re: MIL Qualified RTOS for PowerPc 405
    103631: 06/06/07: Re: Problems with ISE logic optimization
    103633: 06/06/07: Re: Problems with ISE logic optimization
    103682: 06/06/08: Re: Can ILMB and DLMB of Microblaze be 24kByte?
    103683: 06/06/08: Re: Block Ram vs Distributed Ram
    104148: 06/06/20: Microblaze, -mxl-gp-opt and small data areas
    104190: 06/06/21: Re: comp.arch.fpga : Selection of Device
    104196: 06/06/21: Re: comp.arch.fpga : Selection of Device
    104359: 06/06/26: Re: multisource on signal in XPS
    104362: 06/06/26: Re: multisource on signal in XPS
    104740: 06/07/05: Re: Can I use all 18bits of a BlockRAM?
    104923: 06/07/10: Re: Xilinx Xcell Journal received damaged
    104935: 06/07/10: Re: Xilinx Xcell Journal received damaged
    105945: 06/08/03: Re: EDK, user IP, how to use user-functions
    105978: 06/08/04: Re: coming soon: MB 5.0
    108910: 06/09/19: Re: uBlaze : -m compile directives...
    109259: 06/09/22: Re: uBlaze : Programming in C++... Is Possible ?
    109348: 06/09/25: Re: uBlaze : Programming in C++... Is Possible ?
    109566: 06/09/29: Help with xilinx OPB Arbiter
    109573: 06/09/29: Re: Interfacing second bram port to user logic?
    109709: 06/10/04: Re: Xilinx PowerPC & MicroBlaze Development Kit
    109715: 06/10/04: Re: Xilinx PowerPC & MicroBlaze Development Kit
    110103: 06/10/11: Re: Xilinx MicroBlaze 4.00.a source codes released by Xilinx !?
    110277: 06/10/13: Re: Last ISE version that supports XC95xxXL ?
    110644: 06/10/19: Problema when upgrading from Xilinx 8.1 to Xilinx 8.2
    110648: 06/10/19: Re: Problema when upgrading from Xilinx 8.1 to Xilinx 8.2
    110649: 06/10/19: Re: Problema when upgrading from Xilinx 8.1 to Xilinx 8.2
    110712: 06/10/20: Re: Problema when upgrading from Xilinx 8.1 to Xilinx 8.2
    110717: 06/10/20: Re: Reversing SPI shift out order on Microblaze design
    110817: 06/10/24: Re: Microblaze : FSL bus
    110972: 06/10/26: Re: Problema when upgrading from Xilinx 8.1 to Xilinx 8.2
    111014: 06/10/27: Re: Problema when upgrading from Xilinx 8.1 to Xilinx 8.2
    111019: 06/10/27: Re: Problema when upgrading from Xilinx 8.1 to Xilinx 8.2
    111127: 06/10/30: Re: Problema when upgrading from Xilinx 8.1 to Xilinx 8.2
    111555: 06/11/06: Re: FSL microblaze to co-processor write problem...
    111682: 06/11/08: Re: Problema when upgrading from Xilinx 8.1 to Xilinx 8.2
    112500: 06/11/23: Re: Problems connecting MicroBlaze to custom IP
    113303: 06/12/11: Re: How to develop custom opb devices for Microblaze?
    113855: 06/12/26: Re: OPB master implementation
    113875: 06/12/27: Re: OPB master implementation
    113908: 06/12/29: Re: moving from xlinx 8.1 to 8.2 or better wait ?
    114348: 07/01/12: XMD with Microblaze and EDK 8.2
    114401: 07/01/15: Re: SDK 8.2 error 127
    114518: 07/01/18: Re: Xilinx website login problems
    115245: 07/02/05: Re: UNKNOWN Processor Version (0) in XMD
    115576: 07/02/14: Re: IP to OPB FIFO
    115768: 07/02/20: Re: Managing input clock of 20MHz at input of DCM
    116025: 07/02/28: Re: Spartan MicroBlaze
    116137: 07/03/02: Re: How to connect an IP to OPB bus??
    116320: 07/03/07: Re: No Clock in ChipScope Pro Analyzer
    117119: 07/03/23: Re: EDK and Custom Peripheral: error occur when generating bitstream
    117309: 07/03/28: Re: Help with Xilinx Parallel Cable IV.
    118897: 07/05/07: Re: My Dear Spartan-3A, Please Please WAKE UP!
    118901: 07/05/07: Re: My Dear Spartan-3A, Please Please WAKE UP!
    118951: 07/05/08: Re: My Dear Spartan-3A, Please Please WAKE UP!
    118968: 07/05/08: Re: An Open-Source suggestion for Xilinx
    118969: 07/05/08: Re: My Dear Spartan-3A, Please Please WAKE UP!
    119165: 07/05/14: Re: Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;)
    119170: 07/05/14: Re: Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;)
    119273: 07/05/16: Re: Xilinx EDK: Slow OPB write speeds
    119345: 07/05/17: Re: Mutiple MAC on OPB Bus
    119525: 07/05/22: Re: DDR Controller Blue
    120378: 07/06/06: Re: Install two version of EDK/ISE (8.1, 8.2) in my windows xp?
    120905: 07/06/20: Re: Weird behavior in debuggin using XMD
    121365: 07/07/03: Re: Microblaze and software interrupts?
    121719: 07/07/12: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
    122915: 07/08/10: Re: Amount of wire and logic
    122965: 07/08/13: Re: ucf editor edk
    123803: 07/09/05: Re: Multiple CPLDs on a PCB.
    124025: 07/09/11: Re: Uses of Gray code in digital design
    128534: 08/01/30: Re: Can I connect PLB and OPB to mlcroblase v7 (use EDK 9.2 and Virtex 5) ?
    130259: 08/03/19: Re: problem with edk9.2
    130260: 08/03/19: Re: ISE 9.2SP4 error
    130711: 08/03/31: Re: ISE 10.1 - Initial experience
    130807: 08/04/02: Re: "Number of BSCANs: 2 out of 1 200%"
<zazpximytig@gmail.com>:
    138392: 09/02/19: Re: Any Experiences with the GN4124 PCI Express - FPGA bridge?
<zckhfx@nowhere.com>:
zcsizmadia@gmail.com:
    91214: 05/11/01: Re: can ethereal detect an ethernet packet for which crc is wrong
    105052: 06/07/12: Re: how to implement multi-port memory
    106989: 06/08/23: Re: Open source Xilinx JTAG Programmer released on sourceforge.net
    106999: 06/08/23: Re: virtex4fx board and ethernet
    107044: 06/08/23: Re: Open source Xilinx JTAG Programmer released on sourceforge.net
    107133: 06/08/24: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
    107136: 06/08/24: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
    107155: 06/08/24: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
    107157: 06/08/24: Re: Open source Xilinx JTAG Programmer released on sourceforge.net
    107194: 06/08/25: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
    107210: 06/08/25: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
    107226: 06/08/25: Re: F&*% School
    107227: 06/08/25: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
    107228: 06/08/25: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
    107296: 06/08/26: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
    107727: 06/08/31: Open-source CableServer for Impact (no more need for Jungo driver on Linux)
    107732: 06/08/31: Re: Open-source CableServer for Impact (no more need for Jungo driver on Linux)
    108147: 06/09/05: Open-source CableServer for Impact on sourceforge.net
    108167: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
    108168: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
    108169: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
    108183: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
    108190: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
    108200: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
    108202: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
    108207: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
    108209: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
    108233: 06/09/06: Zigbee mesh sensor network
    108273: 06/09/07: Re: Open-source CableServer for Impact on sourceforge.net
    108743: 06/09/15: Re: USB programming cables
    109341: 06/09/24: Re: MicroFpga = program an FPGA as it would be a MCU !
    109876: 06/10/06: Re: Open protocol USB JTAG cable
    109877: 06/10/06: Re: Open protocol USB JTAG cable
    111082: 06/10/28: Virtex-4 & Wifi
    117091: 07/03/22: Re: Programming XCF from MicroBlaze over JTAG???
    117141: 07/03/23: Re: Programming XCF from MicroBlaze over JTAG???
    117143: 07/03/23: Re: Programming XCF from MicroBlaze over JTAG???
    117326: 07/03/28: Re: Problems with Xilinx Parallel III Cable
    117370: 07/03/29: Re: Regarding connecting two Ethernet Mac Phy
    117530: 07/04/03: Re: Implementing a communication protocol for data transfer over TCP on an FPGA
    117805: 07/04/10: =?iso-8859-1?q?Re:_CPLD_+_=B5C_with_reasonably-priced_tools=3F?=
    117811: 07/04/10: =?iso-8859-1?q?Re:_CPLD_+_=B5C_with_reasonably-priced_tools=3F?=
    117841: 07/04/11: =?iso-8859-1?q?Re:_CPLD_+_=B5C_with_reasonably-priced_tools=3F?=
    118449: 07/04/26: Re: Sscanf replacement for xilinx EDK
    118926: 07/05/07: sysace and high capacity CF
<zcsizmadia@gmail.com>:
    88375: 05/08/16: Re: Antti's last comp.arch.fpga posting
Zdenka Safarzik:
    31423: 01/05/23: LCD/CRT video controller and whole MMI in FPGA
<zdenko.baksa@zg.tel.hr>:
    28066: 00/12/20: ttl in cpld
Zdravko:
    36703: 01/11/16: OrCAD footprints for CoolRunner
Zebht325:
zee:
    23258: 00/06/19: cpld
zeeman_be:
    84692: 05/05/24: Re: more and more and more issues with Xilinx tools
    85408: 05/06/09: Re: DDR desing with FPGA
    87238: 05/07/20: Re: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1
    87677: 05/07/28: Re: question for Xilinx ppl
    90124: 05/10/05: Re: Where to get informations about Virtex 4 FX Engineering Samples
    101871: 06/05/08: Strange power up issue on Virtex4
    101890: 06/05/08: Re: Strange power up issue on Virtex4
    101902: 06/05/08: Re: Strange power up issue on Virtex4
    101907: 06/05/08: Re: Strange power up issue on Virtex4
    101914: 06/05/08: Re: Strange power up issue on Virtex4
    102744: 06/05/19: Re: Error in XPS 7.1 mb_opb_wrapper
    109489: 06/09/27: MicroBlaze : Linkerscript for splitting the text block into 64kByte blocks
    124785: 07/10/04: Re: JPEG-LS hardware implementation
    141203: 09/06/11: Re: Safe margin in FPGA static timing analysis
Zeev Yelin:
    2004: 95/09/30: Re: Altera Sim. with Leapfrog
    2878: 96/02/22: Re: Xilinx FPGA's with Mentor Tools?
    6725: 97/06/19: Actel HDL cores - request for information
    9554: 98/03/23: AHDL to Verilog conversion (Q)
Zefram Cochrane:
    25264: 00/09/03: Re: Non-disclosures in job interviews, Round Two
Zeke:
    54977: 03/04/23: Re: Reason Xess discontinued XSV prototyping boards?
    54978: 03/04/23: Nice VHDL tutorial and POD/PCI Board
    55020: 03/04/24: Re: ANN : Online VHDL Memo
Zeki Basbuyuk:
    16160: 99/05/06: Re: How do I design this ?(synchronous interface)
<zelixor@gmail.com>:
    117631: 07/04/05: Re: Xilinx ISE webpack in Ubuntu?
    117824: 07/04/11: Re: Xilinx ISE webpack in Ubuntu?
Zeljko Blazek:
    9783: 98/04/05: Re: Rees-Solomon
    10130: 98/04/28: [Q] Cheap Xilinx Proto Boards
zengya:
    88032: 05/08/07: anybody knows where i can get the fibre channel ip core
zephyrer:
    94191: 06/01/06: How to keep the design from Synplify or XST optimizing
    94335: 06/01/09: Re: How to keep the design from Synplify or XST optimizing
zerang shah:
    53647: 03/03/18: fpga implementation problems
    75297: 04/11/01: "frying" FPGAs
    75412: 04/11/04: Re: "frying" FPGAs
Zerang Shah:
    79492: 05/02/19: Re: Make program stop
ZEYNEP14:
    27130: 00/11/12: Easy money for the Holidays!
zg:
    37560: 01/12/14: Testing used xilinx components
    72302: 04/08/13: NIOS II - Instantiating array on SDRAM
    73916: 04/09/30: Re: Altera SDRAM controller - Only 2 words burst???
    73601: 04/09/24: Altera SDRAM controller - Only 2 words burst???
    74125: 04/10/04: Re: Altera SDRAM controller - Only 2 words burst???
    74138: 04/10/04: Re: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
zgora:
    142552: 09/08/16: ANNC: Parallel flash programming using boundary-scan
Zhane:
    133473: 08/06/30: Translate problem
    133478: 08/06/30: Re: Translate problem
    133485: 08/07/01: Re: Translate problem
    133538: 08/07/02: Re: Translate problem
    133542: 08/07/03: Insert IP cores
    133546: 08/07/03: Re: Insert IP cores
    133557: 08/07/03: Re: Insert IP cores
    133566: 08/07/03: FiFo Help Needed
    133567: 08/07/03: Re: FiFo Help Needed
    133569: 08/07/03: Re: FiFo Help Needed
    133570: 08/07/03: Re: FiFo Help Needed
    133596: 08/07/05: Re: FiFo Help Needed
    133611: 08/07/06: Help to SImulate Uart TX
    133618: 08/07/06: Re: Help to SImulate Uart TX
    133619: 08/07/06: Re: Help to SImulate Uart TX
    133621: 08/07/06: Re: Help to SImulate Uart TX
    133641: 08/07/07: Re: FiFo Help Needed
    133651: 08/07/08: Spartan 3E I/O Pins -- LPC Bus Interface
    133661: 08/07/08: Help =(
    133662: 08/07/08: Help Needed - LPC Bus Interface
    133663: 08/07/08: Re: Spartan 3E I/O Pins -- LPC Bus Interface
    133731: 08/07/12: How to simulate baud rate generator?
    133739: 08/07/12: Re: How to simulate baud rate generator?
    133741: 08/07/12: Re: How to simulate baud rate generator?
    133800: 08/07/15: Fifo Simulation Error
    133807: 08/07/16: Re: Fifo Simulation Error
    133823: 08/07/16: Re: Fifo Simulation Error
    133824: 08/07/16: Re: Fifo Simulation Error
    133827: 08/07/16: Re: Fifo Simulation Error
    133866: 08/07/17: Re: Fifo Simulation Error
    134047: 08/07/23: Modelsim Simulate INOUT port
    134134: 08/07/27: vhdl code for debouncing push button
    134146: 08/07/28: Chipscope Error
    134148: 08/07/28: Re: Chipscope Error
    134157: 08/07/28: Re: Chipscope Error
    134173: 08/07/28: Re: Chipscope Error
    134420: 08/08/09: Block Rams
    134423: 08/08/09: Re: Block Rams
    134424: 08/08/09: Re: Block Rams
    134426: 08/08/09: Re: Block Rams
    134431: 08/08/10: Re: Block Rams
    134444: 08/08/11: Re: Block Rams
    134461: 08/08/11: Re: Block Rams
zhang:
    55126: 03/04/28: DDR SDRAM controlled by fpga?
zhangbert:
    149483: 10/10/29: Xilinx ISE ERRORS HDLCompilers:108
zhangdidi:
    70424: 04/06/16: example for excalibur epxa1
<zhanglingmu@gmail.com>:
    104464: 06/06/27: X-Ray Inspection System
zhanglixing7890:
    150149: 10/12/20: Help! Question about Debug!
<zhangpei@gmail.com>:
    79229: 05/02/15: How to display synplify_pro version in tcl command
    118049: 07/04/16: type/subtype definition in entity
    118115: 07/04/17: Re: type/subtype definition in entity
<zhangweidai@gmail.com>:
    96570: 06/02/06: Software Defined Radio Transmitter Demo Board
    96640: 06/02/07: Re: Software Defined Radio Transmitter Demo Board
    96641: 06/02/07: Re: Software Defined Radio Transmitter Demo Board
    96872: 06/02/12: spartan3 starter kit.
    96894: 06/02/13: Re: spartan3 starter kit.
    97726: 06/02/26: miniuart
    97737: 06/02/26: Re: miniuart
    97773: 06/02/27: Re: miniuart
    97791: 06/02/27: Re: miniuart
    97989: 06/03/02: Spartan 3 Expansion Board
    98000: 06/03/02: Re: Spartan 3 Expansion Board
    98079: 06/03/04: Re: Spartan 3 Expansion Board
    98132: 06/03/06: ISE freezing up with picoblaze code.
<zhangxun0501@gmail.com>:
    96976: 06/02/14: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98230: 06/03/07: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98298: 06/03/08: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
    98387: 06/03/09: slice macro replace the bus macro in the virtex-4 how to do that?????
    98400: 06/03/09: Re: slice macro replace the bus macro in the virtex-4 how to do that?????
    99937: 06/03/31: hwicap can be used in the virtex4
    99948: 06/03/31: Re: hwicap can be used in the virtex4
    99949: 06/03/31: Re: hwicap can be used in the virtex4
    100051: 06/04/02: Re: hwicap can be used in the virtex4
    100052: 06/04/02: Re: hwicap can be used in the virtex4
    100360: 06/04/07: one question for a error of map
    100389: 06/04/07: who know what is the problem
    103397: 06/06/01: is anyone knew the new version of HWICAP "opb_hwicap_v1_00_c" for
zhangy:
    9419: 98/03/12: SOS!! Big Urgent Problem
    9414: 98/03/12: Re: SOS!! Big Urgent Problem
    9415: 98/03/12: Byteblaster
    9967: 98/04/18: Re: Verilog to VHDL or VHDL to Verilog
    10194: 98/05/03: Make a delay in Altera
zhao:
    64101: 03/12/16: Altera Stratix 80: How to divide a bits stream to even bits stream
Zhao Zhang:
    4962: 97/01/04: Help on Fucntional Disk Systems document
zhaoke:
    58335: 03/07/21: synplify pro
Zhe Li:
    3195: 96/04/23: Application Question
Zhen:
    59058: 03/08/07: How to find the intersection of two vectors?
    59149: 03/08/10: a quick searching problem
Zhen Luo:
    14818: 99/02/18: edge-triggered registers on Xilinx 4000e.
    14899: 99/02/23: Your view on this article?
    15190: 99/03/12: Questions on Pamette.
    15304: 99/03/18: Xilinx routing problem: removing "reset" increases cycle time.
    15331: 99/03/18: Re: Xilinx routing problem: removing "reset" increases cycle time.
    27391: 00/11/20: What is the fundamental limitation factor for FPGA clock rate
    27461: 00/11/22: Re: Virtex-PCI-Boards
    27467: 00/11/22: Survey on design methodologies
    29019: 01/02/02: FPGA board with lots of SRAM?
    30736: 01/04/26: bidirectional I/O
"zheng Daixun":
    24651: 00/08/16: how to use script file in the Design Manager
Zheng Yang,13325,1100,g:
    682: 95/02/05: blif2vst
ZhengLin:
    37898: 01/12/23: Re: THE SIGNAL LIST IS NOT AVAILABLE TO SIMULATE
    37900: 01/12/23: Re: You take the low road and I'll ......
    37902: 01/12/23: Re: Does the core or Xilinx Core Generator support timing-simlulation?
    37903: 01/12/23: Re: no net attached to set reset cell
    37907: 01/12/23: Re: Does the core or Xilinx Core Generator support timing-simlulation?
    37930: 01/12/25: Re: Where could I get a signal waveform editor?
    39597: 02/02/14: Re: Foundation 4.1 vs. ISE 4.1?
    39599: 02/02/14: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
    39721: 02/02/16: Re: FPGA choices and questions
    39733: 02/02/18: Re: Do I need to install software in order to use Multilinx?
    45050: 02/07/10: Re: FPGA/CPLD Decision help?
Zhenglin:
    49359: 02/11/10: rs encode
zhengyu:
    48829: 02/10/25: C to verilog
    50038: 02/11/29: programmable FSM
    50090: 02/12/01: CAM tutorial
    50091: 02/12/01: string to int conversion
    52061: 03/01/30: one hot encoding
    53417: 03/03/13: write a single byte in to DRAM
    53809: 03/03/24: Re: synthesizability question
    58861: 03/08/03: two questions
ZHI:
    103950: 06/06/15: How process statement works in vhdl
    104177: 06/06/20: Re: How process statement works in vhdl
    104603: 06/06/30: How to control the uart
    104615: 06/07/01: Re: How to control the uart
    104627: 06/07/02: Re: How to control the uart
    104628: 06/07/02: How to trigger write signal and read sigal
    104868: 06/07/07: Warning issue!!!
    106055: 06/08/07: WHAT SITUATION I NEED A BUFFER
    106081: 06/08/07: Re: WHAT SITUATION I NEED A BUFFER
    106110: 06/08/07: Re: WHAT SITUATION I NEED A BUFFER
    106124: 06/08/08: Re: WHAT SITUATION I NEED A BUFFER
    106176: 06/08/08: Re: WHAT SITUATION I NEED A BUFFER
    106230: 06/08/09: Re: WHAT SITUATION I NEED A BUFFER
    106233: 06/08/09: Re: WHAT SITUATION I NEED A BUFFER
    111542: 06/11/05: How to transform matlab value to FPGA value
    111672: 06/11/07: H for FPGA
    112184: 06/11/17: How could the 'Serial write time out' happen
    112279: 06/11/19: Re: How could the 'Serial write time out' happen
    112309: 06/11/20: Re: How could the 'Serial write time out' happen
    113957: 06/12/30: How to deal with the negative value
    113958: 06/12/30: Re: How to deal with the negative value
    114636: 07/01/21: how to use register to save data
    114637: 07/01/21: Re: how to use register to save data
    114647: 07/01/22: Re: how to use register to save data
    115329: 07/02/07: test UART
    116944: 07/03/21: Data width in Block ram
    117007: 07/03/21: Re: Data width in Block ram
    117040: 07/03/22: Re: Data width in Block ram
    118622: 07/05/01: About ModelSim
    118636: 07/05/01: Re: About ModelSim
    118646: 07/05/01: Re: switched to xcf32p prom and now doesn't run
    121296: 07/06/30: Multiplier in Xilinx
    121319: 07/07/02: Re: Multiplier in Xilinx
    121358: 07/07/03: Re: Multiplier in Xilinx
    121436: 07/07/04: Re: Multiplier in Xilinx
    121535: 07/07/06: Re: Multiplier in Xilinx
    121586: 07/07/09: The delay time of coregen Multiplier in Modelsim
    122723: 07/08/04: Area report
    122900: 07/08/09: Re: Area report
    123826: 07/09/05: How to deal with the tempary coefficient in the FPGA design
    123859: 07/09/06: Re: How to deal with the tempary coefficient in the FPGA design
    125943: 07/11/09: What the 'c2p' and 'c2o' stand for?
Zhi:
    76250: 04/11/29: Re: RocketIO success?
    76272: 04/11/29: Re: Xilinx and Altera -- maximum total bitrate for high-speed serial I/O
Zhi Ye:
    7960: 97/11/03: interface between FPGA & user?
Zhibin Dai:
    17423: 99/07/26: XACT vs. Workview office
    21133: 00/03/07: Quick questions for Xilinx tools
    23978: 00/07/19: Fundation serial & Alliance serial
Zhiguo:
    138324: 09/02/16: Re: Announce: new TimingAnalyzer version beta 0.92
Zhijian Hu:
    44828: 02/07/02: Partners wanted for MP3 ASIC core
Zhiping:
    9714: 98/04/01: Re: Dual port
Zhiyuan Li:
    8986: 98/02/11: ask for applications
zhj1985:
    139254: 09/03/24: Can the complex DSP archetecture based on FPGA+DSP be replaced by FPGA
zhl_gs1980:
    90965: 05/10/26: cic filter
<zhongqiang.cheng@gmail.com>:
    113030: 06/12/05: How to check high impedance of a RAM with Logic Analyzer
    113079: 06/12/06: Re: How to check high impedance of a RAM with Logic Analyzer
    113657: 06/12/19: Operate on RAM through FPGA
    114270: 07/01/10: Operate Flash S29GL-N from Spansion
Zhou Chang:
    48945: 02/10/27: Re: High Performance FPGA's - Xilinx and ??????
    48990: 02/10/28: Re: High Performance FPGA's - Xilinx and ??????
Ziad Abu-Lebdeh:
    55225: 03/04/30: Re: WANTED ALTERA CYCLONE PCI BOARD
    55310: 03/05/03: Re: MJL Stratix Dev Kit
    55311: 03/05/03: Re: DDR SDRam Controller on ACEX1K
    55312: 03/05/03: Re: WANTED ALTERA CYCLONE PCI BOARD
ZIAD ABUOWAIMER:
    156267: 14/01/31: PathFinder Source Code (in C)
ziavras:
    76626: 04/12/07: Available POSTDOCTORAL position in Reconfigurable Computing
zibby sobota:
    6349: 97/05/17: xilinx xblox with capture ver 7.00
<zibixx76@yahoo.com>:
    118433: 07/04/26: differential pins assignment in Synplify fro altera device
ziggy:
    95106: 06/01/20: Re: need for a group FAQ?
    95746: 06/01/25: Re: Spartan-3 Starter Board
    98463: 06/03/10: Z80 Support Cores
    98536: 06/03/12: Re: LEON processor core
    98952: 06/03/18: Re: Where are FPGA heading?
    98953: 06/03/18: Re: Where are FPGA heading?
    98954: 06/03/18: Re: PacoBlaze update
    99037: 06/03/19: Re: Historical Fpga Resources
    99044: 06/03/19: Spartan-3E Sample Pack
    99045: 06/03/19: Re: microprocessor design: where to go from here?
    99066: 06/03/20: Re: Spartan-3E Sample Pack
    99149: 06/03/20: Re: Spartan-3E Sample Pack
    99157: 06/03/21: Re: PacoBlaze with multiply and 16-bit add/sub instructions
    100509: 06/04/10: Re: FPGA FAQ and the spam problem
    101051: 06/04/25: Opinions on Viva
    101052: 06/04/25: Re: vhdl cpu emulator (any interest?)
    102781: 06/05/20: Re: Why do the electronics manufacturers have to spam me?
    108746: 06/09/15: http://www.srisc.com ?
    108764: 06/09/16: Re: http://www.srisc.com ?
    108779: 06/09/16: Board Opinions TS7300
    108814: 06/09/17: Re: Board Opinions TS7300
    108816: 06/09/17: Re: SSFP16 GPL licensed 16 Fpga processor released
    109101: 06/09/20: Re: Which soft core to use?
    109102: 06/09/20: Re: MicroFpga = program an FPGA as it would be a MCU !
    109298: 06/09/23: Re: MicroFpga = program an FPGA as it would be a MCU !
    115791: 07/02/20: Spartan-3E Sample Packs
    115850: 07/02/22: Re: Xilinx Platform Studio Evaluation Trial Expired (included in Spartan 3E Starter Kit)
    115851: 07/02/22: Re: Spartan-3E starter kit : trouble with configuration from NOR Flash
Ziggy:
    77422: 05/01/06: xilinx as video processor?
    77440: 05/01/06: Re: Spartan 3 Experimenter's Board
    78339: 05/01/29: Re: i need xilinx edk
    78342: 05/01/30: Re: i need xilinx edk
    78346: 05/01/30: Re: i need xilinx edk
    78740: 05/02/07: Re: Xilinx makes dreams true :)
    78756: 05/02/07: Re: Xilinx makes dreams true :)
    78770: 05/02/07: Re: Xilinx makes dreams true :)
    79955: 05/02/27: Re: Implementing Multi-Processor Systems in FPGAs
    79972: 05/02/27: Re: Implementing Multi-Processor Systems in FPGAs
    81862: 05/04/03: Open PowerPC Core?
    81874: 05/04/03: Re: Open PowerPC Core?
    81967: 05/04/05: Re: Open PowerPC Core?
    81973: 05/04/05: Re: Open PowerPC Core?
    81977: 05/04/05: Re: Open PowerPC Core?
    82008: 05/04/05: Re: Reverse engineering ASIC into FPGA
    82290: 05/04/10: Re: edk annual renewal cost?
    82295: 05/04/10: Re: edk annual renewal cost?
    83136: 05/04/24: New FPGA Development Board
    83144: 05/04/25: Re: New FPGA Development Board
    83168: 05/04/25: Re: New FPGA Development Board
    83169: 05/04/25: Re: what is microblaze ?
    83180: 05/04/25: Re: New FPGA Development Board
    83261: 05/04/26: Re: Another Altera FPGA Development Board
    83263: 05/04/26: Re: webpack for os x or freebsd ?
    83300: 05/04/27: Re: *RANT* Ridiculous EDA software "user license agreements"?
    83468: 05/04/30: FPGA Article on Slashdot.
    83897: 05/05/09: Re: 8051 IP core
    84023: 05/05/11: Re: An FPGA eval board at $49!!
    84134: 05/05/12: Re: Minimum circuit to get Spartan-3 running
    84207: 05/05/14: Re: 8051 IP core
    88743: 05/08/27: Re: Library of eBooks on FPGA's and other programming stuff
<zihu88@hotmail.com>:
    77590: 05/01/11: Xilinx PC4 cable programming voltage issue?
    77729: 05/01/15: No device found in Boundary Scan Chain, for Xilinx PC4 Cable
Zik Saleeba:
    15306: 99/03/18: Reconfigurable computing thesis on the web
    15322: 99/03/19: Re: Reconfigurable computing thesis on the web
    15325: 99/03/19: Re: Reconfigurable computing thesis on the web
    15379: 99/03/22: Re: Reconfigurable computing thesis on the web
    15494: 99/03/26: Re: Reconfigurable computing thesis on the web
zilinxchip:
    82744: 05/04/17: Re: FPGA/Embedded courses online or near Toronto
Zimba:
    29465: 01/02/22: Re: How to get Xilinx FPGA demo board?
    29819: 01/03/12: Re: IP Cores, Megacores
    29888: 01/03/15: Re: IP Cores, Megacores
    29897: 01/03/16: Re: IP Cores, Megacores
    29904: 01/03/16: Re: IP Cores, Megacores
    31571: 01/05/30: Re: Spartan2 PCI-IP Core @ power-up
    31638: 01/06/01: Re: Spartan2 PCI-IP Core @ power-up
    33322: 01/07/23: Synchronous output enable not supported?
    33348: 01/07/24: Re: Synchronous output enable not supported?
    33460: 01/07/27: Re: PCI-Interface
    33541: 01/07/30: Re: PCI-Interface
    33542: 01/07/30: Re: 3.3i service pack 8
zimmer:
    79061: 05/02/12: Xilinx : UCF
    79062: 05/02/12: Re: Xilinx : UCF
Zimmer:
    74554: 04/10/13: Where to buy cheap MAXII CPLD?
    74575: 04/10/14: Re: Where to buy cheap MAXII CPLD?
Zinabu Haile:
    155506: 13/07/09: How to Use Spartan 6 Ethernet Port
zinc:
    68957: 04/04/22: xilinx virtex xcv1000 bg560 - init pin does not go high
    69003: 04/04/24: PLease help - afx bg560-100 board
zinger:
    31179: 01/05/14: test
ZioPino:
    83091: 05/04/23: DDR SODIMM on Avnet Virtex II PRO development kit
    83097: 05/04/23: Re: DDR SODIMM on Avnet Virtex II PRO development kit
    83105: 05/04/23: Re: DDR SODIMM on Avnet Virtex II PRO development kit
    83119: 05/04/24: Re: DDR SODIMM on Avnet Virtex II PRO development kit
    83155: 05/04/25: Re: DDR SODIMM on Avnet Virtex II PRO development kit
    83819: 05/05/07: Re: DDR SODIMM on Avnet Virtex II PRO development kit
<zkwjy@tiscali.it>:
    83689: 05/05/05: Xilinx Prom programming
zl:
    118386: 07/04/25: interrupt handler on the Xilkernel PPC405
    118387: 07/04/25: interrupt handler on the Xilkernel PPC405
    118426: 07/04/26: Re: interrupt handler on the Xilkernel PPC405
    118466: 07/04/27: Re: interrupt handler on the Xilkernel PPC405
zl502593045:
    155709: 13/08/12: [HELP]problem with asynchronous fifo ip
<zlatkopetrov@yahoo.com>:
    121287: 07/06/30: How to pass several commands inside xps from script?
    121320: 07/07/02: Re: How to pass several commands inside xps from script?
<zljxii@nowhere.com>:
zlotawy:
    98349: 06/03/08: problem
    98689: 06/03/14: Re: problem
    106790: 06/08/19: xc2vp30-6ff1152
    106792: 06/08/19: Re: xc2vp30-6ff1152
    106998: 06/08/23: DQPs
    107374: 06/08/28: Post-route simulation
    115092: 07/01/30: ahdl --> vhdl
    126094: 07/11/14: Block-ram FIFO in Xilinx
    126134: 07/11/15: Re: Block-ram FIFO in Xilinx
    126187: 07/11/16: Re: Block-ram FIFO in Xilinx
    126229: 07/11/17: Re: Block-ram FIFO in Xilinx
    126483: 07/11/24: Fifo Block-RAM Xilinx ISE - port empty
zlyh:
    92160: 05/11/23: We need to program several thousands Xilinx flashes XCF025...
    92222: 05/11/23: Chief decides to ask Xilinx
    97076: 06/02/16: WebPACK license (and Quartus Web Edition too).
    97135: 06/02/16: Re: WebPACK license (and Quartus Web Edition too).
    130890: 08/04/04: One more question. WebPACK key with ISE
zohair:
    108294: 06/09/07: Synchronous Clocks
    108381: 06/09/09: HOLD violations in Xilinx fpga
    109000: 06/09/19: synchronous clocks
    109503: 06/09/27: Re: synchronous clocks
<zoharl3@gmail.com>:
    89768: 05/09/26: altera new bee
zoinks@mytrashmail.com:
    84860: 05/05/31: program simulation of the ML310 with XPS+ModelSim
    85261: 05/06/07: Simulation problems virtex II
    85690: 05/06/14: generating 90, 180 and 270 shifts
    86449: 05/06/28: CPU address to OCM address translation
    86563: 05/06/30: Cannot find net in ucf, but it's there....
    86570: 05/06/30: Re: Cannot find net in ucf, but it's there....
    86573: 05/06/30: Re: Cannot find net in ucf, but it's there....
    86956: 05/07/11: stupid question about XPS peripheral filenames
    87201: 05/07/19: simulation troubles
    88459: 05/08/18: DDR memory writing all data twice & IPIF questions
    88568: 05/08/23: DCM does not do anything?
    88586: 05/08/23: Re: DCM does not do anything?
    88628: 05/08/24: Re: DCM does not do anything?
    88634: 05/08/24: Re: DCM does not do anything?
    88962: 05/09/01: Re: DCM does not do anything?
    88963: 05/09/01: Using the XUP Virtex-II Pro with EDK 6.3 => errors during platform level signal connect.
    88998: 05/09/02: Re: Using the XUP Virtex-II Pro with EDK 6.3 => errors during platform level signal connect.
    89005: 05/09/02: XUP Virtex-II Pro "invalid target architecture"
    89083: 05/09/05: Re: XUP Virtex-II Pro "invalid target architecture"
    89084: 05/09/05: Re: XUP Virtex-II Pro "invalid target architecture"
    89344: 05/09/13: Re: XUP Virtex-II Pro "invalid target architecture"
    89447: 05/09/15: Re: XUP Virtex-II Pro "invalid target architecture"
    89486: 05/09/16: DCM question
<zoinks@mytrashmail.com>:
    84670: 05/05/24: cannot get compedklib tool to work
    84726: 05/05/25: Re: cannot get compedklib tool to work
Zolee:
    85074: 05/06/03: Share one BRAM block between user logic and microblaze (Spartan3)
    85080: 05/06/03: Re: Share one BRAM block between user logic and microblaze (Spartan3)
    85284: 05/06/07: Re: Placing variables at a specific location (address) using microblaze GCC
    85323: 05/06/07: Re: Anonymous structs in Microblaze C compiler
Zoltan Kocsi:
    3999: 96/09/01: Re: CHEAP XILINX FPGA ROUTING SOFTWARE ?
    4532: 96/11/10: Re: Info on FPGA Internal Architecture/ Programming
    4905: 96/12/28: Re: Exemplar's Leonardo on Linux
    5337: 97/02/08: Anyone for Linux ?
    6987: 97/07/19: Survey
    8496: 97/12/25: Re: PCs vs. workstations
    9029: 98/02/16: Re: Devices and Prices
    9410: 98/03/11: Re: The case for Linux and EDA
    9686: 98/03/31: Re: XactStep6 - The cure for a dongle
    9972: 98/04/19: Re: Verilog to VHDL or VHDL to Verilog
    10206: 98/05/04: Re: Xilinx Foundation and Linux
    10881: 98/06/27: Altera MaxPlus-II problems
    11323: 98/08/05: Re: PCI Core In FPGA
    12056: 98/09/26: Re: Design Security Question
    12076: 98/09/28: Re: Design Security Question
    12181: 98/10/03: Re: Synthesis: Exemplar or Synopsys
    12290: 98/10/08: Re: Altera's reply to request for Max+Plus II under Linux
    12627: 98/10/21: Re: GUI GRINDERs vs SLICK SCRIPTOs
    12628: 98/10/21: Re: isp download cable ?
    13127: 98/11/17: Re: Big-Endian vs Little-Endian
    14326: 99/01/26: Re: The development of a free FPGA synthesis tool
    14386: 99/01/28: Re: The development of a free FPGA synthesis tool
    14452: 99/01/30: Re: The development of a free FPGA synthesis tool
    16451: 99/05/23: Re: Xilinx M1.5 Crash
    16472: 99/05/25: Re: Xilinx M1.5 Crash
    16500: 99/05/26: Re: Xilinx M1.5 Crash
    16540: 99/05/27: Re: Xilinx M1.5 Crash
    16555: 99/05/28: Re: Xilinx M1.5 Crash
    17322: 99/07/21: Re: Solaris vs. NT
    17340: 99/07/22: Re: Solaris vs. NT
    17399: 99/07/24: Re: Solaris vs. NT
    17819: 99/09/08: Re: QuickLogic FPGAs
    21332: 00/03/17: Re: ,,..SAY A PRAYER FOR THE INNOCENT VICTIMS OF BLACK VIOLENCE AND LAWLESSNESS!!..
    21573: 00/03/25: Re: No- FPGA openness
    21651: 00/03/28: Re: FPGA openness
    21723: 00/03/30: Re: FPGA openness
    21809: 00/04/01: Re: FPGA openness
    21808: 00/04/01: Re: FPGA openness
    21827: 00/04/03: Re: FPGA openness
    22246: 00/05/03: Re: How to Prevent theft of FPGA design
    23196: 00/06/17: Two questions
    23629: 00/07/04: Re: Altera Ships Largest PLD
    24302: 00/08/03: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
    25056: 00/08/25: Re: Non-disclosures in job interviews, Round Two
    25181: 00/08/30: Re: Xilinx and CD databooks (rant)
    25553: 00/09/14: Re: hardware compatibility and patent infringement
    26160: 00/10/06: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26215: 00/10/09: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26290: 00/10/11: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26292: 00/10/11: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
    26870: 00/11/02: Re: Alliance under Linux?
    26966: 00/11/06: Re: Alliance under Linux?
    26871: 00/11/02: Re: Alliance under Linux?
    26934: 00/11/04: Re: Alliance under Linux?
    26936: 00/11/04: Re: level shifting buffers ??
    35379: 01/10/02: Linux tools
    35533: 01/10/10: Re: Synplicity/Leonardo License Agreement Information
zooplibob@gmail.com:
    134279: 08/08/04: Chipscope - Clock Error
zootsuit:
    16938: 99/06/18: Re: Actel ActGen and Desktop problem
zora:
    92187: 05/11/23: virtex II global buffer
    92188: 05/11/23: Bidirectional Bus
    92272: 05/11/25: re:Bidirectional Bus
Zoran Miljanic:
    11373: 98/08/07: Employment opportunities in NEC Development Center, Princeton, NJ
Zorjak:
    110624: 06/10/18: generic ROM memory help
    110692: 06/10/19: FIR filter generic
    110708: 06/10/20: Re: FIR filter generic
    110744: 06/10/20: Re: FIR filter generic
    120723: 07/06/14: Quartus Timing Analyzer question
    120773: 07/06/15: Re: Quartus Timing Analyzer question
    120794: 07/06/16: Re: Quartus Timing Analyzer question
    120907: 07/06/20: Re: Quartus Timing Analyzer question
    122738: 07/08/05: bidirectional pin
    122750: 07/08/06: Re: bidirectional pin
    122788: 07/08/07: Re: bidirectional pin
    123394: 07/08/27: bidirectional pin help
    123407: 07/08/27: Re: bidirectional pin help
    123423: 07/08/28: Re: bidirectional pin help
    123497: 07/08/29: Re: bidirectional pin help
    123528: 07/08/29: Re: bidirectional pin help
    123534: 07/08/29: Re: bidirectional pin help
    123542: 07/08/29: Re: bidirectional pin help
    123555: 07/08/30: Re: bidirectional pin help
    127787: 08/01/08: passive serial quaestion
    127792: 08/01/08: Re: passive serial quaestion
    127802: 08/01/08: Re: passive serial quaestion
    128048: 08/01/14: fpga pin to pin conecting
    128090: 08/01/15: Re: fpga pin to pin conecting
    128093: 08/01/15: Re: fpga pin to pin conecting
    132114: 08/05/14: xilinx beginner modelsim question
    132132: 08/05/15: Re: xilinx beginner modelsim question
    132405: 08/05/26: XILINX core generator question
    132442: 08/05/27: Re: XILINX core generator question
    132462: 08/05/27: Re: XILINX core generator question
    132612: 08/06/03: Counter implementation with ise problem
    132629: 08/06/03: Re: Counter implementation with ise problem
    132669: 08/06/05: Re: Counter implementation with ise problem
    133073: 08/06/17: Basic Questions about MIG (Memory Interface Generator)
    133074: 08/06/17: Re: Xilinx Spartan FPGA BlockRAM in Simulation
    133101: 08/06/18: MIG core generator problem
    133144: 08/06/19: Re: Basic Questions about MIG (Memory Interface Generator)
    133579: 08/07/04: Serial Pheripheral Interface for XILINX FPGA
    133581: 08/07/04: Re: Serial Pheripheral Interface for XILINX FPGA
    133623: 08/07/06: Re: Serial Pheripheral Interface for XILINX FPGA
    134450: 08/08/11: spartan sa dcm maximal frequency
    134465: 08/08/11: Re: spartan sa dcm maximal frequency
    138651: 09/03/03: XILINX sysgen cordic divider
    142293: 09/08/02: Questa price
    142361: 09/08/06: ise simulator simple question
    142799: 09/09/02: Sysgen simulation question
    142902: 09/09/07: Xilinx System Generator - Multiple system generator block
zotya:
    79769: 05/02/24: re:C compiler for Picoblaze
zqhpnp@gmail.com:
    90444: 05/10/13: IO interface standard of fpga
    90480: 05/10/14: Help me
    90708: 05/10/19: Re: How to speed up the critical path (Xilinx)
ZR1TECH:
    120667: 07/06/13: Re: DVI-D Tx directly from FPGA?
    120668: 07/06/13: Newbie questions: Can I do this PLL all digitally in a FPGA? 8Khz clock locked on a 100hz pulse
    120675: 07/06/13: Re: Newbie questions: Can I do this PLL all digitally in a FPGA? 8Khz clock locked on a 100hz pulse
    120677: 07/06/13: Re: Newbie questions: Can I do this PLL all digitally in a FPGA? 8Khz clock locked on a 100hz pulse
zsolt.garamvolgyi:
    152952: 11/11/04: PCI Express development board
    152961: 11/11/05: Re: PCI Express development board
    152962: 11/11/05: Re: PCI Express development board
    152965: 11/11/05: Re: PCI Express development board
    152972: 11/11/07: Re: PCI Express development board
ZSpider:
    42429: 02/04/23: Reasonably Priced Development Software ??
    42447: 02/04/24: Re: Reasonably Priced Development Software ??
Zspider:
    69860: 04/05/22: OT: Electronics learner kit?
    69894: 04/05/23: Re: OT: Electronics learner kit?
zss:
    143844: 09/10/29: error while opening hex file
zubinkumar:
    141190: 09/06/10: USB3300 - Xilinx ML401 interface
zule:
    15913: 99/04/21: Re: Okay, a really dumb Xilinx FPGA question.
    15977: 99/04/24: Re: Using Embedded RAM in Xilinx Virtex Chips
    16055: 99/04/30: Re: pricess for Xilinx Virtex XV300 and XV800
    16056: 99/04/30: Re: XILINX configuration through JTAG
    16057: 99/04/30: Re: Need HELP!!! Hurry
    16058: 99/04/30: Re: Help with XACT 5.2 - 6
    16109: 99/05/04: Re: Any Material on advances in FPGA Technology
    16200: 99/05/10: Re: Looking for Altera APEX board
    16417: 99/05/21: Re: Xilinx M1.5 Crash
    16501: 99/05/26: Re: Beginner's Virtex pinout Question
    16537: 99/05/27: Re: Instantiate Clocks
    16538: 99/05/27: Re: FPGA express : Schematic viewing options w/o Vista?
    16541: 99/05/27: Re: JTAG: Altera & Xilinx
<zuzaila@gmail.com>:
    131884: 08/05/06: How program PROM from msc file
zwalter:
    154385: 12/10/19: Periodic reads - Xilinx Virtex6
<zwsdotcom@gmail.com>:
    95580: 06/01/24: Re: OT:Shooting Ourselves in the Foot
    106815: 06/08/20: ISE/EDK "target pattern contains no `%'"
    106823: 06/08/20: Re: xilinx or altera?
    107442: 06/08/28: Semi-OT: Free (USA) tube of Philips CPLDs
    107858: 06/09/01: Impossible to download WebPACK?
    107869: 06/09/01: Re: Impossible to download WebPACK?
    107881: 06/09/01: Re: Impossible to download WebPACK?
    107915: 06/09/02: Re: Impossible to download WebPACK?
    107921: 06/09/02: Here are the URLs (was Re: Impossible to download WebPACK?)
    107925: 06/09/02: Re: Here are the URLs (was Re: Impossible to download WebPACK?)
    107945: 06/09/02: Re: Impossible to download WebPACK?
    107947: 06/09/02: Re: Impossible to download WebPACK?
    107986: 06/09/03: Re: Here are the URLs (was Re: Impossible to download WebPACK?)
    108592: 06/09/13: Microblaze development without EDK?
    109611: 06/09/30: Re: Are you ready for Virtex-5? We are...
    109619: 06/10/01: Re: Are you ready for Virtex-5? We are...
    111883: 06/11/12: Xilinx USB cable - can't install driver
    112054: 06/11/15: Old Spartan-II, worth prototyping?
    112065: 06/11/15: Re: Old Spartan-II, worth prototyping?
    112248: 06/11/18: Re: PCMCIA interface
    113943: 06/12/29: Re: ChipScope - impact on design or not?
    113949: 06/12/29: Re: FPGA workstation - should I wait for Window Vista?
    114639: 07/01/21: Using demo IP libraries?
    115386: 07/02/08: Re: Radar pulse detection
    139015: 09/03/18: Re: Bullshit! - Re: Zero operand CPUs
ZX:
    52743: 03/02/20: Quartus II problem
    52744: 03/02/20: Re: How good are Megafunctions
    52757: 03/02/20: Re: Quartus II problem
zyan:
    109015: 06/09/20: DDR2 Memory Controller : IOSTANDARD
    109019: 06/09/20: Re: DDR2 Memory Controller : IOSTANDARD
    109104: 06/09/20: Re: DDR2 Memory Controller : IOSTANDARD
    109115: 06/09/20: Re: DDR2 Memory Controller : IOSTANDARD
    109117: 06/09/20: Re: DDR2 Memory Controller : IOSTANDARD
    109129: 06/09/21: iMPACT: Problem in downloading bit file
    109210: 06/09/21: Re: iMPACT: Problem in downloading bit file
    109954: 06/10/08: Re: Xilinx distributor in South East Asia
    111907: 06/11/13: Virtex-4 : OCM
    111908: 06/11/13: MPMC2: MPMC2 with DDR2 SDRAM
    111969: 06/11/13: Re: Virtex-4 : OCM
    112772: 06/11/28: Re: MPMC2: MPMC2 with DDR2 SDRAM
$:
    22142: 00/04/26: Looking for contract/consulting help
$$$$:
    7900: 97/10/28: $$$$$$$ Easy Money $$$$$$$$$$$
*:
    2831: 96/02/14: Re: Help: Xilinx behavior if Power down
**** ****:
    31515: 01/05/29: Re: what cables and softwares do you need to use "Xilinx FPGA Demonstration Evaluation Board"?
******:
    42906: 02/05/06: Re: max 7000
,, ,:
    4982: 97/01/08: FAQ
--:
    36061: 01/10/27: Re: DSP on FPGA Opinions Needed->Those are good questions.
.:
    142934: 09/09/08: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::)
.-:
    26727: 00/10/26: hebben eengoedkoop bordje
123:
    51183: 03/01/06: help for MAXPLUS2!
3.14:
    83696: 05/05/05: MicroBlaze latencies
345678:
    37538: 01/12/13: Problem with PALASM 4 and 22V10 and GLOBAL.SETF
7:
    72371: 04/08/17: New cache
    76290: 04/11/30: Re: Quartus Debian Install
:-):
    95153: 06/01/20: Hi :-) Someone build a parallel JTAG cable like the xilinx one ?
    95744: 06/01/25: Re: Hi :-) Someone build a parallel JTAG cable like the xilinx one
    96889: 06/02/13: Newb question about Xilinx Impact and parallel cable III ....
    96952: 06/02/14: Re: Newb question about Xilinx Impact and parallel cable III ....
    96953: 06/02/14: Re: Newb question about Xilinx Impact and parallel cable III ....
    96955: 06/02/14: Re: Newb question about Xilinx Impact and parallel cable III ....
    97810: 06/02/28: Re: XC9500 JTAG Initialize problem
    97811: 06/02/28: New XC9572 decoupling newbie question :-)
    97846: 06/02/28: Re: New XC9572 decoupling newbie question :-)
<()>:
    35619: 01/10/12: Re: High level synthesis will never work well :)
<212>:
    113696: 06/12/19: Need book for verilog on xc9536?
<222>:
    113568: 06/12/17: Frequency divider?
    113569: 06/12/17: Re: Frequency divider?
    113574: 06/12/17: Re: Frequency divider?
    113578: 06/12/17: Re: Frequency divider?
    113586: 06/12/17: Re: Frequency divider?
    113632: 06/12/18: Re: Frequency divider?
    113643: 06/12/19: Frequency divider ?
    113646: 06/12/19: Re: Frequency divider ?
    113663: 06/12/19: Re: Frequency divider ?
    113670: 06/12/19: Re: Frequency divider ?
    113685: 06/12/19: Re: Frequency divider ?
<223>:
    113771: 06/12/21: timing?
<>:
    8939: 98/02/08: HOT Phone numbers
    30375: 01/04/04: PC software for 10$/cd
    59080: 03/08/07: Re: Size does matter
??:
    141334: 09/06/19: Re: Open source processors
    141336: 09/06/19: Re: Xilinx Block RAM Sim
???:
    64793: 04/01/14: Re: simulating xilinx clkdll
    91374: 05/11/04: Re: Xilinx ISERDES
?????? ?????:
    63112: 03/11/15: Re: XILINX Foundation Series 3_1i Problem with installation...
두루넷:
    31203: 01/05/15: vertex echo PLL logic
박구용:
    20134: 00/01/28: ARM core?
보라넷:
    22276: 00/05/04: [Q] Virtex FPGA : compile time error message
손기영:
    45787: 02/08/06: Re: Pricing on Virtex 2 pro XC2VP4?
    53831: 03/03/25: where is SMC34c60 similar IP ?
양세양:
    22081: 00/04/20: A New FPGA Board Capable of HW/SW Co-debugging
에이터치:
    29185: 01/02/09: FPGA for ADS7843
이병욱:
    23093: 00/06/14: FPGA Express & MAX+PLUS II Using ?
이춘용:
    38447: 02/01/15: SDH Pointer generator and Pointer interpreter
이헌영:
    11648: 98/08/28: (req)I'm looking for foundation
임재환:
    14698: 99/02/12: help to look for VHDL source related with PCI.
장영진:
    21399: 00/03/22: Looking for Xilinx Spartan Synthesis library for Synopsys.
장종우:
    30663: 01/04/23: What is reconfigurable processor?
전성모:
    35955: 01/10/25: What's the JBits ?
쩜쉔:
    141337: 09/06/19: Re: Open source processors
킹퓐:
    33813: 01/08/06: Re: Why did Zephram spool outside all the users? We can't post procedures unless Brion will grudgingly dig afterwards.
律碌頓 詵 菹蓋訣테:
    2444: 95/12/06: Where to obtain the FPGA group FAQ?
纘老탱 險虜:
    62924: 03/11/11: XILINX Foundation Series 3_1i Problem with installation...
    62988: 03/11/12: Re: XILINX Foundation Series 3_1i Problem with installation...
    63113: 03/11/15: Re: XILINX Foundation Series 3_1i Problem with installation...


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