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Jim Granville <no.spam@designtools.maps.co.nz> wrote: ... > Another wrinkle in the "drop the die into a PQ208" idea, is that > many now use flip chip spread bonding (bond pads over the whole die) > - works very well in BGA, but rather kills using a perihperal bond > package. Even MLF only gets low Z on the Gnd bondings, and FPGA's > have many supplies. The National Ethernet PHYS DP83847 has an interesting LLP package with "split" exposed pad. So some package creativity not going the obvious BGA way. It seem however newer National PHYS use "normal" packaging -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 116126
As I mentioned before, Virtex-5 devices are plentifully available at Xilinx, and now also from Avnet and NuHorizon. The outcry in this newsgroup helped to speed up the process ! The easiest way is to go to www.xilinx.com, click on the Xilinx store listing in the lower left hand corner, then click on Virtex-5 in the upper right hand corner, and admire the long list of available parts. Then click on your favorite distributor's name, and voila, you have reached the listing. Their listing is not user-friendly, 1/1 means you can buy parts in single-piece quantity (I checked that specifically, it does not mean a whole tray!), but prices and available quantity are not published. You will have to use the phone. Believe it or not, this is still the U.S. of A, where the customer is known to be king ;-) But let's rejoice that, at last, you can get hold of these parts. (The distributor has them physically in his inventory, so challenge him on the 6 weeks). The cage-rattling paid off. Peter AlfkeArticle: 116127
On Mar 1, 12:45 pm, "Brandon Jasionowski" <killerhe...@gmail.com> wrote: > On Mar 1, 7:12 am, "John McCaskill" <junkm...@fastertechnology.com> > wrote: > > > > > On Feb 28, 11:12 pm, "Brandon Jasionowski" <killerhe...@gmail.com> > > wrote: > > > > Hello, > > > > I'm getting usual results from my BUFR network in Timing Analyzer: > > > > <SNIP> > > > -------------------------------------------------------------------------------- > > > Hold Violations: TS_adc1_dclk_p = PERIOD TIMEGRP "TG_adc1_dclk_p" 4 ns > > > HIGH 50%; > > > -------------------------------------------------------------------------------- > > > Hold Violation: -0.974ns (requirement - (clock path skew + > > > uncertainty - data path)) > > > Source: adc1_reg_inst/nshifts_gen[1].dff_ins/d_r_7 > > > (FF) > > > Destination: adc1_reg_inst/nshifts_gen[2].dff_ins/d_r_7 > > > (FF) > > > Requirement: 0.000ns > > > Data Path Delay: 1.275ns (Levels of Logic = 0) > > > Positive Clock Path Skew: 2.249ns > > > Source Clock: adc1_dclk rising at 0.000ns > > > Destination Clock: adc1_dclk rising at 4.000ns > > > Clock Uncertainty: 0.000ns > > > Timing Improvement Wizard > > > Data Path: adc1_reg_inst/nshifts_gen[1].dff_ins/d_r_7 to > > > adc1_reg_inst/nshifts_gen[2].dff_ins/d_r_7 > > > Delay type Delay(ns) Logical Resource(s) > > > ---------------------------- ------------------- > > > Tcko 0.268 adc1_reg_inst/nshifts_gen[1].dff_ins/ > > > d_r_7 > > > net (fanout=1) 1.065 adc1_reg_inst/d_array<2><7> > > > Tckdi (-Th) 0.058 adc1_reg_inst/nshifts_gen[2].dff_ins/ > > > d_r_7 > > > ---------------------------- --------------------------- > > > Total 1.275ns (0.210ns logic, 1.065ns route) > > > (16.5% logic, 83.5% route) > > > </SNIP> > > > > 2.25 ns positive clock path skew? Omg!? So, then I looked at the > > > partially PAR'ed output on this SX55 FPGA. Turns out the stupid tools > > > are expanding the BUFR network across multiple BUFR regions, including > > > horizontally (x direction). I have an 8k FIFO (necessary) to > > > transition from this BUFR clock to a slower BUFG clock. Looks like the > > > tools are placing the FIFO on the left side of the FPGA and the top- > > > right BUFR is using non BUFR resources (I assume) to route the clock > > > across. > > > > Is this what's causing my enormous clock path skew? I will try to > > > apply some area_group slice/bram constraints to my FIFOs, but I find > > > this to be an extreme pain in the butt... I'm using a COTS board, > > > which is configured with 4 ADC data channels and 4 ADC clocks. The ADC > > > data is about 180 degrees out of phase w/ the clock (fine). Is there a > > > way to constrain nets/instances/etc. to a regional clock region? > > > That'd be really sweet... > > > > Is there a better way to transition from the regional clock to a > > > global clock other than using a FIFO? This is giving me a headache b/c > > > my design takes forever to PAR and I can't meet timing :( > > > > Thanks, > > > -B > > > When we first started using the regional clock buffer in our designs, > > the tools did not automatically place the logic that used that clock > > into the three clock regions that the clock could reach. In my case, > > it just failed to route. Our solution was to put an area group > > constraint on the logic that used that clock, and that fixed the > > problem. This was with a 7.x version of EDK/ISE. > > > That little inconvenience aside, the BUFIOs and BUFRs are very nice. > > The BUFR is what makes it possible for us to meet timing for 66 MHz > > PCI on a V4FX60. As the FPGAs get bigger, the BUFG delays get longer. > > On PCI, you should not use a DCM to tune out the clock delay because > > the clock speed is allowed to vary, but I don't know how many system > > do that. > > > Regards, > > > John McCaskillwww.fastertechnology.com > > Right. So I'm trying constraints like: > > <SNIP> > INST "fifoadc1_inst" AREA_GROUP = "AG_fifoadc1_inst"; > AREA_GROUP "AG_fifoadc1_inst" COMPRESSION = 100; > AREA_GROUP "AG_fifoadc1_inst" RANGE = SLICE_X48Y128:SLICE_X95Y255; > AREA_GROUP "AG_fifoadc1_inst" RANGE = RAMB16_X4Y16:RAMB16_X7Y31; > </SNIP> > > Is there an area group constraint that's all encompassing, i.e. > includes FIFO16, DSP48, SLICES, RAMB16, etc.? > > Thanks, > -Brandon Set range to clock regions may be what you are looking for. e.g. AREA_GROUP "AG_fifoadc1_inst" RANGE = CLOCKREGION_X0Y4, CLOCKREGION_X0Y7; Cheers, Jim http://home.comcast.net/~jimwu88/tools/Article: 116128
Hi > and the link in opencores site > for VHDL CAN core is going to some odd page. You can download the Opencores VHDL CAN core from here: http://web.archive.org/web/20050407203157/http://www.logic-xpress.com/CAN_VHD.ZIP (it is an archive of the site from 2005). I have no idea if it works however. The developer says it is untested, so it probably needs work. If at all possible, I advise you to use the Verilog version: http://www.opencores.org/pdownloads.cgi/list/can I have tested and implemented this (on Xilinx Spartan IIE), and it works well. You can have a mixed-source project in recent version of Xilinx tools, so you could combine the Verilog core with the rest of your code in VHDL. Simulation is a bit more tricky if you only have the "limited" editions of Modelsim etc. TomArticle: 116129
>> Anyway, I hope this is of interest, Syms. There's an interesting link in one of the papers to FastHenry, a free 3D solver, at http://www.fastfieldsolvers.com/Article: 116130
"Fred" <fred@n0spam.com> wrote in message news:1172763185.94208.0@despina.uk.clara.net... > > "TC" <noone@nowhere.com> wrote in message > news:u0oFh.7044$_73.434@newsread2.news.pas.earthlink.net... >> >> "Fred" <fred@n0spam.com> wrote in message >> news:1172664477.23596.0@proxy00.news.clara.net... >>> I'm writing the initial state machine for a PCI-Express card and am >>> stuck at the very first hurdle. I'm using a Philips PX1011 PHY and I'm >>> able detect the receiver on the motherboard. >>> >>> I then send it TS1s with pad characters in the Link and Lane numbers but >>> the motherboard transmitter doesn't transmit TS2 but instead goes into >>> idle state. I'm convinced that correct serial data is coming out of the >>> PHY. There's no need for speed negotiation since both are advertising >>> the slowest speed. >>> >>> I would be grateful if anyone here could help. >>> >>> >> >> If you designed/developed the board are you sure that you didn't simply >> swap Rx and Tx? You wouldn't be the first to do that! > > The signal naming convention is perhaps ambiguous but the signals are > definitely the correct way round. > >> >> How are you debugging this? Do you have equipment connected >> (oscilliscopes or logic analyzers) that let you directly observer the >> link (differential pairs) or are you inferring what is going on? >> >> You didn't say if the motheboard transmitted TS1s, or not. >> >> If the motherboard DID NOT transmit TS1's then the motheboard probably >> didn't succesfully "detect" your board (i.e. never exited the detect >> state and never entered the polling state). >> >> If the motherboard did transmit TS1s and then eventually went back to >> electical-idle then it probably isn't receiving your TS1s correctly (and >> it is configured to NOT go into "compliance mode"). >> > > > Many thanks - this is presently this is my conclusion. Unfortunately, > while PHYs have a loopback mode they don't have a simple means of > connecting RX input to TX output to ensue that anything transmitted isn't > garbage! > > Many thanks again. > > > Of course, the reason that the motherboard might not be receiving your TS1's correctly might be that they are not correctly transmitted. In other words, it might be receiving exactly what you transmitted but it determines that it isn't a TS1 (i.e. it is malformed). Are you sure you have properly constructed the TS1? Are you sure that you are transmitting it in the correct byte order? Are you sure that you have the right bit-order between your PHY and FPGA? TCArticle: 116131
Austin Lesea wrote: > As the largest FPGA part in existence, we were unable to meet the demand > so soon after first lot fab-out. Austin Out of general interest, is the die still around 22mm x 24mm, or are you a bit closer to the Canon EOS-5D number posted by Tom Womack at 36mm x 24mm?Article: 116132
On Feb 22, 4:29 pm, ziggy <z...@fakedaddress.com> wrote: > In article <1170834754.019178.292...@a34g2000cwb.googlegroups.com>, > > > > > Not that this answers your question, but where did you buy it from? Im > looking to get one of them myself.- Hide quoted text - > > - Show quoted text - you can purchase it online from the xilinx web page, here is the link http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-SK-US&sGlobalNavPick=PRODUCTS&sSecondaryNavPick=BOARDS)and thanks sawaakArticle: 116133
Hi, I am working with Virtex-4. I have generated a VHDL code and need it to communicate it with Power PC and some other cores such as UART and I2C which sits on the OPB. I am willing to connect my IP core to this bus. can anyone help me how to do this?? Thanks and regards, SandipArticle: 116134
On 3=E6=9C=882=E6=97=A5, =E4=B8=8A=E5=8D=8812=E6=97=B655=E5=88=86, "Benjami= n Todd" <benjamin.toddREMOVEALLCAPIT...@cernREMOVEALLCAPITALS.ch> wrote: > i'd say Yes...But make sure it's only teh asynchronous reset thats causing > these problems, nothing else. And even then I recommend you have a look > around for debates over synch vs asynch reset... it's one of these issues > that is unpredictable, and can make your circuits really misbehave... > Ben > > "skyworld" <chenyong20...@gmail.com> wrote in message > > news:1172720587.730126.106160@s48g2000cws.googlegroups.com... > So do you mean that I can ignore these warnings? > > On 2=C3=94=C3=8227=C3=88=C3=95, =C3=8F=C3=82=C3=8E=C3=A74=C3=8A=C2=B157= =C2=B7=C3=96, "Benjamin Todd" > > <benjamin.toddREMOVEALLCAPIT...@cernREMOVEALLCAPITALS.ch> wrote: > > normally you wont have specified any time constraints on the reset > > signal... > > I aam assuming you have a global asynchronous reset. > > > To correctly manage the reset you should try to synchronise it to the > > internal clock using a couple of flip-flops. This way it ensures a > > synchronous release of the reset that can be treated and analysed in the > > same way as any other. I think you may still get the warnings for > > violations of the first asynchronous input. > > > Anyways, the idea of synchronous vs asynchronous reset is a long > > discussion > > =3D) > > > Ben > > > "skyworld" <chenyong20...@gmail.com> wrote in message > > >news:1172557239.722343.245410@p10g2000cwp.googlegroups.com... > > > > Hi, > > > I am doing FPGA design with xilinx spartan 3e. When I finished P&R, I > > > checked the timing report. Everything is ok, and there is no timing > > > violations. But when I run post simulation, the modelsim reports some > > > timing errors for some registers with $recovery(...). I checked the > > > time when these errors occur. They happened to be the time when reset > > > is de-assertion. I tried to change reset period, but this time other > > > register report $recovery/$setup/$hold errors. It is very strange > > > because I have passed P&R, there is no timing violations, why does > > > these errors orrur? Can anybody help me? thanks very much. Thanks for your help.Article: 116135
>
> > library ieee;
> > use ieee.std_logic_1164.all;
> > use ieee.std_logic_unsigned.all;
>
> > entity BRAM_test is
> > port (CLOCK : in std_logic;
> > reset : in std_logic;
> > di : in std_logic_vector(15 downto 0);
> > do : out std_logic_vector(15 downto 0));
> > end BRAM_test;
>
> > architecture syn of BRAM_test is
>
> > type ram_type is array (1023 downto 0) of std_logic_vector (15 downto 0);
> > signal RAM : ram_type;
> > attribute ram_style : string;
> > attribute ram_style of RAM: signal is "block";
>
> > type STATE_TYPE is (P1, P2, P3);
> > signal STATE : STATE_TYPE;
>
> > signal addr : std_logic_vector(9 downto 0);
>
> > begin
> > main : process (CLOCK, RESET)
> > begin
> > if (RESET = '1') then
> > STATE <= P1;
> > addr <= (others => '0');
> > elsif (CLOCK'event and CLOCK = '1') then
> > case STATE is
> > when P1 =>
> > RAM(conv_integer(addr)) <= di;
> > STATE <= P2;
> > when P2 =>
> > do <= RAM(conv_integer(addr));
> > STATE <= P3;
> > when P3 =>
> > addr <= addr + '1';
> > STATE <= P1;
> > end case;
> > end if;
> > end process main;
> > end syn;
hi,
I think there can be no reset to the block ram....
remove it and try.
and i believe u r using ur RAM in write first mode.
i think the following modification to your code should work.
ibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity BRAM_test is
port (CLOCK : in std_logic;
-- reset : in std_logic;
di : in std_logic_vector(15 downto 0);
do : out std_logic_vector(15 downto 0));
end BRAM_test;
architecture syn of BRAM_test is
type ram_type is array (1023 downto 0) of std_logic_vector (15 downto
0);
signal RAM : ram_type;
attribute ram_style : string;
attribute ram_style of RAM: signal is "block";
type STATE_TYPE is (P1, P2, P3);
signal STATE : STATE_TYPE;
signal addr : std_logic_vector(9 downto 0);
begin
main : process (CLOCK)
begin
-- if (RESET = '1') then
-- STATE <= P1;
-- addr <= (others => '0');
if (CLOCK'event and CLOCK = '1') then
case STATE is
when P1 =>
RAM(conv_integer(addr)) <= di;
do<=di;
STATE <= P2;
when P2 =>
do <= RAM(conv_integer(addr));
STATE <= P3;
when P3 =>
addr <= addr + '1';
STATE <= P1;
end case;
end if;
end process main;
end syn;
-
Article: 116136On 2007-03-02, Steve Battazzo <thesteveman_ice9@yahoo.co.jp> wrote: > error while loading shared libraries: libXm.so.3: cannot open shared > object file: no such file or directory > > Do I need to find this file and get it into the appropriate directory, > or is it there and I just need to point the program to it? libXm is not included so you have to find it in some way. If you didn't already know it, libXm is the Motif library. /AndreasArticle: 116137
On 1 Mar 2007 22:44:05 -0800, "Sandip" <sandip.gaikwad@gmail.com> wrote: >Hi, > >I am working with Virtex-4. I have generated a VHDL code and need it >to communicate it with Power PC and some other cores such as UART and >I2C which sits on the OPB. I am willing to connect my IP core to this >bus. can anyone help me how to do this?? > You may use the generic OPB_IPIF from Xilinx ( directly or using the create/Import peroipherla wizzard), or you may implement your own OPB interface by reading the OPB specification. The first way is faster to develop, while the second may have faster throughput Best regards, ZaraArticle: 116138
Hello, guys... another question. I've started playing around with this software a bit and when I tried to use floorplanner I got this error: error while loading shared libraries: libXm.so.3: cannot open shared object file: no such file or directory Do I need to find this file and get it into the appropriate directory, or is it there and I just need to point the program to it? Thanks, SteveArticle: 116139
Hi, Thank you all for your inputs. i did download the code from the path that you have given me. Tom, thank you for informing on mixed mode implementation. i will look into it, and try to work it out that way. thanks rajuArticle: 116140
On 2 mar, 09:34, Steve Battazzo <thesteveman_i...@yahoo.co.jp> wrote: > I've started playing around with this software a bit and when I tried to > use floorplanner I got this error: > > error while loading shared libraries: libXm.so.3: cannot open shared > object file: no such file or directory Open a terminal, and run this command : $ sudo apt-get install libmotif3 This package contains the libXm.so.3 As explained in my french article, you may also require other lib that can be installed by the following commands : $ sudo apt-get install libxp6 $ sudo apt-get install libcurl3 Luzerne GANHIR PS : with Ubuntu, an easy "GUI" way to find the package containing a required library is to open "synaptic" (System>Administration>Synaptic) and search for the name of the lib.Article: 116141
Hi, Do check your reset sequence PHY requires... If motherboard is not receving TS1 that means transmitter isnt reset properly. Again how are u watching the traffic. Do let me know..i hav debugged our PCIe core with altera PHY on board too...so i can surely help u... regards, RohitArticle: 116142
Hi
Thanks for your feedback. Unfortunately both suggestions didn't work :-(.
When removing the Reset path the synthesized ram will get dual ported
instead of single ported (see below). I tried to rewrite it and make the
read and write enable signals explicit and decoupling the reset from ram.
It also doesn't work i.e. it still gives distributed instead of block
ram :-(.
Any other suggestions?
ST
rewritten part:
main : process (CLOCK, reset)
begin
if (RESET = '1') then
STATE <= P1;
addr <= (others => '0');
we <= '0';
re <= '0';
elsif (CLOCK'event and CLOCK = '1') then
case STATE is
when P1 =>
we<='1';
STATE <= P2;
when P2 =>
we<='0';
re<='1';
STATE <= P3;
when P3 =>
addr <= addr + '1';
STATE <= P1;
end case;
end if;
end process main;
ram_ctl: process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
if(we='1') then
RAM(conv_integer(addr)) <= di;
end if;
if(re='1') then
do <= RAM(conv_integer(addr));
end if;
end if;
end process ram_ctl;
Version with no reset path:
Found 1024x16-bit dual-port distributed RAM for signal <RAM>.
-----------------------------------------------------------------------
| ram_style | block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 1024-word x 16-bit | |
| clkA | connected to signal <CLOCK> | rise |
| weA | connected to internal node | high |
| addrA | connected to signal <addr> | |
| diA | connected to signal <di> | |
-----------------------------------------------------------------------
| Port B |
| aspect ratio | 1024-word x 16-bit | |
| enB | connected to internal node | high |
| addrB | connected to signal <addr> | |
| doB | connected to internal node | |
-----------------------------------------------------------------------
WARNING:Xst:1440 - Cannot use block RAM resources. Please check that the RAM
contents is read synchronously.
original version:
Synthesizing Unit <BRAM_test>.
Related source file
is "/amd/iss1/users/ma/tstone/georg/bram/BRAM_test.vhd".
Found 1024x16-bit single-port distributed RAM for signal <RAM>.
-----------------------------------------------------------------------
| ram_style | block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 1024-word x 16-bit | |
| clkA | connected to signal <CLOCK> | rise |
| weA | connected to internal node | high |
| addrA | connected to signal <addr> | |
| diA | connected to signal <di> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
WARNING:Xst:1440 - Cannot use block RAM resources. Please check that the RAM
contents is read synchronously.
Article: 116143"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message news:dptdu29sj45cdlj37vmtqjn0nvn8t1p7ro@4ax.com... >> > Another cost that's often poorly accounted for is component placement. > Some years ago I worked with an analog designer who was trying to > figure out how much it cost an assembly house to place a small > discrete component on a board. He asked our assembly house, which > declined to give us a precise--or even semi-precise--answer. (Some > assembly houses seem to treat their formula for calculating board > assembly costs as a trade secret; I guess they're afraid the customers > will use the formula to sanity-check future quotes.) > > This analog designer, a very bright fellow, was not to be deterred by > this, and proceeded to create his own formula based on a number of > assemblies we'd built (if you try this, it helps when you have some > assemblies with only ICs, and other assemblies with ICs plus about > 5,000 analog parts). He concluded that while we were paying a penny > for a capacitor or resistor, we paid the assembly house 8 or 9 cents > to place the part on the board. Maybe this is the correct number and > maybe it isn't, but it bolsters your point that reducing total > component cost may not lead to the lowest overall assembly cost. > > Bob Perlman > Cambrian Design Works > http://www.cambriandesign.com > Hi Bob, That's interesting. I've emailed some assembly folks I know, to see if I can get hold of how they price their work. If I get anywhere with it, I'll report back! Cheers, Syms.Article: 116144
Sandip wrote: > Hi, > > I am working with Virtex-4. I have generated a VHDL code and need it > to communicate it with Power PC and some other cores such as UART and > I2C which sits on the OPB. I am willing to connect my IP core to this > bus. can anyone help me how to do this?? > > Thanks and regards, > Sandip > You also need an plb to opb bridge (available within the edk). FrankArticle: 116145
Hi, I need to access a PLB slave from the Microblaze CPU via the OPB-to- PLB bus. The PLB slave requires a cache line when written to. Can I generate this? It seems to me that since the Microblaze only writes byte, half-word or word to the OPB-to-PLB, the bridge will never do a line write on the PLB. Any suggestions? Thanks, eArticle: 116146
"Patrick Dubois" <prdubois@gmail.com> writes: >> This has just reminded me of something I discovered recently: >> >> Neither PAR nor TRCE return an error if the design fails timing, so >> any script/makefile which relies on the return code being non-zero as >> an error (like... well... just about anything sane!) will carry on >> through it's script as if everything is OK! >> >> You have to parse the PAR logfile for "No timing errors found" if you >> want to be sure. >> >> I have a change request in to fix this, please add your weight to the >> request (unless you think I'm bonkers for thinking that failing timing >> is an error!) >> >> Cheers, >> Martin > > Very good point. I always try to remind new engineers here to always > remember to check the timing report part of the PAR log to make sure > that there are no timing errors. I'll try to open a webcase on the > issue. Do you have a CR number I can refer to? > Not yet, I'll try and remember to post it here when I get it... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 116147
Oh, you wanted a single port? Look at the BlockRAM operation in single port mode. You can have an ENA that will allow a read and write. You can have a WE that - combined with ENA - will allow a write. There is no read enable. If you want a read enable - rather than a global enable - it will be a dual port. - John_H S.T. wrote: > Hi > > Thanks for your feedback. Unfortunately both suggestions didn't work :-(. > When removing the Reset path the synthesized ram will get dual ported > instead of single ported (see below). I tried to rewrite it and make the > read and write enable signals explicit and decoupling the reset from ram. > It also doesn't work i.e. it still gives distributed instead of block > ram :-(. > > Any other suggestions? > ST > > rewritten part: > main : process (CLOCK, reset) > begin > if (RESET = '1') then > STATE <= P1; > addr <= (others => '0'); > we <= '0'; > re <= '0'; > elsif (CLOCK'event and CLOCK = '1') then > case STATE is > when P1 => > we<='1'; > STATE <= P2; > when P2 => > we<='0'; > re<='1'; > STATE <= P3; > when P3 => > addr <= addr + '1'; > STATE <= P1; > end case; > end if; > end process main; > ram_ctl: process (CLOCK) > begin > if (CLOCK'event and CLOCK='1') then > if(we='1') then > RAM(conv_integer(addr)) <= di; > end if; > if(re='1') then > do <= RAM(conv_integer(addr)); > end if; > end if; > end process ram_ctl; > > > Version with no reset path: > Found 1024x16-bit dual-port distributed RAM for signal <RAM>. > ----------------------------------------------------------------------- > | ram_style | block | | > ----------------------------------------------------------------------- > | Port A | > | aspect ratio | 1024-word x 16-bit | | > | clkA | connected to signal <CLOCK> | rise | > | weA | connected to internal node | high | > | addrA | connected to signal <addr> | | > | diA | connected to signal <di> | | > ----------------------------------------------------------------------- > | Port B | > | aspect ratio | 1024-word x 16-bit | | > | enB | connected to internal node | high | > | addrB | connected to signal <addr> | | > | doB | connected to internal node | | > ----------------------------------------------------------------------- > WARNING:Xst:1440 - Cannot use block RAM resources. Please check that the RAM > contents is read synchronously. > > original version: > > Synthesizing Unit <BRAM_test>. > Related source file > is "/amd/iss1/users/ma/tstone/georg/bram/BRAM_test.vhd". > Found 1024x16-bit single-port distributed RAM for signal <RAM>. > ----------------------------------------------------------------------- > | ram_style | block | | > ----------------------------------------------------------------------- > | Port A | > | aspect ratio | 1024-word x 16-bit | | > | clkA | connected to signal <CLOCK> | rise | > | weA | connected to internal node | high | > | addrA | connected to signal <addr> | | > | diA | connected to signal <di> | | > | doA | connected to internal node | | > ----------------------------------------------------------------------- > WARNING:Xst:1440 - Cannot use block RAM resources. Please check that the RAM > contents is read synchronously.Article: 116148
Hello! So the only ucf timing-related constraint I've ever really had
cause to use is the PERIOD constraint, such as:
NET "CLKIN" TNM_NET = "CLKIN";
TIMESPEC "TS_CLKIN" = PERIOD "CLKIN" 19.9 ns HIGH 50 %;
I remember reading somewhere on the xilinx supprt site that you should
always give yourself several hundred ps of wiggle-room, but I also
remember reading that the tools take into account process and temp
variations and so I should never try and be over-agressive in my
timing constraints.
Does anyone have any experience one way or the other that they can
share? What is your constraint strategy? I notice that the synthesis
of my designs tends to be pretty sensitive to the actual constraint
value -- devices that that synth at 19.8 ns might not at 19.9, even
though it is a "slower" design.
Thanks!
...Eric
Article: 116149On Mar 2, 10:49 am, j...@mit.edu wrote: > Hello! So the only ucf timing-related constraint I've ever really had > cause to use is the PERIOD constraint, such as: > > NET "CLKIN" TNM_NET = "CLKIN"; > TIMESPEC "TS_CLKIN" = PERIOD "CLKIN" 19.9 ns HIGH 50 %; > > I remember reading somewhere on the xilinx supprt site that you should > always give yourself several hundred ps of wiggle-room, but I also > remember reading that the tools take into account process and temp > variations and so I should never try and be over-agressive in my > timing constraints. > > Does anyone have any experience one way or the other that they can > share? What is your constraint strategy? I notice that the synthesis > of my designs tends to be pretty sensitive to the actual constraint > value -- devices that that synth at 19.8 ns might not at 19.9, even > though it is a "slower" design. > > Thanks! > ...Eric The place and route process for a relatively unconstained design starts with a random seed and works from there. Any change in the design or constraints can re-shape the process in an unpredictable way - like chaos. If you're seeing a lot of sensitivity to a small change in constraints it is possible that a little floorplanning will help the placement process a lot. Also if you don't meet constraints when you loosen them, try starting with a different "cost table" number (defaults to 1) or use multipass place&route. My experience with PERIOD constraints is that often loosening the constraint when possible can help to increase the final frequency of the routed design. This is especially true of multi-clock designs where the tools need to trade off one constraint against another. But even in single clock designs I've seen cases where my PERIOD constraint might be at 7.5 nS and when finished the routed design meets 7.1 nS. But if I tried to set the PERIOD to 7.1 nS the final result would not meet timing. HTH, Gabor
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