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Threads Starting Jul 2000
23579: 00/07/01: Ben: Powering XCV300
23622: 00/07/03: Tobias-Dirk Stumber: Re: Powering XCV300
23696: 00/07/05: Rick Filipkiewicz: Re: Powering XCV300
23703: 00/07/05: peter dudley: Re: Powering XCV300
23590: 00/07/01: Boogie: How much would a PCI core be worth?
23596: 00/07/02: Tom Burgess: Re: How much would a PCI core be worth?
23598: 00/07/02: Joel Kolstad: Re: How much would a PCI core be worth?
23597: 00/07/02: Peter Alfke: Remedies after the Fathers' Day Massacre
23600: 00/07/02: Simon: Re: Remedies after the Fathers' Day Massacre
23751: 00/07/06: Robert Binkley: Re: Remedies after the Fathers' Day Massacre
23757: 00/07/07: Simon: Re: Remedies after the Fathers' Day Massacre
23791: 00/07/09: Rick Filipkiewicz: Re: Remedies after the Fathers' Day Massacre
23792: 00/07/08: rickman: Re: Remedies after the Fathers' Day Massacre
23608: 00/07/02: John Larkin: Re: Remedies after the Fathers' Day Massacre
23616: 00/07/02: Peter Alfke: Re: Remedies after the Fathers' Day Massacre
23800: 00/07/10: Hal Murray: Re: Remedies after the Fathers' Day Massacre
23803: 00/07/10: rickman: Re: Remedies after the Fathers' Day Massacre
23820: 00/07/11: Scott Bilik: Re: Remedies after the Fathers' Day Massacre
23833: 00/07/12: Hal Murray: Re: Remedies after the Fathers' Day Massacre
23884: 00/07/14: Steve Rencontre: Re: Remedies after the Fathers' Day Massacre
23601: 00/07/02: Tony Burch: ANN: FPGA Proto Kits now 25% cheaper
23602: 00/07/02: <erika_uk@my-deja.com>: why???
23609: 00/07/02: John Larkin: Re: why???
23617: 00/07/03: Hal Murray: Re: why???
23658: 00/07/04: Keith R. Williams: Re: why???
23603: 00/07/02: Steve L: First time chip design. Is my roadmap correct ?
23619: 00/07/03: Nicholas Velastegui: Re: First time chip design. Is my roadmap correct ?
23604: 00/07/02: Dan: division in FPGA - help !
23623: 00/07/03: Kate Atkins: Re: division in FPGA - help !
23639: 00/07/04: <bkk411@hotmail.com>: Re: division in FPGA - help !
23787: 00/07/08: Allan Redenbaugh: Re: division in FPGA - help !
23605: 00/07/02: Bill Lenihan: BIST in FPGAs?
23606: 00/07/02: Peter Alfke: Re: BIST in FPGAs?
23607: 00/07/02: Phil Hays: Re: BIST in FPGAs?
23615: 00/07/02: Peter Alfke: Re: BIST in FPGAs?
23647: 00/07/04: rk: Re: BIST in FPGAs?
23648: 00/07/04: Greg Neff: Re: BIST in FPGAs?
23650: 00/07/04: Rickman: Re: BIST in FPGAs?
23655: 00/07/04: Phil Hays: Re: BIST in FPGAs?
23656: 00/07/04: Greg Neff: Re: BIST in FPGAs?
23667: 00/07/05: Rickman: Re: BIST in FPGAs?
23681: 00/07/05: Greg Neff: Re: BIST in FPGAs?
23682: 00/07/05: Rickman: Re: BIST in FPGAs?
23683: 00/07/05: Peter Alfke: Re: BIST in FPGAs?
23767: 00/07/07: Robert Posey: Re: BIST in FPGAs?
23770: 00/07/07: rickman: Re: BIST in FPGAs?
23773: 00/07/07: Robert Posey: Re: BIST in FPGAs?
23777: 00/07/07: rickman: Re: BIST in FPGAs?
23779: 00/07/07: Robert Posey: Re: BIST in FPGAs?
23784: 00/07/07: rk: Re: BIST in FPGAs?
23783: 00/07/07: rk: Re: BIST in FPGAs?
23708: 00/07/06: Ray Andraka: Re: BIST in FPGAs?
23715: 00/07/05: Rickman: Re: BIST in FPGAs?
23611: 00/07/02: Rickman: Re: BIST in FPGAs?
23644: 00/07/04: Etienne Racine: Re: BIST in FPGAs?
23651: 00/07/04: rk: Re: BIST in FPGAs?
23646: 00/07/04: rk: Re: BIST in FPGAs?
23674: 00/07/05: Alasdair MacLean: Re: BIST in FPGAs?
23612: 00/07/02: Dan: How can I search this newsgroup archive?
23614: 00/07/02: B. Joshua Rosen: Re: How can I search this newsgroup archive?
23620: 00/07/03: Phil Endecott: Re: How can I search this newsgroup archive?
23621: 00/07/03: <bompf@my-deja.com>: LCD-Controller
23624: 00/07/03: Utku Ozcan: Virtex DLL deskew of board clock with a clock/2
23625: 00/07/03: Utku Ozcan: addition
23664: 00/07/05: <korthner@my-deja.com>: Re: Virtex DLL deskew of board clock with a clock/2
23704: 00/07/06: Utku Ozcan: Re: Virtex DLL deskew of board clock with a clock/2
23626: 00/07/03: EKC: Altera Ships Largest PLD
23627: 00/07/03: Rickman: Re: Altera Ships Largest PLD
23643: 00/07/04: Jens Hildebrandt: Re: Altera Ships Largest PLD
23689: 00/07/05: Don Husby: Re: Altera Ships Largest PLD
23690: 00/07/05: Rickman: Re: Altera Ships Largest PLD
23698: 00/07/05: Don Husby: Re: Altera Ships Largest PLD
23712: 00/07/05: John McCluskey: ORCA4 (was Re: Altera Ships Largest PLD)
23716: 00/07/06: Rickman: Re: ORCA4 (was Re: Altera Ships Largest PLD)
23717: 00/07/06: Philip Freidin: Re: ORCA4 (was Re: Altera Ships Largest PLD)
23732: 00/07/06: Rickman: Re: ORCA4 (was Re: Altera Ships Largest PLD)
23736: 00/07/06: Don Husby: Re: ORCA4 (was Re: Altera Ships Largest PLD)
23744: 00/07/06: Rickman: Re: ORCA4 (was Re: Altera Ships Largest PLD)
23628: 00/07/03: John Larkin: Re: Altera Ships Largest PLD
23629: 00/07/04: Zoltan Kocsi: Re: Altera Ships Largest PLD
23641: 00/07/04: Nicolas Matringe: Re: Altera Ships Largest PLD
23654: 00/07/04: Jan Gray: Altera and Xilinx processor core announcements
23631: 00/07/03: Peter Elliot: Graphic LCD controller design
23711: 00/07/06: Steve Rencontre: Re: Graphic LCD controller design
23633: 00/07/04: <est0@lehigh.edu>: How to augment the output of a Xilinx lfsr in verilog??
23634: 00/07/04: Hal Murray: Re: How to augment the output of a Xilinx lfsr in verilog??
23635: 00/07/04: Peter Alfke: Re: How to augment the output of a Xilinx lfsr in verilog??
23636: 00/07/04: Peter Alfke: Re: How to augment the output of a Xilinx lfsr in verilog??
23653: 00/07/04: <est0@lehigh.edu>: Re: How to augment the output of a Xilinx lfsr in verilog??
23668: 00/07/05: Rickman: Re: How to augment the output of a Xilinx lfsr in verilog??
23702: 00/07/05: Ray Andraka: Re: How to augment the output of a Xilinx lfsr in verilog??
23638: 00/07/04: Jan Gray: on arbitrary m-cycle n-bit lfsrs
23684: 00/07/05: Jan Gray: Re: on arbitrary m-cycle n-bit lfsrs
23938: 00/07/17: JEAN NICOLLE: better than a long explanation, the LFSR testbench
23943: 00/07/17: rickman: Re: better than a long explanation, the LFSR testbench
23637: 00/07/04: <korthner@my-deja.com>: Serial Number embedded in PROM.
23649: 00/07/04: Rickman: Re: Serial Number embedded in PROM.
23662: 00/07/04: <korthner@my-deja.com>: Re: Serial Number embedded in PROM.
23670: 00/07/05: Rickman: Re: Serial Number embedded in PROM.
23685: 00/07/05: Jason T. Wright: Re: Serial Number embedded in PROM.
23687: 00/07/05: Rickman: Re: Serial Number embedded in PROM.
23672: 00/07/05: Rickman: Re: Serial Number embedded in PROM.
23665: 00/07/04: Peter Alfke: Re: Serial Number embedded in PROM.
23671: 00/07/05: Rickman: Re: Serial Number embedded in PROM.
23677: 00/07/05: dmac: Re: Serial Number embedded in PROM.
23678: 00/07/05: Etienne Racine: Re: Serial Number embedded in PROM.
23640: 00/07/04: Yekta Ayduk: 2.1i better than 1.5?
23686: 00/07/05: Jason T. Wright: Re: 2.1i better than 1.5?
23642: 00/07/04: Bernard Bertrand: search free pcb programmer FPGA or CPLD
23931: 00/07/16: Richard Erlacher: Re: search free pcb programmer FPGA or CPLD
23941: 00/07/17: Leon Heller: Re: search free pcb programmer FPGA or CPLD
23982: 00/07/19: Leon Heller: Re: search free pcb programmer FPGA or CPLD
23645: 00/07/04: SteVe: Virtex Global Set Reset
23688: 00/07/05: Andy Peters: Re: Virtex Global Set Reset
23720: 00/07/06: David Gilchrist: Re: Virtex Global Set Reset
23652: 00/07/04: SteVe: Programming Virtex with the MultiLINX cable
23659: 00/07/04: Alun: Re: Programming Virtex with the MultiLINX cable
23663: 00/07/05: <korthner@my-deja.com>: Re: Programming Virtex with the MultiLINX cable
23657: 00/07/04: <ramesh_z@my-deja.com>: silicon
23666: 00/07/05: Andrew Buckin: Help I/O pin
23669: 00/07/05: Muzaffer Kal: Spartan II PCI32 suggestions ?
23676: 00/07/05: Tobias-Dirk Stumber: Virtex-E PCI (MB with 3.3Vsignaling)
23699: 00/07/05: Rick Filipkiewicz: Re: Virtex-E PCI (MB with 3.3Vsignaling)
23713: 00/07/05: Rickman: Re: Virtex-E PCI (MB with 3.3Vsignaling)
23750: 00/07/07: Rick Filipkiewicz: Re: Virtex-E PCI (MB with 3.3Vsignaling)
23679: 00/07/05: Bernard Bertrand: help making // cable III xilinx
23680: 00/07/05: Dave Vanden Bout: tutorial on configurable system-on-chip design is available
23693: 00/07/05: Anurag Tiwari: Timing Simulation on wildforce board
23694: 00/07/05: Rickman: VHDL code for LFSR
23697: 00/07/05: Srinivasan Venkataramanan: Re: VHDL code for LFSR
23700: 00/07/05: Colin Marquardt: Re: VHDL code for LFSR
23740: 00/07/06: Andy Peters: Re: VHDL code for LFSR
23718: 00/07/06: Vikram Pasham: Re: VHDL code for LFSR
23719: 00/07/06: Vikram Pasham: Re: VHDL code for LFSR
23701: 00/07/05: Jan Decaluwe: Re: VHDL code for LFSR
23752: 00/07/07: rickman: Re: VHDL code for LFSR
23706: 00/07/06: Ray Andraka: Re: VHDL code for LFSR
23709: 00/07/06: Miloslaw Smyk: A diary of a battle: Wild-One, 2.1i and FPGA Express3.3
23710: 00/07/06: Mathew Wojko: PamDC question.
23749: 00/07/06: Stefan Ludwig: Re: PamDC question.
23885: 00/07/14: Mathew Wojko: Re: PamDC question.
23721: 00/07/06: Kai Schulze: XILINX configuration
23722: 00/07/06: wenger: Before and after configuration, are the undefined I/O ports input or output?
23765: 00/07/07: Tom Fischaber: Re: Before and after configuration, are the undefined I/O ports input or
23724: 00/07/06: Pierce Chen: 3.3v supply 2.5v chips
23725: 00/07/06: Simon Bilodeau: Problem with XC95288 using JTAG with HW-JTAG-PC
23775: 00/07/07: Alun: Re: Problem with XC95288 using JTAG with HW-JTAG-PC
23726: 00/07/06: Kai Schulze: Clock Buffer
23739: 00/07/06: Andy Peters: Re: Clock Buffer
23754: 00/07/07: Jens Hildebrandt: Re: Clock Buffer
23771: 00/07/07: Andy Peters: Re: Clock Buffer
23778: 00/07/07: rickman: Re: Clock Buffer
23780: 00/07/07: Andy Peters: Re: Clock Buffer
23796: 00/07/10: Utku Ozcan: Re: Clock Buffer
23799: 00/07/10: Jens Hildebrandt: Re: Clock Buffer
23728: 00/07/06: Johnny: IBIS model for the XCV400E
23734: 00/07/06: Austin Lesea: Re: IBIS model for the XCV400E
23729: 00/07/06: Nial Stewart: Altera's promises unfulfilled???
23738: 00/07/06: Mike H.: Re: Altera's promises unfulfilled???
23758: 00/07/07: Nial Stewart: Re: Altera's promises unfulfilled???
23759: 00/07/07: Mike H.: Re: Altera's promises unfulfilled???
23891: 00/07/14: Leon Heller: Re: Altera's promises unfulfilled???
23860: 00/07/13: Brent A. Hayhoe: Re: Altera's promises unfulfilled???
23864: 00/07/13: Nial Stewart: Re: Altera's promises unfulfilled???
24013: 00/07/21: Nial Stewart: Downloadable versions available
23735: 00/07/06: Asher Martin-CRAY: Where is the documentation on .ll files for Xilinx parts?
23737: 00/07/06: Jens Popp: Xilinx Design Flow
23798: 00/07/10: Lars Rzymianowicz: Re: Xilinx Design Flow
23742: 00/07/06: Jeff Reeve: 56 independent PN streams
23745: 00/07/06: Rickman: Re: 56 independent PN streams
23746: 00/07/06: Rickman: Re: 56 independent PN streams
23748: 00/07/06: Rickman: Re: 56 independent PN streams
23755: 00/07/07: Juan-Luis Lopez: RE: 56 independent PN streams
23760: 00/07/07: Jonas Thor: Re: 56 independent PN streams
23747: 00/07/06: Ties Bos: Q: high fanout distribution
23761: 00/07/07: Michael Boehnel: Virtex Debug
23762: 00/07/07: Christopher Malkin: calculating modulo N
23763: 00/07/07: Don Husby: Re: calculating modulo N
23774: 00/07/07: Alun: Re: calculating modulo N
23804: 00/07/10: Savekar Santosh: Re: calculating modulo N
23764: 00/07/07: Jens Popp: FPGA Express/Foundation Error 470
23776: 00/07/07: Anna Acevedo: Re: FPGA Express/Foundation Error 470
23768: 00/07/07: S.K. Sharma: Quattus Automatic clock Selection
23769: 00/07/07: Xanatos: Re: Quattus Automatic clock Selection
23781: 00/07/07: Steve Oldridge: Xilinx 6200 series data sheets
23788: 00/07/08: Dmitry Senjakin: Re: Xilinx 6200 series data sheets
23785: 00/07/08: <jmcdonald@eg3.com>: FPGA Internet Resources - Updated
23786: 00/07/09: webber: Where can I get Altera MAX+Plus2 9.x software?
23789: 00/07/08: Carlhermann Schlehaus: Re: Where can I get Altera MAX+Plus2 9.x software?
23790: 00/07/08: alastairallen99: PhD studentship: UK
23793: 00/07/09: <wqjchn@sdjxtrwhsh.gov>: Nuke the Competition!
23794: 00/07/09: Andrew Buckin: I/O Help
23795: 00/07/09: Eric L: Xilinx Data memory
23814: 00/07/10: Marc Baker: Re: Xilinx Data memory
23797: 00/07/10: Bill Lenihan: JTAG headers
23809: 00/07/10: G. Hobson Frater: Re: JTAG headers
23819: 00/07/11: Leon Heller: Re: JTAG headers
23801: 00/07/10: Jens Popp: Xilinx XC4000E / Renoir
23836: 00/07/12: Chris Shenton: Re: Xilinx XC4000E / Renoir
23802: 00/07/10: christelle: Quartus
23872: 00/07/13: Alan: Re: Quartus
23963: 00/07/18: Jaap H. Mol: Re: Quartus
23805: 00/07/10: rickman: Xilinx buys LavaLogic
23811: 00/07/11: Jim Granville: Re: Xilinx buys LavaLogic
23818: 00/07/10: Joel Kolstad: Re: Xilinx buys LavaLogic
23828: 00/07/12: Ray Andraka: Re: Xilinx buys LavaLogic
23830: 00/07/12: Jan Gray: C++/Java generators vs. synthesizers
23831: 00/07/12: rickman: Re: C++/Java generators vs. synthesizers
23835: 00/07/12: Hal Murray: Re: C++/Java generators vs. synthesizers
23858: 00/07/12: rickman: Re: C++/Java generators vs. synthesizers
23846: 00/07/12: Mike Treseler: Re: C++/Java generators vs. synthesizers
23867: 00/07/13: Jan Gray: Re: C++/Java generators vs. synthesizers
23847: 00/07/12: Nicholas C. Weaver: Re: C++/Java generators vs. synthesizers
23851: 00/07/12: Jan Gray: Re: C++/Java generators vs. synthesizers
23806: 00/07/10: Michael Hopey: AHDL question
23863: 00/07/13: Nikolay Rognlien: Re: AHDL question
23807: 00/07/10: Ottwald Holler: XC2018 development system xact5 or xact6 sale?
23808: 00/07/10: Austin Lesea: Re: XC2018 development system xact5 or xact6 sale?
23812: 00/07/10: rickman: Re: XC2018 development system xact5 or xact6 sale?
23834: 00/07/12: Tony Burch: Re: XC2018 development system xact5 or xact6 sale?
23877: 00/07/13: Ottwald Holler: Re: XC2018 development system xact5 or xact6 sale?
23878: 00/07/13: rickman: Re: XC2018 development system xact5 or xact6 sale?
23926: 00/07/15: Peter: Re: XC2018 development system xact5 or xact6 sale?
23948: 00/07/17: Ray Andraka: Re: XC2018 development system xact5 or xact6 sale?
23810: 00/07/10: John Larkin: PCI to dual-port memory
23813: 00/07/10: sriley: phase lock different frequencies
23815: 00/07/10: Muzaffer Kal: Re: phase lock different frequencies
23817: 00/07/11: Jim Granville: Re: phase lock different frequencies
24060: 00/07/25: Fred Skalka: Re: phase lock different frequencies
23821: 00/07/11: Jo: Electronic Design Automation - UK
23822: 00/07/11: <khanzode@yahoo.com>: Timing Simulation for Alter FPGAs
23824: 00/07/11: Muzaffer Kal: Re: Timing Simulation for Alter FPGAs
23845: 00/07/12: S.K. Sharma: Re: Timing Simulation for Alter FPGAs
23823: 00/07/11: <khanzode@yahoo.com>: Timing Simulation for Alter FPGAs
23871: 00/07/13: darrell mcginnis: Re: Timing Simulation for Alter FPGAs
23837: 00/07/12: Franz Hollerer: Boundary-Scan Tests with JTAG Technologies Tools
23856: 00/07/12: rickman: Re: Boundary-Scan Tests with JTAG Technologies Tools
23859: 00/07/13: Franz Hollerer: Re: Boundary-Scan Tests with JTAG Technologies Tools
23866: 00/07/13: rickman: Re: Boundary-Scan Tests with JTAG Technologies Tools
23889: 00/07/14: Franz Hollerer: Re: Boundary-Scan Tests with JTAG Technologies Tools
23909: 00/07/14: Mike Treseler: Re: Boundary-Scan Tests with JTAG Technologies Tools
23911: 00/07/14: rickman: Re: Boundary-Scan Tests with JTAG Technologies Tools
23915: 00/07/14: Mike Treseler: Re: Boundary-Scan Tests with JTAG Technologies Tools
23919: 00/07/14: rickman: Re: Boundary-Scan Tests with JTAG Technologies Tools
23925: 00/07/15: Alain Cloet: Re: Boundary-Scan Tests with JTAG Technologies Tools
23862: 00/07/13: Etienne Racine: Re: Boundary-Scan Tests with JTAG Technologies Tools
23865: 00/07/13: rickman: Re: Boundary-Scan Tests with JTAG Technologies Tools
23873: 00/07/13: Alain Cloet: Re: Boundary-Scan Tests with JTAG Technologies Tools
23923: 00/07/15: Gary Watson: Re: Boundary-Scan Tests with JTAG Technologies Tools
23838: 00/07/12: Renzo Marcanzin: newbi question
23839: 00/07/12: Dave Vanden Bout: tutorial on configurable system-on-chip design is available
23840: 00/07/12: <rlm@kauai.mv.com>: FS: domain name: AsicGuru.com
23841: 00/07/12: Matt Gavin: hold time errors in FPGA's ?
23843: 00/07/12: Bob Perlman: Re: hold time errors in FPGA's ?
23844: 00/07/12: Matt Gavin: Re: hold time errors in FPGA's ?
23857: 00/07/12: rickman: Re: hold time errors in FPGA's ?
23918: 00/07/14: Matt Gavin: Re: hold time errors in FPGA's ?
23927: 00/07/15: rickman: Re: hold time errors in FPGA's ?
23944: 00/07/17: Greg Neff: Re: hold time errors in FPGA's ?
23875: 00/07/13: Jason T. Wright: Re: hold time errors in FPGA's ?
23848: 00/07/12: Greg Neff: Re: hold time errors in FPGA's ?
23849: 00/07/12: Rick Filipkiewicz: Re: hold time errors in FPGA's ?
23842: 00/07/12: md: DESIGNERS WANTED
23850: 00/07/12: Steve Logue: How may ns should a 32-bit add take ?
23852: 00/07/13: Dmitry Senjakin: Re: How may ns should a 32-bit add take ?
23853: 00/07/13: saffary: SerialProm programmer
23961: 00/07/18: Lino de Martin: Re: SerialProm programmer
23855: 00/07/13: Don Husby: Silicon Valley Housing Nightmare?
23882: 00/07/13: Richard F. Man: Re: Silicon Valley Housing Nightmare?
23914: 00/07/14: Stuart Clubb: Re: Silicon Valley Housing Nightmare?
23921: 00/07/14: Anna Acevedo: Re: Silicon Valley Housing Nightmare?
24024: 00/07/24: K.Orthner: Re: Silicon Valley Housing Nightmare?
24041: 00/07/24: Andy Peters: Re: Silicon Valley Housing Nightmare?
24063: 00/07/25: Joseph H Allen: Re: Silicon Valley Housing Nightmare?
24071: 00/07/26: Ray Andraka: Re: Silicon Valley Housing Nightmare?
23924: 00/07/15: B. Joshua Rosen: Re: Silicon Valley Housing Nightmare?
23957: 00/07/18: Scott Bilik: Re: Silicon Valley Housing Nightmare?
23932: 00/07/16: <erika_uk@my-deja.com>: Re: Silicon Valley Housing Nightmare?
23979: 00/07/19: Don Husby: Summary: Re: Silicon Valley Housing Nightmare?
23984: 00/07/19: Andy Peters: Re: Summary: Re: Silicon Valley Housing Nightmare?
24004: 00/07/20: Don Husby: Re: Summary: Re: Silicon Valley Housing Nightmare?
23861: 00/07/13: Daning Ren / 30066: Functional Simulation for Xilinx PCI Example Ping
23870: 00/07/13: Eric Crabill: Re: Functional Simulation for Xilinx PCI Example Ping
23868: 00/07/14: kamal: Configuration Cache
23869: 00/07/13: Gary Watson: Init time of Xilinx Virtex / Spartan II
23874: 00/07/13: rickman: Re: Init time of Xilinx Virtex / Spartan II
23892: 00/07/14: Bill Blyth: Re: Init time of Xilinx Virtex / Spartan II
23901: 00/07/14: rickman: Re: Init time of Xilinx Virtex / Spartan II
23902: 00/07/14: Bill Blyth: Re: Init time of Xilinx Virtex / Spartan II
23910: 00/07/14: rickman: Re: Init time of Xilinx Virtex / Spartan II
23876: 00/07/13: Joe Lavelle: Category : Simple UART in VHDL
23880: 00/07/13: Paul Smith: Dual Port RAM
23886: 00/07/14: <klaro@my-deja.com>: Re: Dual Port RAM
23905: 00/07/14: Paul Smith: Re: Dual Port RAM
23908: 00/07/14: rickman: Re: Dual Port RAM
23916: 00/07/14: Frank Bemelman: Re: Dual Port RAM
23917: 00/07/14: Muzaffer Kal: Re: Dual Port RAM
23965: 00/07/18: Philip Freidin: Re: Dual Port RAM
23972: 00/07/19: rickman: Re: Dual Port RAM
23912: 00/07/14: Paul Smith: Re: Dual Port RAM
23920: 00/07/14: rickman: Re: Dual Port RAM
23974: 00/07/19: Ian J. Smith: Re: Dual Port RAM
23987: 00/07/19: Paul Smith: Re: Dual Port RAM
23881: 00/07/13: A. Alsolaim: HELP!! Nallatech Virtex Board.
24012: 00/07/21: Paul Dunn: RE: HELP!! Nallatech Virtex Board.
23883: 00/07/14: Arthur F. Ross: i2c VHDL code
23887: 00/07/14: Tobias Stumber: Re: i2c VHDL code
23888: 00/07/14: Andrew Buckin: IDE VHDL
23893: 00/07/14: alastairallen99: PhD studentship: Aberdeen, UK
23894: 00/07/14: cheng: Help FFT core!
23895: 00/07/14: Nick Young: FPGA Intro
23896: 00/07/14: Dave Vanden Bout: Re: FPGA Intro
23933: 00/07/16: Jamil Khatib: Re: FPGA Intro
23952: 00/07/18: Tony Burch: Re: FPGA Intro
23897: 00/07/14: Mark Hillers: synopsys 2000.05 loses control of virtexBlockRam
23898: 00/07/14: Michael Barr: Embedded Systems Resources
23899: 00/07/14: Sreedhar Sampath: Timing Analysis
23913: 00/07/14: rickman: Re: Timing Analysis
23900: 00/07/14: <matt_hocker@yahoo.com>: ARC ARChitect
23903: 00/07/14: Jasper Hendriks: Need help with Maxplus and large bus multiplexer
23904: 00/07/14: Valeri Serebrianski: Re: Need help with Maxplus and large bus multiplexer
23906: 00/07/14: Valeri Serebrianski: Re: Need help with Maxplus and large bus multiplexer
23907: 00/07/14: Valeri Serebrianski: Re: Need help with Maxplus and large bus multiplexer
23922: 00/07/15: Jens Popp: Renoir/Update Symbol from HDL
23940: 00/07/17: Yacine EL KOLLI: Re: Renoir/Update Symbol from HDL
23930: 00/07/15: Muzaffer Kal: jtag connections for Spartan II on PCI ?
24008: 00/07/20: mike johnson: Re: jtag connections for Spartan II on PCI ?
23939: 00/07/16: Richard B. Katz: 2000 MAPLD International Conference - Program and Registration
23942: 00/07/17: Keith Wootten: Xilinx Foundation 2.1 Run Times
23951: 00/07/18: Keith R. Williams: Re: Xilinx Foundation 2.1 Run Times
23946: 00/07/17: MikeT: Atmel 1508 EPLD's
23947: 00/07/17: <martin@gubbins.demon.co.uk>: Altera fitter woes
23950: 00/07/17: Ken McElvain: Re: Altera fitter woes
23954: 00/07/18: <martinthompson@my-deja.com>: Re: Altera fitter woes
23955: 00/07/18: <martinthompson@my-deja.com>: Re: Altera fitter woes
23958: 00/07/18: Eric Pearson: Re: Altera fitter woes
23960: 00/07/18: Eric Pearson: Re: Altera fitter woes
23962: 00/07/18: Martin: Re: Altera fitter woes
23949: 00/07/17: Gordon Stoll: Java API for Boundary Scan (JTAG)
23953: 00/07/18: Andreas Wüstefeld: download to a xilinx fpga
23967: 00/07/19: Tony Burch: Re: download to a xilinx fpga
23956: 00/07/18: Christof Paar: CHES 2000 Program
23959: 00/07/18: Lino de Martin: xilinx prom 17s05lvc Need programming specification
23964: 00/07/18: John Cooley: 104 Page Collective DAC'00 Trip Report Up
23968: 00/07/19: Robert Carney: Re: 104 Page Collective DAC'00 Trip Report Up
24006: 00/07/20: John Cooley: Re: 104 Page Collective DAC'00 Trip Report Up
24007: 00/07/20: Raman Narayan: Re: 104 Page Collective DAC'00 Trip Report Up
23966: 00/07/18: EKC: FPGA Conferences
23969: 00/07/19: Simmler Harald: Re: FPGA Conferences
23970: 00/07/19: Simmler Harald: Re: FPGA Conferences
23976: 00/07/19: vikramp: Re: FPGA Conferences
24002: 00/07/20: Richard B. Katz: Re: FPGA Conferences
23971: 00/07/19: David Dart: IP CORE, 8250 core with 16byte fifo which only uses 100CLB's
24046: 00/07/24: Ray Andraka: Re: IP CORE, 8250 core with 16byte fifo which only uses 100CLB's
23973: 00/07/19: Randy Given: Experts-Exchange
23975: 00/07/19: Dave Vanden Bout: tutorial on configurable system-on-chip design is available
23977: 00/07/19: <cjfocf@mnet.com>: Re: I found it for you 6334
23978: 00/07/19: Zhibin Dai: Fundation serial & Alliance serial
23983: 00/07/19: rickman: Re: Fundation serial & Alliance serial
23980: 00/07/19: Dick Maio: FPGAs in AC Magnetic Field
23981: 00/07/19: Greg Neff: Re: FPGAs in AC Magnetic Field
23988: 00/07/19: Austin Lesea: Re: FPGAs in AC Magnetic Field
23989: 00/07/19: Alun: Re: FPGAs in AC Magnetic Field
23985: 00/07/19: Mike Trowers: Erasing PLD's
23986: 00/07/19: Mike Trowers: Re: Erasing PLD's
23991: 00/07/19: Mike Trowers: Re: Erasing PLD's
23990: 00/07/19: Jerry English: synthesizer memory useage
23993: 00/07/20: Pratip Mukherjee: New Xilinx Student Edition
24009: 00/07/20: Anna Acevedo: Re: New Xilinx Student Edition
24048: 00/07/24: Ray Andraka: Re: New Xilinx Student Edition
24050: 00/07/24: Dave Vanden Bout: Re: New Xilinx Student Edition
24052: 00/07/24: Pratip Mukherjee: Re: New Xilinx Student Edition
23996: 00/07/20: Tom Vrankar: Q: PAL22V10 JEDEC file-toVHDL translators?
23997: 00/07/20: rickman: Re: Q: PAL22V10 JEDEC file-toVHDL translators?
24001: 00/07/20: <rob_dickinson@my-deja.com>: Re: Q: PAL22V10 JEDEC file-toVHDL translators?
24026: 00/07/24: Jim Granville: Re: Q: PAL22V10 JEDEC file-toVHDL translators?
24051: 00/07/24: Greg Neff: Re: Q: PAL22V10 JEDEC file-toVHDL translators?
24049: 00/07/24: Ray Andraka: Re: Q: PAL22V10 JEDEC file-toVHDL translators?
23998: 00/07/20: Bill Lenihan: Re: Warning! -- SONY SUBSTANDARD SERVICE
23999: 00/07/20: Leon Heller: DIY ByteBlaster equivalent
24000: 00/07/20: Michael Schmid: Foundation 3.1i in Germany
24005: 00/07/20: <erika_uk@my-deja.com>: Re: Foundation 3.1i in Germany
24010: 00/07/21: Michael Schmid: Re: Foundation 3.1i in Germany
24011: 00/07/21: <eml@riverside-machines.com.NOSPAM>: Re: Foundation 3.1i in Germany
24003: 00/07/20: <ggd@reivax.com.br>: IRIG decoder and accurate time
24014: 00/07/21: <qwerty@scottfamily.cc>: Real time sims with NC-Verilog
24023: 00/07/24: K.Orthner: Re: Real time sims with NC-Verilog
24034: 00/07/24: Stephen Lohning: Re: Real time sims with NC-Verilog
24054: 00/07/25: Rick Filipkiewicz: Re: Real time sims with NC-Verilog
24326: 00/08/04: <qwerty@scottfamily.cc>: Re: Real time sims with NC-Verilog
24015: 00/07/21: mcb: AM85C30 SCC probs
24016: 00/07/22: Jonas Thor: 17 clocks in a Virtex
24017: 00/07/22: Andy Holt: Re: 17 clocks in a Virtex
24033: 00/07/24: Jonas Thor: Re: 17 clocks in a Virtex
24029: 00/07/24: Michael Schmid: Re: 17 clocks in a Virtex
24053: 00/07/25: Ray Andraka: Re: 17 clocks in a Virtex
24470: 00/08/10: Ben Franchuk: Re: 17 clocks in a Virtex
24474: 00/08/10: Emil Blaschek: Re: 17 clocks in a Virtex
24018: 00/07/23: Márcio Longaray: Need MP3 decoder souce
24019: 00/07/23: Pasquale Corsonello: Announcement: New high-speed low-power adders
24030: 00/07/24: Pasquale Corsonello: Re: Announcement: New high-speed low-power adders
24020: 00/07/23: <channing@21cn.com>: Routing Resources for Xilinx BlockRAM
24038: 00/07/24: <seb30@my-deja.com>: Re: Routing Resources for Xilinx BlockRAM
24044: 00/07/24: Ray Andraka: Re: Routing Resources for Xilinx BlockRAM
24021: 00/07/23: <channing@21cn.com>: Routing Resources for Xilinx BlockRAM
24042: 00/07/24: Ray Andraka: Re: Routing Resources for Xilinx BlockRAM
24055: 00/07/25: <channing@my-deja.com>: Re: Routing Resources for Xilinx BlockRAM
24069: 00/07/26: Ray Andraka: Re: Routing Resources for Xilinx BlockRAM
24022: 00/07/24: K.Orthner: Virtex DLL problem.
24025: 00/07/24: =?iso-2022-jp?B?GyRCMEIwZhsoQiAbJEI3chsoQg==?=: Re: Virtex DLL problem.
24035: 00/07/24: K.Orthner: Re: Virtex DLL problem.
24032: 00/07/24: Kate Atkins: Re: Virtex DLL problem.
24201: 00/07/29: Hal Murray: Re: Virtex DLL problem.
24027: 00/07/24: K.Orthner: Xilinx Core Generators.
24028: 00/07/24: <felix_bertram@my-deja.com>: Re: Xilinx Core Generators.
24075: 00/07/26: K.Orthner: Re: Xilinx Core Generators.
24085: 00/07/26: <felix_bertram@my-deja.com>: Re: Xilinx Core Generators.
24106: 00/07/27: K.Orthner: Re: Xilinx Core Generators.
24119: 00/07/27: <felix_bertram@my-deja.com>: Re: Xilinx Core Generators.
24031: 00/07/24: Nicolas Matringe: Re: Xilinx Core Generators.
24036: 00/07/24: <erika_uk@my-deja.com>: jedec ???
24040: 00/07/24: Greg Neff: Re: jedec ???
24037: 00/07/24: <erika_uk@my-deja.com>: XC4000 select ram
24045: 00/07/24: Ray Andraka: Re: XC4000 select ram
24266: 00/08/02: <yuryws@banet.net>: Re: XC4000 select ram
24039: 00/07/24: <seb30@my-deja.com>: CLKDLLE using VirtexE device.
24043: 00/07/24: Russell Tessier: 2nd Call for Papers: FPGA'2001
24056: 00/07/25: Leumann Robert: Spartan II Pin
24059: 00/07/25: rickman: Re: Spartan II Pin
24062: 00/07/25: darrell mcginnis: Re: Spartan II Pin
24064: 00/07/25: Philip Freidin: Re: Spartan II Pin
24070: 00/07/26: Ray Andraka: Re: Spartan II Pin
24057: 00/07/25: K.Orthner: Xilinx "MUX_OP not inferred" error.
24065: 00/07/25: Winzker: Re: Xilinx "MUX_OP not inferred" error.
24068: 00/07/26: K.Orthner: Re: Xilinx "MUX_OP not inferred" error.
24074: 00/07/26: rickman: Re: Xilinx "MUX_OP not inferred" error.
24079: 00/07/26: K.Orthner: Re: Xilinx "MUX_OP not inferred" error.
24087: 00/07/26: rickman: Re: Xilinx "MUX_OP not inferred" error.
24107: 00/07/27: K.Orthner: Re: Xilinx "MUX_OP not inferred" error.
24103: 00/07/26: Andy Peters: Re: Xilinx "MUX_OP not inferred" error.
24058: 00/07/25: <rob_dickinson@my-deja.com>: Re: EASY MONEY- NOT A SCAM!!!!!!!!!!!!!!
24061: 00/07/25: Fred Skalka: Category : Fndtn 3.1 compatability
24067: 00/07/25: peter dudley: Power PC with Xilinx - what do you think?
24076: 00/07/26: Andreas Doering: Re: Power PC with Xilinx - what do you think?
24091: 00/07/26: Steve Casselman: Re: Power PC with Xilinx - what do you think?
24093: 00/07/26: Nicholas C. Weaver: Re: Power PC with Xilinx - what do you think?
24198: 00/07/28: Joel Kolstad: Re: Power PC with Xilinx - what do you think?
24077: 00/07/26: Tim Forcer: ANNOUNCE: Workshop on Embedded Systems & Hardware/Software co-design
24078: 00/07/26: Jamil Khatib: Arithmetic Operators
24128: 00/07/27: Ernest Jamro: Re: Arithmetic Operators
24196: 00/07/28: Joel Kolstad: Re: Arithmetic Operators
24080: 00/07/26: Isidro Urriza: Pad trireg in XLA FPGA
24098: 00/07/26: Andy Peters: Re: Pad trireg in XLA FPGA
24100: 00/07/26: rickman: Re: Pad trireg in XLA FPGA
24102: 00/07/26: Andy Peters: Re: Pad trireg in XLA FPGA
24108: 00/07/26: rickman: Re: Pad trireg in XLA FPGA
24140: 00/07/27: Andy Peters: Re: Pad trireg in XLA FPGA
24144: 00/07/27: rickman: Re: Pad trireg in XLA FPGA (beating a horse to death)
24172: 00/07/28: <eml@riverside-machines.com.NOSPAM>: Re: Pad trireg in XLA FPGA (beating a horse to death)
24177: 00/07/28: rickman: Re: Pad trireg in XLA FPGA (beating a horse to death)
24142: 00/07/27: Andy Peters: Re: Pad trireg in XLA FPGA
24171: 00/07/28: <eml@riverside-machines.com.NOSPAM>: Re: Pad trireg in XLA FPGA
24112: 00/07/27: Ray Andraka: Re: Pad trireg in XLA FPGA
24081: 00/07/26: <erika_uk@my-deja.com>: F3.1 in Great Britain
24086: 00/07/26: Henryk Cieslak: Re: F3.1 in Great Britain
24082: 00/07/26: Dave Vanden Bout: tutorial on configurable system-on-chip design is available
24083: 00/07/26: Lewin A.R.W. Edwards: Re: tutorial on configurable system-on-chip design is available
24084: 00/07/26: Jamil Khatib: Variable shifting
24089: 00/07/26: rickman: Re: Variable shifting
24092: 00/07/26: Ray Andraka: Re: Variable shifting
24095: 00/07/26: Aki M Suihkonen: Re: Variable shifting
24110: 00/07/27: Ray Andraka: Re: Variable shifting
24097: 00/07/26: rickman: Re: Variable shifting
24099: 00/07/26: Gilbert H. Herbeck: Re: Variable shifting
24101: 00/07/26: rickman: Re: Variable shifting
24104: 00/07/27: Gilbert H. Herbeck: Re: Variable shifting
24109: 00/07/26: rickman: Re: Variable shifting
24111: 00/07/27: Ray Andraka: Re: Variable shifting
24113: 00/07/26: rickman: Re: Variable shifting
24148: 00/07/27: Ray Andraka: Re: Variable shifting
24165: 00/07/28: rickman: Re: Variable shifting
24189: 00/07/29: Ray Andraka: Re: Variable shifting
24197: 00/07/28: rickman: Re: Variable shifting
24200: 00/07/29: Ray Andraka: Re: Variable shifting
24205: 00/07/29: rickman: Re: Variable shifting
24208: 00/07/29: Ray Andraka: Re: Variable shifting
24096: 00/07/26: Hal Murray: Re: Variable shifting
24090: 00/07/26: nullandvoid: Re: Variable shifting
24127: 00/07/27: Nial Stewart: Re: Variable shifting
24134: 00/07/27: nullandvoid: Re: Variable shifting
24235: 00/07/31: Jamil Khatib: Re: Variable shifting
24094: 00/07/26: Jerry English: Re: Variable shifting
24265: 00/08/01: <yuryws@banet.net>: Re: Variable shifting
24088: 00/07/26: Steven Derrien: Retiming for Virtex with FC2
24105: 00/07/26: Arrigo Benedetti: Re: Retiming for Virtex with FC2
24114: 00/07/27: MK Yap: Which one is good coding style?
24115: 00/07/27: rickman: Re: Which one is good coding style?
24124: 00/07/27: K.Orthner: Re: Which one is good coding style?
24182: 00/07/28: Steve Rencontre: OT: was: Re: Which one is good coding style?
24213: 00/07/30: K. Orthner: Re: OT: was: Re: Which one is good coding style?
24240: 00/07/31: Steve Rencontre: Re: OT: was: Re: Which one is good coding style?
24222: 00/07/30: Andrew Cannon: OT: was Re: Which one is good coding style?
24225: 00/07/30: Keith R. Williams: Re: OT: was Re: Which one is good coding style?
24232: 00/07/31: Andrew Cannon: Re: OT: was Re: Which one is good coding style?
24243: 00/07/31: <hiennguyen@my-deja.com>: Re: OT: was Re: Which one is good coding style?
24246: 00/08/01: Keith R. Williams: Re: OT: was Re: Which one is good coding style?
24245: 00/08/01: Keith R. Williams: Re: OT: was Re: Which one is good coding style?
24120: 00/07/27: MK Yap: Re: Which one is good coding style?
24121: 00/07/27: Renaud Pacalet: Re: Which one is good coding style?
24122: 00/07/27: MK Yap: Re: Which one is good coding style?
24123: 00/07/27: Renaud Pacalet: Re: Which one is good coding style?
24129: 00/07/27: rickman: Re: Which one is good coding style?
24141: 00/07/27: Andrew MacCormack: Re: Which one is good coding style?
24170: 00/07/28: <eml@riverside-machines.com.NOSPAM>: Re: Which one is good coding style?
24139: 00/07/27: Andy Peters: Re: Which one is good coding style?
24185: 00/07/28: Andy Peters: Re: Which one is good coding style?
24187: 00/07/28: rickman: Re: Which one is good coding style?
24214: 00/07/30: K. Orthner: Re: Which one is good coding style?
24218: 00/07/30: Peter Alfke: Re: Which one is good coding style?
24195: 00/07/29: K.Orthner: Re: Which one is good coding style?
24116: 00/07/27: rickman: Viewlogic Licencing
24131: 00/07/27: Greg Neff: Re: Viewlogic Licencing
24160: 00/07/28: rickman: Re: Viewlogic Licencing
24202: 00/07/29: rk: Re: Viewlogic Licencing
24206: 00/07/29: rickman: Re: Viewlogic Licencing
24228: 00/07/30: rk: Re: Viewlogic Licencing
24229: 00/07/30: rickman: Re: Viewlogic Licencing
24236: 00/07/31: Ray Andraka: Re: Viewlogic Licencing
24210: 00/07/30: Austin Franklin: Re: Viewlogic Licencing
24211: 00/07/30: rickman: Re: Viewlogic Licencing
24212: 00/07/30: rickman: Re: Viewlogic Licensing
24221: 00/07/30: Ray Andraka: Re: Viewlogic Licensing
24226: 00/07/30: rickman: Re: Viewlogic Licensing
24286: 00/08/02: rickman: Re: Viewlogic Licensing
24290: 00/08/02: Ray Andraka: Re: Viewlogic Licensing
24329: 00/08/04: Austin Franklin: Re: Viewlogic Licensing
24334: 00/08/04: rickman: Re: Viewlogic Licensing
24459: 00/08/09: Greg Neff: Re: Viewlogic Licencing
24269: 00/08/01: Philip Freidin: Re: Viewlogic Licencing
24275: 00/08/02: rickman: Re: Viewlogic Licencing
24319: 00/08/03: Don Husby: Re: Viewlogic Licencing
24331: 00/08/03: rickman: Re: Viewlogic Licencing
24117: 00/07/27: Richard Meester: Crossbar Switch.
24118: 00/07/27: K.Orthner: End of my rope.
24126: 00/07/27: Jerry English: Re: End of my rope.
24320: 00/08/03: sriley: Re: End of my rope.
24324: 00/08/04: K. Orthner: Re: End of my rope.
24125: 00/07/27: Leumann Robert: Spartan-II power consumption
24130: 00/07/27: K.Orthner: Re: Spartan-II power consumption
24132: 00/07/27: rickman: Re: Spartan-II power consumption
24137: 00/07/27: Greg Neff: Re: Spartan-II power consumption
24143: 00/07/27: rickman: Re: Spartan-II power consumption
24152: 00/07/27: Greg Neff: Re: Spartan-II power consumption
24157: 00/07/27: Bryan Williams: Re: Spartan-II power consumption
24161: 00/07/28: rickman: Re: Spartan-II power consumption
24194: 00/07/29: K.Orthner: Re: Spartan-II power consumption
24149: 00/07/27: Simon: Re: Spartan-II power consumption
24133: 00/07/27: Seb C: Implementation
24135: 00/07/27: Nicolas Matringe: Re: Implementation
24150: 00/07/27: Ray Andraka: Re: Implementation
24136: 00/07/27: <channing@my-deja.com>: Question of Virtex DLL
24158: 00/07/27: Ben Sanchez: Re: Question of Virtex DLL
24179: 00/07/28: Ben Sanchez: Re: Question of Virtex DLL
24199: 00/07/29: K.Orthner: Re: Question of Virtex DLL
24192: 00/07/29: K.Orthner: Re: Question of Virtex DLL
24138: 00/07/27: Daixun Zheng: implementation problem of Foundation 2.1i
24163: 00/07/28: <felix_bertram@my-deja.com>: Re: implementation problem of Foundation 2.1i
24164: 00/07/28: Klaus Falser: Re: implementation problem of Foundation 2.1i
24191: 00/07/29: K.Orthner: Re: implementation problem of Foundation 2.1i
24145: 00/07/27: Vicente Marti: RE: XCS05XL de Xilinx
24146: 00/07/27: Vicente Marti: RE: XCS05XL de Xilinx
24156: 00/07/27: Pablo Bleyer Kocik: Re: XCS05XL de Xilinx
24147: 00/07/27: myke hats: 2 bios
24151: 00/07/27: Alun: Re: Ya tengo mi correo @barcelona.com 4982
24153: 00/07/27: Ben Sanchez: LFSR as a divider
24154: 00/07/28: Jonas Thor: Re: LFSR as a divider
24155: 00/07/28: Jonas Thor: Re: LFSR as a divider
24162: 00/07/28: rickman: Re: LFSR as a divider
24166: 00/07/28: K.Orthner: Re: LFSR as a divider
24167: 00/07/28: rickman: Re: LFSR as a divider
24184: 00/07/28: Ben Sanchez: Re: LFSR as a divider
24180: 00/07/28: Ben Sanchez: Re: LFSR as a divider
24181: 00/07/28: rickman: Re: LFSR as a divider
24193: 00/07/29: Ray Andraka: Re: LFSR as a divider
24190: 00/07/29: K.Orthner: Re: LFSR as a divider
24216: 00/07/30: <erika_uk@my-deja.com>: Re: LFSR as a divider
24217: 00/07/30: Peter Alfke: Re: LFSR as a divider
24220: 00/07/30: Ray Andraka: Re: LFSR as a divider
24159: 00/07/27: Raj B Krishnamurthy: compact PCI Xilinx virtex FPGA card
24168: 00/07/28: Franz Hollerer: JTAG Technologies Boundary-Scan Test
24169: 00/07/28: John Chambers: 5V Lattice 1032E and 3.3V compatability
24345: 00/08/04: Helmut Juchems: Re: 5V Lattice 1032E and 3.3V compatability
24173: 00/07/28: Klaus Falser: FPGAExpress fe_shell and FSM encoding
24174: 00/07/28: Dave Vanden Bout: Re: FPGAExpress fe_shell and FSM encoding
24175: 00/07/28: Klaus Falser: Re: FPGAExpress fe_shell and FSM encoding
24178: 00/07/28: Dave Vanden Bout: Re: FPGAExpress fe_shell and FSM encoding
24176: 00/07/28: Hans: Foreign generated EDIF file in Foundation 2.1i
24224: 00/07/31: Rick Filipkiewicz: Re: Foreign generated EDIF file in Foundation 2.1i
24183: 00/07/28: Stuart J Adams: alternatives to costly FPGA config proms ??
24186: 00/07/28: Dave Vanden Bout: Re: alternatives to costly FPGA config proms ??
24239: 00/07/31: Robert Posey: Re: alternatives to costly FPGA config proms ??
24188: 00/07/28: Paul Smart: For Sale: XC17128 serial proms
24204: 00/07/29: Laurent Gauch: Spartan-II / Virtex-E / DC linear regulators
24209: 00/07/29: Peter Alfke: Re: Spartan-II / Virtex-E / DC linear regulators
24233: 00/07/31: Michael J. Kelly: Re: Spartan-II / Virtex-E / DC linear regulators
24237: 00/07/31: Ray Andraka: Re: Spartan-II / Virtex-E / DC linear regulators
24207: 00/07/29: <jesse@jumboprawn.net>: QuickLogic programmer bits for sale
24215: 00/07/30: K. Orthner: Free-running Oscillator.
24230: 00/07/31: Nicolas Matringe: Re: Free-running Oscillator.
24219: 00/07/30: Alun: Virtex SelectMAP download from CPU problem
24227: 00/07/30: rickman: Re: Virtex SelectMAP download from CPU problem
24223: 00/07/30: Bernardino León: Look-up tables in Altera
24241: 00/07/31: Eric Pearson: Re: Look-up tables in Altera
24253: 00/08/01: Bernardino León: RE: Look-up tables in Altera
24256: 00/08/01: Eric Pearson: Re: Look-up tables in Altera
24259: 00/08/01: Bernardino León: RE: Look-up tables in Altera
24261: 00/08/01: Ray Andraka: Re: Look-up tables in Altera
24264: 00/08/01: Eric Pearson: Re: Look-up tables in Altera
24231: 00/07/31: kctang: _ newbie want to know FPGA
24234: 00/07/31: seamus: Virtex DLL and external clocks
24244: 00/07/31: Ben Sanchez: Re: Virtex DLL and external clocks
24247: 00/08/01: rickman: Re: Virtex DLL and external clocks
24254: 00/08/01: Ben Sanchez: Re: Virtex DLL and external clocks
24238: 00/07/31: <erika_uk@my-deja.com>: tbuf
24248: 00/08/01: rickman: Re: tbuf
24274: 00/08/02: Domagoj: Re: tbuf
24432: 00/08/08: Andrew Ince: Re: tbuf
24488: 00/08/10: Domagoj: Re: tbuf
24512: 00/08/11: Andrew Ince: Re: tbuf
24548: 00/08/13: Keith R. Williams: Re: tbuf
24267: 00/08/02: <yuryws@banet.net>: Re: tbuf
24306: 00/08/03: <eml@riverside-machines.com.NOSPAM>: Re: tbuf
24311: 00/08/03: rickman: Re: tbuf
24242: 00/07/31: Austin Franklin: QuickLogic PCI/FPGA chip (QL5064)...experiences?
24255: 00/08/01: Steve Rencontre: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
24287: 00/08/02: Wayne: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
24317: 00/08/03: Steve Rencontre: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
24302: 00/08/03: Zoltan Kocsi: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
24257: 00/08/01: Richard Meester: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
24262: 00/08/02: Austin Franklin: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
24273: 00/08/02: Mark Korsloot: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
24310: 00/08/03: Austin Franklin: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
24539: 00/08/12: Magnus Homann: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
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