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Threads Starting Nov 2002
49105: 02/11/01: <skyhawk172L@attbi.com>: XC18VXX PROM Corruption
49106: 02/11/01: Jim Granville: Re: XC18VXX PROM Corruption
49107: 02/11/01: <skyhawk172L@attbi.com>: Re: XC18VXX PROM Corruption
49112: 02/11/01: Jim Granville: Re: XC18VXX PROM Corruption
49147: 02/11/02: <skyhawk172L@attbi.com>: Re: XC18VXX PROM Corruption
49148: 02/11/02: Jim Granville: Re: XC18VXX PROM Corruption
49111: 02/11/01: Hot Dog: Sales News
49117: 02/11/01: Allan Herriman: FDRE inference in Synplify
49124: 02/11/01: Alan Fitch: Re: FDRE inference in Synplify
49131: 02/11/01: Allan Herriman: Re: FDRE inference in Synplify
49132: 02/11/01: <hamish@cloud.net.au>: Re: FDRE inference in Synplify
49133: 02/11/01: Ray Andraka: Re: FDRE inference in Synplify
49139: 02/11/01: Ken McElvain: Re: FDRE inference in Synplify
49178: 02/11/04: RobertS: Re: FDRE inference in Synplify
49126: 02/11/01: Jun Xu: Q on extracting the state bits of registers from readback bitstream
49130: 02/11/01: Rick Filipkiewicz: 5.1i and Win-NT
49242: 02/11/06: Russell: Re: 5.1i and Win-NT
49250: 02/11/06: Stephen Williams: Re: 5.1i and Win-NT
49270: 02/11/07: Neeraj Varma: Re: 5.1i and Win-NT
49979: 02/11/27: FPGA Wonderkid: Re: 5.1i and Win-NT
49134: 02/11/01: David Collier: Using OrCAD to generate a Xilinx 9536 CPLD
49137: 02/11/01: Henri Faber: Asynchronous clock enable with stable data
49141: 02/11/01: Uwe Bonnes: Re: Asynchronous clock enable with stable data
49143: 02/11/01: Peter Alfke: Re: Asynchronous clock enable with stable data
49150: 02/11/02: David Rogoff: Re: Asynchronous clock enable with stable data
49160: 02/11/03: Peter Alfke: Re: Asynchronous clock enable with stable data
49152: 02/11/02: John Larkin: Re: Asynchronous clock enable with stable data
49153: 02/11/02: John_H: Re: Asynchronous clock enable with stable data
49144: 02/11/01: Konrad Eisele: MMU for Leon finished -> porting linux
49154: 02/11/03: lenman: 16-bit FGPA CPU core (commercial)
49155: 02/11/03: Spam Hater: Re: 16-bit FGPA CPU core (commercial)
49157: 02/11/03: Karl de Boois: Re: 16-bit FGPA CPU core (commercial)
49159: 02/11/03: lenman: Re: 16-bit FGPA CPU core (commercial)
49162: 02/11/03: Jan Gray: Re: 16-bit FGPA CPU core (commercial)
49163: 02/11/03: Jan Gray: Re: 16-bit FGPA CPU core (commercial)
49173: 02/11/04: Rob Finch: Re: 16-bit FGPA CPU core (commercial)
49190: 02/11/04: Brian Davis: Re: 16-bit FGPA CPU core (commercial)
49263: 02/11/06: Brian Davis: Re: 16-bit FGPA CPU core (commercial)
49164: 02/11/03: Jan Gray: Re: 16-bit FGPA CPU core (commercial)
49200: 02/11/04: Roger Larsson: Re: 16-bit FGPA CPU core (commercial)
49165: 02/11/04: Ralph Mason: Learner ? - Open Collector in Verilog
49168: 02/11/04: Muzaffer Kal: Re: Learner ? - Open Collector in Verilog
49170: 02/11/04: Utku Ozcan: Re: Learner ? - Open Collector in Verilog
49166: 02/11/04: Joseph H Allen: Re: 16-bit FGPA CPU core (commercial)
49167: 02/11/03: newb: pc to fpga cpu commands
49176: 02/11/04: Falk Brunner: Re: pc to fpga cpu commands
49169: 02/11/03: ssy: read and write same address of the ESB memory in the same cycle
49185: 02/11/04: Mike Treseler: Re: read and write same address of the ESB memory in the same cycle
49214: 02/11/05: Wolfgang Loewer: Re: read and write same address of the ESB memory in the same cycle
49171: 02/11/04: Peng Cong: Incremental design question
49177: 02/11/04: Jay: Re: Incremental design question
49186: 02/11/04: g. Field: Re: Incremental design question
49193: 02/11/04: Vishker: Re: Incremental design question
49194: 02/11/04: Brian Jackson: Re: Incremental design question
49257: 02/11/06: Richard Iachetta: Re: Incremental design question
49504: 02/11/13: Kate Kelley: Re: Incremental design question
49174: 02/11/04: Andreas Kugel: Excessive heating on Xilinx XC9500XL
49175: 02/11/04: Falk Brunner: Re: Excessive heating on Xilinx XC9500XL
49181: 02/11/04: Jay: Re: Excessive heating on Xilinx XC9500XL
49183: 02/11/04: Peter Alfke: Re: Excessive heating on Xilinx XC9500XL
49184: 02/11/04: David Hawke: Re: Excessive heating on Xilinx XC9500XL
49198: 02/11/04: Lorenzo Lutti: Re: Excessive heating on Xilinx XC9500XL
49201: 02/11/04: Peter Alfke: Re: Excessive heating on Xilinx XC9500XL
49236: 02/11/05: Lorenzo Lutti: Re: Excessive heating on Xilinx XC9500XL
49187: 02/11/04: Amy Mitby: tips for cutting down on slice usage in a VirtexII
49188: 02/11/04: Austin Franklin: Re: tips for cutting down on slice usage in a VirtexII
49232: 02/11/05: Amy Mitby: Re: tips for cutting down on slice usage in a VirtexII
49195: 02/11/04: Tim Jaynes: Re: tips for cutting down on slice usage in a VirtexII
49207: 02/11/05: Rick Filipkiewicz: Re: tips for cutting down on slice usage in a VirtexII
49252: 02/11/06: dr.no: Re: tips for cutting down on slice usage in a VirtexII
49192: 02/11/04: Klemen: new to fpga, what language is better to start with
49204: 02/11/05: Spam Hater: Re: new to fpga, what language is better to start with
49239: 02/11/06: rk: Re: new to fpga, what language is better to start with
49325: 02/11/09: glen herrmannsfeldt: Re: new to fpga, what language is better to start with
49334: 02/11/09: John Larkin: Re: new to fpga, what language is better to start with
49335: 02/11/09: Phil Hays: Re: new to fpga, what language is better to start with
49339: 02/11/09: Stephen Williams: Re: new to fpga, what language is better to start with
49443: 02/11/12: Nicholas C. Weaver: Re: new to fpga, what language is better to start with
49387: 02/11/11: Scott Munroe: Re: new to fpga, what language is better to start with
49398: 02/11/11: Ray Andraka: Re: new to fpga, what language is better to start with
49412: 02/11/12: Phil Hays: Re: new to fpga, what language is better to start with
49434: 02/11/12: Terry Newton: Re: new to fpga, what language is better to start with
49474: 02/11/13: Phil Hays: Re: new to fpga, what language is better to start with
49488: 02/11/13: Terry Newton: Re: new to fpga, what language is better to start with
49441: 02/11/12: James Bonanno: Re: new to fpga, what language is better to start with
49196: 02/11/04: Brian Jackson: WANTED: Technology partner to help verify new FPGA floorplanner
49199: 02/11/04: Scott Munroe: VME Master Design
49208: 02/11/05: Jan Pech: WebPACK 5.1 SP2
49215: 02/11/05: Uwe Bonnes: Re: WebPACK 5.1 SP2
49217: 02/11/05: Jan Pech: Re: WebPACK 5.1 SP2
49255: 02/11/06: Hans Holten-Lund: Re: WebPACK 5.1 SP2
49218: 02/11/05: Leon Heller: Re: WebPACK 5.1 SP2
49220: 02/11/05: Petter Gustad: Re: WebPACK 5.1 SP2
49223: 02/11/05: Peter Wallace: Re: WebPACK 5.1 SP2
49231: 02/11/05: Uwe Bonnes: Re: WebPACK 5.1 SP2
49287: 02/11/07: Uwe Bonnes: Re: WebPACK 5.1 SP2
49292: 02/11/07: Klaus Vestergaard Kragelund: Re: WebPACK 5.1 SP2
49284: 02/11/07: Rick: Re: WebPACK 5.1 SP2
49228: 02/11/05: Larry McKeogh: Re: WebPACK 5.1 SP2
49216: 02/11/05: Uwe Bonnes: Decoupling requirements on VREF pins (Xilinx)
49225: 02/11/05: Austin Lesea: Re: Decoupling requirements on VREF pins (Xilinx)
49235: 02/11/05: Uwe Bonnes: Re: Decoupling requirements on VREF pins (Xilinx)
49237: 02/11/05: Austin Lesea: Re: Decoupling requirements on VREF pins (Xilinx)
49219: 02/11/05: =?ISO-8859-1?Q?Bernhard_M=E4der?=: LVDS I/Os on Virtex-II Devices: Short circuit safety?
49226: 02/11/05: Austin Lesea: Re: LVDS I/Os on Virtex-II Devices: Short circuit safety?
49272: 02/11/07: =?ISO-8859-1?Q?Bernhard_M=E4der?=: Re: LVDS I/Os on Virtex-II Devices: Short circuit safety?
49221: 02/11/05: Ken Mac: multi-channel filters - how many channels?
49479: 02/11/13: Ray Andraka: Re: multi-channel filters - how many channels?
49483: 02/11/13: Ken Mac: Re: multi-channel filters - how many channels?
49516: 02/11/14: Ray Andraka: Re: multi-channel filters - how many channels?
49224: 02/11/05: Timing Newb: How to approch timing constraints...
49227: 02/11/05: Scott Munroe: Re: How to approch timing constraints...
49233: 02/11/05: hristo: VersaRing
49349: 02/11/10: hristo: Re: VersaRing
49357: 02/11/10: John_H: Re: VersaRing
49363: 02/11/10: Jay: Re: VersaRing
49234: 02/11/05: Uwe Bonnes: ISE for Linux: How is programming done
49238: 02/11/05: David Gesswein: Xilinx HDL Bencher
49240: 02/11/05: Al Williams: PLD Project of the Month Experiment
49241: 02/11/06: Johannes: fir filter mit xilinx coregen
49247: 02/11/06: Rudolf Usselmann: Re: fir filter mit xilinx coregen
49273: 02/11/07: Faycal Bensaali: Re: fir filter mit xilinx coregen
49244: 02/11/06: Thomas Buerner: webpack 5.1 under w2k
49248: 02/11/06: Jan Pech: Re: webpack 5.1 under w2k
49820: 02/11/21: Speedy Zero Two: Re: webpack 5.1 under w2k
49245: 02/11/06: Tullio Grassi: synthesis tools
49249: 02/11/06: Vulcain_75: Altera ACAP?
49251: 02/11/06: Paul: Quicklogic PAsic problem
49368: 02/11/10: Jay: Re: Quicklogic PAsic problem
49372: 02/11/11: Hal Murray: Re: Quicklogic PAsic problem
49413: 02/11/12: Allan Herriman: Re: Quicklogic PAsic problem
49253: 02/11/06: Thomas Pollischansky: Compiling Altera Nios Designs
49275: 02/11/07: Prager Roman: Re: Compiling Altera Nios Designs
49280: 02/11/07: Thomas Pollischansky: Re: Compiling Altera Nios Designs
49337: 02/11/09: jerry1111: Re: Compiling Altera Nios Designs
49366: 02/11/11: Prager Roman: Re: Compiling Altera Nios Designs
49422: 02/11/11: Thomas Pollischansky: Re: Compiling Altera Nios Designs
49414: 02/11/11: fictionalsam: Re: Compiling Altera Nios Designs
49538: 02/11/14: Thomas Pollischansky: Re: Compiling Altera Nios Designs
49256: 02/11/06: qlyus: Xilinx, where is DesignManager in ISE 5.1 ?
49271: 02/11/06: RS: Re: Xilinx, where is DesignManager in ISE 5.1 ?
49276: 02/11/07: Jan Gray: Project Navigator Console thumb behavior (was Re: Xilinx, where is DesignManager in ISE 5.1 ?)
49258: 02/11/06: hristo: glue logic device
49259: 02/11/06: Tullio Grassi: Re: glue logic device
49285: 02/11/07: hristo: Re: glue logic device
49322: 02/11/09: Altogether_Andrews: Re: glue logic device
49296: 02/11/08: Roland Macho: Re: glue logic device
49261: 02/11/06: Jeff: Question about algorithm implementing in FPGA
49267: 02/11/07: Hal Murray: Re: Question about algorithm implementing in FPGA
49277: 02/11/07: Jeff: Re: Question about algorithm implementing in FPGA
49525: 02/11/14: Ray Andraka: Re: Question about algorithm implementing in FPGA
49262: 02/11/07: Sanjay Patil: LUT Consumption in Virtex-2
49268: 02/11/07: Hal Murray: Re: LUT Consumption in Virtex-2
49269: 02/11/07: Sanjay Patil: Re: LUT Consumption in Virtex-2
49278: 02/11/07: Peter Alfke: Re: LUT Consumption in Virtex-2
49517: 02/11/14: Ray Andraka: Re: LUT Consumption in Virtex-2
49847: 02/11/22: glen herrmannsfeldt: Re: LUT Consumption in Virtex-2
49851: 02/11/22: Ray Andraka: Re: LUT Consumption in Virtex-2
49336: 02/11/09: Jay: Re: LUT Consumption in Virtex-2
49264: 02/11/07: Ralph Mason: Instruction sets to implement instruction sets
49266: 02/11/07: Henry Davis: Re: Instruction sets to implement instruction sets
49279: 02/11/07: Peter Alfke: Re: Instruction sets to implement instruction sets
49282: 02/11/07: emanuel stiebler: Re: Instruction sets to implement instruction sets
49324: 02/11/09: Ralph Mason: Re: Instruction sets to implement instruction sets
49330: 02/11/09: Helmut Sennewald: Re: Instruction sets to implement instruction sets
49283: 02/11/07: Leon Heller: Re: Instruction sets to implement instruction sets
49289: 02/11/07: Henry Davis: Re: Instruction sets to implement instruction sets
49291: 02/11/07: Geoffrey G. Rochat: Re: Instruction sets to implement instruction sets
49274: 02/11/07: Markus Fras: Programming Altera EPC16
49281: 02/11/07: dr.no: Re: Programming Altera EPC16
49689: 02/11/20: Paul Bealing: Re: Programming Altera EPC16
49288: 02/11/07: Bob: ISE web pack multiplier CORE
49298: 02/11/08: Bill Turnip: Re: ISE web pack multiplier CORE
49290: 02/11/07: Catalin: Wrong speed specs for Spartan II ??
49293: 02/11/08: fireball: LU-decomposition
49294: 02/11/08: Utku Ozcan: Re: LU-decomposition
49301: 02/11/08: Muzaffer Kal: Re: LU-decomposition
49326: 02/11/09: glen herrmannsfeldt: Re: LU-decomposition
49408: 02/11/12: Stan: Re: LU-decomposition
49417: 02/11/12: glen herrmannsfeldt: Re: LU-decomposition
49351: 02/11/10: fireball: Re: LU-decomposition
49354: 02/11/10: Jan Gray: Re: LU-decomposition
49410: 02/11/12: Stan: Re: LU-decomposition
49420: 02/11/11: Jan Gray: Re: LU-decomposition
49360: 02/11/11: glen herrmannsfeldt: Re: LU-decomposition
49409: 02/11/12: Stan: Re: LU-decomposition
49416: 02/11/12: Muzaffer Kal: Re: LU-decomposition
49418: 02/11/12: glen herrmannsfeldt: Re: LU-decomposition
49435: 02/11/12: Goran Bilski: Re: LU-decomposition
49463: 02/11/12: Jan Gray: Re: LU-decomposition
49499: 02/11/13: Goran Bilski: Re: LU-decomposition
49523: 02/11/14: Ray Andraka: Re: LU-decomposition
49526: 02/11/14: glen herrmannsfeldt: Re: LU-decomposition
49371: 02/11/11: fireball: Re: LU-decomposition
49386: 02/11/11: Kolja Sulimma: Re: LU-decomposition
49390: 02/11/11: Dr. Andy Nisbet: Re: LU-decomposition
49407: 02/11/12: Stan: Re: LU-decomposition
49534: 02/11/14: fireball: Re: LU-decomposition
49556: 02/11/15: Stan: Re: LU-decomposition
49295: 02/11/08: hiro: BUFT bus contention
49303: 02/11/08: Falk Brunner: Re: BUFT bus contention
49316: 02/11/09: Phil Hays: Re: BUFT bus contention
49297: 02/11/08: Old Radio Days: Online pinouts of glue chips
49304: 02/11/08: Hal Murray: Re: Online pinouts of glue chips
49299: 02/11/08: Philippe Robert: Modular Design for Project Manager 5.1.02
49305: 02/11/08: Chen Wei Tseng: Re: Modular Design for Project Manager 5.1.02
49302: 02/11/08: Kirk: Help on using multiple ABEL sources
49306: 02/11/08: Max K.: functional test for Xilinx virtex II Pro
49307: 02/11/08: Peter Alfke: Re: functional test for Xilinx virtex II Pro
49308: 02/11/08: Max K.: Re: functional test for Xilinx virtex II Pro
49309: 02/11/08: Peter Alfke: Re: functional test for Xilinx virtex II Pro
49385: 02/11/11: Ken Ryan: Re: functional test for Xilinx virtex II Pro
49320: 02/11/09: Phil Hays: Re: functional test for Xilinx virtex II Pro
49317: 02/11/09: rk: Re: functional test for Xilinx virtex II Pro
49405: 02/11/12: Stan: Re: functional test for Xilinx virtex II Pro
49468: 02/11/13: rk: Re: functional test for Xilinx virtex II Pro
49321: 02/11/09: Altogether_Andrews: Re: functional test for Xilinx virtex II Pro
49358: 02/11/10: Uwe Bonnes: Re: functional test for Xilinx virtex II Pro
49406: 02/11/12: Stan: Re: functional test for Xilinx virtex II Pro
49472: 02/11/13: John Williams: Re: functional test for Xilinx virtex II Pro
51237: 03/01/08: rk: Re: functional test for Xilinx virtex II Pro
49310: 02/11/08: Saffary: Spartan I with ISE Webpack
49329: 02/11/08: Eric Smith: Re: Spartan I with ISE Webpack
49311: 02/11/08: Amy Mitby: Pros and Cons of using Xilinx CoreGen components
49315: 02/11/08: Mike Treseler: Re: Pros and Cons of using Xilinx CoreGen components
49348: 02/11/10: Rudolf Usselmann: Re: Pros and Cons of using Xilinx CoreGen components
49312: 02/11/08: Saffary: Spartan I with ISE Webpack
49313: 02/11/08: Falk Brunner: Re: Spartan I with ISE Webpack
49314: 02/11/08: lpm: External memory or on-chip?
49318: 02/11/09: Phil Hays: Re: External memory or on-chip?
49389: 02/11/11: lpm: Re: External memory or on-chip?
49338: 02/11/09: Kevin Neilson: Re: External memory or on-chip?
49319: 02/11/09: Altogether_Andrews: Has anyone tried Lattice's chips?
49347: 02/11/10: Rudolf Usselmann: Re: Has anyone tried Lattice's chips?
49546: 02/11/14: Marc Randolph: Re: Has anyone tried Lattice's chips?
49562: 02/11/15: Symon: Re: Has anyone tried Lattice's chips?
49327: 02/11/08: fi: Xilinx LUT-based FPGAs
49328: 02/11/09: Hal Murray: Re: Xilinx LUT-based FPGAs
49333: 02/11/09: Jan Gray: Re: Xilinx LUT-based FPGAs
49331: 02/11/09: Bob: Core generator modules & Copyright
49332: 02/11/09: Thomas Bartzick: FPGA: SPARTAN IIE-Configuration via JTAG
49340: 02/11/10: Jim Antone: PCI core
49346: 02/11/10: Rudolf Usselmann: Re: PCI core
49341: 02/11/09: Ru-Chin Tsai: How to instanciate Altera primitive component in VHDL for FPGA Compiler synthesis?
49382: 02/11/11: Martin Schoeberl: Re: How to instanciate Altera primitive component in VHDL for FPGA Compiler synthesis?
49388: 02/11/11: Prager Roman: Re: How to instanciate Altera primitive component in VHDL for FPGA Compiler synthesis?
49411: 02/11/11: Ru-Chin Tsai: Re: How to instanciate Altera primitive component in VHDL for FPGA Compiler synthesis?
49431: 02/11/12: Marco Serafini: Re: How to instanciate Altera primitive component in VHDL for FPGA Compiler synthesis?
49342: 02/11/09: golchehreh sohrab: Back annotation initialization problem
49345: 02/11/10: Dali: Re: Back annotation initialization problem
49378: 02/11/11: Ulises Hernandez: Re: Back annotation initialization problem
49343: 02/11/10: Stevenson: Unexplained signal interaction
49367: 02/11/10: Jay: Re: Unexplained signal interaction
49344: 02/11/09: chankc: Request for multi-stage digital decimation filter's core.
49350: 02/11/10: Philip Pemberton: Altera MAX7000E (EPM7128ELC84) - programmer?
49373: 02/11/11: Martin Thompson: Re: Altera MAX7000E (EPM7128ELC84) - programmer?
49393: 02/11/11: Philip Pemberton: Re: Altera MAX7000E (EPM7128ELC84) - programmer?
49425: 02/11/12: Satya: Re: Altera MAX7000E (EPM7128ELC84) - programmer?
49428: 02/11/12: Martin Thompson: Re: Altera MAX7000E (EPM7128ELC84) - programmer?
49451: 02/11/12: ted: Re: Altera MAX7000E (EPM7128ELC84) - programmer?
49678: 02/11/19: Philip Pemberton: Re: Altera MAX7000E (EPM7128ELC84) - programmer?
49352: 02/11/10: <devnull@mighty.morphism.org>: CLB numbers for various ops?
49353: 02/11/10: Falk Brunner: Re: CLB numbers for various ops?
49355: 02/11/10: Hal Murray: Re: CLB numbers for various ops?
49356: 02/11/10: Falk Brunner: Re: CLB numbers for various ops?
49423: 02/11/12: Ralph Mason: Re: CLB numbers for various ops?
49359: 02/11/10: Zhenglin: rs encode
49361: 02/11/11: Kevin Neilson: Re: rs encode
49377: 02/11/11: Neeraj Varma: Re: rs encode
49362: 02/11/11: Young-Su Kwon: EDIF generation from XST of ISE 5.1i
49430: 02/11/12: Sanjay Patil: Re: EDIF generation from XST of ISE 5.1i
49454: 02/11/12: Falk Brunner: Re: EDIF generation from XST of ISE 5.1i
49501: 02/11/13: Michael Rhotert: Re: EDIF generation from XST of ISE 5.1i
49460: 02/11/12: lass: Re: EDIF generation from XST of ISE 5.1i
49537: 02/11/14: Muthu: Re: EDIF generation from XST of ISE 5.1i
49369: 02/11/11: dan: How much to build this? xvga to ntsc uhf broadcaster
49512: 02/11/14: Ray Andraka: Re: How much to build this? xvga to ntsc uhf broadcaster
49529: 02/11/14: glen herrmannsfeldt: Re: How much to build this? xvga to ntsc uhf broadcaster
49375: 02/11/11: Andreas Schweizer: Xilinx Virtex SelectMAP question
49383: 02/11/11: Austin Lesea: Re: Xilinx Virtex SelectMAP question
49424: 02/11/12: Andreas Schweizer: Re: Xilinx Virtex SelectMAP question
49376: 02/11/11: H.L: Chipscope 3.3 and pentium 4
49379: 02/11/11: Ashwini G: New to FPGA!
49380: 02/11/11: Ruppen Michael: Partial Reconfiguration, Modular Design
49384: 02/11/11: Austin Lesea: Re: Partial Reconfiguration, Modular Design
49461: 02/11/12: Craig Cholvin: Re: Partial Reconfiguration, Modular Design
49381: 02/11/11: Andreas Merkle: problem with rocbuf
49391: 02/11/11: Nicholas C. Weaver: Silly FPGA Arch question...
49392: 02/11/12: Jim Granville: Re: Silly FPGA Arch question...
49394: 02/11/11: Nicholas C. Weaver: Re: Silly FPGA Arch question...
49395: 02/11/11: Anonymous4: HDL vs RTL
49397: 02/11/11: Kevin Neilson: Re: HDL vs RTL
49403: 02/11/12: Stan: Re: HDL vs RTL
49415: 02/11/12: Ray Andraka: Re: HDL vs RTL
49470: 02/11/13: Stan: Re: HDL vs RTL
49445: 02/11/12: Jerry: Re: HDL vs RTL
49455: 02/11/12: aaron: Re: HDL vs RTL
49457: 02/11/12: Nicholas C. Weaver: Re: HDL vs RTL
49465: 02/11/12: Jan Gray: Re: HDL vs RTL
49467: 02/11/12: Nicholas C. Weaver: Re: HDL vs RTL
49530: 02/11/14: Rick Filipkiewicz: Re: HDL vs RTL
49478: 02/11/13: Ray Andraka: Re: HDL vs RTL
49456: 02/11/12: aaron: Re: HDL vs RTL
49396: 02/11/11: <mr_donk@hotmail.com>: FPGA Size?
49419: 02/11/12: Hal Murray: Re: FPGA Size?
49440: 02/11/12: <mr_donk@hotmail.com>: Re: FPGA Size?
49436: 02/11/12: Scott Munroe: Re: FPGA Size?
49448: 02/11/12: Amy Mitby: Re: FPGA Size?
49450: 02/11/12: jerry1111: Re: FPGA Size?
49399: 02/11/11: Justin A. Kolodziej: The "Do"s and "Don't"s of Synthesizing VHDL?
49421: 02/11/12: Jussi =?ISO-8859-1?Q?L=E4hteenm=E4ki?=: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
49427: 02/11/12: M Pedley: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
49433: 02/11/12: Jussi =?ISO-8859-1?Q?L=E4hteenm=E4ki?=: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
49439: 02/11/12: Ralf Hildebrandt: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
49442: 02/11/12: Mike Treseler: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
49531: 02/11/14: Rick Filipkiewicz: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
49552: 02/11/15: Lasse Langwadt Christensen: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
49553: 02/11/14: Ray Andraka: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
49543: 02/11/14: Phil Connor: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
49554: 02/11/15: David R Brooks: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
49555: 02/11/14: Clyde R. Shappee: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
49965: 02/11/27: Mike D: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
49400: 02/11/11: Rajesh Bawankule: FAQ: Verilog FAQ : November 15, 2002
49402: 02/11/12: John Williams: Associative memory and multiport memories
49404: 02/11/12: Stan: Re: Associative memory and multiport memories
49429: 02/11/12: Ken Mac: repost: parallel multi-channel filters - how many channels?
49432: 02/11/12: C. Peter: FPGA PCMCIA-card?
49437: 02/11/12: atlgpag: vhdl inout question
49444: 02/11/12: Mike Treseler: Re: vhdl inout question
49438: 02/11/12: Shareef Jalloq: How to disable IOB register packing?
49469: 02/11/13: John_H: Re: How to disable IOB register packing?
49481: 02/11/12: Jay: Re: How to disable IOB register packing?
49484: 02/11/13: Shareef Jalloq: Re: How to disable IOB register packing?
49490: 02/11/13: <hamish@cloud.net.au>: Re: How to disable IOB register packing?
49497: 02/11/13: Shareef Jalloq: Re: How to disable IOB register packing?
49500: 02/11/13: Shareef Jalloq: Re: How to disable IOB register packing?
49532: 02/11/14: Rick Filipkiewicz: Re: How to disable IOB register packing?
49446: 02/11/12: Amy Mitby: Efficient implementation memory-mapped regisetrs
49452: 02/11/12: Falk Brunner: Re: Efficient implementation memory-mapped regisetrs
49533: 02/11/14: Rick Filipkiewicz: Re: Efficient implementation memory-mapped regisetrs
49447: 02/11/12: Amy Mitby: Registering inputs or outputs of modules
49480: 02/11/12: Jay: Re: Registering inputs or outputs of modules
49487: 02/11/13: Ray Andraka: Re: Registering inputs or outputs of modules
49508: 02/11/14: John Williams: Re: Registering inputs or outputs of modules
49509: 02/11/13: Mike Treseler: Re: Registering inputs or outputs of modules
49510: 02/11/14: John Williams: Re: Registering inputs or outputs of modules
49518: 02/11/14: Ray Andraka: Re: Registering inputs or outputs of modules
49521: 02/11/14: Stan: Re: Registering inputs or outputs of modules
49563: 02/11/15: M Schreiber: Re: Registering inputs or outputs of modules
49571: 02/11/15: Mike Treseler: Re: Registering inputs or outputs of modules
49449: 02/11/12: David Binnie: jedec
49462: 02/11/13: Jim Granville: Re: jedec
49506: 02/11/13: Dennis McCrohan: Re: jedec
49507: 02/11/13: Stephen Williams: Re: jedec
49453: 02/11/12: FAQ: buffer ports on lower level VHDL modules
49485: 02/11/13: Alan Fitch: Re: buffer ports on lower level VHDL modules
49459: 02/11/12: Steven Derrien: EPP slave interface
49491: 02/11/13: Martin Schoeberl: Re: EPP slave interface
49493: 02/11/13: Falk Brunner: Re: EPP slave interface
49540: 02/11/14: Laurent Gauch: Re: EPP slave interface
49541: 02/11/14: Steven Derrien: Re: EPP slave interface
49572: 02/11/15: Laurent Gauch: Re: EPP slave interface
49464: 02/11/12: Amy Mitby: Feedback from a 200 MHz Virtex2 design
49466: 02/11/12: Nicholas C. Weaver: Re: Feedback from a 200 MHz Virtex2 design
49475: 02/11/13: Stan: Re: Feedback from a 200 MHz Virtex2 design
49486: 02/11/13: Utku Ozcan: Re: Feedback from a 200 MHz Virtex2 design
49477: 02/11/13: Ray Andraka: Re: Feedback from a 200 MHz Virtex2 design
49524: 02/11/14: Ray Andraka: Re: Feedback from a 200 MHz Virtex2 design
49471: 02/11/12: Anup Raghavan: Tristate buffers + leonardo Spectrum
49489: 02/11/13: Martin Schoeberl: Re: Tristate buffers + leonardo Spectrum
49492: 02/11/13: <hamish@cloud.net.au>: Re: Tristate buffers + leonardo Spectrum
49657: 02/11/19: pradeep: Re: Tristate buffers + leonardo Spectrum
49482: 02/11/13: Sanjay Patil: Simulation Modes
49494: 02/11/13: ted: Costing FPGA design projects
49577: 02/11/15: Tullio Grassi: Re: Costing FPGA design projects
49496: 02/11/13: mehmeto: question about booth multipliers
49520: 02/11/14: Sanjay Patil: Re: question about booth multipliers
49498: 02/11/13: JP Nicholls: Problem with Xilinx Application 134 "Synthesizable High-Performance SDRAM Controllers"
49502: 02/11/13: bbrown: creating a fabric in an FPGA
49519: 02/11/13: Jay: Re: creating a fabric in an FPGA
49522: 02/11/14: Stan: Re: creating a fabric in an FPGA
49527: 02/11/13: Dali: Re: creating a fabric in an FPGA
49503: 02/11/13: <Jee@hotmail.com>: how to name the IOBUF attribute in UCF
49528: 02/11/14: Jyke: Re: how to name the IOBUF attribute in UCF
49505: 02/11/13: Alfredo: why systemc?
49542: 02/11/14: Jerry: Re: why systemc?
49544: 02/11/14: Marty Pietruszka: Re: why systemc?
49560: 02/11/15: Rick Filipkiewicz: Re: why systemc?
49826: 02/11/21: Alfredo: Re: why systemc?
49511: 02/11/14: Jens Niemann: Programming a Spartan2 via JTAG
49545: 02/11/14: Falk Brunner: Re: Programming a Spartan2 via JTAG
49548: 02/11/14: Larry Doolittle: Re: Programming a Spartan2 via JTAG
49514: 02/11/14: Tim: Cool LED Flasher
49536: 02/11/14: Charles Braquet: configuration with Altera EPC16?
49558: 02/11/15: Wolfgang Loewer: Re: configuration with Altera EPC16?
49561: 02/11/15: Fredrik: Re: configuration with Altera EPC16?
49539: 02/11/14: Don: xc9500 tristate question
49549: 02/11/14: Rick Filipkiewicz: Re: xc9500 tristate question
49550: 02/11/14: Steve Casselman: MiroTech
49557: 02/11/15: rickman: Metastability in FPGAs
49570: 02/11/15: Falk Brunner: Re: Metastability in FPGAs
49595: 02/11/16: rickman: Re: Metastability in FPGAs
49596: 02/11/16: Hal Murray: Re: Metastability in FPGAs
49607: 02/11/17: Michael S: Re: Metastability in FPGAs
49613: 02/11/18: nospam: Re: Metastability in FPGAs
49633: 02/11/18: Michael S: Re: Metastability in FPGAs
49635: 02/11/18: nospam: Re: Metastability in FPGAs
49683: 02/11/19: Michael S: Re: Metastability in FPGAs
49645: 02/11/18: rickman: Re: Metastability in FPGAs
49648: 02/11/19: Jim Granville: Re: Metastability in FPGAs
49616: 02/11/18: rickman: Re: Metastability in FPGAs
49618: 02/11/18: Hal Murray: Re: Metastability in FPGAs
49647: 02/11/18: rickman: Re: Metastability in FPGAs
49630: 02/11/18: Michael S: Re: Metastability in FPGAs
49631: 02/11/18: Bob Perlman: Re: Metastability in FPGAs
49653: 02/11/18: Michael S: Re: Metastability in FPGAs
49655: 02/11/18: Bob Perlman: Re: Metastability in FPGAs
49669: 02/11/19: Bob Perlman: Re: Metastability in FPGAs
49681: 02/11/19: Hal Murray: Re: Metastability in FPGAs
49682: 02/11/19: Hal Murray: Re: Metastability in FPGAs
49687: 02/11/19: Rick Filipkiewicz: Re: Metastability in FPGAs
49688: 02/11/19: Jim Granville: Re: Metastability in FPGAs
49665: 02/11/18: rickman: Re: Metastability in FPGAs
49672: 02/11/19: Ray Andraka: Re: Metastability in FPGAs
49675: 02/11/19: Phil Hays: Re: Metastability in FPGAs
49695: 02/11/19: Ray Andraka: Re: Metastability in FPGAs
49697: 02/11/19: rickman: Re: Metastability in FPGAs
49709: 02/11/19: Ray Andraka: Re: Metastability in FPGAs
49801: 02/11/21: Philip Freidin: Re: Metastability in FPGAs
49686: 02/11/19: Michael S: Re: Metastability in FPGAs
49649: 02/11/18: rickman: Re: Metastability in FPGAs
49650: 02/11/19: Jim Granville: Re: Metastability in FPGAs
49652: 02/11/18: Hal Murray: Re: Metastability in FPGAs
49666: 02/11/18: rickman: Re: Metastability in FPGAs
49659: 02/11/19: nospam: Re: Metastability in FPGAs
49661: 02/11/19: Hal Murray: Re: Metastability in FPGAs
49662: 02/11/19: Jim Granville: Re: Metastability in FPGAs
49664: 02/11/19: Nicholas C. Weaver: Re: Metastability in FPGAs
49667: 02/11/18: rickman: Re: Metastability in FPGAs
49677: 02/11/19: Hal Murray: Re: Metastability in FPGAs
49651: 02/11/18: Hal Murray: Re: Metastability in FPGAs
49660: 02/11/19: nospam: Re: Metastability in FPGAs
49668: 02/11/18: rickman: Re: Metastability in FPGAs
49679: 02/11/19: Hal Murray: Re: Metastability in FPGAs
49698: 02/11/19: rickman: Re: Metastability in FPGAs
49806: 02/11/21: Rick Filipkiewicz: Re: Metastability in FPGAs
49685: 02/11/19: Michael S: Re: Metastability in FPGAs
49805: 02/11/21: Pierre-Olivier Laprise: Re: Metastability in FPGAs
49808: 02/11/21: Nicholas C. Weaver: Re: Metastability in FPGAs
49827: 02/11/21: Pierre-Olivier Laprise: Re: Metastability in FPGAs
49838: 02/11/22: nospam: Re: Metastability in FPGAs
49844: 02/11/22: Jim Granville: Re: Metastability in FPGAs
49881: 02/11/24: Hal Murray: Re: Metastability in FPGAs
49829: 02/11/21: rickman: Re: Metastability in FPGAs
49832: 02/11/22: Nicholas C. Weaver: Re: Metastability in FPGAs
49835: 02/11/22: Ray Andraka: Re: Metastability in FPGAs
49840: 02/11/22: Nicholas C. Weaver: Re: Metastability in FPGAs
49628: 02/11/18: Ray Andraka: Re: Metastability in FPGAs
50021: 02/11/28: A. Karen Alfke: Re: Metastability in FPGAs
50030: 02/11/28: Michael S: Re: Metastability in FPGAs
50032: 02/11/28: A. Karen Alfke: Re: Metastability in FPGAs
50053: 02/11/29: glen herrmannsfeldt: Re: Metastability in FPGAs
50052: 02/11/29: glen herrmannsfeldt: Re: Metastability in FPGAs
50055: 02/11/29: A. Karen Alfke: Re: Metastability in FPGAs
49559: 02/11/15: =?ISO-8859-1?Q?Bernhard_M=E4der?=: Asynchronous FIFOs using Handel-C?
49573: 02/11/15: Mike Treseler: Re: Asynchronous FIFOs using Handel-C?
49603: 02/11/17: Bernhard Mäder: Re: Asynchronous FIFOs using Handel-C?
49606: 02/11/17: Mike Treseler: Re: Asynchronous FIFOs using Handel-C?
49703: 02/11/19: Bernhard Mäder: Re: Asynchronous FIFOs using Handel-C?
49639: 02/11/18: Falk Brunner: Re: Asynchronous FIFOs using Handel-C?
49702: 02/11/19: Bernhard Mäder: Re: Asynchronous FIFOs using Handel-C?
49708: 02/11/19: Falk Brunner: Re: Asynchronous FIFOs using Handel-C?
49757: 02/11/20: Bernhard Mäder: Re: Asynchronous FIFOs using Handel-C?
49975: 02/11/27: Alan Fitch: Re: Asynchronous FIFOs using Handel-C?
50008: 02/11/28: Bernhard Mäder: Re: Asynchronous FIFOs using Handel-C?
50018: 02/11/28: A. Karen Alfke: Re: Asynchronous FIFOs using Handel-C?
50067: 02/11/30: Bernhard Mäder: Re: Asynchronous FIFOs using Handel-C?
50071: 02/11/30: A. Karen Alfke: Re: Asynchronous FIFOs using Handel-C?
50076: 02/11/30: Bernhard Mäder: Re: Asynchronous FIFOs using Handel-C?
50077: 02/11/30: A. Karen Alfke: Re: Asynchronous FIFOs using Handel-C?
50074: 02/11/30: Ray Andraka: Re: Asynchronous FIFOs using Handel-C?
49564: 02/11/15: suchitra: cpld pin configuration is wrongly assigned
49565: 02/11/15: nospam: Re: cpld pin configuration is wrongly assigned
49654: 02/11/18: Dennis McCrohan: Re: cpld pin configuration is wrongly assigned
49568: 02/11/15: Eric Smith: Webpack and Virtex Pro?
49588: 02/11/16: <hamish@cloud.net.au>: Re: Webpack and Virtex Pro?
49619: 02/11/18: Petter Gustad: Re: Webpack and Virtex Pro?
49766: 02/11/20: lass: Re: Webpack and Virtex Pro?
49643: 02/11/18: Speedy Zero Two: Re: Webpack and Virtex Pro?
49723: 02/11/19: Eric Smith: Re: Webpack and Virtex Pro?
49736: 02/11/20: <hamish@cloud.net.au>: Re: Webpack and Virtex Pro?
49753: 02/11/20: Larry Doolittle: Re: Webpack and Virtex Pro?
49762: 02/11/20: Ray Andraka: Re: Webpack and Virtex Pro?
49575: 02/11/15: Prashant: FPGA board random error
49578: 02/11/15: Falk Brunner: Re: FPGA board random error
49609: 02/11/17: Prashant: Re: FPGA board random error
49581: 02/11/15: John_H: Re: FPGA board random error
49580: 02/11/15: Xie Jubo: about schmatic symbol
49644: 02/11/18: Chen Wei Tseng: Re: about schmatic symbol
49582: 02/11/15: Anonymous4: DLL again :-)
49583: 02/11/16: Kevin Neilson: Re: DLL again :-)
49584: 02/11/16: Nicholas C. Weaver: Re: DLL again :-)
49585: 02/11/16: Hal Murray: Re: DLL again :-)
49586: 02/11/15: Austin Franklin: Re: DLL again :-)
49587: 02/11/16: Hal Murray: Re: DLL again :-)
49594: 02/11/16: Austin Franklin: Re: DLL again :-)
49597: 02/11/16: Hal Murray: Re: DLL again :-)
49599: 02/11/16: Austin Franklin: Re: DLL again :-)
49601: 02/11/17: Rick Filipkiewicz: Re: DLL again :-)
49589: 02/11/16: ted: CoolBlaze and PicoBlaze
49608: 02/11/17: Christoph Hauzeneder: Re: CoolBlaze and PicoBlaze
49610: 02/11/18: Jim Granville: Re: CoolBlaze and PicoBlaze
49640: 02/11/18: Sylvain Yon: Re: CoolBlaze and PicoBlaze
49590: 02/11/16: Lorenzo Lutti: Intelligent pin grouping in ISE
49591: 02/11/16: Mirko Scarana: Global clock routing
49592: 02/11/16: Uwe Bonnes: Re: Global clock routing
49593: 02/11/16: Ray Andraka: Re: Global clock routing
49809: 02/11/21: Rick Filipkiewicz: Re: Global clock routing
49814: 02/11/21: Ray Andraka: Re: Global clock routing
49772: 02/11/20: Mirko Scarana: Re: Global clock routing
49773: 02/11/21: Ray Andraka: Re: Global clock routing
49842: 02/11/21: Ru-Chin Tsai: Re: Global clock routing
49843: 02/11/22: Ray Andraka: Re: Global clock routing
49787: 02/11/21: Vishker: Re: Global clock routing
49796: 02/11/21: Ray Andraka: Re: Global clock routing
49882: 02/11/23: siriuswmx: Re: Global clock routing
49899: 02/11/24: Michael S: Re: Global clock routing
49598: 02/11/16: Anonymous4: Virtex is the 4th Xilinx Fpga generation
49605: 02/11/17: Steve Casselman: Re: Virtex is the 4th Xilinx Fpga generation
49614: 02/11/18: Larry Doolittle: Re: Virtex is the 4th Xilinx Fpga generation
49615: 02/11/18: Nicholas C. Weaver: Re: Virtex is the 4th Xilinx Fpga generation
49621: 02/11/18: Tim: Re: Virtex is the 4th Xilinx Fpga generation
49642: 02/11/18: Steve Casselman: Re: Virtex is the 4th Xilinx Fpga generation
49646: 02/11/18: Larry Doolittle: Re: Virtex is the 4th Xilinx Fpga generation
49737: 02/11/20: <hamish@cloud.net.au>: Re: Virtex is the 4th Xilinx Fpga generation
49600: 02/11/17: Flora Cathy: CLB logic function capabilities
49604: 02/11/17: Duane Clark: Re: CLB logic function capabilities
49602: 02/11/17: martin: mcu and fpga interface question
49611: 02/11/17: Lorenzo Lutti: Are block RAMs supported in simulation?
49612: 02/11/18: Peng Cong: Re: Are block RAMs supported in simulation?
49673: 02/11/19: Stan: Re: Are block RAMs supported in simulation?
49714: 02/11/19: Lorenzo Lutti: Re: Are block RAMs supported in simulation?
49740: 02/11/20: Falk Brunner: Re: Are block RAMs supported in simulation?
49763: 02/11/20: Lorenzo Lutti: Re: Are block RAMs supported in simulation?
49769: 02/11/20: Falk Brunner: Re: Are block RAMs supported in simulation?
49620: 02/11/18: Mohamed Shiha: XC5204 bitstream
50075: 02/11/30: Philip Freidin: Re: XC5204 bitstream
50155: 02/12/03: Kuan Zhou: Re: XC5204 bitstream
49622: 02/11/18: Rinux: max3000
49627: 02/11/18: luigi funes: Re: max3000
49634: 02/11/18: Rene Tschaggelar: Re: max3000
49846: 02/11/22: Rinux: R: max3000
49623: 02/11/18: =?iso-8859-1?q?Asbj=F8rn?= Djupdal: xst and vhdl-generate
49624: 02/11/18: Florian-Wolfgang Stock: Jbits and DLLs
49625: 02/11/18: Stefan Kulke: problem with clkdll on spartan2
49638: 02/11/18: Falk Brunner: Re: problem with clkdll on spartan2
49663: 02/11/18: Vikram: Re: problem with clkdll on spartan2
49694: 02/11/19: Stefan Kulke: Re: problem with clkdll on spartan2
49724: 02/11/19: Vikram: Re: problem with clkdll on spartan2
49744: 02/11/20: Stefan Kulke: Re: problem with clkdll on spartan2
49750: 02/11/20: Falk Brunner: Re: problem with clkdll on spartan2
49818: 02/11/21: Stefan Kulke: Re: problem with clkdll on spartan2
49862: 02/11/22: Stefan Kulke: Re: problem with clkdll on spartan2 - Bug on Xilinx webpack 4.2 wp3????
49626: 02/11/18: luigi funes: programming Altera EPC1
49641: 02/11/18: Leon Heller: Re: programming Altera EPC1
49632: 02/11/18: sowteng: counter error no matching overload for "+"
49637: 02/11/18: Falk Brunner: Re: counter error no matching overload for "+"
49636: 02/11/18: DarkDawn: looking for a VHDL imlementation of MD5 Hash algorithm.
49656: 02/11/18: Gary Desrosiers: Re: looking for a VHDL imlementation of MD5 Hash algorithm.
49658: 02/11/19: Ralph Mason: Some Basic Understanding - RTL
49670: 02/11/18: Rob Finch: Re: Some Basic Understanding - RTL
49671: 02/11/18: Jyoti Wagholikar: Newbie Question: Instantiating Muliplier18X18
49700: 02/11/19: Ryan Laity: Re: Newbie Question: Instantiating Muliplier18X18
49674: 02/11/19: Ray Andraka: Re: clock difference between DLL input and output?
49729: 02/11/20: louis: Re: clock difference between DLL input and output?
50202: 02/12/04: Jeff Cunningham: Re: clock difference between DLL input and output?
50209: 02/12/05: Ray Andraka: Re: clock difference between DLL input and output?
50210: 02/12/05: Hal Murray: Re: clock difference between DLL input and output?
50224: 02/12/05: Ray Andraka: Re: clock difference between DLL input and output?
50222: 02/12/05: Peter Alfke: Re: clock difference between DLL input and output?
49676: 02/11/19: Matthew E Rosenthal: xilinx device inception dates
49680: 02/11/18: Michael: Common sense and pin assignment.
49684: 02/11/19: FPGA Design / Logicblock: Altera Byteblaster
49690: 02/11/19: Phil Connor: What combinational logic will produce a falling edge only.
49691: 02/11/19: ae: Re: What combinational logic will produce a falling edge only.
49751: 02/11/20: Phil Connor: Re: What combinational logic will produce a falling edge only.
49693: 02/11/19: Holger Veit: Re: What combinational logic will produce a falling edge only.
49752: 02/11/20: Phil Connor: Re: What combinational logic will produce a falling edge only.
49788: 02/11/21: Holger Veit: Re: What combinational logic will produce a falling edge only.
49701: 02/11/19: Muzaffer Kal: Re: What combinational logic will produce a falling edge only.
49704: 02/11/19: Georgi Beloev: Re: What combinational logic will produce a falling edge only.
49748: 02/11/20: Phil Connor: Re: What combinational logic will produce a falling edge only.
49747: 02/11/20: Phil Connor: Re: What combinational logic will produce a falling edge only.
49777: 02/11/20: rickman: Re: What combinational logic will produce a falling edge only.
49790: 02/11/21: Phil Connor: Re: What combinational logic will produce a falling edge only.
49857: 02/11/22: Phil Connor: Re: What combinational logic will produce a falling edge only.
49869: 02/11/22: Joe: Re: What combinational logic will produce a falling edge only.
49767: 02/11/20: Joe: Re: What combinational logic will produce a falling edge only.
49692: 02/11/19: Vicky: Small Program for Functinality Test of ApexII
49696: 02/11/19: Anup Kumar Raghavan: Input / Output flop in IOB + Virtex II
49730: 02/11/19: Vikram: Re: Input / Output flop in IOB + Virtex II
49699: 02/11/19: Tom: FPGA to implement Bluetooth baseband
49710: 02/11/19: Ray Andraka: Re: FPGA to implement Bluetooth baseband
49705: 02/11/19: Pepito Perez: Free FPGA Development Board
49712: 02/11/19: Mike D: Re: Free FPGA Development Board
49721: 02/11/19: Pepito Perez: Re: Free FPGA Development Board
49713: 02/11/19: Jan Pech: Re: Free FPGA Development Board
49720: 02/11/19: strut911: Re: Free FPGA Development Board
49728: 02/11/20: Tony M: Re: Free FPGA Development Board
49732: 02/11/19: Rudolf Usselmann: Re: Free FPGA Development Board
49759: 02/11/20: Pepito Perez: Re: Free FPGA Development Board
49706: 02/11/19: Mike D: What is a big design?
49707: 02/11/19: Jack: how to use carry chain in Virtexe
49711: 02/11/19: Ray Andraka: Re: how to use carry chain in Virtexe
49725: 02/11/20: Stan: Re: how to use carry chain in Virtexe
49727: 02/11/20: Ray Andraka: Re: how to use carry chain in Virtexe
49761: 02/11/20: Jack: Re: how to use carry chain in Virtexe
49776: 02/11/21: Stan: Re: how to use carry chain in Virtexe
49784: 02/11/21: Ray Andraka: Re: how to use carry chain in Virtexe
49848: 02/11/22: glen herrmannsfeldt: Re: how to use carry chain in Virtexe
49852: 02/11/22: Ray Andraka: Re: how to use carry chain in Virtexe
49717: 02/11/19: Pallavi: design of LVDS
49718: 02/11/19: frank yuan (rogers): need Actel programmer adaptor
49719: 02/11/20: no_spam: spartan-II Block RAM
49739: 02/11/20: Falk Brunner: Re: spartan-II Block RAM
49722: 02/11/19: abigael: switch block architecture for fpga
49726: 02/11/19: B. Joshua Rosen: HDLmaker
49731: 02/11/19: Muthu: State Machine Coding....
49733: 02/11/20: Muzaffer Kal: Re: State Machine Coding....
49980: 02/11/27: Nachiket Kapre: Re: State Machine Coding....
49734: 02/11/20: valentin tihomirov: good schmatic entry?
49735: 02/11/20: FPGA Design / Logicblock: Altera Byteblaster-compatible FPGA programmer
49738: 02/11/20: Erik Fischer: Problems With DW8051 Synthesis
49913: 02/11/25: dr.no: Re: Problems With DW8051 Synthesis
49741: 02/11/20: Ewan D. Milne: Foundation 2.1i with Windows 2000?
49742: 02/11/20: Thomas Heller: Re: Foundation 2.1i with Windows 2000?
49764: 02/11/20: Lorenzo Lutti: Re: Foundation 2.1i with Windows 2000?
49743: 02/11/20: Dziadek: Xilinx programming and PCI printer port
49770: 02/11/20: Neil Glenn Jacobson: Re: Xilinx programming and PCI printer port
49786: 02/11/21: Dziadek: Re: Xilinx programming and PCI printer port
49803: 02/11/21: Jerzy: Re: Xilinx programming and PCI printer port
49957: 02/11/26: Neil Glenn Jacobson: Re: Xilinx programming and PCI printer port
49807: 02/11/21: Kolja Sulimma: Re: Xilinx programming and PCI printer port
49745: 02/11/20: Vincent PINON: Programming Altera Flex10k under Linux
49798: 02/11/21: Iwo Mergler: Re: Programming Altera Flex10k under Linux
49746: 02/11/20: Alderan: Cpld beginner
49749: 02/11/20: Falk Brunner: Re: Cpld beginner
49765: 02/11/20: Alderan: Re: Cpld beginner
49768: 02/11/20: Falk Brunner: Re: Cpld beginner
49771: 02/11/20: Alderan: Re: Cpld beginner
49754: 02/11/20: Emmanuel Said: Re: Cpld beginner
49755: 02/11/20: John Retta: Spartan IIe - DLL Max Input Clock Frequency
49834: 02/11/22: John_H: Re: Spartan IIe - DLL Max Input Clock Frequency
49910: 02/11/25: Nachiket Kapre: Re: Spartan IIe - DLL Max Input Clock Frequency
49756: 02/11/20: Jerry: Convert AHDL design to schematics(RTL)
49758: 02/11/20: HDLadmirer: Re: Convert AHDL design to schematics(RTL)
49775: 02/11/20: Anand: programmable oscillator for Virtex-E (XCV2000E)
49782: 02/11/21: Ray Andraka: Re: programmable oscillator for Virtex-E (XCV2000E)
49824: 02/11/21: Jay: Re: programmable oscillator for Virtex-E (XCV2000E)
49871: 02/11/23: Seiran: Re: programmable oscillator for Virtex-E (XCV2000E)
49778: 02/11/21: Declan and Caulfield: XST Limitations?
49779: 02/11/21: Daryl: "new" Xilinx IOB timing paramter "Tiotp"
49833: 02/11/22: John_H: Re: "new" Xilinx IOB timing paramter "Tiotp"
50508: 02/12/11: Kate Kelley: Re: "new" Xilinx IOB timing paramter "Tiotp"
49780: 02/11/21: Markus Wolfgart: XCS-05-3PC84 and XCS10-3PC84 Question
49783: 02/11/21: Ray Andraka: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49785: 02/11/21: Hal Murray: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49823: 02/11/21: Jay: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49845: 02/11/22: Markus Wolfgart: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49850: 02/11/22: Ray Andraka: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49860: 02/11/22: Falk Brunner: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49907: 02/11/25: Markus Wolfgart: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49921: 02/11/25: Ray Andraka: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49937: 02/11/26: Nachiket Kapre: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49789: 02/11/21: Uwe Bonnes: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49795: 02/11/21: Leon Heller: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49813: 02/11/21: Falk Brunner: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49853: 02/11/22: Leon Heller: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49865: 02/11/22: Falk Brunner: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49791: 02/11/21: <Mancini =?iso-8859-1?q?St=E9phane=22?= <stephane.mancini@inpg.fr>>: Altera Logick lock newbie
49839: 02/11/22: Subroto Datta: Re: Altera Logick lock newbie
49912: 02/11/25: <Mancini =?iso-8859-1?q?St=E9phane=22?= <stephane.mancini@inpg.fr>>: Re: Altera Logick lock newbie
49792: 02/11/21: Ru-Chin Tsai: How to un-flatten bus when compiling *.edf netlist to generate *.vho in Maxplus2?
49793: 02/11/21: Noddy: Sub-busses...
49811: 02/11/21: Tom Burgess: Re: Sub-busses...
49794: 02/11/21: Michael Winter: Problems with simulation after synthesis
49855: 02/11/22: Ansgar Bambynek: Re: Problems with simulation after synthesis
49797: 02/11/21: Andreas Schweizer: Virtex timing problem
49822: 02/11/21: Jay: Re: Virtex timing problem
49873: 02/11/23: Rick Filipkiewicz: Re: Virtex timing problem
50168: 02/12/04: Andreas Schweizer: Re: Virtex timing problem
49799: 02/11/21: hiro: clock enable timing analysis
49821: 02/11/21: Jay: Re: clock enable timing analysis
49825: 02/11/21: nospam: Re: clock enable timing analysis
49800: 02/11/21: Hua WANG: Open source for floorplan wanted
49804: 02/11/21: Kevin Neilson: Re: Open source for floorplan wanted
49810: 02/11/21: Tom: Look up tables
49815: 02/11/21: Falk Brunner: Re: Look up tables
49837: 02/11/21: Dmitri Katchalov: Re: Look up tables
49849: 02/11/22: Jens Frauenschlaeger: Re: Look up tables
49812: 02/11/21: Chip: exp^x in virtex 2
49830: 02/11/21: Jay: Re: exp^x in virtex 2
49841: 02/11/22: Stan: Re: exp^x in virtex 2
49870: 02/11/22: Chip: Re: exp^x in virtex 2
49819: 02/11/21: gaby: Webpack : "others "
49828: 02/11/21: Bryan: Slice count for BCH(31,16,7) in virtex-II
49831: 02/11/21: Steve T Shannon: 8B/10B patent problems? IBM Patent # 4486739
49836: 02/11/22: Steve Casselman: Re: 8B/10B patent problems? IBM Patent # 4486739
49858: 02/11/22: Brian Drummond: Re: 8B/10B patent problems? IBM Patent # 4486739
49854: 02/11/22: Tim Nicolson: hardware image processing - log computation
49856: 02/11/22: Ray Andraka: Re: hardware image processing - log computation
50010: 02/11/28: Martin Brown: Re: hardware image processing - log computation
50054: 02/11/29: glen herrmannsfeldt: Re: hardware image processing - log computation
50383: 02/12/10: Philip Freidin: Re: hardware image processing - log computation
50418: 02/12/10: Normand Bélanger: Re: hardware image processing - log computation
50456: 02/12/11: Ray Andraka: Re: hardware image processing - log computation
50466: 02/12/11: Normand Bélanger: Re: hardware image processing - log computation
50473: 02/12/11: Ray Andraka: Re: hardware image processing - log computation
50474: 02/12/11: Normand Bélanger: Re: hardware image processing - log computation
50491: 02/12/11: Ray Andraka: Re: hardware image processing - log computation
50513: 02/12/11: John: Re: hardware image processing - log computation
50516: 02/12/11: Kip Ingram: Re: hardware image processing - log computation
50560: 02/12/12: Dave Martindale: Re: hardware image processing - log computation
50568: 02/12/13: Kip Ingram: Re: hardware image processing - log computation
50631: 02/12/14: Dave Martindale: Re: hardware image processing - log computation
50765: 02/12/19: Ray Andraka: Re: hardware image processing - log computation
60667: 03/09/19: Stan: Re: hardware image processing - log computation
60719: 03/09/19: Ray Andraka: Re: hardware image processing - log computation
50518: 02/12/12: John Williams: Re: hardware image processing - log computation
49859: 02/11/22: Rene Tschaggelar: BGA footprints
49863: 02/11/22: Marcin E. Hamerla: Re: BGA footprints
49866: 02/11/22: Rene Tschaggelar: Re: BGA footprints
49868: 02/11/22: Marcin E. Hamerla: Re: BGA footprints
49874: 02/11/23: Uwe Bonnes: Re: BGA footprints
49891: 02/11/23: Rudolf Usselmann: Re: BGA footprints
49893: 02/11/24: Marcin E. Hamerla: Re: BGA footprints
49878: 02/11/23: Hal Murray: Re: BGA footprints
49861: 02/11/22: Prashant: Conversion functions
49864: 02/11/22: Ray Andraka: Re: Conversion functions
49872: 02/11/22: Kuan Zhou: An Virtex FPGA architecture question
49887: 02/11/23: Muthu: Re: An Virtex FPGA architecture question
49900: 02/11/24: Kuan Zhou: Re: An Virtex FPGA architecture question
49918: 02/11/25: g. Field: Re: An Virtex FPGA architecture question
49876: 02/11/23: Ru-Chin Tsai: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
49879: 02/11/23: Muzaffer Kal: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
49888: 02/11/23: Muthu: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
49880: 02/11/23: strut911: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
49884: 02/11/23: Srinivasan Venkataramanan: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
49886: 02/11/24: Ken McElvain: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
49894: 02/11/24: Rick Filipkiewicz: Re: Why do post-synthesis simulation result fall into unknow output
49892: 02/11/23: Rudolf Usselmann: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
49895: 02/11/24: Niv: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
49896: 02/11/24: wallytempe: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
49883: 02/11/23: siriuswmx: What's the matter with "clock skew and data delay"?
49885: 02/11/24: Subroto Datta: Re: What's the matter with "clock skew and data delay"?
49890: 02/11/24: Kumaran Selvaratnam: Re: What's the matter with "clock skew and data delay"?
49898: 02/11/24: siriuswmx: Re: What's the matter with "clock skew and data delay"?
49906: 02/11/25: Kumaran Selvaratnam: Re: What's the matter with "clock skew and data delay"?
49897: 02/11/24: siriuswmx: Re: What's the matter with "clock skew and data delay"?
49902: 02/11/24: Jay: Re: What's the matter with "clock skew and data delay"?
49904: 02/11/24: siriuswmx: Re: What's the matter with "clock skew and data delay"?
49917: 02/11/25: Jay: Re: What's the matter with "clock skew and data delay"?
49930: 02/11/26: siriuswmx: Re: What's the matter with "clock skew and data delay"?
49889: 02/11/23: siriuswmx: How to use altera's IP core in QUARTUS?
49901: 02/11/24: Holger Baxmann: picoJava & the other of Eclipse Sun
50068: 02/11/30: Martin Schoeberl: Re: picoJava & the other of Eclipse Sun
49905: 02/11/24: Nagaraj: Using DLL output offchip
49908: 02/11/25: ahk: ModelSim XE v5.6a : missing libswiftpli.dll
49909: 02/11/25: Ryan: PCI Bridge
49911: 02/11/25: Muthu: Virtex-II Place and Route...
49915: 02/11/25: Hal Murray: Re: Virtex-II Place and Route...
49914: 02/11/25: Martin Guibert: Q about operating temperatures
49919: 02/11/25: Javier =?iso-8859-1?Q?Fern=E1ndez?=: Help: Virtex-II Pro eval.brd for System Generator
49939: 02/11/26: David Hawke: Re: Help: Virtex-II Pro eval.brd for System Generator
50029: 02/11/28: Hua Ai: What HW/SW do I need to build a PowerPC system on Vertex II Pro?
50036: 02/11/29: David Hawke: Re: What HW/SW do I need to build a PowerPC system on Vertex II Pro?
49920: 02/11/25: Alderan: Problem programming XC9536
49943: 02/11/26: Bob: Re: Problem programming XC9536
49982: 02/11/27: Alderan: Re: Problem programming XC9536
49922: 02/11/25: Seth: Anybody know of vendors of PCI boards with FPGAs?
49924: 02/11/26: Stephen Bradshaw: Re: Anybody know of vendors of PCI boards with FPGAs?
49929: 02/11/26: Laurent Gauch: Re: Anybody know of vendors of PCI boards with FPGAs?
49938: 02/11/26: David: Re: Anybody know of vendors of PCI boards with FPGAs?
49960: 02/11/26: Kolin Paul: Re: Anybody know of vendors of PCI boards with FPGAs?
49978: 02/11/27: Noel Klonsky: Re: Anybody know of vendors of PCI boards with FPGAs?
49983: 02/11/27: Bill Blyth: Re: Anybody know of vendors of PCI boards with FPGAs?
50019: 02/11/28: Robert: Re: Anybody know of vendors of PCI boards with FPGAs?
50035: 02/11/29: Ali Ahmadi Naaghed: Re: Anybody know of vendors of PCI boards with FPGAs?
50044: 02/11/29: Brian Tithecott: Re: Anybody know of vendors of PCI boards with FPGAs?
50089: 02/12/01: john jakson: Re: Anybody know of vendors of PCI boards with FPGAs?
50137: 02/12/03: Ron Huizen: Re: Anybody know of vendors of PCI boards with FPGAs?
49923: 02/11/25: Kyle Guichard: problems programming/verifying fpga using ISE 5.1
49926: 02/11/26: Spam Hater: Re: problems programming/verifying fpga using ISE 5.1
49955: 02/11/26: Neil Glenn Jacobson: Re: problems programming/verifying fpga using ISE 5.1
49976: 02/11/27: Nachiket Kapre: Re: problems programming/verifying fpga using ISE 5.1
49927: 02/11/26: Skillwood: Frequency multiplier with digital h/w
49949: 02/11/26: John_H: Re: Frequency multiplier with digital h/w
49963: 02/11/27: Gary Desrosiers: Re: Frequency multiplier with digital h/w
50001: 02/11/27: Marc Guardiani: Re: Frequency multiplier with digital h/w
50003: 02/11/27: A. Karen Alfke: Re: Frequency multiplier with digital h/w
50012: 02/11/28: FPGA Wonderkid: Re: Frequency multiplier with digital h/w
49928: 02/11/25: naveen: Delayed Transactions for PCI Target Core
49932: 02/11/26: Skillwood: count based Frequency generator
49934: 02/11/26: Rene Tschaggelar: Re: count based Frequency generator
49969: 02/11/27: Skillwood: Re: count based Frequency generator
49971: 02/11/27: Jim Granville: Re: count based Frequency generator
49972: 02/11/27: Skillwood: Re: count based Frequency generator
49997: 02/11/28: Jim Granville: Re: count based Frequency generator
49998: 02/11/27: Ray Andraka: Re: count based Frequency generator
49994: 02/11/27: John_H: Re: count based Frequency generator
49995: 02/11/28: Jim Granville: Re: count based Frequency generator
50028: 02/11/28: John_H: Re: count based Frequency generator
49952: 02/11/26: David Gamboa: Re: count based Frequency generator
49933: 02/11/26: Noddy: Simulator probes...
49935: 02/11/26: ted: Fast Digital Synthesis Generator
49936: 02/11/26: Allan Herriman: Re: Fast Digital Synthesis Generator
49947: 02/11/26: John_H: Re: Fast Digital Synthesis Generator
49951: 02/11/26: Mark McMahon: Re: Fast Digital Synthesis Generator
49959: 02/11/26: Rene Tschaggelar: Re: Fast Digital Synthesis Generator
49973: 02/11/27: ted: Re: Fast Digital Synthesis Generator
49985: 02/11/27: Ben Twijnstra: Re: Fast Digital Synthesis Generator
49993: 02/11/27: John_H: Re: Fast Digital Synthesis Generator
50082: 02/11/30: Hal Murray: Re: Fast Digital Synthesis Generator
50104: 02/12/02: ted: Re: Fast Digital Synthesis Generator
49958: 02/11/26: Ray Andraka: Re: Fast Digital Synthesis Generator
49940: 02/11/26: Nagaraj: Timing with ISE5.1i
49946: 02/11/26: John_H: Re: Timing with ISE5.1i
49986: 02/11/27: Nagaraj: Re: Timing with ISE5.1i
49941: 02/11/26: Angus Bryant: XC5210 sourcing
49944: 02/11/26: Mike Rosing: Re: Where can find MPEG-2 codec SOFT-IP CORE module, DCT、Motion-estimation...etc
49948: 02/11/26: Jeffrey Arnold: FCCM'03 Call for Papers
49950: 02/11/26: Andy Mitchell: Custom FPGA synthesis
49953: 02/11/26: Stephen Williams: Re: Custom FPGA synthesis
49956: 02/11/26: Mike Treseler: Re: Custom FPGA synthesis
50017: 02/11/28: Jay: Re: Custom FPGA synthesis
49954: 02/11/26: Anand: question about programmable oscillator ?
50024: 02/11/28: Kolja Sulimma: Re: question about programmable oscillator ?
50083: 02/12/01: Hal Murray: Re: question about programmable oscillator ?
50087: 02/12/01: Ray Andraka: Re: question about programmable oscillator ?
49961: 02/11/27: pradeep: Initialising Spartan's Block RAM
49962: 02/11/26: Nicholas C. Weaver: Re: Initialising Spartan's Block RAM
49964: 02/11/26: Anand: question about PCB traces for FPGA board... ?
49968: 02/11/27: MM: Re: question about PCB traces for FPGA board... ?
49970: 02/11/26: E. Backhus: Re: question about PCB traces for FPGA board... ?
49987: 02/11/27: Bob: Re: question about PCB traces for FPGA board... ?
49988: 02/11/27: Bob Perlman: Re: question about PCB traces for FPGA board... ?
49992: 02/11/27: Larry Doolittle: Re: question about PCB traces for FPGA board... ?
49999: 02/11/27: Ray Andraka: Re: question about PCB traces for FPGA board... ?
50057: 02/11/29: rickman: Re: question about PCB traces for FPGA board... ?
49989: 02/11/27: Falk Brunner: Re: question about PCB traces for FPGA board... ?
49991: 02/11/27: A. Karen Alfke: Re: question about PCB traces for FPGA board... ?
50000: 02/11/27: Ray Andraka: Re: question about PCB traces for FPGA board... ?
50002: 02/11/28: Bob: Re: question about PCB traces for FPGA board... ?
50005: 02/11/27: A. Karen Alfke: Re: question about PCB traces for FPGA board... ?
50007: 02/11/28: Bob: Re: question about PCB traces for FPGA board... ?
50016: 02/11/28: A. Karen Alfke: Re: question about PCB traces for FPGA board... ?
50020: 02/11/28: Bob: Re: question about PCB traces for FPGA board... ?
50023: 02/11/28: A. Karen Alfke: Re: question about PCB traces for FPGA board... ?
50130: 02/12/03: Bill Blyth: Re: question about PCB traces for FPGA board... ?
50140: 02/12/03: rickman: Re: question about PCB traces for FPGA board... ?
50143: 02/12/03: Bill Blyth: Re: question about PCB traces for FPGA board... ?
50144: 02/12/03: Austin Lesea: Re: question about PCB traces for FPGA board... ?
50145: 02/12/03: Bill Blyth: Re: question about PCB traces for FPGA board... ?
49996: 02/11/27: Theron Hicks: Re: question about PCB traces for FPGA board... ?
50015: 02/11/28: Jay: question about PCB traces for FPGA board... ?
49966: 02/11/27: MM: Has anyone implemented a IEEE1394 LLC?
49967: 02/11/26: Muthu: How to instantiate a Hard-Macro in a design?
49974: 02/11/27: Muthu: HardMacro (from FPGA Editor) Instantiation
49990: 02/11/27: Ryan Laity: Re: HardMacro (from FPGA Editor) Instantiation
50006: 02/11/27: Muthu: Re: HardMacro (from FPGA Editor) Instantiation
50103: 02/12/02: Ryan Laity: Re: HardMacro (from FPGA Editor) Instantiation
49977: 02/11/27: Tim Nicolson: Microblaze, OPBs, ZBTs and other animals
49981: 02/11/27: Nachiket Kapre: Re: clock difference between DLL input and output?
50118: 02/12/03: louis: Re: clock difference between DLL input and output?
50172: 02/12/04: Nachiket Kapre: Re: clock difference between DLL input and output?
50188: 02/12/04: Ray Andraka: Re: clock difference between DLL input and output?
49984: 02/11/27: Gary Partis: Xilinx Virtex 2 BIT Files
50004: 02/11/28: Sanjay Patil: Xilinx ISE/XST Problem or FFT Designer can help me.
50009: 02/11/28: Jan Gray: Xilinx XC2S400E and XC2S600E
50011: 02/11/28: Eduard Kriegler: Leon Softcore and Altera
50014: 02/11/28: Leon Heller: Re: Leon Softcore and Altera
50013: 02/11/28: Ru-Chin Tsai: Where can find MPEG-2 codec SOFT-IP CORE module, DCT、Motion-estimation...etc
50025: 02/11/28: genius: Re: Finding MPEG1 & MPEG2 codec chips?
50026: 02/11/28: RFrank1234: Where can I find low cost 3rd party Xilinx j-tag programmer?
50064: 02/11/30: Nachiket Kapre: Re: Where can I find low cost 3rd party Xilinx j-tag programmer?
50105: 02/12/02: Seiran: Re: Where can I find low cost 3rd party Xilinx j-tag programmer?
50027: 02/11/28: Catalin: Spartan-II 2S200 PCI Board
50031: 02/11/28: Kevin Brace: Re: Spartan-II 2S200 PCI Board
50033: 02/11/29: Uwe Bonnes: Re: Spartan-II 2S200 PCI Board
50062: 02/11/30: Kevin Brace: Re: Spartan-II 2S200 PCI Board
50073: 02/11/30: Austin Franklin: Re: Spartan-II 2S200 PCI Board
50127: 02/12/03: Kevin Brace: Re: Spartan-II 2S200 PCI Board
50059: 02/11/29: Austin Franklin: Re: Spartan-II 2S200 PCI Board
50063: 02/11/30: Kevin Brace: Re: Spartan-II 2S200 PCI Board
50069: 02/11/30: Ray Andraka: Re: Spartan-II 2S200 PCI Board
50072: 02/11/30: Austin Franklin: Re: Spartan-II 2S200 PCI Board
50061: 02/11/30: Kevin Brace: Re: Spartan-II 2S200 PCI Board
50034: 02/11/29: Semih Hazar: Coolrunner II Voltage levels
50037: 02/11/29: Uwe Bonnes: Re: Coolrunner II Voltage levels
50038: 02/11/29: zhengyu: programmable FSM
50039: 02/11/29: David Hawke: Re: programmable FSM
50046: 02/11/29: Muthu: Re: programmable FSM
50051: 02/11/29: Theron Hicks: Re: programmable FSM
50047: 02/11/29: Nachiket Kapre: Re: programmable FSM
50050: 02/11/29: A. Karen Alfke: Re: programmable FSM
50066: 02/11/30: Nachiket Kapre: Re: programmable FSM
50070: 02/11/30: A. Karen Alfke: Re: programmable FSM
50040: 02/11/29: Sasa Bremec: System Generator and 18x18 multipliers
50042: 02/11/29: Paul Hardy: Re: System Generator and 18x18 multipliers
50043: 02/11/29: Laurent Gauch: Re: System Generator and 18x18 multipliers
50045: 02/11/29: Muthu: Re: System Generator and 18x18 multipliers
50049: 02/11/29: A. Karen Alfke: Re: System Generator and 18x18 multipliers
50041: 02/11/29: Guy Eschemann: SDRAM technology
50048: 02/11/29: Re: R: SDRAM technology
50056: 02/11/29: Spam Hater: Re: SDRAM technology
50060: 02/11/30: Kevin Brace: Re: SDRAM technology
50058: 02/11/29: rickman: Re: SDRAM technology
50065: 02/11/30: Nachiket Kapre: RAM and IO Standards
50078: 02/11/30: John Jacob: Interfacing DSP to PCI bridge using a FPGA
50080: 02/11/30: rickman: Re: Interfacing DSP to PCI bridge using a FPGA
50084: 02/11/30: John Jacob: Re: Interfacing DSP to PCI bridge using a FPGA
50088: 02/12/01: rickman: Re: Interfacing DSP to PCI bridge using a FPGA
50093: 02/12/01: John Jacob: Re: Interfacing DSP to PCI bridge using a FPGA
50081: 02/11/30: MM: Re: Interfacing DSP to PCI bridge using a FPGA
50085: 02/11/30: John Jacob: Re: Interfacing DSP to PCI bridge using a FPGA
50092: 02/12/02: MM: Re: Interfacing DSP to PCI bridge using a FPGA
50101: 02/12/02: John Jacob: Re: Interfacing DSP to PCI bridge using a FPGA
50102: 02/12/02: MM: Re: Interfacing DSP to PCI bridge using a FPGA
50113: 02/12/02: andyman: Re: Interfacing DSP to PCI bridge using a FPGA
50117: 02/12/02: John Jacob: Re: Interfacing DSP to PCI bridge using a FPGA
50201: 02/12/04: Andy Peters: Re: Interfacing DSP to PCI bridge using a FPGA
50206: 02/12/04: John Jacob: Re: Interfacing DSP to PCI bridge using a FPGA
50138: 02/12/03: Ron Huizen: Re: Interfacing DSP to PCI bridge using a FPGA
50203: 02/12/04: John Jacob: Re: Interfacing DSP to PCI bridge using a FPGA
50218: 02/12/05: Ron Huizen: Re: Interfacing DSP to PCI bridge using a FPGA
50200: 02/12/04: Andy Peters: Re: Interfacing DSP to PCI bridge using a FPGA
50204: 02/12/04: John Jacob: Re: Interfacing DSP to PCI bridge using a FPGA
50352: 02/12/09: rickman: Re: Interfacing DSP to PCI bridge using a FPGA
50079: 02/11/30: Frederic Bastenaire: ModelSim XE vcom 5.6a #ERROR: cannot read output
50086: 02/12/01: Ray Andraka: Re: ModelSim XE vcom 5.6a #ERROR: cannot read output
50099: 02/12/02: Frederic Bastenaire: Re: ModelSim XE vcom 5.6a #ERROR: cannot read output
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