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Threads Starting Jun 2009

140963: 09/06/01: Antti: Peter Alfke's 6 EASY
    140974: 09/06/01: Weng Tianxiang: Re: Peter Alfke's 6 EASY
    140976: 09/06/01: Antti.Lukats@googlemail.com: Re: Peter Alfke's 6 EASY
140968: 09/06/01: fl: Xilinx DDS cannot pass simulation in Simulink
    141239: 09/06/11: cwoodring: Re: Xilinx DDS cannot pass simulation in Simulink
140969: 09/06/01: fl: Why Xilinx DDS cannot pass simulation in Simulink?
    140972: 09/06/01: fl: Re: Why Xilinx DDS cannot pass simulation in Simulink?
    140973: 09/06/01: fl: Re: Why Xilinx DDS cannot pass simulation in Simulink?
140970: 09/06/01: Neil Steiner: Maximum tilemap size for Virtex6 devices?
    140971: 09/06/01: Antti.Lukats@googlemail.com: Re: Maximum tilemap size for Virtex6 devices?
        140975: 09/06/01: <peter@xilinx.com>: Re: Maximum tilemap size for Virtex6 devices?
        140978: 09/06/01: Antti.Lukats@googlemail.com: Re: Maximum tilemap size for Virtex6 devices?
        140980: 09/06/01: Neil Steiner: Re: Maximum tilemap size for Virtex6 devices?
        140981: 09/06/01: Antti.Lukats@googlemail.com: Re: Maximum tilemap size for Virtex6 devices?
140983: 09/06/01: jack.gassett: Open Source FPGA circuit design.
    140984: 09/06/01: Matthew Hicks: Re: Open Source FPGA circuit design.
    140986: 09/06/01: Rich Webb: Re: Open Source FPGA circuit design.
        141003: 09/06/02: Rich Webb: Re: Open Source FPGA circuit design.
        141013: 09/06/02: MikeWhy: Re: Open Source FPGA circuit design.
        141031: 09/06/02: Nico Coesel: Re: Open Source FPGA circuit design.
    141001: 09/06/02: jack.gassett: Re: Open Source FPGA circuit design.
140987: 09/06/01: <soar2morrow@yahoo.com>: Has anyone tried to install a Xilinx floating license? The
    140989: 09/06/01: phil hays: Re: Has anyone tried to install a Xilinx floating license? The
        140993: 09/06/01: MikeWhy: Re: Has anyone tried to install a Xilinx floating license? The documentation (UG631 (v 11.1.0) April 27, 2009) says that the required
            140998: 09/06/02: MikeWhy: Re: Has anyone tried to install a Xilinx floating license? The documentation (UG631 (v 11.1.0) April 27, 2009) says that the required
        141000: 09/06/02: Andreas Ehliar: Re: Has anyone tried to install a Xilinx floating license? The documentation (UG631 (v 11.1.0) April 27, 2009) says that the required
    140991: 09/06/01: <soar2morrow@yahoo.com>: Re: Has anyone tried to install a Xilinx floating license? The
    140997: 09/06/01: <soar2morrow@yahoo.com>: Re: Has anyone tried to install a Xilinx floating license? The
    141008: 09/06/02: OutputLogic: Re: Has anyone tried to install a Xilinx floating license? The
    141040: 09/06/03: Allan Herriman: Re: Has anyone tried to install a Xilinx floating license? The
        141047: 09/06/03: MM: Re: Has anyone tried to install a Xilinx floating license? The documentation (UG631 (v 11.1.0) April 27, 2009) says that the required
            141091: 09/06/04: MM: Re: Has anyone tried to install a Xilinx floating license? The documentation (UG631 (v 11.1.0) April 27, 2009) says that the required
    141052: 09/06/04: Allan Herriman: Re: Has anyone tried to install a Xilinx floating license? The
141002: 09/06/02: <chenyong20000@gmail.com>: how to run synplify & ise in tcl?
141005: 09/06/02: Bond: the reach of VHDL
    141006: 09/06/02: glen herrmannsfeldt: Re: the reach of VHDL
    141009: 09/06/02: Jonathan Bromley: Re: the reach of VHDL
    141012: 09/06/02: doug: Re: the reach of VHDL
    141051: 09/06/04: whygee: Re: the reach of VHDL
        141077: 09/06/04: MikeWhy: Re: the reach of VHDL
            141081: 09/06/04: whygee: Re: the reach of VHDL
                141085: 09/06/04: MikeWhy: Re: the reach of VHDL
    141074: 09/06/04: Bond: Re: the reach of VHDL
141007: 09/06/02: Joseph H Allen: Tektronix vs. Agilent, probes
    141011: 09/06/02: John Devereux: Re: Tektronix vs. Agilent, probes
    141015: 09/06/02: Joel Koltner: Re: Tektronix vs. Agilent, probes
        141017: 09/06/02: Joseph H Allen: Re: Tektronix vs. Agilent, probes
            141065: 09/06/04: JosephKK: Re: Tektronix vs. Agilent, probes
141014: 09/06/02: Antti: Xilinx GbE performance
    141025: 09/06/02: OutputLogic: Re: Xilinx GbE performance
    141027: 09/06/02: Antti.Lukats@googlemail.com: Re: Xilinx GbE performance
141019: 09/06/02: Jan Pech: Re: Xilinx GbE performance
    141020: 09/06/02: Antti.Lukats@googlemail.com: Re: Xilinx GbE performance
        141021: 09/06/02: Phil Jessop: Re: Xilinx GbE performance
        141032: 09/06/02: MM: Re: Xilinx GbE performance
    141022: 09/06/02: Jan Pech: Re: Xilinx GbE performance
    141023: 09/06/02: Jan Pech: Re: Xilinx GbE performance
    141024: 09/06/02: Antti.Lukats@googlemail.com: Re: Xilinx GbE performance
    141026: 09/06/02: Antti.Lukats@googlemail.com: Re: Xilinx GbE performance
    141028: 09/06/02: Antti.Lukats@googlemail.com: Re: Xilinx GbE performance
    141042: 09/06/03: john.orlando@gmail.com: Re: Xilinx GbE performance
    141043: 09/06/03: OutputLogic: Re: Xilinx GbE performance
    141118: 09/06/07: Bert_Paris: Re: Xilinx GbE performance
141033: 09/06/02: <namth299@gmail.com>: error with xps_ll_temac
141034: 09/06/02: Venkat: BRAM/LUT Comparison
    141036: 09/06/03: Frank Buss: Re: BRAM/LUT Comparison
    141037: 09/06/02: <goouse@twinmail.de>: Re: BRAM/LUT Comparison
    141038: 09/06/02: Mike Treseler: Re: BRAM/LUT Comparison
    141039: 09/06/02: Venkat: Re: BRAM/LUT Comparison
    141045: 09/06/03: General Schvantzkoph: Re: BRAM/LUT Comparison
141041: 09/06/03: Real SoPC New-Be: Xilinx ISE doesn't recognize a signal added in Xilinx Platform Studio
    141044: 09/06/03: MM: Re: Xilinx ISE doesn't recognize a signal added in Xilinx Platform Studio
        141068: 09/06/04: MM: Re: Xilinx ISE doesn't recognize a signal added in Xilinx Platform Studio
    141054: 09/06/03: Real SoPC New-Be: Re: Xilinx ISE doesn't recognize a signal added in Xilinx Platform
    141113: 09/06/06: Marteno Rodia: Re: Xilinx ISE doesn't recognize a signal added in Xilinx Platform
141048: 09/06/03: maxascent: Secure netlist
    141049: 09/06/03: Mike Treseler: Re: Secure netlist
    141050: 09/06/03: Muzaffer Kal: Re: Secure netlist
        141056: 09/06/04: maxascent: Re: Secure netlist
141055: 09/06/04: Marc Kelly: Help with Remote debugging ideas.
    141078: 09/06/04: Mike Treseler: Re: Help with Remote debugging ideas.
        141080: 09/06/04: Marc Kelly: Re: Help with Remote debugging ideas.
            141084: 09/06/04: Marc Kelly: Re: Help with Remote debugging ideas.
                141097: 09/06/05: Alan Fitch: Re: Help with Remote debugging ideas.
                    141126: 09/06/07: Marc Kelly: Re: Help with Remote debugging ideas.
                141101: 09/06/05: Petter Gustad: Re: Help with Remote debugging ideas.
    141082: 09/06/04: gabor: Re: Help with Remote debugging ideas.
    141088: 09/06/04: OutputLogic: Re: Help with Remote debugging ideas.
        141123: 09/06/07: MikeWhy: Re: Help with Remote debugging ideas.
    141095: 09/06/05: Petter Gustad: Re: Help with Remote debugging ideas.
    141100: 09/06/05: JuanC: Re: Help with Remote debugging ideas.
141057: 09/06/04: Jaco Naude: Xilinx FIR Compiler gives zero only output in hardware
    141058: 09/06/04: <jon@beniston.com>: Re: Xilinx FIR Compiler gives zero only output in hardware
    141094: 09/06/04: Jaco Naude: Re: Xilinx FIR Compiler gives zero only output in hardware
    141098: 09/06/05: <ales.gorkic@gmail.com>: Re: Xilinx FIR Compiler gives zero only output in hardware
141059: 09/06/04: PeterUK: Urgent help with a Simple AND simulation
    141066: 09/06/04: MikeWhy: Re: Urgent help with a Simple AND simulation
    141075: 09/06/04: Rob Gaddi: Re: Urgent help with a Simple AND simulation
141060: 09/06/04: anushina: Need help VHDL code 5-to-7 decoder (Xilinx)
    141069: 09/06/04: anushina: Re: Need help VHDL code 5-to-7 decoder (Xilinx)
    141072: 09/06/04: MikeWhy: Re: Need help VHDL code 5-to-7 decoder (Xilinx)
141061: 09/06/04: Biswarup: ACTEL 8051s core
    141067: 09/06/04: Antti.Lukats@googlemail.com: Re: ACTEL 8051s core
141063: 09/06/04: Tiwana: Dumb questions needs urgent answer
141064: 09/06/04: haowen: how to write data to a register in the FPGA
    141071: 09/06/04: Andrew Holme: Re: how to write data to a register in the FPGA
141070: 09/06/04: LittleAlex: Re: Has anyone tried to install a Xilinx floating license? The
141083: 09/06/04: VIPS: I2C SDA LINE
    141086: 09/06/04: gabor: Re: I2C SDA LINE
141087: 09/06/04: DAJ: How to generate clocks of higher frequency?
    141090: 09/06/04: <soar2morrow@yahoo.com>: Re: How to generate clocks of higher frequency?
    141093: 09/06/04: Jaco Naude: Re: How to generate clocks of higher frequency?
    141096: 09/06/05: Symon: Re: How to generate clocks of higher frequency?
141089: 09/06/04: <soar2morrow@yahoo.com>: Re: Has anyone tried to install a Xilinx floating license? The
141099: 09/06/05: <plaquidara@gmail.com>: Actel Fusion AFS600 FPGA Flash Memory Bug
    141102: 09/06/05: whygee: Re: Actel Fusion AFS600 FPGA Flash Memory Bug
141104: 09/06/05: wallge: digital RGB Video to Analog VGA triple DAC question
    141106: 09/06/05: Nico Coesel: Re: digital RGB Video to Analog VGA triple DAC question
    141107: 09/06/05: glen herrmannsfeldt: Re: digital RGB Video to Analog VGA triple DAC question
        141111: 09/06/06: Mike Harrison: Re: digital RGB Video to Analog VGA triple DAC question
            141114: 09/06/06: Mike Harrison: Re: digital RGB Video to Analog VGA triple DAC question
            141134: 09/06/08: Martin Thompson: Re: digital RGB Video to Analog VGA triple DAC question
    141109: 09/06/05: Rob Gaddi: Re: digital RGB Video to Analog VGA triple DAC question
    141110: 09/06/05: gabor: Re: digital RGB Video to Analog VGA triple DAC question
    141112: 09/06/06: wallge: Re: digital RGB Video to Analog VGA triple DAC question
    141115: 09/06/06: Sandro: Re: digital RGB Video to Analog VGA triple DAC question
    141117: 09/06/07: Bert_Paris: Re: digital RGB Video to Analog VGA triple DAC question
        141122: 09/06/07: Nico Coesel: Re: digital RGB Video to Analog VGA triple DAC question
141116: 09/06/06: <monurlu@gmail.com>: Microblaze and external block memory
    141119: 09/06/06: MikeWhy: Re: Microblaze and external block memory
141120: 09/06/07: rosaldorosa: clock skew as an asset
    141121: 09/06/07: rosaldorosa: Re: clock skew as an asset
        141125: 09/06/07: Matthew Hicks: Re: clock skew as an asset
141124: 09/06/07: iquadri: Power Estimation for Dynamic Reconfiguration
    141127: 09/06/07: Moazzam: Re: Power Estimation for Dynamic Reconfiguration
141128: 09/06/07: Venkat: Virtex 5 LUT Outpus
    141139: 09/06/08: john: Re: Virtex 5 LUT Outpus
    141197: 09/06/10: OutputLogic: Re: Virtex 5 LUT Outpus
    141199: 09/06/10: Antti.Lukats@googlemail.com: Re: Virtex 5 LUT Outpus
141129: 09/06/08: DAJ: refresh to refresh period
    141137: 09/06/08: rickman: Re: refresh to refresh period
141131: 09/06/08: Brane2: Where are new Xilinx FPGAs ?
    141133: 09/06/08: Antti.Lukats@googlemail.com: Re: Where are new Xilinx FPGAs ?
    141138: 09/06/08: Kolja: Re: Where are new Xilinx FPGAs ?
141135: 09/06/08: maxascent: ISE 11.1
    141154: 09/06/09: Mike Treseler: Re: ISE 11.1
    141155: 09/06/09: OutputLogic: Re: ISE 11.1
        141158: 09/06/09: maxascent: Re: ISE 11.1
    141166: 09/06/10: Allan Herriman: Re: ISE 11.1
141136: 09/06/08: maxascent: Xilinx Block RAM Sim
    141140: 09/06/08: LittleAlex: Re: Xilinx Block RAM Sim
        141141: 09/06/08: maxascent: Re: Xilinx Block RAM Sim
            141143: 09/06/08: maxascent: Re: Xilinx Block RAM Sim
                141144: 09/06/08: Fredxx: Re: Xilinx Block RAM Sim
                141147: 09/06/08: Mike Treseler: Re: Xilinx Block RAM Sim
                141157: 09/06/09: Mike Treseler: Re: Xilinx Block RAM Sim
                    141164: 09/06/10: Matthew Hicks: Re: Xilinx Block RAM Sim
                        141165: 09/06/09: john: Re: Xilinx Block RAM Sim
                            141336: 09/06/19: ??: Re: Xilinx Block RAM Sim
                        141175: 09/06/10: rickman: Re: Xilinx Block RAM Sim
                141159: 09/06/09: maxascent: Re: Xilinx Block RAM Sim
                    141160: 09/06/09: Mike Treseler: Re: Xilinx Block RAM Sim
                    141162: 09/06/09: Jonathan Bromley: Re: Xilinx Block RAM Sim
                    141181: 09/06/10: Jonathan Bromley: Re: Xilinx Block RAM Sim
    141142: 09/06/08: Rob Gaddi: Re: Xilinx Block RAM Sim
    141145: 09/06/08: Andy Peters: Re: Xilinx Block RAM Sim
    141148: 09/06/08: gabor: Re: Xilinx Block RAM Sim
    141156: 09/06/09: rickman: Re: Xilinx Block RAM Sim
    141163: 09/06/09: rickman: Re: Xilinx Block RAM Sim
    141167: 09/06/10: Allan Herriman: Re: Xilinx Block RAM Sim
    141169: 09/06/10: OutputLogic: Re: Xilinx Block RAM Sim
        141170: 09/06/10: maxascent: Re: Xilinx Block RAM Sim
    141176: 09/06/10: rickman: Re: Xilinx Block RAM Sim
    141225: 09/06/11: rickman: Re: Xilinx Block RAM Sim
    141236: 09/06/11: Prevailing over Technology: Re: Xilinx Block RAM Sim
141149: 09/06/08: <news-support@sbcglobal.net>: AT&T Usenet Netnews Service Shutting Down
    141150: 09/06/08: MikeWhy: Re: AT&T Usenet Netnews Service Shutting Down
        141237: 09/06/11: Prevailing over Technology: Re: AT&T Usenet Netnews Service Shutting Down
141151: 09/06/09: david wang: dsp with fpgas by Uwe Meyer-Baese
    141152: 09/06/09: james: Re: dsp with fpgas by Uwe Meyer-Baese
        141153: 09/06/09: Dave: Re: dsp with fpgas by Uwe Meyer-Baese
    141161: 09/06/09: wallge: Re: dsp with fpgas by Uwe Meyer-Baese
141168: 09/06/10: recoder: IF board for fpga?
    141174: 09/06/10: Moti Litochevski: Re: IF board for fpga?
        141200: 09/06/11: Al Clark: Re: IF board for fpga?
    141193: 09/06/11: Marty Ryba: Re: IF board for fpga?
    141221: 09/06/11: Sebastien @ Sundance: Re: IF board for fpga?
    141509: 09/06/26: Kolja: Re: IF board for fpga?
        141542: 09/06/27: Al Clark: Re: IF board for fpga?
141171: 09/06/10: whygee: async. SRAM control signal generation
    141172: 09/06/10: Antti.Lukats@googlemail.com: Re: async. SRAM control signal generation
        141177: 09/06/10: whygee: Re: async. SRAM control signal generation
        141180: 09/06/10: whygee: Re: async. SRAM control signal generation
    141173: 09/06/10: Jacko: Re: async. SRAM control signal generation
    141179: 09/06/10: john: Re: async. SRAM control signal generation
        141183: 09/06/10: whygee: Re: async. SRAM control signal generation
    141259: 09/06/12: Antti.Lukats@googlemail.com: Re: async. SRAM control signal generation
        141262: 09/06/13: whygee: Re: async. SRAM control signal generation
    141260: 09/06/12: Antti.Lukats@googlemail.com: Re: async. SRAM control signal generation
141178: 09/06/10: Biswarup: Actel HAL
141182: 09/06/10: Pablo: Use XMD to configure more than one board
    141184: 09/06/10: MM: Re: Use XMD to configure more than one board
        141187: 09/06/10: MM: Re: Use XMD to configure more than one board
    141185: 09/06/10: Pablo: Re: Use XMD to configure more than one board
    141204: 09/06/11: Pablo: Re: Use XMD to configure more than one board
141186: 09/06/10: Pablo: Error in FSL Bus
    141202: 09/06/10: Goran_Bilski: Re: Error in FSL Bus
    141205: 09/06/11: Pablo: Re: Error in FSL Bus
    141241: 09/06/12: Goran_Bilski: Re: Error in FSL Bus
141188: 09/06/10: fl: What the switch of FFT implementation in FPGA for
    141189: 09/06/10: Weng Tianxiang: Re: What the switch of FFT implementation in FPGA for
141190: 09/06/10: zubinkumar: USB3300 - Xilinx ML401 interface
    141194: 09/06/10: LittleAlex: Re: USB3300 - Xilinx ML401 interface
        141258: 09/06/12: MikeWhy: Re: USB3300 - Xilinx ML401 interface
141191: 09/06/10: Manfred: Virtex 2 Pro IO Banks Vcco
    141332: 09/06/18: vertago1: Re: Virtex 2 Pro IO Banks Vcco
    141343: 09/06/19: austin: Re: Virtex 2 Pro IO Banks Vcco
    141344: 09/06/19: austin: Re: Virtex 2 Pro IO Banks Vcco
    141352: 09/06/19: Ed McGettigan: Re: Virtex 2 Pro IO Banks Vcco
141196: 09/06/10: OutputLogic: Safe margin in FPGA static timing analysis
    141198: 09/06/11: MM: Re: Safe margin in FPGA static timing analysis
    141203: 09/06/11: zeeman_be: Re: Safe margin in FPGA static timing analysis
    141215: 09/06/11: Nathan Bialke: Re: Safe margin in FPGA static timing analysis
    141219: 09/06/11: Andy: Re: Safe margin in FPGA static timing analysis
    141227: 09/06/11: whygee: Re: Safe margin in FPGA static timing analysis
    141228: 09/06/11: rickman: Re: Safe margin in FPGA static timing analysis
    141232: 09/06/11: austin: Re: Safe margin in FPGA static timing analysis
    141234: 09/06/11: Muzaffer Kal: Re: Safe margin in FPGA static timing analysis
141201: 09/06/11: jayantbala: XILINX WEB SERVER DEMO
    141213: 09/06/11: radarman: Re: XILINX WEB SERVER DEMO
141207: 09/06/11: Antti: opencores shut down?
    141208: 09/06/11: HT-Lab: Re: opencores shut down?
        141210: 09/06/11: RCIngham: Re: opencores shut down?
        141211: 09/06/11: Symon: Re: opencores shut down?
    141209: 09/06/11: Antti.Lukats@googlemail.com: Re: opencores shut down?
    141212: 09/06/11: Sandro: Re: opencores shut down?
141216: 09/06/11: Rob Gaddi: Latest Xilinx Discontinuations
    141217: 09/06/11: austin: Re: Latest Xilinx Discontinuations
        141218: 09/06/11: Antti.Lukats@googlemail.com: Re: Latest Xilinx Discontinuations
        141220: 09/06/11: Mike Harrison: Re: Latest Xilinx Discontinuations
        141224: 09/06/11: -jg: Re: Latest Xilinx Discontinuations
        141231: 09/06/11: austin: Re: Latest Xilinx Discontinuations
        141240: 09/06/11: Antti.Lukats@googlemail.com: Re: Latest Xilinx Discontinuations
        141243: 09/06/12: Symon: Re: Latest Xilinx Discontinuations
    141235: 09/06/11: Prevailing over Technology: Re: Latest Xilinx Discontinuations
141222: 09/06/11: john: ISE 10.1 Free Downlaod Web Install
    141238: 09/06/12: Brian Drummond: Re: ISE 10.1 Free Downlaod Web Install
141229: 09/06/11: John Blyler: ASIC Proto and Verif with FPGA survey - Gift Certificate to Amazon
141233: 09/06/11: Andrew Holme: Fast carry chain
141242: 09/06/12: nachum: Verilog "for loop" - exit by setting i to exit value?
    141244: 09/06/12: Brian Drummond: Re: Verilog "for loop" - exit by setting i to exit value?
    141245: 09/06/12: Jonathan Bromley: Re: Verilog "for loop" - exit by setting i to exit value?
        141247: 09/06/12: Jonathan Bromley: Re: Verilog "for loop" - exit by setting i to exit value?
            141252: 09/06/12: Jonathan Bromley: Re: Verilog "for loop" - exit by setting i to exit value?
        141253: 09/06/12: glen herrmannsfeldt: Re: Verilog "for loop" - exit by setting i to exit value?
    141246: 09/06/12: nachumk: Re: Verilog "for loop" - exit by setting i to exit value?
    141249: 09/06/12: nachumk: Re: Verilog "for loop" - exit by setting i to exit value?
    141256: 09/06/12: Andy: Re: Verilog "for loop" - exit by setting i to exit value?
    141267: 09/06/14: nachumk: Re: Verilog "for loop" - exit by setting i to exit value?
141248: 09/06/12: wallge: NTSC/PAL Encoder using FPGA and DAC
    141250: 09/06/12: Pete Fraser: Re: NTSC/PAL Encoder using FPGA and DAC
    141251: 09/06/12: Curt Johnson: Re: NTSC/PAL Encoder using FPGA and DAC
    141254: 09/06/12: glen herrmannsfeldt: Re: NTSC/PAL Encoder using FPGA and DAC
        141255: 09/06/12: whygee: Re: NTSC/PAL Encoder using FPGA and DAC
    141257: 09/06/12: -jg: Re: NTSC/PAL Encoder using FPGA and DAC
    141302: 09/06/16: gabor: Re: NTSC/PAL Encoder using FPGA and DAC
141261: 09/06/13: iquadri: Correlation Algorithm: converting user type integer array into
    141263: 09/06/13: Jonathan Bromley: Re: Correlation Algorithm: converting user type integer array into std_logic_vector
        141264: 09/06/14: Brian Drummond: Re: Correlation Algorithm: converting user type integer array into std_logic_vector
            141265: 09/06/14: Jonathan Bromley: Re: Correlation Algorithm: converting user type integer array into std_logic_vector
    141266: 09/06/14: iquadri: Re: Correlation Algorithm: converting user type integer array into
141268: 09/06/14: Weng Tianxiang: About Altera patent application "Logic Cell Supporting Addition of
    141272: 09/06/15: rickman: Re: About Altera patent application "Logic Cell Supporting Addition
        141277: 09/06/15: Markus: Re: About Altera patent application "Logic Cell Supporting Addition
        141287: 09/06/15: Muzaffer Kal: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words"
    141274: 09/06/15: Weng Tianxiang: Re: About Altera patent application "Logic Cell Supporting Addition
    141279: 09/06/15: rickman: Re: About Altera patent application "Logic Cell Supporting Addition
    141280: 09/06/15: Weng Tianxiang: Re: About Altera patent application "Logic Cell Supporting Addition
    141281: 09/06/15: OutputLogic: Re: About Altera patent application "Logic Cell Supporting Addition
        141309: 09/06/16: Chris Abele: Re: About Altera patent application "Logic Cell Supporting Addition
            141310: 09/06/16: Chris Abele: Re: About Altera patent application "Logic Cell Supporting Addition
    141283: 09/06/15: Weng Tianxiang: Re: About Altera patent application "Logic Cell Supporting Addition
    141285: 09/06/15: Weng Tianxiang: Re: About Altera patent application "Logic Cell Supporting Addition
    141286: 09/06/15: Weng Tianxiang: Re: About Altera patent application "Logic Cell Supporting Addition
    141289: 09/06/15: Weng Tianxiang: Re: About Altera patent application "Logic Cell Supporting Addition
    141291: 09/06/15: rickman: Re: About Altera patent application "Logic Cell Supporting Addition
    141292: 09/06/15: rickman: Re: About Altera patent application "Logic Cell Supporting Addition
    141293: 09/06/15: rickman: Re: About Altera patent application "Logic Cell Supporting Addition
    141298: 09/06/16: Weng Tianxiang: Re: About Altera patent application "Logic Cell Supporting Addition
    141299: 09/06/16: Weng Tianxiang: Re: About Altera patent application "Logic Cell Supporting Addition
    141303: 09/06/16: rickman: Re: About Altera patent application "Logic Cell Supporting Addition
    141306: 09/06/16: Weng Tianxiang: Re: About Altera patent application "Logic Cell Supporting Addition
    141311: 09/06/16: Weng Tianxiang: Re: About Altera patent application "Logic Cell Supporting Addition
141269: 09/06/15: Antti: Xilinx bitstream decompiler has been made and working
    141270: 09/06/15: h.e.: Re: Xilinx bitstream decompiler has been made and working
    141271: 09/06/15: Antti.Lukats@googlemail.com: Re: Xilinx bitstream decompiler has been made and working
141273: 09/06/15: Test01: How to convert from 2x data rate signals to 1x data rate signals
    141278: 09/06/15: rickman: Re: How to convert from 2x data rate signals to 1x data rate signals
    141284: 09/06/15: Test01: Re: How to convert from 2x data rate signals to 1x data rate signals
    141290: 09/06/15: rickman: Re: How to convert from 2x data rate signals to 1x data rate signals
141275: 09/06/15: namit: bidirectional buffer
    141282: 09/06/15: Phil Jessop: Re: bidirectional buffer
141276: 09/06/15: janigav: Ethernet y MicroBlaze with Spartan 3e starter kit
    141288: 09/06/16: argee: Re: Ethernet y MicroBlaze with Spartan 3e starter kit
141294: 09/06/16: luudee: BSB/XBD Problem
141295: 09/06/16: hassen Karray: what is non-aligned -- memory accesses ?
    141296: 09/06/16: Nobby Anderson: Re: what is non-aligned -- memory accesses ?
    141297: 09/06/16: Andy: Re: what is non-aligned -- memory accesses ?
141300: 09/06/16: RonGr: Cortex M1 and GUI
    151335: 11/03/24: yjhgj: Re: Cortex M1 and GUI
141301: 09/06/16: Weng Tianxiang: Do you know how aggressive the patent fighting between Xilinx and
    141313: 09/06/17: Jon: Re: Do you know how aggressive the patent fighting between Xilinx and
        141322: 09/06/17: Ed McGettigan: Re: Do you know how aggressive the patent fighting between Xilinx
    141314: 09/06/17: Weng Tianxiang: Re: Do you know how aggressive the patent fighting between Xilinx and
    141316: 09/06/17: Andy: Re: Do you know how aggressive the patent fighting between Xilinx and
    141317: 09/06/17: Weng Tianxiang: Re: Do you know how aggressive the patent fighting between Xilinx and
    141321: 09/06/17: james: Re: Do you know how aggressive the patent fighting between Xilinx and Altera is going?
    141323: 09/06/17: Weng Tianxiang: Re: Do you know how aggressive the patent fighting between Xilinx and
141304: 09/06/16: demod: QPSK demod development: Integration problems
    141307: 09/06/16: John: Re: QPSK demod development: Integration problems
141305: 09/06/16: wallge: 5.0V and 3.3V PCI interfacing with Altera Cyclone III
    141308: 09/06/16: John Adair: Re: 5.0V and 3.3V PCI interfacing with Altera Cyclone III
    141312: 09/06/17: Nial Stewart: Re: 5.0V and 3.3V PCI interfacing with Altera Cyclone III
    141318: 09/06/17: MM: Re: 5.0V and 3.3V PCI interfacing with Altera Cyclone III
        141327: 09/06/18: Nial Stewart: Re: 5.0V and 3.3V PCI interfacing with Altera Cyclone III
    141319: 09/06/17: radarman: Re: 5.0V and 3.3V PCI interfacing with Altera Cyclone III
    141320: 09/06/17: wallge: Re: 5.0V and 3.3V PCI interfacing with Altera Cyclone III
141315: 09/06/17: <newsmaster@bellsouth.net>: AT&T Usenet Netnews Service Shutting Down
141324: 09/06/18: Phil Jessop: Re: Preselection counter in verilog
141325: 09/06/18: skyworld: synplify script for constraint
    141329: 09/06/18: skyworld: Re: synplify script for constraint
        141330: 09/06/18: Mike Treseler: Re: synplify script for constraint
            141347: 09/06/19: Mike Treseler: Re: synplify script for constraint
    141333: 09/06/18: skyworld: Re: synplify script for constraint
    141339: 09/06/18: skyworld: Re: synplify script for constraint
141326: 09/06/18: Marc Jet: ISC_DNA over JTAG in Spartan3A-DSP?
    141328: 09/06/18: Uwe Bonnes: Re: ISC_DNA over JTAG in Spartan3A-DSP?
141331: 09/06/18: Antti: Lattice XP3 any infos leaked? ;)
141338: 09/06/18: Jay K: Spartan 3A vs 3E SSO guidelines
    141341: 09/06/19: gabor: Re: Spartan 3A vs 3E SSO guidelines
141340: 09/06/19: fl: How to set environment to ModelsimXE
    141345: 09/06/19: HT-Lab: Re: How to set environment to ModelsimXE
141342: 09/06/19: Serkan: set dont touch in Xilinx Xst
    141350: 09/06/19: Muzaffer Kal: Re: set dont touch in Xilinx Xst
    141374: 09/06/21: Serkan: Re: set dont touch in Xilinx Xst
141346: 09/06/19: <lenz19@gmx.de>: FDRSE Spartan 3A - Active high/low set/reset
    141348: 09/06/19: Rob Gaddi: Re: FDRSE Spartan 3A - Active high/low set/reset
        141358: 09/06/20: Andreas Ehliar: Re: FDRSE Spartan 3A - Active high/low set/reset
    141349: 09/06/19: john: Re: FDRSE Spartan 3A - Active high/low set/reset
    141355: 09/06/19: <lenz19@gmx.de>: Re: FDRSE Spartan 3A - Active high/low set/reset
    141356: 09/06/19: Rob Gaddi: Re: FDRSE Spartan 3A - Active high/low set/reset
        141359: 09/06/19: Ed McGettigan: Re: FDRSE Spartan 3A - Active high/low set/reset
    141357: 09/06/19: <lenz19@gmx.de>: Re: FDRSE Spartan 3A - Active high/low set/reset
    141370: 09/06/21: <lenz19@gmx.de>: Re: FDRSE Spartan 3A - Active high/low set/reset
    141380: 09/06/22: Rob Gaddi: Re: FDRSE Spartan 3A - Active high/low set/reset
141351: 09/06/19: Dr. Thomas Ansorg: Preselection counter in verilog
    141360: 09/06/20: Phil Jessop: Re: Preselection counter in verilog (Verilog Version)
        141363: 09/06/20: Dr. Thomas Ansorg: Re: Preselection counter in verilog (Verilog Version)
141353: 09/06/19: John Speth: Lookup table in VHDL?
    141354: 09/06/19: Mike Treseler: Re: Lookup table in VHDL?
        141361: 09/06/20: John Speth: Re: Lookup table in VHDL?
141362: 09/06/20: timinganalyzer: TimingAnalyzer is now freeware
    141365: 09/06/20: Antti.Lukats@googlemail.com: Re: TimingAnalyzer is now freeware
    141366: 09/06/20: chewie: Re: TimingAnalyzer is now freeware
    141681: 09/07/03: James Harris: Re: TimingAnalyzer is now freeware
    141686: 09/07/03: chewie: Re: TimingAnalyzer is now freeware
    141750: 09/07/06: Petrov: Re: TimingAnalyzer is now freeware
141364: 09/06/20: john.lv: How to access Plx 8311 doorbell register?
141367: 09/06/20: Benjamin Krill: Re: TimingAnalyzer is now freeware
    141368: 09/06/20: chewie: Re: TimingAnalyzer is now freeware
        141369: 09/06/20: OutputLogic: Re: TimingAnalyzer is now freeware
141371: 09/06/21: rickman: Subtleties of Booth's Algorithm Implementation
    141372: 09/06/21: Muzaffer Kal: Re: Subtleties of Booth's Algorithm Implementation
        141375: 09/06/22: Muzaffer Kal: Re: Subtleties of Booth's Algorithm Implementation
            141384: 09/06/22: Andy Botterill: Re: Subtleties of Booth's Algorithm Implementation
                141399: 09/06/23: Andy Botterill: Re: Subtleties of Booth's Algorithm Implementation
    141373: 09/06/21: Weng Tianxiang: Re: Subtleties of Booth's Algorithm Implementation
    141379: 09/06/22: Weng Tianxiang: Re: Subtleties of Booth's Algorithm Implementation
    141383: 09/06/22: Mike Treseler: Re: Subtleties of Booth's Algorithm Implementation
        141387: 09/06/22: Muzaffer Kal: Re: Subtleties of Booth's Algorithm Implementation
            141389: 09/06/22: Jonathan Bromley: Re: Subtleties of Booth's Algorithm Implementation
            141391: 09/06/22: Mike Treseler: Re: Subtleties of Booth's Algorithm Implementation
        141397: 09/06/22: Mike Treseler: Re: Subtleties of Booth's Algorithm Implementation
            141440: 09/06/24: Mike Treseler: Re: Subtleties of Booth's Algorithm Implementation
                141732: 09/07/05: Andy Botterill: Re: Subtleties of Booth's Algorithm Implementation
                    141735: 09/07/05: Andy Botterill: Re: Subtleties of Booth's Algorithm Implementation
    141388: 09/06/22: Weng Tianxiang: Re: Subtleties of Booth's Algorithm Implementation
    141395: 09/06/22: rickman: Re: Subtleties of Booth's Algorithm Implementation
    141396: 09/06/22: rickman: Re: Subtleties of Booth's Algorithm Implementation
    141398: 09/06/22: rickman: Re: Subtleties of Booth's Algorithm Implementation
    141407: 09/06/23: rickman: Re: Subtleties of Booth's Algorithm Implementation
    141416: 09/06/23: Weng Tianxiang: Re: Subtleties of Booth's Algorithm Implementation
    141430: 09/06/24: rickman: Re: Subtleties of Booth's Algorithm Implementation
    141448: 09/06/24: Weng Tianxiang: Re: Subtleties of Booth's Algorithm Implementation
    141462: 09/06/24: rickman: Re: Subtleties of Booth's Algorithm Implementation
    141733: 09/07/05: rickman: Re: Subtleties of Booth's Algorithm Implementation
    141734: 09/07/05: rickman: Re: Subtleties of Booth's Algorithm Implementation
    141737: 09/07/05: rickman: Re: Subtleties of Booth's Algorithm Implementation
141376: 09/06/22: Ndf: Using SERDES to detect very high-speed pulse.
    141377: 09/06/22: Antti.Lukats@googlemail.com: Re: Using SERDES to detect very high-speed pulse.
141378: 09/06/22: GrIsH: problem with XPS and SDK!!
141381: 09/06/22: Test01: Question on FPGA driver
    141382: 09/06/22: Muzaffer Kal: Re: Question on FPGA driver
        141386: 09/06/22: Jonathan Bromley: Re: Question on FPGA driver
        141390: 09/06/22: Muzaffer Kal: Re: Question on FPGA driver
            141394: 09/06/22: glen herrmannsfeldt: Re: Question on FPGA driver
    141385: 09/06/22: Test01: Re: Question on FPGA driver
    141392: 09/06/22: Test01: Re: Question on FPGA driver
    141393: 09/06/22: Test01: Re: Question on FPGA driver
141400: 09/06/22: uche: UART testbench debug
    142961: 09/09/10: jaimico: Re: UART testbench debug
    142962: 09/09/10: johnp: Re: UART testbench debug
141401: 09/06/23: rajsinghdua: Interfacing microblaze with External RAM
141408: 09/06/23: David Fejes: 10gbit phy interface
    141409: 09/06/23: General Schvantzkoph: Re: 10gbit phy interface
141410: 09/06/23: Dr. Thomas Ansorg: index in arrays doesn't work
    141411: 09/06/23: Jonathan Bromley: Re: index in arrays doesn't work
        141412: 09/06/23: Dr. Thomas Ansorg: Re: index in arrays doesn't work
            141413: 09/06/23: Jonathan Bromley: Re: index in arrays doesn't work
        141414: 09/06/23: Dave: Re: index in arrays doesn't work
        141456: 09/06/24: Andy: Re: index in arrays doesn't work
    141415: 09/06/23: Mike Treseler: Re: index in arrays doesn't work
141417: 09/06/23: Aldorus: EPM7064 Altera PLD oe1\oe2\gclr1
    141418: 09/06/23: Mike Treseler: Re: EPM7064 Altera PLD oe1\oe2\gclr1
    141446: 09/06/24: Andrew Holme: Re: EPM7064 Altera PLD oe1\oe2\gclr1
    141498: 09/06/25: Aldorus: Re: EPM7064 Altera PLD oe1\oe2\gclr1
        141533: 09/06/26: Andrew Holme: Re: EPM7064 Altera PLD oe1\oe2\gclr1
141419: 09/06/23: kmawjood: XUPV2P board and EDK 10.1
141422: 09/06/24: oliver.hofherr@googlemail.com: How do you use multiple bitfiles with different designs on the same
141424: 09/06/24: Jonathan Bromley: True dual-port RAM in VHDL: XST question
    141425: 09/06/24: Fredxx: Re: True dual-port RAM in VHDL: XST question
        141426: 09/06/24: Jonathan Bromley: Re: True dual-port RAM in VHDL: XST question
            141427: 09/06/24: Fredxx: Re: True dual-port RAM in VHDL: XST question
                141428: 09/06/24: Jonathan Bromley: Re: True dual-port RAM in VHDL: XST question
                    141429: 09/06/24: Fredxx: Re: True dual-port RAM in VHDL: XST question
                    141432: 09/06/24: Fredxx: Re: True dual-port RAM in VHDL: XST question
                        141433: 09/06/24: Jonathan Bromley: Re: True dual-port RAM in VHDL: XST question
                            141436: 09/06/24: Fredxx: Re: True dual-port RAM in VHDL: XST question
                                141439: 09/06/24: Muzaffer Kal: Re: True dual-port RAM in VHDL: XST question
                                    141451: 09/06/24: Fredxx: Re: True dual-port RAM in VHDL: XST question
                        141435: 09/06/24: Ed McGettigan: Re: True dual-port RAM in VHDL: XST question
                        141437: 09/06/24: Fredxx: Re: True dual-port RAM in VHDL: XST question
                    141442: 09/06/24: Jonathan Bromley: Re: True dual-port RAM in VHDL: XST question
                        141444: 09/06/24: Muzaffer Kal: Re: True dual-port RAM in VHDL: XST question
                            141472: 09/06/25: Nial Stewart: Re: True dual-port RAM in VHDL: XST question
                            141484: 09/06/25: Muzaffer Kal: Re: True dual-port RAM in VHDL: XST question
                                141495: 09/06/25: Jonathan Bromley: Re: True dual-port RAM in VHDL: XST question
                                    141527: 09/06/26: Mike Treseler: Re: True dual-port RAM in VHDL: XST question
                            141514: 09/06/26: Fredxx: Re: True dual-port RAM in VHDL: XST question
                                141528: 09/06/26: Mike Treseler: Re: True dual-port RAM in VHDL: XST question
                                    141564: 09/06/28: Fredxx: Re: True dual-port RAM in VHDL: XST question
                                        141573: 09/06/28: Mike Treseler: Re: True dual-port RAM in VHDL: XST question
                                            141574: 09/06/28: Mike Treseler: Re: True dual-port RAM in VHDL: XST question -typo
                                            141576: 09/06/28: Fredxx: Re: True dual-port RAM in VHDL: XST question
                        141449: 09/06/24: Mike Treseler: Re: True dual-port RAM in VHDL: XST question
                141515: 09/06/26: Andy: Re: True dual-port RAM in VHDL: XST question
            141443: 09/06/24: Jonathan Bromley: Re: True dual-port RAM in VHDL: XST question
                141470: 09/06/25: Martin Thompson: Re: True dual-port RAM in VHDL: XST question
        141431: 09/06/24: rickman: Re: True dual-port RAM in VHDL: XST question
        141434: 09/06/24: rickman: Re: True dual-port RAM in VHDL: XST question
        141438: 09/06/24: Sandro: Re: True dual-port RAM in VHDL: XST question
        141441: 09/06/24: Andy: Re: True dual-port RAM in VHDL: XST question
        141452: 09/06/24: Andy Peters: Re: True dual-port RAM in VHDL: XST question
        141461: 09/06/24: Alex: Re: True dual-port RAM in VHDL: XST question
        141475: 09/06/25: sleeman: Re: True dual-port RAM in VHDL: XST question
        141481: 09/06/25: rickman: Re: True dual-port RAM in VHDL: XST question
        141491: 09/06/25: rickman: Re: True dual-port RAM in VHDL: XST question
        141613: 09/06/30: rickman: Re: True dual-port RAM in VHDL: XST question
    141511: 09/06/26: Jonathan Bromley: Re: True dual-port RAM in VHDL: XST question
    141590: 09/06/29: Jonathan Bromley: Re: True dual-port RAM in VHDL: XST question
141450: 09/06/24: Antti: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141454: 09/06/24: Andy: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141455: 09/06/24: Antti.Lukats@googlemail.com: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141457: 09/06/24: Fredxx: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141503: 09/06/25: Ed McGettigan: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141504: 09/06/25: Manny: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141521: 09/06/26: Prevailing over Technology: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
        141526: 09/06/26: glen herrmannsfeldt: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
            141532: 09/06/26: glen herrmannsfeldt: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
                141540: 09/06/26: KJ: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
            141534: 09/06/26: Nico Coesel: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
        141539: 09/06/26: Ed McGettigan: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
            141541: 09/06/27: glen herrmannsfeldt: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
            141556: 09/06/27: Ed McGettigan: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141523: 09/06/26: Antti.Lukats@googlemail.com: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141529: 09/06/26: Antti.Lukats@googlemail.com: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141537: 09/06/26: -jg: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141538: 09/06/26: rickman: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141543: 09/06/26: Antti.Lukats@googlemail.com: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
    141549: 09/06/27: -jg: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
141453: 09/06/24: recoder: 720 Mhz IF Processing
    141458: 09/06/24: Steve Pope: Re: 720 Mhz IF Processing
    141464: 09/06/25: recoder: Re: 720 Mhz IF Processing
    141465: 09/06/25: Sebastien @ Sundance: Re: 720 Mhz IF Processing
        141486: 09/06/25: Eric Jacobsen: Re: 720 Mhz IF Processing
            141487: 09/06/25: Joerg: Re: 720 Mhz IF Processing
            141488: 09/06/25: Steve Pope: Re: 720 Mhz IF Processing
            141502: 09/06/25: Jerry Avins: Re: 720 Mhz IF Processing
                141505: 09/06/25: Joerg: Re: 720 Mhz IF Processing
        141492: 09/06/25: Josh Model: Re: 720 Mhz IF Processing
    141476: 09/06/25: recoder: Re: 720 Mhz IF Processing
    141489: 09/06/25: langwadt@fonz.dk: Re: 720 Mhz IF Processing
    141500: 09/06/25: Tim Wescott: Re: 720 Mhz IF Processing
    141510: 09/06/26: recoder: Re: 720 Mhz IF Processing
    141614: 09/06/30: Darol Klawetter: Re: 720 Mhz IF Processing
141460: 09/06/24: Pratap: Cable autodetection/programming the Xilinx Virtex2Pro FPGA failing.
    141493: 09/06/25: Chet: Re: Cable autodetection/programming the Xilinx Virtex2Pro FPGA failing.
    141497: 09/06/25: Pratap: Re: Cable autodetection/programming the Xilinx Virtex2Pro FPGA
141466: 09/06/25: urock: SRAM vs Flash based FPGA one more time
    141467: 09/06/25: Gael Paul: Re: SRAM vs Flash based FPGA one more time
    141471: 09/06/25: =?KOI8-R?B?4NLBIPLVzdHOw8XX?=: Re: SRAM vs Flash based FPGA one more time
    141473: 09/06/25: Nial Stewart: Re: SRAM vs Flash based FPGA one more time
    141474: 09/06/25: Antti.Lukats@googlemail.com: Re: SRAM vs Flash based FPGA one more time
    141477: 09/06/25: Kim Enkovaara: Re: SRAM vs Flash based FPGA one more time
    141482: 09/06/25: rickman: Re: SRAM vs Flash based FPGA one more time
    141494: 09/06/25: gabor: Re: SRAM vs Flash based FPGA one more time
    141496: 09/06/25: rickman: Re: SRAM vs Flash based FPGA one more time
    141501: 09/06/25: gabor: Re: SRAM vs Flash based FPGA one more time
141478: 09/06/25: Dirk Koch: Has anybody tried ISE for Virtex-6/Spartan-6?
    141479: 09/06/25: Antti.Lukats@googlemail.com: Re: Has anybody tried ISE for Virtex-6/Spartan-6?
    141480: 09/06/25: Antti.Lukats@googlemail.com: Re: Has anybody tried ISE for Virtex-6/Spartan-6?
    141483: 09/06/25: Antti.Lukats@googlemail.com: Re: Has anybody tried ISE for Virtex-6/Spartan-6?
    141490: 09/06/25: Antti.Lukats@googlemail.com: Re: Has anybody tried ISE for Virtex-6/Spartan-6?
141499: 09/06/25: Serkan: pre-initialized dpram functional simulation
141508: 09/06/25: Antti: opencores again with problems?
    141513: 09/06/26: OC-team: Re: opencores again with problems?
    141518: 09/06/26: Antti.Lukats@googlemail.com: Re: opencores again with problems?
141516: 09/06/26: Larry: SPARTAN-3AN open-drain at vccio1.8V
    141517: 09/06/26: Uwe Bonnes: Re: SPARTAN-3AN open-drain at vccio1.8V
    141519: 09/06/26: Antti.Lukats@googlemail.com: Re: SPARTAN-3AN open-drain at vccio1.8V
141520: 09/06/26: jack.gassett: Using Xilinx tools with ft2232 based programming cable.
    141522: 09/06/26: Antti.Lukats@googlemail.com: Re: Using Xilinx tools with ft2232 based programming cable.
    141524: 09/06/26: Uwe Bonnes: Re: Using Xilinx tools with ft2232 based programming cable.
    141525: 09/06/26: Antti.Lukats@googlemail.com: Re: Using Xilinx tools with ft2232 based programming cable.
141530: 09/06/26: Denis2Gif: Buy Live design kit from Altium
141531: 09/06/26: sanika: Error while downloading prodram on CPLD
    141535: 09/06/26: Jon Elson: Re: Error while downloading prodram on CPLD
        141545: 09/06/27: sanika: Re: Error while downloading prodram on CPLD
            141607: 09/06/29: Jon Elson: Re: Error while downloading prodram on CPLD
141536: 09/06/26: Gabor: Lattice Universal File Writer - command line problems
    141544: 09/06/26: Antti.Lukats@googlemail.com: Re: Lattice Universal File Writer - command line problems
141546: 09/06/27: Antti: 6/6 infos
    141547: 09/06/27: MK: Re: 6/6 infos
    141548: 09/06/27: Antti.Lukats@googlemail.com: Re: 6/6 infos
    141550: 09/06/27: -jg: Re: 6/6 infos
        141580: 09/06/28: Sean Durkin: Re: 6/6 infos
    141551: 09/06/27: Antti.Lukats@googlemail.com: Re: 6/6 infos
    141552: 09/06/27: Brian Drummond: Re: 6/6 infos
        141557: 09/06/27: Ed McGettigan: Re: 6/6 infos
    141560: 09/06/27: -jg: Re: 6/6 infos
    141583: 09/06/28: Kolja: Re: 6/6 infos
    141584: 09/06/28: Antti.Lukats@googlemail.com: Re: 6/6 infos
141553: 09/06/27: Antti: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::) yippii
    141555: 09/06/27: Uwe Bonnes: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::) yippii ?yee
        141558: 09/06/27: Ed McGettigan: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::) yippii
            141567: 09/06/28: maxascent: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::) yippii ?yee
                142269: 09/07/31: markman: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::) yippii ?yee
    141559: 09/06/27: Antti.Lukats@googlemail.com: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::)
    141568: 09/06/28: Antti.Lukats@googlemail.com: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::)
    142272: 09/07/31: Antti.Lukats@googlemail.com: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::)
    142934: 09/09/08: .: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::)
    142935: 09/09/08: Antti.Lukats@googlemail.com: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::)
141554: 09/06/27: Sudhir Singh: Spartan3E or Cyclone III ?
    141570: 09/06/28: Antti.Lukats@googlemail.com: Re: Spartan3E or Cyclone III ?
        141594: 09/06/29: Jaime Andres Aranguren Cardona: Re: Spartan3E or Cyclone III ?
    141589: 09/06/28: John Adair: Re: Spartan3E or Cyclone III ?
    141595: 09/06/29: Sudhir Singh: Re: Spartan3E or Cyclone III ?
    141605: 09/06/29: John Adair: Re: Spartan3E or Cyclone III ?
141561: 09/06/27: stripline: Virtex 5 Block Ram usage with Coregen FIFO
    141566: 09/06/28: maxascent: Re: Virtex 5 Block Ram usage with Coregen FIFO
    141596: 09/06/29: stripline: Re: Virtex 5 Block Ram usage with Coregen FIFO
141562: 09/06/27: Weng Tianxiang: Expand unsigned 4*4 module to signed 16*16 module
    141563: 09/06/27: Mike Treseler: Re: Expand unsigned 4*4 module to signed 16*16 module
        141575: 09/06/28: Mike Treseler: Re: Expand unsigned 4*4 module to signed 16*16 module
    141565: 09/06/27: Weng Tianxiang: Re: Expand unsigned 4*4 module to signed 16*16 module
    141588: 09/06/28: rickman: Re: Expand unsigned 4*4 module to signed 16*16 module
141569: 09/06/28: vcar: STA Problem on Asynchronous FIFO
    141579: 09/06/28: Gael Paul: Re: STA Problem on Asynchronous FIFO
    141581: 09/06/28: Peter Alfke: Re: STA Problem on Asynchronous FIFO
        141592: 09/06/29: Jonathan Bromley: Re: STA Problem on Asynchronous FIFO
    141586: 09/06/28: Gael Paul: Re: STA Problem on Asynchronous FIFO
    141587: 09/06/28: vcar: Re: STA Problem on Asynchronous FIFO
    141591: 09/06/29: Antti.Lukats@googlemail.com: Re: STA Problem on Asynchronous FIFO
    141600: 09/06/29: vcar: Re: STA Problem on Asynchronous FIFO
141571: 09/06/28: CMOS: usefulness of Virtex-II devices
    141572: 09/06/28: Antti.Lukats@googlemail.com: Re: usefulness of Virtex-II devices
        141585: 09/06/28: james: Re: usefulness of Virtex-II devices
            141593: 09/06/29: Jaime Andres Aranguren Cardona: Re: usefulness of Virtex-II devices
    141597: 09/06/29: radarman: Re: usefulness of Virtex-II devices
    141599: 09/06/29: gabor: Re: usefulness of Virtex-II devices
    141608: 09/06/29: John Eaton: Re: usefulness of Virtex-II devices
    141626: 09/07/01: CMOS: Re: usefulness of Virtex-II devices
141577: 09/06/28: cpld-fpga-asic: FPGA / CPLD Group on LinkedIn -- Networking Group
    141578: 09/06/28: Antti.Lukats@googlemail.com: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
        141668: 09/07/03: steve: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
            141691: 09/07/03: MM: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
                141697: 09/07/03: MM: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
                    141724: 09/07/04: MM: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
            141727: 09/07/05: Nico Coesel: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
                141743: 09/07/06: steve: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
                    141744: 09/07/06: Jonathan Bromley: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
    141598: 09/06/29: rickman: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
    141684: 09/07/03: rickman: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
    141693: 09/07/03: rickman: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
    141700: 09/07/03: rickman: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
    141725: 09/07/04: rickman: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
    141747: 09/07/06: rickman: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
141601: 09/06/29: Benjamin Couillard: dual port inference problem
    141602: 09/06/29: Mike Treseler: Re: dual port inference problem
    141603: 09/06/29: gabor: Re: dual port inference problem
    141604: 09/06/29: Benjamin Couillard: Re: dual port inference problem
141606: 09/06/29: Thomas Rudloff: SATA Phy
    141609: 09/06/29: OutputLogic: Re: SATA Phy
141610: 09/06/30: iquadri: Formatting ML405 system compact flash card.;
141611: 09/06/30: Nashit Ashraf: help needed regarding NOR Flash
    141612: 09/06/30: Symon: Re: help needed regarding NOR Flash
141615: 09/06/30: Svenn Are Bjerkem: How to keep documentation of control and status registers and VHDL
    141616: 09/06/30: Mike Treseler: Re: How to keep documentation of control and status registers and
        141630: 09/07/01: Hal Murray: Re: How to keep documentation of control and status registers and VHDL code in sync
    141625: 09/07/01: whygee: Re: How to keep documentation of control and status registers and
    141663: 09/07/02: Derek Wallace: Re: How to keep documentation of control and status registers and
        141690: 09/07/03: MM: Re: How to keep documentation of control and status registers and VHDL code in sync
    141748: 09/07/06: Petrov: Re: How to keep documentation of control and status registers and
141618: 09/06/30: Sharan: pinout
    141619: 09/07/01: Symon: Re: pinout
        141623: 09/07/01: Walter: Re: pinout
        141629: 09/07/01: Ed McGettigan: Re: pinout
        141632: 09/07/01: Nico Coesel: Re: pinout
        141637: 09/07/02: Kim Enkovaara: Re: pinout
    141620: 09/07/01: Dave: Re: pinout
    141621: 09/07/01: Sharanbr: Re: pinout
    141622: 09/07/01: Dave: Re: pinout
    141740: 09/07/05: Sharanbr: Re: pinout


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