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On Jun 1, 8:37=A0am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On 1 June, 18:20, Neil Steiner <neil.stei...@east.isi.edu> wrote: > > > > > [Haven't yet figured out the fauna of forums.xilinx.com. =A0I posted th= ere > > first, but received no reply, so I'm opting for the tried and true c.a.= f.] > > > I'm working on some XDL tools, and I need an upper bound on the number > > of tiles in the largest Virtex6 devices. =A0The ISE 11.1 info doesn't y= et > > list any support for Virtex6, so I wondered if anybody else might happe= n > > to know. =A0Note that dimensions like SLICE_XnYm are insufficient for m= y > > purposes. > > > If anybody with access to the right tools is willing to check, the > > following should work for the xc6vlx760: > > > =A0 =A0 =A0xdl -report xc6vlx760 > > =A0 =A0 =A0grep tiles xc6vlx760.xdlrc > > > The two lines that come out of that would give me the row and column an= d > > total tile counts. > > if somebody would tell you this, Xilinx would sue them > this info still under NDA, until the 11.1 SP1 is out > > Antti Here is the URL for presently available public information on Virtex-6. http://www.xilinx.com/publications/prod_mktg/Virtex6_Overview.pdf Peter AlfkeArticle: 140976
On 1 June, 20:36, Weng Tianxiang <wtx...@gmail.com> wrote: > On Jun 1, 12:05=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > Hi > > > as this comes to topic again and again, and as it is no longer > > available from the original location > > and as i have it converted to PDF and as I happen to have one "micro > > IP" based on the ideas > > described there, i did upload this PDF version > > > should be accessible as > > >http://antti-brain.googlegroups.com/web/6EASY.pdf > > > it is based on snapshot taken from web.archive.com, > > hopefully i get no C&D letters now > > (well i would just remove the document then :) > > > Antti > > Hi Antty and Peter, > Thank you for your good information. > > Yesterday I run across a patent by Lester Schowe of Maxtor > Corporation, titled "Circuit For Synchronous, Glitch-Free Clock > Switching", having a similar schemes as Peter's, but it uses 6 flip- > flops. The printed copy of the patent was collected in my a folder > called "My most favorite patents" > > http://www.google.com/patents?id=3D_px7AAAAEBAJ&dq=3Dpatent:5315181&as_dr= ... > > I think Lester's may be real glitch-free when switching between two > asynchronous clocks. Peter's scheme only uses one level of flip-flop > to coordinate two asynchronous clocks and it seems to me that it is > not long enough to reliably do the job. > > Weng well well well, Altera has an application dated same year as 6-easy it includes several circuits, one of them being replica from 6-easy but also another with longer FF stages AnttiArticle: 140977
On Jun 1, 5:35=A0am, gabor <ga...@alacron.com> wrote: > On May 29, 9:15=A0pm, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > > > > > > > "Mike Treseler" <mtrese...@gmail.com> wrote in message > > >news:78b42pF1lj91bU1@mid.individual.net... > > > > Weng Tianxiang wrote: > > > >> I don't like to print download version of many documents. The downlo= ad > > >> prints are huge and not easy to keep them in order. > > > >http://www.google.com/search?q=3Dkindle+dx > > > A not unreasonable alternative today is to take the same $500 and buy a= good > > double sided network printer (HP P2015N) and a 19 ring comb binder. OTO= H, I > > might be just sore that I spent my $500 and did just that. For sure, ei= ther > > way is faster, more convenient, and overall cheaper than sending every > > document to Kinkos for printing. > > > I have a few reservations about the Kindle DX. If you have one and use = it > > for, specifically, Xilinx and similar other PDF documents, can you fill= me > > in on how well it's working for you? I'm mostly interested in comparing= ease > > of use to printed, letter size documents. Is the screen a full letter s= ize > > page in size? If not, is it reasonably easy to zoom and navigate? How e= asy > > is it to download your documents to the device? Can you at least minima= lly > > search the document for specific text? Does it work well with the PDF t= able > > of contents and bookmarks? I'm not especially keen on the wireless serv= ice > > charges, and would prefer to focus on its equivalence to a printed page= . > > Thanks. > > Quite frankly I would think that the whole idea of Kindle misses > the original point of having the book in print. =A0If you want an > electronic reader, your PC is still better than Kindle. =A0If you > want the convenience of printed pages you can cover your desk with, > mark up, quickly scan through, etc. you still really want a print. > Maybe Xilinx is missing an opportunity to sell printed user guides, > but my guess is that the real reason printed manuals are going away > is the rate at which the data becomes obsolete or otherwise > irrelevant. =A0One of my colleagues here likes to print the user > guides reduced to half-size thereby getting 4 pages to a sheet > of letter paper. =A0Then bound along the long side you can see > four pages at a time. =A0Try that on a PC screen... > > Regards, > Gabor- Hide quoted text - > > - Show quoted text - Hi, I searched the website for FPGA Handbook and found two used books from Xilinx: http://www.findbookprices.com/search/?isbn=3DFPGA+handbook One is Spartan-3 Platform FPGA Handbook; another is Virtex-II Pro Platform FPGA Handbook. What surprised me is their asking prices for those used books: $99.99 + $3.95 mailing fee each. WengArticle: 140978
On 1 June, 20:42, pe...@xilinx.com wrote: > On Jun 1, 8:37=A0am, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > On 1 June, 18:20, Neil Steiner <neil.stei...@east.isi.edu> wrote: > > > > [Haven't yet figured out the fauna of forums.xilinx.com. =A0I posted = there > > > first, but received no reply, so I'm opting for the tried and true c.= a.f.] > > > > I'm working on some XDL tools, and I need an upper bound on the numbe= r > > > of tiles in the largest Virtex6 devices. =A0The ISE 11.1 info doesn't= yet > > > list any support for Virtex6, so I wondered if anybody else might hap= pen > > > to know. =A0Note that dimensions like SLICE_XnYm are insufficient for= my > > > purposes. > > > > If anybody with access to the right tools is willing to check, the > > > following should work for the xc6vlx760: > > > > =A0 =A0 =A0xdl -report xc6vlx760 > > > =A0 =A0 =A0grep tiles xc6vlx760.xdlrc > > > > The two lines that come out of that would give me the row and column = and > > > total tile counts. > > > if somebody would tell you this, Xilinx would sue them > > this info still under NDA, until the 11.1 SP1 is out > > > Antti > > Here is the URL for presently available public information on > Virtex-6. > > http://www.xilinx.com/publications/prod_mktg/Virtex6_Overview.pdf > > Peter Alfke I think we all can find this document, there isnt much in it as we all know AnttiArticle: 140979
"gabor" <gabor@alacron.com> wrote in message news:677918e8-fd73-40a8-ad8c-035dd1984364@v2g2000vbb.googlegroups.com... One of my colleagues here likes to print the user guides reduced to half-size thereby getting 4 pages to a sheet of letter paper. Then bound along the long side you can see four pages at a time. Try that on a PC screen... ====== Try that past your 46th birtday. ;) And yes, as strange as it sounds, the apparent disorder of stacked and piled documents and detritus on desktops and workbenches have significance and utility to their makers. One of the conclusions of a Microsoft study is that the folder heirarchy suits the computer, not the user.Article: 140980
>> If anybody with access to the right tools is willing to check, the >> following should work for the xc6vlx760: >> >> xdl -report xc6vlx760 >> grep tiles xc6vlx760.xdlrc >> >> The two lines that come out of that would give me the row and column and >> total tile counts. > > if somebody would tell you this, Xilinx would sue them > this info still under NDA, until the 11.1 SP1 is out Oh, I didn't realize this was still under NDA. I knew that Virtex6 was supposed to be supported in 11.1, but wasn't aware of the SP1 distinction. When I initially posted the question to forums.xilinx.com, I figured somebody inside Xilinx might be willing to respond, since the "Logic Cells" counts for the devices are already published.Article: 140981
On 1 June, 22:07, Neil Steiner <neil.stei...@east.isi.edu> wrote: > >> If anybody with access to the right tools is willing to check, the > >> following should work for the xc6vlx760: > > >> =A0 =A0 =A0xdl -report xc6vlx760 > >> =A0 =A0 =A0grep tiles xc6vlx760.xdlrc > > >> The two lines that come out of that would give me the row and column a= nd > >> total tile counts. > > > if somebody would tell you this, Xilinx would sue them > > this info still under NDA, until the 11.1 SP1 is out > > Oh, I didn't realize this was still under NDA. =A0I knew that Virtex6 was > supposed to be supported in 11.1, but wasn't aware of the SP1 distinction= . > > When I initially posted the question to forums.xilinx.com, I figured > somebody inside Xilinx might be willing to respond, since the "Logic > Cells" counts for the devices are already published. no it will be silence until the SP1 is released (or the information otherwise made public officially) AnttiArticle: 140982
On May 27, 11:03 pm, Peter Alfke <al...@sbcglobal.net> wrote: > On May 27, 2:43 pm, rickman <gnu...@gmail.com> wrote: > > > > > On May 27, 4:10 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > On May 27, 1:33 pm, Muzaffer Kal <k...@dspia.com> wrote: > > > > > On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 > > > > > <j...@jonathanleslie.com> wrote: > > > > >on a spartan 3e, the DCM speaks to havein a high-resolution phase > > > > >shifting function, but it goes on and says the DCM has a wide > > > > >frequency range of 5MHz to 300MHz. How can I get my 2MHz signal phase > > > > >locked? > > > > > >The idea is this, I have a 2MHz signal coming in on a pin, and I want > > > > >to mimic that signal on an internal std_logic pin with the idea that > > > > >if the 2MHz signal on the incoming pin is ever lost, the internal > > > > >std_logic pin continues the original timing as if nothing has > > > > >happened. > > > > > >Any suggestions? > > > > > Implement your own NCO. Basically run a high resolution counter with > > > > high speed clock and detect at which count the 2MHz signal is toggling > > > > (both edges if need be) and generate an internal signal at the same > > > > count. Now even if the external signal disappears you have the count > > > > (phase) already and you can keep generating the internal signal. You > > > > can use this internal signal either as a clock source (ie a divided > > > > clock) or as an enable to its downstream logic. > > > > -- > > > > Muzaffer Kal > > > > > DSPIA INC. > > > > ASIC/FPGA Design Services > > > > >http://www.dspia.com > > > > as I've been thinking about this today I also thought to forget the > > > DCM and just do it with the regular system clock. The main system > > > clock will be anywhere between 25-100MHZ, and for that matter, the > > > 25MHz can be 4X with the DCM. so now the issue is on the rising edge > > > of the inbound 2MHz clock have the internal 2mhz clock count off 50 > > > ticks of the 100MHz clock to do my best "phase lock" > > > Hi Jonathan, > > > I am currently working on the same sort of design. I don't think an > > NCO is the entire job. What you need is a phase locked loop with a > > mode of holding the last setting when the input clock is lost. To do > > this you need an integrator between the phase detector and the NCO > > which will accumulate and hold a value to maintain the output > > frequency when the input clock is lost. The trick is this is not a > > stable circuit and needs other feedback to stabilize it. If you know > > anything about DSP, this is not a hard problem to analyze. The > > integrator puts a pole on the unit circle at 1,0 which by itself is > > not stable. You can add a proportional feedback element to add a zero > > which can be placed very close to the pole which will stabilize it for > > frequencies other than near DC. But we don't care about being DC > > bounded because the feedback loop will compensate for that. > > > Rick > > Here is an all-digital solution: > Assume we have a high clock frequency, e.g. 100 MHz. > We use it to clock a DDS accumulator, whose parallel input is an up/ > down counter. > We also use the 100 MHz to differentiate the rising edge of the > incoming 2 MHz frequency. > We check whether this short 10 ns pulse occurs during the High or the > Low time of the DDS output square wave. > If during the Low level, we increment the up/down counter,(speeding up > the DDS output) if during the High level, we decrement the counter. > When there is no pulse, we leave the counter value stable, since it > remembers the missing frequency. > > I have not checked whether this circuit will always start under all > circumstances. > Peter Alfke Sorry Peter, I wasn't quite sure how to comment on this solution. I have a 100MHz system clock, and my input pin has the 2MHz signal, Its easy enough to catch the exact 10ns pulse where the 2MHz input pin switches state, but the count up/count confused me. I interpreted this as I keep a 2MHz counter going based on my 100Mhz clock, and on the state switch of 2MHz input pin I mark the count value of this 2Mhz_counter. I then use that value as the state switch value for my synch_2MHz signal.Article: 140983
Hello all, I just wanted to post that I have released an open source FPGA circuit design. Please feel free to use it as is or to quick start your own designs. It is released under the Creative Commons Attribution license exactly like the Arduino. This is a work in progress so any feedback is appreciated. Here are some specifications: -Schematic and Board layout in EAGLE. -Modular design that separates the FPGA from the power supply and USB. -Handles Xilinx Spartan 3E 250K and 500K devices in the compact VTQFP-100 footprint. -A two layer design with as many traces routed over an unbroken ground plane as possible. -An FTDI FT2232 dual channel USB chip allows JTAG programming and UART communications to coexist. -Uses the URJTAG open source application to load SVF files over the USB JTAG channel. All project information and EAGLE files can be found in the various projects located at: http://www.gadgetfactory.net/gf/project/butterfly_main/ Thanks. Jack Gassett http://www.GadgetFactory.net Home of the ButterFly Platform, an open source FPGA circuit design.Article: 140984
Looks interesting, especially for anyone that wants to learn how to build their own PCB with an FPGA or similar device on it. Good luck. ---Matthew Hicks > Hello all, > > I just wanted to post that I have released an open source FPGA circuit > design. Please feel free to use it as is or to quick start your own > designs. It is released under the Creative Commons Attribution license > exactly like the Arduino. This is a work in progress so any feedback > is appreciated. > > Here are some specifications: > -Schematic and Board layout in EAGLE. > -Modular design that separates the FPGA from the power supply and USB. > -Handles Xilinx Spartan 3E 250K and 500K devices in the compact > VTQFP-100 footprint. > -A two layer design with as many traces routed over an unbroken ground > plane as possible. > -An FTDI FT2232 dual channel USB chip allows JTAG programming and UART > communications to coexist. > -Uses the URJTAG open source application to load SVF files over the > USB JTAG channel. > All project information and EAGLE files can be found in the various > projects located at: > http://www.gadgetfactory.net/gf/project/butterfly_main/ > > Thanks. > Jack Gassett > http://www.GadgetFactory.net > Home of the ButterFly Platform, an open source FPGA circuit design.Article: 140985
On Jun 1, 1:10=A0pm, jleslie48 <j...@jonathanleslie.com> wrote: > On May 27, 11:03 pm, Peter Alfke <al...@sbcglobal.net> wrote: > > > > > On May 27, 2:43 pm, rickman <gnu...@gmail.com> wrote: > > > > On May 27, 4:10 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > On May 27, 1:33 pm, Muzaffer Kal <k...@dspia.com> wrote: > > > > > > On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 > > > > > > <j...@jonathanleslie.com> wrote: > > > > > >on a spartan 3e, the DCM speaks to havein a high-resolution phas= e > > > > > >shifting function, but it goes on and says the DCM has a wide > > > > > >frequency range of 5MHz to 300MHz. =A0How can I get my 2MHz sign= al phase > > > > > >locked? > > > > > > >The idea is this, I have a 2MHz signal coming in on a pin, and I= want > > > > > >to mimic that signal on an internal std_logic pin with the idea = that > > > > > >if the 2MHz signal on the incoming pin is ever lost, the interna= l > > > > > >std_logic pin continues the original timing as if nothing has > > > > > >happened. > > > > > > >Any suggestions? > > > > > > Implement your own NCO. Basically run a high resolution counter w= ith > > > > > high speed clock and detect at which count the 2MHz signal is tog= gling > > > > > (both edges if need be) and generate an internal signal at the sa= me > > > > > count. Now even if the external signal disappears you have the co= unt > > > > > (phase) already and you can keep generating the internal signal. = You > > > > > can use this internal signal either as a clock source (ie a divid= ed > > > > > clock) or as an enable to its downstream logic. > > > > > -- > > > > > Muzaffer Kal > > > > > > DSPIA INC. > > > > > ASIC/FPGA Design Services > > > > > >http://www.dspia.com > > > > > as I've been thinking about this today I also thought to forget the > > > > DCM and just do it with the regular system clock. =A0The main syste= m > > > > clock will be anywhere between 25-100MHZ, and for that matter, the > > > > 25MHz can be 4X with the DCM. =A0so now the issue is on the rising = edge > > > > of the inbound 2MHz clock have the internal 2mhz clock count off 50 > > > > ticks of the 100MHz clock to do my best "phase lock" > > > > Hi Jonathan, > > > > I am currently working on the same sort of design. =A0I don't think a= n > > > NCO is the entire job. =A0What you need is a phase locked loop with a > > > mode of holding the last setting when the input clock is lost. =A0To = do > > > this you need an integrator between the phase detector and the NCO > > > which will accumulate and hold a value to maintain the output > > > frequency when the input clock is lost. =A0The trick is this is not a > > > stable circuit and needs other feedback to stabilize it. =A0If you kn= ow > > > anything about DSP, this is not a hard problem to analyze. =A0The > > > integrator puts a pole on the unit circle at 1,0 which by itself is > > > not stable. =A0You can add a proportional feedback element to add a z= ero > > > which can be placed very close to the pole which will stabilize it fo= r > > > frequencies other than near DC. =A0But we don't care about being DC > > > bounded because the feedback loop will compensate for that. > > > > Rick > > > Here is an all-digital solution: > > Assume we have a high clock frequency, e.g. 100 MHz. > > We use it to clock a DDS accumulator, whose parallel input is an up/ > > down counter. > > We also use the 100 MHz to differentiate the rising edge of the > > incoming 2 MHz frequency. > > We check whether this short 10 ns pulse occurs during the High or the > > Low time of the DDS output square wave. > > If during the Low level, we increment the up/down counter,(speeding up > > the DDS output) if during the High level, we decrement the counter. > > When there is no pulse, we leave the counter value stable, since it > > remembers the missing frequency. > > > I have not checked whether this circuit will always start under all > > circumstances. > > Peter Alfke > > Sorry Peter, > > I wasn't quite sure how to comment on this solution. =A0I have a 100MHz > system clock, and my input pin has the 2MHz signal, Its easy enough to > catch the exact 10ns pulse where the =A02MHz input pin switches state, > but the count up/count confused me. =A0I interpreted this as I keep a > 2MHz counter going based on my 100Mhz clock, and on the state switch > of 2MHz input pin I mark the count value of this 2Mhz_counter. =A0I then > use that value as the state switch value for my synch_2MHz signal. Not quite. You use the 100 MHz clock to drive a DDS circuit, which is another name for a phase accumulator, 10 or 16 bits long. Such an accumulator adds a fixed value to its content on every clock pulse, i.e. 100 MHz. The "fixed" value is actually an up/down counter, which is controlled by the 2 MHz differentiated edge. Depending on whether this edge occurs during the High or the Low time of the most significant output from the DDS,the counter is incremented or decremented. No edge, no counter change. The counter can thus change by only one count at a 2 MHz rate, or not change at all. The length of the DDS accumulator and the counter determined the speed of adjustment, the gain of the PLL. This is really a digital model of an analog PLL, but without any leakage from the Low-pass filter. PeterArticle: 140986
On Mon, 1 Jun 2009 13:15:13 -0700 (PDT), "jack.gassett" <jack.gassett@gadgetfactory.net> wrote: >Hello all, > >I just wanted to post that I have released an open source FPGA circuit >design. Please feel free to use it as is or to quick start your own >designs. It is released under the Creative Commons Attribution license >exactly like the Arduino. This is a work in progress so any feedback >is appreciated. > >Here are some specifications: >-Schematic and Board layout in EAGLE. Just curious, but why EAGLE and not one of the open source schematic capture and board layout apps like gEDA or Kicad? If you're not familiar with the DRM issues associated with EAGLE, here's one person's experience: <http://groups.google.com/group/comp.arch.embedded/browse_frm/thread/f794e82d26b59e18/d7cf4149edb93ac7?q=*-*-website+reus> -- Rich Webb Norfolk, VAArticle: 140987
Host ID will be: System information is pre-populated in the option menu if you arrived at the Product Download and Licensing Site from a link within the Xilinx License Configuration Manager (XLCM). Now, just try to find XLCM on Xilinx's website (all you will find are references to it. To further complicate issues, it seems like the only way to get help of ANY KIND is to submit a web case. Just try to talk to someone on the phone! I actually did; guess what they said: SUBMIT A WEB CASE!Article: 140988
The next round of Avnet X-Fest events are scheduled from October 2009 through February 2010. http://www.businesswire.com/portal/site/home/permalink/?ndmViewId=3Dnews_vi= ew&newsId=3D20090527005387&newsLang=3Den www.em.avnet.com/xfest On May 18, 8:53=A0am, Bryan <bryan.fletc...@avnet.com> wrote: > Avnet hosts a 1-day, Xilinx-focused "X-Fest" every 18 to 24 months. > Here's a few links from the last time it was held in 2007. =A0The > articles mention that the next one was tentatively planned for 2008, > but that did not happen. > > http://www.fpgajournal.com/news_2007/08/20070815_01.htmhttp://news.thomas= net.com/companystory/518935http://www.em.avnet.com/evs/home/0,4582,CID%253D= 35679%2526CCD%253DUSA... > > BryanArticle: 140989
soar2morrow wrote: Has anyone tried to install a Xilinx floating license? Yes, three days ago. It really was no problem. And this was on Fedora, which isn't supported. > Now, just try to find XLCM on Xilinx's website (all you will find are > references to it. If the Xilinx tools are installed on the system, open a command prompt and type xclm. > To further complicate issues, it seems like the only > way to get help of ANY KIND is to submit a web case. Just try to talk to > someone on the phone! I actually did; guess what they said: SUBMIT A WEB > CASE! I'll be happy to solve problems like this for you for $85/hour plus expenses and travel. Send me an email. I'm very familiar with the Xilinx tools and FPGA design. -- Phil Hays (phil_hays at eeei.gro (fix the order for email)Article: 140990
On Jun 1, 4:10=A0pm, jleslie48 <j...@jonathanleslie.com> wrote: > On May 27, 11:03 pm, Peter Alfke <al...@sbcglobal.net> wrote: > > > > > On May 27, 2:43 pm, rickman <gnu...@gmail.com> wrote: > > > > On May 27, 4:10 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > On May 27, 1:33 pm, Muzaffer Kal <k...@dspia.com> wrote: > > > > > > On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 > > > > > > <j...@jonathanleslie.com> wrote: > > > > > >on a spartan 3e, the DCM speaks to havein a high-resolution phas= e > > > > > >shifting function, but it goes on and says the DCM has a wide > > > > > >frequency range of 5MHz to 300MHz. =A0How can I get my 2MHz sign= al phase > > > > > >locked? > > > > > > >The idea is this, I have a 2MHz signal coming in on a pin, and I= want > > > > > >to mimic that signal on an internal std_logic pin with the idea = that > > > > > >if the 2MHz signal on the incoming pin is ever lost, the interna= l > > > > > >std_logic pin continues the original timing as if nothing has > > > > > >happened. > > > > > > >Any suggestions? > > > > > > Implement your own NCO. Basically run a high resolution counter w= ith > > > > > high speed clock and detect at which count the 2MHz signal is tog= gling > > > > > (both edges if need be) and generate an internal signal at the sa= me > > > > > count. Now even if the external signal disappears you have the co= unt > > > > > (phase) already and you can keep generating the internal signal. = You > > > > > can use this internal signal either as a clock source (ie a divid= ed > > > > > clock) or as an enable to its downstream logic. > > > > > -- > > > > > Muzaffer Kal > > > > > > DSPIA INC. > > > > > ASIC/FPGA Design Services > > > > > >http://www.dspia.com > > > > > as I've been thinking about this today I also thought to forget the > > > > DCM and just do it with the regular system clock. =A0The main syste= m > > > > clock will be anywhere between 25-100MHZ, and for that matter, the > > > > 25MHz can be 4X with the DCM. =A0so now the issue is on the rising = edge > > > > of the inbound 2MHz clock have the internal 2mhz clock count off 50 > > > > ticks of the 100MHz clock to do my best "phase lock" > > > > Hi Jonathan, > > > > I am currently working on the same sort of design. =A0I don't think a= n > > > NCO is the entire job. =A0What you need is a phase locked loop with a > > > mode of holding the last setting when the input clock is lost. =A0To = do > > > this you need an integrator between the phase detector and the NCO > > > which will accumulate and hold a value to maintain the output > > > frequency when the input clock is lost. =A0The trick is this is not a > > > stable circuit and needs other feedback to stabilize it. =A0If you kn= ow > > > anything about DSP, this is not a hard problem to analyze. =A0The > > > integrator puts a pole on the unit circle at 1,0 which by itself is > > > not stable. =A0You can add a proportional feedback element to add a z= ero > > > which can be placed very close to the pole which will stabilize it fo= r > > > frequencies other than near DC. =A0But we don't care about being DC > > > bounded because the feedback loop will compensate for that. > > > > Rick > > > Here is an all-digital solution: > > Assume we have a high clock frequency, e.g. 100 MHz. > > We use it to clock a DDS accumulator, whose parallel input is an up/ > > down counter. > > We also use the 100 MHz to differentiate the rising edge of the > > incoming 2 MHz frequency. > > We check whether this short 10 ns pulse occurs during the High or the > > Low time of the DDS output square wave. > > If during the Low level, we increment the up/down counter,(speeding up > > the DDS output) if during the High level, we decrement the counter. > > When there is no pulse, we leave the counter value stable, since it > > remembers the missing frequency. > > > I have not checked whether this circuit will always start under all > > circumstances. > > Peter Alfke > > Sorry Peter, > > I wasn't quite sure how to comment on this solution. =A0I have a 100MHz > system clock, and my input pin has the 2MHz signal, Its easy enough to > catch the exact 10ns pulse where the =A02MHz input pin switches state, > but the count up/count confused me. =A0I interpreted this as I keep a > 2MHz counter going based on my 100Mhz clock, and on the state switch > of 2MHz input pin I mark the count value of this 2Mhz_counter. =A0I then > use that value as the state switch value for my synch_2MHz signal. This is a bit of a simplistic solution. It assumes that your 100 MHz clock and the 2 MHz clock are ***EXACT*** multiples in frequency. Assuming the 2 MHz clock is dead on and your 100 MHz clock is 1 ppm (which is a *very* good oscillator) then you will see 2 extra (or missing) cycles per second in your synthesized clock, in other words a 4*PI phase shift per second. When you say the 2 MHz clock phase contains the information, what is being used as the reference for phase? In an earlier post you said, "it cannot add any phase difference to the downstream consumer of the signal". You also refer to an RS-485 signal. I think we are not getting the entire picture and that we are not really helping you at all because of that. Does your synthesized 2 MHz clock have to remain in phase with the missing 2 MHz clock the entire time it is gone or just at the point of transition? I really think that none of us can really help you with this until we understand the problem better. If the problem is as you described originally, your solution will not work. It will require a DCO (DDS is clearly overkill since the signal is digital and not a sine wave) and even then there will be drift based on the system clock stability. RickArticle: 140991
On Jun 1, 3:34=A0pm, phil hays <philh...@dont.spam> wrote: > soar2morrow wrote: > > Has anyone tried to install a Xilinx floating license? > > Yes, three days ago. It really was no problem. And this was on Fedora, > which isn't supported. > > > Now, just try to find XLCM on Xilinx's website (all you will find are > > references to it. > > If the Xilinx tools are installed on the system, open a command prompt > and type xclm. > > > To further complicate issues, it seems like the only > > way to get help of ANY KIND is to submit a web case. Just try to talk t= o > > someone on the phone! I actually did; guess what they said: SUBMIT A WE= B > > CASE! > > I'll be happy to solve problems like this for you for $85/hour plus > expenses and travel. Send me an email. I'm very familiar with the Xilinx > tools and FPGA design. > > -- > Phil Hays > (phil_hays at eeei.gro (fix the order for email) Well, I guess I need to know how I can install Xilinx tools, because it isn't obvious to me.Article: 140992
On Jun 2, 10:56=A0am, rickman <gnu...@gmail.com> wrote: > This is a bit of a simplistic solution. =A0It assumes that your 100 MHz > clock and the 2 MHz clock are ***EXACT*** multiples in frequency. > Assuming the 2 MHz clock is dead on and your 100 MHz clock is 1 ppm > (which is a *very* good oscillator) then you will see 2 extra (or > missing) cycles per second in your synthesized clock, in other words a > 4*PI phase shift per second. That's not what I read from Peter's suggestion. His Digital Lock scheme, would have no missing or extra clocks, but would have snap-jumps, of 10ns applied as they were needed. IIRC he had a dead-band or in-lock, where no jumps would occur, and outside that it jumps left, or right as needed. 10ns in 2MHz is a 2% time window, so I make a 1ppm skew, going outside that window every ~10ms, and getting a kick. 10ppm will correct ~ 1ms A simple U/D scheme will lock in 50% time steps, worst case, or 25 2Mhz clocks. -jgArticle: 140993
Well, I guess I need to know how I can install Xilinx tools, because it isn't obvious to me. ========== Until a moment, the question hadn't occurred to me. How could I possibly answer that for you? What troubles are you anticipating?Article: 140994
On Jun 1, 4:34=A0pm, -jg <Jim.Granvi...@gmail.com> wrote: > On Jun 2, 10:56=A0am, rickman <gnu...@gmail.com> wrote: > > > This is a bit of a simplistic solution. =A0It assumes that your 100 MHz > > clock and the 2 MHz clock are ***EXACT*** multiples in frequency. > > Assuming the 2 MHz clock is dead on and your 100 MHz clock is 1 ppm > > (which is a *very* good oscillator) then you will see 2 extra (or > > missing) cycles per second in your synthesized clock, in other words a > > 4*PI phase shift per second. > > That's not what I read from Peter's suggestion. His Digital Lock > scheme, > would have no missing or extra clocks, but would have snap-jumps, of > 10ns applied as they were needed. IIRC he had a dead-band or in-lock, > where no jumps would occur, and outside that it jumps left, or right > as needed. > 10ns in 2MHz is a 2% =A0time window, so I make a 1ppm skew, going > outside that window =A0every ~10ms, and getting a kick. > 10ppm will correct ~ 1ms > A simple U/D scheme will lock in 50% time steps, worst case, or 25 > 2Mhz > clocks. > > -jg The beauty of the DDS scheme is that the ratio between the two frequencies (100 MHz and 2 MHz in this case) can be approximated by an arbitrary long binary number, the length of the accumulator. A 27-bit accumulator can represent any integer Hz, if that is what matters. But nothing can possibly compensate for 100 MHz frequency drift while the 2 MHz pulses are missing. That would need clairvoyance... Peter AArticle: 140995
On Jun 1, 7:34 pm, -jg <Jim.Granvi...@gmail.com> wrote: > On Jun 2, 10:56 am, rickman <gnu...@gmail.com> wrote: > > > This is a bit of a simplistic solution. It assumes that your 100 MHz > > clock and the 2 MHz clock are ***EXACT*** multiples in frequency. > > Assuming the 2 MHz clock is dead on and your 100 MHz clock is 1 ppm > > (which is a *very* good oscillator) then you will see 2 extra (or > > missing) cycles per second in your synthesized clock, in other words a > > 4*PI phase shift per second. > > That's not what I read from Peter's suggestion. His Digital Lock > scheme, > would have no missing or extra clocks, but would have snap-jumps, of > 10ns applied as they were needed. IIRC he had a dead-band or in-lock, > where no jumps would occur, and outside that it jumps left, or right > as needed. > 10ns in 2MHz is a 2% time window, so I make a 1ppm skew, going > outside that window every ~10ms, and getting a kick. > 10ppm will correct ~ 1ms > A simple U/D scheme will lock in 50% time steps, worst case, or 25 > 2Mhz > clocks. > =E2=99=A6 > -jg I'm sorry, I didn't make myself clear. I was addressing Jonathan's approach of just generating a 2 MHz signal by dividing the 100 MHz signal. But actually, I've been thinking a bit and if the 2 MHz is dead on 2 MHz +- some tolerance and the 100 MHz is dead on +- a tolerance, then Jonathan's approach may not be so bad. Both of the tolerances are likely very small so that may be good enough, especially since he has no spec to work with. Using a DCO will only improve the accuracy by the tolerance of the 100 MHz clock which he has control over anyway. RickArticle: 140996
On Jun 1, 11:35=A0pm, Peter Alfke <al...@sbcglobal.net> wrote: > On Jun 1, 4:34=A0pm, -jg <Jim.Granvi...@gmail.com> wrote: > > > > > On Jun 2, 10:56=A0am, rickman <gnu...@gmail.com> wrote: > > > > This is a bit of a simplistic solution. =A0It assumes that your 100 M= Hz > > > clock and the 2 MHz clock are ***EXACT*** multiples in frequency. > > > Assuming the 2 MHz clock is dead on and your 100 MHz clock is 1 ppm > > > (which is a *very* good oscillator) then you will see 2 extra (or > > > missing) cycles per second in your synthesized clock, in other words = a > > > 4*PI phase shift per second. > > > That's not what I read from Peter's suggestion. His Digital Lock > > scheme, > > would have no missing or extra clocks, but would have snap-jumps, of > > 10ns applied as they were needed. IIRC he had a dead-band or in-lock, > > where no jumps would occur, and outside that it jumps left, or right > > as needed. > > 10ns in 2MHz is a 2% =A0time window, so I make a 1ppm skew, going > > outside that window =A0every ~10ms, and getting a kick. > > 10ppm will correct ~ 1ms > > A simple U/D scheme will lock in 50% time steps, worst case, or 25 > > 2Mhz > > clocks. > > > -jg > > The beauty of the DDS scheme is that the ratio between the two > frequencies (100 MHz and 2 MHz in this case) can be approximated by an > arbitrary long binary number, the length of the accumulator. A 27-bit > accumulator can represent any integer Hz, if that is what matters. > But nothing can possibly compensate for 100 MHz frequency drift while > the 2 MHz pulses are missing. That would need clairvoyance... > Peter A How about an infinite improbability drive circuit? That could work, at least in theory. RickArticle: 140997
On Jun 1, 7:52=A0pm, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > Well, I guess I need to know how I can install Xilinx tools, because > it isn't obvious to me. > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > Until a moment, the question hadn't occurred to me. How could I possibly > answer that for you? What troubles are you anticipating? You must be on the staff of the Xilinx Help team.Article: 140998
<soar2morrow@yahoo.com> wrote in message news:b6e68c33-6ce3-4039-9bac-90b0baeb00d1@g19g2000yql.googlegroups.com... On Jun 1, 7:52 pm, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > Well, I guess I need to know how I can install Xilinx tools, because > it isn't obvious to me. > > ========== > Until a moment, the question hadn't occurred to me. How could I possibly > answer that for you? What troubles are you anticipating? You must be on the staff of the Xilinx Help team. ======== All through the work day, I set aside all pretensions of being able to read minds and ascertain unarticulated needs. The wife, OTOH, demands the opposite. I think I see your problem.Article: 140999
Thank you - you're right, it's highly improfessional to let my frustration be shown... But I was really frustrated! I still don't like Xilinx, but now I'm saying this for the last time. At least, while asking for help. MR
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