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Threads Starting Oct 2001
35357: 01/10/01: Noddy: 45 degree mixer
35360: 01/10/01: Noddy: Re: 45 degree mixer
35361: 01/10/01: Theron Hicks: bufgmux in virtex2 not found
35367: 01/10/01: Jon Harrison: Re: bufgmux in virtex2 not found
35362: 01/10/01: Scott Thibault: ANN: VHDL Studio for Solaris
35366: 01/10/01: Chris Elliott: Xilinx Spartan-II slave parallel configuration
35460: 01/10/06: Tim: Re: Xilinx Spartan-II slave parallel configuration
35370: 01/10/01: Dave Brown: CTL Register in Virtex-E Configuration
35371: 01/10/01: Austin Lesea: Re: CTL Register in Virtex-E Configuration
35372: 01/10/01: Nate Goldshlag: barrel shifter in Xilinx Virtex-E
35373: 01/10/02: Tom Dillon: Re: barrel shifter in Xilinx Virtex-E
35374: 01/10/02: Ray Andraka: Re: barrel shifter in Xilinx Virtex-E
35375: 01/10/02: Peter Alfke: Re: barrel shifter in Xilinx Virtex-E
35376: 01/10/02: Ray Andraka: Re: barrel shifter in Xilinx Virtex-E
35384: 01/10/02: Peter Alfke: Re: barrel shifter in Xilinx Virtex-E
35388: 01/10/02: Falk Brunner: Re: barrel shifter in Xilinx Virtex-E
35387: 01/10/02: Speedy Zero Two: Re: barrel shifter in Xilinx Virtex-E
35379: 01/10/02: Zoltan Kocsi: Linux tools
35432: 01/10/04: Rene Tschaggelar: Re: Linux tools
35710: 01/10/15: James C. Schwalbe: Re: Linux tools
35790: 01/10/17: Tim O'Connell: Re: Linux tools
35870: 01/10/21: Asher C. Martin: Re: Linux tools
39909: 02/02/21: B. Joshua Rosen: Re: Linux tools
39929: 02/02/22: Jan Pech: Re: Linux tools
39933: 02/02/22: Claudio: Re: Linux tools
39939: 02/02/22: Petter Gustad: Re: Linux tools
39944: 02/02/22: Veli-Matti Karppinen: Re: Linux tools
39936: 02/02/22: Uwe Bonnes: Re: Linux tools
39977: 02/02/22: Petter Gustad: Re: Linux tools
35380: 01/10/02: Duane Hague: Re: Barrel Shifter
35385: 01/10/02: Mike Treseler: Re: Barrel Shifter
35389: 01/10/02: Falk Brunner: Re: Barrel Shifter
35395: 01/10/02: glen herrmannsfeldt: Re: Barrel Shifter
35396: 01/10/02: Duane Hague: Re: Barrel Shifter
35397: 01/10/02: Ray Andraka: Re: Barrel Shifter
35401: 01/10/03: NotMe: Re: Barrel Shifter
35411: 01/10/03: stefaan vanheesbeke: Re: Barrel Shifter
35417: 01/10/04: Ray Andraka: Re: Barrel Shifter
35444: 01/10/04: Jan Gray: Re: Barrel Shifter
35448: 01/10/05: Tim: Re: Barrel Shifter
35381: 01/10/02: Antonio: QPSK BER QUESTION
35383: 01/10/02: Martin Fischer: Which Cable for the Xilinx 3064XL ?
35390: 01/10/02: Falk Brunner: Re: Which Cable for the Xilinx 3064XL ?
35394: 01/10/02: Peter Alfke: Re: Which Cable for the Xilinx 3064XL ?
35405: 01/10/03: Magnus Homann: Re: Which Cable for the Xilinx 3064XL ?
35420: 01/10/04: Martin Fischer: Re: Which Cable for the Xilinx 3064XL ?
35422: 01/10/04: Magnus Homann: Re: Which Cable for the Xilinx 3064XL ?
35386: 01/10/02: Speedy Zero Two: Webpack V4 && IBUFG
35393: 01/10/02: Speedy Zero Two: Re: Webpack V4 && IBUFG
35391: 01/10/02: rafael plonka: Implementation of Quartus Megafunctions in Mentor HDS???
35406: 01/10/03: Eric Mullaley: Virtex II DCM: Phase Shifting
35407: 01/10/03: Austin Lesea: Re: Virtex II DCM: Phase Shifting
35408: 01/10/03: John_H: Re: Virtex II DCM: Phase Shifting
35409: 01/10/03: Richard Dungan: Xilinx Foundation vs. ISE
35410: 01/10/03: stefaan vanheesbeke: Re: Xilinx Foundation vs. ISE
35421: 01/10/04: Noddy: Re: Xilinx Foundation vs. ISE
35439: 01/10/04: stefaan vanheesbeke: Re: Xilinx Foundation vs. ISE
35474: 01/10/07: KsTiger: Re: Xilinx Foundation vs. ISE
35412: 01/10/03: Ultimate Bob: error from BUFGMUX in ModelSim??
35413: 01/10/03: Theron Hicks: Re: error from BUFGMUX in ModelSim?? Sorry wrong address...
35414: 01/10/03: Martin Rice: What's a process?
35418: 01/10/03: Jeff Cunningham: Re: What's a process?
35415: 01/10/03: Martin Euredjian: [OT] Prototyping with BGA's
35440: 01/10/04: Pak K. Chan: Re: Prototyping with BGA's
35416: 01/10/03: Bob Perlman: Virtex II multiplier speed?
35423: 01/10/04: Sebastian: Xilinx: JTAG parallel connection problem
35452: 01/10/05: Rienk van der Scheer: Re: Xilinx: JTAG parallel connection problem
35453: 01/10/05: Seb: Re: Xilinx: JTAG parallel connection problem
35516: 01/10/09: David Kinsell: Re: Xilinx: JTAG parallel connection problem
35424: 01/10/04: viswanath: multipliers in virtex-II
35430: 01/10/04: Ray Andraka: Re: multipliers in virtex-II
35441: 01/10/04: Tom Dillon: Re: multipliers in virtex-II
35425: 01/10/04: Ignacy Kudla: ISE4 - HDL Bencher
35433: 01/10/04: Kamal Patel: Re: ISE4 - HDL Bencher
35426: 01/10/04: Ignacy Kudla: Xilinx ISE 4.1, HDL Bencher
35428: 01/10/04: Manfred Kraus: CoreGenerator and WebPack ISE
35446: 01/10/05: Matthias Fuchs: Re: CoreGenerator and WebPack ISE
35550: 01/10/10: Manfred Kraus: Re: CoreGenerator and WebPack ISE
35431: 01/10/04: Nicolas Matringe: Xilinx Spartan2E samples availability?
35438: 01/10/04: Rick Filipkiewicz: Re: Xilinx Spartan2E samples availability?
35449: 01/10/05: Nicolas Matringe: Re: Xilinx Spartan2E samples availability?
35434: 01/10/04: Ivana Raffe: input signal frequency
35436: 01/10/04: Falk Brunner: Re: input signal frequency
35437: 01/10/04: Peter Alfke: Re: input signal frequency
35435: 01/10/04: Oliver Meike: Converting VHDL into state machine with FPGA advantage 5.1
35445: 01/10/05: Klaus Falser: Beware : Xilinx JTAG programmer Impact does not support older XC9500s
35447: 01/10/05: Jo Kenens: Xilinx XST synthesis signal naming
35471: 01/10/06: Newman5382: Re: Xilinx XST synthesis signal naming
35450: 01/10/05: Andrea Sabatini: QuartusII compiler error message
35454: 01/10/05: Andrew Barnish: ROM based FSMs
35455: 01/10/05: Sergio Masci: Re: ROM based FSMs
35456: 01/10/05: Ray Andraka: Re: ROM based FSMs
35466: 01/10/06: Sergio Masci: Re: ROM based FSMs
35462: 01/10/06: Rick Filipkiewicz: Re: ROM based FSMs
35463: 01/10/06: Ray Andraka: Re: ROM based FSMs
35467: 01/10/06: Rick Filipkiewicz: Re: ROM based FSMs
35468: 01/10/06: Sergio Masci: Re: ROM based FSMs
35469: 01/10/06: Ray Andraka: Re: ROM based FSMs
35472: 01/10/06: Peter Alfke: Re: ROM based FSMs
35478: 01/10/07: Rick Filipkiewicz: Re: ROM based FSMs
35480: 01/10/07: Ray Andraka: Re: ROM based FSMs
35482: 01/10/07: Rick Filipkiewicz: Re: ROM based FSMs
35484: 01/10/07: Ray Andraka: Re: ROM based FSMs
35502: 01/10/08: Falk Brunner: Re: ROM based FSMs
35495: 01/10/08: <hamish@cloud.net.au>: Re: ROM based FSMs
35465: 01/10/06: Sergio Masci: Re: ROM based FSMs
35473: 01/10/06: Andrew Barnish: Re: ROM based FSMs
35475: 01/10/07: Sergio Masci: Re: ROM based FSMs
35476: 01/10/07: Ray Andraka: Re: ROM based FSMs
35477: 01/10/07: Falk Brunner: Re: ROM based FSMs
35481: 01/10/07: Ray Andraka: Re: ROM based FSMs
35508: 01/10/09: Hal Murray: Re: ROM based FSMs
35511: 01/10/09: Martin Thompson: Re: ROM based FSMs
35457: 01/10/05: Mike Treseler: Re: ROM based FSMs
35464: 01/10/06: Sergio Masci: Re: ROM based FSMs
35500: 01/10/08: Mike Treseler: Re: ROM based FSMs
35503: 01/10/08: Peter Alfke: Re: ROM based FSMs
35506: 01/10/09: Jim Granville: Re: ROM based FSMs
35496: 01/10/08: Jonathan Bromley: Re: ROM based FSMs
35497: 01/10/08: Jonathan Bromley: Re: ROM based FSMs
35458: 01/10/05: Ben: Video processing
35459: 01/10/05: Ray Andraka: Re: Video processing
35485: 01/10/07: Jolly Joker: Re: Video processing
35543: 01/10/10: Ahmed Shihab: Re: Video processing
35461: 01/10/06: S. Ramirez: Synplify vs. Leonardo
35501: 01/10/08: Mike Treseler: Re: Synplify vs. Leonardo
35479: 01/10/07: luigi funes: Altera LCELL and output pins
35489: 01/10/07: VLSI: IEEE 802.11 Design
35490: 01/10/07: Sriram S: VIRTEX-II PCIX CORE
35491: 01/10/08: himanshu: Virtex-2 maximum clock speed
35523: 01/10/09: Speedy Zero Two: Re: Virtex-2 maximum clock speed
35531: 01/10/10: Peter Alfke: Re: Virtex-2 maximum clock speed
35553: 01/10/10: Austin Lesea: Re: Virtex-2 maximum clock speed
35558: 01/10/10: Falk Brunner: Re: Virtex-2 maximum clock speed
35563: 01/10/10: Ray Andraka: Re: Virtex-2 maximum clock speed
35574: 01/10/10: Austin Lesea: Re: Virtex-2 maximum clock speed
35576: 01/10/11: Hal Murray: Re: Virtex-2 maximum clock speed
35610: 01/10/11: Falk Brunner: Re: Virtex-2 maximum clock speed
35614: 01/10/11: Tim: Re: Virtex-2 maximum clock speed
35617: 01/10/12: Tim: Re: Virtex-2 maximum clock speed
37942: 01/12/26: Carl Brannen: Re: Virtex-2 maximum clock speed
38038: 02/01/02: Austin Lesea: Re: Virtex-2 maximum clock speed
38040: 02/01/02: Rick Filipkiewicz: Re: Virtex-2 maximum clock speed
38061: 02/01/03: Kevin Brace: Re: Virtex-2 maximum clock speed
38063: 02/01/03: Andy Peters: Re: Virtex-2 maximum clock speed
38599: 02/01/18: William Vollrath: Re: Virtex-2 maximum clock speed
37873: 01/12/22: Otomo: Re: Virtex-2 maximum clock speed
35498: 01/10/08: Paul Butler: Synplify and internal tristate
35504: 01/10/08: Rajeev Jayaraman: Call For Papers - Special Issue on Programmable Logic (ACM Trans. on
35507: 01/10/09: Peter Alfke: Re: Call For Papers - Special Issue on Programmable Logic (ACM Trans. on
35505: 01/10/08: Theron Hicks: virtex2 simulation and modelsim_xe/starter 5.5b
35509: 01/10/08: jas: FPGA reset
35510: 01/10/09: Hal Murray: Re: FPGA reset
35513: 01/10/09: Andrew Brown: Re: FPGA reset
35517: 01/10/09: Jason Daughenbaugh: Re: FPGA reset
35512: 01/10/09: Philip Freidin: Re: FPGA reset
35518: 01/10/09: Austin Franklin: Re: FPGA reset
35524: 01/10/09: Tom Seim: Re: FPGA reset
35532: 01/10/10: Peter Alfke: Re: FPGA reset
35556: 01/10/10: Tom Seim: Re: FPGA reset
35561: 01/10/10: Peter Alfke: Re: FPGA reset
35579: 01/10/11: Hal Murray: Re: FPGA reset
35593: 01/10/11: Ray Andraka: Re: FPGA reset
35514: 01/10/09: Sebastian: microblaze?
35515: 01/10/09: Radó Zoltán: VHDL code
35522: 01/10/09: Speedy Zero Two: Re: VHDL code
35537: 01/10/10: Tamas Csetkovics: Re: VHDL code
35519: 01/10/09: n_d_solanki: Re. gate count comparison of diff tap size for PDA FIR filter
35520: 01/10/09: Michael Feygin: Help in speeding up image processing
35530: 01/10/10: Tom Dillon: Re: Help in speeding up image processing
35521: 01/10/09: Andrew Gray: Help reading from SmartMedia cards
35528: 01/10/09: Lachlan J Follett: Re: Help reading from SmartMedia cards
35529: 01/10/09: Lachlan J Follett: Re: Help reading from SmartMedia cards
35546: 01/10/10: Kolja Sulimma: Re: Help reading from SmartMedia cards
35535: 01/10/09: Ste: Re: Help reading from SmartMedia cards
35525: 01/10/09: Richard Meester: anyone know of SDRDRAM controller for free?
35536: 01/10/10: Martin Thompson: Re: anyone know of SDRDRAM controller for free?
35526: 01/10/09: S. Ramirez: Synplify vs. Leonardo
35565: 01/10/10: Rick Filipkiewicz: Re: Synplify vs. Leonardo
35527: 01/10/09: S. Ramirez: Synplicity/Leonardo License Agreement Information
35533: 01/10/10: Zoltan Kocsi: Re: Synplicity/Leonardo License Agreement Information
35534: 01/10/09: Austin Franklin: Re: Synplicity/Leonardo License Agreement Information
35557: 01/10/10: Tom Seim: Re: Synplicity/Leonardo License Agreement Information
35566: 01/10/10: Rick Filipkiewicz: Re: Synplicity/Leonardo License Agreement Information
35567: 01/10/11: Jim Granville: Re: Synplicity/Leonardo License Agreement Information
35568: 01/10/10: Rick Filipkiewicz: Re: Synplicity/Leonardo License Agreement Information
35575: 01/10/10: Jeff Cunningham: Re: Synplicity/Leonardo License Agreement Information
35672: 01/10/13: Andy Peters: Re: Synplicity/Leonardo License Agreement Information
35694: 01/10/13: Brian Davis: Re: Synplicity/Leonardo License Agreement Information
35719: 01/10/15: Ken McElvain: Re: Synplicity/Leonardo License Agreement Information
35696: 01/10/13: Brian Davis: Re: Synplicity/Leonardo License Agreement Information
35721: 01/10/15: Ken McElvain: Re: Synplicity/Leonardo License Agreement Information
35755: 01/10/16: Andy Peters: Re: Synplicity/Leonardo License Agreement Information
35538: 01/10/10: Andrew Gray: Linking components in VHDL
35554: 01/10/10: Mike Treseler: Re: Linking components in VHDL
35578: 01/10/11: Andrew Gray: Re: Linking components in VHDL
35588: 01/10/11: Andrew Gray: I found the error
35612: 01/10/11: Andy Peters: Re: Linking components in VHDL
35624: 01/10/12: balakrishnan: Re: Linking components in VHDL
35539: 01/10/10: Justin Cui: Who knows the news server of synplicity?
35540: 01/10/10: Utku Ozcan: Re: Who knows the news server of synplicity?
35541: 01/10/10: Rini.vDijk: vhdl code keyboard controller 8279
35542: 01/10/10: Erik Lins: Handel-C
35547: 01/10/10: Tim: Re: Handel-C
35625: 01/10/12: Erik Lins: Re: Handel-C
35785: 01/10/17: Erik Lins: Re: Handel-C
35631: 01/10/12: Chris: Re: Handel-C
35544: 01/10/10: Hermann Winkler: Virtex2 DCM: frequenqy synthesis
35592: 01/10/11: Apllehead: Re: Virtex2 DCM: frequenqy synthesis
35597: 01/10/11: Austin Lesea: Re: Virtex2 DCM: frequenqy synthesis
35545: 01/10/10: eas: qpsk clock recovery
35549: 01/10/10: Ray Andraka: Re: qpsk clock recovery
35555: 01/10/10: Bhaskar Thiagarajan: Re: qpsk clock recovery
35591: 01/10/11: eas: Re: qpsk clock recovery
35603: 01/10/11: Eric Jacobsen: Re: qpsk clock recovery
36047: 01/10/26: Tony San: Re: qpsk clock recovery
36084: 01/10/28: Abhijit Patait: Re: qpsk clock recovery
35548: 01/10/10: Theron Hicks: contract assembler for BGA based board???
35613: 01/10/11: Alex Sherstuk: Re: contract assembler for BGA based board???
35559: 01/10/10: Falk Brunner: Re: 155MHz to DLL in Spartan II
35560: 01/10/10: Kolja Sulimma: Re: 155MHz to DLL in Spartan II
35564: 01/10/10: Falk Brunner: Re: 155MHz to DLL in Spartan II
35573: 01/10/10: Peter Alfke: Re: 155MHz to DLL in Spartan II
35577: 01/10/11: Hal Murray: Re: 155MHz to DLL in Spartan II
35562: 01/10/10: Ray Andraka: Re: 155MHz to DLL in Spartan II
35580: 01/10/11: Ulises Hernandez: Re: 155MHz to DLL in Spartan II
35552: 01/10/10: Ulises Hernandez: 155MHz to a DLL in Spartan II
35569: 01/10/10: Don Husby: High level synthesis will never work well :)
35570: 01/10/10: Rick Filipkiewicz: Re: High level synthesis will never work well :)
35581: 01/10/11: Andrew Brown: Re: High level synthesis will never work well :)
35628: 01/10/12: Rick Filipkiewicz: Re: High level synthesis will never work well :)
35632: 01/10/12: Andrew Brown: Re: High level synthesis will never work well :)
35601: 01/10/11: Don Husby: Re: High level synthesis will never work well :)
35607: 01/10/11: Falk Brunner: Re: High level synthesis will never work well :)
35639: 01/10/12: Martin Thompson: Re: High level synthesis will never work well :)
35606: 01/10/11: Falk Brunner: Re: High level synthesis will never work well :)
35611: 01/10/11: NotMe: Re: High level synthesis will never work well :)
35626: 01/10/12: Andrew Brown: Re: High level synthesis will never work well :)
35653: 01/10/12: Falk Brunner: Re: High level synthesis will never work well :)
35671: 01/10/13: Andy Peters: Re: High level synthesis will never work well :)
35677: 01/10/12: Jan Gray: Re: High level synthesis will never work well :)
35702: 01/10/14: Falk Brunner: Re: High level synthesis will never work well :)
35776: 01/10/17: Utku Ozcan: Re: High level synthesis will never work well :)
36217: 01/11/02: <Iwo.mergler@soton.sc.philips.com>: Re: High level synthesis will never work well :)
36219: 01/11/02: Petter Gustad: Re: High level synthesis will never work well :)
36278: 01/11/05: Andrew Brown: Re: High level synthesis will never work well :)
36279: 01/11/05: Petter Gustad: Re: High level synthesis will never work well :)
35589: 01/10/11: =?ISO-8859-1?Q?L=E4hteenm=E4ki?= Jussi: Re: High level synthesis will never work well :)
35590: 01/10/11: Andrew Brown: Re: High level synthesis will never work well :)
35594: 01/10/11: Ray Andraka: Re: High level synthesis will never work well :)
35595: 01/10/11: Andrew Brown: Re: High level synthesis will never work well :)
35596: 01/10/11: Allan Herriman: Re: High level synthesis will never work well :)
35605: 01/10/11: Ray Andraka: Re: High level synthesis will never work well :)
35609: 01/10/11: Philip Freidin: Re: High level synthesis will never work well :)
35615: 01/10/11: Don Husby: Re: High level synthesis will never work well :)
35618: 01/10/11: Vitaliy Tkachenko: Re: High level synthesis will never work well :)
35619: 01/10/12: <()>: Re: High level synthesis will never work well :)
35620: 01/10/12: Don Husby: Re: High level synthesis will never work well :)
35640: 01/10/12: Ray Andraka: Re: High level synthesis will never work well :)
35644: 01/10/12: Andrew Brown: Re: High level synthesis will never work well :)
35649: 01/10/12: Tim: Re: High level synthesis will never work well :)
35663: 01/10/12: Ken McElvain: Re: High level synthesis will never work well :)
35681: 01/10/13: Rick Filipkiewicz: Re: High level synthesis will never work well :)
36195: 01/11/01: Ken McElvain: Re: High level synthesis will never work well :)
35659: 01/10/12: Don Husby: Re: High level synthesis will never work well :)
35651: 01/10/12: Brian Davis: Re: High level synthesis will never work well :)
35654: 01/10/12: Rene Tschaggelar: Re: High level synthesis will never work well :)
35797: 01/10/17: Josh Fryman: Re: High level synthesis will never work well :)
35571: 01/10/10: Ras Sim: I need free PCI-Core (vhdl)!!
35616: 01/10/11: Kevin Brace: Re: I need free PCI-Core (vhdl)!!
35641: 01/10/12: Ray Andraka: Re: I need free PCI-Core (vhdl)!!
35676: 01/10/12: Kevin Brace: Re: I need free PCI-Core (vhdl)!!
35684: 01/10/13: Kolja Sulimma: Re: I need free PCI-Core (vhdl)!!
35735: 01/10/15: Kevin Brace: Re: I need free PCI-Core (vhdl)!!
35817: 01/10/18: Tom Seim: Re: I need free PCI-Core (vhdl)!!
35678: 01/10/12: Ru-Chin Tsai: Re: I need free PCI-Core (vhdl)!!
35706: 01/10/14: Uwe Bonnes: Re: I need free PCI-Core (vhdl)!!
35582: 01/10/11: Philippe Robert: Dual Port Fifo for Virtex II
35598: 01/10/11: Peter Alfke: Re: Dual Port Fifo for Virtex II
35583: 01/10/11: Leo Breuss: Timing constraints for unrelated clocks?
35586: 01/10/11: fred: Re: Timing constraints for unrelated clocks?
35645: 01/10/12: Leo Breuss: Re: Timing constraints for unrelated clocks?
35662: 01/10/12: Mike Treseler: Re: Timing constraints for unrelated clocks?
35712: 01/10/15: fred: Re: Timing constraints for unrelated clocks?
35723: 01/10/15: Leo Breuss: Re: Timing constraints for unrelated clocks?
35727: 01/10/15: fred: Re: Timing constraints for unrelated clocks?
35754: 01/10/16: Andy Peters: Re: Timing constraints for unrelated clocks?
35584: 01/10/11: thao: Error : Operand divide
35630: 01/10/12: Rick Filipkiewicz: Re: Error : Operand divide
35585: 01/10/11: Rini.van.Dijk: vhdl code keyboard controller
35587: 01/10/11: Nisreen Taiyeby: Exemplar : LUT's are ix & Nets are nx
35599: 01/10/11: Theron Hicks: DCM simulation results do not match part spec's
35600: 01/10/11: Markus Meng: [Spartan-XL] Driving a BUFGS from a std. IO ...
35608: 01/10/11: Falk Brunner: Re: [Spartan-XL] Driving a BUFGS from a std. IO ...
35602: 01/10/11: Stephen Byrne: Use of Global in Altera FLEX 10KA
35646: 01/10/12: Martin Thompson: Re: Use of Global in Altera FLEX 10KA
35604: 01/10/11: A. de Boer: Tool qualification for airborne hardware, DO-254
35621: 01/10/11: Gautam: Block RAMs
35622: 01/10/12: Peter Alfke: Re: Block RAMs
35623: 01/10/12: Peter Alfke: Re: Block RAMs
35670: 01/10/13: R Allen: Re: Block RAMs
35629: 01/10/12: Martin Fischer: PWM Signal in VHDL ?
35633: 01/10/12: Panu H: Re: PWM Signal in VHDL ?
35634: 01/10/12: Thomas Stanka: Re: PWM Signal in VHDL ?
35647: 01/10/12: Manfred Kraus: Re: PWM Signal in VHDL ?
35831: 01/10/18: Brian Philofsky: Re: PWM Signal in VHDL ?
35635: 01/10/12: Huang Qiang: Problem about Leonardo Spectrum with Altera MaxPlus II
35718: 01/10/15: Wolfgang Loewer: Re: Problem about Leonardo Spectrum with Altera MaxPlus II
35636: 01/10/12: M. Praekelt: Lattice discontinues all smaller MACH circuits and other devices
35660: 01/10/12: Gerald Coe: Re: Lattice discontinues all smaller MACH circuits and other devices
35674: 01/10/13: Jim Granville: Re: Lattice discontinues all smaller MACH circuits and other devices
35667: 01/10/12: Richard Steven Walz: Re: Lattice discontinues all smaller MACH circuits and other devices
35688: 01/10/13: Gerald Coe: Re: Lattice discontinues all smaller MACH circuits and other devices
35637: 01/10/12: Panu H: Re: PWM Signal in VHDL ?
35642: 01/10/12: Ray Andraka: Re: PWM Signal in VHDL ?
35650: 01/10/12: Jonathan Bromley: Re: PWM Signal in VHDL ?
35685: 01/10/13: renaux: Re: PWM Signal in VHDL ?
35638: 01/10/12: Arthur Sharp: Small FPGA proto boards
35643: 01/10/12: Ray Andraka: Re: Small FPGA proto boards
35661: 01/10/12: John Jakson: Re: Small FPGA proto boards
35648: 01/10/12: Dan Oprisan: max+plus2 under winNT
35652: 01/10/12: Juergen Otterbach: Reassemble a BGA560 device
35656: 01/10/12: Rene Tschaggelar: Re: Reassemble a BGA560 device
35657: 01/10/12: Ben: Re: Reassemble a BGA560 device
35664: 01/10/12: Mike Treseler: Re: Reassemble a BGA560 device
35668: 01/10/13: Tim: Re: Reassemble a BGA560 device
35682: 01/10/13: Rick Filipkiewicz: Re: Reassemble a BGA560 device
36626: 01/11/13: Alex Rast: Re: Reassemble a BGA560 device
36632: 01/11/13: Eric Smith: Re: Reassemble a BGA560 device
35666: 01/10/12: Johan Ditmar: how do I avoid glitches in this design?
35687: 01/10/13: Philip Freidin: Re: how do I avoid glitches in this design?
35701: 01/10/14: Falk Brunner: Re: how do I avoid glitches in this design?
35705: 01/10/14: Bob Perlman: Re: how do I avoid glitches in this design?
35673: 01/10/12: Alan Nishioka: How do you program Xilinx XC18V00?
35686: 01/10/13: Phil Short: FPGA Asynchronous Design
35689: 01/10/13: Ray Andraka: Re: FPGA Asynchronous Design
35695: 01/10/14: Phil Short: Re: FPGA Asynchronous Design
35703: 01/10/14: Ray Andraka: Re: FPGA Asynchronous Design
35690: 01/10/13: Marko: Instantiating Virtex II library macros.
35699: 01/10/14: <hamish@cloud.net.au>: Re: Instantiating Virtex II library macros.
35704: 01/10/14: Ray Andraka: Re: Instantiating Virtex II library macros.
35745: 01/10/16: <hamish@cloud.net.au>: Re: Instantiating Virtex II library macros.
35752: 01/10/16: Ray Andraka: Re: Instantiating Virtex II library macros.
35756: 01/10/16: Petter Gustad: Re: Instantiating Virtex II library macros.
35691: 01/10/13: Marko: How to instantiate I/O port with both registered input and output?
35692: 01/10/13: Tim: Re: How to instantiate I/O port with both registered input and output?
35700: 01/10/14: Rick Filipkiewicz: Re: How to instantiate I/O port with both registered input and output?
35709: 01/10/14: Gautam: PLLs & DLLs
35711: 01/10/15: Falk: Re: PLLs & DLLs
35728: 01/10/15: Peter Alfke: Re: PLLs & DLLs
35729: 01/10/15: Austin Lesea: Re: PLLs & DLLs
35739: 01/10/16: <Graham>: Re: PLLs & DLLs
35742: 01/10/16: Gautam: Re: PLLs & DLLs
35760: 01/10/17: Peter Ormsby: Re: PLLs & DLLs
35763: 01/10/17: Peter Alfke: Re: PLLs & DLLs
35765: 01/10/17: Peter Ormsby: Re: PLLs & DLLs
35714: 01/10/15: Noddy: Improving timing
35717: 01/10/15: Rick Filipkiewicz: Re: Improving timing
35738: 01/10/16: Noddy: Re: Improving timing
35716: 01/10/15: Hayden So: Spartan2: opposite of Synch-to-DONE?
35720: 01/10/15: Marc Reinert: JTAG-Programmer Linux
35724: 01/10/15: Stefano Ho: Re: JTAG-Programmer Linux
35725: 01/10/15: mariani: help request about lattice isp 1032
35731: 01/10/15: Mikeandmax: Re: help request about lattice isp 1032
35726: 01/10/15: C.Hermine: ask for ispLSI 1016
35730: 01/10/15: C.Hermine: ask for ispLSI 1016
36819: 01/11/21: Tim Forcer: Re: ask for ispLSI 1016
35732: 01/10/15: Ben Franchuk: Re: System Gates
35733: 01/10/15: Dave Brown: SpartanXL bidirectional buffers
35734: 01/10/16: Ray Andraka: Re: System Gates
35736: 01/10/16: AH: open-drain bidirs in xilinx or altera
35740: 01/10/16: Martin Thompson: Re: open-drain bidirs in xilinx or altera
35792: 01/10/17: Henk Bliek: Re: open-drain bidirs in xilinx or altera
35805: 01/10/18: Martin Thompson: Re: open-drain bidirs in xilinx or altera
35741: 01/10/16: luigi funes: Re: System Gates
35744: 01/10/16: Kolja Sulimma: Re: System Gates
35743: 01/10/16: Georg Acher: Xilinx coregen and Linux (success)
35746: 01/10/16: Paul Teagle: Programming interface reference designs
35747: 01/10/16: thilo jeremias: Repost: Fine graine vs coarse graine FPGA
35748: 01/10/16: Jan Gray: Re: System Gates
35768: 01/10/17: Thomas Stanka: Re: System Gates
35770: 01/10/17: Kolja Sulimm: Re: System Gates
35749: 01/10/16: mounther: 1024 point non-complex FFT on a SPARTAN2
35751: 01/10/16: Ray Andraka: Re: 1024 point non-complex FFT on a SPARTAN2
35750: 01/10/16: Allan Herriman: LUT Glitches
35753: 01/10/16: Peter Alfke: Re: LUT Glitches
35762: 01/10/17: Allan Herriman: Re: LUT Glitches
35758: 01/10/16: Falk Brunner: Re: LUT Glitches
35764: 01/10/17: Peter Alfke: Re: LUT Glitches
35780: 01/10/17: rk: Re: LUT Glitches
35766: 01/10/17: Jim Granville: Re: LUT Glitches
35786: 01/10/17: Bob Perlman: Re: LUT Glitches
35922: 01/10/24: glen herrmannsfeldt: Re: LUT Glitches
35991: 01/10/25: Andy Peters: Re: LUT Glitches
36006: 01/10/25: glen herrmannsfeldt: Re: LUT Glitches
36011: 01/10/26: Bob Perlman: Re: LUT Glitches
36031: 01/10/26: glen herrmannsfeldt: Re: LUT Glitches
36038: 01/10/26: Neil Franklin: Re: LUT Glitches
36066: 01/10/27: glen herrmannsfeldt: Re: LUT Glitches
35757: 01/10/16: Seb: pci-card with Virtex2?
35773: 01/10/17: Ken: Re: pci-card with Virtex2?
35781: 01/10/17: Erik Lins: Re: pci-card with Virtex2?
35794: 01/10/18: Seb: Re: pci-card with Virtex2?
35796: 01/10/17: Phil James-Roxby: Re: pci-card with Virtex2?
35798: 01/10/18: Seb: Re: pci-card with Virtex2?
36152: 01/10/31: Andreas Kugel: Re: pci-card with Virtex2?
35759: 01/10/16: qlyus: Is Xilinx AppNote#258 correctly documented ?
35761: 01/10/17: Peter Ormsby: Re: System Gates
35767: 01/10/17: #BASUKI ENDAH PRIYANTO#: Xilinx 64 Point FFT Core Problem
35774: 01/10/17: John Adair: Re: Xilinx 64 Point FFT Core Problem
35769: 01/10/17: Noddy: Recommended Newsgroup
35771: 01/10/17: Jan Pech: Re: Recommended Newsgroup
35778: 01/10/17: Leon Heller: Re: Recommended Newsgroup
35791: 01/10/17: MK: Re: Recommended Newsgroup
35793: 01/10/18: Jim Granville: Re: Recommended Newsgroup
35772: 01/10/17: Paul Teagle: Phase noise of Xilinx/Altera DLL/PLL
35807: 01/10/18: Falk Brunner: Re: Phase noise of Xilinx/Altera DLL/PLL
35816: 01/10/18: Austin Lesea: Re: Phase noise of Xilinx/Altera DLL/PLL
35833: 01/10/19: Falk Brunner: Re: Phase noise of Xilinx/Altera DLL/PLL
36112: 01/10/30: Ian Dedic: Re: Phase noise of Xilinx/Altera DLL/PLL
36117: 01/10/30: Austin Lesea: Re: Phase noise of Xilinx/Altera DLL/PLL
36136: 01/10/31: Paul Teagle: Re: Phase noise of Xilinx/Altera DLL/PLL
35775: 01/10/17: Tom St Denis: memory cell
35777: 01/10/17: Jonathan Bromley: Re: memory cell
35779: 01/10/17: Tom St Denis: Re: memory cell
35789: 01/10/17: NotMe: Re: memory cell
35782: 01/10/17: Theron Hicks: simple question
35784: 01/10/17: Jonathan Bromley: Re: simple question
35810: 01/10/18: Theron Hicks: Re: simple question
35827: 01/10/18: Andy Peters: Re: simple question
35783: 01/10/17: eas: Digital mixers,complex multipliers
35788: 01/10/17: Topi Maurola: Re: Digital mixers,complex multipliers
35837: 01/10/19: John_H: Re: Digital mixers,complex multipliers
35787: 01/10/17: Vladimir: Could VirtexII multiplier work faster?
35795: 01/10/17: Tony Kirke: SDRAM Controller for Xilinx Virtex
35806: 01/10/18: Martin Thompson: Re: SDRAM Controller for Xilinx Virtex
35799: 01/10/18: Jack: Career advice in fpga/asic design
35804: 01/10/18: Rene Tschaggelar: Re: Career advice in fpga/asic design
35812: 01/10/18: Mike Treseler: Re: Career advice in fpga/asic design
35830: 01/10/19: Rick Filipkiewicz: Re: Career advice in fpga/asic design
35834: 01/10/19: Falk Brunner: Re: Career advice in fpga/asic design
35801: 01/10/18: John Smith: Xilinx PCI core and XST
35818: 01/10/18: Mark Aaldering: Re: Xilinx PCI core and XST
35967: 01/10/25: Tobias Stumber: Re: Xilinx PCI core and XST
35802: 01/10/18: sudin: 8051 timing diagrams
35803: 01/10/18: Tom St Denis: Re: 8051 timing diagrams
35813: 01/10/18: Ivar: Re: 8051 timing diagrams
36082: 01/10/28: ivar: Re: 8051 timing diagrams
35808: 01/10/18: Ben: Firewire chipset
35814: 01/10/18: Jan Pech: Re: Firewire chipset
35820: 01/10/18: Ben: Re: Firewire chipset
35821: 01/10/18: Christoph Hauzeneder: Re: Firewire chipset
35826: 01/10/19: Ben: Re: Firewire chipset
35867: 01/10/21: Dan: To Christoph Hauze
36074: 01/10/27: Jeff Cunningham: Re: Firewire chipset
36114: 01/10/30: electron-man: Re: Firewire chipset
36157: 01/10/31: Eric Braeden: Re: Firewire chipset
35809: 01/10/18: RS: VirtexII ES
35811: 01/10/18: Austin Lesea: Re: VirtexII ES
35815: 01/10/18: Falk Brunner: Glitch Hunting, a true story ;-)
35841: 01/10/19: Rick Filipkiewicz: Re: Glitch Hunting, a true story ;-)
35842: 01/10/19: Peter Alfke: Re: Glitch Hunting, a true story ;-)
35843: 01/10/19: Austin Lesea: Re: Glitch Hunting, a true story ;-)
35848: 01/10/20: Rick Filipkiewicz: Re: Glitch Hunting, a true story ;-)
35844: 01/10/19: Tom Burgess: Re: Glitch Hunting, a true story ;-)
35846: 01/10/20: Bob Perlman: Re: Glitch Hunting, a true story ;-)
35847: 01/10/20: Rick Filipkiewicz: Re: Glitch Hunting, a true story ;-)
35890: 01/10/22: Andy Peters: Re: Glitch Hunting, a true story ;-)
35822: 01/10/18: Eric LaForest: XST verilog synthesis of Virtex-II BlockRAM
35823: 01/10/18: Dave Brown: Timing Constarint Error message
35824: 01/10/18: Mike Treseler: Re: Timing Constarint Error message
35825: 01/10/18: Dave Brown: Re: Timing Constarint Error message
35829: 01/10/18: Andy Peters: Re: Timing Constarint Error message
35832: 01/10/19: Rick Filipkiewicz: Re: Timing Constarint Error message
35838: 01/10/19: Dave Brown: Re: Timing Constarint Error message
35840: 01/10/19: Rick Filipkiewicz: Re: Timing Constarint Error message
35828: 01/10/18: Nandini: map,place &route
35930: 01/10/24: Nicolas Matringe: Re: map,place &route
35835: 01/10/19: Falk Brunner: Re: unused I/O cell
35836: 01/10/19: A. Chemeris: About BLIF
35874: 01/10/22: Utku Ozcan: Re: About BLIF
35839: 01/10/19: TonyS2: FS Data I/O 2900 Prog Fixture
35845: 01/10/19: Jack Tai: memory dump for Xilinx block ram
35971: 01/10/25: Jim: Re: memory dump for Xilinx block ram
35849: 01/10/20: Radó Zoltán: I search a free 8086 core...
35856: 01/10/20: Jan Gray: Re: I search a free 8086 core...
35861: 01/10/21: Philipp Krause: Re: I search a free 8086 core...
35850: 01/10/20: Marc Battyani: what is carry mode INC-F-CI ?
35851: 01/10/20: Ramnath: Xilinx Libraries
35852: 01/10/20: Ramnath: Fpga Synthesis Process
35934: 01/10/24: Johan Van Dyck: Re: Fpga Synthesis Process
35968: 01/10/25: krishna P V: Re: Fpga Synthesis Process
36888: 01/11/23: Ramnath: Re: Fpga Synthesis Process
35853: 01/10/20: AME: Verilog vs. VHDL
35854: 01/10/21: rafael plonka: Re: Verilog vs. VHDL
35855: 01/10/20: AME: Re: Verilog vs. VHDL
36101: 01/10/29: rickman: Re: Verilog vs. VHDL
36191: 01/11/01: Richard Iachetta: Re: Verilog vs. VHDL
35857: 01/10/21: <hamish@cloud.net.au>: Re: Verilog vs. VHDL
35865: 01/10/21: AME: Re: Verilog vs. VHDL
35883: 01/10/22: Edwin Naroska: Re: Verilog vs. VHDL
35886: 01/10/22: Rick Filipkiewicz: Re: Verilog vs. VHDL
35935: 01/10/24: <tgingold@pc204.ipricot.fr>: Re: Verilog vs. VHDL
35944: 01/10/24: Andy Peters: Re: Verilog vs. VHDL
35984: 01/10/25: Falk Brunner: Re: Verilog vs. VHDL
35931: 01/10/24: <hamish@cloud.net.au>: Re: Verilog vs. VHDL
35860: 01/10/21: Brian Drummond: Re: Verilog vs. VHDL
35872: 01/10/21: AME: Re: Verilog vs. VHDL
35875: 01/10/22: Thomas Stanka: Re: Verilog vs. VHDL
35880: 01/10/22: Utku Ozcan: Re: Verilog vs. VHDL
35866: 01/10/21: Kevin Brace: Re: Verilog vs. VHDL
35868: 01/10/21: AME: Re: Verilog vs. VHDL
35932: 01/10/24: <hamish@cloud.net.au>: Re: Verilog vs. VHDL
35869: 01/10/22: Ray Andraka: Re: Verilog vs. VHDL
35898: 01/10/22: Kevin Brace: Re: Verilog vs. VHDL
35912: 01/10/23: Ray Andraka: Re: Verilog vs. VHDL
35889: 01/10/22: Andy Peters: Re: Verilog vs. VHDL
35897: 01/10/22: Kevin Brace: Re: Verilog vs. VHDL
35904: 01/10/23: Andrew Brown: Re: Verilog vs. VHDL
35906: 01/10/23: Tim: Re: Verilog vs. VHDL
35919: 01/10/24: Rick Filipkiewicz: Re: Verilog vs. VHDL
35911: 01/10/23: Ray Andraka: Re: Verilog vs. VHDL
35926: 01/10/23: AME: Re: Verilog vs. VHDL
35927: 01/10/24: Andrew Brown: Re: Verilog vs. VHDL
35943: 01/10/24: Andy Peters: Re: Verilog vs. VHDL
35952: 01/10/24: AME: Re: Verilog vs. VHDL
35917: 01/10/23: Magnus Homann: Re: Verilog vs. VHDL
35920: 01/10/24: Andy Peters: Re: Verilog vs. VHDL
35925: 01/10/23: AME: Re: Verilog vs. VHDL
36080: 01/10/28: Antonio Pasini: Re: Verilog vs. VHDL
36098: 01/10/29: AME: Re: Verilog vs. VHDL
36245: 01/11/03: Antonio Pasini: Re: Verilog vs. VHDL
36344: 01/11/06: AME: Re: Verilog vs. VHDL
35882: 01/10/22: Dan Oprisan: Re: Verilog vs. VHDL
35894: 01/10/22: John Jakson: Re: Verilog vs. VHDL
35858: 01/10/21: Antonio D'Ottavio: Interpolating in QPSK with f_IF = f_clk/4
36052: 01/10/26: Tony San: Re: Interpolating in QPSK with f_IF = f_clk/4
35859: 01/10/21: Ramnath: FPGA based IPv6 router -- hi
35871: 01/10/22: Srinivasan Venkataramanan: Re: FPGA based IPv6 router -- hi
35862: 01/10/21: rs: Virtex II powerdown
35864: 01/10/21: Eric Crabill: Re: Virtex II powerdown
35873: 01/10/22: Tomasz Brychcy: What is a difference?
35885: 01/10/22: Tom: Re: What is a difference?
35895: 01/10/22: Peter Alfke: Re: What is a difference?
35877: 01/10/22: pfor: Maser Serial Config Problem
35884: 01/10/22: Falk Brunner: Re: Maser Serial Config Problem
35896: 01/10/22: Peter Alfke: Re: Maser Serial Config Problem
35878: 01/10/22: Erik Lins: one-hot statemachine
35888: 01/10/22: Andy Peters: Re: one-hot statemachine
35891: 01/10/22: Rick Filipkiewicz: Re: one-hot statemachine
35879: 01/10/22: Kolja Sulimma: Looking for benchmark bitstreams
35881: 01/10/22: Allan Aasma: Problems with writing into text file
35887: 01/10/22: Andy Peters: Re: Problems with writing into text file
35900: 01/10/23: Martin Thompson: Re: Problems with writing into text file
35892: 01/10/22: Dave Brown: Xilinx Functrional Schematic, extra elemtents?
35893: 01/10/22: Tom St Denis: Hardware help requested
35899: 01/10/23: Internet-PC: Re: Hardware help requested
35901: 01/10/23: <golov@sony>: ModelSim SE vs. PE in terms of speed?
35903: 01/10/23: Allan Herriman: Re: ModelSim SE vs. PE in terms of speed?
35902: 01/10/23: Peter: Are there any Coolrunner P5Z22V10 (PLCC) devices left anywhere?
35914: 01/10/24: Jim Granville: Re: Are there any Coolrunner P5Z22V10 (PLCC) devices left anywhere?
35941: 01/10/24: Andy Peters: Re: Are there any Coolrunner P5Z22V10 (PLCC) devices left anywhere?
35939: 01/10/24: Peter Alfke: Re: Are there any Coolrunner P5Z22V10 (PLCC) devices left anywhere?
36094: 01/10/29: Peter: Re: Are there any Coolrunner P5Z22V10 (PLCC) devices left anywhere?
35905: 01/10/23: Wade D. Peterson: WISHBONE / SoC Interconnect / IP Core
35907: 01/10/23: John Branthoover: Newbie: Need Help With Xilinx State Machine Using ABEL.....
35909: 01/10/23: John Branthoover: Re: Newbie: Need Help With Xilinx State Machine Using ABEL.....
35908: 01/10/23: Anton Zechner: comp.arch.fpg : Reconfiguring of a virtex via JTAG
35948: 01/10/24: Mike: Re: comp.arch.fpg : Reconfiguring of a virtex via JTAG
35910: 01/10/23: Jan Pech: New Spartan-II Evaluation Board
35913: 01/10/23: Dave Brown: Bidirectional port is converted to input during synthesis
35915: 01/10/23: Dave Brown: Re: Bidirectional port is converted to input during synthesis
35929: 01/10/24: Nicolas Matringe: Re: Bidirectional port is converted to input during synthesis
35937: 01/10/24: Dave Brown: Re: Bidirectional port is converted to input during synthesis
35933: 01/10/24: Jens Hildebrandt: Re: Bidirectional port is converted to input during synthesis
35938: 01/10/24: Dave Brown: Re: Bidirectional port is converted to input during synthesis
35940: 01/10/24: Andy Peters: Re: Bidirectional port is converted to input during synthesis
35916: 01/10/23: Peter: P5Z22V10 - any left anywhere?
36091: 01/10/29: <Iwo.mergler@soton.sc.philips.com>: Re: P5Z22V10 - any left anywhere?
36095: 01/10/29: Peter Alfke: Re: P5Z22V10 - any left anywhere?
35918: 01/10/23: rk: High-speed Logic, Military/Space Grade
35946: 01/10/24: Rene Tschaggelar: Re: High-speed Logic, Military/Space Grade
35950: 01/10/24: Daniel Lang: Re: High-speed Logic, Military/Space Grade
35921: 01/10/24: <khtsoi@pc90026.cse.cuhk.edu.hk>: RLOC under VHDL
35924: 01/10/24: Ray Andraka: Re: RLOC under VHDL
35923: 01/10/24: Dean Armstrong: JTAG question
35947: 01/10/24: Mike: Re: JTAG question
35951: 01/10/25: Dean Armstrong: Re: JTAG question
35999: 01/10/25: Mike: Re: JTAG question
35928: 01/10/24: Robert Staven: S/PDIF interface for FPGA
35942: 01/10/24: Andy Peters: Re: S/PDIF interface for FPGA
35953: 01/10/24: Eric Smith: Re: S/PDIF interface for FPGA
35954: 01/10/25: Allan Herriman: Re: S/PDIF interface for FPGA
35958: 01/10/25: Robert Staven: Re: S/PDIF interface for FPGA
35983: 01/10/25: Falk Brunner: Re: S/PDIF interface for FPGA
35989: 01/10/25: Andy Peters: Re: S/PDIF interface for FPGA
36000: 01/10/25: Eric Smith: Re: S/PDIF interface for FPGA
36015: 01/10/26: Allan Herriman: Re: S/PDIF interface for FPGA
36019: 01/10/26: Robert Staven: Re: S/PDIF interface for FPGA
36030: 01/10/26: Falk Brunner: Re: S/PDIF interface for FPGA
36033: 01/10/26: Ray Andraka: Re: S/PDIF interface for FPGA
36037: 01/10/26: Falk Brunner: Re: S/PDIF interface for FPGA
36050: 01/10/27: Georg Acher: Re: S/PDIF interface for FPGA
36244: 01/11/03: Robert Staven: OT: Re: S/PDIF interface for FPGA
36246: 01/11/03: Falk Brunner: Re: Re: S/PDIF interface for FPGA
35936: 01/10/24: phil: handel-C
35965: 01/10/25: Noel Klonsky: Re: handel-C
35949: 01/10/24: Dave Brown: SpartanXL Device Utilization Summary
35972: 01/10/25: Patrick Hibbs: Re: SpartanXL Device Utilization Summary
35979: 01/10/25: Dave Brown: Re: SpartanXL Device Utilization Summary
35993: 01/10/25: Patrick Hibbs: Re: SpartanXL Device Utilization Summary
35955: 01/10/25: Àü¼º¸ð: What's the JBits ?
35981: 01/10/25: Noel Klonsky: Re: What's the JBits ?
35956: 01/10/24: Assaf Sarfati: CPLD with built-in oscillator?
35957: 01/10/25: Jim Granville: Re: CPLD with built-in oscillator?
35985: 01/10/25: Leon Heller: Re: CPLD with built-in oscillator?
35959: 01/10/25: Noddy: Recommend a book
35962: 01/10/25: Srinivasan Venkataramanan: Re: Recommend a book
35973: 01/10/25: Ray Andraka: Re: Recommend a book
35976: 01/10/25: Srinivasan Venkataramanan: Re: Recommend a book
35974: 01/10/25: Patrick Hibbs: Re: Recommend a book
36014: 01/10/26: #BASUKI ENDAH PRIYANTO#: Re: Recommend a book
35960: 01/10/25: Jerre: How to make an implementable big counter?
35961: 01/10/25: Andrew MacCormack: Re: How to make an implementable big counter?
35963: 01/10/25: fred: Re: How to make an implementable big counter?
35964: 01/10/25: fred: Re: How to make an implementable big counter?
35966: 01/10/25: Rene Tschaggelar: Re: How to make an implementable big counter?
35977: 01/10/25: Ray Andraka: Re: How to make an implementable big counter?
35982: 01/10/25: Theron Hicks: Re: How to make an implementable big counter?
35997: 01/10/25: Ray Andraka: Re: How to make an implementable big counter?
36027: 01/10/26: <Graham>: Re: How to make an implementable big counter?
36028: 01/10/26: Ray Andraka: Re: How to make an implementable big counter?
36035: 01/10/26: John_H: Re: How to make an implementable big counter?
36041: 01/10/26: glen herrmannsfeldt: Re: How to make an implementable big counter?
36051: 01/10/27: Ray Andraka: Re: How to make an implementable big counter?
36053: 01/10/27: Tom St Denis: Re: How to make an implementable big counter?
36054: 01/10/27: Tom St Denis: Re: How to make an implementable big counter?
36068: 01/10/27: glen herrmannsfeldt: Re: How to make an implementable big counter?
36070: 01/10/27: Ray Andraka: Re: How to make an implementable big counter?
36073: 01/10/28: Peter Alfke: Re: How to make an implementable big counter?
36077: 01/10/28: Ray Andraka: Re: How to make an implementable big counter?
36906: 01/11/24: Richard Erlacher: Re: How to make an implementable big counter?
36907: 01/11/24: Hal Murray: Re: How to make an implementable big counter?
36908: 01/11/24: Theron Hicks (Terry): Re: How to make an implementable big counter?
36910: 01/11/25: Peter Alfke: Re: How to make an implementable big counter?
36925: 01/11/26: Richard Erlacher: Re: How to make an implementable big counter?
36927: 01/11/26: Peter Alfke: Re: How to make an implementable big counter?
37846: 01/12/21: Carl Brannen: Re: How to make an implementable big counter?
37853: 01/12/21: Ian Smith: Re: How to make an implementable big counter?
37861: 01/12/21: Peter Alfke: Re: How to make an implementable big counter?
37860: 01/12/21: Peter Alfke: Re: How to make an implementable big counter?
35969: 01/10/25: Utku Ozcan: SpartanXL: DOUT or GCK6?
35992: 01/10/25: Philip Freidin: Re: SpartanXL: DOUT or GCK6?
35970: 01/10/25: <hamish@cloud.net.au>: transferring data between related clocks
35975: 01/10/25: Patrick Hibbs: Re: transferring data between related clocks
36075: 01/10/28: <hamish@cloud.net.au>: Re: transferring data between related clocks
35978: 01/10/25: Ray Andraka: Re: transferring data between related clocks
36007: 01/10/26: Hamish Moffatt: Re: transferring data between related clocks
35994: 01/10/25: Peter Alfke: Re: transferring data between related clocks
35995: 01/10/25: Austin Lesea: Re: transferring data between related clocks
36013: 01/10/26: Allan Herriman: Re: transferring data between related clocks
35980: 01/10/25: srinas: 2/3 trellis code in vhdl
35986: 01/10/25: Patrick Hibbs: Re: 2/3 trellis code in vhdl
36005: 01/10/25: Bob Cain: Re: 2/3 trellis code in vhdl
35987: 01/10/25: Peter Heitzer: Cheap programming of XC2018?
35998: 01/10/25: Ray Andraka: Re: Cheap programming of XC2018?
36017: 01/10/26: Peter Heitzer: Re: Cheap programming of XC2018?
36221: 01/11/02: Richard Erlacher: Re: Cheap programming of XC2018?
35988: 01/10/25: Gunther May: GAL compiler
35990: 01/10/25: Peter Heitzer: Re: GAL compiler
35996: 01/10/25: Bertram Geiger: Re: GAL compiler
36001: 01/10/26: Jim Granville: Re: GAL compiler
36222: 01/11/02: Richard Erlacher: Re: GAL compiler
36002: 01/10/26: Jim Granville: Re: GAL compiler
36820: 01/11/21: Tim Forcer: Re: GAL compiler
36003: 01/10/25: Don Stauffer: Probing BGA Designs
36020: 01/10/26: Ben Popoola: Re: Probing BGA Designs
36021: 01/10/26: Ben Popoola: Re: Probing BGA Designs
36049: 01/10/26: AME: Re: Probing BGA Designs
36106: 01/10/30: Erik Lins: Re: Probing BGA Designs
36032: 01/10/26: Mike Treseler: Re: Probing BGA Designs
36544: 01/11/12: Emil Blaschek: Re: Probing BGA Designs
36004: 01/10/25: Philip Freidin: FCCM02 Call for Papers
36008: 01/10/25: Dave Millman: DSP on FPGA Opinions Needed->Earn $100
36010: 01/10/26: Ray Andraka: Re: DSP on FPGA Opinions Needed->Earn $100
36044: 01/10/26: Dave Millman: Re: DSP on FPGA Opinions Needed->Earn $100
36061: 01/10/27: --: Re: DSP on FPGA Opinions Needed->Those are good questions.
36064: 01/10/27: Ray Andraka: Re: DSP on FPGA Opinions Needed->Those are good questions.
36009: 01/10/25: David Rogoff: Xilinx XST vs FPGA Express?
36016: 01/10/26: Tobias Stumber: Re: Xilinx XST vs FPGA Express?
36025: 01/10/26: Austin Lesea: Re: Xilinx XST vs FPGA Express?
36012: 01/10/26: ggang1: Using xsvf file configures Xilinx FPGA
36018: 01/10/26: Simon Leung: WinXP Pro and Xilinx Foundation 3.3.8
36022: 01/10/26: William L Hunter Jr: ILA CHIPSCOPE
36023: 01/10/26: V R: Foundation 3.1I+SP8 vs 4.1ISE
36024: 01/10/26: olivier JEAN: Problem with IOBUF in WEBPACK 4.1
36029: 01/10/26: R.Sriram: Bi directional pin
36034: 01/10/26: C.Schlehaus: Re: Bi directional pin
36036: 01/10/26: Mike Treseler: Re: Bi directional pin
36039: 01/10/26: Kevin Brace: Cloning someone else's IP core
36040: 01/10/26: Ulf Samuelsson: Re: Cloning someone else's IP core
36045: 01/10/27: Kolja Sulimma: Re: Cloning someone else's IP core
36055: 01/10/26: Eric Smith: Re: Cloning someone else's IP core
36042: 01/10/26: Mike Treseler: Re: Cloning someone else's IP core
36200: 01/11/01: Kevin Neilson: Re: Cloning someone else's IP core
36043: 01/10/26: Eric Smith: Re: Cloning someone else's IP core
36067: 01/10/27: Kevin Brace: Re: Cloning someone else's IP core
36069: 01/10/27: glen herrmannsfeldt: Re: Cloning someone else's IP core
36083: 01/10/28: Kolja Sulimma: Re: Cloning someone else's IP core
36086: 01/10/28: Eric Crabill: Re: Cloning someone else's IP core
36146: 01/10/31: Kolja Sulimma: Re: Cloning someone else's IP core
36166: 01/10/31: Eric Crabill: Re: Cloning someone else's IP core
36179: 01/10/31: Kevin Brace: Re: Cloning someone else's IP core
36097: 01/10/29: Eric Smith: Re: Cloning someone else's IP core
36145: 01/10/31: Kolja Sulimma: Re: Cloning someone else's IP core
36100: 01/10/29: Leon Heller: Re: Cloning someone else's IP core
36103: 01/10/29: Kevin Brace: Re: Cloning someone else's IP core
36147: 01/10/31: Kolja Sulimma: Re: Cloning someone else's IP core
36178: 01/10/31: Kevin Brace: Re: Cloning someone else's IP core
36215: 01/11/02: Kolja Sulimma: Re: Cloning someone else's IP core
36176: 01/10/31: Kevin Brace: Re: Cloning someone else's IP core
36046: 01/10/26: Abhijeet: Synplicity Ver. 7.0 Mapper Error
36057: 01/10/27: hitajian: Confusion of Macro!
36060: 01/10/27: Arthur Sharp: Distributed ROM init
36062: 01/10/27: DaveG: Digital image input for simulation on Altera FPGA
36063: 01/10/27: Ray Andraka: Re: Digital image input for simulation on Altera FPGA
36088: 01/10/29: Martin Thompson: Re: Digital image input for simulation on Altera FPGA
36065: 01/10/28: #BASUKI ENDAH PRIYANTO#: Virtex 2 or E Evaluation Board
36078: 01/10/27: Matt Bielstein: Re: Virtex 2 or E Evaluation Board
36185: 01/11/01: John Adair: Re: Virtex 2 or E Evaluation Board
36099: 01/10/29: Andreas Kugel: Re: Virtex 2 or E Evaluation Board
36071: 01/10/27: finish: FIR >14 taps
36076: 01/10/28: Ray Andraka: Re: FIR >14 taps
36072: 01/10/27: Dereck: Jbits 2.0.1: BoardScope
36079: 01/10/28: Antonio D'Ottavio: Coefficient storing in VHDL
36087: 01/10/28: Antonio: Re: Coefficient storing in VHDL
36081: 01/10/28: finish: automation caused exception
36085: 01/10/28: Johann Glaser: University project: DSO
36096: 01/10/29: Manfred Kraus: Re: University project: DSO
36104: 01/10/30: Eugene Sablin: Re: University project: DSO
36089: 01/10/29: Thomas Bornhaupt: Jam Player and MAX+plus II
36093: 01/10/29: Thomas Bornhaupt: Re: Jam Player and MAX+plus II
36090: 01/10/29: Dave Vanden Bout: New WebPACK 4.1 tutorials
36092: 01/10/29: Ben Franchuk: OT - prototyping in Canada
36102: 01/10/30: Peter Alfke: Re: How can I design a bi-deriction bus buffer?
36113: 01/10/30: Ben Franchuk: Re: How can I design a bi-deriction bus buffer?
36135: 01/10/30: deerlux: Re: How can I design a bi-deriction bus buffer?
36105: 01/10/30: William Lenihan: Guided Design, Xilinx Virtex-E
36124: 01/10/30: Petter Gustad: Re: Guided Design, Xilinx Virtex-E
36133: 01/10/31: Kevin Neilson: Re: Guided Design, Xilinx Virtex-E
36228: 01/11/02: chris: Re: Guided Design, Xilinx Virtex-E
36230: 01/11/02: Ray Andraka: Re: Guided Design, Xilinx Virtex-E
36319: 01/11/06: William Lenihan: Re: Guided Design, Xilinx Virtex-E
36321: 01/11/06: Rick Filipkiewicz: Re: Guided Design, Xilinx Virtex-E
36107: 01/10/30: Russell Shaw: Leonardo bugs
36108: 01/10/30: Russell Shaw: Re: Leonardo bugs
36109: 01/10/30: django625: Shift Registers with Xilinx Foundation 2.1
36120: 01/10/30: Falk Brunner: Re: Shift Registers with Xilinx Foundation 2.1
36134: 01/10/31: Philip Freidin: Re: Shift Registers with Xilinx Foundation 2.1
36110: 01/10/30: VR: Device support Foundation 3.1i SP8
36131: 01/10/30: Kamal Patel: Re: Device support Foundation 3.1i SP8
36111: 01/10/30: Steffen Thieringer: Autostart Problem SPROM->FPGA
36116: 01/10/30: Nicolas Matringe: Re: Autostart Problem SPROM->FPGA
36121: 01/10/30: jakab tanko: Re: Autostart Problem SPROM->FPGA
36122: 01/10/30: Alan Nishioka: Re: Autostart Problem SPROM->FPGA
36115: 01/10/30: Nandini: timing difference
36118: 01/10/30: Mike Treseler: Re: timing difference
36167: 01/10/31: Norman Yang: Re: timing difference
36119: 01/10/30: Peter Alfke: Re: How can I design a bi-deriction bus buffer?
36123: 01/10/30: deerlux: How can I design a bi-deriction bus buffer?
36125: 01/10/30: David: Can anyone guide me in selecting an FPGA?
36126: 01/10/30: Mike Treseler: Re: Can anyone guide me in selecting an FPGA?
36132: 01/10/31: Philip Freidin: Re: Can anyone guide me in selecting an FPGA?
36308: 01/11/06: Peter Ormsby: Re: Can anyone guide me in selecting an FPGA?
36314: 01/11/06: Ray Andraka: Re: Can anyone guide me in selecting an FPGA?
36153: 01/10/31: Erik Lins: Re: Can anyone guide me in selecting an FPGA?
36159: 01/10/31: Wenyi_Feng: Re: Can anyone guide me in selecting an FPGA?
36154: 01/10/31: Peter Ormsby: Re: Can anyone guide me in selecting an FPGA?
36199: 01/11/01: Peter Alfke: Re: Can anyone guide me in selecting an FPGA?
36127: 01/10/31: Russell Shaw: Re: Leonardo bugs
36130: 01/10/30: Mike Treseler: Re: Leonardo bugs
36137: 01/10/31: Russell Shaw: Re: Leonardo bugs
36160: 01/10/31: Don Husby: Re: Leonardo bugs
36268: 01/11/04: Brian Drummond: Re: Leonardo bugs
36169: 01/10/31: David Meigs: Re: Leonardo bugs
36171: 01/11/01: Rick Filipkiewicz: Re: Leonardo bugs
36174: 01/11/01: Russell Shaw: Re: Leonardo bugs
36175: 01/11/01: Ray Andraka: Re: Leonardo bugs
36182: 01/11/01: Rick Filipkiewicz: Re: Leonardo bugs
36128: 01/10/30: Irwin Kennedy: Field Programmable Logic in energy poor environments
36138: 01/10/31: Peter Alfke: Re: Field Programmable Logic in energy poor environments
36144: 01/10/31: Kolja Sulimma: Re: Field Programmable Logic in energy poor environments
36163: 01/10/31: Peter Alfke: Re: Field Programmable Logic in energy poor environments
36216: 01/11/02: Kolja Sulimma: Re: Field Programmable Logic in energy poor environments
36155: 01/10/31: Tim: Re: Field Programmable Logic in energy poor environments
36264: 01/11/04: Kolja Sulimma: Re: Field Programmable Logic in energy poor environments
36129: 01/10/31: Jae-cheol Lee: what about FPGA with embedded processor?
36237: 01/11/02: Steven K. Knapp: Re: what about FPGA with embedded processor?
36250: 01/11/03: Peter Ormsby: Re: what about FPGA with embedded processor?
36139: 01/10/30: Chua Kah Hean: BRAM usage reduction in FIFO design: First Scenario
36149: 01/10/31: Falk Brunner: Re: BRAM usage reduction in FIFO design: First Scenario
36172: 01/10/31: Chua Kah Hean: Re: BRAM usage reduction in FIFO design: First Scenario
36188: 01/11/01: Falk Brunner: Re: BRAM usage reduction in FIFO design: First Scenario
36243: 01/11/03: Chua Kah Hean: Re: BRAM usage reduction in FIFO design: First Scenario
36140: 01/10/30: Chua Kah Hean: Second Scenario: BRAM usage reduction in FIFO design
36150: 01/10/31: Falk Brunner: Re: Second Scenario: BRAM usage reduction in FIFO design
36161: 01/10/31: Ray Andraka: Re: Second Scenario: BRAM usage reduction in FIFO design
36173: 01/10/31: Chua Kah Hean: Re: Second Scenario: BRAM usage reduction in FIFO design
36192: 01/11/01: Peter Alfke: Re: Second Scenario: BRAM usage reduction in FIFO design
36193: 01/11/01: Peter Alfke: Re: Second Scenario: BRAM usage reduction in FIFO design
36141: 01/10/31: Phillip: Re: Clock attribute problem
36273: 01/11/04: Banana: Re: Clock attribute problem
36142: 01/10/30: Banana: Clock attribute problem
36151: 01/10/31: Falk Brunner: Re: Clock attribute problem
36143: 01/10/31: Utku Ozcan: one SPROM for 2 XCS30XLs?
36162: 01/10/31: Ray Andraka: Re: one SPROM for 2 XCS30XLs?
36164: 01/10/31: Peter Alfke: Re: one SPROM for 2 XCS30XLs?
36148: 01/10/31: Richard Meester: searchin for High density non bga packages something like PGA.
36177: 01/11/01: Kevin Neilson: Re: searchin for High density non bga packages something like PGA.
36630: 01/11/13: Alex Rast: Re: searchin for High density non bga packages something like PGA.
36156: 01/10/31: mbonnici: Hard macro in xilinx
36203: 01/11/01: Bryan: Re: Hard macro in xilinx
36158: 01/10/31: fre: Implementing Filter
36209: 01/11/02: <vt313@comsys.ntu-kpi.kiev.ua>: Re: Implementing Filter
36214: 01/11/02: Ken: Re: Implementing Filter
36285: 01/11/05: Ray Andraka: Re: Implementing Filter
36218: 01/11/02: Matthias: Re: Implementing Filter
36165: 01/10/31: Dany XP: Synthesis of picoJava II for FSOC
36168: 01/10/31: Dave Brown: Xilinx CLB Pack Factor Percentage setting?
36170: 01/10/31: Christofire: Hardware Software Partitioning help required.
36180: 01/10/31: Kevin Brace: LeonardoSpectrum-Altera stability
36186: 01/11/01: Andrzej Ekiert: Re: LeonardoSpectrum-Altera stability
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