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Authors (J)
95486158j:
6507: 97/05/30: Re: Cheap way to develop for FPGAs?
j:
27511: 00/11/26: Fifo design problem
27639: 00/11/30: Re: Orca 3t sram gsr question
53490: 03/03/14: Re: RESET --- Synchronous Vs Asynchronous
J Adams:
3916: 96/08/19: SAMS Needs Your Electronics URLs
J buytaert:
90181: 05/10/06: ACTEL ProASIC plus mixed-voltage I/O macro's in Designer 6.2 ....?
90190: 05/10/06: Re: ACTEL ProASIC plus mixed-voltage I/O macro's in Designer 6.2 ....?
J Kenens:
40030: 02/02/25: Virtex-E,Spartan2 and cpld jtag chain problem
40095: 02/02/27: Re: Virtex-E,Spartan2 and cpld jtag chain problem
J Klukan:
10719: 98/06/12: Free Computer (Read--Easy, No money down)
J Mills:
15923: 99/04/21: Asynchronous Logic in Altera 10K devices
j n:
32203: 01/06/19: Re: Re: Flexlm license and windows 2000
J o h n _ E a t o n (at) hp . com (no spaces):
80236: 05/03/02: Re: Need suggestion abt FFs without RST for pipelined datapath.
99361: 06/03/23: Re: OpenSPARC released
99375: 06/03/23: Re: OpenSPARC released
99641: 06/03/27: Re: OpenSPARC released
99811: 06/03/29: Re: OpenSPARC released
99823: 06/03/29: Re: OpenSPARC released
100096: 06/04/03: Re: OpenSPARC released
105471: 06/07/24: Re: Hardware book like "Code Complete"?
J R:
50464: 02/12/11: Urgent : Need help with VHDL modeling on Cypress's Warp 5.2
J Silverman:
98926: 06/03/17: Support software for XC3042
98958: 06/03/17: Re: Support software for XC3042
98960: 06/03/17: Re: Support software for XC3042
99042: 06/03/19: Re: Support software for XC3042
J Thomas:
108084: 06/09/05: Re: Forth-CPU design
108148: 06/09/06: Re: Forth-CPU design
108161: 06/09/06: Re: Forth-CPU design
108165: 06/09/06: Re: Forth-CPU design
j zhang:
41559: 02/04/01: pricing and gate count info
J&P Lezcano:
16195: 99/05/08: SE VENDE FINCA EN MADRID
J-Wing:
59289: 03/08/13: Memory map in Altera NIOS
59420: 03/08/18: determine clock cycles (wait states) in interface to user logic in NIOS.
59435: 03/08/19: User logic to NIOS processor with bigger data width
60198: 03/09/07: system simulation and verification methods (NIOS)
60309: 03/09/10: simulating memory models in sopc builder
63734: 03/12/02: increase NIOS processor clock speed on APEX20K200E device
64366: 03/12/30: dynamic memory allocation NIOS
j.:
150066: 10/12/09: Interfacing DS92LV1021 with FPGA serdes
150079: 10/12/10: Re: Interfacing DS92LV1021 with FPGA serdes
J. A. Herrera Camacho:
3782: 96/07/31: Multi-FPGA Partitioners?
J. Boss:
22404: 00/05/08: Programming FPGA
22460: 00/05/09: Re: Programming FPGA
22617: 00/05/14: Bidirectional BUS!!!
J. Jansen:
7657: 97/10/01: Re: vme vs compact pci
J. Khatib:
8162: 97/11/22: FPAA Motorola's new tech.
9185: 98/02/28: Dsp Fpga and vhdl project
9521: 98/03/20: Dual port
9577: 98/03/24: Best solution
11201: 98/07/24: CPLD vs. FPGA
12319: 98/10/08: FPGA core design
14787: 99/02/17: Free circuit design
15008: 99/03/03: Selt-Timed circuit
15638: 99/04/05: Re: HELP NEEDED: FPGA and Neural Networks
15738: 99/04/11: Re: Does any one want to talk about Dynamic Configuration?
15772: 99/04/13: bitstream
15788: 99/04/14: SUBSCRIBE
16202: 99/05/10: Bitstream size
16203: 99/05/10: Re: FPGA, PLD, EPLD, CPLD differences
16338: 99/05/17: Dual Port mem
J. Mark Wolf:
9057: 98/02/17: Trade device programmer for 8051 C compiler
9087: 98/02/18: Will trade device programmer for 8051 C compiler
J. Mejia:
7098: 97/07/31: Re: Quick prototyping? Best solution?
7109: 97/08/01: Re: Where is Actel's www?
J. Michael Milner:
53195: 03/03/05: Re: Issues in Outsourcing?
65540: 04/02/01: Re: Differences between Xilinx ISE and Altera Quartus software
J. Reed Walker:
36234: 01/11/02: JTAG problem
J. Scott Dickson:
3618: 96/07/03: Re: FSM encoding in VHDL with MAX+plusII
3671: 96/07/10: Re: FPGA capacity comparison
J. Scott Fuller:
8222: 97/11/30: Re: what is metastability time of a flip_flop
j.bernspang:
109739: 06/10/04: Re: logarithm look-up table
J.Curtis:
47914: 02/10/07: String Matching Developments on FPGA's
<j.d.morrison@gmail.com>:
123724: 07/09/03: Re: An FPGA startup is seeking testcase from potential customers
123726: 07/09/03: Re: Die size, pitch size?
J.F. FOURCADIER:
64477: 04/01/05: Altera CPLD - Illegal assignment-global clock
J.G.:
52541: 03/02/12: FPGA for audio record and playback???
J.H.R. Schrader:
28817: 01/01/25: Field Programmable Gate Array selection and task suitability
J.Ho:
35196: 01/09/25: Virtex2 slice level instantiation in verilog question
35207: 01/09/25: Re: Virtex2 slice level instantiation in verilog question
40813: 02/03/15: [Virtex 2] DCM: "Factory_JF" option box in FPGA editor question
41007: 02/03/19: Re: [Virtex 2] DCM: "Factory_JF" option box in FPGA editor question
63860: 03/12/05: How to explicitly call out cell elements in Altera Stratix?
<j.kreyssig@fh-wolfenbuettel.de>:
9792: 98/04/05: installation altera maxplus2 8.2
J.L. Mitchell:
26099: 00/10/04: test
<j.m.granville@gmail.com>:
153628: 12/04/06: Re: Digital Tachometer VHDL
153746: 12/05/04: Re: FPGA and Package-on-Package
153748: 12/05/05: Re: Smallest GPL UART
153798: 12/05/23: Re: Smallest GPL UART
153801: 12/05/23: Re: Logic Glitches in Spartan-3?
153813: 12/05/24: Re: Logic Glitches in Spartan-3?
153846: 12/06/04: Re: Questions about LCMXO2280-B-EVN and LCMXO2-1200ZE-B-EVN ev kits
153906: 12/06/28: Re: Replacement for XC4005E
J.Mawer:
4387: 96/10/23: Re: VHDL for Xilinx designs?
5116: 97/01/24: Designing Xilinx with cadence
J.Niu:
27261: 00/11/16: test
27262: 00/11/16: Re: Basic question on PLD & FPGA
27263: 00/11/16: can FPGA perform float point calculaton?
27264: 00/11/16: Can FPGA perform float point calculation?
J.Oscar:
59629: 03/08/25: Esquematic with XC2S100
J.P.Liao:
15079: 99/03/05: Can multiple FPGA share same SPROM for configuration?
J.R.:
19356: 99/12/15: Speed grade
19528: 99/12/29: An online division unit with constant divisor
19874: 00/01/15: EARN MONEY EASILY-READ THIS!!
20562: 00/02/14: Is EDIF format adopted by all FPGA manufacturers???
20732: 00/02/19: Re: BEHAVIOURAL VHDL
20801: 00/02/23: Help!!!
20811: 00/02/23: Re: Help!!!
21517: 00/03/24: ERROR:NgdHelpers:312
21802: 00/04/01: FPGA price vs Size
J.Ram:
119473: 07/05/21: Timing not met but working on board
119576: 07/05/22: Design running on board but timing are not met
120662: 07/06/13: programming virtex2 FPGA
120701: 07/06/13: Re: programming virtex2 FPGA
136682: 08/11/30: simulation results is correct but synthesis result is not correct
136701: 08/12/02: Re: simulation results is correct but synthesis result is not correct
138093: 09/02/06: clock generation by divide and reset
J.Simmons:
10683: 98/06/10: Re: XILINX Foundation - how to minimize project archive?
10684: 98/06/10: Re: Atmel AT40K
10685: 98/06/10: Re: Xilinx Foundation
J.W. Holloway:
72807: 04/09/02: StateCad, IO vector question.
J.W. Krych:
22711: 00/05/18: FPGA emultaion of a microprocessor
J.Walliker:
1995: 95/09/29: Altera EPX880QC132-10 Availability?
3083: 96/03/28: Re: Low-power FPGA or EPLD
3329: 96/05/14: Re: Looking for free FPGA softw./Xilinx
J.Wild:
124058: 07/09/11: application about hardeware attributes
125091: 07/10/16: Re: application about hardeware attributes
j93005:
103506: 06/06/05: How to use usb on Alter EPXA4??
J?rgen:
66584: 04/02/23: Usage of Xilinx Library elements in ModelSim simulation
66963: 04/03/02: Re: Usage of Xilinx Library elements in ModelSim simulation
67648: 04/03/16: Modelsim & ISE Foundation: Hierarchical update
69344: 04/05/07: Error while simulation with XILINX DCM
69386: 04/05/10: Re: Error while simulation with XILINX DCM
69389: 04/05/10: Re: Error while simulation with XILINX DCM
JA:
12198: 98/10/04: Re: Which FPGA tool is better
16786: 99/06/08: Re: Altera EPC1 PROM + Data IO ChipWriter
Jaakko Varteva:
88606: 05/08/23: Re: Good SystemC tutorials or books?
Jaan Sirp:
28233: 01/01/03: Re: FFs in IOBs in XC4000
28258: 01/01/04: Re: Serial interface (urgent)
28301: 01/01/05: Re: Spartan-II DLL Usage
28359: 01/01/10: Re: grey code counters
28389: 01/01/11: Re: grey code counters
28390: 01/01/11: Re: grey code counters
28744: 01/01/23: Re: VirtexII and high speed counter
28967: 01/01/31: Re: XILINX FPGA programming through JTAG
29149: 01/02/08: Re: JTAG debugging?
29441: 01/02/21: Re: Infering DPRAM with both outputs
29713: 01/03/06: Re: Suggestions for I/O card
29717: 01/03/06: Re: Suggestions for I/O card
29836: 01/03/13: Re: sample code for JTAG configuration of Virtex, Spartan II?
29889: 01/03/15: Re: Low volume users (was: Re: VirtexE LVPECL I/O Ports? experience?)
29890: 01/03/15: Re: Programming CPLD and FPGA on XESS board for Ethernet.
31170: 01/05/14: Bug in Xilinx Hardware Debugger?
31175: 01/05/14: Re: Bug in Xilinx Hardware Debugger?
68209: 04/03/30: Virtex2 partial reconfiguration
68216: 04/03/30: Re: maybe a stupid question
Jaap H. Mol:
14185: 99/01/18: Re: Programmng ALTERA EPROMS
18775: 99/11/14: Altera NOT-gate push back
23963: 00/07/18: Re: Quartus
25369: 00/09/08: IEEE 754 Floating point VHDL functions / MATH package
38949: 02/01/28: QuartusII Timing Analysis
Jaap Mol:
5740: 97/03/11: Re: ACTEL RAM BASED FPGAs
6026: 97/04/06: Re: clock edge specification for Synopsys synthesis
7321: 97/08/26: Re: MaxPlusII from Altera.
52122: 03/02/01: Re: How to do on-the-fly reconfiguration of a Flex10ke using an EPC16?
55822: 03/05/20: Ethernet MAC IP-core in Nios design
56694: 03/06/11: Re: Virtex 2 evaluation board
56695: 03/06/11: Re: about the uclinux in Altera Nios
56698: 03/06/11: Re: Constant on Multiplier Synthesis problem with XST for VirteX 2/E
56701: 03/06/11: Re: Which Init Technique for BlockRAMs and Modelsim?
56726: 03/06/12: Re: Post P&R Verilog/VHDL netlist
Jabari Zakiya:
66393: 04/02/18: Re: Dual-stack (Forth) processors
66433: 04/02/19: Re: Dual-stack (Forth) processors
Jabberwork:
18033: 99/09/24: Re: Modelsim,synplify,Leonardo,MAX+plus, you name it!!
Jac Athow:
75823: 04/11/16: Extending chipscope capture memory by using external async SRAM
Jacek Mocki:
68931: 04/04/22: Re: Document State Machines?
68968: 04/04/23: transport applications
69141: 04/04/28: Re: transport applications
69142: 04/04/28: Re: transport applications
Jacek Wawrzaszek:
70923: 04/07/01: Re: Compact FPGA Board?
103634: 06/06/07: Re: API on Virtex 4 FPGA or the email of Delon Levi wanted
Jack:
32774: 01/07/08: Offer: Extra Xilinx PCI development kit (HOT 2)
35799: 01/10/18: Career advice in fpga/asic design
47314: 02/09/23: Re: Altera Cyclone low-cost FPGA chips?
47423: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
49707: 02/11/19: how to use carry chain in Virtexe
49761: 02/11/20: Re: how to use carry chain in Virtexe
57340: 03/06/27: projects for beginners
64701: 04/01/11: Altera NIOS cyclone edition development board problem
64839: 04/01/14: Re: Altera NIOS cyclone edition development board problem
67983: 04/03/23: study verilog or vhdl?
69929: 04/05/25: VPR & Reconfigurable system ?
75989: 04/11/21: Re: FPGA development board
78653: 05/02/04: memory size of C code
78704: 05/02/06: warning messages,NgdBuild:454,DesignRules:331
78772: 05/02/07: Re: warning messages,NgdBuild:454,DesignRules:331
78832: 05/02/08: BRAM utilization - how to calculate
79308: 05/02/17: thread programming support in EDK?
79375: 05/02/17: microblaze with opb, brams?
79377: 05/02/17: Re: thread programming support in EDK?
79455: 05/02/19: distributed shared memory in fpga?
84772: 05/05/26: V2pro configuration problem - PROM SIZE
87608: 05/07/26: how to measure number of cycles in ISE6.3
91135: 05/10/30: array type implementable in ISE?
132769: 08/06/06: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
144455: 09/12/08: FPGA kit
jack:
28518: 01/01/16: help
83807: 05/05/06: how can i join the comp.arch.fpga group
83809: 05/05/06: how can i add my math library libm.a in my project
150808: 11/02/14: Xilinx USB programming cable.
150852: 11/02/16: Re: Xilinx USB programming cable.
Jack Crenshaw:
31922: 01/06/08: Re: My80-- i8080A instruction compatible processor core
Jack D. Ma:
22000: 00/04/11: Is there any DSP and FPGA based board suitable to motor drive control?
Jack Daly:
102278: 06/05/13: Trouble understanding Synplicity timing report
102281: 06/05/13: Re: Trouble understanding Synplicity timing report
Jack Falk:
85858: 05/06/17: Atmel tools: any way to edit intra-cell connections in IDS/Figaro?
87153: 05/07/18: chips with partial reconfig other than atmel & xilinx?
87154: 05/07/18: "Tbufs don't exist"
Jack Greenbaum:
504: 94/12/12: Re: L-Edit and Benchmarks
1736: 95/08/21: Re: Design protection
2299: 95/11/17: Re: [Q] FPGA Software for Linux
2497: 95/12/18: Re: Floor Planning for Xilinx
7709: 97/10/06: Re: FPGA multiprocessors
16904: 99/06/16: Re: Evolutionary computation
Jack Huang:
8015: 97/11/07: Where can I find documents talking about constraining FPGA?
Jack Klein:
77186: 04/12/28: Re: Primers for Handel-C
94194: 06/01/06: Re: Programming Xilinx PowerPC
105834: 06/08/01: Re: Where are Huffman encoding applications?
111124: 06/10/29: Re: Hardware mapping of algorithms
132886: 08/06/09: Re: how to prevent timer code firmware running on Microblaze from being optimised
139784: 09/04/13: Re: Find FPGA updates On Twitter
Jack Lai:
8836: 98/01/30: Re: xilinx M1 protection
9038: 98/02/16: Re: the problem about counter.
9146: 98/02/24: Re: Correlation implementation...
24379: 00/08/05: Abel from dataIO?
jack lalo:
79488: 05/02/19: Help using the ML310 developement board
79654: 05/02/22: Is there any compatibility difference between The parallel JTAG PC4 and JTAG III??
jack lee:
114997: 07/01/29: virtex-II DCM phase shift problems
120145: 07/06/01: How to guarantee the same relative placement and routing in ISE?
Jack Leong:
149283: 10/10/13: Re: i don't have any idea to select write mode at ASMI_PARALLEL
153481: 12/03/08: Re: CPU Design in Xilinx Spartan 3E
153482: 12/03/08: Re: Error JTAG chain problem detected
153483: 12/03/08: Re: configuring an Altera Cyclone 3
153484: 12/03/08: Re: Using both Verilog and VHDL for Xilinx simulation
Jack Moderatz:
67252: 04/03/09: bit stream file examples ?
67316: 04/03/10: FPGA benchmark....and ..... some questions
Jack Mott:
1241: 95/05/21: Re: affordable fpga design tools?
Jack Nimble:
33549: 01/07/30: Help: Simple counter example in WebPack schamatic capture
41706: 02/04/05: Help: Design a crystal oscillator in a Xilinx XCR3256XL
Jack Ogawa:
766: 95/02/25: Re: Looking for Tech Info
866: 95/03/16: Re: FPGA multi-chip modules ?
3621: 96/07/04: RE: Sanity check for 100K gate DSP FPGA project
3656: 96/07/09: RE: Sanity check for 100K gate DSP FPGA project
Jack Sandell:
2361: 95/11/23: Re: Industry Trends
Jack Seredyniecki:
59265: 03/08/13: Re: Can i trace client activity?
Jack Smith:
57421: 03/06/30: advice
Jack Stone:
58524: 03/07/25: Relative placement constraints in VHDL for Virtex multipliers
59830: 03/08/28: Re: Moving Sum
59935: 03/09/01: Re: Moving Sum
Jack Tai:
34578: 01/08/29: Model sim vhdl simulation crash
35845: 01/10/19: memory dump for Xilinx block ram
37507: 01/12/12: Re: xilinx ise 4
Jack Zhu:
76173: 04/11/27: Q:iMPACK:583 - '1' error
Jack Zkcmbcyk:
108482: 06/09/11: Help for Altera Nios II Cyclone EP1C12 evaluation kit!
108519: 06/09/12: Re: Help for Altera Nios II Cyclone EP1C12 evaluation kit!
109112: 06/09/21: Verification errors using Xilinx Spartan 3E board
jack.gassett:
140369: 09/05/11: Re: Getting started with FPGA
140983: 09/06/01: Open Source FPGA circuit design.
141001: 09/06/02: Re: Open Source FPGA circuit design.
141520: 09/06/26: Using Xilinx tools with ft2232 based programming cable.
144253: 09/11/23: Goal to make $30-40 Open Source Logic Analyzer with Spartan 3E.
jack.harvard@googlemail.com:
128232: 08/01/18: Re: How is FIFO implemented in FPGA and ASIC?
128238: 08/01/18: Re: How is FIFO implemented in FPGA and ASIC?
128433: 08/01/25: Thoughts about memory controller problems
129398: 08/02/22: Re: Interview questions
129399: 08/02/22: Re: Interview questions
133072: 08/06/17: Xilinx Spartan FPGA BlockRAM in Simulation
133683: 08/07/09: Question: What are the tricks mentioned on Viterbi Decoder Wikipedia
134817: 08/09/02: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
134818: 08/09/02: Re: why does inferred RAM cause synthesis times to explode?
134820: 08/09/02: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
134836: 08/09/03: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
134841: 08/09/03: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
135287: 08/09/24: decimal to ieee 754 single precision floating point
135439: 08/10/02: floating point round off errors
135451: 08/10/02: Re: floating point round off errors
135475: 08/10/03: synopsys designware components on xilinx fpga
139570: 09/04/03: Xilinx Spartan3A XC3S700A die area?
<jack.pett.son@gmail.com>:
154334: 12/10/03: fft in fpga using polar form
154348: 12/10/11: fixed point fft butterfly stage testing help
Jack// ani:
75339: 04/11/02: FPGA/CPLD Basics
75363: 04/11/03: Re: FPGA/CPLD Basics
75386: 04/11/03: Re: FPGA/CPLD Basics
75952: 04/11/20: FPGA development board
75991: 04/11/22: Re: FPGA development board
76031: 04/11/22: Re: FPGA development board
76156: 04/11/26: Re: FPGA development board
JackBonn:
149104: 10/10/01: Microblaze, Xilkernel, and g++
JackC:
48239: 02/10/14: Power Cnsumption Benchmark
62171: 03/10/21: Structure of the Embedded Multiplier?
Jacke:
41030: 02/03/19: Fixed Point Library
41190: 02/03/22: SystemC compiler
<jackhab@gmail.com>:
104942: 06/07/10: PROM files: build .bin for daisy chain on the fly
104960: 06/07/10: Re: PROM files: build .bin for daisy chain on the fly
105275: 06/07/19: Virtex-4 PowerPC and Trace32 ICD - start up help wanted
Jackie Meyer:
4210: 96/09/27: CFP: Design and Test
4236: 96/10/03: CFP: Memory Technology Design and Testing
4557: 96/11/13: CFP Memory Workshop
4728: 96/12/06: Re: ASICs Vs. FPGA in Safety Critical Apps.
4929: 97/01/01: CFP Memory Technology Workshop
5000: 97/01/10: CFP Memory Technology Workshop
5389: 97/02/12: CFP Design and Test special issue
6038: 97/04/07: CFP: Design and Test, FPGA special issue
6174: 97/04/22: Memory workshop, San Jose, August 11-12
6181: 97/04/23: CFP Design and Test (FPGA issue)
6400: 97/05/21: memory workshop ram/rom/pld/fpga
6577: 97/06/03: Memory workshop, San Jose
7074: 97/07/29: Memory workshop
8965: 98/02/10: IEEE memory workshop
9093: 98/02/19: [CFP] San Jose workshop on MEMORY
10561: 98/05/29: ieee Memory workshop
10664: 98/06/09: papers wanted on DRAM
10983: 98/07/08: papers sought, DRAM
11262: 98/07/31: register for IEEE memory workshop
11482: 98/08/19: memory workshop starts Monday
jackm:
157736: 15/02/25: Program Xilinx with Altera JTAG Programmer?
157739: 15/02/25: Re: Program Xilinx with Altera JTAG Programmer?
157751: 15/03/01: Re: Program Xilinx with Altera JTAG Programmer?
jacko:
106532: 06/08/14: Re: Crystal input for FPGA
106587: 06/08/15: Re: Maximum Current Draw of FPGA
106588: 06/08/15: Re: Maximum Current Draw of FPGA
106833: 06/08/20: Re: CPU design
106839: 06/08/20: Re: CPU design
106876: 06/08/21: Re: CPU design
106880: 06/08/21: CPU design
106881: 06/08/21: hex format 16 bit?
106905: 06/08/22: Re: CPU design
106935: 06/08/22: hex and AHDL?
106936: 06/08/22: Re: Xilinx Virtual Platform
107047: 06/08/23: Re: CPU design
107134: 06/08/24: Re: JOP as SOPC component
107176: 06/08/25: Re: Why No Process Shrink On Prior FPGA Devices ?
107759: 06/08/31: Re: CPU design
108003: 06/09/03: Re: Forth-CPU design
108076: 06/09/04: Re: Forth-CPU design
108080: 06/09/05: Re: Forth-CPU design
108085: 06/09/05: Re: Forth-CPU design
108087: 06/09/05: Re: Forth-CPU design
108112: 06/09/05: LUT Blocks?
108351: 06/09/08: Re: Why No Process Shrink On Prior FPGA Devices ?
108360: 06/09/08: Re: ddr with multiple users
109432: 06/09/26: Re: PUBLISHABLE PAPER RELATED TO FPGA!
109439: 06/09/26: Re: PUBLISHABLE PAPER RELATED TO FPGA!
109440: 06/09/26: Re: uBlaze prototype PCB UART issues
109441: 06/09/26: BSD Indi FPGA processor seeks new webserver
109444: 06/09/26: Re: PERISHABLE PAPER RELATED TO FPGA!
109660: 06/10/02: Modules for IO on BSD indi processor ideas?
109670: 06/10/02: Re: Modules for IO on BSD indi processor ideas?
109681: 06/10/03: Re: Modules for IO on BSD indi processor ideas?
109699: 06/10/03: Re: Modules for IO on BSD indi processor ideas?
109792: 06/10/05: BSD indi processor IP compiles at 283 LEs
109800: 06/10/05: Re: Just a matter of time
109802: 06/10/05: Re: SMPTE310 interface
109819: 06/10/05: Re: BSD indi processor IP compiles at 386 LEs (MAX II)
109827: 06/10/05: Re: BSD indi processor IP compiles at ($13.30)
109829: 06/10/05: Re: BSD indi processor IP compiles at ($13.30)
109878: 06/10/06: Re: BSD indi processor IP compiles at ($13.30)
109884: 06/10/06: Re: BSD indi processor IP compiles at 283 LEs
109896: 06/10/07: Re: Just a matter of time
109898: 06/10/07: Re: BSD indi processor IP compiles at 283 LEs
109946: 06/10/08: Re: Antifuse, lower cost?
110041: 06/10/09: Re: BSD indi processor IP compiles at ($13.30)
110059: 06/10/10: Re: BSD indi CPLD processor IP 60MHz 12MIPS 330LEs
110083: 06/10/10: Re: BSD indi CPLD processor IP 60MHz 12MIPS 330LEs
110248: 06/10/12: Re: New Electronic Design Web site
110297: 06/10/13: Re: New Electronic Design Web site
110435: 06/10/15: echo $LM_LICENCE_FILE not working
110443: 06/10/15: Re: echo $LM_LICENCE_FILE not working
110478: 06/10/16: Re: echo $LM_LICENCE_FILE not working
110592: 06/10/18: Re: BSD indi CPLD processor IP 60MHz 12MIPS 330LEs
110622: 06/10/18: Re: Cheapest FPGA board to study VHDL on
111259: 06/10/31: Re: Question about bandwidth of scope?
112585: 06/11/25: Dev Kit Shipping Costs
113833: 06/12/23: max II dev kit pin grid
114297: 07/01/10: Santa Clara Connector and LVTTL etc
114299: 07/01/10: altera MAX II dev kit LCD mountings??
121685: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
134361: 08/08/07: Nibz processor @ 472 LEs (16 bit generic specified)
134454: 08/08/11: Re: Altera question - MAX3000 vs MAX7000
134494: 08/08/13: Re: Altera question - MAX3000 vs MAX7000
136209: 08/11/05: nibz processor new version
138799: 09/03/11: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
140126: 09/04/29: Quartus Timing
140667: 09/05/21: Nibz VHDL Processor (Version G-spot)
140708: 09/05/22: Re: Nibz VHDL Processor (Version G-spot)
140729: 09/05/22: 512*256 resolution on VGA (generic code available)
140849: 09/05/27: Nibz (Version P)
145765: 10/02/22: Re: Looking for Ultimate RISC/MISC that runs LINUX Website
145934: 10/02/28: Re: Frustration with Vendors!
145994: 10/03/02: Re: Tabula. (FPGA start up)
146422: 10/03/17: Re: Awkward Arithmetic
146423: 10/03/17: Re: Nested interrupts in Nios system and hung system
146526: 10/03/22: Re: Awkward Arithmetic
146807: 10/03/29: Re: Which is the most beautiful and memorable hardware structure in a
147084: 10/04/13: Re: Nios Memory Protection Unit
148370: 10/07/15: Re: 1-wire question
151461: 11/04/11: Altera web 10.1sp1
151515: 11/04/16: NibzX7 processor
151524: 11/04/17: Re: NibzX7 processor
151528: 11/04/17: Re: NibzX7 processor
151548: 11/04/18: Re: NibzX7 processor
151564: 11/04/19: Re: NibzX7 processor
151568: 11/04/20: Re: NibzX7 processor
151571: 11/04/20: Re: NibzX7 processor
151574: 11/04/20: Re: NibzX7 processor
151579: 11/04/21: Re: NibzX7 processor
Jacko:
106408: 06/08/12: dynamic fpga via bytecode sequence?
106409: 06/08/12: Re: Embedded clocks
138781: 09/03/10: Re: Integer arithmetic in HDLs
138804: 09/03/11: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138816: 09/03/11: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138817: 09/03/11: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138836: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138837: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138842: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138847: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138853: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138874: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138883: 09/03/13: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138884: 09/03/13: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138894: 09/03/13: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138912: 09/03/14: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138915: 09/03/14: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138925: 09/03/14: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138969: 09/03/17: Re: Zero operand CPUs
138984: 09/03/17: Re: Zero operand CPUs
138986: 09/03/17: Re: Zero operand CPUs
139001: 09/03/18: Re: Zero operand CPUs
139009: 09/03/18: Re: Zero operand CPUs
139022: 09/03/18: Re: Zero operand CPUs
139057: 09/03/19: Re: Zero operand CPUs
139063: 09/03/19: Re: Zero operand CPUs
139067: 09/03/19: Re: Zero operand CPUs
139074: 09/03/19: Re: Zero operand CPUs
139101: 09/03/20: Re: Zero operand CPUs
139106: 09/03/20: Re: Re Zero operand CPUs
139111: 09/03/20: Re: Re Zero operand CPUs
139128: 09/03/21: Re: Re Zero operand CPUs
139159: 09/03/22: Re: Re Zero operand CPUs
139179: 09/03/22: Re: Re Zero operand CPUs
139323: 09/03/26: Re: some nibz decoding ?
140135: 09/04/29: Re: Quartus Timing
140158: 09/04/30: Re: Quartus Timing
140342: 09/05/09: Re: Dual Port RAM Inference
140348: 09/05/10: Re: implementing arbitrary combinational functions using block rams
140466: 09/05/14: Re: cheapest FPGA?
140684: 09/05/21: Re: Nibz VHDL Processor (Version G-spot)
140688: 09/05/21: Re: Nibz VHDL Processor (Version G-spot)
140689: 09/05/21: Re: Nibz VHDL Processor (Version G-spot)
140726: 09/05/22: Re: Nibz VHDL Processor (Version G-spot)
140863: 09/05/27: Re: Nibz (Version P)
140865: 09/05/27: Re: Nibz (Version P)
140899: 09/05/28: Re: When is it to generate transparent latch or usual combinational
141173: 09/06/10: Re: async. SRAM control signal generation
<Jackolantern25@gmail.com>:
90301: 05/10/10: 16550 VHDL code
<jacks343@msn.com>:
11668: 98/08/29: Here is my page of DIRTY PICTURES
Jackson Pang:
71356: 04/07/15: Xilinx EDK PCI
71362: 04/07/15: RE: Xilinx Virtex-II Configuration in Slave Serial
71394: 04/07/16: Re: Xilinx EDK PCI
71652: 04/07/26: Re: Xilinx EDK PCI
71710: 04/07/28: Re: Xilinx EDK PCI
71711: 04/07/28: Re: Xilinx EDK PCI
71717: 04/07/28: Re: XUP Support
jacky:
120261: 07/06/04: modelsim
120292: 07/06/05: Re: modelsim
Jacky Renaux:
36659: 01/11/14: Re: interleaver delay question
40665: 02/03/12: Re: 32-taps FIR !
40971: 02/03/19: Re: simple Free FPGA tool
42467: 02/04/24: Re: INIT constrain
42545: 02/04/26: Re: Changing ROM contents
43566: 02/05/24: Re: FPGA and VHDL: question about RAM initialization
43567: 02/05/24: Re: FPGA and VHDL: question about RAM initialization
43800: 02/06/03: Re: Pipelining
44422: 02/06/19: barrel shifter
44465: 02/06/20: Re: barrel shifter
48280: 02/10/15: Re: AHDL Command Reference?
50823: 02/12/20: Re: 16-bit LFSR
52601: 03/02/15: end-around-carry
52810: 03/02/23: Re: end-around-carry
jacky Renaux:
37338: 01/12/07: Re: xilinx ise 4.1i
38107: 02/01/05: RNS
65089: 04/01/20: Re: Which version of ISE Webpack has FPGA Editor on it?
Jaco Naude:
121665: 07/07/11: Re: XilinxSystemGenerator and Simulink
121684: 07/07/11: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol
121686: 07/07/11: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol
121727: 07/07/12: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol
141057: 09/06/04: Xilinx FIR Compiler gives zero only output in hardware
141093: 09/06/04: Re: How to generate clocks of higher frequency?
141094: 09/06/04: Re: Xilinx FIR Compiler gives zero only output in hardware
153477: 12/03/07: Virtex 6 System Monitor sensor readings in ChipScope gives weird values
154179: 12/08/29: Cross-vendor firmware design management environment
jacob:
Jacob =?iso-8859-1?q?S=F8rensen?=:
65518: 04/01/31: Altera DSP builder problem with delay and Integrator
65627: 04/02/03: Re: Altera DSP builder problem with delay and Integrator
65677: 04/02/04: Re: Altera DSP builder problem with delay and Integrator
Jacob Bower:
76407: 04/12/01: EDIF -> Map & Place -> EDIF ?
76418: 04/12/01: Re: EDIF -> Map & Place -> EDIF ?
76437: 04/12/02: Re: EDIF -> Map & Place -> EDIF ?
76455: 04/12/02: Re: EDIF -> Map & Place -> EDIF ?
76456: 04/12/02: Re: EDIF -> Map & Place -> EDIF ?
76469: 04/12/03: Re: EDIF -> Map & Place -> EDIF ?
76482: 04/12/03: Re: EDIF -> Map & Place -> EDIF ?
76583: 04/12/06: FPGA as host for a USB peripheral
76613: 04/12/07: Re: FPGA as host for a USB peripheral
78517: 05/02/02: Modifying a post PAR xilinx design
78518: 05/02/02: Re: Modifying a post PAR xilinx design (solved)
Jacob Eluz:
16095: 99/05/03: Virtex
Jacob Schaffner:
129556: 08/02/27: Re: Xilinx's microblaze hangs when a timer interrupt occurs after a
Jacob Sparre Andersen:
87417: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
Jacob W Janovetz:
6677: 97/06/12: Power consumption (Xilinx FPGA) questions
6713: 97/06/18: Re: Help: Interfacing a Xilinx 4k to a microprocessor
6766: 97/06/25: Re: FPGA prototype board
7818: 97/10/18: Q: Clocking for address decode/chip select.
7862: 97/10/24: Xilinx 4000 on an ISA bus...
7992: 97/11/05: Re: Digital reverberator on FPGA
8007: 97/11/06: Re: I'm interested in FPGAs. How do I start ?
8082: 97/11/16: Re: I need Help
8224: 97/12/01: Xilinx .bit file format.
9186: 98/02/28: Re: Xilinx Info.
9147: 98/02/25: Leonardo/VHDL and pullups in FPGAs.
9187: 98/02/28: Re: The case for Linux and EDA
9218: 98/03/03: Debugging question.
9233: 98/03/03: Re: Debugging question.
9306: 98/03/06: Leonardo/Xilinx BUFGLS question
9307: 98/03/06: Re: Leonardo/Xilinx BUFGLS question
9422: 98/03/12: Re: SOS!! Big Urgent Problem
9498: 98/03/19: Re: Cypress ISR
9764: 98/04/03: Xilinx routing optimization?
9799: 98/04/06: Re: Xilinx routing optimization?
9820: 98/04/07: Re: Xilinx routing optimization?
9909: 98/04/13: Re: Xilinx routing optimization?
9950: 98/04/16: Xilinx RPMs for DSP (16-tap 8-bit FIR)
10100: 98/04/27: Re: FPGA pin assignment for I/O
10200: 98/05/03: Re: Xilinx Foundation and Linux
11289: 98/08/02: Re: how much ? prices of Xilinx chips
11301: 98/08/03: Re: [****] VHDL Compile Error ( +, & Operator )
13065: 98/11/14: Xilinx COREgen and Leonardo troubles...
13107: 98/11/16: Re: Xilinx COREgen and Leonardo troubles...
13276: 98/11/23: Xilinx XL vs XLA.
<jacob.bower@gmail.com>:
87500: 05/07/25: Re: verilog to blif(lut)
99191: 06/03/21: Ignoring hierachy while flagging false with with Xilinx flow.
104486: 06/06/28: Synplify prepending Z's to top level signal names in Verilog
104500: 06/06/28: Re: Synplify prepending Z's to top level signal names in Verilog
jacobo:
69633: 04/05/16: Please, I need help with a mpeg layer 1 decoder in vhdl
69644: 04/05/17: Re: Please, I need help with a mpeg layer 1 decoder in vhdl
jacobusn@xilinx.com:
121808: 07/07/13: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol
122237: 07/07/24: Re: DDR2 w/ MIG on Xilinx ML501 Board
122607: 07/08/01: Re: Xilinx Webpack 9.2 and Windows 2000 Pro?
122689: 07/08/03: Re: Spartan 3E starter kit DDR SDRAM
122691: 07/08/03: Re: Spartan 3E starter kit DDR SDRAM
122717: 07/08/04: Re: SDR SDRAM controller for Xilinx Spartan-3E
122878: 07/08/09: Re: Xilinx Webpack 9.1: How do I export a netlist to another project?
122977: 07/08/13: Re: Xilinx 13th August opportunity
124300: 07/09/18: Re: Unexplained behavior with DDR2 controller on Xilinx V5
124999: 07/10/15: Re: MIG for Linux?
126595: 07/11/28: Re: DDR2 controler
Jacqueline Linich:
29628: 01/03/02: San Francisco bay Hardware engineers
Jacques athow:
55952: 03/05/24: Has anyone tried Internet Design Team.
56304: 03/06/02: Re: HDLmaker update available
58308: 03/07/19: XILINX frequency meter from XCELL design question.
58329: 03/07/20: Re: XILINX frequency meter from XCELL design question.
58694: 03/07/30: DDS question. How to generate a square from a sine wave?
58711: 03/07/31: Re: DDS question. How to generate a square from a sine wave?
59577: 03/08/22: Re: Question about slew rate for SpartanII using ISE5.1
64059: 03/12/15: FLEX 10K50E, which software support it?
65470: 04/01/29: One bit Virtex BRAM.
65500: 04/01/30: Re: One bit Virtex BRAM.
67151: 04/03/06: Can anyone advise me on how to reduce the compilation time for our design...
67231: 04/03/08: Re: Can anyone advise me on how to reduce the compilation time for our design...
67629: 04/03/15: PACE 6.2 pin assignment before design HOW TO??
68767: 04/04/16: Huh, anybody wants to play some NES???
68771: 04/04/17: Re: Huh, anybody wants to play some NES???
68835: 04/04/19: Re: Huh, anybody wants to play some NES???
68841: 04/04/20: Re: Huh, anybody wants to play some NES???
72952: 04/09/08: Re: Need assistance with an FPGA based project.
72974: 04/09/09: Re: Need assistance with an FPGA based project.
74306: 04/10/07: Re: XILINX SHIPS ONE MILLION SPARTAN-3 FPGAS
Jacques GENIN:
108384: 06/09/10: X4000 bad configuration
108509: 06/09/12: Re: X4000 bad configuration
108604: 06/09/13: Re: X4000 bad configuration
108609: 06/09/14: Re: X4000 bad configuration
109248: 06/09/22: Re: X4000 bad configuration
109272: 06/09/22: Re: X4000 bad configuration
109311: 06/09/23: Re: X4000 bad configuration
109313: 06/09/23: Re: X4000 bad configuration
Jacques Pelletier:
6153: 97/04/18: FLEX 8000 FPGA Configuration
Jacques-Olivier Haenni:
7779: 97/10/14: AHDL to VHDL translation
<jacques77@gmail.com>:
87404: 05/07/22: Transfert data to Memec Virtex II Pro Card from PC
Jaded:
59750: 03/08/27: Help ! compxlib Error " mti_se not found" while Bulding XILINX libraries for ModelSim SE
<jadey@my-deja.com>:
23829: 00/07/12: Re: FFT/IFFT for FPGA
jadwin79:
142380: 09/08/07: Stale RTL schematic from VHDL in Xilinx ISE 11.1
Jae Cho:
95: 94/08/13: translator needed
4028: 96/09/04: speed up Xilinx P & R
4879: 96/12/23: Integer divide IC
Jae-cheol Lee:
30536: 01/04/13: Is there any free processor core for vertex series?
30538: 01/04/13: Thank you very much.
33392: 01/07/25: Q: dividing by 2 results in out-of-phase pulse sometimes
36129: 01/10/31: what about FPGA with embedded processor?
Jae-Ho Shin:
4720: 96/12/06: Or- gated clock solution?
5309: 97/02/06: PMC alternative
5310: 97/02/06: PMC alternative
Jaerder Sousa:
142128: 09/07/26: How to start FPGA development
142168: 09/07/28: Re: How to start FPGA development
142247: 09/07/30: Re: Antti-Brain, should I keep going?
JaeYong Kim:
21277: 00/03/15: Difference between FPGA, PLD, CPLD ?
jag9624:
138777: 09/03/10: Finding aligned clock transitions with state machine
138779: 09/03/10: Re: Finding aligned clock transitions with state machine
138795: 09/03/11: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
138796: 09/03/11: Re: Finding aligned clock transitions with state machine
138810: 09/03/11: Re: Finding aligned clock transitions with state machine
jagadeesh:
85624: 05/06/12: xilinx ml310 : to run applications on 2 nd ppc
86587: 05/06/30: Re: ppc 405 in debug halt mode
86816: 05/07/07: Re: ppc 405 in debug halt mode
Jagadeesh:
86222: 05/06/23: Re: ppc 405 in debug halt mode
jaggu:
86136: 05/06/22: ppc 405 in debug halt mode
86415: 05/06/27: Re: ppc 405 in debug halt mode
Jaggu:
82996: 05/04/21: xilinx ml310 + linux + System.map file problem
Jahagirdar Vijayvithal S:
87300: 05/07/21: Re: Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?
Jahanzebanwer:
149845: 10/11/28: EDIF netlist access in Xilinx ISE 8.1i
Jahid:
134468: 08/08/12: Re: Block Rams
jai:
12792: 98/10/29: 3.3V PCI without clamp diodes.
13120: 98/11/16: newbie question about timing
Jai:
110574: 06/10/18: how to implement integrator?
110658: 06/10/19: Re: how to implement integrator?
jai kishan:
11980: 98/09/22: 3.3V PCI to 5V local bus interface?
12834: 98/10/31: Re: 3.3V PCI to 5V local bus interface?
jai.dhar@gmail.com:
86608: 05/06/30: Re: Small FPGA
86707: 05/07/04: Ethernet FPGA development board
86771: 05/07/06: Re: Ethernet FPGA development board
88794: 05/08/28: Bootloading with flash-config devices
89177: 05/09/07: Re: Cyclone conf flash - 25p10 !
89227: 05/09/08: Re: Cyclone conf flash - 25p10 !
89248: 05/09/08: Re: Cyclone conf flash - 25p10 !
89259: 05/09/09: Re: Cyclone conf flash - 25p10 !
89271: 05/09/09: Re: Cyclone conf flash - 25p10 !
89356: 05/09/13: Re: SDRAM quality
89556: 05/09/19: FPGA's in bulk and pricing
89567: 05/09/19: FPGA's in bulk and pricing
89686: 05/09/22: Re: FPGA's in bulk and pricing
89817: 05/09/27: Re: altera new bee
90278: 05/10/07: New Ethernet Development board, open-source
90479: 05/10/14: Re: How to Reduce Interconnects (VDD and VSS)
90487: 05/10/14: Re: How to Reduce Interconnects (VDD and VSS)
90531: 05/10/15: Re: How to Reduce Interconnects (VDD and VSS)
90544: 05/10/16: Re: How to Reduce Interconnects (VDD and VSS)
90547: 05/10/16: Re: How to Reduce Interconnects (VDD and VSS)
90573: 05/10/17: Re: How to Reduce Interconnects (VDD and VSS)
90974: 05/10/26: Re: ETHERNET MAC
91735: 05/11/11: Re: How do i detect ethernet frames of layer 2 using ethereal?
91736: 05/11/11: Re: SDRAM controller.
100648: 06/04/14: Re: PCB Stack
100667: 06/04/15: Re: PCB Stack
106341: 06/08/11: Clock domain crossing (again)
106411: 06/08/12: Re: Clock domain crossing (again)
108996: 06/09/19: Re: E1 to ethernet conversion
114603: 07/01/20: Re: Altera EP2S60 rebooting itself
120633: 07/06/12: TDM stream multiplex/demultiplex
jaideep:
34587: 01/08/29: XC2V3000-4BF957
44113: 02/06/11: Digital FM demodulator in FPGA
44119: 02/06/12: Digital FM demodulator in FPGA-continue
44167: 02/06/12: Re: Digital FM demodulator in FPGA-continue
45457: 02/07/23: Field Programmable SoC's
59465: 03/08/19: random address
60294: 03/09/09: Re: AWGN in VHDL
60980: 03/09/25: Re: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
Jaime Andres Aranguren C.:
148078: 10/06/19: Re: Anyone else need bigger parts in small (low pin count) packages
148131: 10/06/22: Re: Xilinx BULLSHITIX-8, when?
149325: 10/10/16: Re: FPGA or CPLD?
Jaime Andres Aranguren Cardona:
33732: 01/08/02: 4 (8) bit Microporcessor Implementation
33784: 01/08/04: FPGA - VHDL Design Tools (Was: 4 (8) bit Microporcessor Implementation)
33790: 01/08/05: Which is the best Design Toolchain?
33800: 01/08/05: Re: Which is the best Design Toolchain?
33826: 01/08/06: Re: Which is the best Design Toolchain?
36381: 01/11/07: "Illegal assignment" message, NEED HELP, PLEASE!!!
36428: 01/11/08: Re: "Illegal assignment" message, NEED HELP, PLEASE!!!
41328: 02/03/25: I2C Slave sampling edge
48427: 02/10/17: Proveedor de Soluciones uC/FPGA/DSP - uC/FPGA/DSP Solutions Provider
48457: 02/10/17: Re: Proveedor de Soluciones uC/FPGA/DSP - uC/FPGA/DSP Solutions Provider
59352: 03/08/15: Re: FPGA/DSP Expert - business partner for innovative FFT
72578: 04/08/25: Re: DSP/FPGA/video board?
94053: 06/01/05: ModelSim vsim-3601 message
94065: 06/01/05: Re: ModelSim vsim-3601 message
94206: 06/01/07: Re: ISE 7.1 & ModelSim - Simulating Internal Signals
94384: 06/01/11: Re: Downloading WebPack-8.1, server maxes out at 30 kB / second (= > 7 hours)?
94385: 06/01/11: Re: Xilinx 7.1 ISE ModelSim input files
127415: 07/12/21: PowerPC & Spartan-3E Embedded Processing Development Kit - SP3E1600E MicroBlaze Edition
127417: 07/12/21: Re: PowerPC & Spartan-3E Embedded Processing Development Kit - SP3E1600E MicroBlaze Edition
130945: 08/04/06: Re: Examples for Spartan3 StarterKit
141593: 09/06/29: Re: usefulness of Virtex-II devices
141594: 09/06/29: Re: Spartan3E or Cyclone III ?
Jaime Andrés Aranguren Cardona:
20775: 00/02/21: Installing Xilinx Foundation on PC
74660: 04/10/15: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
74806: 04/10/19: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
94264: 06/01/09: Downloading Nios II Eval from Altera website
94766: 06/01/17: Re: xilinx free Sample Pack info now also on Xilinx own webpages
112746: 06/11/28: Re: logic analyzer using FPGA
<jaime.aranguren@ieee.org>:
28203: 00/12/29: Re: Verilog or VHDL
<jaimearanguren@my-deja.com>:
28204: 00/12/29: MAX+Plus II Output. to HEX
"Jaimeet Aneja":
29481: 01/02/23: Partial reconfig
29561: 01/02/27: Partial Reconfig using JBits
29562: 01/02/27: Re: Re: Partial reconfig
29594: 01/02/28: Re: Re: Partial Reconfig using JBits
jaimico:
142961: 09/09/10: Re: UART testbench debug
jaink:
134037: 08/07/22: Re: XAUI v7.2 - timing issue - *channel bonding attributes*
jajo:
109989: 06/10/09: Control of physical layer in a 802.11b
110042: 06/10/09: Finite State Machine
112236: 06/11/18: Input setup time & Output valid delay
112241: 06/11/18: Static Timing Analysis vs Dinamic Timing Analysis
112310: 06/11/20: Input setup time & Hold Input
117560: 07/04/04: Conceptos about VCCINT,VCCAUX,etc
JAK:
35265: 01/09/27: Xilinx Xactstep 5.1/6.1
Jakab Tanko:
28295: 01/01/05: Re: Fixing pins on Spartan II
28312: 01/01/05: Re: Fixing pins on Spartan II
28914: 01/01/29: Xilinx NODELAY attribute question
29163: 01/02/08: Re: Xilinx vs Altera
29193: 01/02/09: Re: Xilinx vs Altera
29275: 01/02/12: Re: Xilinx vs Altera
29749: 01/03/07: Re: Is there any Virtex-II Evaluation Board?
31030: 01/05/09: Re: Good VHDL/synthesis book
66755: 04/02/26: Re: DCM Simulation Error
67256: 04/03/09: Re: HOW to Increase jitter in ALTERA PLL ?
67337: 04/03/10: Re: HOW to Increase jitter in ALTERA PLL ?
67589: 04/03/15: Re: Which should I use, Floorplanner or PACE
159096: 16/07/27: Altera Ethernet MAC without DMA
159110: 16/07/31: Re: Altera Ethernet MAC without DMA
jakab tanko:
17578: 99/08/11: Xilinx: Verilog only???
20315: 00/02/04: Re: Conditional compilation in VHDL?
36121: 01/10/30: Re: Autostart Problem SPROM->FPGA
36419: 01/11/08: Xilinx dedicated IO pins
36435: 01/11/08: Re: Xilinx dedicated IO pins
37454: 01/12/11: DCM error
37493: 01/12/12: Re: DCM error
39563: 02/02/13: Re: Altera's new family Stratix
41599: 02/04/03: Re: Configuring the Virtex II FPGA
42482: 02/04/24: Re: SpartanII design considerations...
43219: 02/05/16: Re: SPARTAN II - Master serial mode configuration problem
44236: 02/06/14: Re: MAP problem with RLOC'ed macros
44461: 02/06/20: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
44943: 02/07/07: Re: DC to DC converter at 1.5V
45390: 02/07/22: Re: Xilinx (spartan 2) - SI even applies to the config pins
45855: 02/08/07: Re: Xilinx hiring practises
47059: 02/09/16: Re: Question about Virtex-II DCM's jitter
47221: 02/09/20: Re: Apex unused pins voluntarily assigned by Quartus?
47422: 02/09/25: Re: virtex II pro development board
48268: 02/10/15: Virtex2 5V tolerant I/O ??
51117: 03/01/02: Re: interface DRAM to FPGA
51120: 03/01/02: Re: interface DRAM to FPGA
51135: 03/01/03: Re: interface DRAM to FPGA
52637: 03/02/17: Measuring die temperature
52971: 03/02/27: Re: Unprogrammed XC9536XL is driving the databus high
56393: 03/06/04: Re: FPGA's an Flash
60496: 03/09/15: USB transceiver for FPGA
60508: 03/09/15: Re: USB transceiver for FPGA
60509: 03/09/15: Re: USB transceiver for FPGA
60549: 03/09/16: Re: USB transceiver for FPGA
61357: 03/10/02: Re: Good VHDL/Verilog editor?
61418: 03/10/03: Interesting article about FPGAs
62063: 03/10/17: ISE5.2 to ISE6.1
62130: 03/10/20: Re: Altium DXP for designing Xilinx FPGA
68719: 04/04/15: Re: what is a better approach to synthezise synchronous reset on FPGA?
70947: 04/07/02: Re: DCM ISE6.2.3 sim problem
71034: 04/07/06: Re: Place & route question in Xilinx...
<jakab.tanko@gmail.com>:
82650: 05/04/15: DCI question
82803: 05/04/18: Missing post
Jake:
43353: 02/05/20: Upgrade to ISE4.1/4.2 ?
80762: 05/03/11: re:Looking for low-cost protoboards.
109933: 06/10/08: Re: free CAN field bus IP for EDK ?
109959: 06/10/09: Re: free CAN field bus IP for EDK ?
Jake Janovetz:
11991: 98/09/23: Re: How to reduce ringing/ground bounce from FPGA output pin?
12077: 98/09/27: Re: Faster 32_bit integer multiplier required !!
12147: 98/10/01: Synthesis: Exemplar or Synopsys
12161: 98/10/01: Re: Synthesis: Exemplar or Synopsys
12304: 98/10/08: Re: Synthesis: Exemplar or Synopsys
15365: 99/03/20: Re: Bit Error Rate Test
15943: 99/04/22: Re: Job Advert Netiquette?
17317: 99/07/20: Re: Solaris vs. NT
17367: 99/07/22: Re: Solaris vs. NT
17368: 99/07/22: Re: Solaris vs. NT
54412: 03/04/10: Xilinx IOB flip flop mapping
54453: 03/04/10: Re: Xilinx IOB flip flop mapping
54473: 03/04/11: Re: Xilinx IOB flip flop mapping
55034: 03/04/24: Large adder placement / synthesis
55070: 03/04/25: Re: Large adder placement / synthesis
55345: 03/05/04: Re: PLL chips
55610: 03/05/13: "Primitives" in XST?
55620: 03/05/14: Re: "Primitives" in XST?
55667: 03/05/15: Re: "Primitives" in XST?
55832: 03/05/20: Re: a (PC) workstation for FPGA development
55889: 03/05/22: Re: FPGA design: firmware or hardware?
56240: 03/05/31: Re: FSM Coding Style
56419: 03/06/04: Protel DXP or other schematic entry?
56453: 03/06/05: Re: Galois Fields Applications
56871: 03/06/17: Re: Simple FEC algorithm
56892: 03/06/18: Re: Simple FEC algorithm
59526: 03/08/20: Re: DCM vs state machine
60526: 03/09/15: Xilinx ISE 6.1i
60564: 03/09/16: Re: Xilinx ISE 6.1i
60565: 03/09/16: Re: Xilinx ISE 6.1i
60641: 03/09/18: Re: Using LUTs for array of coefficients
60736: 03/09/20: Re: pipelined divider
61015: 03/09/26: Re: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
61050: 03/09/26: Re: Graphics rendering
61058: 03/09/26: Re: FF with CE doesn't synthesize correctly by XST?
61170: 03/09/29: Re: Counting ones
61327: 03/10/01: Good VHDL/Verilog editor?
61329: 03/10/01: Re: Parameterized Multiplier in Xilinx FPGA
61330: 03/10/01: Re: Parameterized Multiplier in Xilinx FPGA
61377: 03/10/02: Re: Good VHDL/Verilog editor?
61442: 03/10/03: Re: Good VHDL/Verilog editor?
61693: 03/10/08: Spartan 3 pinout typo?
61854: 03/10/14: Re: Spartan 3 pinout typo?
61973: 03/10/15: Re: To our future engineers, smart and otherwise...
62029: 03/10/16: Re: Spartan-3 non-ES availability, and misleading pricing info
62077: 03/10/17: Re: ISE5.2 to ISE6.1
62114: 03/10/19: Re: CPU vs. FPGA vs. RAM
62115: 03/10/19: Re: CPU vs. FPGA vs. RAM
62167: 03/10/21: Re: Altium DXP for designing Xilinx FPGA
62454: 03/10/29: Re: How to protect fpga based design against cloning?
62856: 03/11/10: Re: ISE 5.2 to 6.1
62877: 03/11/10: Re: Home grown CPU core legal?
63224: 03/11/18: Re: Xilinx Design entry via Schematic Capture - What tool to use ?
63759: 03/12/03: Command line in Windows?
63801: 03/12/04: Re: Command line in Windows?
63802: 03/12/04: Re: Command line in Windows?
63803: 03/12/04: Re: Command line in Windows?
65265: 04/01/22: Re: Spirit on Mars
67058: 04/03/04: Re: Xilinx Spartan 3 configuration
67080: 04/03/04: Re: Xilinx Spartan 3 configuration
68108: 04/03/26: Generating Xilinx cores.
69026: 04/04/25: Re: Looking for a USB-enabled flash-based microcontroller with CPLD/FPGA
70498: 04/06/17: IOBs in NGC - problem with OBUFT
70548: 04/06/20: Re: IOBs in NGC - problem with OBUFT
70635: 04/06/22: Re: IOBs in NGC - problem with OBUFT
72684: 04/08/28: Re: Counter counting on both clock edges.
73309: 04/09/18: Reconfigure Spartan 3 without losing BRAM?
73476: 04/09/22: Re: Virtex 4 integrated A/Ds? Yes it does.
79542: 05/02/20: Re: why are PCI-based FPGA cards so expensive ?
79913: 05/02/25: Re: Maximum Current utilized by Spartan-3
79927: 05/02/25: Re: Maximum Current utilized by Spartan-3
84703: 05/05/24: Re: Bresenham Algorithms
84709: 05/05/24: Re: Bresenham Algorithms
84765: 05/05/26: Re: State Machines.. and their efficiency.
98586: 06/03/13: Why does Xilinx hate version control?
98609: 06/03/13: Re: Why does Xilinx hate version control?
98612: 06/03/13: Re: Soldering SMT/BGA
98613: 06/03/13: Re: Soldering SMT/BGA
98614: 06/03/13: Re: Soldering SMT/BGA
98624: 06/03/13: Re: Why does Xilinx hate version control?
98755: 06/03/16: Re: Why does Xilinx hate version control?
Jake Kelly:
3136: 96/04/10: FREE Book: "Top Verilog Problems & How To Solve Them."
Jake7:
140562: 09/05/17: Online tool that generates parallel CRC and Scrambler
140905: 09/05/28: Re: Online tool that generates parallel CRC and Scrambler
140906: 09/05/28: Re: Online tool that generates parallel CRC and Scrambler
Jakka Bhasker Reddy:
45395: 02/07/22: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
Jakob:
98983: 06/03/18: Spartan 3 Power Supply Design
99006: 06/03/18: Re: Spartan 3 Power Supply Design
JAKOB NIKLASSON:
24394: 00/08/06: Re: Circuit Drawing
Jaksa:
111183: 06/10/30: FFT help
111188: 06/10/30: Re: FFT help
111234: 06/10/31: Re: FFT help
Jakub:
69658: 04/05/17: Xilinx training
Jakub Dudek:
65870: 04/02/09: Xilinx training
jalaram:
108898: 06/09/18: xilinx fir ipcore
jaleco:
10825: 98/06/24: How to Double Clk Freq in the FPGA design
10827: 98/06/24: Re: How to Double Clk Freq in the FPGA design
Jalen.Ong@gmail.com:
114453: 07/01/16: microcode in verilog?
118056: 07/04/17: Interfacing FPGA with TTL
jam:
28695: 01/01/21: Designing fractional counters?
Jamba:
47412: 02/09/25: spartan II and PCI 5 volt
james:
58051: 03/07/13: Re: Graduation Day: My first 4-layer PCB
58054: 03/07/13: Re: Graduation Day: My first 4-layer PCB
58082: 03/07/14: Re: Graduation Day: My first 4-layer PCB
58084: 03/07/14: Re: Graduation Day: My first 4-layer PCB
59560: 03/08/21: Re: Which software from Xilinx
59562: 03/08/21: Re: 22V10, ABEL & Current Design Tools?
60319: 03/09/10: Re: CMOS camera w/ USB2 -- crazy?
60322: 03/09/10: Re: CMOS camera w/ USB2 -- crazy?
60359: 03/09/11: Re: CMOS camera w/ USB2 -- crazy?
60388: 03/09/12: Re: CMOS camera w/ USB2 -- crazy?
77007: 04/12/20: Re: Digital clock synthesis
80230: 05/03/02: Re: SoC positions in Bangalore
80232: 05/03/02: Re: SoC positions in Bangalore
88370: 05/08/16: Re: image sensor
88552: 05/08/22: Re: how to reduce vga memory????????
88594: 05/08/23: Re: how to reduce vga memory????????
88784: 05/08/28: Re: TTL, CMOS and spartan
98023: 06/03/03: Re: problem with ISE versions
112074: 06/11/15: Re: Old Spartan-II, worth prototyping?
133656: 08/07/08: How can I create a direct FSL connection?
134972: 08/09/08: Re: Spartan 3E evaluation board manufacturers
135006: 08/09/10: Re: Spartan 3E evaluation board manufacturers
135009: 08/09/10: Re: Placing Verilog busses using Xilinx RPMs
135010: 08/09/10: Re: What version of ISE is availabe for Virtex5?
135011: 08/09/10: Re: Can Soft microprocessor replace DSP's
135049: 08/09/12: Re: Placing Verilog busses using Xilinx RPMs
135050: 08/09/12: Re: Spartan-II, config pins 5V tolerant? (slave serial)
137422: 09/01/15: Webpack 10.1 on Windows XP
137736: 09/01/28: Re: Problems when I download and install Xilinx ISE 10.1. Help please.
137739: 09/01/28: Re: What software do you use for PCB with FPGA ?
137749: 09/01/28: Re: What software do you use for PCB with FPGA ?
137780: 09/01/29: Re: What software do you use for PCB with FPGA ?
137933: 09/02/02: Re: Spartan-6
138748: 09/03/07: Re: Character generator ROM and VGA controller for Spartan 3E
139768: 09/04/13: Re: buy XSA-50
140551: 09/05/16: Re: how i can use the external SRAM of FPGA
141152: 09/06/09: Re: dsp with fpgas by Uwe Meyer-Baese
141321: 09/06/17: Re: Do you know how aggressive the patent fighting between Xilinx and Altera is going?
141585: 09/06/28: Re: usefulness of Virtex-II devices
143616: 09/10/18: Re: Memory Interface Generator
143617: 09/10/18: Re: Any interest in a group Xilinx FPGA board build/buy ??
144031: 09/11/08: Re: OK Xilinx users, it's time I was let in on the joke...
145218: 10/02/01: Re: How can I convert size requirements from Altera devices to Xilinx devices?
145236: 10/02/02: Re: What MAXIM chip is used on Spartan 3E 1600E Microblaze Board for RS232 communication?
145324: 10/02/05: Re: using an FPGA to emulate a vintage computer
145418: 10/02/08: Re: using an FPGA to emulate a vintage computer
145476: 10/02/11: Re: using an FPGA to emulate a vintage computer
145478: 10/02/11: Re: using an FPGA to emulate a vintage computer
145830: 10/02/25: Re: EDK spi ip core
146368: 10/03/14: Re: Nu Horizons Spartan 3A DSP board
146389: 10/03/15: Re: Nu Horizons Spartan 3A DSP board
146448: 10/03/18: Re: Nu Horizons Spartan 3A DSP board
146495: 10/03/20: Re: Xilinx only on Avnet now
147156: 10/04/15: Re: Implementing bidirectional bus inside the FPGA
147157: 10/04/15: Re: Implementing bidirectional bus inside the FPGA
150463: 11/01/23: Re: Xilinx news
James:
39298: 02/02/05: Programming Altera PGAs.
39392: 02/02/08: Re: Programming Altera PGAs.
52550: 03/02/13: Re: Generating EDIF from HandelC
58275: 03/07/18: Block Ram Preloading Data
58276: 03/07/18: Initialize Block RAM
60241: 03/09/08: Programming Xilinx CPLD under linux
63079: 03/11/13: Re: Code for accessing CF cards on Cyclone dev.board
69963: 04/05/25: Re: www.opencores.org ???
72199: 04/08/11: Re: Power Supply for Xilinx FPGA
76451: 04/12/02: FPGA Floating Point core IPs
78310: 05/01/29: Sensitive List Question
78324: 05/01/29: Re: Sensitive List Question
80866: 05/03/13: Newb: FSM in no valid state?
80883: 05/03/13: Re: Newb: FSM in no valid state?
80884: 05/03/13: Re: Newb: FSM in no valid state?
114585: 07/01/19: Re: Beginner VHDL questions
119352: 07/05/17: Unusual question about generic port use (optional ports??)
142657: 09/08/24: Help with altera_attribute and AUTO_GLOBAL_CLOCK
151419: 11/04/05: Help with SDC (specifically edge_shift)
151425: 11/04/06: Re: Help with SDC (specifically edge_shift)
152675: 11/09/26: Implementation Issue
152679: 11/09/27: Re: Implementation Issue
James A:
84456: 05/05/19: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84462: 05/05/19: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84463: 05/05/19: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84514: 05/05/20: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84563: 05/05/21: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
James Alston:
70113: 04/06/03: Re: 5 V inputs to 3.3 V CPLD
James Baker:
32923: 01/07/11: Erasing Altera EPC-1441?
James Ball:
85843: 05/06/17: Re: NIOS2 exceptions...
James Beck:
82494: 05/04/13: Re: Regarding driving of SCL and SDA pins of I2C
82577: 05/04/14: Re: Regarding driving of SCL and SDA pins of I2C
James Birmingham:
18303: 99/10/13: .cal .rbt file format
18808: 99/11/17: viewing fpga config
James Bonanno:
49009: 02/10/29: Re: power estimation XC2V2000 virtex-II FPGA
49441: 02/11/12: Re: new to fpga, what language is better to start with
50963: 02/12/23: Re: FPGA accelerated FPGA/ASIC tools
50982: 02/12/24: Re: FPGA accelerated FPGA/ASIC tools
James Bond:
91094: 05/10/29: xilinx design reuse netlist format
91100: 05/10/29: Re: xilinx design reuse netlist format
James Brennan:
30911: 01/05/03: FPGA based PCI cards
31473: 01/05/27: JPEG cores
33391: 01/07/25: A DIME module with simple RAM?
33915: 01/08/09: Wildcard and Foundation tools
33918: 01/08/09: Re: Wildcard and Foundation tools
77013: 04/12/20: Modelsim Segmentation faults
77020: 04/12/20: Re: Modelsim Segmentation faults
James Buchanan:
27245: 00/11/16: Actel Compiler errors..... from Synplify?!
James C. LaLone:
21614: 00/03/26: Re: Clock nets using non-dedicated resources
James C. Schwalbe:
35710: 01/10/15: Re: Linux tools
36600: 01/11/13: Re: Virtex 2 parts availability???
36601: 01/11/13: Re: PLL in Altera's Apex20K
James Calivar:
62632: 03/11/03: Re: Shannon Entropy for Black Holes
James Chang:
60601: 03/09/17: FPGA congress on Asia
James Cleary:
5416: 97/02/14: Re: Gate level Simulation with Mentors Quicksim from Galileo
James Cook:
9910: 98/04/13: Altera MAX+Plus II for sale
10075: 98/04/25: For sale: Altera MAX+Plus II
James Craig Ziegler:
8726: 98/01/22: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
James Dickson:
563: 95/01/05: Re: What's Up At ViewLogic?
614: 95/01/19: Re: Multiple FPGAs
711: 95/02/14: Re: Can I implement a digital PLL in an FPGA??
1106: 95/04/29: Re: VMEbus interface using fpgas
James Doherty:
12021: 98/09/24: Re: Which FPGA tool is better
12234: 98/10/06: Re: Which FPGA tool is better
12172: 98/10/02: Re: ISP Synario - need a help!
James Dow Allen:
145354: 10/02/06: Re: using an FPGA to emulate a vintage computer
145378: 10/02/07: Re: using an FPGA to emulate a vintage computer
James E. Stine:
12132: 98/09/30: Re: Fastest Add
12133: 98/09/30: Re: FIR Filter Design
12139: 98/10/01: Re: Fastest Add
12163: 98/10/01: Re: Fastest Add
12363: 98/10/09: Re: Help Desperately Needed with Altera Microprocessor Design.
12479: 98/10/13: Re: Digital Sine Generator
12481: 98/10/13: Re: Digital Sine Generator
12496: 98/10/13: Re: Digital Sine Generator
James E. Stine, Jr.:
9913: 98/04/13: Synplicity
9914: 98/04/13: Re: VHDL compiler differences ?
James Fakas:
5023: 97/01/14: Great Xilinx FPGA Kits & prices
5342: 97/02/08: Re: REPOST: New Web Site Dedicated to Programmable Logic
James Fitzsimons:
55958: 03/05/25: Newbie CPLD question
55969: 03/05/25: Re: Newbie CPLD question
55971: 03/05/25: Re: Newbie CPLD question
55998: 03/05/27: Re: Newbie CPLD question
60244: 03/09/09: Re: Programming Xilinx CPLD under linux
60252: 03/09/09: Re: Programming Xilinx CPLD under linux
James Flanagan:
52759: 03/02/20: Cupl Simulation Question
53629: 03/03/18: Low Power CPLD suggestion request...
James G:
17372: 99/07/22: Low Cost latched I/O
James H. Grandt:
1573: 95/07/19: FPGA Software...
James Hadley:
325: 94/10/19: Analog FPGAs
James Harris:
123711: 07/09/02: Beginning FPGA programming
123712: 07/09/02: FPGA CPU
123728: 07/09/03: Re: FPGA CPU
123785: 07/09/04: Re: FPGA CPU
123786: 07/09/04: Re: FPGA CPU
123787: 07/09/04: Re: FPGA CPU
123796: 07/09/04: Re: FPGA CPU
124232: 07/09/15: Re: Beginner Advice (Languages, tools etc.)
134642: 08/08/22: Re: Apple II on FPGA
135409: 08/10/01: Re: $99 XMOS Dev kit
135753: 08/10/14: Re: $99 XMOS Dev kit
135776: 08/10/15: Re: $99 XMOS Dev kit
135890: 08/10/20: Re: Looking for a FPGA board for starter
136202: 08/11/05: Xmos now shipping sillicon
136203: 08/11/05: Re: Xmos now shipping silicon
136216: 08/11/06: Re: TCP/IP 3 way handshake
139105: 09/03/20: Re: FPGA users, Please take a few seconds to report SPAM
140714: 09/05/22: Re: SPAM?
141681: 09/07/03: Re: TimingAnalyzer is now freeware
142821: 09/09/02: Re: Choice of Language for FPGA programming
145352: 10/02/06: Re: using an FPGA to emulate a vintage computer
146885: 10/03/30: Re: Which is the most beautiful and memorable hardware structure in a
149179: 10/10/06: Re: Starting a career with FPGAs
James Harry:
87707: 05/07/29: Re: Soft IPs licensing -gpl
James Horn:
8902: 98/02/06: Re: Power consumption
9520: 98/03/20: Re: Ideas for an FPGA Project?
21442: 00/03/22: Windowed Altera 1810s?
22230: 00/05/02: Re: How to Prevent theft of FPGA design
29789: 01/03/09: Springboard design contest
31850: 01/06/06: Re: one state machine
31857: 01/06/06: Re: one state machine
31934: 01/06/08: Re: Flash programming via FPGA's JTAG ????
37306: 01/12/06: Re: where is designed FPGA for APPLE....?
39996: 02/02/23: Re: Coolrunner and ISP
40212: 02/03/01: Re: Altera Excalibur
40584: 02/03/11: Re: Sandwich board at ESC
41079: 02/03/20: Re: FPGA or Micro-controller in Lowpower designs?
41241: 02/03/22: Re: A poor man's boundary scan test tool
41318: 02/03/25: Re: Can't detect Altera MAX7000s using JTAG
42631: 02/04/29: Re: ABEL for the Altera MAX 7000
43820: 02/06/03: Re: divide by 5
45659: 02/07/30: Re: Impedance Measureing
46910: 02/09/11: Re: FPGA comes with a DAC?
57203: 03/06/25: GAL16V8 reverse compilation
57211: 03/06/25: Re: GAL16V8 reverse compilation
58802: 03/08/01: Re: Size does matter
89032: 05/09/03: Re: Digilent's JTAG-USB cable with chipscope
89033: 05/09/03: Re: Platform Cable USB
James Jackson:
15900: 99/04/20: PIN/PAD files to Schematic Symbols
James Kellar:
12297: 98/10/08: Re: Help Desperately Needed with Altera Microprocessor Design.
14586: 99/02/05: Re: can I trust Altera Simulator?
James Kennedy:
23358: 00/06/23: What tools do people use for Xilinx FPGAs?
22977: 00/06/07: VHDL code works in foundation 1.5, dosen't work in 2.1?
44322: 02/06/18: Re: Internal oscillator in CPLD?
94123: 06/01/06: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
96331: 06/02/02: Re: Spartan3 pullups
James Kim:
9978: 98/04/20: Xilinx FPGAs: Usable Pins on XS Boards (Help)
James L Horn:
7543: 97/09/20: Re: Altera FPGA - asynch serial
James LaLone:
9745: 98/04/02: Re: Synthesizable 8B/10B Encoder/Decoder wanted
9776: 98/04/04: Re: Smoking Crater in a Xilinx 3k FPGA
13125: 98/11/17: Synthesizeablel fifo
13187: 98/11/19: Re: Synthesizeablel fifo
James Lawrence:
29560: 01/02/27: Computer Guide
James Lee:
10998: 98/07/09: Re: question on combinational logic synthesis for FPGA
34348: 01/08/22: Re: Principles of Verifiable RTL Design (2nd ed)
James Lewis:
40936: 02/03/18: Xilinx makesrc problem/questions
41100: 02/03/20: Xilinx Spartan XL VHDL????
James Ma:
96822: 06/02/11: Using Ethernet to control/initialize FPGA
103649: 06/06/07: Easily add 4 Gb/s Ethernet link to FPGA systems for control & data transfer
James Meyer:
14036: 99/01/08: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
James Morrison:
66180: 04/02/13: Re: Sensible starter FPGA board
68574: 04/04/08: Re: Can I use the Done signal in FPGA to reset my design
68902: 04/04/21: Re: FPGA within demonstration
68932: 04/04/22: Re: cpld in plcc84 package
69411: 04/05/10: Re: Monolithic state machine or structured state machine?
77899: 05/01/19: Re: LVDS through connectors
77914: 05/01/20: Re: LVDS through connectors
77985: 05/01/21: Re: Configuring FPGA using PROM/uP
80910: 05/03/14: Re: XCF01's in the UK
81287: 05/03/21: Re: TPS75003 for FPGAs
85814: 05/06/16: BGA Rework/Prototype Placement Anyone?
85841: 05/06/16: Xilinx Spartan 3 DCI Power Consumption
86152: 05/06/22: Re: disappointed with Altera this time
86249: 05/06/23: Re: iMPACT downloading error
86258: 05/06/23: Re: Issues with Xilinx xapp635: Interface for TigerSharc Link Ports.
86610: 05/06/30: Re: Coverting .mcs file to .bit file
88551: 05/08/22: Generic Memory-Mapped VHDL Module
97316: 06/02/20: Re: Is FPGA code called firmware?
104816: 06/07/06: Can a BUFGMUX drive a global clock in the Spartan-3?
James Peters:
124466: 07/09/23: Any advice on Steve Kilts' "Advanced FPGA Design: Architecture, Implementation,
James Robinson:
143200: 09/09/25: Super Small MIPS-compatible Altera-Based Soft Processor and compiler
143212: 09/09/25: Re: Super Small MIPS-compatible Altera-Based Soft Processor and
143254: 09/09/28: Re: Super Small MIPS-compatible Altera-Based Soft Processor and
James S.:
25852: 00/09/22: Need Help: Xilinx FastCLK (XC4000XLA)
26388: 00/10/13: clk'event
26881: 00/11/02: OT: Xilinx T-Shirt
James Salisbury:
145758: 10/02/22: Re: FPGA platform??
146665: 10/03/25: Re: EMC discussion
147197: 10/04/17: Re: Which 32 bit cores support full Linux?
James Srinivasan:
38642: 02/01/20: Re: Nios development kit
38643: 02/01/20: Altera Nios v2
38647: 02/01/20: Re: Altera Nios v2
38772: 02/01/24: Re: Altera Nios v2
39952: 02/02/22: Re: Pin assignments in QUARTUS
39961: 02/02/22: Re: Pin assignments in QUARTUS
42172: 02/04/17: Re: Problems with Nios 2.0
42442: 02/04/24: Re: Reasonably Priced Development Software ??
42444: 02/04/24: Re: Reasonably Priced Development Software ??
53660: 03/03/19: Re: Quartus2 : assigning I/O pins
53685: 03/03/20: Re: Quartus2 : assigning I/O pins
53759: 03/03/21: Re: Using FPGAs as coprocessors in a PC
James Stine:
9569: 98/03/24: Re: New radix-4 CORDIC for computing sine and cosine
12151: 98/10/01: Re: Fastest Add
12152: 98/10/01: Re: FIR Filter Design
James T. White:
22665: 00/05/16: Re: PC104+ FPGA Board
96542: 06/02/06: Re: Protected power calculation spread sheets
114013: 07/01/02: Re: Surface mount ic's
James Thiele:
4815: 96/12/17: Re: ASICs Vs. FPGA in Safety Critical Apps.
James Thurley:
41301: 02/03/25: Can't detect Altera MAX7000s using JTAG
41343: 02/03/26: Re: Can't detect Altera MAX7000s using JTAG
James Tucker:
106767: 06/08/18: Re: Open-source JTAG software?
James W. Swonger:
4972: 97/01/07: Re: ASICs Vs. FPGA in Safety Critical Apps.
6269: 97/05/07: Re: Advantages/disadvantages between CMOS/BiCMOS
James Wallis:
29462: 01/02/22: PCI : Not booting on ASUS
29706: 01/03/05: Re: PCI : Not booting on ASUS
James Wang:
32801: 01/07/09: Spartan-II implementation woes
48671: 02/10/22: Altera FPGA and EPLD Download ByteBlaster
48904: 02/10/26: Re: Altera FPGA and EPLD Download ByteBlaster
48906: 02/10/26: Altera ByteBlaster
48922: 02/10/26: Announce: FPGA Demo Board
68528: 04/04/07: Altera ByteBlasterMV Download Cable
71064: 04/07/07: Minford Altera FPGA CPLD Byteblaster Downloader
72315: 04/08/14: Minford MF160 FPGA and CPLD Downloader -- Replace for Altera ByteBlaster II
72643: 04/08/27: Replace for Altera ByteBlaster II -- Minford MF160 FPGA and CPLD Downloader
James West:
4864: 96/12/20: Re: I2C Bus Interface in FPGAs
5098: 97/01/23: Re: Altera support better than Xilinx
5841: 97/03/20: Re: Sole source
James Williams:
60831: 03/09/23: IEEE 1284 Core for Xilinx
60833: 03/09/23: New to VHDL for Xilinx
60842: 03/09/23: Re: New to VHDL for Xilinx
60849: 03/09/23: Re: New to VHDL for Xilinx
60892: 03/09/24: Re: IEEE 1284 Core for Xilinx
60945: 03/09/25: Re: IEEE 1284 Core for Xilinx | Reading Japanese FPGA pages
60948: 03/09/25: Re: IEEE 1284 Core for Xilinx | Reading Japanese FPGA pages
61005: 03/09/26: Re: IEEE 1284 Core for Xilinx | Reading Japanese FPGA pages
61213: 03/09/30: Re: Is Xilinx Webpack 6.1 help crippled?...
61216: 03/09/30: Re: Is Xilinx Webpack 6.1 help crippled?...
61232: 03/09/30: Implementing multiple registers with one single input output bus and address select in VHDL.
James Wolffe:
17559: 99/08/10: Re: Emulating a transputer on FPGA
James Wong:
47179: 02/09/19: designing DDR I/O in CPLD
James Wu:
114535: 07/01/18: Beginner VHDL questions
James Yeh:
17448: 99/07/28: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
17936: 99/09/17: Question about Alliance 2.1i
18242: 99/10/08: Re: Capacity metrics for Virtex
18546: 99/10/29: StateCAD versus Viewdraw
18549: 99/10/30: Re: StateCAD versus Viewdraw
19478: 99/12/23: viewlogic problem
19484: 99/12/24: Re: viewlogic problem
James Young:
23112: 00/06/14: Question: Xilinx FPGA PROGRAM pin
James Zaiter:
43409: 02/05/21: i need help getting started with fpgas
<james.e.steward@gmail.com>:
135580: 08/10/08: ChipScope on Ubuntu 7.10 - blank screen
<james.knoll@gmail.com>:
92064: 05/11/21: JTAG read from xc18v04
<james.lbs@gmail.com>:
123864: 07/09/06: FATAL ERROR ISE9.1i
124169: 07/09/13: Xilinx System Generator Error!
<james.r.lamb@comcast.net>:
90759: 05/10/20: C source for Spartan-3 with microblaze soft core for RS-232 comm
james.rowland1:
29062: 01/02/04: initialise state machine on Altera
30535: 01/04/13: Re: RC4/ARC4 on an FPGA.
James07:
158072: 15/07/30: Picking the best synthesis result before implementation
<james7uw@yahoo.ca>:
103959: 06/06/15: Xilinx MicroBlaze and Multimedia Demo. board: Debugging: 8.1.03i EDK - Unable to sync with stub on board
103961: 06/06/15: Re: Xilinx MicroBlaze and Multimedia Demo. board: Debugging: 8.1.03i EDK - Unable to sync with stub on board
108372: 06/09/09: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108376: 06/09/09: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108401: 06/09/10: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108456: 06/09/11: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108478: 06/09/11: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108516: 06/09/12: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108552: 06/09/12: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108553: 06/09/12: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108642: 06/09/14: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
109339: 06/09/24: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
109343: 06/09/24: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
109367: 06/09/25: Does anyone know what "SE" and "PE" stand for in ModelSim?
109382: 06/09/25: Re: Does anyone know what "SE" and "PE" stand for in ModelSim?
109388: 06/09/25: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
109389: 06/09/25: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
109390: 06/09/25: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
109393: 06/09/25: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
109420: 06/09/26: Re: Does anyone know what "SE" and "PE" stand for in ModelSim?
109443: 06/09/26: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
109564: 06/09/28: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
109565: 06/09/29: ModelSim path problem as fed by Xilinx ISE ver 8.2.03i
109596: 06/09/29: Re: ModelSim path problem as fed by Xilinx ISE ver 8.2.03i
109597: 06/09/29: Re: ModelSim path problem as fed by Xilinx ISE ver 8.2.03i
James823:
154283: 12/09/23: Getting in to the industry
154510: 12/11/22: Set-up and hold times and metastability
154517: 12/11/22: Re: Set-up and hold times and metastability
154519: 12/11/22: Re: Set-up and hold times and metastability
154531: 12/11/23: Re: Set-up and hold times and metastability
<jamesantone@if.rmci.net>:
12865: 98/11/02: Altera bitstream file format
12925: 98/11/04: Re: Altera bitstream file format
jamesp:
92875: 05/12/08: What graphical entry/documentation tools?
<jamesxy@hotmail.com>:
<jamicrotech@gmail.com>:
131001: 08/04/08: OBUF gate delay
Jamie:
55103: 03/04/26: Re: ISE 5.2i evaluation and problem with Windows ME
99999: 06/03/31: Re: Concatenate String in Verilog?
jamie:
72883: 04/09/07: Re: VHDL code for 16-32 bit counter for quadrature encoder signals
72927: 04/09/08: Re: VHDL code for 16-32 bit counter for quadrature encoder signals
Jamie Honan:
20238: 00/02/02: Foundation 1.5 VHDL compiler command line
Jamie Lokier:
10902: 98/06/29: Re: Xilinx file compression
11169: 98/07/22: Re: Too much advertising in this news group?
11269: 98/07/31: Re: Schematic Symbol Generation
11270: 98/07/31: Re: TRISTATE in FPGA
11271: 98/07/31: Altera tools on Linux
11277: 98/08/01: Re: Altera tools on Linux
11558: 98/08/24: Re: Altera FLEX10K ClockLock/ClockBoost ?
11559: 98/08/24: Re: Data I/O Chiplab and NT
11955: 98/09/21: Re: ASIC -> FPGA async issues
12511: 98/10/14: Re: Altera MAXPLUS2 V9 slow.
12512: 98/10/14: Re: 100 MHz FPGA
12948: 98/11/06: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
12866: 98/11/03: Re: Altera bitstream file format
13150: 98/11/17: Re: Synthesizeablel fifo
13223: 98/11/20: Re: Synthesizeablel fifo
13260: 98/11/22: Re: Synthesizeablel fifo
13983: 99/01/06: Re: 22V10 Metastability - my 2c
14020: 99/01/07: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14148: 99/01/15: Re: AHDL VS. VHDL
14149: 99/01/15: The development of a free FPGA synthesis tool
14175: 99/01/17: Re: The development of a free FPGA synthesis tool
14211: 99/01/20: Re: The development of a free FPGA synthesis tool
14332: 99/01/26: C to Hardware translators [was: The development of a free FPGA synthesis tool]
14333: 99/01/26: Re: small correction
14425: 99/01/29: Re: The development of a free FPGA synthesis tool
14427: 99/01/29: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
14428: 99/01/29: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
14460: 99/01/30: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
14463: 99/01/30: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
14501: 99/02/02: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
14839: 99/02/19: Re: P&R times for Altera10K200E and Virtex
14860: 99/02/20: Re: P&R times for Altera10K200E and Virtex
15792: 99/04/14: Re: bitstream
15802: 99/04/15: Re: bitstream
15803: 99/04/15: Re: Problems with high pin count FPGA systems
15931: 99/04/22: Re: Asynchronous Logic in Altera 10K devices
16387: 99/05/19: Re: flex10k 1 gate change
16589: 99/05/29: Re: Xilinx M1.5 Crash
17078: 99/06/29: Re: Read/Writes to memories/register files for PIC core
17094: 99/06/30: Re: Read/Writes to memories/register files for PIC core
17349: 99/07/22: Re: Solaris vs. NT
18813: 99/11/17: Re: implementing TCP/IP on PLD
18852: 99/11/19: Re: implementing TCP/IP on PLD
18858: 99/11/19: Re: implementing TCP/IP on PLD
19443: 99/12/22: Re: Speed grade
20840: 00/02/23: Re: Looking for a small, fast CPU core for FPGA
20899: 00/02/25: Re: Looking for a small, fast CPU core for FPGA
23350: 00/06/23: Re: Error: Clock skew plus hold time of destination register exceeds register-to-register delay
25814: 00/09/21: Re: Ethernet MII + bit ordering
26036: 00/10/01: Re: Altera FPGA experts needed
26037: 00/10/01: Re: multi-input adders in virtex ?
26140: 00/10/05: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26172: 00/10/06: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26260: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26261: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26262: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26263: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26265: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26266: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26267: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26268: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26276: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26285: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26303: 00/10/11: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26309: 00/10/11: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26341: 00/10/12: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26342: 00/10/12: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26349: 00/10/12: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26379: 00/10/13: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26383: 00/10/13: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26916: 00/11/03: Re: Alliance under Linux?
27215: 00/11/15: Re: jobs for FPGA designer (remote)
27379: 00/11/20: Re: In the news
27830: 00/12/11: Re: jtag for fpga
27996: 00/12/19: Re: dual port ram for altera
28435: 01/01/12: Re: Alliance for Linux
28521: 01/01/16: Re: Alliance for Linux
28522: 01/01/16: Re: revision control tools ??
28523: 01/01/16: Re: http://www.datasheetlocator.com/nl
28960: 01/01/31: Re: Advice on FPGA board.
29304: 01/02/13: Re: Handel-C language.
29321: 01/02/14: Re: Handel-C language.
29541: 01/02/26: Re: cpul vs vhdl
30477: 01/04/10: Re: Handel-C
30478: 01/04/10: Re: free software
30977: 01/05/07: Re: Shannon Capacity
jamie morken:
13285: 98/11/24: Foundation 1.4 error message
13330: 98/11/26: parallel cable III -> Spartan
13707: 98/12/18: Re: MP3 and FPGA's
14707: 99/02/12: Re: reconfiguring Logiblox ROM's
14708: 99/02/12: XC6200 series
14812: 99/02/18: four signals into array?
14847: 99/02/19: Re: four signals into array?
14848: 99/02/19: variable assignment in process or outside of process
Jamie Morken:
15333: 99/03/19: Xilinx Vhdl "'event" synthesis problem
15351: 99/03/19: Re: Xilinx Vhdl "'event" synthesis problem
15389: 99/03/21: HDL-307 error
15430: 99/03/23: Re: HDL-307 error
15431: 99/03/23: big/little endian mishap
15522: 99/03/29: virtex partial reconfiguration
47682: 02/10/02: Re: Implementing Delta-Sigma ADC and DAC in Spartan IIE
47725: 02/10/02: Re: Implementing Delta-Sigma ADC and DAC in Spartan IIE
48394: 02/10/17: multiple clocks
48468: 02/10/18: using the JTAG port for debugging
48672: 02/10/22: clock divider
48687: 02/10/22: Re: clock divider
50264: 02/12/06: Clocking in a Spartan IIE
50268: 02/12/07: Re: Clocking in a Spartan IIE
50289: 02/12/07: Re: Clocking in a Spartan IIE
50311: 02/12/08: Using DLL's
50312: 02/12/08: Re: Clocking in a Spartan IIE
50361: 02/12/09: Re: Clocking in a Spartan IIE
56781: 03/06/15: xilinx webpack programming
56783: 03/06/16: Re: xilinx webpack programming
56834: 03/06/17: Re: xilinx webpack programming
134405: 08/08/09: altera cyclone3 484BGA package
134417: 08/08/09: altera cyclone3 vertical migration
134499: 08/08/14: Re: altera cyclone3 484BGA package
134587: 08/08/20: Re: altera cyclone3 vertical migration
134651: 08/08/24: Re: altera cyclone3 vertical migration
136282: 08/11/09: FIR filter in Quartus
137034: 08/12/19: PLL and clock in altera cyclone 2 fpga
137050: 08/12/21: filtering decimation of a signal
Jamie Neilson:
23562: 00/06/30: Re: Canadian University
Jamie Sanderson:
14531: 99/02/03: Re: VHDL clocked one-shot Implementation Problem
14833: 99/02/19: Re: multiple clock domain problem
14924: 99/02/25: Re: Where do I connect my reset pins to?
15775: 99/04/13: Re: Placement constraints on LOGIBLOX instances
16237: 99/05/11: Re: Synchronizer design?
16265: 99/05/12: Re: Synchronizer design?
16562: 99/05/28: Re: High speed with VHDL
16779: 99/06/08: Re: LINE DELAYS USING RAMS
17211: 99/07/09: Re: how to choose only a set of pins
18097: 99/09/29: Re: Need help programming Spartan FPGA with Atmel serial EEPROM
18880: 99/11/19: Virtex: Getting flip-flops into the pads
18936: 99/11/22: Re: Virtex: Getting flip-flops into the pads
19156: 99/12/02: Re: Connection of light diode and FPGA
19157: 99/12/02: Re: Tristate bidirectional pads with Xilinx
19178: 99/12/03: Help with ROM in Xilinx Virtex
19182: 99/12/03: Solution: ROM in Xilinx Virtex
19211: 99/12/06: Re: Help with ROM in Xilinx Virtex
19248: 99/12/08: Re: Is there two-read one-write asynchronous SRAM in FPGA?
21537: 00/03/24: Altering Xilinx FPGA version/ID after PAR
21663: 00/03/28: Re: Altering Xilinx FPGA version/ID after PAR
22200: 00/05/01: Re: Initial DFF value for Virtex in VHDL
25248: 00/09/01: Re: More than 4 clocks in virtex
25252: 00/09/01: Virtex-E DLL Question
25794: 00/09/20: Re: VHDL to SCHEMATIC
26835: 00/10/31: Re: Alliance under Linux?
27104: 00/11/10: Virtex 32x1 RAM - Prevent usage
27727: 00/12/05: Route/Logic delay ratio
27913: 00/12/14: Re: VHDL technique for synchronizer ?
27914: 00/12/14: Re: Is it necessary to synchronize the reset signal in an FPGA ?
27915: 00/12/14: Re: Verilog or VHDL
27977: 00/12/18: Re: Verilog or VHDL
28414: 01/01/11: CRC - from long division to XOR, how?
28436: 01/01/12: Re: CRC - from long division to XOR, how?
28501: 01/01/15: Re: CRC - from long division to XOR, how?
28624: 01/01/18: Re: CRC - from long division to XOR, how?
28626: 01/01/18: Re: revision control tools ??
28645: 01/01/19: Re: revision control tools ??
28789: 01/01/24: Re: Encryption is supported in new Virtex II but.....
28863: 01/01/26: RAM reset question - Xilinx Virtex
29211: 01/02/09: Re: Need help using bitgen
29212: 01/02/09: Re: Low skew lines in Virtex-E
29326: 01/02/14: Re: Duplicate definitions for timing specs (xilinx fnd)
30258: 01/03/29: Re: PCI-X core
30507: 01/04/11: Re: Changing Xilinx ROM contents without recompiling
32027: 01/06/11: Xilinx PCI core location constraints
32125: 01/06/14: Re: Xilinx PCI core location constraints
32645: 01/07/04: Re: Is the Grass Greener for an Engineer in the USA?
32653: 01/07/04: Re: Is the Grass Greener for an Engineer in the USA?
32704: 01/07/05: Re: How to estimate the number of CLBs ?
32971: 01/07/13: Re: Xilinx BRAM failures
33227: 01/07/19: Re: 30 m cable reception with APEX LVDS I/O ?????
33325: 01/07/23: Re: Synchronous output enable not supported?
34146: 01/08/15: Internal clock skew when using DLL
34153: 01/08/15: Re: Internal clock skew when using DLL
34154: 01/08/15: Re: Internal clock skew when using DLL
34207: 01/08/16: Re: Internal clock skew when using DLL
34249: 01/08/17: Re: Internal clock skew when using DLL
34261: 01/08/17: Re: Internal clock skew when using DLL
35115: 01/09/21: Xilinx PCI bridge reference design
35237: 01/09/26: Re: Logical constraints of LUT
35238: 01/09/26: Re: Virtex 2 : using IOB registers
36026: 01/10/26: Re: future Xilinx products wish list ...
69707: 04/05/18: Re: Drive strength on I/O pads
<jamiehl@gmail.com>:
99241: 06/03/21: need help with vhdl code in custom IP
Jamil:
50893: 02/12/22: Compiling Altera LPM on leonardo
51001: 02/12/25: Free Opne hardware designs and tools on CDROMs
Jamil Hayder:
158511: 15/12/09: Error in converting code to VHDL
Jamil Khaib:
17646: 99/08/18: Re: fpga board : make it or buy it?
17993: 99/09/21: Free Hardware "CPLD board"
18259: 99/10/11: GNU License for Hardware
18356: 99/10/18: free Online ASIC course
19492: 99/12/26: FIFO design
19520: 99/12/29: USB2 core call for Volunteers
19521: 99/12/29: OpenIPCore call for examples
19522: 99/12/29: sim error & webfitter
19547: 99/12/30: Re: USB2 core call for Volunteers
19727: 00/01/10: PCI/USB project started
19745: 00/01/11: HW resources increased
19787: 00/01/12: Re: PCI/USB project started
19819: 00/01/13: call for comments
19904: 00/01/17: Design flow needed
19906: 00/01/17: Re: Partly reprogrammable FPGAs
19920: 00/01/18: Cores interfaces
20010: 00/01/23: Re: WebFitter???
20216: 00/02/01: part time
20268: 00/02/03: please help me
Jamil Khatib:
14168: 99/01/16: Run-Time-Reconfigurable logic
15512: 99/03/29: FIFO design
15579: 99/04/01: Re: IP cores and software industry
15713: 99/04/09: Re: Reconfigurable Computing
15715: 99/04/09: Re: Does any one want to talk about Dynamic Configuration?
15716: 99/04/09: Re: FIFO
15964: 99/04/23: JBITs
16600: 99/05/29: Modelsim, VHDL & mem core
17230: 99/07/12: Memory cores
17235: 99/07/13: OpenIP Call for contribution
20519: 00/02/13: FPGA verification
20535: 00/02/14: LUT & VHDL
20915: 00/02/27: clocked or not clocked?
21632: 00/03/27: Stimulus generator
21738: 00/03/30: Memory cores
21824: 00/04/02: Re: RISC/CISC Processor with Reconfigurable Logic
21900: 00/04/06: Power up set
21963: 00/04/10: Distributed Arithmetic
21989: 00/04/11: LUT
21991: 00/04/11: LUT
21988: 00/04/11: LUT
21990: 00/04/11: LUT
22023: 00/04/13: Parallel to serial
22070: 00/04/18: Re: synchronous FIFO
22125: 00/04/26: Foundation 2.1i
22127: 00/04/26: Re: Any good third-party place and route tools?
22215: 00/05/02: random integer
22293: 00/05/04: Vital glitch
22500: 00/05/10: Re: Hardware TCP/IP stack?
22963: 00/06/06: Re: DCT and FPGA !!!!
22964: 00/06/06: Free tools "OpenTech cdrom"
23051: 00/06/11: Virtex questions
23129: 00/06/15: Re: FIFO design
23269: 00/06/20: Re: FIFO design
23452: 00/06/26: Canadian University
23933: 00/07/16: Re: FPGA Intro
24078: 00/07/26: Arithmetic Operators
24084: 00/07/26: Variable shifting
24235: 00/07/31: Re: Variable shifting
24272: 00/08/02: FPGA selection
24299: 00/08/03: Re: FPGA selection
31322: 01/05/18: CDROMs with Free tools and designs
31449: 01/05/24: Vhdl coding style for fpga
31470: 01/05/26: Internal tri states
31625: 01/05/31: Help in FIFO design
31734: 01/06/05: FPU IEEE-754 calculation
137250: 09/01/05: OpenTech Package
<jamil.khatib@googlemail.com>:
103711: 06/06/09: The 3rd International Electronics Design Contest for Students
<jamil.khatib@pmail.net>:
24870: 00/08/21: Re: fifo;s
24873: 00/08/21: OpenTech cdrom new release
24874: 00/08/21: OpenTech cdrom new release
25265: 00/09/03: Win a free OpenTech cdrom
<jamilkhatib75@yahoo.com>:
89166: 05/09/07: OpenTech open source designs and tools
<jamilkhatib@my-deja.com>:
24384: 00/08/06: Re: FPGA selection
Jamin:
69295: 04/05/05: Re: JTAG, Master Serial Mode
jammurao:
136198: 08/11/05: Usage of Rocket IO GTP for 32 bit interface
jams:
115818: 07/02/21: up down lfsr
jan:
46516: 02/09/02: synthesizing hard coded numbers
154165: 12/08/24: Re: How do you do an incdir in Vivado
Jan:
60455: 03/09/13: DDC design
61456: 03/10/04: Re: Graphics rendering revisited
135782: 08/10/16: Simulation
135788: 08/10/16: Distributed Dual-Port RAM
135789: 08/10/16: Re: Distributed Dual-Port RAM
135810: 08/10/16: Re: Distributed Dual-Port RAM
135830: 08/10/17: Re: Simulation
135849: 08/10/17: Port mapping (combining components)
135852: 08/10/17: Re: Port mapping (combining components)
135871: 08/10/19: Field update
136358: 08/11/12: Using the FF @ Port pin
136363: 08/11/13: Re: Using the FF @ Port pin
136902: 08/12/11: Re: How to insert ChipScope
136977: 08/12/16: Microblaze without external ram
137091: 08/12/22: Adding userports to a custom peripheral in XPS
137105: 08/12/23: Re: Adding userports to a custom peripheral in XPS
137278: 09/01/07: Re: Which revision control do fpga designers use (2009)
138026: 09/02/04: Choosing RAM for microblaze and connecting it.
Jan Bernauer:
78113: 05/01/25: Re: trouble setting up ISE 6.3i in linux
86002: 05/06/20: Re: Microblaze address space and variables
Jan Bruns:
74511: 04/10/13: HDL-Models of CLB/Slice
74530: 04/10/13: Re: HDL-Models of CLB/Slice
74690: 04/10/16: Re: SPARTANI II - PCI target logic - what code generates burst read ?
74792: 04/10/19: alternatives to xst-map
74801: 04/10/19: Re: alternatives to xst-map
74826: 04/10/20: Re: alternatives to xst-map
79765: 05/02/24: routing delays (Xilinx)
79770: 05/02/24: Re: How to synthesize the xilinx ip core?
79906: 05/02/25: Re: routing delays (Xilinx)
81358: 05/03/22: VREF for SSTL out only / PCB
81379: 05/03/22: Re: VREF for SSTL out only / PCB
81851: 05/04/02: Re: [info] Sine generation
81885: 05/04/04: Re: how to use both FFs in a CLB's slice using LOC or RLOC
82029: 05/04/06: CPLD: collapse
82032: 05/04/06: Re: collapse
82096: 05/04/06: Re: collapse
82103: 05/04/07: Re: CPLD: collapse
136399: 08/11/14: purpose of MULTAND
136409: 08/11/14: Re: purpose of MULTAND
136491: 08/11/19: Spartan3 SRL16 + SliceFF, LUT stability
136492: 08/11/19: Re: Linux on Microblaze
136497: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
136503: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
136508: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
136511: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
136515: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
136517: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
136524: 08/11/20: Re: Spartan3 SRL16 + SliceFF, LUT stability
136526: 08/11/20: Re: Spartan3 SRL16 + SliceFF, LUT stability
136530: 08/11/20: Re: Spartan3 SRL16 + SliceFF, LUT stability
136568: 08/11/22: Re: Small adders in XST?
136570: 08/11/22: Re: Small adders in XST?
136586: 08/11/24: Re: Small adders in XST?
136621: 08/11/26: Re: added jitter on FPGAs
136945: 08/12/15: Re: JTAG / IMPACT / VIRTEX
137317: 09/01/08: Re: New to FPGA's, please help
137441: 09/01/16: Re: Death of the RLOC?
137444: 09/01/16: Re: Death of the RLOC?
137461: 09/01/18: Re: Using memory blocks generated by CoreGen
137499: 09/01/21: config prob with spartan3
137507: 09/01/21: Re: config prob with spartan3
137553: 09/01/22: Re: config prob with spartan3
137661: 09/01/27: Spartan3: 3.3V IOB on 2.5V config lines
137662: 09/01/27: Re: Spartan3: 3.3V IOB on 2.5V config lines
137678: 09/01/27: Re: Spartan3: 3.3V IOB on 2.5V config lines
137697: 09/01/28: Re: XST Makes Odd Choice
137713: 09/01/28: Re: XST Makes Odd Choice
137753: 09/01/29: Re: XST Makes Odd Choice
137774: 09/01/29: Re: XST Makes Odd Choice
137855: 09/02/01: Re: Heavily pipelined design
137948: 09/02/03: Re: fpga reset
137959: 09/02/03: Re: Why the second flip-flop in Virtex-6?
137979: 09/02/03: Re: Why the second flip-flop in Virtex-6?
137996: 09/02/03: Re: Why the second flip-flop in Virtex-6?
138000: 09/02/04: Re: Why the second flip-flop in Virtex-6?
153383: 12/02/14: LUT6 FPGAs and Carry Logic
153384: 12/02/15: Re: Life after XDL
153396: 12/02/15: Re: LUT6 FPGAs and Carry Logic
153400: 12/02/16: Re: LUT6 FPGAs and Carry Logic
153404: 12/02/17: Re: LUT6 FPGAs and Carry Logic
153406: 12/02/17: Re: LUT6 FPGAs and Carry Logic
153408: 12/02/17: Re: LUT6 FPGAs and Carry Logic
157154: 14/10/18: Re: Fast and slow clocks
Jan Buytaert:
59333: 03/08/15: jamplayer on WinXP ?
Jan C. =?iso-8859-1?Q?Vorbr=FCggen?=:
46703: 02/09/06: Re: Hardware Code Morphing?
jan coombs:
19304: 99/12/11: Re: Is there two-read one-write asynchronous SRAM in FPGA?
Jan Coombs:
11788: 98/09/09: Re: 22V10 programming
12848: 98/11/02: Re: Q: 3.3 V regulators suitable for XILINX - ?
13950: 99/01/05: Re: Bit-Serial Multiplier
36281: 01/11/05: Re: JTAG problem
91122: 05/10/30: Re: Anyone remember the really early Xilinx FPGAs?
96045: 06/01/28: Re: So Xilinx, is XDL and related libraries an available open source
96649: 06/02/08: Re: Microblaze using SPI flash as instruction memory
145108: 10/01/28: Re: Achronix FPGA
148100: 10/06/21: Re: Programming the Actel Smartfusion Eval Kit in Linux
148124: 10/06/22: Re: Programming the Actel Smartfusion Eval Kit in Linux
148923: 10/09/10: Re: Want to get into FPGA
151570: 11/04/20: Re: NibzX7 processor
151584: 11/04/22: Re: NibzX7 processor
151826: 11/05/21: Re: J1 forth processor in FPGA - possibility of interactive work?
153113: 11/12/05: Re: Is it possible to save the FPGA state periodically?
153721: 12/04/30: Re: Smallest GPL UART
157792: 15/03/28: Re: Intel in Talks to buy Altera
157952: 15/05/20: Re: AHDL VS. VHDL
158049: 15/07/28: Re: Finally! A Completely Open Complete FPGA Toolchain
158050: 15/07/28: Re: Finally! A Completely Open Complete FPGA Toolchain
158052: 15/07/29: Re: Finally! A Completely Open Complete FPGA Toolchain
158101: 15/08/07: Re: Is it possible to have a parameterized verilog module name in
158177: 15/09/10: Re: Why is this group so quiet?
159199: 16/09/01: Re: PALCE22v10 / GAL22v10 programming algorithms needed
159296: 16/09/26: Re: learning verilog
159310: 16/10/02: Re: learning verilog (or VHDL (or even MyHDL))
159312: 16/10/02: Re: PALCE22v10 / GAL22v10 programming algorithms ... Found?
159534: 16/12/03: Libre tools, was Re: Phrasing!
159899: 17/04/24: Re: glitching AND gate
160014: 17/05/11: Re: size lattice iCE40 config files
160071: 17/05/18: Re: Test Driven Design?
160232: 17/08/11: Re: SystemVerilog and alternatives
160272: 17/10/06: Re: Xilinx Platform cable USB and impact on linux without windrvr
160416: 18/01/17: Re: My invention: Coding wave-pipelined circuits with buffering
160425: 18/01/20: Re: My invention: Coding wave-pipelined circuits with buffering
160428: 18/01/21: Re: My invention: Coding wave-pipelined circuits with buffering
160644: 18/08/11: Re: FPGA simplest processor
160651: 18/08/16: Re: Cheaptest FPGA board for Computer Architecture
160653: 18/08/16: Re: Cheaptest FPGA board for Computer Architecture
160990: 19/01/09: Re: Can I use Verilog or SystemVerilog to write a state machine
161294: 19/03/24: Re: High-level synthesis
161299: 19/03/24: Re: High-level synthesis - MyHDL?
161346: 19/04/09: Re: Replaceme EPROM by CPLD/FPGA
161611: 20/01/08: Re: Displays - Apple Mac vs. IBM PC
161640: 20/02/07: Re: how to suppress assertion warnings in gtkwave?
161652: 20/02/14: Re: Code block in icestudio
Jan De Ceuster:
52244: 03/02/05: Re: Clock Enables
52625: 03/02/17: Re: SoC pheripheral Design Resouraces
52726: 03/02/20: Re: SoC pheripheral Design
62162: 03/10/21: Re: Running Quartus II on ReadHat Linux 9.0
62163: 03/10/21: Re: Running Quartus II on ReadHat Linux 9.0
62201: 03/10/22: Re: Running Quartus II on ReadHat Linux 9.0
62744: 03/11/06: Re: Creating a vector out of other vectors
72363: 04/08/17: Re: Spooling from FPGA to the PC
76561: 04/12/06: Re: quartus and pll
76808: 04/12/13: altera DDR core simulation with NCSim
76812: 04/12/13: Re: altera DDR core simulation with NCSim
76814: 04/12/13: Re: UART receiver
76815: 04/12/13: Re: UART receiver
76839: 04/12/14: Re: altera DDR core simulation with NCSim
76876: 04/12/15: Re: Cyclone device misteriously overheats
Jan Decaluwe:
1813: 95/09/06: Re: Altera's Max+Plus2 vhdl output, bad!
1875: 95/09/13: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
1895: 95/09/16: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
1894: 95/09/16: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
1897: 95/09/18: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
1898: 95/09/18: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
1981: 95/09/28: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
1980: 95/09/27: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
2060: 95/10/08: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
2102: 95/10/14: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
2103: 95/10/15: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
2586: 96/01/07: Re: Career value: VHDL or Verilog?
10077: 98/04/26: Re: Make a delay in Xilinx FPGAs (Help)?
23701: 00/07/05: Re: VHDL code for LFSR
92926: 05/12/09: Re: ISE = Intelligent Synthesis Expectable :-)
93038: 05/12/12: Re: ISE = Intelligent Synthesis Expectable :-)
93462: 05/12/22: Re: More beginner's verilog questions
93592: 05/12/25: Re: More beginner's verilog questions
93972: 06/01/04: [ANNOUNCE] MyHDL 0.5 released
94079: 06/01/05: Re: [ANNOUNCE] MyHDL 0.5 released
94452: 06/01/11: Re: [ANNOUNCE] MyHDL 0.5 released
99336: 06/03/23: Xilinx ISE tutorial revisited using MyHDL
99337: 06/03/23: Xilinx ISE tutorial revisited using MyHDL
99505: 06/03/25: Re: OpenSPARC released
99731: 06/03/28: Re: OpenSPARC released
99778: 06/03/29: Re: OpenSPARC released
99783: 06/03/29: Re: OpenSPARC released
101647: 06/05/04: Cordic-based Sine Computer in MyHDL
101721: 06/05/05: Re: Cordic-based Sine Computer in MyHDL
111042: 06/10/27: FPGA-based music synthesizer (with MyHDL)
118880: 07/05/05: Re: Atom HDL
118885: 07/05/05: Re: Atom HDL
126234: 07/11/17: Re: VHDL language is out of date! Why? I will explain.
126263: 07/11/18: Re: VHDL language is out of date! Why? I will explain.
126496: 07/11/25: Re: VHDL language is out of date! Why? I will explain.
126508: 07/11/26: Re: VHDL language is out of date! Why? I will explain.
126587: 07/11/28: Re: VHDL language is out of date! Why? I will explain.
127232: 07/12/14: Re: VHDL language is out of date! Why? I will explain.
127233: 07/12/15: Re: VHDL language is out of date! Why? I will explain.
137057: 08/12/21: Why MyHDL?
137067: 08/12/21: Re: Why MyHDL?
137079: 08/12/22: Re: Why MyHDL?
137127: 08/12/24: Re: which HLL for HPC applications implementation?
137340: 09/01/09: [ANNOUNCE] MyHDL 0.6 released
138780: 09/03/10: Integer arithmetic in HDLs
140655: 09/05/21: Re: Sigasi Public Beta: future of VHDL design
140830: 09/05/27: Re: Online tool that generates parallel CRC and Scrambler
140859: 09/05/27: Re: Online tool that generates parallel CRC and Scrambler
141957: 09/07/19: Re: Do you prefer paper or plastic... er, I mean paper or e-books?
142862: 09/09/04: Re: Choice of Language for FPGA programming
144041: 09/11/09: Re: free software/open source projects and FPGA?
144076: 09/11/10: [Announce] Jan on HDL Design
144092: 09/11/11: Re: Jan on HDL Design
145550: 10/02/14: Re: VHDL vs Verilog
147036: 10/04/10: Re: I'd rather switch than fight!
147037: 10/04/10: Re: I'd rather switch than fight!
147047: 10/04/12: Re: I'd rather switch than fight!
147125: 10/04/14: Re: I'd rather switch than fight!
147151: 10/04/15: Re: I'd rather switch than fight!
147188: 10/04/17: Re: I'd rather switch than fight!
147230: 10/04/19: Re: I'd rather switch than fight!
147249: 10/04/20: Re: I'd rather switch than fight!
147261: 10/04/21: Re: I'd rather switch than fight!
147295: 10/04/22: Re: I'd rather switch than fight!
147305: 10/04/22: Re: I'd rather switch than fight!
147307: 10/04/22: Re: I'd rather switch than fight!
147318: 10/04/22: Re: I'd rather switch than fight!
147342: 10/04/23: Re: I'd rather switch than fight!
147362: 10/04/23: Re: I'd rather switch than fight!
147395: 10/04/26: Re: I'd rather switch than fight!
149883: 10/11/30: Re: Brain Cramps...
149903: 10/12/01: Re: Brain Cramps...
149929: 10/12/02: Re: Brain Cramps...
150096: 10/12/13: Re: Brain Cramps...
150108: 10/12/14: Re: Brain Cramps...
150169: 10/12/24: [ANNOUNCE] MyHDL 0.7
150212: 11/01/01: Re: I Give Up!
150388: 11/01/15: Re: Verilog Book for VHDL Users
150389: 11/01/15: Re: Verilog Book for VHDL Users
152501: 11/08/29: A free lunch
152514: 11/08/30: Re: A free lunch
152515: 11/08/30: Re: A free lunch
153836: 12/06/01: Re: PRNG
153946: 12/07/02: Re: The definition of comnatorial prcess?
153948: 12/07/02: Re: The definition of comnatorial prcess?
153958: 12/07/03: Re: The definition of comnatorial prcess?
154535: 12/11/25: VHDL expert puzzle
154541: 12/11/25: Re: VHDL expert puzzle
154547: 12/11/26: Re: VHDL expert puzzle
154553: 12/11/27: Re: VHDL expert puzzle
154555: 12/11/27: Re: VHDL expert puzzle
154557: 12/11/28: Re: VHDL expert puzzle
154563: 12/11/28: Re: VHDL expert puzzle
154575: 12/11/29: Re: VHDL expert puzzle
154580: 12/11/29: Re: VHDL expert puzzle
154591: 12/11/30: Re: VHDL expert puzzle
154592: 12/11/30: Re: VHDL expert puzzle
154593: 12/11/30: Re: VHDL expert puzzle
154597: 12/11/30: Re: VHDL expert puzzle
Jan Gray:
501: 94/12/11: homebuilt processors using FPGAs (long)
888: 95/03/22: Re: FPGA accelerated engines for volume rendering
1973: 95/09/27: Re: FPGA for a 20k gates micro-controller
2114: 95/10/17: "XACT 5.1 is incompatible with everything!!!!!!!!" -- a mild exaggeration, plus some Win95 hints
2136: 95/10/19: Re: "XACT 5.1 is incompatible with everything!!!!!!!!" -- a mild exaggeration, plus some Win95 hints
2203: 95/11/01: Re: small superscalar design ?
2204: 95/11/01: Re: small superscalar design ?
2392: 95/11/28: XBLOX vs. "CNets", lfsr dividers, etc.
2707: 96/01/26: Re: HowTo access a SRAM with a XC4000
2799: 96/02/09: Re: FPGA density
2800: 96/02/09: Re: Performance Benchmarks: Emulating FPGAs Using General Purpose Processors
2801: 96/02/09: Repost: Performance Benchmarks: Emulating FPGAs Using General Purpose Processors
2849: 96/02/16: Re: New Reconfigurable Computing Threads. -- Java machines
3180: 96/04/19: On FPGAs as PC coprocessors
3263: 96/05/06: On FPGAs as PC coprocessors [rererepost]
3350: 96/05/17: considering a new XC4010E/XC4013E proto board with RAM
4397: 96/10/24: Re: Has anyone ever used a C -> Xilinx netlister?
5071: 97/01/20: Re: advice request: CPUs vs. FPGAs again
5080: 97/01/21: Re: FPGA with SRAM
5688: 97/03/07: Re: Xilinx 4002 RAM Question
6309: 97/05/14: Re: Cheap way to develop for FPGAs?
6441: 97/05/24: Xilinx future features?
6561: 97/06/03: Re: What is M1?
6562: 97/06/03: Re: New Reconfigurable Computing newsgroup?
7673: 97/10/02: FPGA multiprocessors
7716: 97/10/07: Re: FPGA multiprocessors => vs. uniprocessors
7717: 97/10/07: Re: FPGA multiprocessors
7718: 97/10/07: Re: FPGA multiprocessors
7723: 97/10/07: Re: FPGA multiprocessors => vs. uniprocessors
7771: 97/10/14: Re: FPGA based CPU ideas, and novel extensions => distributed RAM and Altera CPUs
9550: 98/03/22: Re: Dual port, new Altera FLEX 10KE EABs
9573: 98/03/24: Re: Dual port, new Altera FLEX 10KE EABs
9999: 98/04/21: Re: Could you help me save CLB's?
10449: 98/05/19: Re: Minimal ALU instruction set.
10506: 98/05/25: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
11083: 98/07/17: Re: Floorplanning Intro?
11106: 98/07/19: Re: Too much advertising in this news group?
11458: 98/08/16: RAMBUS for FPGAs -- was Re: Why is Intel *really* pushing rambus into desktop PCs ?
11748: 98/09/06: Re: Altera 10K20 Register File Implementation??
11814: 98/09/10: Re: Xilinx Spartan vs. 4K series
11975: 98/09/22: Re: Efficient max-function architecture?
11987: 98/09/22: Re: Efficient max-function architecture? -- "parallel bitwise max"
12119: 98/09/30: Re: Efficient max-function architecture? -- "parallel bitwise max"
12123: 98/09/30: Re: Efficient max-function architecture? -- "parallel bitwise max"
12218: 98/10/05: Re: info requested for design course
12374: 98/10/10: Re: Help Desperately Needed with Altera Microprocessor Design.
12782: 98/10/29: Re: Q: Configure FPGA from an ISA bus?
13327: 98/11/25: Re: Combining busses Xilinx
13332: 98/11/25: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
14755: 99/02/15: FPGA array computers
15149: 99/03/09: Re: micro computer using Xilinx
15729: 99/04/10: Re: FPGA vs CPLD? Any Experts out there?
15741: 99/04/11: Re: FPGA vs CPLD? Any Experts out there?
15763: 99/04/12: Re: FPGA vs CPLD? Any Experts out there?
15768: 99/04/12: Re: FPGA vs CPLD? Any Experts out there?
15880: 99/04/18: Re: Forth Processor
16322: 99/05/15: Re: How synthesize tools concern with size of the design?
16440: 99/05/21: The Economist article: "Hardware goes soft"
16952: 99/06/18: Re: Read/Writes to memories/register files for PIC core
16964: 99/06/21: Re: Read/Writes to memories/register files for PIC core
16982: 99/06/22: Re: Question: Does FPGA Express 3.2 support RPMs?
16983: 99/06/22: Xilinx "Virtex Configuration Architecture Advanced Users' Guide" appears
17148: 99/07/03: Re: Floating point on fpga, and serial FP adders
17185: 99/07/07: Alto in an FPGA (was CPU's directly executing HLL's)
17406: 99/07/25: Re: Microcomputer buses for use inside FPGA/ASIC devices?
17407: 99/07/25: Re: Microcomputer buses for use inside FPGA/ASIC devices?
17424: 99/07/27: Re: Microcomputer buses for use inside FPGA/ASIC devices?
17558: 99/08/10: Re: Emulating a transputer on FPGA
17852: 99/09/14: Re: Relative Location attribute
18442: 99/10/24: Re: xilinx foundation: bit_gen warning becasue of pullUps
19246: 99/12/08: Re: Is there two-read one-write asynchronous SRAM in FPGA?
19483: 99/12/24: regular expression matching and parsing in FPGAs (was chess...)
19839: 00/01/14: Re: fastest 32 bit RISC
19850: 00/01/14: Re: fastest 32 bit RISC
21357: 00/03/20: "Building a RISC System in an FPGA" magazine series, and XSOC/xr16 RISC SoC
21750: 00/03/30: Re: VGA interface and VHDL
22040: 00/04/14: XSOC news: articles, Verilog, talk
22800: 00/05/25: Re: 8087 in FPGA?
23638: 00/07/04: on arbitrary m-cycle n-bit lfsrs
23654: 00/07/04: Altera and Xilinx processor core announcements
23684: 00/07/05: Re: on arbitrary m-cycle n-bit lfsrs
23830: 00/07/12: C++/Java generators vs. synthesizers
23851: 00/07/12: Re: C++/Java generators vs. synthesizers
23867: 00/07/13: Re: C++/Java generators vs. synthesizers
24383: 00/08/06: help -- of RAMs, FFs, latches, inverted clocks, and other curiosities
24665: 00/08/16: Re: what does 0.35 micron mean
24813: 00/08/19: Re: Xilinx Student Edition Floorplanning
24882: 00/08/21: Re: Arg! 8051 - 6502 and friends
24883: 00/08/21: hard FPGA CPU cores do not moot soft cores
25065: 00/08/25: Re: help -- of RAMs, FFs, latches, inverted clocks, and other curiosities
25077: 00/08/25: Re: help -- of RAMs, FFs, latches, inverted clocks, and other curiosities
25086: 00/08/25: Re: help -- of RAMs, FFs, latches, inverted clocks, and other curiosities
25107: 00/08/26: Re: help -- of RAMs, FFs, latches, inverted clocks, and other curiosities
25386: 00/09/09: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25388: 00/09/09: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25879: 00/09/24: Re: Xilinx Student Edition 2.1i with "Digital Design:Principles and Practices"
26057: 00/10/02: "Xilinx Adds FPGA Support to Free Web Design Tools"
26064: 00/10/02: Re: multi-input adders in virtex ?
26084: 00/10/03: Re: JVM processor
26085: 00/10/03: Re: JVM processor
26113: 00/10/04: Re: JVM processor
26116: 00/10/04: Re: JVM processor
26243: 00/10/09: Re: 68000 vhdl model
26405: 00/10/15: 35 CLB 8-bit MCU
26556: 00/10/20: Re: How safe is the algorithm implemented with FPGA?
26996: 00/11/07: Re: ISO C -> VHDL translator, prefer open source
27064: 00/11/09: FPSLIC
27140: 00/11/12: Virtex circuit tricks -- add/mux in one LUT per bit
27167: 00/11/13: Re: XC4000 maps better than Spartan2
27212: 00/11/15: Re: Job posting info
27258: 00/11/16: 8-way MIMD multiprocessor in an XCV50E
27269: 00/11/16: Re: can FPGA perform float point calculaton?
27389: 00/11/20: Re: 8-way MIMD multiprocessor in an XCV50E
27613: 00/11/30: Re: Reverse-engineering FPGA's
28285: 01/01/05: Re: Nondeterministic FSMs in hardware?
28324: 01/01/06: Re: Update on nondeterministic FSMs in hardware
28441: 01/01/12: Re: Stereo vision on Virtex
28677: 01/01/20: Re: Synplicity newsgroup?
28752: 01/01/23: Re: Designing fractional counters?
28874: 01/01/26: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip multiprocessor!
28882: 01/01/27: Re: RAM reset question - Xilinx Virtex
28883: 01/01/27: Re: RAM reset question - Xilinx Virtex
28966: 01/01/31: Re: Xilinx fast carry counter question
29060: 01/02/04: Re: FPGA Conferences
29103: 01/02/06: Re: switching Matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29174: 01/02/08: on making it too convenient to download PDFs
29259: 01/02/11: Re: OT: IEEE & Floating point
29266: 01/02/11: Re: Wired-or on Virtex FPGAs
29268: 01/02/12: Re: New DES/AES (RIJNDAEL) Cores
29564: 01/02/27: Re: Xilinx tools: RLOC hierarchy with HDL design?
29580: 01/02/27: Re: Xilinx tools: RLOC hierarchy with HDL design?
29943: 01/03/19: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30027: 01/03/20: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30068: 01/03/22: Re: reduced precision floating point
30279: 01/03/30: Re: VIRTEX BLOCK RAM
30460: 01/04/09: MicroBlaze
30463: 01/04/09: Re: MicroBlaze
30537: 01/04/12: Re: Is there any free processor core for vertex series?
30763: 01/04/27: Re: Setting Pins High
32599: 01/07/02: Re: xr16vx: a GPL 16-bit xr16 microcontroller in JHDL
33752: 01/08/03: Re: 4 (8) bit Microporcessor Implementation
33882: 01/08/07: Re: Spartan II and asynchronous memory interface
34021: 01/08/11: Re: Reconfigurable Computational Accelerator
35444: 01/10/04: Re: Barrel Shifter
35677: 01/10/12: Re: High level synthesis will never work well :)
35748: 01/10/16: Re: System Gates
35856: 01/10/20: Re: I search a free 8086 core...
36894: 01/11/23: Re: how to imply tristate buffer in APEX20K
37028: 01/11/28: Re: SpartanIIE
37428: 01/12/10: Re: where is designed FPGA for apple II computer...?
38396: 02/01/13: Re: Homebrew computers using FPGA?
38763: 02/01/24: Re: www.fpga.org
38984: 02/01/29: Re: tri-state vs. Mux
40106: 02/02/27: RAM32X1S, Virtex-II, 4.1i PAR travails
40346: 02/03/05: Xilinx announces Virtex-II Pro is shipping
40831: 02/03/16: Re: Difference between Virtex-II(E) und Virtex-E
40833: 02/03/16: Re: Difference between Virtex-II(E) und Virtex-E, correction
40902: 02/03/17: Re: Difference between Virtex-II(E) und Virtex-E
41308: 02/03/25: Re: question on LFSR
41322: 02/03/25: Re: question on LFSR
41541: 02/04/01: Re: Laying out the design
41568: 02/04/02: Re: powerpc in virtex2pro
41631: 02/04/03: Re: powerpc in virtex2pro
41764: 02/04/07: Re: powerpc in virtex2pro
42552: 02/04/26: Re: Newbie Advice Please
42599: 02/04/28: Re: Xilinx Easypath- Selling parts with known defects
42831: 02/05/03: Re: Xilinx 2GB limit... something has to be done
42847: 02/05/04: Re: Xilinx 2GB limit... something has to be done
43503: 02/05/22: Re: fpga cpu
46020: 02/08/14: Re: transputers
46029: 02/08/14: Re: Xilinx tools: which one? Esp. schematic
46092: 02/08/17: Re: Xilinx tools: which one? Esp. schematic
46484: 02/08/31: Virtex/E/2/2P area efficient addmux, reiterating PAR timing modeler enhancement request
46508: 02/09/01: Re: Virtex/E/2/2P area efficient addmux, reiterating PAR timing modeler enhancement request
46518: 02/09/02: Verilog 2001 < VHDL
46581: 02/09/03: MAP problem: Trivial RPM fails
46582: 02/09/03: Warning: Xilinx 4.2i + Windows 2000 SP3 => blue screen of death
46583: 02/09/03: Re: Warning: Xilinx 4.2i + Windows 2000 SP3 => blue screen of death
46592: 02/09/03: Re: Warning: Xilinx 4.2i + Windows 2000 SP3 => blue screen of death
46605: 02/09/04: Re: Any resource about MCU and DSP
46837: 02/09/09: Re: minimalist FPGA system
46941: 02/09/12: Re: Virtex/E/2/2P area efficient addmux, reiterating PAR timing modeler enhancement request
47260: 02/09/21: Re: RPM zippering redux
47316: 02/09/23: Re: Altera Cyclone low-cost FPGA chips?
47396: 02/09/24: RPM_GRID (was MAP problem: Trivial RPM fails)
47540: 02/09/27: Why no ROC for Xilinx Verilog sim and synthesis?
47555: 02/09/28: Re: Why no ROC for Xilinx Verilog sim and synthesis?
47560: 02/09/28: Re: Why no ROC for Xilinx Verilog sim and synthesis?
47709: 02/10/02: Re: Help for Altera's FPGAs' pinout
47763: 02/10/03: Re: TCP/IP in FPGA
47764: 02/10/03: Re: TCP/IP in FPGA
47818: 02/10/04: Re: TCP/IP in FPGA
47819: 02/10/04: Re: TCP/IP in FPGA
47820: 02/10/04: Re: TCP/IP in FPGA
47827: 02/10/04: Re: TCP/IP in FPGA
48388: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48398: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48513: 02/10/18: Re: Xilinx microblaze vs. picoblaze
48515: 02/10/18: Re: Floorplanner RPM. How to use it?
48522: 02/10/18: Re: Floorplanner RPM. How to use it?
48610: 02/10/21: Re: Newbie Questions - Jan Gray XSOC
48736: 02/10/23: Re: More Newbie Questions - What teaching resources
48891: 02/10/25: Re: Xilinx microblaze vs. picoblaze
49162: 02/11/03: Re: 16-bit FGPA CPU core (commercial)
49163: 02/11/03: Re: 16-bit FGPA CPU core (commercial)
49164: 02/11/03: Re: 16-bit FGPA CPU core (commercial)
49276: 02/11/07: Project Navigator Console thumb behavior (was Re: Xilinx, where is DesignManager in ISE 5.1 ?)
49333: 02/11/09: Re: Xilinx LUT-based FPGAs
49354: 02/11/10: Re: LU-decomposition
49420: 02/11/11: Re: LU-decomposition
49463: 02/11/12: Re: LU-decomposition
49465: 02/11/12: Re: HDL vs RTL
50009: 02/11/28: Xilinx XC2S400E and XC2S600E
50378: 02/12/09: Re: Tiny Forth Processors
51561: 03/01/16: Re: 200K gates FPGA for GPU
52979: 03/02/27: Re: picoChip - DSP as fast as an FPGA - is this for real
53752: 03/03/21: Re: Using FPGAs as coprocessors in a PC
54152: 03/04/03: Re: Internal net names on ISE Foundation
54156: 03/04/03: Re: Internal net names on ISE Foundation
55746: 03/05/18: Re: smallest embedded cpu....and the most pain?
57650: 03/07/03: Re: Parallel processing
61256: 03/10/01: Re: FPGA implementation of a lexer and parser - feasible?
61368: 03/10/02: Re: Graphics rendering -- use a BRAM line buffer
69851: 04/05/22: Re: Never right, always room for improvement
70131: 04/06/04: Re: tri-state in altera and xilinx
70132: 04/06/04: Re: tri-state in altera and xilinx
70138: 04/06/04: Re: tri-state in altera and xilinx
70191: 04/06/08: V4 teaser
70192: 04/06/08: Re: V4 teaser, correction
72513: 04/08/22: Re: XST synthesis
73040: 04/09/11: Re: Need some help with some technical claims...
74069: 04/10/03: Re: spartan-3 sram
74376: 04/10/09: Re: add/sub 2:1 mux and ena in a single LE (Cyclone)
75641: 04/11/11: Re: Internal architecture of lut
76297: 04/11/30: Re: lowest-cost FPGA
76560: 04/12/06: Re: internal tristates and busses
77637: 05/01/13: Re: (d)ram interface
78033: 05/01/23: Re: Master's Project
78749: 05/02/07: Re: WARNING:Xst:382 - Why so many?
81003: 05/03/16: Re: Register file with LUTs in a SPARTAN3
81363: 05/03/22: Re: PowerPC soft-core?
81375: 05/03/22: Re: PowerPC soft-core?
81403: 05/03/23: Re: PowerPC soft-core?
81426: 05/03/23: Re: PowerPC soft-core?
81453: 05/03/24: Re: PowerPC soft-core?
84822: 05/05/28: Re: Control asynchronous SRAM like synchronous SRAM
117216: 07/03/27: Re: RISC implementation questions
117219: 07/03/27: Re: RISC implementation questions
117668: 07/04/06: Re: Transition from ASIC to FPGA
117689: 07/04/07: Re: Transition from ASIC to FPGA
Jan Guffens:
22667: 00/05/17: Re: c -> FPGA netlist compiler
27001: 00/11/07: Re: ISO C -> VHDL translator, prefer open source
Jan Hansen:
104886: 06/07/08: Re: Can I use all 18bits of a BlockRAM?
104887: 06/07/08: Re: Fastest platform to run ISE?
104904: 06/07/09: SP305- PROM configuration
105022: 06/07/12: Re: Programming the Spartan-3E Starter Kit using Linux?
105049: 06/07/12: Re: Development Boards -Your chance to suggest features
105441: 06/07/23: Re: How to print a state flow graph for a state machine using Xilinx ISE or ModelSim
Jan Humme:
5456: 97/02/17: Xilinx or Altera?
5463: 97/02/18: Re: Xilinx or Altera?
5464: 97/02/18: Re: Xilinx or Altera?
5481: 97/02/19: Re: Xilinx or Altera?
Jan Kindt:
28942: 01/01/30: Re: C2VHDL
29030: 01/02/02: Re: Xilinx question
30444: 01/04/08: Re: Spartan II Configuration
30480: 01/04/10: Re: VHDL falling edge in Xilinx Foundation...
59916: 03/09/01: BlockRam @ 333MHz
60250: 03/09/09: Re: VGA display
Jan Krakora:
120590: 07/06/11: Re: Problems to simulate (behavioural) in XPS
Jan Kubuschok:
2266: 95/11/15: Xilinx XACT Windows Version
Jan Lellmann:
22855: 00/05/27: Buying FPGAs in Germany
Jan Losansky:
67796: 04/03/19: Spartan-3 DSL-KIT
69250: 04/05/03: XILINX System Generator "fatal error"
69274: 04/05/04: Re: XILINX System Generator "fatal error"
83229: 05/04/26: Memec JTAG cable IJC-3
Jan Lucas:
152366: 11/08/12: Re: Help needed to emulate a microcontroller.
Jan Maris:
2504: 95/12/20: Altera related Qs.
Jan Martin:
33478: 01/07/27: Re: 3.3i service pack 8
33567: 01/07/30: Re: 3.3i service pack 8
40651: 02/03/12: Re: Mystery two wire interface, or am I being dense?
Jan Martin Wagenaar:
12749: 98/10/27: Re: DynaText **!?!?
12750: 98/10/27: Re: DynaText **!?!?
Jan Mikkelsen:
5373: 97/02/11: Re: DES Challenge
20953: 00/02/29: Re: Extremely fault tolerant strategies
Jan Muska:
6605: 97/06/05: NEED YOUR HELP - IN RETURN COULD WIN FREE ANTI-VIRUS SOFTWARE
Jan Panteltje:
23163: 00/06/16: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
53943: 03/03/28: Question about case statement in XilinX webpack
53982: 03/03/29: More xilinx webpack verilog questions: always @(clock) legal?
53986: 03/03/30: Re: More xilinx webpack verilog questions: always @(clock) legal?
53987: 03/03/30: Re: More xilinx webpack verilog questions: always @(clock) legal?
53988: 03/03/30: Re: Question about case statement in XilinX webpack
55235: 03/05/01: Some general questions about WebPack and debugging and logic in FPGA and layout in the chip and...
55275: 03/05/02: I want a 800 k gates FPGA in 40 pin DIL
55294: 03/05/02: Re: I want a 800 k gates FPGA in 40 pin DIL
55317: 03/05/03: Re: I want a 800 k gates FPGA in 40 pin DIL
55318: 03/05/03: Re: I want a 800 k gates FPGA in 40 pin DIL
55319: 03/05/03: Re: I want a 800 k gates FPGA in 40 pin DIL
55519: 03/05/11: Re: I want a 800 k gates FPGA in 40 pin DIL
55520: 03/05/11: Confused about timing report in clock doubler in XST
55549: 03/05/12: OK I am pissed off with Xilinx webpack.
55596: 03/05/13: Re: OK I am pissed off with Xilinx webpack.
55646: 03/05/14: Re: OK I am pissed off with Xilinx webpack.
55718: 03/05/16: Re: OK I am pissed off with Xilinx webpack.
55829: 03/05/20: Re: OK I am pissed off with Xilinx webpack.
55894: 03/05/22: Re: Xilinx : Tools
57962: 03/07/10: Re: Fpga design with multiple audio rate (44, 48khz ...)
59656: 03/08/25: Re: Interfacing to pc parallel port?
59758: 03/08/27: Re: Free FPGA samples anywhere?
60078: 03/09/04: Re: Input comparator
60285: 03/09/09: Re: Impact error
60335: 03/09/10: Re: Crystal Input to FPGA
60512: 03/09/15: Re: fpga +cpu + wireless
60553: 03/09/16: Re: Digilent board
60574: 03/09/16: Re: fpga +cpu + wireless
60879: 03/09/24: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
61087: 03/09/27: Re: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
61166: 03/09/29: Re: WARNING do not use your real email address in USENET postings!
61307: 03/10/01: Re: Frustrations with Marketing
61308: 03/10/01: Re: USB Core (Japanese Version)
62996: 03/11/12: Trying to digitize video with CTT differential input, but webpack wont't cooperate...:-)
63012: 03/11/12: Trying to digitize video with CTT differential input, but webpack wont't cooperate...:-)
63062: 03/11/13: Re: Trying to digitize video with CTT differential input, but webpack wont't cooperate...:-)
63064: 03/11/13: Re: Frequency Doubler - VHDL/Verilog
63110: 03/11/15: Do I need to connect all Vref in a bank together?
63119: 03/11/15: More basic questions about Spartan 2 IOB
63130: 03/11/15: Re: More basic questions about Spartan 2 IOB
63183: 03/11/17: Re: Do I need to connect all Vref in a bank together?
63238: 03/11/18: Re: Do I need to connect all Vref in a bank together?
63239: 03/11/18: Re: Do I need to connect all Vref in a bank together?
63246: 03/11/18: Re: Do I need to connect all Vref in a bank together?
63252: 03/11/18: Re: Do I need to connect all Vref in a bank together?
63393: 03/11/20: Re: 400 Mb/s ADC
63685: 03/11/29: Re: Digilent Inc.
63716: 03/12/01: Re: about digilent board
64035: 03/12/12: Question about filters and verilog etc..
64043: 03/12/13: Re: Question about filters and verilog etc..
64052: 03/12/14: Re: advantages of ethernet MAC ip core
64251: 03/12/22: A simple horizontal frequency doubler PLL for TV line doubler.
65296: 04/01/23: Re: Spirit on Mars
65400: 04/01/27: Re: Image sensor?
65840: 04/02/07: Re: Pricing, 101
65903: 04/02/09: Re: Pricing, 101
66774: 04/02/26: Re: SmartMedia writer (implments using VHDL)....
66866: 04/02/28: Re: SmartMedia writer (implments using VHDL)....
67694: 04/03/17: Re: FPGA protyping board (Avnet or others)
68140: 04/03/27: Re: study verilog or vhdl?
68218: 04/03/30: Re: Is there any Sync separator IP(Intellectual property) exists?
68225: 04/03/30: Re: Is there any Sync separator IP(Intellectual property) exists?
68230: 04/03/30: Re: Is there any Sync separator IP(Intellectual property) exists?
68232: 04/03/30: Re: study verilog or vhdl?
69419: 04/05/10: Re: SAA7111 YUV
70016: 04/05/27: Re: Good Devlopement Board for learning
70359: 04/06/14: 90nm Xilinx FPGA?
70460: 04/06/17: Re: Xilinx ParallelCable IV vs. Linux
70463: 04/06/17: Re: Xilinx ParallelCable IV vs. Linux
70473: 04/06/17: Re: Xilinx ParallelCable IV vs. Linux
70619: 04/06/22: Re: JTAG - XC2S200E-PQ208
81022: 05/03/16: Re: Cheap 100mbit/s ethernet MAC/PHY daughterboard ?
83443: 05/04/29: Re: Patent issues in implementing embedded fpgas
84279: 05/05/16: Re: FPGA design under Mac OS X ?
85794: 05/06/16: Re: Idea exploration - Image stabilization by means of software.
86295: 05/06/24: Re: Xilinx webshop
87486: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
88906: 05/08/31: Re: LCD Interface
90643: 05/10/18: Re: Data2Mem usage - help required
90846: 05/10/22: Re: .dat to .bit
90888: 05/10/24: Re: a few questions
90944: 05/10/25: Re: a few questions
90978: 05/10/26: Re: 7.1i on Linux installation saga
91259: 05/11/02: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91383: 05/11/04: Re: icarus verilog
91394: 05/11/04: Re: icarus verilog
91480: 05/11/07: Re: icarus verilog
91482: 05/11/07: Re: Verilog Editor.
91525: 05/11/08: Re: Verilog Editor.
91661: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
92048: 05/11/21: Re: Sounds or other means to indicate end of compilation in Xilinx ISE
92869: 05/12/08: Re: FPGA development board with digital image camera
93075: 05/12/13: Re: mixed signal flash FPGAs launched!
93076: 05/12/13: Re: mixed signal flash FPGAs launched!
93278: 05/12/18: Re: Altera based Video development board
93768: 05/12/30: Re: Power Optimization: can the routing and placement really save power?
93892: 06/01/03: Re: CPU86 (Intel 8086) VHDL now available (thanks to HT-LAB !)
93999: 06/01/04: Re: CPU86 (Intel 8086) VHDL now available (thanks to HT-LAB !)
94365: 06/01/10: Downloading WebPack-8.1, server maxes out at 30 kB / second (= > 7 hours)?
94375: 06/01/10: Re: Downloading WebPack-8.1, server maxes out at 30 kB / second (= > 7 hours)?
94539: 06/01/13: Re: FPGA Journal Article
94676: 06/01/16: Re: Don't even get me started on lead,
95002: 06/01/20: Re: Xilinx padding LC numbers, how do you feel about it?
95190: 06/01/21: Re: Irrelevant, stupid, racist, and worse.
95201: 06/01/21: Re: FPGA-Programmable power supply
95669: 06/01/25: Re: encryption
95687: 06/01/25: Re: encryption
95830: 06/01/26: Re: open source fpga programmer programs
96105: 06/01/30: Re: Xilinx Legal
96141: 06/01/30: Re: Xilinx Legal
96972: 06/02/14: Re: digital logic library by 74xxxx part number?
97236: 06/02/19: Re: help with VGA timings
97317: 06/02/20: Re: help with VGA timings
97498: 06/02/23: Re: Input stage for VHF frequency counter in an FPGA?
97599: 06/02/24: Re: Combinatorial Division?
97693: 06/02/26: Re: fpga to 5v ttl logic
97763: 06/02/27: Re: Combinatorial Division?
97788: 06/02/27: Re: Combinatorial Division?
97789: 06/02/27: Re: Combinatorial Division?
97790: 06/02/27: Re: Combinatorial Division?
97853: 06/02/28: Re: FPGA communication, I2C and DAC
98526: 06/03/12: Have webpack-81i running on grml Linux, rewrote ppcableIII jtag driver for Digilent to use direct io.
98585: 06/03/13: Re: Have webpack-81i running on grml Linux, rewrote ppcableIII jtag driver for Digilent to use direct io.
98659: 06/03/14: Re: fpga to 5v ttl logic
98854: 06/03/17: Re: Where are FPGA heading?
99126: 06/03/20: Re: ignore thread
99147: 06/03/20: Re: FPGA FIR advice
99148: 06/03/20: Re: Xilinx programming cable; Linux notebook w/o parallel port; Am I doomed?
99499: 06/03/25: I am a bit stuck with error INTERNAL_ERROR:Xst:cmain.c:3068:1.158.10.1
99543: 06/03/26: Re: XST takes unusually long
99601: 06/03/27: Re: Altera web site inaccessible
99629: 06/03/27: Re: Altera web site inaccessible
99694: 06/03/28: Re: Altera web site inaccessible
99737: 06/03/28: Re: Altera web site inaccessible
100285: 06/04/06: Re: Xilinx Schematic Entry
100380: 06/04/07: Re: Accessing compact flash?????????
100656: 06/04/14: Re: Counting bits
100669: 06/04/15: Re: Counting bits
100699: 06/04/16: Re: Where is the xilinx online store gone?
100731: 06/04/17: Re: Which is the best way to measure low frequencies?
101301: 06/04/28: DRC has announced its newest FPGA that drops into AMD's Socket 940
101444: 06/05/01: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101893: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
101929: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
102096: 06/05/10: Re: Quartus II 6.0 available
102232: 06/05/12: Re: JTAG tutorial
102564: 06/05/17: Re: disappointing 550Mhz performance of V5 DSP slices
102582: 06/05/17: Re: disappointing 550Mhz performance of V5 DSP slices
102587: 06/05/17: Re: disappointing 550Mhz performance of V5 DSP slices
102590: 06/05/17: Re: disappointing 550Mhz performance of V5 DSP slices
103062: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
103063: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
103068: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
103072: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
103094: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
103149: 06/05/26: Re: ISE sends sensitive information to Xilinx site!
103244: 06/05/29: Re: ISE sends sensitive information to Xilinx site!
103541: 06/06/05: Re: Webpack larger than CDs
104842: 06/07/07: Re: Chaos in FF metastability
104967: 06/07/11: Re: High-speed DAC/ADC with FPGA
104971: 06/07/11: Re: High-speed DAC/ADC with FPGA
105088: 06/07/13: Re: Programming the Spartan-3E Starter Kit using Linux?
105167: 06/07/16: Re: An idea for a product (FPGA/ASIC based)
105524: 06/07/25: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105531: 06/07/25: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105753: 06/07/31: Re: Low Cost FPGA Charge Pump Power supply
107191: 06/08/25: Re: high level languages for synthesis
107233: 06/08/25: Re: high level languages for synthesis
107256: 06/08/25: Re: high level languages for synthesis
107331: 06/08/26: Re: high level languages for synthesis
107486: 06/08/29: Re: high level languages for synthesis
107729: 06/08/31: Re: Open-source CableServer for Impact (no more need for Jungo driver on Linux)
107734: 06/08/31: Re: Open-source CableServer for Impact (no more need for Jungo driver on Linux)
108367: 06/09/09: simplyrisc-s1 free core
108699: 06/09/15: Re: Linear Interploation Algorithms
110596: 06/10/18: Re: FIR filter fpga help
110611: 06/10/18: Re: FIR filter fpga help
112435: 06/11/22: Re: CORDIC FM Demodulation
112440: 06/11/22: Re: CORDIC FM Demodulation
112445: 06/11/22: Re: CORDIC FM Demodulation
112446: 06/11/22: Re: CORDIC FM Demodulation
112693: 06/11/27: Re: CORDIC FM Demodulation
114721: 07/01/23: Re: Surface mount ic's
114783: 07/01/24: Re: Surface mount ic's
114930: 07/01/26: Webpack-9.1 working on debian / grml
115018: 07/01/29: Re: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2)
115019: 07/01/29: Re: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2)
115401: 07/02/09: Re: ISE 9.1 Installation crash SuSE 10.2
117184: 07/03/26: Re: Where is Open Source for FPGA development?
117518: 07/04/03: Re: Help with a face recognition system
117536: 07/04/03: Re: Help with a face recognition system
117575: 07/04/04: Re: Help with a face recognition system
118252: 07/04/20: Re: Free Hardware
118257: 07/04/20: Re: Free Hardware
118754: 07/05/03: Re: Video scaler for Spartan 3E?
120958: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120961: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120971: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120972: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120980: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120986: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
121739: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121753: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
139427: 09/03/29: Re: added jitter on FPGAs
142964: 09/09/10: An email from Altera
154980: 13/03/14: The Raspberry Pi JTAG programmer
156075: 13/11/22: Re: microZed adventures
156088: 13/11/22: Re: microZed adventures
156206: 14/01/17: Re: my first microZed board
156213: 14/01/17: Re: my first microZed board
156221: 14/01/18: Re: my first microZed board
156497: 14/04/11: Re: on-chip bypass caps
157982: 15/06/10: Re: PCIe card with FPGA and DAC
161366: 19/06/13: Re: bare-metal ZYNQ
161374: 19/06/13: Re: bare-metal ZYNQ
161380: 19/06/14: Re: bare-metal ZYNQ
161382: 19/06/15: Re: bare-metal ZYNQ
Jan Pech:
33148: 01/07/18: Re: Spartan2XC2S30 vs ACEXEP1K30
34403: 01/08/23: Re: DRAM burst mode
34426: 01/08/24: Spartan-II & clock
34431: 01/08/24: Re: Spartan-II & clock
34508: 01/08/28: Re: Spartan-II & clock
34519: 01/08/28: Re: Orcad Symbol
34886: 01/09/13: Block RAM initialization
34910: 01/09/13: Re: Block RAM initialization
35771: 01/10/17: Re: Recommended Newsgroup
35814: 01/10/18: Re: Firewire chipset
35910: 01/10/23: New Spartan-II Evaluation Board
38470: 02/01/15: Re: RS232 on Atmel ATSTK40 board
39283: 02/02/05: Re: FPGA vs GAL : Lattice
39929: 02/02/22: Re: Linux tools
47647: 02/10/01: iMPACT in WebPACK 5.1
48176: 02/10/12: Re: where can I find the FAQs for this news group???
48182: 02/10/13: Re: where can I find the FAQs for this news group???
48927: 02/10/27: Re: A PCI Data Aqcuisition Card Design
48937: 02/10/27: Re: A PCI Data Aqcuisition Card Design
49208: 02/11/05: WebPACK 5.1 SP2
49217: 02/11/05: Re: WebPACK 5.1 SP2
49248: 02/11/06: Re: webpack 5.1 under w2k
49713: 02/11/19: Re: Free FPGA Development Board
51881: 03/01/24: Re: Problems with "impact.exe" from ISE webpack 5.1
53069: 03/03/03: Re: FPGA demo board schematic
85040: 05/06/03: ISE under Linux: 32 vs 64 bits
120174: 07/06/02: Re: Xilinx OPB External Memory Controller
120199: 07/06/03: Re: Xilinx OPB External Memory Controller
126065: 07/11/14: Re: Synthesis-place&route performance test.
126067: 07/11/14: Re: VCD Files Viewer?
126082: 07/11/14: USR_ACCESS_VIRTEX4 usage
126184: 07/11/16: Re: USR_ACCESS_VIRTEX4 usage
126383: 07/11/20: FPGA Editor (9.2.03i) under Linux x86_64
126888: 07/12/05: Re: can't install Centos 5.1 x86_64 and Xilinx ISE 9.2 evaluation
128558: 08/01/30: EPC in Xilinx EDK 9.2
129207: 08/02/18: Re: Ballpark PLB frequency
129284: 08/02/20: Re: scanf problem in EDk 9.1i (Microbaze)
137984: 09/02/03: Re: Why the second flip-flop in Virtex-6?
138724: 09/03/06: Re: make ise take ngc as source
140243: 09/05/05: Re: Setting top level VHDL generics in XST
141019: 09/06/02: Re: Xilinx GbE performance
141022: 09/06/02: Re: Xilinx GbE performance
141023: 09/06/02: Re: Xilinx GbE performance
141895: 09/07/15: FPGA editor in Fedora 11 x86_64
141958: 09/07/20: Re: FPGA editor in Fedora 11 x86_64
141967: 09/07/20: Re: FPGA editor in Fedora 11 x86_64
144061: 09/11/09: Re: Microblaze performance in V6
144102: 09/11/11: Re: How to interface sgmii core to copper media ?
145583: 10/02/15: Re: Can the Altera USB cable attach to a KVM XP VM?
145584: 10/02/15: Re: Can the Altera USB cable attach to a KVM XP VM?
145598: 10/02/15: Re: Can the Altera USB cable attach to a KVM XP VM?
146970: 10/04/06: Re: Extract single bit from std_logic_vector ...
147746: 10/05/21: Re: Xilinx FIFO cannot be written
150546: 11/01/26: Re: strange problem with RTL
152570: 11/09/15: Re: Can't get the Xilinx cable drivers installed on SL6.1 (RHEL
153226: 12/01/12: Re: Can't get the Xilinx cable drivers installed on SL6.1 (RHEL
154907: 13/02/12: Re: Vivado - Pack I/O Registers?
154914: 13/02/13: Re: Vivado - Pack I/O Registers?
Jan Stumps:
21150: 00/03/08: Q: Hitachi FPGA HD61J215P: Searching Infos!!!
Jan Tjernberg:
32611: 01/07/02: Re: Is the Grass Greener for an Engineer in the USA?
92773: 05/12/06: Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS
Jan Van Belle:
46332: 02/08/26: Starting with VHDL
Jan Vermaete:
16722: 99/06/04: Xilinx symbols, Viewlogic
16758: 99/06/07: Re: Xilinx symbols, Viewlogic
17201: 99/07/08: IEEE1394 core
24712: 00/08/17: Re: how to use script file in the Design Manager
28488: 01/01/15: Re: revision control tools ??
Jan Vorbrueggen:
4824: 96/12/18: Re: ASICs Vs. FPGA in Safety Critical Apps.
5061: 97/01/18: Re: ASICs Vs. FPGA in Safety Critical Apps.
5195: 97/01/30: Re: ASICs Vs. FPGA in Safety Critical Apps.
5264: 97/02/03: Re: ASICs Vs. FPGA in Safety Critical Apps.
17574: 99/08/11: Re: Emulating a transputer on FPGA
28352: 01/01/09: Re: Nondeterministic FSMs in hardware?
Jan Zegers:
9267: 98/03/05: Re: Questions about creating personal package
9394: 98/03/09: Re: Whats wrong with this method
11822: 98/09/11: Re: 16 bit CRC
Jan Ziak:
43215: 02/05/16: What properties has FPGA?
43244: 02/05/17: Re: What properties has FPGA?
43461: 02/05/21: Re: What properties has FPGA?
43482: 02/05/22: Re: What properties has FPGA?
Jan-Hinnerk Reichert:
46526: 02/09/02: Re: Hardware Code Morphing?
jan.kindt:
125241: 07/10/18: Re: VHDL trivia?
<jan_mothers@hotmail.com>:
Janaka:
123847: 07/09/05: Re: high bandwitch ethernet communication
<janbeck@gmail.com>:
76982: 04/12/17: Re: about digilent board
89653: 05/09/21: data logging via JTAG?
89654: 05/09/21: Re: JTAG USB Circuit
118495: 07/04/27: Is there a reset signal available in verilog in Xilinx FPGAs?
122294: 07/07/25: Virtex-5 and powerpc
<jancooo@gmail.com>:
157881: 15/05/08: Re: synthesis tool for systemc
jandc:
67792: 04/03/19: Re: Why It Is not Recommended to Infer latches in VLSI Design...
67985: 04/03/24: Re: study verilog or vhdl?
79863: 05/02/25: Re: Synthesis question
80638: 05/03/09: Re: RS232 VHDL-core
81478: 05/03/24: Re: DDR SDRAM interface working with AMBA-AHB
Jane:
31854: 01/06/06: Re: FPGA / starterkit / VHDL
77388: 05/01/05: VCCO on bank 0
Jane Milton:
49031: 02/10/30: Handel-C Coding for the Motorola 68HC11 chip
Janes:
83956: 05/05/10: Re: Clock delay vs. clock skew
Janet Ellsworth:
3757: 96/07/25: Question about books for FPGA
Janet Rivers:
Janet Tite:
349: 94/10/26: NIM: FPD '95 - Call for Papers
Janick Bergeron:
6315: 97/05/14: Re: VHDL or Verilog?
janigav:
141276: 09/06/15: Ethernet y MicroBlaze with Spartan 3e starter kit
Jann:
22769: 00/05/23: FPGA implementation of LCD controller
22786: 00/05/24: Re: FPGA implementation of LCD controller
Janos Ero:
21886: 00/04/05: Re: Memory cores
21895: 00/04/06: Re: Memory cores
Janos Szamosfalvi:
3982: 96/08/28: RAM inside FLEX 10k
4124: 96/09/13: Re: How to Begin with FPGA design?
4203: 96/09/25: Re: Q: PLD vs. FPGA
4788: 96/12/15: Re: Fpga, Epld, cpld....
Jansyn:
77462: 05/01/07: Showing schematic changes
84644: 05/05/23: Re: VHDL vs. Schematic Capture
janusson:
74855: 04/10/20: Re: How To Provide External Input & Output To Startix 1S40..?
Janusz Raniszewski:
31884: 01/06/07: Re: FPGA & uC8031
43447: 02/05/21: Re: fpga cpu
43821: 02/06/04: Re: NIOS GNUPro tool chain + SDK for Linux
43989: 02/06/08: Re: fpga cpu
44924: 02/07/06: Re: Triscend: SDK CD-ROM : where ?
46488: 02/09/01: Re: Thermoelectric Controller by FPGAs
47622: 02/10/01: Re: TCP/IP in FPGA
47875: 02/10/06: Re: Implementing Delta-Sigma ADC and DAC in Spartan IIE
JanW:
142306: 09/08/03: ucf and clock pin placement on Spartan 3E?
142311: 09/08/03: Re: ucf and clock pin placement on Spartan 3E?
jara:
127716: 08/01/06: Re: How to connect a LED with a clock?
Jared:
57886: 03/07/08: Leonardo changes name of lpm megafunction
Jared Bytheway:
275: 94/10/11: Xilinx configuration
Jared Casper:
145946: 10/03/01: Re: Spice simulation of IBIS details - model examples
Jared Church:
21300: 00/03/16: Re: Difference between FPGA, PLD, CPLD ?
21375: 00/03/21: Re: Clock disabling
21453: 00/03/23: Re: Clock disabling
Jared L. Colflesh:
1839: 95/09/08: looking for a book
<jared.pierce@gmail.com>:
132477: 08/05/28: HDL - simulation vs synthesis
132496: 08/05/28: Re: HDL - simulation vs synthesis
Jarek:
40268: 02/03/04: Atmel back annotation problems
64281: 03/12/24: VHDL-Xilinx-Simulation (signal not connected to port) ?
80891: 05/03/14: Re: Trying to find some Actel A54SX16P FPGAs to purchase
Jarek Lis:
1545: 95/07/12: Intel FLEXLogic
1816: 95/09/06: Lattice ispLSI problem
Jarek Patrzalek:
16641: 99/06/01: Fixed delay in FSM
Jarek Pawelczyk:
77251: 05/01/01: Live Design Ev. Kit with Altera Cyclone
77536: 05/01/10: Re: Configuration devices
Jarek Rozanski:
121566: 07/07/08: LiveDesign, Altium [opinion]
121605: 07/07/09: Re: LiveDesign, Altium [opinion]
121964: 07/07/16: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
124658: 07/09/29: Re: Own soft-processor
124744: 07/10/02: Re: Basic VHDL Development kit
124808: 07/10/04: Re: How to do one hot state machine in verilog for Xilinx V5 using XST
JarekC.DIY:
161345: 19/04/09: Re: Replaceme EPROM by CPLD/FPGA
JaReZ:
119306: 07/05/16: Cyclone II can't enter configuration mode with EPCS1 active serial.
119307: 07/05/16: Cyclone II can't enter in configuration mode with EPCS1.
Jari:
64538: 04/01/06: Generate the first interrupt for MB XMK
64593: 04/01/08: Re: Generate the first interrupt for MB XMK
JarJarJP12:
92426: 05/11/29: Successful use of MGT on Virtex 4
92505: 05/11/30: Re: Successful use of MGT on Virtex 4
92506: 05/11/30: Re: Successful use of MGT on Virtex 4
92565: 05/12/01: Re: Successful use of MGT on Virtex 4
Jarmo:
47410: 02/09/25: PCB Design for Altera FPGA
47813: 02/10/04: Re: PCB Design for Altera FPGA
52130: 03/02/02: How to program Altera EPC1213
Jarod2046@gmail.com:
121463: 07/07/04: Power PC Reference Design timing failed
Jaromir Kolouch:
64677: 04/01/11: PCB for FG456: layers
<jaroslav.sykora@gmail.com>:
126982: 07/12/07: Re: SDRAM and S3E - is the example broken?
Jaroslaw Cichorski Jr.:
8021: 97/11/08: Fitter for PALASM without bug where to download ?
13004: 98/11/10: Problem with the ABEL to Macro convertion in XILINX FB1.3
13032: 98/11/12: Re: Problem with the ABEL to Macro convertion in XILINX FB1.3
Jaroslaw Guzinski:
62161: 03/10/21: Altera programming problem
62204: 03/10/22: Re: Altera programming problem
62285: 03/10/24: Re: Altera programming problem
Jaroslaw Kaczynski:
14778: 99/02/16: Re: Xilinx Foundation Base = Useless?
16907: 99/06/16: Re: Recursive Structures under Aldec AVHDL3.3
Jaroslaw Kubica:
21437: 00/03/22: Re: How to implement STARTBUF / GSR with SpartanXL and VHDL on FNDTN
21572: 00/03/25: Re: Clock on non-dedicate pin
21633: 00/03/27: Re: Clock on non-dedicate pin
21660: 00/03/28: Re: Clock on non-dedicate pin
Jaroslaw Pawelczyk:
94744: 06/01/17: Unassigned pins
94748: 06/01/17: Re: Unassigned pins
Jarrod Wood:
104990: 06/07/11: Xilinx Virtex-4 APU Controller Questions
Jas:
36773: 01/11/20: AHDL to VHDL
37245: 01/12/05: Altera to Actel conversion
jas:
35022: 01/09/18: Xilinx FPGA development boards
35057: 01/09/19: Xilinx equivalent gate count value in the *.mrp report
35509: 01/10/08: FPGA reset
44886: 02/07/04: glitches in back annotation
148048: 10/06/16: Re: How to detect a sync and start of a frame in an optimal way
149268: 10/10/12: Regarding Synchronization of multiple control signals
jasen:
108324: 06/09/08: Re: Please help me with (insert task here)
108383: 06/09/10: Re: Performance Appraisals
118655: 07/05/01: Re: debounce state diagram FSM
118686: 07/05/02: Re: debounce state diagram FSM
118687: 07/05/02: Re: debounce state diagram FSM
Jasen Betts:
121949: 07/07/16: Re: ESR Meter - design contest
157972: 15/06/09: Re: PCIe card with FPGA and DAC
159387: 16/10/21: Re: Microsoft's FPGA Translates Wikipedia in less than a Tenth of a
JASH:
89970: 05/09/30: Re: I am planning to purchase a Virtex-4 Eval board.
89971: 05/09/30: Re: Prevue - FPGA Dev Board Sale
91574: 05/11/08: Re: BRAMs readback
91576: 05/11/08: Re: old xilinx components
91794: 05/11/13: Re: FPGA KIT recommendation
Jasim Khan:
156149: 13/12/19: PPC 405 communication with custom IP ml403
156151: 13/12/19: Re: ppc405 communication with custom ip ml403
156615: 14/05/13: virtex4 software reset problem.
<jasimpson@gmail.com>:
109257: 06/09/22: Altera configuring/programming for FLEX10KE with EPC2 - sof or pof?
jasmile:
147742: 10/05/21: speed grade and temperature grade aren't marked??
Jasmine Hau:
64903: 04/01/15: Can nios_gnupro support file system?
64969: 04/01/16: Re: Can nios_gnupro support file system?
65651: 04/02/04: Altera Nios UART communication
71631: 04/07/25: Gate Count vs Logic Element (LE)
71692: 04/07/27: Re: nios-run: waiting for target.......?
71815: 04/07/31: Re: FPGA prototype board with ethernet interfaces
71816: 04/07/31: LE and EAB on FPGA board
79238: 05/02/15: How to use file input output function?
jason:
48765: 02/10/23: Re: How full is too full?
Jason:
33870: 01/08/07: Reconfigurable Computational Accelerator
34140: 01/08/15: FPGA for Reconfigurable Computing
34259: 01/08/17: Re: FPGA for Reconfigurable Computing
37298: 01/12/06: XC6200
65350: 04/01/25: Re: Spirit on Mars
65391: 04/01/27: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
68863: 04/04/20: the No. of gates of Xilinx FPGA
68866: 04/04/20: calculate the number of logic gate in FPGA
80126: 05/03/01: MGT RXLOSSOFSYNC problem
114399: 07/01/14: SDK 8.2 error 127
117284: 07/03/27: longest webcase record
148417: 10/07/21: Re: Announcing AjarDSP - an open source VLIW DSP
152263: 11/07/29: Re: Bitstream compression
Jason A. Daughenbaugh:
27908: 00/12/14: Re: Verilog or VHDL
Jason Agron:
110831: 06/10/24: Re: Survey on Quartus SOPC/Nios-II
120731: 07/06/15: Re: Build error for multiprocessor sytem.
126577: 07/11/27: Re: 33+ Regs in PLB IPIF
136971: 08/12/16: Re: Problem with infering BRAM in XST
142656: 09/08/24: Re: Multiple Interrupt handling in XPS 8.2i
Jason Berringer:
36778: 01/11/19: ISA interface
36939: 01/11/26: Which vendor to choose
37362: 01/12/08: ISA syncronization?
37395: 01/12/09: Re: ISA syncronization?
37587: 01/12/16: SPI interface in VHDL
38045: 02/01/02: A Fast counter in VHDL?
38067: 02/01/03: Re: A Fast counter in VHDL?
38132: 02/01/06: Re: A Fast counter in VHDL?
45706: 02/08/01: Division
45964: 02/08/12: Re: Division
51163: 03/01/04: conversions and some assistance please
51285: 03/01/09: Re: conversions and some assistance please
56825: 03/06/16: An All Digital Phase Lock Loop
56866: 03/06/17: Re: An All Digital Phase Lock Loop
57701: 03/07/03: constraints, etc
58097: 03/07/14: Re: An All Digital Phase Lock Loop
58639: 03/07/29: Re: binary to BCD assistance
58745: 03/07/31: Re: binary to BCD assistance
59195: 03/08/11: Webpack sees 2 clocks when there is only one
59233: 03/08/12: Re: Webpack sees 2 clocks when there is only one
62905: 03/11/10: Layout examples
69380: 04/05/09: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
70154: 04/06/05: Quick question
70197: 04/06/08: Re: Quick question
70237: 04/06/09: Re: Quick question
71928: 04/08/03: Re: FPGA and RS422
75064: 04/10/25: Re: Async reset
75065: 04/10/25: Bus interfaces & FSMs
74881: 04/10/20: Async reset
75666: 04/11/11: asynchronous bus transfers
75728: 04/11/13: Re: asynchronous bus transfers
75729: 04/11/13: Re: asynchronous bus transfers
75730: 04/11/13: Re: asynchronous bus transfers
76147: 04/11/25: Re: Programming flash connected to CPLD via JTAG
76530: 04/12/05: internal tristates and busses
76592: 04/12/06: Re: internal tristates and busses
77524: 05/01/09: constraints
82172: 05/04/07: FPGA Layout question
82206: 05/04/08: Re: FPGA Layout question
82226: 05/04/08: Re: FPGA Layout question
82371: 05/04/11: Re: FPGA Layout question
82734: 05/04/17: Re: FPGA/Embedded courses online or near Toronto
82755: 05/04/17: Re: FPGA/Embedded courses online or near Toronto
85833: 05/06/16: Re: BGA Rework/Prototype Placement Anyone?
Jason Caulkins:
11457: 98/08/16: SCSI core
12580: 98/10/17: Re: PCI target code
Jason Chan:
14907: 99/02/24: Batch compliation using Altera maxplus2?
Jason Cong:
2353: 95/11/22: FPGA'96 Advance Program
Jason Crawford:
3847: 96/08/08: Extended libraries for OrCAD/Xilinx schematic entry
4150: 96/09/18: OrCAD schematic based multiplier for XC4000 series
45384: 02/07/22: Clock-gating in Virtex-E parts
47117: 02/09/18: linear-log converter required
65696: 04/02/05: PS/2 Keyboard opencore (keyboard side) available ???
Jason Daughenbaugh:
27522: 00/11/27: Re: Fifo design problem
28020: 00/12/19: Re: 3V -> 5V clock signal level conversion
29136: 01/02/07: Re: 8B/10B Encoding
31923: 01/06/08: Re: Force tristate enable register into IOB
32068: 01/06/12: Video Compression on an FPGA
32844: 01/07/10: XC17S00XL vs XC17S00A
35517: 01/10/09: Re: FPGA reset
40933: 02/03/18: Re: Difference between Virtex-II(E) und Virtex-E
41299: 02/03/25: Re: Missing Timing by 30,000 ns
47326: 02/09/23: Re: Fast serial interconnect bus using spartan-II
58126: 03/07/15: Re: programming a PLD/CPLD with a PIC?
60716: 03/09/19: LVDS in Xilinx (Spartan-3)
Jason Flood:
1840: 95/09/08: Re: Jury Verdict + Test Benches
Jason Gomez:
1533: 95/07/10: FPGA modules compatible with 6u VME ???
1511: 95/07/05: FPGA modules compatible with 6u VME
1510: 95/07/05: FPGA modules compatible with 6u VME
Jason Hannula:
50495: 02/12/11: Any experience with Altera Apex PCI Development Kit?
Jason Hou:
1467: 95/06/26: Re: InOut Port in the Synopsys FPGA Compiler
Jason Hsu:
133588: 08/07/04: HELP! How do I install Xilinx ISE WebPack?
134478: 08/08/12: Using a Spartan 3 FPGA kit with a USB/DB9
134481: 08/08/12: Re: Using a Spartan 3 FPGA kit with a USB/DB9
Jason Hu:
89800: 05/09/26: How to run ngcbuild in windows xp environment?
89803: 05/09/26: Re: How to run ngcbuild in windows xp environment?
89805: 05/09/26: Re: question about creating RPM
Jason Lade:
53335: 03/03/11: Interested in FPGA programming using systemc
Jason Langkamer-Smith:
37519: 01/12/13: FPGA introduction
Jason LaPenta:
39883: 02/02/21: Problems : INOUT not allowed, alternatives
Jason Lawley:
31896: 01/06/07: Re: Xilinx RapidIO?
Jason Lewis:
81273: 05/03/20: TPS75003 for FPGAs
jason lim:
32164: 01/06/17: How to connect mp3 player with a hard disk
Jason Lohn:
13538: 98/12/08: CFP: The First NASA/DOD Workshop on Evolvable Hardware
14697: 99/02/11: 2nd CFP: THE FIRST NASA/DoD WORKSHOP ON EVOLVABLE HARDWARE
14923: 99/02/25: EH'99 deadline extended to March 10
16769: 99/06/07: Call for Participation: The First NASA/DoD Workshop on Evolvable
19919: 00/01/18: CFP: The Second NASA/DoD Workshop on Evolvable Hardware
21106: 00/03/07: REMINDER: CFP: The Second NASA/DoD Workshop on Evolvable Hardware
Jason Luska:
151092: 11/03/05: IP Core Delivery Format Info
151112: 11/03/08: Re: IP Core Delivery Format Info
Jason Moore:
40770: 02/03/14: Re: Proto boards for labs
41921: 02/04/10: Re: ChipScope ILA, cable requirements
Jason Morgan:
Jason Nunn:
10405: 98/05/16: Re: Design/document/reference of motion encoder interface wanted
Jason Ozolins:
87376: 05/07/22: Re: (x86 linux) SSE2 usage by simulation applications?
88715: 05/08/26: Re: Library of eBooks on FPGA's and other programming stuff
Jason Pattison:
14107: 99/01/14: Programmng ALTERA EPROMS
15403: 99/03/23: Re: FLEX 10K question
15659: 99/04/07: Re: newbie: FPGA suggestion
16916: 99/06/17: Re: Altera EPC1 replacement?
Jason Phillips:
46406: 02/08/28: Re: V2 Pipelined Embedded Mulitplier PAR issues
Jason Rosinski:
93395: 05/12/21: Re: More beginner's verilog questions
93418: 05/12/21: Re: More beginner's verilog questions
Jason Sewall:
54545: 03/04/13: Re: Hardware acceleration for raytracing purposes
Jason Stratos Papadopoulos:
33417: 01/07/26: prospects for tiny FPGA supercomputer?
33455: 01/07/26: Re: prospects for tiny FPGA supercomputer?
34028: 01/08/12: Re: prospects for tiny FPGA supercomputer?
Jason Sze:
8775: 98/01/26: For sales - Electroinic components
Jason T. Wright:
4263: 96/10/07: Re: FPGA for Reed-Solomon Codec
4339: 96/10/17: Re: xc4000 and 2 clocks
4547: 96/11/12: Re: UART FOR FPGAS
4718: 96/12/05: Re: Memory Requirements
4841: 96/12/19: Re: Cascaded serial PROMS
5301: 97/02/05: Embedded SRAM in FPGAs
5303: 97/02/05: Re: Duplicate PLD?
5322: 97/02/06: Re: Xilinx Xact Step Software
6054: 97/04/08: Re: Chip Temperature (was:Re: Sole source)
6281: 97/05/08: Re: Xilinx .UCF file examples
7453: 97/09/11: Re: Cheap (sub $10) hardwired FPGA? Which manufacturers?
7780: 97/10/14: Re: How fast can fully pipelined XC4000 logic go?
7782: 97/10/14: Re: Synopsys, XACT, XC4000: CLB estimates
8037: 97/11/10: Re: FPGA basics please ?
8184: 97/11/25: Re: AT17C256 problems
8091: 97/11/17: Re: Xilinx Logiblox in Synopsys
16496: 99/05/25: Re: Synthesis problem
16498: 99/05/25: Re: Synthesis problem
17909: 99/09/16: Re: xilinx v2.1i
18796: 99/11/16: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
18824: 99/11/18: Re: FPGA to ASIC conversion
18994: 99/11/23: Re: VHDL vs. schematic entry
20491: 00/02/11: Re: xilinx
21552: 00/03/24: Re: FPGA openness
21553: 00/03/24: Re: FPGA openness
23496: 00/06/27: Re: FPGA and ASIC
23497: 00/06/27: Re: inferring global buffers in Leonardo?
23685: 00/07/05: Re: Serial Number embedded in PROM.
23686: 00/07/05: Re: 2.1i better than 1.5?
23875: 00/07/13: Re: hold time errors in FPGA's ?
25229: 00/08/31: Re: Latches
25230: 00/08/31: Re: Synopsys Synthesis
32092: 01/06/13: Re: who needs clk180
32618: 01/07/02: Re: Modelsim waveform
32797: 01/07/09: Re: Need some help using Synplify ... and also considering Xilinx
36190: 01/11/01: Synplicity, Xilinx, & unwanted BUFGs
37461: 01/12/11: Re: What do you like/dislike about place and route tools?
37462: 01/12/11: Re: XNF file gets corrupted
41383: 02/03/26: Re: Too many clocks
42933: 02/05/07: Re: Timing Scores
55190: 03/04/30: Re: Two RAMs in one slice
55346: 03/05/05: Re: Two RAMs in one slice
Jason Tang:
84271: 05/05/16: Re: Xilinx tools from the commandline
84272: 05/05/16: Re: Impact Kernel 2.6
84321: 05/05/17: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
Jason Tayles:
4567: 96/11/15: Job Post 2 Hardware Engineers Needed VHDL, FPGA $80
4711: 96/12/05: US LA *Job Post* Vhdl, FPGA, Mentor Engineer Needed to $75/hr
Jason Thibodeau:
145890: 10/02/26: Place and Route
145908: 10/02/27: Re: Place and Route
146015: 10/03/03: Re: Laptop for FPGA design?
146051: 10/03/04: Looking for a USB JTAG cable
146054: 10/03/04: Re: Place and Route
146553: 10/03/22: Re: Why hardware designers should switch to Eclipse
146559: 10/03/22: Standard cell library help
146588: 10/03/23: Re: Standard cell library help
146599: 10/03/23: Re: Standard cell library help
146602: 10/03/23: Re: Standard cell library help
146606: 10/03/23: Re: Standard cell library help
146612: 10/03/23: Re: Standard cell library help
146616: 10/03/23: Implementation of IWLS benchmark- Manual place and route
146625: 10/03/24: Re: Implementation of IWLS benchmark- Manual place and route
146639: 10/03/24: Ring Oscillator -> counter differences
146654: 10/03/25: Re: Ring Oscillator -> counter differences
146667: 10/03/25: XST optimization
146712: 10/03/26: Re: XST optimization
146713: 10/03/26: Re: Ring Oscillator -> counter differences
146769: 10/03/28: Re: XST optimization
146785: 10/03/28: Re: XST optimization
146811: 10/03/29: Re: XST optimization
146814: 10/03/29: Re: XST optimization
146819: 10/03/29: Re: XST optimization
146826: 10/03/29: Re: XST optimization
146852: 10/03/30: Re: XST optimization
147608: 10/05/06: Re: FPGA Compilation Time Windows vs Linux
148614: 10/08/06: Re: Vendor Tool Stability
Jason Wang:
535: 94/12/27: Re: fpga-compiler (synopsys)
606: 95/01/18: Re: ACTEL and EXEMPLAR
Jason White:
45340: 02/07/19: fpga or cpld?
Jason Whitwam:
121564: 07/07/08: Question on Virtex2p DCMs usability
121572: 07/07/08: Re: Question on Virtex2p DCMs usability
121573: 07/07/08: Re: Question on Virtex2p DCMs usability
Jason Wu:
82325: 05/04/11: XMD only operating in compatibility mode under Suse9.2 pro
83857: 05/05/08: Parallel Cable IV operating in "Compatibility Mode" under linux kernel 2.6.x
84584: 05/05/21: Re: How to download uClinux on Virtex4 Board.
88899: 05/08/30: Re: Virtex4 : Downloading error
Jason Zheng:
71146: 04/07/09: Re: Icarus Verilog for Windows
80051: 05/02/28: Re: FPGA tool benchmarks on Linux systems
80106: 05/03/01: Re: FPGA tool benchmarks on Linux systems
80113: 05/03/01: Re: FPGA tool benchmarks on Linux systems
80250: 05/03/02: timing diagram tool linux
80521: 05/03/07: Re: state encoding in FSM for simple cases ?
80523: 05/03/07: Re: state encoding in FSM for simple cases ?
80526: 05/03/07: Re: state encoding in FSM for simple cases ?
80530: 05/03/07: Re: state encoding in FSM for simple cases ?
80531: 05/03/07: Re: state encoding in FSM for simple cases ?
80577: 05/03/08: Re: state encoding in FSM for simple cases ?
80679: 05/03/09: Re: Xilinx vs Altera high-end solutions
80721: 05/03/10: Re: Xilinx vs Altera high-end solutions
80723: 05/03/10: Re: Xilinx vs Altera high-end solutions
80739: 05/03/10: Re: Xilinx vs Altera high-end solutions
80810: 05/03/11: Re: Xilinx vs Altera high-end solutions
81926: 05/04/04: Re: Stupid question
82911: 05/04/19: actel blockram the easy way?
83256: 05/04/26: Re: PCI plug n play and Graphics card implementation
83312: 05/04/27: x on ml300?
83324: 05/04/27: Re: x on ml300?
86871: 05/07/07: Re: Verilog exponential operator issues in simulation (ISE 7.1 SP3
93247: 05/12/16: Re: Inverter Chain Synthesis Problem
96351: 06/02/02: Re: How will synthesizers handle these statements?
99368: 06/03/23: Re: OpenSPARC released
99746: 06/03/28: Re: OpenSPARC released
99801: 06/03/29: Re: OpenSPARC released
131582: 08/04/25: Re: Breaking News ... Accellera Verification Working Group Forming
133174: 08/06/19: Re: which commercial HDL-Simulator for FPGA?
133215: 08/06/20: Re: which commercial HDL-Simulator for FPGA?
138410: 09/02/20: Re: GTKWave 3.2.0 for Windows is available
142184: 09/07/28: Re: iCore7 vs Core2 simulation & FPGA tool performance?
142583: 09/08/18: Re: GTKWave 3.2.2 for Windows is available
144081: 09/11/10: Re: Jan on HDL Design
146864: 10/03/30: Re: Which is the most beautiful and memorable hardware structure in
Jason Zimmernann:
41961: 02/04/11: PCI Bridge Question
41999: 02/04/12: Re: PCI Bridge Question
42000: 02/04/12: Re: Difference between the Virtex and the Virtex II
<jason.hy.wu@gmail.com>:
135523: 08/10/06: Re: Reading files from CF (microblaze 7 and plb)
138318: 09/02/15: Re: ERROR:NgdBuild:604
jason.stubbs:
82525: 05/04/13: Re: Xilinx VIIPro power supplies
82574: 05/04/14: Re: Xilinx VIIPro power supplies
82575: 05/04/14: Connecting Virtex2pro to Virtex4 via RocketIO MGT's
82587: 05/04/14: Re: Connecting Virtex2pro to Virtex4 via RocketIO MGT's
82598: 05/04/14: Re: Connecting Virtex2pro to Virtex4 via RocketIO MGT's
83081: 05/04/22: Virtex 4 Power consumption
83156: 05/04/25: Re: Virtex 4 Power consumption
83184: 05/04/25: Re: Virtex 4 Power consumption
83695: 05/05/05: System Ace: How many FPGA's in the JTAG chain before require buffers?
84340: 05/05/17: Virtex 4 MGTVREF pin reference circuit
<jason.stubbs@gmail.com>:
82508: 05/04/13: Re: Xilinx VIIPro power supplies
<jason_hatley@my-deja.com>:
24680: 00/08/16: ASIC folks of all stripes needed in Spokane
24681: 00/08/16: Re: ASIC ---- send resumes to
jasonal:
102340: 06/05/15: uClinux on MicroBlaze: Can't ping now
<jasonf>:
2608: 96/01/10: Re: Emulation for a wireless chip
2634: 96/01/16: Re: Emulation for a wireless chip
2718: 96/01/29: Re: Emulation for a wireless chip
<jasonkailuu@gmail.com>:
155864: 13/10/06: VTR 7.0 Release Announcement
jasonL:
115686: 07/02/16: Does Xilinx XST synthesize combinational divider?
120406: 07/06/06: What should be taken care of when two FPGA broad connected together?
120423: 07/06/06: Re: What should be taken care of when two FPGA broad connected together?
128629: 08/01/31: Why use small resistor for Vcco voltage regulator
128664: 08/02/02: Re: Why use small resistor for Vcco voltage regulator
129297: 08/02/20: From ASIC RTL to FPGA, what are the things I should take care of?
129410: 08/02/22: Re: From ASIC RTL to FPGA, what are the things I should take care of?
Jasper Hendriks:
23903: 00/07/14: Need help with Maxplus and large bus multiplexer
24582: 00/08/14: clock skew problem please help!!
24706: 00/08/17: Re: clock skew problem please help!!
<jasuris@gmail.com>:
123329: 07/08/23: ROUTING=CLOSED in Xilinx 9.1 PR tools
123356: 07/08/24: Re: ROUTING=CLOSED in Xilinx 9.1 PR tools
Jatan C. Shah:
1776: 95/08/30: Neede verilog model for xc4000 clb and xc4000 iob..
Jatan Shah:
869: 95/03/17: Synopsys XACT Interface...
910: 95/03/28: Memory in xc4000 using synopsys...
969: 95/04/05: Xilinx simulation models for synopsys..
1179: 95/05/11: Simulation of Xilinc components on VSS..
1235: 95/05/19: Multi-chip partitioning for XC4k devices
Jatin Bhateja:
128107: 08/01/15: Question on FPGA
<javaguy11111@gmail.com>:
99648: 06/03/27: Re: OpenSPARC released
99674: 06/03/27: Re: OpenSPARC released
120053: 07/05/31: Can't get AREA_GROUP to work
120060: 07/05/31: Re: Can't get AREA_GROUP to work
120073: 07/05/31: Can't get AREA_GROUP to work
120148: 07/06/01: Modular Design Example
120154: 07/06/01: Re: Modular Design Example
120223: 07/06/03: TBUF and modular design flow on spartan
120250: 07/06/04: Re: TBUF and modular design flow on spartan
120276: 07/06/04: Re: TBUF and modular design flow on spartan
<javaguy11111@yahoo.com>:
76060: 04/11/23: Re: Low cost million gate Spartan 3 board?
Javi:
105544: 06/07/25: Clock signal remains HIGH forever in Spartan-3 Starter Kit from Digilent
105548: 06/07/25: Re: Clock signal remains HIGH forever in Spartan-3 Starter Kit from Digilent
Javi Diaz:
36707: 01/11/16: Spartan2 - 5 V tolerance question
javid:
43919: 02/06/06: Xilinx ise software?
50392: 02/12/10: Xilinx ISE 5.1 Wait for statement unsupported??
50430: 02/12/10: Re: Xilinx ISE 5.1 Wait for statement unsupported??
50465: 02/12/11: Re: Xilinx ISE 5.1 Wait for statement unsupported??
58071: 03/07/14: programming a PLD/CPLD with a PIC?
58103: 03/07/14: Re: programming a PLD/CPLD with a PIC?
58115: 03/07/15: Re: programming a PLD/CPLD with a PIC?
58158: 03/07/15: Re: programming a PLD/CPLD with a PIC?
60882: 03/09/24: Portable computer for FPGA/CPLD tools
69293: 04/05/05: Max7000s: how to use the enable of the dffe flip-flop?
69318: 04/05/06: Re: Max7000s: how to use the enable of the dffe flip-flop?
69796: 04/05/20: Timing Questions?
70714: 04/06/24: synchronizer and Reset question?
73640: 04/09/27: MAX7000s GCLRn Pin input current?
76214: 04/11/29: internal logic signal to global routing resource in QII?
<javidiaz@my-deja.com>:
20956: 00/03/01: AMS board simple questions
20979: 00/03/02: AMS board design advice asked
28894: 01/01/28: Standard Deviation Moving Window
Javier =?iso-8859-1?Q?Fern=E1ndez?=:
49919: 02/11/25: Help: Virtex-II Pro eval.brd for System Generator
51156: 03/01/04: Re: Running 2 inter related programs on the FPGA
Javier =?iso-8859-1?Q?Fern=E1ndez?= Baldomero:
45129: 02/07/13: Re: FPGA CPU?
61224: 03/09/30: ISE WebPack 6.1 Impact problem
61262: 03/10/01: Re: ISE WebPack 6.1 Impact problem
61647: 03/10/08: Re: ISE WebPack 6.1 Impact problem
Javier Castillo:
72681: 04/08/28: Re: SOC and ASIC ?
72920: 04/09/08: Re: why systemc?
72962: 04/09/09: Re: why systemc?
73091: 04/09/14: Re: Newbie question systemc
73103: 04/09/14: Re: why systemc?
76806: 04/12/13: Re: Inferring dual port RAMs with different bus widths.
76807: 04/12/13: Re: UART receiver
77029: 04/12/20: New release of SystemC to Verilog translator
80004: 05/02/28: SystemC to Verilog Translator v0.4
80013: 05/02/28: Re: synthesis tool for systemc
85893: 05/06/17: Xilinx FFT
88058: 05/08/08: Hiding data inside a FPGA
88128: 05/08/10: Re: Hiding data inside a FPGA
88223: 05/08/12: Re: Delays in verilog
88356: 05/08/16: Re: Modular design flow
88408: 05/08/17: Re: FPGA-Based system design project
88852: 05/08/30: Re: openrisc, jp1 jtag debug utility
88901: 05/08/31: Re: openrisc, jp1 jtag debug utility
90318: 05/10/10: systemc to verilog translator v0.5
90424: 05/10/12: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4
90437: 05/10/13: Re: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4
90438: 05/10/13: Re: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4
90456: 05/10/13: Re: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4
90755: 05/10/20: Re: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4
90861: 05/10/24: Re: RS232 Uart for Virtex-II Pro
92238: 05/11/24: Re: Access to long lines in Virtex-II
92917: 05/12/09: Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause
92923: 05/12/09: Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause
92937: 05/12/09: Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause
93052: 05/12/13: Re: who can help me? i want to know the bitsream format of Virtex-II
93289: 05/12/19: Re: Inverter Chain Synthesis Problem
95658: 06/01/25: Re: Xilinx Partial Reconfiguration add-on module
96979: 06/02/14: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
97026: 06/02/15: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
97608: 06/02/24: Re: OpenRisc 1200 on Spartan 3 - problems with stability and enabling cache
101209: 06/04/27: Re: OpenRisc 1200 on a XUP
Javier Garcia:
48602: 02/10/21: Buy Small quantities
48670: 02/10/22: Buy fpga
Javier Lopez:
93871: 06/01/02: Re: Actel Fusion
Javier Moran Carrera:
239: 94/09/30: Area of a FPGA tile.
494: 94/12/07: Any benchmark for FCMs?.
Javier Paricio Rodríguez:
10792: 98/06/19: HELP. Anybody knows Orcad Express (VHDL)?
Javier SERRANO:
27589: 00/11/29: Re: PLL vs DLL
27972: 00/12/18: Help with encoder/decoder
Javier Serrano:
47053: 02/09/16: Question about Virtex-II DCM's jitter
47058: 02/09/16: Re: Question about Virtex-II DCM's jitter
47065: 02/09/16: Re: Question about Virtex-II DCM's jitter
47090: 02/09/17: Re: Question about Virtex-II DCM's jitter
<javier@world>:
2485: 95/12/15: WAnted: correlator!!!!!
2484: 95/12/15: WAnted: correlator!!!!!
jawahar ali:
30807: 01/04/30: FPGA-CPLD
Jawahar Ali:
31281: 01/05/16: PowerPC
Jawbreaker:
111058: 06/10/27: Re: FPGA-based music synthesizer (with MyHDL)
<jaxato@gmail.com>:
79525: 05/02/20: difficult to build counter, some help please : (
79536: 05/02/20: Re: difficult to build counter, some help please : (
80022: 05/02/28: Re: difficult to build counter, some help please : (
80029: 05/02/28: Re: difficult to build counter, some help please : (
80218: 05/03/02: Re: Signal Integrity, ground bounce, crosstalk, SSOs, BGA pin-outs, parasitic inductance...
80229: 05/03/02: Re: Signal Integrity, ground bounce, crosstalk, SSOs, BGA pin-outs, parasitic inductance...
80300: 05/03/03: How to readback a BRAM
80408: 05/03/04: Re: How to readback a BRAM
83860: 05/05/08: Re: Which chip should I use?
92111: 05/11/22: Re: Sounds or other means to indicate end of compilation in Xilinx ISE
92763: 05/12/06: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS
92769: 05/12/06: Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS
92772: 05/12/06: Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS
92778: 05/12/06: Re: xilinx research labs
93006: 05/12/11: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93047: 05/12/12: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93147: 05/12/14: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93190: 05/12/15: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93259: 05/12/16: Re: Avnet hav2 s3e starter kit?
96612: 06/02/07: Spartan3 Live Insertion with XC9572XL chip
100072: 06/04/02: Re: KEEP_HIERARCHY
100676: 06/04/15: Where is the xilinx online store gone?
100685: 06/04/15: Re: Where is the xilinx online store gone?
100696: 06/04/16: Re: Petition about the xilinx online store ?
100707: 06/04/16: Re: Petition about the xilinx online store ?
101283: 06/04/28: What would be the tariff classification of an FPGA development board?
101358: 06/04/29: Re: What would be the tariff classification of an FPGA development board?
101364: 06/04/29: Re: What would be the tariff classification of an FPGA development board?
103110: 06/05/25: DSP48E, What are the internal implementations used?
103115: 06/05/25: Re: DSP48E, What are the internal implementations used?
103122: 06/05/25: Re: DSP48E, What are the internal implementations used?
103704: 06/06/08: Re: stable, tested 6502 core
107469: 06/08/28: Re: What is the truth about the Virtex5 ?
138774: 09/03/09: Re: Image loading into FPGA - from computer
<jaxatwork1@gmail.com>:
95367: 06/01/22: Re: Reading user data from PROM
<jaxatwork@gmail.com>:
84490: 05/05/19: Re: Spartan 3 CPI
jay:
133398: 08/06/26: NVRAM design in CPLD
133405: 08/06/27: Re: NVRAM design in CPLD
143440: 09/10/11: ncelab: *W,SDFINF warning when back annotating SDF
143484: 09/10/12: How to get clocks from DCM that the duty cycle is not 1:1
143511: 09/10/13: Re: How to get clocks from DCM that the duty cycle is not 1:1
143514: 09/10/14: Re: How to get clocks from DCM that the duty cycle is not 1:1
143535: 09/10/15: Re: How to get clocks from DCM that the duty cycle is not 1:1
143559: 09/10/16: Re: How to get clocks from DCM that the duty cycle is not 1:1
144140: 09/11/13: An incomplete Mux and Latch?
144145: 09/11/13: Re: An incomplete Mux and Latch?
144146: 09/11/13: Re: An incomplete Mux and Latch?
151103: 11/03/06: Re: IP Core Delivery Format Info
151106: 11/03/07: Re: IP Core Delivery Format Info
151109: 11/03/07: Re: IP Core Delivery Format Info
151327: 11/03/23: Re: pcb&bitstream
Jay:
33657: 01/08/01: Re: What way for Xilinx to ASIC migration ?
33658: 01/08/01: Re: Altera MPLD
33772: 01/08/03: Re: UART problems
34011: 01/08/10: Re: Question on use of FPGA in a special Data Aquisition system
36508: 01/11/09: Re: speed of HW JPEG implementations
36874: 01/11/22: Re: too large a 32 entry 3 read 2 write register file
36875: 01/11/22: Re: slew rate of virtex output buffers figures
36876: 01/11/22: Re: Fast Fourier Transformation - camera data
36877: 01/11/22: Re: How can I solve the "clock" warning of synplify.
38278: 02/01/10: Re: FPGA and CCD : any experience?
38279: 02/01/10: Re: Interpreting Xilinx Timing Analyser report files
38280: 02/01/10: Re: multiply (*) 11000000000
38291: 02/01/10: Re: ASIC faster than VirtexII FPGA?
38292: 02/01/10: Re: How do I use Altera's PLL megafunction to multiply some frequency ?
38294: 02/01/10: Re: The speedest FPGA
38295: 02/01/10: Re: ROM die area question
38495: 02/01/15: Re: FPGA and CCD : any experience?
38496: 02/01/15: Re: Altera Compiling Error..WHY?????
38498: 02/01/15: Re: remainder
38499: 02/01/15: Re: SYN_HIER attribute in synplify v7.0
38500: 02/01/15: Re: variable declare
38523: 02/01/16: Re: Synthesis in FPGA Express
38734: 02/01/23: Re: Q: can ROM content affect logic syn result
38740: 02/01/23: Re: APEX-II vs VIRTEX-II
38742: 02/01/23: Re: Simple shift register not working
38743: 02/01/23: Re: Xilinx Timing report question
39232: 02/02/04: Re: RAM question
39234: 02/02/04: Re: FPGA or Micro-controller in Lowpower designs?
39236: 02/02/04: Re: LARGE ultra low power FPGA/CPLD recommendation
39237: 02/02/04: Re: Dual ported RAM in SpartanII, output = ?????
39238: 02/02/04: Re: Pin assignment on ACEX1K
39239: 02/02/04: Re: Flex10KA vs MAX7000S
39299: 02/02/05: Re: Virtex-II and SDRAM Controller at 133MHz
39327: 02/02/06: Re: Making Altera development quicker
39331: 02/02/06: Re: random
39338: 02/02/06: Re: Making Altera development quicker
39339: 02/02/06: Re: designing a protocol analyzer for proprietary serial bus
39340: 02/02/06: Re: the cause of the simulation/synthesis mismatch
39374: 02/02/07: Re: Which PC for ALTERA development tools ?
39375: 02/02/07: Re: BRAM, clka too short setup time
39377: 02/02/07: Re: Virtex2-3000 (XC2V3000) engineering samples and chipscope
39426: 02/02/08: Re: Help on bus interface needed.
39427: 02/02/08: Re: the cause of the simulation/synthesis mismatch
39428: 02/02/08: Re: Multiple clock domein synchronization.
39486: 02/02/11: Re: Help on bus interface needed.
39520: 02/02/12: Re: Making Altera development quicker
39521: 02/02/12: Re: Help on bus interface needed.
39542: 02/02/12: Re: Help on bus interface needed.
39573: 02/02/13: Re: Help on bus interface needed.
39589: 02/02/13: Re: Is Leonardo spectrum OEM version for Altera limited?
39774: 02/02/19: Re: Virtex-E BRAM timing
39775: 02/02/19: Re: Maximum # of logic level
39776: 02/02/19: Re: Edge selection with RAM
39777: 02/02/19: Re: Multipliers in Altera FPGAs
39778: 02/02/19: Re: FPGA: JTAG CABLE
39792: 02/02/19: Re: Faster designs
39794: 02/02/19: Re: Coolrunner and ISP
39795: 02/02/19: Re: Xilinx IP Core multiplier performance
39798: 02/02/19: Re: Clocking issues w/ CoolRunner & Webpack
39829: 02/02/20: Re: Counter does not fit CPLD?
39830: 02/02/20: Re: gate array
39875: 02/02/21: Re: Need largest CPLD devices?
39976: 02/02/22: Re: CPLD PROJECT
40049: 02/02/25: Re: Comparison between two FPGAs- what is decisive factor?
40050: 02/02/25: Re: Beginner Altera Questions
40074: 02/02/26: Re: Beginner Altera Questions
40075: 02/02/26: Re: Quartus (finding node)
40108: 02/02/27: Re: Beginner Altera Questions
40120: 02/02/27: Re: SDRAM+FPGA
40146: 02/02/28: Synopsys Design Compiler
40209: 02/03/01: Re: Synopsys Design Compiler
40289: 02/03/04: Re: share two months salary with you if you have job information
40290: 02/03/04: Re: What FPGA to use?
40327: 02/03/05: Re: digital video PLL
40329: 02/03/05: Re: share two months salary with you if you have job information
40333: 02/03/05: Re: exceeding 2GB limits in xilinx
40344: 02/03/05: Re: FPGA problems
40469: 02/03/07: Re: Using a battery instead of Config device
40470: 02/03/07: Re: Fast transmission
40471: 02/03/07: Re: Virtex-II : Temperature Sensing Diodes
40472: 02/03/07: Re: V-II DCM options
40484: 02/03/07: Re: Clamping Diode in the I/O !!!
40523: 02/03/08: Re: exceeding 2GB limits in xilinx
40531: 02/03/08: Re: Sandwich board at ESC
40612: 02/03/11: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40613: 02/03/11: Re: Synopsys Design Compiler
40623: 02/03/11: Re: high active and low active reset signal mixed in a design
40624: 02/03/11: Re: floating pins
40668: 02/03/12: Re: nOOb: wants to start using an fpga
40669: 02/03/12: Re: floating pins
40753: 02/03/14: Re: Synthesis tools comparison?
40754: 02/03/14: Re: Difference between Virtex-II(E) und Virtex-E
40797: 02/03/15: Re: where to start with constraining..
40947: 02/03/18: Re: How to deal with a high fan-out net in FPGA.
41000: 02/03/19: Re: High speed clock routing
41020: 02/03/19: Re: 1,5V power supply?
41021: 02/03/19: Re: Xilinx : Altera pin compatibility
41023: 02/03/19: Re: state machine coding style
41098: 02/03/20: Re: how to deal with signal pass through two clock domain
41102: 02/03/20: Re: Possibility of RTL and Gate-level simulation dont match?
41103: 02/03/20: Re: Fixed Point Library
41584: 02/04/02: Re: pricing and gate count info
41620: 02/04/03: Re: ByteblasterMV EPM7064S voltage problem
41621: 02/04/03: Re: ACEX maximal clock...
41622: 02/04/03: Re: Pullup of Spartan-2
41672: 02/04/04: Re: ACEX maximal clock...
41724: 02/04/05: Re: Help: Design a crystal oscillator in a Xilinx XCR3256XL
41726: 02/04/05: Re: How to force Foundation to NOT use an ILB flop?
41748: 02/04/06: Re: Distributed ram
41749: 02/04/06: Re: How to probe internal signals from Xilinx netlist?
41751: 02/04/06: Re: strange RAM timing problem (VirtexE)
42229: 02/04/18: Re: 1000 I/O Pins -- What is cheapest FPGA?
42236: 02/04/18: Re: fpga limitation
42239: 02/04/18: Re: FPGA Timing Problem
42245: 02/04/18: Re: prototyping an ASIC
42252: 02/04/18: Re: GND Outputs being optimized out using FPGA Express 3.6.1 in ISE4.2.01
42292: 02/04/19: Xilinx Easypath- Selling parts with known defects
42295: 02/04/19: Re: fpga limitation
42307: 02/04/19: Re: ModelSim closes for unknown reason
42352: 02/04/21: Re: Xilinx Easypath- Selling parts with known defects
42403: 02/04/22: Re: Xilinx Easypath- Selling parts with known defects
42417: 02/04/23: Re: Maximum Usage in a Virtex FPGA
42473: 02/04/24: Re: Using PAL/GAL/FPGA to replace CPU's (correct news group?)
42474: 02/04/24: Re: Xilinx Easypath- Selling parts with known defects
42503: 02/04/25: Re: Input Frequence
42510: 02/04/25: Re: configuration mystery
42743: 02/05/01: Vertex 2 IOB- unwanted flops inside
42793: 02/05/02: Re: Vertex 2 IOB- unwanted flops inside
42830: 02/05/03: Xilinx 2GB limit... something has to be done
43152: 02/05/14: Re: Driving high speed external devices from an FPGA
43153: 02/05/14: Re: Bus arbiter with low latency
43225: 02/05/16: Re: 50 mA sink
43602: 02/05/26: Re: Xilinx chip scope: Comments
43603: 02/05/26: Re: P&R times
43713: 02/05/30: Re: about Configure FLEX10K10 with 89c51
43771: 02/06/01: Re: CMOS camera
43809: 02/06/03: Re: Looking for FPGA board with USB interface
43810: 02/06/03: Re: Pipelining
43812: 02/06/03: Re: Clock double trigger problem
43901: 02/06/05: Re: synthesis issue
43902: 02/06/05: Re: Do I have metastability issues?
43904: 02/06/05: Re: chipscope
43934: 02/06/06: Re: xc3042
43937: 02/06/06: Re: How to add delay in fpga(spartan)?
44077: 02/06/11: Re: where did my MHz go!
44080: 02/06/11: Re: OFFSET constraint for internal clock
44102: 02/06/11: Re: burning a design
44103: 02/06/11: Re: Busses & permutations
44137: 02/06/12: Re: where did my MHz go!
44141: 02/06/12: Re: virtual ground in Xilinx XC9572 CPLD?
44195: 02/06/13: Re: clock gating by any other name...
44196: 02/06/13: Re: constrains for external memory
44201: 02/06/13: Re: fpga and ultra highspeed counters
44479: 02/06/20: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
44480: 02/06/20: Re: fpga and ultra highspeed counters
44519: 02/06/21: Re: Logic Minimization in Max+Plus II compiler
44534: 02/06/22: Re: Bad Virtex2 devices - any similar experiences
44625: 02/06/24: Re: skew control between different signals ?
44626: 02/06/24: Re: Will this clock divider be good on hardware?
44659: 02/06/25: Re: too hot fpga device
44687: 02/06/26: Re: fast adders using HDL in Xilinx fpga
44725: 02/06/27: Re: VIRTEX II DCM Question
44757: 02/06/29: Re: VIRTEX II DCM Question
44759: 02/06/29: Re: Altera equivalent for GAL 16V8
44760: 02/06/29: Re: Programming a Xilinx CPDL with a Microcontroller
44761: 02/06/29: Re: clock skew in quartus, not in maxplus
44849: 02/07/02: Re: VHDL Compliation Problem in Synario
44850: 02/07/02: Re: Converting to Altera Quartus
45180: 02/07/14: Re: Sensitivity list (VHDL) & FPGA pin assignment
45181: 02/07/14: Re: 6 parallel inputs to Mux? How?
45219: 02/07/16: Re: I want to buy 4 Xilinx FPGA
45251: 02/07/17: Re: problem porting sync write, async read RAM to Xilinx...
45252: 02/07/17: Re: Security features
45255: 02/07/17: Re: Xilinx (spartan 2) - SI even applies to the config pins
45257: 02/07/17: Re: dsp v fpga
45403: 02/07/22: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
45405: 02/07/22: Re: Verilog newbie question
45690: 02/08/01: Re: Who can compare the synthesis tools for me ?
45875: 02/08/08: ... milk for free, Opencores?
45876: 02/08/08: Re: Asynchronous signals recommendations?
45877: 02/08/08: Re: Xilinx TIG
45880: 02/08/08: Re: Xilinx hiring practises
45937: 02/08/11: Re: ASIC conversion
47294: 02/09/22: Re: Can a fpga replace external inverters in a crystal osc ?
47427: 02/09/25: Re: PCB Design for Altera FPGA
47428: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
47474: 02/09/26: Re: Dual Port RAM
47583: 02/09/29: Re: Chipscope cores
47834: 02/10/04: Re: system item in synplify report
47919: 02/10/07: Re: .13 micron - what does it indicate
48106: 02/10/10: Re: Gate array & standard cell based design.
48107: 02/10/10: Re: extreme cell usage minimization req.
48155: 02/10/11: Re: How to keep components from being optimized out of VHDL
48156: 02/10/11: Re: Sync Reset without clocks
48464: 02/10/17: Re: Quartus design question
48585: 02/10/21: Re: Transferring Design from XILINX --> ALTERA
48626: 02/10/21: Re: Buy Small quantities
48688: 02/10/22: Re: low power embedded FPGA
48743: 02/10/23: Re: Serial PROM Configuration
48746: 02/10/23: Re: Altera FPGA and EPLD Download ByteBlaster
48751: 02/10/23: Re: clock divider
48884: 02/10/25: Re: DLL and PLL in Xilinx and Altera
48885: 02/10/25: Re: Who has some Lecture materialson I2C Bus?
48886: 02/10/25: Re: GlobalReset hogging routing resources
48936: 02/10/27: Re: #1's in verilog
49044: 02/10/30: Re: Can we retaining EAB Data using BACK UP power SUPPLY for Vccint
49045: 02/10/30: Re: GlobalReset hogging routing resources
49078: 02/10/31: Re: How important is simulation?
49145: 02/11/01: Re: How important is simulation?
49146: 02/11/01: Re: FPGA convert to ASIC
49177: 02/11/04: Re: Incremental design question
49181: 02/11/04: Re: Excessive heating on Xilinx XC9500XL
49336: 02/11/09: Re: LUT Consumption in Virtex-2
49363: 02/11/10: Re: VersaRing
49367: 02/11/10: Re: Unexplained signal interaction
49368: 02/11/10: Re: Quicklogic PAsic problem
49370: 02/11/11: Re: FPGA convert to ASIC
49480: 02/11/12: Re: Registering inputs or outputs of modules
49481: 02/11/12: Re: How to disable IOB register packing?
49519: 02/11/13: Re: creating a fabric in an FPGA
49821: 02/11/21: Re: clock enable timing analysis
49822: 02/11/21: Re: Virtex timing problem
49823: 02/11/21: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49824: 02/11/21: Re: programmable oscillator for Virtex-E (XCV2000E)
49830: 02/11/21: Re: exp^x in virtex 2
49902: 02/11/24: Re: What's the matter with "clock skew and data delay"?
49917: 02/11/25: Re: What's the matter with "clock skew and data delay"?
50015: 02/11/28: question about PCB traces for FPGA board... ?
50017: 02/11/28: Re: Custom FPGA synthesis
50121: 02/12/02: Re: string to int conversion
50191: 02/12/04: Re: ISA bus VGA
50192: 02/12/04: Re: Full-Page in SDRAM
50193: 02/12/04: Re: Clock fan-out and other issues
50255: 02/12/06: Re: Full-Page in SDRAM
50256: 02/12/06: Re: meaning of system gates vs. logic gates?
50449: 02/12/10: Re: question about fft vs. cross corelation in fpga
50570: 02/12/12: Re: Two clocks for the same module
50571: 02/12/12: Re: Distributed RAM in cyclone
50604: 02/12/13: Re: Hold violation in synthesis but not fitting
50605: 02/12/13: Re: Two clocks for the same module
50606: 02/12/13: Re: Distributed RAM in cyclone
50607: 02/12/13: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
50609: 02/12/13: Re: Can I use bus keeper like this?
50697: 02/12/17: Re: Is it true that if you have a clock routed to non-clock resources then you are not allowed to use the clock nets?
50698: 02/12/17: Re: Xilinx FPGA PAR warning
50710: 02/12/17: Re: Video timing generator on a Flex 20K / Acex 1K.
50903: 02/12/22: Re: I didn't understand altera's max+plus2 software to setting up.
50904: 02/12/22: Re: FPGA Supercomputing opportunity
51126: 03/01/02: Re: BP programmer questions, prices, alternatives
52339: 03/02/06: Re: Clock Enables
52390: 03/02/07: Re: Clock Enables
56118: 03/05/29: Re: Multiply 19.44MHz with Virtex-II DCM
56197: 03/05/30: Is something wrong with ISE5.1 simulation library
56441: 03/06/05: ASIC prototype software
57062: 03/06/23: Re: What's the difference between ASIC and FPGA?
57064: 03/06/23: Virtex-II's IO Level?
57229: 03/06/26: Everything need a reset?
57616: 03/07/03: post-PAR simulation model
57697: 03/07/04: Re: post-PAR simulation model
57698: 03/07/04: Re: Everything need a reset?
57776: 03/07/06: Re: DCM usage question
58061: 03/07/13: Re: Graduation Day: My first 4-layer PCB
58098: 03/07/15: Re: problems on using CLKDLL in Xilinx ISE
58107: 03/07/15: Re: An All Digital Phase Lock Loop
58219: 03/07/17: Re: An All Digital Phase Lock Loop
58292: 03/07/19: Phase / frequency detector types
58558: 03/07/26: Simple circuit / good design?
58660: 03/07/30: PLL / DPLL phase question
58792: 03/08/01: Re: PLL / DPLL phase question
58853: 03/08/02: Re: PLL / DPLL phase question
58883: 03/08/04: Gates Counting?
58887: 03/08/04: Re: Gates Counting?
58952: 03/08/05: Conflict found between ActiveHDL6.1 and ModelSim SE
58999: 03/08/06: Re: Conflict found between ActiveHDL6.1 and ModelSim SE
59044: 03/08/07: Re: Gates Counting?
59076: 03/08/07: Re: Size does matter
59285: 03/08/14: Anyone familiar with ispXPLD?
59422: 03/08/19: Re: Anyone familiar with ispXPLD?
59431: 03/08/19: Re: Anyone familiar with ispXPLD?
59491: 03/08/20: Re: performance tweaking FPGA designs
59697: 03/08/26: Multi-clock / clocking counter
59722: 03/08/27: Asynchronous clock switching circuits vs. BUFGMUX
59763: 03/08/27: Re: Multi-clock / clocking counter
59861: 03/08/30: Re: DCM divide/phase problem
59862: 03/08/30: Re: Selecting between two clock signals
59982: 03/09/03: OT: Block diagramming tools?
60065: 03/09/04: Flex6K configuration PROM
60099: 03/09/05: Re: Flex6K configuration PROM
60100: 03/09/05: Re: Flex6K configuration PROM
60103: 03/09/05: Re: Flex6K configuration PROM
60225: 03/09/08: Re: Flex6K configuration PROM
62154: 03/10/21: Re: please help, modelsim does not simulate
62397: 03/10/29: Re: BoardScope
62400: 03/10/29: Re: Virtex-II DCM frequency synthesizer
63145: 03/11/17: Vertex-II configuration in slave SelectMap mode
63150: 03/11/17: ISE5.2 on solaris, can't use promgen
63201: 03/11/18: Re: ISE5.2 on solaris, can't use promgen
63202: 03/11/18: Re: Xilinx Design entry via Schematic Capture - What tool to use ?
63413: 03/11/21: Re: Does anyone know anything about DC-FPGA?
63588: 03/11/26: Input pins without Vcco supply-- Virtex-II
63637: 03/11/27: Re: Input pins without Vcco supply-- Virtex-II
64575: 04/01/08: Re: iMPACT error : Done did not go high.
64576: 04/01/08: Re: DPRAM using the CoreGenerator, VHDL-example
64749: 04/01/13: Re: using signal as clk source
66104: 04/02/12: Re: Programmable clock, FPGA PLLs, and Actel PLL Core
69037: 04/04/26: Re: PLL and DLL
112527: 06/11/23: Are FPGAs available with ADCs onchip ?
120908: 07/06/20: How to use UART on Spartan 3E Starter Kit
120911: 07/06/20: Re: How to use UART on Spartan 3E Starter Kit
133697: 08/07/10: Re: Altera FPGA and data from matlab workspace.
148843: 10/09/02: Re: Xilinx Series 7 device availability
150551: 11/01/26: Interfacing with a 5v micro controller
150559: 11/01/26: Re: Interfacing with a 5v micro controller
150573: 11/01/26: Re: Interfacing with a 5v micro controller
150593: 11/01/27: Re: Interfacing with a 5v micro controller
150600: 11/01/27: Re: Interfacing with a 5v micro controller
150613: 11/01/28: Re: How to place some delay blocks adjacent to each other after Xilinx ISE P&R tool?
150847: 11/02/16: Re: Xilinx USB programming cable.
Jay Berg:
37582: 01/12/16: Certicom challenge and FPGA based modular math
37591: 01/12/16: Re: Certicom challenge and FPGA based modular math
37593: 01/12/16: Re: Certicom challenge and FPGA based modular math
37594: 01/12/16: Re: Certicom challenge and FPGA based modular math
37609: 01/12/17: Re: Certicom challenge and FPGA based modular math
37611: 01/12/17: Re: Certicom challenge and FPGA based modular math
37613: 01/12/17: Re: Certicom challenge and FPGA based modular math
37644: 01/12/18: Re: Certicom challenge and FPGA based modular math
Jay Darmon:
9182: 98/02/28: The case for Linux and EDA
9360: 98/03/07: Re: The case for Linux and EDA (Vox Populi?)
Jay Francis:
2356: 95/11/22: Re: Device Programmer Selection
2371: 95/11/24: Re: (no subject)
2372: 95/11/24: Re: (no subject)
Jay K:
141338: 09/06/18: Spartan 3A vs 3E SSO guidelines
Jay Lessert:
2396: 95/11/28: Re: Lattice GAL16VP8 -is it real ?
8334: 97/12/09: Re: what is metastability time of a flip_flop
8337: 97/12/09: Re: what is metastability time of a flip_flop
17297: 99/07/19: Re: License sharing for synopsys/cadence/modeltech
17316: 99/07/20: Re: License sharing for synopsys/cadence/modeltech
jay mitchell:
38336: 02/01/11: Re: asic vs. fpga
Jay Southard:
1124: 95/05/02: Re: Viewlogic VHDL for Xilinx
jay.diem:
151208: 11/03/15: HiTech Global Virtex5 PCIe Board
jaya:
133653: 08/07/08: How do I send data and receive data from the FPGA and simulink/matlab
134084: 08/07/24: Using signal tap analysis with multiple clock domains in Simulink
134783: 08/08/29: Serial port issues with Matlab
Jaya Rajesh:
17123: 99/07/01: Re: ALTERA GDF to VHDL QUESTION
17138: 99/07/02: Re: ALTERA GDF to VHDL QUESTION
Jaya_Kanajan:
9957: 98/04/17: state machine
<jayadeep90kodali@gmail.com>:
157050: 14/09/16: Comparision of Advantages/Disadvantges of Verilog or VHDL in Hardware verification
Jayant Nagda:
15637: 99/04/05: Re: Application Consulting Engineer (ACE)
jayantbala:
140425: 09/05/13: connecting FPGA with PC using ethernet MAC layer only
140455: 09/05/14: Re: connecting FPGA with PC using ethernet MAC layer only
140458: 09/05/14: EDK Enviorment setting problem
141201: 09/06/11: XILINX WEB SERVER DEMO
<jayanth.kalvakuntla1996@gmail.com>:
160471: 18/01/31: Interface on board ADC to Spartan 3E startkit
160473: 18/02/03: Re: Interface on board ADC to Spartan 3E startkit
160474: 18/02/03: Re: Interface on board ADC to Spartan 3E startkit
160478: 18/02/04: Re: Interface on board ADC to Spartan 3E startkit
160479: 18/02/04: Re: Interface on board ADC to Spartan 3E startkit
160480: 18/02/04: Re: Interface on board ADC to Spartan 3E startkit
Jayaram_Bhasker:
1150: 95/05/05: Call for Papers: Fall95 VIUF
<jayblue_16@yahoo.com>:
130596: 08/03/27: Re: problem simulating in modelsim - swiftpli_mti.dll
<jayloveben@hotmail.com>:
152823: 11/10/26: newable need help
<jaymode@gmail.com>:
128395: 08/01/24: EDK 9.2i install issues in Linux
128448: 08/01/26: Re: EDK 9.2i install issues in Linux
<jaypt123@my-deja.com>:
27113: 00/11/11: Webpack 3.2WP3.x from Xilinx is useless
jaypt@hotmail.com:
70970: 04/07/03: A simple VHDL question
71586: 04/07/22: How to program a spartan-3
<jazimme2@yahoo.com>:
85721: 05/06/14: Re: Help with USB cable, Xilinx XUP board, Linux FC3 and EDK
85749: 05/06/15: Re: Help with USB cable, Xilinx XUP board, Linux FC3 and EDK
jazzy_21:
149844: 10/11/28: MicroBlaze Simulation Question
JB:
41648: 02/04/04: Monostable multivibrator
150260: 11/01/07: Detecting cold reset on flash FPGA
150264: 11/01/07: Re: Detecting cold reset on flash FPGA
150273: 11/01/07: Re: Detecting cold reset on flash FPGA
151992: 11/06/20: Sporadic simulation result with modelsim
151994: 11/06/20: Re: Sporadic simulation result with modelsim
152012: 11/06/21: Re: Sporadic simulation result with modelsim
152013: 11/06/21: Re: Sporadic simulation result with modelsim
152017: 11/06/22: Re: Sporadic simulation result with modelsim
152035: 11/06/23: Re: Sporadic simulation result with modelsim
jb:
44816: 02/07/02: Re: How can I preserve FFs in LeonardoSpectrum?
60466: 03/09/14: logic from jed file
60470: 03/09/14: Re: logic from jed file
147921: 10/06/02: Re: How good are Actel tools
<jb@capsec.org>:
127675: 08/01/05: Re: DDR SDRAM demo for Spartan-3E starter kit?
127695: 08/01/05: Re: DDR SDRAM demo for Spartan-3E starter kit?
127713: 08/01/06: Re: DDR SDRAM demo for Spartan-3E starter kit?
127786: 08/01/08: Re: DDR SDRAM demo for Spartan-3E starter kit?
130343: 08/03/20: Re: ISE 10.0 finally with multi-threading and SV support ?
<jb@nospam.com>:
53845: 03/03/25: Re: Permanent Local Damage to FPGA
<jball99653@aol.com>:
20610: 00/02/16: Re: clock
jbj:
145310: 10/02/05: ISPLever, devlist command
jbnote:
110058: 06/10/10: Virtex-4 configuration details
110281: 06/10/13: Xilinx documentation typos
110583: 06/10/18: from LUT contents to boolean equation
110588: 06/10/18: Re: from LUT contents to boolean equation
110777: 06/10/22: Virtex4 debug bitstream generation problem
111034: 06/10/27: Re: Xilinx documentation typos
111421: 06/11/02: Re: Dual-port BlockRAM "write first" puzzler...
112179: 06/11/17: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112239: 06/11/18: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112276: 06/11/19: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112280: 06/11/19: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112283: 06/11/19: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
113631: 06/12/18: Re: incremental compiles in quartus
114648: 07/01/22: Re: "Divide" a video line in two stripe
114650: 07/01/22: Re: "Divide" a video line in two stripe
114652: 07/01/22: Re: "Divide" a video line in two stripe
114746: 07/01/23: Re: FPGA damage from bad bitstream
114748: 07/01/23: Re: Xilinx ISE 8.2
114773: 07/01/24: Re: "Divide" a video line in two stripe
114775: 07/01/24: Re: FPGA damage from bad bitstream
114861: 07/01/25: Re: video buffering scheme, nonsequential access (no spatial locality)
115235: 07/02/04: Re: Xilinx Interconnects/Routing
115240: 07/02/04: Re: Xilinx Interconnects/Routing
116673: 07/03/15: Re: .bit file to VHDL/verilog source code
116691: 07/03/15: Re: .bit file to VHDL/verilog source code
117949: 07/04/13: Re: Where is Open Source for FPGA development?
117954: 07/04/14: Re: Where is Open Source for FPGA development?
<jbnote@gmail.com>:
105594: 06/07/26: Re: Calculate CRC in Virtex-Spartan II bitstream
105808: 06/08/01: Re: Quick way to change Xilinx BRAM init values
105819: 06/08/01: Re: Quick way to change Xilinx BRAM init values
106426: 06/08/13: Re: virtex II inner organisation
<jboothbee@gmail.com>:
97057: 06/02/15: Re: digital logic library by 74xxxx part number?
jbs80922:
77205: 04/12/29: Rocket I/O Fail modes/problems help
jc:
1446: 95/06/23: Job Opportunities in UK: ATM (RBB) VHDL/C++ ASIC/FPGA
10697: 98/06/11: Re: Are you looking for a good VHDL/Verilog Editor?
64509: 04/01/06: Xilinx Virtex II Output Register
142432: 09/08/11: DDR2 Controllers: Bursting to Odd Addresses
142435: 09/08/11: Re: DDR2 Controllers: Bursting to Odd Addresses
145113: 10/01/28: Re: Please help, Xilinx FIFO problem!
145116: 10/01/28: Re: Please help, Xilinx FIFO problem!
145699: 10/02/19: Re: Unpredictable design
145774: 10/02/23: Re: System design in FPGA
149158: 10/10/05: Re: FPGA design not working!
149579: 10/11/08: Re: Statemachine debugging with Chipscope
149586: 10/11/08: Re: Statemachine debugging with Chipscope
149593: 10/11/09: Re: Statemachine debugging with Chipscope
149611: 10/11/11: Re: Statemachine debugging with Chipscope
149627: 10/11/12: Re: Statemachine debugging with Chipscope
149634: 10/11/12: Re: Statemachine debugging with Chipscope
149635: 10/11/12: Re: Statemachine debugging with Chipscope
149706: 10/11/19: Re: What is the meaning of 'combinatorial path crossing multiple units'?
149759: 10/11/23: Re: Synthesis/place and route with Solid-State Drives
149787: 10/11/24: Re: Synthesis/place and route with Solid-State Drives
149818: 10/11/25: Re: Synthesis/place and route with Solid-State Drives
149837: 10/11/26: Re: Multiple clock domains
149850: 10/11/28: Re: Synthesis/place and route with Solid-State Drives
149949: 10/12/03: Re: FSM single process...BIG question
149972: 10/12/04: Re: FSM single process...BIG question
150192: 10/12/30: Re: Error in Clock Divider!
150245: 11/01/05: Re: Transfer data from one clock domain to another clock created by
151489: 11/04/13: Re: Source of Dynamic Power Consumption in FPGAs
151641: 11/04/29: Re: same RTL on two same boards giving different behaviour
151770: 11/05/16: Re: Random behavior of xilinx simple dual port block ram
151848: 11/05/24: Re: comparator fast implementation
151938: 11/06/10: Re: multiplication in indexation
151999: 11/06/21: Re: Sporadic simulation result with modelsim
152028: 11/06/23: Re: Sporadic simulation result with modelsim
152034: 11/06/23: Re: Sporadic simulation result with modelsim
152185: 11/07/17: Re: RTL timing issue
jcain:
10908: 98/06/29: Sr. Hardware Engineer?
jcalder:
7609: 97/09/26: USB Legacy Implementation
jcarr@linuxmachines.com:
89193: 05/09/07: Re: Spartan-3E Starter Kit availability slips to December
jcding:
38719: 02/01/23: Analog input into Altera FLEX10K using ADC. Can anyone help??
38757: 02/01/24: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
38789: 02/01/25: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
<jcpsoft@my-deja.com>:
16744: 99/06/06: Digital Filter Design Software
<jcr_alr@xplornet.com>:
122650: 07/08/02: DOSFS for EDK
127217: 07/12/14: Re: FPGA Board design basics
127263: 07/12/16: Re: Spartan-3E starter kit, what's "J8" 6-pin for?
127555: 08/01/02: Re: Where are the LCD or OLED bitmapped displays?
128763: 08/02/05: Problems with GDB in EDK 9.2
128832: 08/02/07: Re: Problems with GDB in EDK 9.2
<jcurren@my-deja.com>:
19411: 99/12/20: Re: hobbyist friendly pld?
<jcvilleneuve@hotmail.com>:
11571: 98/08/25: PROM alternative
jd:
116838: 07/03/19: a project work
JD Newcomb:
115408: 07/02/09: Applications under MontaVista Linux on ML310
115419: 07/02/09: Re: Interrupts and PPC/opb_intc
121551: 07/07/08: XPS 8.2 "UPDATE Tcl procedures"?
121606: 07/07/09: Re: Build error for multiprocessor sytem.
121618: 07/07/10: Re: XPS 8.2 "UPDATE Tcl procedures"?
122327: 07/07/25: EDK Microblaze project without OPB?
123180: 07/08/18: Re: EDK 9.1.02i warnings flood
127740: 08/01/06: MicroBlaze floating point precision issues
127744: 08/01/06: Re: MicroBlaze floating point precision issues
127759: 08/01/07: Re: MicroBlaze floating point precision issues
JD_Design:
83527: 05/05/02: Xilinx V4 Power Calculations
83587: 05/05/03: Re: Xilinx V4 Power Calculations
83590: 05/05/03: Re: Xilinx V4 Power Calculations
83602: 05/05/03: Re: Xilinx V4 Power Calculations
83637: 05/05/04: Re: Xilinx V4 Power Calculations
83694: 05/05/05: Re: Xilinx V4 Power Calculations
83710: 05/05/05: Re: Xilinx V4 Power Calculations
87228: 05/07/19: Virtex-4 hot-swappable?
87859: 05/08/02: Re: Virtex-4 hot-swappable?
88108: 05/08/09: Re: Virtex-4 hot-swappable?
<jdaughenb@my-deja.com>:
29003: 01/02/01: Re: More then 4 Clocks
<jdehaven@my-dejanews.com>:
12995: 98/11/10: Re: Why doesn't Xilinx's simulator work?
13215: 98/11/20: Re: Serial EPROMs
jdhduighejhvkxjcn:
28180: 00/12/24: Re: driving color VGA from FPGA ??
jdiaz_pr:
32743: 01/07/06: Floating Point SQRT
32927: 01/07/11: FPGA-based board vs bigger FPGA
33713: 01/08/02: Simple Division by Shift/Add (2nd try)
34918: 01/09/13: Foundation 3.1i REINSTALLATION
34919: 01/09/13: Looking for knowledge on CORDIC, division, correlators, TSBs, sorting, and path-delay handling
Jdon:
91616: 05/11/09: Rocket IO reset problem
99253: 06/03/21: need help on asynchronous buffer
99256: 06/03/21: Re: need help on asynchronous buffer
99257: 06/03/21: Re: need help on asynchronous buffer
JDS:
53236: 03/03/07: Multipliers Architectures use on FPGA COREGEN
53276: 03/03/09: Minimum Real-state K-multiplier/divider
53464: 03/03/13: Path delay and timer question
53518: 03/03/14: Re: Path delay and timer question
55461: 03/05/08: Missing App Notes
<jdy0803@hotmail.com>:
78299: 05/01/28: How do I get the contents in FPGA
78413: 05/01/31: FPGA configration Data/Firmware
Jean Lachance:
4674: 96/11/28: Re: How to utilize XC4000e IOB FFs in Synopsys?
JEAN NICOLLE:
23938: 00/07/17: better than a long explanation, the LFSR testbench
Jean Nicolle:
27574: 00/11/29: Re: Fifo design problem
27748: 00/12/06: Re: ALTERA MAX PLUS LPM FIFOs
56122: 03/05/29: fpga4un
56532: 03/06/08: tiny FPGA board
56651: 03/06/10: Re: Learning FPGAs
56780: 03/06/15: fpgas are fun
56930: 03/06/19: Re: Altera FPGA
57057: 03/06/22: fpga4fun
57089: 03/06/23: Re: fpga4fun
57179: 03/06/25: Re: fpga4fun
57447: 03/06/30: pong game
57775: 03/07/07: control R/C servos with FPGAs
57810: 03/07/07: Re: Altera licenses
59138: 03/08/09: Re: I am new and I want to help
59402: 03/08/18: Re: serial communication between pc and altera fpga
59692: 03/08/26: How to listen to music through an FPGA pin?
59895: 03/08/31: Re: How to listen to music through an FPGA pin?
59903: 03/09/01: Re: Xilinx bit files
60106: 03/09/05: Sending and receiving Ethernet traffic
60130: 03/09/05: Re: Sending and receiving Ethernet traffic
60239: 03/09/09: Re: Sending and receiving Ethernet traffic
60291: 03/09/10: Re: VGA display
62574: 03/11/02: Re: Minimalist RS232 on Cyclone
63146: 03/11/17: Re: getting started in FPGA
63483: 03/11/22: Re: Affordable Development Board
63640: 03/11/27: Re: Slightly unmatched UART frequencies
63988: 03/12/11: Re: Soldering of FPGAs
64046: 03/12/13: Re: advantages of ethernet MAC ip core
64050: 03/12/14: Re: advantages of ethernet MAC ip core
64435: 04/01/04: Re: rs-232 trouble
64560: 04/01/07: Tutorials for ISE and Quartus
64564: 04/01/07: Re: Tutorials for ISE and Quartus
64757: 04/01/13: Send Ethernet traffic from an FPGA
64775: 04/01/13: Re: Send Ethernet traffic from an FPGA
64811: 04/01/14: Re: Send Ethernet traffic from an FPGA
64998: 04/01/18: Re: Send Ethernet traffic from an FPGA
64999: 04/01/18: Re: Send Ethernet traffic from an FPGA
65001: 04/01/18: Re: fpga4fun
65023: 04/01/19: Re: Send Ethernet traffic from an FPGA
65085: 04/01/20: Re: Send Ethernet traffic from an FPGA
65298: 04/01/23: Re: Send Ethernet traffic from an FPGA
65461: 04/01/29: Re: FPGA basics
65464: 04/01/30: Re: Where to get FPGA devices for testing?
65497: 04/01/31: Re: Where to get FPGA devices for testing?
65498: 04/01/31: Re: Where to get FPGA devices for testing?
65534: 04/02/01: Differences between Xilinx ISE and Altera Quartus software
65541: 04/02/01: Re: Differences between Xilinx ISE and Altera Quartus software
65543: 04/02/01: Re: Differences between Xilinx ISE and Altera Quartus software
65544: 04/02/01: Re: Clocking an FPGA??
65547: 04/02/02: Re: Differences between Xilinx ISE and Altera Quartus software
65583: 04/02/03: Re: Differences between Xilinx ISE and Altera Quartus software
65584: 04/02/03: Re: Differences between Xilinx ISE and Altera Quartus software
65805: 04/02/06: Re: Differences between Xilinx ISE and Altera Quartus software
65845: 04/02/08: Re: Differences between Xilinx ISE and Altera Quartus software
65846: 04/02/08: Re: Differences between Xilinx ISE and Altera Quartus software
66149: 04/02/13: Re: Programmable clock, FPGA PLLs, and Actel PLL Core
66199: 04/02/14: Re: Programmable clock, FPGA PLLs, and Actel PLL Core
67773: 04/03/19: Re: PCI Development Board
68016: 04/03/24: Re: cheapest & best FPGA???
68510: 04/04/07: Re: Cyclone and ByteBlasterMV?
70042: 04/05/28: Re: How to generate a 320x200 VGA signal?
70060: 04/06/01: Re: solderless breadboard + fpga + smt-adaptable socket?
80368: 05/03/04: Re: Newby Getting started with FPGA
83104: 05/04/23: is the 8051 architecture public domain?
102220: 06/05/12: JTAG tutorial
102260: 06/05/12: Re: JTAG tutorial
102261: 06/05/12: Re: JTAG tutorial
112613: 06/11/26: vccaux and vccint
112624: 06/11/27: Re: vccaux and vccint
113259: 06/12/09: Re: FPGA+Ethernet
116251: 07/03/05: Multiple devices within one ISE project
Jean Paul Heron -COD-RW:
4013: 96/09/03: Xact 6000
Jean Williams:
32250: 01/06/21: Help with VHDL
Jean-Baptiste:
148470: 10/07/26: Performing incremental code coverage with modelsim
jean-baptiste:
98669: 06/03/14: Re: slice macro replace the bus macro in the virtex-4 how to do that?????
Jean-Baptiste Monnard:
35024: 01/09/18: Re: Altera Quartus II: Ouput skew ;-(
35174: 01/09/25: Re: How to fix the hold time violation (clock skew>data skew) in QuartusII
39949: 02/02/22: Re: Pin assignments in QUARTUS
<jean-baptiste.nouvel@jdsu.com>:
104856: 06/07/07: PCI IOs, tiofoi, source sampling bypass
104862: 06/07/07: Re: PCI IOs, tiofoi, source sampling bypass
104972: 06/07/11: Re: PCI IOs, tiofoi, source sampling bypass
104973: 06/07/11: Re: PCI IOs, tiofoi, source sampling bypass
104982: 06/07/11: Re: High-speed DAC/ADC with FPGA
104984: 06/07/11: Re: High-speed DAC/ADC with FPGA
116549: 07/03/12: /* synopsys enum state_code */ on XST???
116550: 07/03/12: Heatsink on FPGA?
116622: 07/03/14: Re: Heatsink on FPGA?
116623: 07/03/14: Re: Heatsink on FPGA?
116749: 07/03/16: Re: Xilinx FPGA, OFFSET OUT AFTER
Jean-francois Hasson:
17977: 99/09/20: Maxplus+II and constraints on a MAX9000 chip
jean-francois hasson:
25088: 00/08/25: PCI macros
26374: 00/10/13: 5V compatible Virtex
28899: 01/01/28: Actel's FPGA : A54SX32A
29005: 01/02/01: A54SX type FPGA from ACTEL questions
39988: 02/02/23: Question about multiple Virtex DLLs locking management after configuration
59097: 03/08/08: Clocking in a virtex 2 without using the clock trees : questions
59186: 03/08/11: Re: Clocking in a virtex 2 without using the clock trees : questions
59277: 03/08/13: Skew on a clock tree on a virtex II : what is the good figure ?
59296: 03/08/14: Re: Skew on a clock tree on a virtex II : what is the good figure ?
59927: 03/09/01: DDR capabilities of a Virtex II device
60136: 03/09/05: Automatic signal fanout management in an FPGA (Xilinx type in this case)
62470: 03/10/30: CLKFX problem with a Virtex II
63883: 03/12/07: Skew between the output of a DCM ?
63976: 03/12/10: Re: Skew between the output of a DCM ?
64942: 04/01/16: Impact of voltage variations on timings for an FPGA
69186: 04/04/29: package choice, temperature and obsolesence issues with a xilinx fpga
72331: 04/08/15: SSO and other banks behavior of Xilinx FPGAs
72534: 04/08/23: SSO and decoupling relationship
72548: 04/08/24: Maximum allowable ground bounce for xilinx fpgas
80313: 05/03/03: Jitter calculation for RocketIO reference clock
82711: 05/04/16: rocketio decoupling
108297: 06/09/07: Altera CPLD 7128S heating up
109092: 06/09/20: Use of XMD in EDK7.1i
109114: 06/09/21: Profiling issue with EDK 7.1
139832: 09/04/15: Synchronous clocking between Cyclone III and SDRAM
Jean-Francois Richard:
16270: 99/05/13: floating points to fixed points on a FPGA
16271: 99/05/13: Reference on word lenght quantization
Jean-Jacques Bordes:
62228: 03/10/22: Re: mp3 project
Jean-Louis VERN:
9695: 98/03/31: Re: New radix-4 CORDIC for computing sine and cosine
Jean-Luc:
58659: 03/07/30: apex20ke library and simulation
58702: 03/07/31: Re: apex20ke library and simulation
Jean-Luc Cooke:
47601: 02/09/30: Diving in for the first time
47602: 02/09/30: correction
Jean-Luc danger:
17693: 99/08/24: APEX20K boards
Jean-Luc Nagel:
22647: 00/05/16: PC104+ FPGA Board
22666: 00/05/17: Re: PC104+ FPGA Board
22695: 00/05/18: Re: PC104+ FPGA Board
jean-marc:
20483: 00/02/11: Processing a sdf file
Jean-Marc Bourguet:
28294: 01/01/05: Re: Nondeterministic FSMs in hardware?
Jean-Marc Lienher:
152935: 11/11/02: Re: draw lines, circles, squares on FPGA by mouse and display on
Jean-marc Lienher:
159566: 16/12/31: Re: Slightly OT: Digital watch circuits
160566: 18/04/14: Re: FPGA selection recommendation
Jean-Marc REMONDEAU:
8703: 98/01/21: Re: complex number challenge
Jean-Marie Bussat:
24480: 00/08/10: Viewlogic to Orcad conversion
27033: 00/11/08: Re: Anything wrong with Xilinx website?
30220: 01/03/28: VHDL question
30228: 01/03/28: Re: VHDL question
30254: 01/03/29: Re: VHDL question
30280: 01/03/30: Re: HAL-15
30578: 01/04/17: Re: Getting license for Modelsim in Xilinx webpack?
32096: 01/06/13: Re: High Speed Sampling Oscilloscope in an FPGA
Jean-Michel GUEUGNOT:
29025: 01/02/02: Re: FPGA board with lots of SRAM?
Jean-Michel Vuillamy:
3879: 96/08/14: Xilinx Product Strategy
4418: 96/10/25: Re: Synplicity vs. FPGA Express
6854: 97/07/02: Re: Verilog Simulation and Synthesis for FPGA Devices
144830: 10/01/07: Re: PMC or XMC based on Altera parts (preferably Stratix)
Jean-Paul GOGLIO:
20294: 00/02/04: Re: Spartan 2 & Foundation
20295: 00/02/04: Re: Spartan 2 & Foundation
20296: 00/02/04: Re: Spartan 2 & Foundation
20374: 00/02/08: Timing constraint on a DLL output
20375: 00/02/08: Re: Timing constraint on a DLL output
20376: 00/02/08: Re: Timing constraint on a DLL output
20378: 00/02/08: Re: Timing constraint on a DLL output
20607: 00/02/16: Re: Simulating Virtex
21855: 00/04/04: Re: JTAG programming
21896: 00/04/06: Re: JTAG programming
21903: 00/04/06: Re: JTAG programming
21930: 00/04/07: Re: multiprocessor support of IC design tools
21936: 00/04/07: Re: multiprocessor support of IC design tools
21959: 00/04/10: Re: multiprocessor support of IC design tools
21987: 00/04/11: Virtex E Pads Output Impedance
26872: 00/11/02: Bits swapping with XC18V02
27491: 00/11/24: Re: How to reduce the Tco
27500: 00/11/24: Re: How to reduce the Tco
Jean-Paul Ricaud:
8084: 97/11/17: What is the difference between CPLD and FPGA ?
Jean-Paul Smeets:
2427: 95/12/04: Xilinx vs Altera with Verilog/VHDL
4088: 96/09/09: Xilinx ViewLogic package and simulating VHDL
4089: 96/09/09: Re: ViewSynthesis and Xilinx
24294: 00/08/03: Re: Desperatly needing a SpartanII
25597: 00/09/15: Xilinx PCI interface: buy the LogiCORE or do it yourself?
29138: 01/02/07: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29291: 01/02/13: QuickLogic PCI arbiter in QAN24 completely wrong
29419: 01/02/20: Re: Altera process change....
31581: 01/05/31: Barrel shifter in Xilinx Virtex-E
Jean-Pierre Gehrig:
31246: 01/05/16: XilinxCoreLib with Renoir
Jean-Réginald Louis:
21242: 00/03/13: DSP with FPGA
21247: 00/03/13: Re: DSP with FPGA
Jean-sébastien LEROY:
128936: 08/02/11: RC340E board to sell
128984: 08/02/12: XiRisc softcore processor
129027: 08/02/13: Re: XiRisc softcore processor
129330: 08/02/21: Re: XiRisc softcore processor
129331: 08/02/21: Re: Which Linux Distro to use for Xilinx tools
129620: 08/02/29: DSP Ip Core
Jeanan Del:
33266: 01/07/20: Re: SystemC
41356: 02/03/26: Handel-C useless.. Move to SystemC
41598: 02/04/02: Re: Handel-C vs SystemC
<jeanfrancois62@gmail.com>:
139840: 09/04/15: Re: Synchronous clocking between Cyclone III and SDRAM
<jeanpaul@stack.urc.tue.nl>:
1306: 95/05/30: Re: affordable fpga design tools?
Jecel:
77953: 05/01/20: Re: Copying/Reverse Engineering PAL
78090: 05/01/24: Re: Copying/Reverse Engineering PAL
78107: 05/01/24: Re: Copying/Reverse Engineering PAL
78263: 05/01/27: Re: Copying/Reverse Engineering PAL
80529: 05/03/07: Re: Asynchronous processor !?!
82730: 05/04/16: Re: Xilinx tools on Linux
90054: 05/10/03: Re: Xilinx dev board with high quality video?
90110: 05/10/04: Re: Xilinx dev board with high quality video?
90112: 05/10/04: Re: Xilinx dev board with high quality video?
91440: 05/11/06: Re: Why Spartan-3e is the best
91538: 05/11/08: Re: Why Spartan-3e is the best
104032: 06/06/16: Re: High speed differential to single ended
107944: 06/09/02: Re: Forth-CPU design
108000: 06/09/03: Re: Forth-CPU design
108068: 06/09/04: Re: Forth-CPU design
108122: 06/09/05: Re: Forth-CPU design
108822: 06/09/17: Re: old computer architecture book
111762: 06/11/09: Re: How to send data/program to the memory of a Spartan 3 starter kit board
111831: 06/11/10: Re: JOP @ Spartan3 Starter Kit - Compile error (missing components)
111832: 06/11/10: Re: JOP @ Spartan3 Starter Kit - Compile error (missing components)
115162: 07/02/01: Webpack 9.1 problems with Impact on parallel cable
115168: 07/02/01: Re: Webpack 9.1 problems with Impact on parallel cable
124644: 07/09/28: Re: FPGA NTSC signal with 2 resistors and PWM
124677: 07/09/29: Re: FPGA NTSC signal with 2 resistors and PWM
124716: 07/10/01: Re: FPGA NTSC signal with 2 resistors and PWM
124722: 07/10/01: Re: FPGA NTSC signal with 2 resistors and PWM
124772: 07/10/03: Re: FPGA NTSC signal with 2 resistors and PWM
125514: 07/10/26: Re: FPGA vs ASIC
126852: 07/12/04: Re: Researching Reconfigurable Computing
127764: 08/01/07: Re: Processor in CPLD
128404: 08/01/24: Re: EDK 9.2i install issues in Linux
130184: 08/03/17: Re: Designing CPU
130206: 08/03/17: Re: Designing CPU
130299: 08/03/19: Re: A Challenge for serialized processor design and implementation
130345: 08/03/20: Re: A Challenge for serialized processor design and implementation
132125: 08/05/14: Re: xsa-50 issues
137059: 08/12/21: Re: Bit width in CPU cores
138659: 09/03/03: Re: Lattice announces ECP3
138702: 09/03/05: Re: Lattice announces ECP3
139071: 09/03/19: Re: Documenting a simple CPU
139326: 09/03/26: Re: Dynamic reconfiguration in Spartan 3
140633: 09/05/20: Re: Open source processors
140690: 09/05/21: Re: Open source processors
145366: 10/02/06: Re: using an FPGA to emulate a vintage computer
145401: 10/02/08: Re: using an FPGA to emulate a vintage computer
145402: 10/02/08: Re: using an FPGA to emulate a vintage computer
151563: 11/04/19: Re: NibzX7 processor
152487: 11/08/28: Re: Very cheap Spartan3 board that can be configured by simple USB
154804: 13/01/13: Re: Chisel as alternative HDL
154811: 13/01/14: Re: Chisel as alternative HDL
154824: 13/01/15: Re: Chisel as alternative HDL
156141: 13/12/09: Re: Implementing multiple interrupts
156946: 14/08/01: Re: Professional VHDL Examples?
158900: 16/05/16: Re: FPGA boards in egypt
159018: 16/06/13: Re: J1 forth processor in FPGA - possibility of interactive work?
159020: 16/06/14: Re: J1 forth processor in FPGA - possibility of interactive work?
159022: 16/06/15: Re: J1 forth processor in FPGA - possibility of interactive work?
159024: 16/06/16: Re: J1 forth processor in FPGA - possibility of interactive work?
159030: 16/06/17: Re: J1 forth processor in FPGA - possibility of interactive work?
159034: 16/06/18: Re: J1 forth processor in FPGA - possibility of interactive work?
159083: 16/07/27: Re: Mod-24: The State of High-Level Synthesis in 2016
159753: 17/02/24: Re: designing a fpga
160023: 17/05/13: Re: increment or decrement one of 16, 16-bit registers
160034: 17/05/15: Re: Pipelining on Multiple Clock Edges
160194: 17/08/03: Re: minimal HDMI pins to send video ?
160195: 17/08/03: Re: minimal HDMI pins to send video ?
160489: 18/02/13: Re: Most power efficient FPGA?
160713: 18/10/26: Re: FPGA Market Entry Barriers
jedes:
58279: 03/07/18: Multi device Altera configuration problem
58293: 03/07/19: Multi device ALTERA chain configuration problem!
JeDi:
132718: 08/06/05: HDL tricks for better timing closure in FPGAs
132787: 08/06/06: Re: HDL tricks for better timing closure in FPGAs
jedi:
80844: 05/03/12: Re: Free Stencil For SMD Soldering
88513: 05/08/21: Altera mysupport
Jedi:
77840: 05/01/18: cyclone jtag
77875: 05/01/19: Re: video decoder for altera dev. board
77876: 05/01/19: epcs prices
78119: 05/01/25: Re: epcs prices
78252: 05/01/27: Re: =?ISO-8859-1?Q?ProASIC=A7_Released?=
78253: 05/01/27: EPCS binary files...
78258: 05/01/27: Re: EPCS binary files...
78287: 05/01/28: Re: =?ISO-8859-1?Q?ProASIC=A7_Released?=
78294: 05/01/28: Is Atmel producing Altera EPCS memories???
78309: 05/01/28: Altera Quartus 4.2 Service Pack 1 fails to install
78320: 05/01/29: Re: Altera Quartus 4.2 Service Pack 1 fails to install
78322: 05/01/29: Altera subscriptions deleted?
78326: 05/01/29: Re: Is Atmel producing Altera EPCS memories???
78334: 05/01/29: Re: Altera Quartus 4.2 Service Pack 1 fails to install
78347: 05/01/30: Re: Is Atmel producing Altera EPCS memories???
78380: 05/01/31: Re: Is Atmel producing Altera EPCS memories???
78381: 05/01/31: Lattice LFEC20
78452: 05/02/01: Re: Input logic level on Spartan 3?
78466: 05/02/01: Re: Altera Quartus 4.2 Service Pack 1 fails to install
78486: 05/02/01: Synplicity and Mentor denying evaluation licenses
78552: 05/02/03: Re: Is Atmel producing Altera EPCS memories???
78583: 05/02/03: Re: Is Atmel producing Altera EPCS memories???
78623: 05/02/04: NIOS2 toolchain rebuild...
78680: 05/02/05: Altera's NIOS2 examples...
78739: 05/02/07: Re: Cyclone configuration device
78753: 05/02/07: Re: Cyclone configuration device
78843: 05/02/08: quartus "make clean" ?
78885: 05/02/09: Re: Cyclone configuration device
79029: 05/02/11: Why are the NIOS toolchain sources removed from Altera's ftp?
79427: 05/02/18: Altera support getting worse and worse......
79430: 05/02/18: nios2 flash programmer
79452: 05/02/19: Re: Graphic LCD
79583: 05/02/21: Re: NIOS2 toolchain rebuild...
80301: 05/03/03: Re: Lattice lowcost flash FPGAs announced
80518: 05/03/07: NIOS2 1.1 toolchain sources...
80846: 05/03/12: Re: Free Stencil For SMD Soldering
81425: 05/03/23: Re: Xilinx ISE 7.1 - Can this get any worse?
81965: 05/04/05: Quartus 5
84723: 05/05/25: Lattice ROM file tool....
84756: 05/05/26: ARC A4
84865: 05/05/31: Re: Nios II - Booting software from Flash
84889: 05/05/31: Altera NIOS2 50.0 SOPC periphals broken???
84892: 05/05/31: Re: Altera NIOS2 50.0 SOPC periphals broken???
84982: 05/06/02: Altera's fast NIOS update service (o;
85078: 05/06/03: Re: Altera's fast NIOS update service (o;
85106: 05/06/04: Re: ispLSI1016
85214: 05/06/06: Re: Altera NIOS2 50.0 SOPC periphals broken???
85263: 05/06/07: nios32 -> nios2 assembly porting?
85290: 05/06/07: Re: Sch & Layout Free Program
85418: 05/06/09: Lattice LFEC20 DDR SDRAM connection
85698: 05/06/14: Re: Altera's fast NIOS update service (o;
85764: 05/06/15: NIOS2 exceptions...
85971: 05/06/19: Lattice LFEC
85988: 05/06/19: use lattice and actel synplify together...
86013: 05/06/20: Re: Lattice LFEC
86017: 05/06/20: Re: Lattice LFEC
86023: 05/06/20: Re: Design tools comparison between Xilinx, Altera and Lattice for
86029: 05/06/20: Re: Lattice LFEC
86065: 05/06/21: JTAG port access in Cyclone
86085: 05/06/21: Re: JTAG port access in Cyclone
86086: 05/06/21: Re: dru files for eagle ?
86116: 05/06/22: Re: JTAG port access in Cyclone
86117: 05/06/22: Re: JTAG port access in Cyclone
86124: 05/06/22: Re: JTAG port access in Cyclone
86125: 05/06/22: Re: JTAG port access in Cyclone
86169: 05/06/22: Re: JTAG port access in Cyclone
86242: 05/06/23: NIOS2 subscription online?
86243: 05/06/23: nios2 gnu sources broken for amd64 linux
86256: 05/06/23: Re: nios2 gnu sources broken for amd64 linux
86267: 05/06/23: Re: Good FPGA introduction book ?
86300: 05/06/24: Re: Good FPGA introduction book ?
86351: 05/06/26: good bye nios (o;
86357: 05/06/26: Re: good bye nios (o;
86372: 05/06/27: Re: good bye nios (o;
86374: 05/06/27: Re: good bye nios (o;
86375: 05/06/27: Re: good bye nios (o;
86450: 05/06/28: Re: good bye nios (o;
86493: 05/06/29: xp3/xp6 in ispLever
86540: 05/06/29: Cyclone online store
86571: 05/06/30: init ProASIC3 Ram from spi
86626: 05/07/01: Re: init ProASIC3 Ram from spi
86692: 05/07/04: nios2 toolchain sources...
86714: 05/07/05: Re: nios2 toolchain sources...
86720: 05/07/05: Re: nios2 toolchain sources...
86729: 05/07/05: Re: nios2 toolchain sources...
86972: 05/07/11: Re: Bazix introduce FPGA based One Chip computer system
87022: 05/07/13: NIOS2 toolchain sources...
87028: 05/07/13: Re: NIOS2 toolchain sources...
87418: 05/07/23: Update contacts at Altera
87489: 05/07/25: Re: Update contacts at Altera
87592: 05/07/26: Re: Update contacts at Altera
<Jedi>:
117696: 07/04/07: ispLever FTP Download
117736: 07/04/09: ByteBlaster Parallel Driver for Linux > 2.6.13
117854: 07/04/11: ispLever 6.1 complains about missing libc.so.6 on Gentoo 2006.1
117857: 07/04/12: Re: ispLever 6.1 complains about missing libc.so.6 on Gentoo 2006.1
Jee:
45693: 02/08/01: Xilinx ISE 4.2: UCF file name
50739: 02/12/18: What's the easy way to port an ISE project
Jee Chi:
44194: 02/06/13: what's difference between .edf and .edn
<Jee@hotmail.com>:
49503: 02/11/13: how to name the IOBUF attribute in UCF
Jef Patat:
81390: 05/03/22: clock division using DCM, how?
Jeff:
8782: 98/01/26: Re: Radhard FPGA Vendors?
8892: 98/02/05: Re: Can XACT6 run in a NT4 DOS box?
9014: 98/02/13: Fun with Orcad Express and M1!
9214: 98/03/02: Re: ORCAD front End Tools
9283: 98/03/05: Re: ++ TMS320C6x DSP info website ++
11317: 98/08/04: Re: how much ? prices of Xilinx chips
30719: 01/04/25: What is wrong with Xilinx Foundation Simulator?
30734: 01/04/26: Bidirection port simulation
30743: 01/04/26: Bidirection Macro
42825: 02/05/03: Hard macro with Xilinx
42886: 02/05/06: Re: Hard macro with Xilinx
43545: 02/05/23: Xilinx proprietary format?
49246: 02/11/06: Re: Hard macro
49261: 02/11/06: Question about algorithm implementing in FPGA
49277: 02/11/07: Re: Question about algorithm implementing in FPGA
50566: 02/12/12: Want to buy an board with Xilinx FPGA Virtex II
50637: 02/12/15: Could you explain compact PCI, PCI and PCI bridge to me?
50908: 02/12/22: Where can I download ISE 4.x?
50913: 02/12/22: Re: Where can I download ISE 4.x?
51000: 02/12/25: Question from newbie of WebPACK
51106: 03/01/01: Question about HDL bencher (Xilinx) from newbie?
51181: 03/01/05: Re: Question about HDL bencher (Xilinx) from newbie?
51483: 03/01/14: How to run XST from command line?
52216: 03/02/04: Re: Xilinx's XDL
57968: 03/07/10: Questions about the figure in algorithm implimenting in hardware
64508: 04/01/06: Questions about guard bits in CORDIC algorithm
64529: 04/01/06: Re: Questions about guard bits in CORDIC algorithm
64572: 04/01/07: Re: Questions about guard bits in CORDIC algorithm
65352: 04/01/25: How to do with guard bits practically?
65355: 04/01/26: Re: How to do with guard bits practically?
65369: 04/01/26: Re: How to do with guard bits practically?
66477: 04/02/20: altera, xilinx susceptible to power transients?
95724: 06/01/25: Re: Spartan-3 Starter Board
95729: 06/01/25: Re: Spartan-3 Starter Board
jeff:
41881: 02/04/09: Need help with Insight Spartan II demo board and the counter demo.
41925: 02/04/10: Re: Need help with Insight Spartan II demo board and the counter demo.
41927: 02/04/10: Re: Need help with Insight Spartan II demo board and the counter demo.
42259: 02/04/18: Update -- Need help with Insight Spartan II demo board and the counter demo.
42262: 02/04/18: Re: Update -- Need help with Insight Spartan II demo board and the counter demo.
42437: 02/04/23: Re: Reasonably Priced Development Software ??
Jeff and Bev Neil:
29089: 01/02/06: .ucf commands
34290: 01/08/18: Re: [Spartan-II] JTAG configuration problem ...
Jeff Berryhill:
8444: 97/12/15: Re: bus design in Altera 10K, how to increase speed -- Check out Xilinx
8456: 97/12/16: Re: bus design in Altera 10K, how to increase speed -- Check out Xilinx
8469: 97/12/18: Re: bus design in Altera 10K, how to increase speed -- Check out Xilinx
11589: 98/08/25: Re: PROM alternative
Jeff Brandenburg:
434: 94/11/16: Re: Sources for FGPA's and "exotic" PLDs?
Jeff Brower:
98935: 06/03/17: Re: Urgent Help Needed!!!!!
99015: 06/03/18: Re: Urgent Help Needed!!!!!
99701: 06/03/28: combinatorial always blocks + for-loops in XST
99705: 06/03/28: Re: combinatorial always blocks + for-loops in XST
99711: 06/03/28: Re: combinatorial always blocks + for-loops in XST
99720: 06/03/28: Re: deglitching a clock
99722: 06/03/28: Re: combinatorial always blocks + for-loops in XST
99741: 06/03/28: Re: combinatorial always blocks + for-loops in XST
99910: 06/03/30: no output from BUFGMUX
99911: 06/03/30: Re: Xilinx Schematic Entry
99925: 06/03/30: Re: Xilinx Schematic Entry
100243: 06/04/05: initializing arrays with Verilog and XST
100260: 06/04/05: Re: initializing arrays with Verilog and XST
100263: 06/04/05: Re: Xilinx Schematic Entry
100271: 06/04/05: Re: initializing arrays with Verilog and XST
100508: 06/04/10: Configuration Rate with multiple .bit files
100512: 06/04/10: Re: Configuration Rate with multiple .bit files
100524: 06/04/10: Re: Configuration Rate with multiple .bit files
100705: 06/04/16: XST not inferring distributed RAM
100728: 06/04/17: Re: XST not inferring distributed RAM
100760: 06/04/17: Re: Spartan 3 chips in power up
100761: 06/04/17: Re: Spartan 3 chips in power up
100767: 06/04/17: comparison with integer
100794: 06/04/18: Re: Spartan 3 chips in power up
100806: 06/04/18: Re: comparison with integer
100855: 06/04/19: XST issues with loop code
100904: 06/04/20: Re: Spartan 3 chips in power up
100966: 06/04/21: XST pre-defined macros
101234: 06/04/27: Re: Xilinx PCI 64/32 bits IP
101240: 06/04/27: Re: Xilinx: Prohibit propagation of timing constraint through a mux
101241: 06/04/27: initializing array of registers in XST
101312: 06/04/28: Re: initializing array of registers in XST
101315: 06/04/28: Re: initializing array of registers in XST
101416: 06/04/30: Re: Pull up resistors on Spartan 3 mode pins
101461: 06/05/01: Re: ISE 8.1 Comment Bug, Very hideous
101517: 06/05/02: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
101519: 06/05/02: Re: ISE 8.1 Comment Bug, Very hideous
101623: 06/05/03: Re: ports of multidimentional arrays in verilog.
101624: 06/05/03: Re: ISE8.1 inout, tristate Problem?Please help!
101626: 06/05/03: Re: How to open an ISE 8.1 project in ISE 7.1?
102004: 06/05/09: Re: Xilinx 3s8000?
102015: 06/05/09: Re: Xilinx 3s8000?
102213: 06/05/11: Re: Xilinx 3s8000?
102214: 06/05/11: Re: Xilinx 3s8000?
102483: 06/05/16: Re: getting good deals on small qty?
102783: 06/05/20: initial block processing in XST 8.1
102843: 06/05/22: Re: initial block processing in XST 8.1
103163: 06/05/26: initial block processing in XST 8.1, part 2
135916: 08/10/21: Spartan 3 IO banking rules problem in ISE
135948: 08/10/23: Re: Spartan 3 IO banking rules problem in ISE
135952: 08/10/23: Re: Spartan 3 IO banking rules problem in ISE
Jeff Buckles:
6303: 97/05/12: Re: Desperate college students need help!!!
Jeff Carter:
24418: 00/08/07: FPGA
24523: 00/08/11: fpga
Jeff Christenson:
16035: 99/04/29: Re: flex10k 1 gate change
Jeff Collins:
542: 94/12/28: Dual Xilinx 4000->3000 question
705: 95/02/13: Can I implement a digital PLL in an FPGA??
754: 95/02/23: Re: Can I implement a digital PLL in an FPGA??
Jeff Cummings:
173: 94/09/09: Re: Help, Please (Urgent)
Jeff Cunningham:
260: 94/10/06: Re: AT&T ORCA FPGA
1341: 95/06/02: Re: Latch up in Xilinx 3000 Series FPGA's. Part smokes &
1292: 95/05/29: Re: Any company for conversion FPGA to ASIC?
1668: 95/08/13: Re: Xilinx PROMs
2777: 96/02/06: Re: Xilinx FPGA's with Mentor Tools?
3869: 96/08/12: Re: ASIC simulations in multiple FPGAs
30900: 01/05/02: Re: Need info : Training on ASIC/FPGA
31304: 01/05/17: Can anyone comment on the difference between modelsim PE and XE
31306: 01/05/17: Re: help for BGA ?
31420: 01/05/22: Aldec, Synplify (was: free simulator)
35418: 01/10/03: Re: What's a process?
35575: 01/10/10: Re: Synplicity/Leonardo License Agreement Information
36074: 01/10/27: Re: Firewire chipset
37524: 01/12/13: referencing Spartan2 DLL to 24.576 Mhz?
42434: 02/04/23: Re: Reasonably Priced Development Software ??
45274: 02/07/17: Re: Simulating Xilinx Block RAM with ModelSim
45276: 02/07/17: Re: Commercial FPGA Architectures
45545: 02/07/25: Re: Xilinx ISE 4.2i Is A Step Backwards! Beware!!!
45783: 02/08/05: Re: modelsim XE starter
46264: 02/08/23: Re: How to include Xilinx library for both ModelSim and Synplify?
48918: 02/10/26: Re: A PCI Data Aqcuisition Card Design
50202: 02/12/04: Re: clock difference between DLL input and output?
51841: 03/01/23: Re: VHDL or Verilog?
52401: 03/02/07: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
52913: 03/02/25: Re: Licencing for downloadable FPGA tools
52914: 03/02/25: Re: VHDL & FPGA Design tools
53376: 03/03/12: Re: comp.arch.fpga : VCC shorted to GND within FPGA???
58833: 03/08/02: Re: Multi Cycle path and False paths
61903: 03/10/15: Re: Universities that focus on IC design
62309: 03/10/26: Re: Are clock and divided clock synchronous?
62399: 03/10/29: Re: Are clock and divided clock synchronous?
62705: 03/11/05: Re: I/O on current FPGAs - deserialise first ??
62732: 03/11/06: Re: I/O on current FPGAs - deserialise first ??
62842: 03/11/10: Re: FPGAs and DRAM bandwidth
64567: 04/01/07: Re: Synthesis in VHDL vs. Verilog
67159: 04/03/07: Re: Release asynchrounous resets synchronously
68992: 04/04/23: Re: What is MPGA?
69439: 04/05/11: Re: One issue about free hardware
69674: 04/05/18: Re: Instantiating subblock signals with VHDL
69675: 04/05/18: Re: std_logic_vector vs unsigned
70127: 04/06/03: Re: tri-state in altera
71933: 04/08/04: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
74998: 04/10/23: Re: Altera Cubic Cyclonium
76433: 04/12/02: Does Easypath make sense for a XC2S15 @ 20K units?
76744: 04/12/10: Re: Getting Started With Simple Sound Synthesis
76746: 04/12/10: Re: Open source FPGA EDA Tools
76946: 04/12/16: Re: algorithm: square operation
77313: 05/01/04: Re: Skew between signals
77392: 05/01/06: Re: Utilisation of Xilinx FPGAs
77393: 05/01/06: Re: Synchronous Interface to XScale CPU
77819: 05/01/18: Re: FPGA Board with RF Front end
78180: 05/01/26: Re: 60Hz clock on XC9572
82449: 05/04/13: Re: General question about soft CPUs
82674: 05/04/16: Re: Soft CPU vs Hard CPU's
82998: 05/04/21: Is Cyclone-2 EP2C5 or EP2C8 available? If not, when?
83830: 05/05/07: Re: Using capacitor to slow the rise time.
83850: 05/05/08: Re: Using capacitor to slow the rise time.
85021: 05/06/03: Re: Basics FPGA
85395: 05/06/09: Re: FPGA I/O pin current sink
85397: 05/06/09: Re: FPGA/CPLD trend
85934: 05/06/18: Re: AbusivepPricing information in marketing publications
86097: 05/06/22: Re: FPGAs: Where will they go?
88719: 05/08/26: Re: Xilinx place and route cost table
88777: 05/08/28: Re: mails from Aman Mediratta
89104: 05/09/05: Re: Reading internal signals through a testbench.
90392: 05/10/11: Re: LUT 4:1 VS FF
92851: 05/12/07: Re: Virtex 4 not meeting timing constraints
92913: 05/12/09: Re: some new PCIe products
92950: 05/12/09: Re: Post PAR Simulation and Actual FPGA results differ
95364: 06/01/22: Re: Xilinx padding LC numbers, how do you feel about it?
96938: 06/02/13: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
97019: 06/02/14: Re: digital logic library by 74xxxx part number?
97633: 06/02/24: Re: Combinatorial Division?
98309: 06/03/08: Re: for all those who believe in ASICs....
100342: 06/04/06: Re: Streamlining FIRs in System Generator
106119: 06/08/07: Re: WHAT SITUATION I NEED A BUFFER
106537: 06/08/14: chipscope_opb_iba woes in XPS EDK
106590: 06/08/15: Re: chipscope_opb_iba woes in XPS EDK
106953: 06/08/22: Re: ISE 8.2i and EDK 8.1i
108619: 06/09/13: Re: Prefered ieee libraries?
110349: 06/10/14: Re: Xilinx documentation typos
110877: 06/10/25: XPS crashes while performing clock DRCs when I have DCR components
111284: 06/10/31: Re: SPDIF receiver
111308: 06/11/01: Re: SPDIF receiver
111970: 06/11/13: Re: Why 64-bit PLB?
114019: 07/01/02: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
114021: 07/01/02: Re: PPC PLB <=> FPGA fabric
114190: 07/01/06: Does Modelsim XE support coreconnect BFM simulation?
114333: 07/01/11: Re: Does Modelsim XE support coreconnect BFM simulation?
114519: 07/01/18: Re: running applications from external memory
115963: 07/02/26: Re: Interfacing to 10Gig ethernet with Xilinx FPGAs
115995: 07/02/27: Re: How can we know how many BRAM are used?
116594: 07/03/13: using system ACE for generic app data storage - file system intelligence
117029: 07/03/22: Re: Why is Xilinx's WebPACK so inferior?
118050: 07/04/16: Re: PLB Master
118051: 07/04/16: Re: FPGA High speed Transceivers for source synchronus bus application
118100: 07/04/17: Re: PLB Master
118559: 07/04/30: Re: DS18B20 connection on FPGA?
118599: 07/04/30: Re: Please help me fast !!!!!
119016: 07/05/09: Re: lwIP RAW mode support for V4 temac
120007: 07/05/30: Re: Building Gradually Expertise on VHDL/Verilog Design
120175: 07/06/02: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
120733: 07/06/15: booting a large V4 PPC program with a minimum of on chip bram
120734: 07/06/15: How to make a small (<4Kbyte) program for V4 PPC
120741: 07/06/15: Re: How to make a small (<4Kbyte) program for V4 PPC
120743: 07/06/15: Re: booting a large V4 PPC program with a minimum of on chip bram
120768: 07/06/15: Re: How to make a small (<4Kbyte) program for V4 PPC
120771: 07/06/15: Re: booting a large V4 PPC program with a minimum of on chip bram
120774: 07/06/15: Re: booting a large V4 PPC program with a minimum of on chip bram
120813: 07/06/18: Re: booting a large V4 PPC program with a minimum of on chip bram
121014: 07/06/21: is Ultracontroller-2 supposed to work under XPS/ISE 9.1?
121323: 07/07/02: Re: Multiplier in Xilinx
121869: 07/07/13: Re: ASM within C code in a PPC405 of VIRTEX II Pro
121981: 07/07/16: Re: 1ms delay in V5 FPGA
121990: 07/07/17: chipscope PLB IBA - how to get meaningful labels on signals?
122007: 07/07/17: Re: chipscope PLB IBA - how to get meaningful labels on signals?
122664: 07/08/02: V4 DSOCM always reads back zeroes
122731: 07/08/05: Re: V4 DSOCM always reads back zeroes
122761: 07/08/06: Re: bidirectional pin
123418: 07/08/27: Re: bidirectional pin help
123517: 07/08/29: Re: Problems with PLB_DDR2 core and soft reset
124123: 07/09/12: Re: Address sensitive process, Xilinx virtex2pro
124228: 07/09/14: Re: Beginner Advice (Languages, tools etc.)
124240: 07/09/16: Re: Beginner Advice (Languages, tools etc.)
124241: 07/09/16: Re: Beginner Advice (Languages, tools etc.)
124360: 07/09/19: Re: Guess: what is the largest number of state machines in a current
124362: 07/09/19: Re: Guess: what is the largest number of state machines in a current
124402: 07/09/20: Re: DMA scatter gather with PLB bus?
124601: 07/09/27: Re: Xilinx upgrade
124602: 07/09/27: Re: Never buy Altera!!!!
124809: 07/10/05: Re: How to do one hot state machine in verilog for Xilinx V5 using
125008: 07/10/15: Re: FPGA quiz: what can be wrong
125025: 07/10/15: Re: FPGA quiz: what can be wrong
125140: 07/10/16: Re: FPGA quiz: what can be wrong
125920: 07/11/08: Re: Microblaze PLB vs. OPB busses
126334: 07/11/19: Re: Microblaze books
126357: 07/11/20: Re: problem with adding custom logic to an IP core (xilinx edk)
128081: 08/01/14: DCR_INTC usage in EDK - where is SR18804?
128140: 08/01/16: Re: Basic FPGA question about Reset
128685: 08/02/03: Re: Bitstream verification through readback
128804: 08/02/06: Re: function/process to generate sine and cosine wave
129176: 08/02/17: Re: Ballpark PLB frequency
129201: 08/02/18: Re: Ballpark PLB frequency
129267: 08/02/19: Re: Ballpark PLB frequency
129290: 08/02/20: Re: Ballpark PLB frequency
129554: 08/02/27: Why must a V4 be configured within 10 minutes of power up?
129591: 08/02/28: Re: Making changes to custom IP in EDK
129663: 08/03/02: Re: Software for FPGA-based PC scope
129676: 08/03/03: Re: Software for FPGA-based PC scope
129949: 08/03/11: Re: Could I develop a new gui using java based on the script language
130756: 08/03/31: Re: Xilinx and Modelsim?
130845: 08/04/03: Re: coregenerator bram in synplify pro error
131287: 08/04/17: Re: Survey: FPGA PCB layout
131673: 08/04/28: understanding xilinx silicon revisions (does ES come before CES4,
131676: 08/04/29: Re: Debounce in Verilog?
131780: 08/05/01: Re: Functional Simulation of Virtex-4 Block Memory
131783: 08/05/01: Re: Functional Simulation of Virtex-4 Block Memory
132051: 08/05/12: has anyone made PLB_DDR work with 1Gb DRAM chips?
132256: 08/05/19: Re: 2-bit Pseudo Random Number Generator
132260: 08/05/19: Re: bizarre state machine behavior
132295: 08/05/20: Re: 2-bit Pseudo Random Number Generator
132296: 08/05/20: Re: bizarre state machine behavior
132651: 08/06/04: Re: Xilinx vs Altera
133138: 08/06/18: Re: =?windows-1252?Q?NVIDIA=92s_Tesla_T10P_Blurs_Some_?=
133140: 08/06/19: Re: Fixed point number hardware implementation
133314: 08/06/24: Re: Migrating to 9.2i from 8.2i
133507: 08/07/02: Re: How do I program an fpga once it has been designed and layout
133763: 08/07/14: Re: Mismatch simulation & post sythese results
134374: 08/08/07: Re: Downsizing Verilog synthesization.
135037: 08/09/11: Re: Spartan-II, config pins 5V tolerant? (slave serial)
136116: 08/11/02: Re: PLBv4.6 with more than 16 slaves
136228: 08/11/07: Re: Tilera multicore replaces FPGA?
136230: 08/11/07: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
136435: 08/11/16: Re: MAC PHY Configuration
137032: 08/12/19: Re: FPGA partial/catastrophic failure mode question
137033: 08/12/19: Re: Custom IP Core DMA (Xilinx Virtex II Pro)
137176: 08/12/30: Re: FPGA > ASIC
138526: 09/02/25: Re: Converting state machine encoding to std_logic_vector
138941: 09/03/15: Re: Getting started with FPGA
140103: 09/04/28: Re: a basics question: using input pins, pullup, short to ground
140351: 09/05/10: Re: implementing arbitrary combinational functions using block rams
146367: 10/03/14: Re: Tier Logic introduces the world's first 3D FPGA
146942: 10/04/03: Re: Free VHDL or Verilog Simulator
148603: 10/08/05: Re: Logic implementation probelm
148604: 10/08/05: Re: Xilinx EasyPath Pricing
149021: 10/09/21: Re: Xilinx XST and a State Machine - A Mystery
149629: 10/11/12: Re: Statemachine debugging with Chipscope
Jeff Fox:
66295: 04/02/16: Re: Dual-stack (Forth) processors
66316: 04/02/17: Re: Dual-stack (Forth) processors
66410: 04/02/18: Re: Dual-stack (Forth) processors
66442: 04/02/19: Re: Dual-stack (Forth) processors
66543: 04/02/21: Re: Dual-stack (Forth) processors
138977: 09/03/17: Re: Zero operand CPUs
139010: 09/03/18: Re: Bullshit! - Re: Zero operand CPUs
139037: 09/03/18: Re: Bullshit! - Re: Zero operand CPUs
139038: 09/03/18: Re: Bullshit! - Re: Zero operand CPUs
Jeff Graham:
10412: 98/05/17: XC5200s and Foundation 1.4
12392: 98/10/10: Re: Xilinx F1.5/FPGA Express wackiness
23536: 00/06/29: Re: Xilinx XC5200 implementation with F2.1i
Jeff Hunsinger:
2022: 95/10/03: Re: cheap (free) fpga design software (VHDL
2533: 95/12/28: Re: [q][Reverse Engineering Protection]
3479: 96/06/06: Re: FPGA Companies
3796: 96/08/02: Xilinx/FPGA Timing Problems
3807: 96/08/05: Re: Xilinx/FPGA Timing Problems
3828: 96/08/07: Re: Xilinx/FPGA Timing Problems
3895: 96/08/15: Re: Xilinx XC3090 intermittent place/route prob
3967: 96/08/26: Re: CHEAP XILINX FPGA ROUTING SOFTWARE ?
14748: 99/02/14: Xilinx Foundation Base = Useless?
14783: 99/02/16: Re: Xilinx Foundation Base = Useless?
14964: 99/02/27: Re: Foundation V1.5 Crash
15289: 99/03/17: Xilinx Spartan configuration troubles
15301: 99/03/17: Re: Xilinx Spartan configuration troubles
Jeff Hunsinger/RZXZ30/:
5405: 97/02/13: Re: Anyone for Linux ?
Jeff Hutchings:
258: 94/10/05: Motorola MPA (FPGA's)
311: 94/10/18: Re: FPGA RISC Processor
Jeff Iverson:
12531: 98/10/15: Re: books
14980: 99/03/01: Re: newbie questions
16042: 99/04/29: Re: Reconfigurable Computing
17933: 99/09/17: Re: simple VHDL?
Jeff Johnson:
108715: 06/09/15: upgrading firmware on stratix 2 without NIOS IDE
108741: 06/09/15: Re: upgrading firmware on stratix 2 without NIOS IDE
108970: 06/09/19: Re: upgrading firmware on stratix 2 without NIOS IDE
Jeff Kiser:
16994: 99/06/22: Re: Altera/Synplicity TIMESTAMP?
Jeff koehler x221:
999: 95/04/11: Re: Xilinx simulation models for synopsys..
Jeff Lucas:
117: 94/08/17: Sizeable symbols using Actel/Concept?
Jeff Millar:
4911: 96/12/29: Re: ASICs Vs. FPGA in Safety Critical Apps.
7031: 97/07/25: Re: How do FPGAs outperform DSP at FFT?
8142: 97/11/20: Re: what is metastability time of a flip_flop
Jeff Mock:
42059: 02/04/14: Re: virtex2 bufgce or not bufgce
42260: 02/04/18: Re: Understanding clock routing (or not)
42803: 02/05/02: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43231: 02/05/16: Spartan2 on a Compact Flash card
43380: 02/05/20: Re: How to generate fractional-N clock ?
43694: 02/05/29: Re: place and route simulation time
44513: 02/06/21: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
44723: 02/06/27: Re: VIRTEX II DCM Question
44749: 02/06/28: Re: VIRTEX II DCM Question
45013: 02/07/09: Re: how to keep info. in RAM during reconfiguration?
45046: 02/07/10: Re: how to keep info. in RAM during reconfiguration?
45051: 02/07/10: Re: How to locate the combinational loop in RTL source
jeff murphy:
87039: 05/07/13: ise 7.1 Input clk is never used.
87079: 05/07/14: Re: ise 7.1 Input clk is never used.
87116: 05/07/15: Re: Linux Fedora and Xilinx ISE
88841: 05/08/29: openrisc, jp1 jtag debug utility
88893: 05/08/30: Re: openrisc, jp1 jtag debug utility
89159: 05/09/06: Re: openrisc, jp1 jtag debug utility
Jeff Peterson:
63291: 03/11/19: 400 Mb/s ADC
63324: 03/11/19: Re: 400 Mb/s ADC
63341: 03/11/19: Re: 400 Mb/s ADC
63342: 03/11/19: Re: 400 Mb/s ADC
63410: 03/11/20: Re: 400 Mb/s ADC
63411: 03/11/20: Re: 400 Mb/s ADC
Jeff Piper:
22112: 00/04/25: ****Easy Money****
Jeff Reeve:
23742: 00/07/06: 56 independent PN streams
45449: 02/07/24: 32-bit PCI Target core
Jeff Sampson:
3453: 96/06/01: Re: PldShell -> Max+Plus2 conversion
9430: 98/03/13: Strange Xilinx question?
9441: 98/03/14: Re: Strange Xilinx question?
9445: 98/03/14: Re: Strange Xilinx question?
9446: 98/03/14: Re: Strange Xilinx question?
59284: 03/08/13: Old Xilinx FPGAs
59319: 03/08/14: Re: Old Xilinx FPGAs
59323: 03/08/14: Re: Old Xilinx FPGAs
59357: 03/08/15: Re: Old Xilinx FPGAs
59457: 03/08/19: Re: Parallel interface to an FPGA
59464: 03/08/19: Xilinx FPGA pin locking/assignment
59495: 03/08/20: Re: Xilinx FPGA pin locking/assignment
59528: 03/08/20: Re: Xilinx FPGA pin locking/assignment
59529: 03/08/21: Re: Xilinx FPGA pin locking/assignment
Jeff Sasmor:
8942: 98/02/08: Re: Free FPGA tools???
Jeff Seeger:
8688: 98/01/20: Re: bypass for 68 pin PLCC
Jeff Seltzer:
59809: 03/08/28: Re: Datasheet for National PAL20L10
98493: 06/03/10: Re: Troubles when upgrading Embedded Virtex-4Fx PowerPc
Jeff Shafer:
96371: 06/02/02: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
96396: 06/02/03: Re: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
96455: 06/02/03: Re: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
98032: 06/03/03: Re: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
99837: 06/03/29: Re: EDK/Xilinx : Insertion of ECC capability into BRAM controller
100123: 06/04/04: Re: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
100180: 06/04/04: Re: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
115220: 07/02/03: Re: data OCM BRAM Issues
Jeff Simmons:
10333: 98/05/12: Re: PALCE22v10 / GAL22v10 programming algorithms needed
Jeff Smith:
19257: 99/12/09: Lattice ispLSI Security
Jeff Stout:
9339: 98/03/06: Re: Version Control for schematics?
13806: 98/12/28: Re: 22V10 Metastability - help please
24604: 00/08/14: Re: Non-disclosures in job interviews
24636: 00/08/15: Re: Non-disclosures in job interviews
39262: 02/02/05: I want pla2tdf.exe
40549: 02/03/09: Re: Xilinx Download Cable Connectors
Jeff Streznetcky:
14811: 99/02/18: Re: Digital PLL
17463: 99/07/29: Xilinx timing constraints question
17776: 99/09/02: Re: Virtex dev boards
17777: 99/09/02: Re: Virtex dev boards
17778: 99/09/02: Re: Virtex dev boards
17813: 99/09/07: xilinx placer score?
Jeff Tong:
26352: 00/10/12: PCB board simulation - Need basic help!
Jeff Tucker:
10607: 98/06/05: Re: Example of 8051 codes to configure Xilinx fpga
Jeff Vallier:
13124: 98/11/16: Re: Low Cost FPGA Development Tools
13126: 98/11/16: Re: Board for FPGA ?
13562: 98/12/09: Re: The best PLD?
Jeff Wallace:
42232: 02/04/18: XCV812E-6BG560C - Virtex - E !!!!!!!!!
42828: 02/05/03: Re: Availability of XC2S150E-6FG456I
42829: 02/05/03: CAN EVERYONE PLEASE READ THIS!! - FEEDBACK APPRECIATED!!
Jeff Weintraub:
51272: 03/01/09: Re: Different Versions of Coregen
Jeff Wetch:
1603: 95/07/25: Actel Place and Route response
1604: 95/07/25: Actel Place and Route response
3236: 96/04/30: Re: S-modules and C-modules of Actel's FPGA
3878: 96/08/14: Re: ACTEL Security Fuse
8385: 97/12/11: Re: Z80 in FPGA: clockspeed?
47931: 02/10/07: Re: xilinx contact with regard to qpro
Jeff Wilkinson:
2538: 95/12/29: Programmable Interconnect ICs
2539: 95/12/29: Programmable Interconnect ICs - Repost
Jeff Wills:
85: 94/08/11: Re: Would you like a free C to netlist compiler?
<jeff.johnson.au@gmail.com>:
122995: 07/08/13: Using Virtex-II Pro MGT with external CDR
jeff_n_moz:
68109: 04/03/26: counter design
<jeffbush001@gmail.com>:
157712: 15/02/11: Open Source GPGPU core
157715: 15/02/13: Re: Open Source GPGPU core
157719: 15/02/13: Re: Open Source GPGPU core
157721: 15/02/15: Re: Open Source GPGPU core
jeffcannon:
93149: 05/12/14: Custom data rates with Virtex 2 Pro-X MGTs
94172: 06/01/06: Re: Chipscope Pro
<jeffery_dong@hotmail.com>:
130668: 08/03/29: Re: TCL testcase in Modelsim.
jeffg:
136988: 08/12/17: Re: Microblaze without external ram
<jeffjcannon@gmail.com>:
130525: 08/03/26: Re: Serial Transmission w/o 8B/10B encoding
135089: 08/09/15: Re: Moving to Altera from Xilinx
136469: 08/11/18: Re: Why memory for this Nios II is still not enough
JeffM:
87934: 05/08/03: Re: System Engineering in the R/D World
110233: 06/10/12: SPAM -- FPGA image processing camera
110244: 06/10/12: Re: SPAM -- FPGA image processing camera
<jeffnewcomb@nci-usa.com>:
104487: 06/06/28: Virtex5 Availability
104502: 06/06/28: Re: Virtex5 Availability
106755: 06/08/18: Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE 8.2 SP2
106760: 06/08/18: Re: Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE 8.2 SP2
106771: 06/08/18: Re: Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE 8.2 SP2
106776: 06/08/18: Re: Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE 8.2 SP2
107299: 06/08/26: What is the truth about the Virtex5 ?
107340: 06/08/26: Re: What is the truth about the Virtex5 ?
107345: 06/08/26: Re: What is the truth about the Virtex5 ?
107494: 06/08/29: Re: What is the truth about the Virtex5 ?
Jeffrey Arnold:
2936: 96/03/03: Re: Comp.Arch.FPGA
3242: 96/05/02: Re: On FPGAs as PC coprocessors
4609: 96/11/20: CFP: FCCM'97 IEEE Symp on Custom Computing Machines
49948: 02/11/26: FCCM'03 Call for Papers
64469: 04/01/05: FCCM'04 Reminder -- submission deadline Jan 19
Jeffrey Bain:
2235: 95/11/07: Needed: Protozone Adapter
Jeffrey C. Marden:
3514: 96/06/12: Re: FPGA Companies
4495: 96/11/06: Actel Designer and Win NT 4.0
7116: 97/08/01: Re: Download FLEX10K over the LPT port
Jeffrey David Cohen:
259: 94/10/05: CLI
Jeffrey Ebert:
3339: 96/05/15: Re: Looking for free FPGA softw./Xilinx
Jeffrey Graham:
35107: 01/09/21: comparison of performance and advantages for fpga's versus
jeffrey j cook:
19318: 99/12/13: VirtexE availability?
19344: 99/12/15: Re: VirtexE availability?
21621: 00/03/27: Virtex DLL Spread-spectrum clock sensitivity
25271: 00/09/04: FS: Xilinx XCV200-5PQ240, IDT 71V3558S/133PF
Jeffrey L. Hutchings:
1418: 95/06/20: Re: Low cost ISA board
1597: 95/07/25: Re: Lattice isp programming adapters
2574: 96/01/04: Re: What does VHDL stand for?
5586: 97/02/26: Re: Customizing Viewdraw in Workview Office 7.3 ... Is it possible?
Jeffrey L. Jensen:
16728: 99/06/04: Re: The Chickenshit War in Kosovo!
Jeffrey L. Madden:
14086: 99/01/12: Problems with processes
Jeffrey LIU:
12444: 98/10/13: Re: PCI target code
Jeffrey M. Arnold:
62: 94/08/07: Charter (was Re: This (new) froup)
80: 94/08/11: Re: Wanted: Literature on Reconfigurable Systems..
205: 94/09/21: Mail reflector
206: 94/09/21: C.A.F. WWW page (aperiodic reminder)
254: 94/10/03: WWW server
297: 94/10/14: FCCM'95 Call for Papers
422: 94/11/14: C.A.F. WWW page (aperiodic reminder)
421: 94/11/14: C.A.F. WWW page (aperiodic reminder)
508: 94/12/13: FCCM'95 final Call for Papers
538: 94/12/27: 6 th IEEE International Workshop Rapid Systems Prototyping
696: 95/02/09: FCCM'95 Registration and Call for Participation
792: 95/03/02: FPL'95: Final Call for Papers
793: 95/03/03: C.A.F. WWW page (aperiodic reminder)
852: 95/03/13: FCCM'95 Program
893: 95/03/22: FCCM'95 Registration and Hotel
931: 95/03/30: Re: FAQ/getting started/cheap?
1014: 95/04/13: FCCM'95 Program
1121: 95/05/02: Re: Web/FTP site for FPGA based research
1288: 95/05/28: Re: Altera Contacts ...
1521: 95/07/06: anonymous postings
1866: 95/09/12: Archive reminder
2023: 95/10/03: Call For Papers: FCCM'96
2202: 95/10/31: Re: AMCC pci kit- problems
2241: 95/11/08: FPL'96 Call for Papers
2778: 96/02/06: FCCM'96 Registration
3018: 96/03/14: FCCM'96 Preliminary Program
3019: 96/03/14: FCCM'96 Registration
4421: 96/10/27: CFP: FCCM'97 Int'l Symp on Custom Computing Machines, 16-18 April Napa, CA
5675: 97/03/05: FCCM'97 Registration and Hotel Information
5822: 97/03/18: FCCM'97 Preliminary Program
5976: 97/04/01: FCCM'97 Preliminary Program
6053: 97/04/08: Re: Reconfig computing and multimedia?
6085: 97/04/10: Re: comp.arch.fpga archiv dead?
6166: 97/04/21: FCCM'97 Photo album
6184: 97/04/23: Re: Reconfigurable Computing
6646: 97/06/09: Re: readback on xc40xx ?
8031: 97/11/09: FCCM'98 Call For Papers
8362: 97/12/10: Reminder: FCCM98 Call For Papers
9455: 98/03/14: FCCM'98 Preliminary Program
12645: 98/10/21: FCCM'99 Call for Papers
Jeffrey R. White:
7028: 97/07/24: real-life Aptix experiences
Jeffrey S. Dutky:
10377: 98/05/15: Re: Minimal ALU instruction set.
19808: 00/01/12: Re: HW resources increased
19840: 00/01/14: Re: HW resources increased
Jeffrey Smith:
81864: 05/04/02: USB blaster
Jeffrey Turner:
52255: 03/02/05: Re: clock ditribution tree
Jeffrey Vallier:
31931: 01/06/08: Re: safe state machine design problem
31933: 01/06/08: Re: Download problems
32028: 01/06/11: Re: Xilinx webpack annoyances (long and whiny)
32042: 01/06/11: Re: Doing Ethernet in a Virtex ?
32091: 01/06/13: Re: Fifo Clock in SpartanII
32429: 01/06/26: Re: Xilinx Spartan - Power Rail Related Timing Problem
33052: 01/07/16: Re: Fixing routing in a Virtex FPGA
Jeffrey Yuan:
2619: 96/01/11: Lattice isp Starter Kit and 3 ispLSI1016-80LJ Devices For Sale
jeffrey.johnson:
137516: 09/01/21: Re: rank beginner here, need to know where to start to get RS232 comm's working, and ...
<jeffrey.thia@gmail.com>:
159315: 16/10/03: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
<jeffreyzuelch@my-deja.com>:
20627: 00/02/16: Re: 100% slice utilization in Virtex FPGA
20628: 00/02/16: Re: 100% slice utilization in Virtex FPGA
20629: 00/02/16: Re: 100% slice utilization in Virtex FPGA
jeffsen:
77943: 05/01/20: How does a SDRAM controller work?
Jeffsen:
74949: 04/10/22: Re: Partial reconfiguration of Xilinx
74950: 04/10/22: CoreConnect Bus : How to speed up the PLB
75770: 04/11/14: DMA for PPC in Virtex-II Pro/EDK6.2
77965: 05/01/21: Re: Virtex-II bus macro doubt
79014: 05/02/11: Re: C program to big for microblaze?
Jeffsen (dot):
78956: 05/02/10: GEMAC and MGT on ML300
78957: 05/02/10: Re: GEMAC and MGT on ML300
jeffsen (toberemoved):
84569: 05/05/21: Re: For accessing my SDRAM,what should i do?
jega:
122546: 07/07/31: Clarifications Regarding FlexRay Stand Alone Cotroller Interfacing With PIC Microcontroller
<jelle@bang.zap>:
14743: 99/02/14: Re: Xilinx de-compiler
<jelloaman@gmail.com>:
159822: 17/03/24: Re: Master Xilinx FPGA like Jtag bridge.
159823: 17/03/24: Re: Master Xilinx FPGA like Jtag bridge.
Jelly:
65669: 04/02/04: Reconfiguring at runtime internally?
Jen:
34581: 01/08/29: Virtex II sizing rule of thumb
34735: 01/09/05: Re: Virtex II sizing rule of thumb
58011: 03/07/11: Re: Leonardo changes name of lpm megafunction
Jeniffer:
52968: 03/02/27: Newbie Qn: Power connections with virtex FPGAs
53112: 03/03/04: Implementation of latch in FPGA
53289: 03/03/10: Static Tming Analysis
53622: 03/03/18: Conversion of Xilinx bit file
Jenn Lee:
72182: 04/08/10: Example of network router and # of LUTs utilized - Searching for 3rd party compilation of "typical" specs
Jennifer Hou:
9873: 98/04/10: IEEE RTSS 98 -- Submission Deadline May 1
9898: 98/04/11: IEEE RTSS 98 -- Submission Deadline May 1
Jennifer Jenkins:
28340: 01/01/08: Re: WebPack-ISE .ucf problem?
30156: 01/03/26: Re: Simplified ISP of XCR3256XL from BIF file fails
32919: 01/07/11: Re: WebPACK problem
33336: 01/07/23: Re: free VHDL and/or Verilog tools?
33597: 01/07/31: Re: i2c master
54351: 03/04/08: Re: Dead cpld?
54574: 03/04/14: Re: request for simple UART
Jennifer Walton:
31382: 01/05/21: Hardware Engineer-RTOS,PLD,VXworks,fibre channel
jenny howard:
10894: 98/06/29: need help!
Jenny Pencis:
2916: 96/02/28: Zycad GF100K FPGA's
Jens:
87208: 05/07/19: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1
jens:
106691: 06/08/17: Re: FFT on an FPGA
109806: 06/10/05: Re: An implementation of a clean reset signal
109864: 06/10/06: Re: An implementation of a clean reset signal
118587: 07/04/30: Re: debounce state diagram FSM
128399: 08/01/24: Re: Random Number Generation in VHDL
131129: 08/04/11: Re: case statements- verilog to vhdl
Jens Baumann:
80206: 05/03/02: spartan3 development board in Europe?
80227: 05/03/02: Re: spartan3 development board in Europe?
80343: 05/03/04: Re: spartan3 development board in Europe?
80622: 05/03/09: Re: spartan3 development board in Europe?
81141: 05/03/18: Re: Spartan 3 to tempsensor interface
82331: 05/04/11: free HDL ebook?
89346: 05/09/13: Re: FFT implementation in Xilinx's Spartan 3
Jens Clausen:
7608: 97/09/26: AMD TAXI
Jens Frauenschlaeger:
37236: 01/12/04: JTAG readback format
40065: 02/02/26: readback by JTAG
41711: 02/04/05: Parallel cable IV schematic available???
42755: 02/05/02: Re: JTAG programmer (ick!)
42757: 02/05/02: Re: Xilinx Download Cable III
49849: 02/11/22: Re: Look up tables
Jens Ginzel:
6747: 97/06/23: looking for FPGA to access VMEBus
Jens Hagemeyer:
109713: 06/10/04: Re: Virtex-II Pro Platform FPGA : Assembling the modules
109730: 06/10/04: Re: Virtex-II Pro Platform FPGA : Assembling the modules
109751: 06/10/05: Re: Virtex-II Pro Platform FPGA : Assembling the modules
109790: 06/10/05: Re: Virtex-II Pro Platform FPGA : Assembling the modules
109841: 06/10/06: Re: Virtex-II Pro Platform FPGA : Assembling the modules
109885: 06/10/06: Re: Virtex-II Pro Platform FPGA : Assembling the modules
110353: 06/10/14: Re: Virtex-II Pro Platform FPGA : Assembling the modules
110383: 06/10/14: Re: Virtex-II Pro Platform FPGA : Assembling the modules
130847: 08/04/03: Re: Beginner's silly question about ICAP
133334: 08/06/25: Re: 1D or 2D Placement for dynamically partially reconfigurable
136004: 08/10/27: vMAGIC 0.1.1 (alpha) released
Jens Hildebrandt:
21699: 00/03/29: LUT components in Synopsys/Xilinx design flow
21785: 00/03/31: Re: 82C54
22060: 00/04/17: PULL-UPs on Xilinx-FPGA pads
22072: 00/04/18: Re: PULL-UPs on Xilinx-FPGA pads
22083: 00/04/20: Re: PULL-UPs on Xilinx-FPGA pads
22668: 00/05/17: Re: SMT 7 segment display ??
23643: 00/07/04: Re: Altera Ships Largest PLD
23754: 00/07/07: Re: Clock Buffer
23799: 00/07/10: Re: Clock Buffer
25069: 00/08/25: "generate" and instance name indexes in Synopsys
32019: 01/06/11: Re: Flash programming via FPGA's JTAG ????
35933: 01/10/24: Re: Bidirectional port is converted to input during synthesis
39079: 02/01/31: Re: Java or bytecode processors??
42364: 02/04/22: Re: Xilinx Easypath- Selling parts with known defects
42647: 02/04/30: Re: SpartanII ISA interface, IDE and ISA contention??
45210: 02/07/16: Re: I want to buy 4 Xilinx FPGA
52739: 03/02/20: Re: XCV800 Configuration PROM
53121: 03/03/04: Re: Implementation of latch in FPGA
53429: 03/03/13: Re: [Xilinx] Looking for Parallel Cable III ...
53877: 03/03/26: Re: How to avoid this Latch
54961: 03/04/23: Re: request for simple UART
61697: 03/10/09: Re: beginner - exisit some free schematics programmer for fpga ?
70382: 04/06/15: Re: Several Problems with Spartan2 Configuration
Jens Huettemann:
53421: 03/03/13: Re: RESET --- Synchronous Vs Asynchronous
Jens Konig:
26109: 00/10/04: Re: Whoa, Noise on a digital output pin?, and Minor rant on XC9500 S/W, was Re: Simon,Floating Inputs
Jens Lauer:
18986: 99/11/23: Hyperstones RiscDSP Eva Kit seems buggy
Jens Mander:
54325: 03/04/08: Educational FPGA board requirements
54333: 03/04/08: Re: Power Supply for Spartan II FPGA
54334: 03/04/08: Re: Constraints for high speed I/O signals.
85484: 05/06/10: fast universal compression scheme and its implementation in VHDL
88803: 05/08/29: fast universal compression scheme and its implementation in VHDL
Jens Niemann:
39526: 02/02/12: Newbie SpartanII Block Ram question
39557: 02/02/13: Re: Newbie SpartanII Block Ram question
39659: 02/02/15: Newbie question Synchronous RAM
47947: 02/10/08: Booting a FPGA via USB
48018: 02/10/09: Re: Booting a FPGA via USB
49511: 02/11/14: Programming a Spartan2 via JTAG
51927: 03/01/26: Prob. with data-input of SDRAM-Controller
Jens Nowack:
55135: 03/04/28: LVDS I/O with Altera Cyclone
55159: 03/04/29: Re: LVDS I/O with Altera Cyclone
55161: 03/04/29: clock i/o`s Altera Cyclone
55537: 03/05/12: Register in FPGA
55838: 03/05/21: Re: Register in FPGA
56070: 03/05/28: Simulation in Altera Quartus II
56479: 03/06/06: Quartus II time delay
Jens Petersen:
156727: 14/06/08: Re: 22V10 programmer
Jens Popp:
23737: 00/07/06: Xilinx Design Flow
23764: 00/07/07: FPGA Express/Foundation Error 470
23801: 00/07/10: Xilinx XC4000E / Renoir
23922: 00/07/15: Renoir/Update Symbol from HDL
28780: 01/01/24: Hardware Debugger crashes with Xchecker Cable
Jens Weigle:
4488: 96/11/05: UART FOR FPGAS
Jens-Christian Lache:
34944: 01/09/14: using BlockRAM
34969: 01/09/17: Re: using BlockRAM
34972: 01/09/17: Re: how to simulate virtex components?
34978: 01/09/17: Re: how to simulate virtex components?
35021: 01/09/18: Re: using BlockRAM
35066: 01/09/20: Re: Timing constraints...
35071: 01/09/20: Re: Timing constraints...
35217: 01/09/26: Re: Virtex 2 : using IOB registers
35218: 01/09/26: how to dublicate logic?
35230: 01/09/26: Re: how to dublicate logic?
35254: 01/09/27: Re: how to dublicate logic?
35304: 01/09/28: Re: how to dublicate logic?
35314: 01/09/28: Re: how to dublicate logic?
35945: 01/10/24: Re: how to dublicate logic?
36332: 01/11/06: placement for if (vhdl)
36360: 01/11/07: Re: placement for if (vhdl)
36429: 01/11/08: Re: Xilinx dedicated IO pins
Jens-Peter Kaps:
8083: 97/11/16: Xilinx Logiblox in Synopsys
9033: 98/02/16: Xilinx Simulation in Synopsys
<jens_strauss@my-deja.com>:
19961: 00/01/20: Correlator with VHDL
jenze:
97784: 06/02/27: Re: A dev board supporting partial/dynamic reconf.
100048: 06/04/02: Re: Xilinx SelectMAP problem
100073: 06/04/03: Re: Xilinx SelectMAP problem
101722: 06/05/05: Re: Xilinx SelectMAP Question
101970: 06/05/08: Re: Installing BFM toolkit
102185: 06/05/11: Re: Installing BFM toolkit
Jeong-Gun Lee:
68069: 04/03/26: Finding Triscend A7 Examples
Jep:
101808: 06/05/07: flashing a led
101834: 06/05/07: Re: flashing a led
Jer-Sheng Chen:
13112: 98/11/16: Re: Looking for a good documentation on FPGA
Jered:
91478: 05/11/07: ML402 DDR SDRAM
Jeremie:
72341: 04/08/16: Re: Xilinx 804 Aurora vhdl Design patch
120865: 07/06/19: Rocketio connection Virtex2pro-Virtex4
Jeremie Veyret:
72294: 04/08/13: Xilinx 804 Aurora vhdl Design patch
Jeremie WEBER:
47402: 02/09/25: Re: FPGA fail when Electrostatic discharge Occurs
47404: 02/09/25: Re: FPGA fail when Electrostatic discharge Occurs
Jeremy:
66605: 04/02/23: How to configure FPGA manually ?
66693: 04/02/25: Example using a custom OPB slave core with and interrupt
95167: 06/01/20: Virtual Pin in Xilinx ISE
95559: 06/01/23: Re: Virtual Pin in Xilinx ISE
121137: 07/06/26: Xilinx ISE 9.1 - Version Control - VSS
jeremy:
39553: 02/02/13: CLKDLL doesn't work without BUFG ?
Jeremy Bennett:
136634: 08/11/27: Re: opencores can core
137077: 08/12/22: Re: Bit width in CPU cores
137146: 08/12/28: Re: which HLL for HPC applications implementation?
138877: 09/03/13: Re: What happens at opencores.org?
139469: 09/03/31: Re: SiliconBlue on Wikipedia
Jeremy Cooke:
27017: 00/11/07: Re: FPGA DESIGNER LONG ISLAND
27018: 00/11/07: Architecture/environment suggestions
27078: 00/11/09: Re: Microprocessor Verilog/VHDL Models
Jeremy D. Grotte:
42452: 02/04/24: Using PAL/GAL/FPGA to replace CPU's (correct news group?)
42488: 02/04/25: Re: Using PAL/GAL/FPGA to replace CPU's (correct news group?)
42534: 02/04/26: Re: Using PAL/GAL/FPGA to replace CPU's (correct news group?)
Jeremy Harris:
122736: 07/08/05: Re: bare bone PCI cards with FPGAs
Jeremy Price:
106139: 06/08/08: Networking : Multicast Performance
106509: 06/08/14: Error building mpmc2
Jeremy Ralph:
101783: 06/05/06: FPGA-based hardware accelerator for PC
101790: 06/05/06: Re: FPGA-based hardware accelerator for PC
101792: 06/05/06: Re: FPGA-based hardware accelerator for PC
101917: 06/05/08: Re: FPGA-based hardware accelerator for PC
102110: 06/05/10: Re: FPGA-based hardware accelerator for PC
103137: 06/05/25: Re: FPGA-based hardware accelerator for PC
103994: 06/06/16: Re: ARM cores in FPGA ?
Jeremy Sonander:
2559: 96/01/02: Re: VHDL Editor for Windows PC, Suggestions?
3759: 96/07/26: Re: ATT serial EEPROMs
Jeremy Stringer:
77764: 05/01/17: Re: Problems in timing simulations
77952: 05/01/21: Re: X-checker Pod : Problem w/ X-checker and Win2000
78529: 05/02/03: Spartan-3 Static Timing Analysis with Voltage/Temperature Pro-rating
79538: 05/02/21: Re: why are PCI-based FPGA cards so expensive ?
79604: 05/02/22: Jitter and Static Timing Analysis
79607: 05/02/22: Re: Shift register example?
79612: 05/02/22: Re: Jitter and Static Timing Analysis
79841: 05/02/25: Re: publishing IP
79983: 05/02/28: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx
80027: 05/03/01: Re: publishing IP
80107: 05/03/02: Re: Problem with LXT970A
80517: 05/03/08: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx
81040: 05/03/17: Re: Help with ram controller on Xilinx Spartan IIE
81041: 05/03/17: Re: spartan3E price
81042: 05/03/17: Re: SR latches in Xilinx devices?
81051: 05/03/17: Re: Creating own RPMs using Xilinx ISE
81274: 05/03/21: Re: Is the Xilinx EDK free?
81407: 05/03/23: Re: Difference between simulation types
81683: 05/03/30: Re: Difference between simulation types
82038: 05/04/06: Re: Protection measurements
82105: 05/04/07: Re: Open PowerPC Core?
82366: 05/04/12: Re: process trouble, error: multi source
83114: 05/04/24: Re: CAM for FPGA ...
83338: 05/04/28: DCM Cycle-to-Cycle Jitter
83392: 05/04/29: Re: DCM Cycle-to-Cycle Jitter
83671: 05/05/05: Re: Newbie VHDL/FPGA question
83677: 05/05/05: Re: Timing and synthesis problem+xilinx
83993: 05/05/11: Re: Using capacitor to slow the rise time.
84054: 05/05/12: Re: Using capacitor to slow the rise time.
84363: 05/05/18: Re: Registers replication on Xilinx IOBs
84506: 05/05/20: Jobs going in New Zealand
84639: 05/05/24: Re: Jobs going in New Zealand
84850: 05/05/31: Re: Jobs going in New Zealand
84914: 05/06/01: Re: Xilinx Answer Record 21127
85396: 05/06/09: Re: Why do VHDL gate level models simulate slower than verilog
85475: 05/06/10: Re: floorplanning
85629: 05/06/13: Re: FPGA or SSE2 ?
85679: 05/06/14: Re: FPGA or SSE2 ?
85731: 05/06/15: Re: Somewhat OT - falling behind the times ...
85779: 05/06/16: Re: convert vhdl to edif
85837: 05/06/17: Re: Idea exploration 1.1 - Inertia based angular sensor.
85995: 05/06/20: Re: comp.arch.fpga.<mfr>
85996: 05/06/20: ISE 7.1 Service Pack 2 - Ready yet?
86033: 05/06/21: Re: ISE 7.1 Service Pack 2 - Ready yet?
86616: 05/07/01: Re: ip core supply
86622: 05/07/01: Re: Avnet V2P development kit woes
86623: 05/07/01: Re: V4 and DDR2 666
87093: 05/07/15: Re: Reading a PS/2 mouse
87187: 05/07/19: Re: Reading a PS/2 mouse
87712: 05/07/29: 2-bit RAM16X In a V2PRo
87985: 05/08/05: Re: System Engineering in the R/D World
88198: 05/08/12: Re: fpga- DDR or DDR2
88334: 05/08/16: Re: Creating EDIF from VHDL
88709: 05/08/26: Re: Kingston module structure
90208: 05/10/07: Re: FSM with High load on clock signal
90212: 05/10/07: Re: Xilinx IMPACT Problem... detects 101 unknown devices
90465: 05/10/14: Re: How to Reduce Interconnects (VDD and VSS)
90612: 05/10/18: Re: FPGA timming
91222: 05/11/02: Re: can ethereal detect an ethernet packet for which crc is wrong
91225: 05/11/02: Re: newbie question
91348: 05/11/04: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91429: 05/11/07: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91486: 05/11/08: Re: clock timing
91603: 05/11/10: Re: What are important factors when selecting Intellectual Property?
91626: 05/11/10: Re: Bus for Spartan3
91824: 05/11/15: Re: i2c slave does not acknowlege
93104: 05/12/14: SGMII Interface
93148: 05/12/15: Re: SGMII Interface
93430: 05/12/22: Re: Is there anyboay work on the subject with the embeded system
93490: 05/12/23: Re: Place and Route Algorithms: where's the fat?
94495: 06/01/13: Re: How to create a delay BUF?
94519: 06/01/13: Re: How to create a delay BUF?
94649: 06/01/16: Re: Don't even get me started on lead,
97385: 06/02/22: Re: FPGA - software or hardware -2-
97803: 06/02/28: Re: VHDL to create LUT based delay
98745: 06/03/16: Re: Soldering SMT/BGA
98808: 06/03/17: Re: Debugging ideas.
98826: 06/03/17: Re: Urgent Help Needed!!!!!
99233: 06/03/22: Re: Virtex-4 RocketIO and G.709 OTU-2
99650: 06/03/28: Re: OpenSPARC released
100171: 06/04/05: Source-synchronous IO constraints in Synplify
100456: 06/04/10: Re: FPGA FAQ and the spam problem
109121: 06/09/21: Re: VHDL oddity
112016: 06/11/15: Re: Influence of temperature and manufacturing to propagation delay
Jeremy Webb:
61726: 03/10/09: Re: Digesting runs of ones or zeros "well"
61755: 03/10/09: Re: Digesting runs of ones or zeros "well"
73028: 04/09/10: Re: Simulation probs with Altera LPM_FIFO+
73030: 04/09/10: Re: Simulation probs with Altera LPM_FIFO+
74766: 04/10/18: Re: Modelsim simulation problem
Jeremy Whatley:
37297: 01/12/06: Xilinx CPLD pin mapping with Foundation F3.1i
44980: 02/07/08: ISE 4.2i : Clock Buffer Disable
52855: 03/02/24: Delay element in Virtex2
59306: 03/08/14: Virtex II Output Impedance
Jeremy Wood:
92171: 05/11/23: Design Implementation in Xilinx XST
92183: 05/11/23: Re: Design Implementation in Xilinx XST
106448: 06/08/13: Xilinx Webpack inferring BRAMS, RedHat version
<jeremy.webb@ieee.org>:
76559: 04/12/06: Re: JTAG recognise xcv50e instead of xc2s50e
79101: 05/02/14: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
79130: 05/02/14: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
jeremywwebb@gmail.com:
137095: 08/12/22: Re: Adding userports to a custom peripheral in XPS
Jerker Hammarberg (DST):
63757: 03/12/03: Spartan IIE daisy chain problems
71075: 04/07/07: FSM in illegal state
71081: 04/07/07: Re: FSM in illegal state
71082: 04/07/07: Re: FSM in illegal state
71090: 04/07/07: Re: FSM in illegal state
71094: 04/07/07: Re: FSM in illegal state
71098: 04/07/08: Re: FSM in illegal state
71108: 04/07/08: Re: FSM in illegal state
71121: 04/07/08: Re: FSM in illegal state
71123: 04/07/08: Re: FSM in illegal state
71125: 04/07/08: Re: FSM in illegal state
71126: 04/07/08: Re: FSM in illegal state
71269: 04/07/13: Re: FSM in illegal state (conclusion)
72350: 04/08/16: Usercode in bit/mcs file
72355: 04/08/16: Re: How to ? 2.1i to ISE6.2 SCHEMATIC converter!!
72369: 04/08/17: Re: Usercode in bit/mcs file
Jeroen:
6285: 97/05/08: Neede: Resellers for Adv. Comp. Products.(only serious replies).
62920: 03/11/11: Code for accessing CF cards on Cyclone dev.board
65088: 04/01/20: Re: Help on qu@rtus memory initialization file
66171: 04/02/13: makefile to generate memory contents in Altera SOPC Builder
69544: 04/05/13: EPCS4 Configuration+firmware, Quartus problem
69545: 04/05/13: Re: Anyone who has worked with Altera Cyclone???
69739: 04/05/19: Re: Nios II Going Live...
69741: 04/05/19: Re: Inversion of signals on synthesis
69932: 04/05/25: Re: HOWTO calculate the binary size of a .hexout/.flash/.germs file
69933: 04/05/25: Re: USB HUB?
70727: 04/06/25: Re: Why does Quartus take 4 hours for a pin I/O change?
71234: 04/07/12: Re: Programable Logic & Video stuff
72306: 04/08/14: Re: NIOS II - Instantiating array on SDRAM
73039: 04/09/11: Re: Need some help with some technical claims...
73300: 04/09/18: Re: Problem with I/O state while power on
73434: 04/09/21: Re: From whence the MAC on an Altera NIOS devel kit board?
73459: 04/09/22: Re: edge reset
73535: 04/09/23: Re: using both edges of clocks in a design - effects on synthesis
73960: 04/10/01: Re: Removing set/reset logic for shift register (HDL ADVISOR )
73240: 04/09/16: Re: Twister + Lancelot
76129: 04/11/25: Re: MIL-Qualified RTOS for uBlaze or NiosII
76731: 04/12/10: Re: Getting Started With Simple Sound Synthesis
76743: 04/12/10: Re: Getting Started With Simple Sound Synthesis
76827: 04/12/13: Re: Cyclone device misteriously overheats
76829: 04/12/14: Re: Cyclone device misteriously overheats
76843: 04/12/14: Re: Cyclone device misteriously overheats
76865: 04/12/15: Re: Cyclone device misteriously overheats
76957: 04/12/17: Re: JTAG vs. Passive Serial Config speed
77155: 04/12/26: Re: PS: Synchronous design and power consumption
77548: 05/01/10: Re: Configuration devices
78277: 05/01/28: Re: EPCS binary files...
Jeroen Belleman:
148191: 10/06/25: Re: fooling the compiler
149628: 10/11/12: Re: cool BGA pattern
Jeroen Fokker:
11412: 98/08/11: Re: Combinatoric Divide-by-3 Algorithm
Jeroen Tenbult:
106924: 06/08/22: Re: ISE 8.1: Process "Map" failed
Jeroen Van den Keybus:
38805: 02/01/25: Pin assignment on ACEX1K
38978: 02/01/29: Re: Pin assignment on ACEX1K
<jeroen.claes@gemidis.be>:
127783: 08/01/08: Bad micro blaze behaviour during power off
127837: 08/01/09: Re: Bad micro blaze behaviour during power off
127864: 08/01/09: Re: Bad micro blaze behaviour during power off
Jerome:
70563: 04/06/21: Re: VDHL implementation of RAM with serial input and parallel outpout ? thx
74526: 04/10/13: Re: simprim errors
88387: 05/08/17: Re: image sensor
91095: 05/10/29: Re: xilinx design reuse netlist format
93221: 05/12/16: Re: FPGA-pci communication
93266: 05/12/17: Re: FPGA-pci communication
94436: 06/01/11: Re: Samples
94462: 06/01/12: Re: Samples
94895: 06/01/19: Re: clock generation with DOPPLER shift
96583: 06/02/07: cheap USB analyzer based on FPGA
96639: 06/02/08: Re: cheap USB analyzer based on FPGA
96733: 06/02/09: Re: cheap USB analyzer based on FPGA
96840: 06/02/11: Re: cheap USB analyzer based on FPGA
96944: 06/02/14: Re: cheap USB analyzer based on FPGA
96947: 06/02/14: Re: cheap USB analyzer based on FPGA
98534: 06/03/12: Re: LEON processor core
98541: 06/03/12: Re: LEON processor core
101075: 06/04/25: Virtex 2 Config Times
103722: 06/06/09: PCI Express - Root Complex ?
114074: 07/01/04: Re: DC timing violation, what to do first?
114230: 07/01/08: Re: Use Multi-cycle Path or Pipeline?
jerome:
67639: 04/03/16: FPGA protyping board (Avnet or others)
67674: 04/03/17: Re: FPGA protyping board (Avnet or others)
75181: 04/10/28: information about Nuhorizon Spartan-3 Development Board ?
Jerre:
34968: 01/09/17: xilinx prom readback with jtag
35960: 01/10/25: How to make an implementable big counter?
43497: 02/05/22: stability/timing problem on reset
43879: 02/06/05: Resetting problem on my Xi 4000 due to very slow reset
44060: 02/06/11: How to implement synchronous reset on an FPGA
44335: 02/06/18: How to deal with a slowly rising reset signal?
jerry:
48606: 02/10/21: Re: Buy Small quantities
Jerry:
27901: 00/12/14: Spartan configuration : Why Done returns to Low?
27902: 00/12/14: Re: Spartan configuration : Why Done returns to Low?
27923: 00/12/14: Re: Spartan configuration : Why Done returns to Low?
27971: 00/12/18: Re: Spartan configuration : Why Done returns to Low?
33454: 01/07/26: Re: Scope of libraries in leonardo spectrum
33849: 01/08/06: Re: Which is the best Design Toolchain?
36619: 01/11/13: Re: Incrementing counter from state-machine
45647: 02/07/30: VirtexE : OrCAD capture part symbol
49445: 02/11/12: Re: HDL vs RTL
49542: 02/11/14: Re: why systemc?
49756: 02/11/20: Convert AHDL design to schematics(RTL)
51673: 03/01/18: Multi Project DIE
51745: 03/01/20: Re: Multi Project DIE
52285: 03/02/05: Redhat versions
52953: 03/02/26: linux vs windows
52998: 03/02/27: Re: linux vs windows
53157: 03/03/04: Re: Issues in Outsourcing?
53571: 03/03/16: Re: FPGA dev boards
54002: 03/03/30: Re: $4000 FPGAs
54039: 03/03/31: What would it take?
54046: 03/03/31: Re: What would it take?
54072: 03/04/01: Re: What would it take?
55953: 03/05/24: Re: FPGA Board
55954: 03/05/24: Re: FPGA Board
56928: 03/06/18: Re: FPGA to Custom ASIC ??
57347: 03/06/27: Re: ASIC divider in FPGA?
57830: 03/07/07: eCOS port for NIOS
58965: 03/08/05: Re: Patent granted for "system on a chip" framework?
60176: 03/09/06: Stratix pricing
60967: 03/09/25: NIOS and OCI
61092: 03/09/27: Re: NIOS and OCI
61180: 03/09/29: Re: NIOS and OCI
61252: 03/09/30: Re: Frustrations with Marketing
61399: 03/10/02: Re: Quartus II tutorial vs the real world
62244: 03/10/22: Re: The Luddite Needs Reference Books...
62642: 03/11/03: Re: Altera "my support" :-(
63131: 03/11/15: standalone IMPACT
64399: 04/01/01: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
64441: 04/01/04: Re: is this a good idea
70268: 04/06/10: Re: SOPC BUILDER - SOFTWARE GENERATION
71560: 04/07/21: Altera Cyclone Web presentation
72144: 04/08/09: Re: Now I am really confused!
72145: 04/08/09: Altera winner?
72186: 04/08/10: Re: Altera winner?
72279: 04/08/12: Re: Altera winner?
72473: 04/08/19: NIOS II Sim
72500: 04/08/20: Re: NIOS II Sim
72901: 04/09/07: Altera DDR SDRAM & external DSP
72904: 04/09/07: Re: I NEED HELP / MENTOR
73372: 04/09/20: Re: Virtex 4 integrated A/Ds? Yes it does.
76745: 04/12/09: XPS errors
76833: 04/12/13: ISE/XPS ERRORS
82543: 05/04/13: Altera DSP dev board stratix II
82614: 05/04/14: Re: Altera DSP dev board stratix II
88614: 05/08/23: 802.11 IP
88615: 05/08/23: Re: Verilog examples???
90553: 05/10/16: LSI RAPIDCHIP
90689: 05/10/18: Re: LSI RapidChip
90690: 05/10/18: Re: LSI RAPIDCHIP
97863: 06/02/28: DDR2 FPGA PWB SIMULATION
104184: 06/06/20: Re: altera cyclone memory example
Jerry Avins:
9188: 98/02/28: Re: Dsp Fpga and vhdl project
10761: 98/06/16: Re: Do You need any components
12002: 98/09/23: Re: easier testing for PCI cards??
20148: 00/01/28: Re: ADC to DSP... FIFO?
20415: 00/02/09: Re: ADC to DSP... FIFO?
20772: 00/02/21: Re: Distributed Arithmetic De-mystified
20812: 00/02/23: Re: Bit Serial Arithmetic De-mystified
20813: 00/02/23: Re: Bit Serial Arithmetic De-mystified
20826: 00/02/23: Re: Bit Serial Arithmetic De-mystified
20835: 00/02/23: Re: Bit Serial Arithmetic De-mystified
20837: 00/02/23: Re: Bit Serial Arithmetic De-mystified
20870: 00/02/24: Re: Bit Serial Arithmetic De-mystified
22393: 00/05/08: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22405: 00/05/08: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22421: 00/05/08: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22458: 00/05/09: Re:OT ANNOUNCE: Embedded Systems Glossary and Bibliography
22555: 00/05/11: Re: OT ANNOUNCE: Embedded Systems Glossary and Bibliography
22594: 00/05/12: Re: OT ANNOUNCE: Embedded Systems Glossary and Bibliography
25134: 00/08/27: Re: Non-disclosures in job interviews, Round Two
25141: 00/08/27: Re: Non-disclosures in job interviews, Round Two
27019: 00/11/07: Re: ANNOUNCE: New article about Network Processors
30015: 01/03/20: Re: TOA measurement
30044: 01/03/21: Re: TOA measurement
30074: 01/03/22: Re: TOA measurement
38347: 02/01/11: Re: speech recognition - active noise cancellation
38367: 02/01/12: Re: speech recognition - active noise cancellation
39189: 02/02/03: Re: solutions manuals, and no they are not for school
39285: 02/02/05: Re: solutions manuals, and no they are not for school
39380: 02/02/07: Re: solutions manuals, and no they are not for school
39417: 02/02/08: Re: solutions manuals, and no they are not for school
39437: 02/02/09: Re: solutions manuals, and no they are not for school
43281: 02/05/17: Re: SDRAM pricing
45438: 02/07/23: Re: xilinx v ti
48446: 02/10/17: Re: Proveedor de Soluciones uC/FPGA/DSP - uC/FPGA/DSP Solutions Provider
56049: 03/05/27: Re: JTAG madness
56051: 03/05/27: Re: JTAG madness
56082: 03/05/28: Re: JTAG madness
56086: 03/05/28: Re: JTAG madness
56114: 03/05/28: Re: JTAG madness
58366: 03/07/21: Re: Phase / frequency detector types
62551: 03/10/31: OT Shannon Entropy for Black Holes
62635: 03/11/03: Re: Shannon Entropy for Black Holes
62790: 03/11/07: Re: Shannon Entropy for Black Holes
65900: 04/02/09: Re: iteration Vs LUT table entry vs accuracy in Cordic
65949: 04/02/10: Re: iteration Vs LUT table entry vs accuracy in Cordic
66437: 04/02/19: Re: Dual-stack (Forth) processors
66438: 04/02/19: Re: Dual-stack (Forth) processors
66444: 04/02/19: Re: Dual-stack (Forth) processors
66452: 04/02/19: Re: Dual-stack (Forth) processors
66455: 04/02/19: Re: Dual-stack (Forth) processors
66459: 04/02/19: Re: Dual-stack (Forth) processors
66461: 04/02/19: Re: Dual-stack (Forth) processors
67972: 04/03/23: Re: Bus width between registers in IIR
68024: 04/03/24: Re: Bus width between registers in IIR
68822: 04/04/19: Re: Image-reject IF downmixing
83074: 05/04/22: Re: What is the cause of a "can not see clock" problem in logic analyser?
83075: 05/04/22: Re: What is the cause of a "can not see clock" problem in logic analyser?
86365: 05/06/26: Re: Idea exploration 1.1 - Inertia based angular sensor.
87356: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87395: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87410: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87427: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87429: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87448: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87449: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87450: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87454: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87455: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87460: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87461: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87473: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87474: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87475: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87499: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87503: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87548: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87563: 05/07/26: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87564: 05/07/26: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87758: 05/07/31: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87787: 05/08/01: Re: Best Practices to Manage Complexity in Hardward/Software Design?
88030: 05/08/06: Re: System Engineering in the R/D World
88034: 05/08/07: Re: System Engineering in the R/D World
88040: 05/08/07: Re: System Engineering in the R/D World
88049: 05/08/07: Re: Good intro books on OFDM?
92353: 05/11/28: Re: AD9218, what will the negative values be in binary mode?
92375: 05/11/28: Re: Why does two channels of ADC give different outputs?
92400: 05/11/29: Re: Why does two channels of ADC give different outputs?
92588: 05/12/01: Re: Quick question, how do I supply +-5V?
92590: 05/12/01: Re: Quick question, how do I supply +-5V?
92626: 05/12/02: Re: Quick question, how do I supply +-5V?
92630: 05/12/02: Re: Quick question, how do I supply +-5V?
92646: 05/12/02: Re: Quick question, how do I supply +-5V?
92735: 05/12/05: Re: Quick question, how do I supply +-5V?
93080: 05/12/13: Re: How can I surpress noise in an ADC board?
95333: 06/01/22: Re: How in Design Compiler disable writing out "Assign" statement
102725: 06/05/19: Re: Output gain adjuster of digital filters
102741: 06/05/19: Re: Output gain adjuster of digital filters
107731: 06/08/31: Re: Performance Appraisals
107749: 06/08/31: Re: Performance Appraisals
107891: 06/09/01: Re: Performance Appraisals
107898: 06/09/01: Re: Performance Appraisals
107933: 06/09/02: Re: Performance Appraisals
108138: 06/09/05: Re: Forth-CPU design
108315: 06/09/07: Re: Performance Appraisals
108436: 06/09/11: Re: Performance Appraisals
109245: 06/09/22: Re: Dell Laptop for Embedded Work
109319: 06/09/23: Re: IBM Thinkpads, used
113427: 06/12/13: Re: IQ multiplier
113504: 06/12/14: Re: IQ multiplier
113527: 06/12/15: Re: IQ multiplier
116797: 07/03/18: Re: how to transform Arun's LDPC code to max-product (Min-sum)?
132796: 08/06/06: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
133933: 08/07/19: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
133937: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
133958: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
133960: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
133961: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
133970: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
133971: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
141502: 09/06/25: Re: 720 Mhz IF Processing
141756: 09/07/06: Re: How to interpret polyphase coefficients generated in MATLAB
141758: 09/07/06: Re: How to interpret polyphase coefficients generated in MATLAB
Jerry Coffin:
93481: 05/12/22: Re: real-time compression algorithms on fpga
93488: 05/12/22: Re: real-time compression algorithms on fpga
93491: 05/12/22: Re: real-time compression algorithms on fpga
93525: 05/12/23: Re: real-time compression algorithms on fpga
95624: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
95871: 06/01/26: Re: open source fpga programmer programs
95897: 06/01/26: Re: open source fpga programmer programs
96028: 06/01/28: Re: open source fpga programmer programs
96221: 06/01/31: Re: Impact 8.1 problems=> uClinux rules on MicroBlaze !!!
96367: 06/02/02: Re: Die Area
96859: 06/02/11: Re: which one among the available FPGAs is best for a fresher?
97254: 06/02/19: Re: FPGA - software or hardware?
97709: 06/02/26: Re: VGA specification
97733: 06/02/26: Re: VGA specification
97794: 06/02/27: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
97795: 06/02/27: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
97838: 06/02/28: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
97858: 06/02/28: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
98005: 06/03/02: Re: FPGA - software or hardware -2-
98008: 06/03/02: Re: FPGA - software or hardware -2-
98159: 06/03/06: Re: Which CPU and Screen Rez for ISE 6.3i ?
98344: 06/03/08: Re: for all those who believe in ASICs....
98407: 06/03/09: Re: delay in altera cyclone about led
101910: 06/05/08: Re: PCI Express and DMA
101960: 06/05/08: Re: Xilinx 3s8000?
116444: 07/03/08: Re: Introducing picosecond delay between two output signals
Jerry D. Harthcock:
46543: 02/09/02: Re: Actel Proto Boards
46545: 02/09/02: Re: MicroBlaze processor core
46567: 02/09/03: Re: Actel Proto Boards
46616: 02/09/04: Re: Any resource about MCU and DSP
46620: 02/09/04: Re: Actel Proto Boards
46687: 02/09/05: Re: Actel Libero
46748: 02/09/06: Re: Actel Proto Boards
46794: 02/09/09: Re: minimalist FPGA system
48881: 02/10/25: Re: Please recommend a FPGA chip!
63002: 03/11/12: Re: Home grown CPU core legal?
jerry english:
11966: 98/09/21: Re: Verilog newsgroup
12986: 98/11/09: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
12952: 98/11/06: FPGA HDL tool benchmarks
13403: 98/12/01: HELP, Tool selection
13696: 98/12/18: GSR
13703: 98/12/18: Re: GSR
14287: 99/01/23: Re: small correction
14507: 99/02/02: Re: Espresso logic tool
14686: 99/02/11: Re: Current of I/O driver
15005: 99/03/02: Re: Fast-turn ASIC vendors
15470: 99/03/25: Re: FPGA Express Synthesis Problem
Jerry English:
4656: 96/11/26: Re: How to use Xilinx ?
8544: 98/01/07: Re: serial conf. PROMS
10637: 98/06/08: Re: FPGA Conversion
10638: 98/06/08: Re: FPGA Conversion
10753: 98/06/16: Re: Wallace trees
19927: 00/01/18: Re: Viterbi decoder in FPGA
20073: 00/01/26: Re: Anyone changed an NT disk serial number?
20974: 00/03/01: Re: Xilinx Tools Vs Altera tools
21021: 00/03/03: Re:
21183: 00/03/09: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86,
22151: 00/04/27: AHDL to Verilog
23455: 00/06/26: Re: How to speed it up?
23990: 00/07/19: synthesizer memory useage
24094: 00/07/26: Re: Variable shifting
24126: 00/07/27: Re: End of my rope.
24752: 00/08/17: Re: Board suggestion for high gate count FPGA board
25163: 00/08/29: Re: largest fpga in the industry
25469: 00/09/12: Anybody receiving Spartan II?
26081: 00/10/03: Re: "Xilinx Adds FPGA Support to Free Web Design Tools"
26111: 00/10/04: Re: Xilinx Licensing.
26204: 00/10/08: Foundation iSE and Coregen limited devices
26564: 00/10/20: Re: Virtex E development boards
26877: 00/11/02: Re: Excellent Opportunity ASIC Engineers CA International Relocation
26897: 00/11/02: Re: OT: Xilinx T-Shirt
28404: 01/01/11: Xilinx's XST hanging
28785: 01/01/24: Re: Xilinx's XST hanging
29083: 01/02/05: Re: who wants to work in France ????
29542: 01/02/26: Re: Spartan II power
29603: 01/02/28: Re: Virtex ambit support
29850: 01/03/13: bonding information
Jerry Francis:
44025: 02/06/10: Virtex 2 Pro Board
44087: 02/06/11: Visual SourceSafe and VHDL files
Jerry Greer:
853: 95/03/13: Re: Questions of implementing asynchronous circu
Jerry Hicks:
7758: 97/10/11: Re: FPGA News Resource Page
7759: 97/10/11: Looking for CUPL, PALASM, etc. source
7763: 97/10/12: Re: design sites
7866: 97/10/25: Re: Anyone know of an I2C Controller design for an FPGA?
Jerry McGoveran:
3803: 96/08/05: Re: Job posting
Jerry O'Keefe:
9237: 98/03/03: Re: Survey - Proto Board for Xilinx FPGA
Jerry Pongstaporn:
27760: 00/12/06: dual port ram for altera
Jerry Schroefter:
28217: 01/01/01: Re: Virtex ROM ques.
Jerry Zdenek:
11044: 98/07/14: Re: Dataio Chipwriter won't burn Altera EPC1 generated with Maxplus2 8.2 or greater???
17196: 99/07/08: Re: Altera 10K I/O's
17323: 99/07/21: Re: Solaris vs. NT
jerry1111:
39923: 02/02/22: Re: Beginner Altera Questions
40079: 02/02/26: Re: Beginner Altera Questions
40184: 02/03/01: Re: Beginner Altera Questions
40197: 02/03/01: Altera Excalibur
40219: 02/03/02: Re: Altera Excalibur
40221: 02/03/02: Re: Altera Excalibur
40241: 02/03/03: Re: Altera Excalibur
41626: 02/04/03: Re: powerpc in virtex2pro
42861: 02/05/05: Re: Xilinx MicroBlaze, Opinion?
42966: 02/05/08: Re: Xilinx MicroBlaze, Opinion?
43791: 02/06/03: Re: fpga cpu
43840: 02/06/04: Re: fpga cpu
43841: 02/06/04: Re: fpga cpu
43843: 02/06/04: Re: NIOS GNUPro tool chain + SDK for Linux
43851: 02/06/04: Re: fpga cpu
44585: 02/06/24: Re: Help!I can't use the programmer of Max-plus II on windows XP.
49337: 02/11/09: Re: Compiling Altera Nios Designs
49450: 02/11/12: Re: FPGA Size?
54084: 03/04/02: Matrix multiply in FPGA
54095: 03/04/02: Re: Matrix multiply in FPGA
54181: 03/04/04: Re: Matrix multiply in FPGA
54237: 03/04/05: Re: Matrix multiply in FPGA
55341: 03/05/04: Re: 2.5V switching regulator for Spartan 2
56281: 03/06/02: Re: NIOS-GERMS
62563: 03/11/01: Nios & external RAM
62566: 03/11/01: Re: Nios & external RAM
64189: 03/12/19: Re: Spartan3 availability
64215: 03/12/20: Re: Spartan3 availability
64228: 03/12/21: Re: Spartan3 availability
68819: 04/04/20: Re: NIOS: Run program from SDRAM
68934: 04/04/22: Re: NIOS: Run program from SDRAM
<jerryjsy@hotmail.com>:
89710: 05/09/23: Need help in Flash simulation module.
<jerryzy@gmail.com>:
90627: 05/10/17: Newbie question: XC3S400 Gate Count
90679: 05/10/18: Re: Newbie question: XC3S400 Gate Count
Jerzy:
46675: 02/09/05: OFDM - looking for something more
47199: 02/09/20: Re: Overheat with XCV-600E
48721: 02/10/23: ngdbuild - command line in xilinx' ISE tools
48775: 02/10/24: Re: ngdbuild - command line in xilinx' ISE tools
49803: 02/11/21: Re: Xilinx programming and PCI printer port
54089: 03/04/02: FFT 256pt on Spartan
54140: 03/04/03: Re: Xilinx Divider Core
54549: 03/04/14: Simulate Post-PAR VHDL Model - Error
57944: 03/07/10: viterbi - SMU - trace back calculation
69343: 04/05/07: Virtex2 (500) DCM Frequency Synthesize
69368: 04/05/08: Re: Virtex2 (500) DCM Frequency Synthesize
Jerzy Gbur:
43076: 02/05/13: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43245: 02/05/17: Re: Timing constraints on internal signals
43410: 02/05/21: Off topic - a little
44577: 02/06/24: CIC filter
60409: 03/09/12: Re: DCM not locking in XC2V4000
60491: 03/09/15: Re: DCM not locking in XC2V4000
71397: 04/07/17: Re: Xilinx Virtex-II Configuration in Slave Serial
83001: 05/04/21: Re: LVDS pin assignment
83094: 05/04/23: Re: Xilinx multiplier out of slices
86922: 05/07/09: Re: Rocket IO failure after power cycle.
87481: 05/07/25: Re: DCM.
93211: 05/12/16: Re: Parallel Cable III is not detected
94102: 06/01/05: Re: Virtex2 I/O state in configure phase
94501: 06/01/12: Re: Virtex2 I/O state in configure phase
94492: 06/01/12: Re: Virtex2 I/O state in configure phase
97451: 06/02/22: FPGA to ASIC migrate
97642: 06/02/25: Re: FPGA to ASIC migrate
113962: 06/12/31: Re: Memory controller design
jerzy.gbur@gmail.com:
86636: 05/07/01: Re: interpolation in FPGA
90700: 05/10/19: Re: which is Low power FPGA?
90745: 05/10/20: Re: which is Low power FPGA?
92824: 05/12/07: Re: A stupid question about constraints
93852: 06/01/02: Re: basic DSP with FPGA
93853: 06/01/02: Re: Start up condition of flip flops in FPGA?
93976: 06/01/04: Re: DCM and buffers
95688: 06/01/25: Re: Remapping from Virtex-II to Virtex-4
94086: 06/01/05: Virtex2 I/O state in configure phase
95964: 06/01/27: Re: SDRAM Controller
98765: 06/03/16: Re: ADC Interleaving
109683: 06/10/03: Re: Virtex 4 Configuration Pins
114029: 07/01/03: Re: Memory controller design
117563: 07/04/04: Re: Conceptos about VCCINT,VCCAUX,etc
120017: 07/05/31: Re: Virtex4 Configuration Problem
124384: 07/09/20: Re: Virtex-4 SELECT MAP configuration
124755: 07/10/03: Tcl - Xilinx - ISE - WindowsXP
124776: 07/10/04: Re: Tcl - Xilinx - ISE - WindowsXP
124813: 07/10/05: Re: Tcl - Xilinx - ISE - WindowsXP
126458: 07/11/23: Re: xilinx spartan 3 + 16 adc
133847: 08/07/17: Re: What's wrong with this Virtex4 DCM?
135097: 08/09/16: Re: Ultra low power FPGAs
135288: 08/09/24: Re: OFDM band switch ...
135322: 08/09/26: Re: OFDM band switch ...
135368: 08/09/29: Re: OFDM band switch ...
136053: 08/10/29: Re: Possibility of Driving FPGA clock from an other FPGA ?
143626: 09/10/19: Re: Handwritten recognition using FPGA
147736: 10/05/20: Availability of XC6SLX16-2CPG196C
jerzy.zielinski:
107639: 06/08/30: xgpio_DiscreteRead
107857: 06/09/01: Read from Microblaze
109149: 06/09/21: Interrupts in Microblaze
109256: 06/09/22: Re: Interrupts in Microblaze
113539: 06/12/15: uClinux bootloader on Spartan-3e Starter Kit
Jesper Kristensen:
45636: 02/07/30: How to generate correct Express Mode configuration bit stream for Spartan-XL...?
68173: 04/03/28: C++ Runtime Error when using RTL View in ISE6.2i WebPack...
152526: 11/09/03: Virtex-6 XC6VHX380T Master SPI Configuration Problems....
152533: 11/09/06: Re: Virtex-6 XC6VHX380T Master SPI Configuration Problems....
<Jesper.Kristensen@tellabs.com>:
105209: 06/07/17: Reuse a Speed Grade -8 Stratix image in Speed Grade -6 ...?
113149: 06/12/06: Quartus II: Back-annotating bidir's gives two entries per pin...
121469: 07/07/05: Spartan-3A: 200A & 400A Image problems / variance...
Jespr:
132225: 08/05/18: Problem with Scheduler in Xilkernel.
132268: 08/05/19: Re: Problem with Scheduler in Xilkernel.
132302: 08/05/20: Re: Problem with Scheduler in Xilkernel.
Jess:
19717: 00/01/09: Make thousands$$$$ form only $6!!!!!!!!!!!!!!!!!
jesse:
31687: 01/06/02: QuickLogic programming HW for sale
36384: 01/11/07: QuickLogic Programmer (s) for Sale
Jesse Bouwman:
9107: 98/02/21: Re: Free FPGA tools???
jesse jenkins:
57805: 03/07/07: Re: XPLA3 vs. MAX3000A
Jesse Kempa:
40119: 02/02/27: Re: microblaze
40192: 02/03/01: Re: microblaze
42092: 02/04/15: Re: problems with Nios 2.0
43814: 02/06/03: Re: ALtera SOPC Builder
44320: 02/06/17: Re: MicroBlaze uClinux port?
46467: 02/08/30: Re: Crashes while reading from memory with Nios
47670: 02/10/01: Re: Nios interrupt latency?
47757: 02/10/03: Re: TCP/IP in FPGA
49197: 02/11/04: Re: 2-nios design using SOPC builder
53099: 03/03/03: Re: Nios - > 8 bit Ram
53636: 03/03/18: Re: LogicLock and SOPC Builder
54437: 03/04/10: Re: Cheap(er) FPGA configuration?
54809: 03/04/18: Re: Avalon Bus Master
54947: 03/04/22: Re: NIOS 3.0 Spurious Interrupts
54981: 03/04/23: Re: NIOS 3.0 Spurious Interrupts
55923: 03/05/23: Re: Using GERMS monitor with NIOS CPU on non-Altera board
56156: 03/05/29: Re: Any recommendation for an FPGA kit ?
56298: 03/06/02: Re: NIOS-GERMS
57511: 03/07/01: Re: Can Altera NIOS processor be syntheized on a Flex FPGA
58540: 03/07/25: Re: Altera Nios 3: Using Interface To User Logic Problem
58671: 03/07/30: Re: SRAM question in Cyclone Dev. Board
58924: 03/08/04: Re: Tiny TCP/IP stack and tiny MAC controller on FPGA for direct download to S(D)RAM memory
58945: 03/08/04: Re: Nios Ethernet Development Kit Problems
59237: 03/08/12: Re: Nios Clock Frequency
59348: 03/08/15: Re: Memory map in Altera NIOS
60272: 03/09/09: Re: Suitable FPGA architecture for Robots..
60274: 03/09/09: Re: system simulation and verification methods (NIOS)
60611: 03/09/17: Re: fpga +cpu + wireless
60620: 03/09/17: Re: Nios Quartus II Question...
60647: 03/09/18: Re: mouse to Nios Development kit
60691: 03/09/19: Re: mouse to Nios Development kit
60786: 03/09/22: Re: Italy is out of FPGA world?
61175: 03/09/29: Re: NIOS and OCI
61429: 03/10/03: Re: Quartus II tutorial vs the real world
61433: 03/10/03: Re: Xilinx courses
61534: 03/10/06: Re: MicroBlaze size
61536: 03/10/06: Re: large integer support in GNUPro for Altera Nios software development
61947: 03/10/15: Re: mp3 project
61966: 03/10/15: Re: Debugging software in an ACEX device with Nios 32 via JTAG
62064: 03/10/17: Re: Xilinx Slice and Altera ...?
62139: 03/10/20: Re: Debugging software in an ACEX device with Nios 32 via JTAG
63006: 03/11/12: Re: Code for accessing CF cards on Cyclone dev.board
63907: 03/12/08: Re: NIOS: Running code from flash
63938: 03/12/09: Re: NIOS: Running code from flash
64171: 03/12/18: Re: interfacing a WishBone IP core to a CoreConnect bus
64474: 04/01/05: Re: Floating point in Nios SDK
64481: 04/01/05: Re: dynamic memory allocation NIOS
64899: 04/01/15: Re: yo, Mr. FPGA Engineer
65741: 04/02/05: Re: Stratix II NIOS sizes ?
65744: 04/02/05: Re: Differences between Xilinx ISE and Altera Quartus software
65885: 04/02/09: Re: Is nobody using c++ and/or plugs-lib? was Re: nios c++ and ethernet [may by ot?]
65904: 04/02/09: Re: Stratix II NIOS sizes ?
66189: 04/02/13: Re: APEX fit problem
66498: 04/02/20: Re: Dhrystone figures - Was: Microblaze instruction timings
66826: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
68073: 04/03/25: Re: Altera NIOS SOPC Builder---- Can I edit a text file
68402: 04/04/02: Re: Can't do a single byte read in Nios?
69167: 04/04/28: Re: Error in SoPC Builder
69285: 04/05/04: Re: Best way to handle multiple common data busses in Altera FPGA (and others)
69300: 04/05/05: Re: Altera SoPC builder command line system generator
69624: 04/05/16: Re: best fpga development board?
69760: 04/05/19: Re: Nios II Going Live...
69761: 04/05/19: Re: NIOS Board Stratix Edition - FPGA won't configure
69812: 04/05/20: Re: Never right, always room for improvement
69818: 04/05/20: Re: program flash memory through JTAG on FPGA
69841: 04/05/21: Re: Never right, always room for improvement
69914: 04/05/24: Re: NIOS Board Stratix Edition - FPGA won't configure
70080: 04/06/01: Re: NIOS 2 memory limitations
70304: 04/06/11: Re: Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5
70429: 04/06/16: Re: Using Altera libraries for Nios Dev Board
70430: 04/06/16: Re: C Header files for User Design Logic in the Nios.
70432: 04/06/16: Re: Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5
70865: 04/06/30: Re: Altera SOPC Master Peripheral Design?
70870: 04/06/30: Re: Altera Nios Ethernet Development Kit: "spurious interrupt number: 0000 001C"
71238: 04/07/12: Re: Nios - Ethernet Frame Format
71243: 04/07/12: Re: NIOS 2 HAL, libraries, ...
71276: 04/07/13: Re: Using gprof with Nios II
71316: 04/07/14: Re: Altera SOPC SDRAM & CLK Input?
71355: 04/07/15: Re: Altera SOPC SDRAM & CLK Input?
72428: 04/08/18: Re: Nios II debugging with gdb
72429: 04/08/18: Re: Nios II debugging with gdb
72444: 04/08/18: Re: NIOS II memory devices on tristate bridges
72466: 04/08/19: Re: NIOS II memory devices on tristate bridges
72471: 04/08/19: Re: Nios II debugging with gdb
72492: 04/08/20: Re: NIOS II Sim
72495: 04/08/20: Re: NIOS II memory devices on tristate bridges
73665: 04/09/27: Re: NIOS II / Cyclone II - Multiply, Barrel Shift and Divide
73666: 04/09/27: Re: [ALTERA] NIOS-II + MMU + FPU
74146: 04/10/04: Re: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
75841: 04/11/16: Re: Hello anyone! Does someone works with CS8900 under NIOSII? It's really works? Please, write works it with HAL? Thx.
76441: 04/12/02: Re: NIOS II & CS8900?
jesse lackey:
114772: 07/01/24: Re: Xilinx ISE 8.2
115024: 07/01/29: Re: Global Clocks in Xilinx ISE
119716: 07/05/25: Testbenches in C driving ISE simulator?
Jesse Newcomb:
20536: 00/02/13: QuickLogic FPGA programmers for sale
20538: 00/02/13: HP 16500B logic analyzer for sale
21065: 00/03/05: QuickLogic programmers for sale
<jesse@jumboprawn.net>:
24207: 00/07/29: QuickLogic programmer bits for sale
26619: 00/10/22: QuickLogic programmer(s) for sale
<jesse@telematrix.com>:
746: 95/02/22: ITC
<jessen@sgi.com>:
12164: 98/10/02: Looking for QuickLogic programmer
Jessica Felix:
<jessiek@polbox.com>:
18714: 99/11/09: Re: Frequency Division in Altera AHDL ?
18727: 99/11/10: Re: Frequency Division in Altera AHDL ?
Jesus Jimenez:
56224: 03/05/31: Re: Simulation in Altera Quartus II
56225: 03/05/31: Is it possible to simulate Nios designs with Quartus?
56484: 03/06/06: Re: Is it possible to simulate Nios designs with Quartus?
Jesus Molina:
39828: 02/02/20: PCI/FPGA evaluation board
39836: 02/02/20: Re: PCI/FPGA evaluation board
Jet Morgan:
81881: 05/04/03: Re: problem in driving I2C bus through memory-mapped register
jetmarc:
37955: 01/12/27: Atmel FPSLIC - Problem with concurrent statements
37976: 01/12/28: Re: Atmel FPSLIC - Problem with concurrent statements
39622: 02/02/14: Lean serial communication processor
43111: 02/05/14: Bus arbiter with low latency
43728: 02/05/31: LFSR with 2^n instead of (2^n)-1
43755: 02/05/31: Re: LFSR with 2^n instead of (2^n)-1
43768: 02/06/01: Clock double trigger problem
43782: 02/06/02: Re: Clock double trigger problem
43906: 02/06/05: Re: burning a design
45206: 02/07/15: AT40K / FPSLIC - Place & Route tools (3rd party)?
45228: 02/07/16: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45392: 02/07/22: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45393: 02/07/22: Delays in Leonardo
45678: 02/07/31: Re: tone detection...
45945: 02/08/12: Re: Programming bits reverse engineering
46336: 02/08/26: Evaluation board recommendation?
51324: 03/01/10: Re: External RAM...
51325: 03/01/10: Re: shift register implementation
51604: 03/01/17: Re: Multiple FPGA-boards integration issues
51784: 03/01/21: Re: Atmel FPSLIC UART Code
51786: 03/01/21: Re: FLEXlm
51837: 03/01/23: Re: FLEXlm
52322: 03/02/06: Re: low pass FIR filter in FPGA
52665: 03/02/18: Re: About automatically programming my FPGA
54870: 03/04/21: Re: Atmel FPSLIC BGA, real?
56227: 03/05/31: Re: FPGA's an Flash
56356: 03/06/03: Re: FPGA's an Flash
56631: 03/06/10: Re: What's in a bitstream?
57330: 03/06/27: Re: Partial reconfiguration of Vertex-2 devices.
57600: 03/07/02: Re: Everything need a reset?
59747: 03/08/27: Can SpartanIIE talk 3.3v and 1.8v at the same time?
60612: 03/09/17: Re: platform flash as storage?
60614: 03/09/17: Re: Digilent board
60787: 03/09/22: Re: FPGA implementation in (V)HDL
61227: 03/09/30: Timing constraint for BUFG?
61287: 03/10/01: Re: Timing constraint for BUFG?
61923: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
61957: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
62830: 03/11/09: Re: Building the 'uber processor'
<jetmarc@hotmail.com>:
95006: 06/01/20: Security of Xilinx Virtex2 Pro
100471: 06/04/10: Re: Compiler to FPSLIC
100530: 06/04/11: Re: Atmel FPSLIC
105986: 06/08/04: Re: 100m JTAG cable
111219: 06/10/31: Re: Taking forever to synthesise (XILINX ISE 8.1i)
111603: 06/11/06: ISE/EDK project on a file server?
112031: 06/11/15: Share BRAM for data and instruction OCM?
112556: 06/11/24: Re: Protecting netlist for Xilinx
112827: 06/11/29: ISE on a cluster?
113232: 06/12/08: Barrel shifter in Virtex4?
113626: 06/12/18: FX12 ethernet resource usage
113874: 06/12/27: Re: OPB master implementation
114255: 07/01/09: V4FX PPC data cache behaviour?
114848: 07/01/25: On-chip randomness (V4FX)
115004: 07/01/29: Re: On-chip randomness (V4FX)
115397: 07/02/09: Re: Need advice to help improve timing on V4 FX
115954: 07/02/26: Re: Not power of two BRAM size problem
116154: 07/03/02: Re: OPB-to-PLB bridge
116423: 07/03/08: Load V4 bitstream encryption key with XSVF
116449: 07/03/09: Re: Load V4 bitstream encryption key with XSVF
116451: 07/03/09: Re: Load V4 bitstream encryption key with XSVF (solved)
116674: 07/03/15: Re: Programming XCF from MicroBlaze over JTAG???
116807: 07/03/19: Re: Programming XCF from MicroBlaze over JTAG???
117111: 07/03/23: Re: FPGA with 5V and PLCC package
118025: 07/04/16: Re: OPB To Wishbone Bridge
118129: 07/04/18: Re: OPB To Wishbone Bridge
118339: 07/04/24: Re: Slave PLB core interrupt
118471: 07/04/27: Prope timing constraint for this pin?
118722: 07/05/02: Re: ISE 8.2 Strange cache problem? Warning...
118726: 07/05/02: Re: Read 64-bit value over PLB
118753: 07/05/03: Re: OPB Master Peripheral
118848: 07/05/04: Re: Select pullup, pulldown or none via embedded S/W
118961: 07/05/08: Chipscope with custom cable?
119092: 07/05/11: V4FX PPC ICU data transfer timeout?
119851: 07/05/28: Atmel FPSLIC users out there?
120749: 07/06/15: Re: booting a large V4 PPC program with a minimum of on chip bram
121250: 07/06/29: Re: d-link router?
122281: 07/07/25: Re: Xint64 ?
122550: 07/07/31: Re: Looking for PLD with embedded memory
122551: 07/07/31: Re: Looking for 2 simple Xilinx examples of FSL
126018: 07/11/12: Re: Embedded Linux & Code Security
129733: 08/03/04: Re: Software Defined Radio auf Xilinx Virtex 4
129773: 08/03/05: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
133375: 08/06/26: Re: FPGA area use by module?
133586: 08/07/04: Re: Processor Debug interface
135129: 08/09/17: Re: SDRAM question
135131: 08/09/17: Re: Random Mask Generation on FPGAs
136992: 08/12/17: V4FX PPC405: DCR bus and synchronization
137602: 09/01/23: Re: XPS PowerPC accessing DCR register
138100: 09/02/06: Re: Xilinx Powerpc issue with custom peripherals
140129: 09/04/29: ASIC from working FPGA design
140255: 09/05/06: Re: some soft-processors
140757: 09/05/25: Re: BSCAN_SPARTAN3 proper use with CAPTURE and UPDATE
jetq88:
106660: 06/08/16: xilinx or altera?
108441: 06/09/11: VHDL or Verilog or SystemC?
109548: 06/09/28: Re: ISE DDR Memory Controller to write between RAM and FPGA
109551: 06/09/28: Re: ISE DDR Memory Controller to write between RAM and FPGA
109742: 06/10/04: Can I use MIG tool to generate memory controller for DIMM module of DDR SDRAM?
114039: 07/01/03: Spartan3 XC3S400 won't work after upgrading ISE from ISE6.3 to ISE8.2
114662: 07/01/22: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
115597: 07/02/14: Need fair opinions on choosing either Altera or Xilinx as main FPGA source
117506: 07/04/02: Re: Does the XC3S250E-VQ100 exist?
117522: 07/04/03: Re: Implementing a communication protocol for data transfer over TCP on an FPGA
117632: 07/04/05: what is the best practice to exchange data between microblaze softcore and customer hardware writen in VHDL
jeung joon ee:
26679: 00/10/24: ultra low cost Evaluation boards
30641: 01/04/20: FREE SDRAM-controller core
jeverett@xilinx.com:
98701: 06/03/14: Re: Why does Xilinx hate version control?
jey:
128127: 08/01/16: Basic FPGA question about Reset
128131: 08/01/16: Re: Basic FPGA question about Reset
128133: 08/01/16: Re: Basic FPGA question about Reset
jeycrisis:
83920: 05/05/09: Configuring an XC3S400 Spartan 3 with JTAG
83961: 05/05/10: Re: Configuring an XC3S400 Spartan 3 with JTAG
83974: 05/05/10: Re: Configuring an XC3S400 Spartan 3 with JTAG
Jez Smith:
65834: 04/02/07: Xilinx webpack
<jez-smith@hotmail.co.uk>:
112762: 06/11/28: Re: verilog 2 VHDL translator
112778: 06/11/28: Re: Double buffering
112811: 06/11/29: Re: FPGA application field
112838: 06/11/29: Re: FPGA application field
112858: 06/11/29: Re: ISE on a cluster?
112899: 06/11/30: Re: DCM jitter (again)
112902: 06/11/30: Re: DCM jitter (again)
Jezwold:
77544: 05/01/10: Re: Configuration devices
77558: 05/01/10: Re: San Jose job offer - need advice
77595: 05/01/11: Re: (d)ram interface
77641: 05/01/12: Re: Configuration devices
77719: 05/01/15: Re: Questions from a beginner...
77723: 05/01/15: Re: Questions from a beginner...
77724: 05/01/15: Re: Cheap source for GAL's
77962: 05/01/20: Re: lasy question about VHDL: logic between a bit and a vector
78029: 05/01/23: Don't touch in altera maxplus 2
78030: 05/01/23: Re: Microscope examination of a PLD
78130: 05/01/25: Re: Don't touch in altera maxplus 2
78308: 05/01/28: Re: How do I get the contents in FPGA
78317: 05/01/29: Re: Sensitive List Question
78318: 05/01/29: Re: Sensitive List Question
78321: 05/01/29: Re: Quartus II megafunction
78329: 05/01/29: Re: Sensitive List Question
78330: 05/01/29: Re: Quartus II megafunction
78338: 05/01/29: Re: i need xilinx edk
78340: 05/01/29: Re: i need xilinx edk
78370: 05/01/30: Re: OT: Design security
78419: 05/01/31: Re: Design security
78460: 05/02/01: Re: Evaluating EDIF netlist
78501: 05/02/01: Re: MP3 Player Project
78503: 05/02/01: Re: Design security
78551: 05/02/03: Re: How to handle clock skew?
78557: 05/02/03: Re: Q, compile option, mb-gcc
78574: 05/02/03: Re: Help, i'm geting warnings :-(
78646: 05/02/04: Re: Spartan-3 Starter Kit supplier in the UK?
78853: 05/02/08: Re: .vho (Xilinx Core Generator) to .vhd ??
78984: 05/02/10: Re: Sending text from fpga to printer
78985: 05/02/10: Re: C program to big for microblaze?
79025: 05/02/11: Re: Altera's Megafunction altaccumulator
79030: 05/02/11: Re: ISE and IEEE.Fixed_pkg (fixed point math for synth?)
79474: 05/02/19: Re: why to use FIFO on FPGA?
79564: 05/02/20: Re: WYSIWYG option in xilinx webpack 6.3
79772: 05/02/24: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
79900: 05/02/25: Re: Error in ISE 6.3
79962: 05/02/27: Re: I2C protocol to communicate between FPGAs
80875: 05/03/13: Re: Which HDL?
80930: 05/03/14: Re: Which HDL?
81091: 05/03/17: Re: Newbie: Slow FPGAs
81099: 05/03/17: Re: Newbie: Slow FPGAs
Jezz:
75376: 04/11/03: Re: FPGA for Game and Amusement
75391: 04/11/04: Re: FPGA for Game and Amusement
jf hasson:
45676: 02/07/31: logicore pci macro in virtex problem
jfh:
34136: 01/08/15: Hysteresis behavior of an fpga buffer
34807: 01/09/08: Powering up a multi virtex fpga board
36835: 01/11/21: slew rate of virtex output buffers figures
43235: 02/05/17: LOCKED signal of a DLL in a Virtex device questions
87874: 05/08/03: RocketIO connexion to an optical transceiver
87875: 05/08/03: Re: RocketIO connexion to an optical transceiver
87879: 05/08/03: Re: RocketIO connexion to an optical transceiver
87885: 05/08/03: Re: RocketIO connexion to an optical transceiver
94902: 06/01/18: profiling with virtex4 powerpc
99579: 06/03/26: Linux on ml403
99766: 06/03/28: Re: Linux on ml403
99928: 06/03/30: Re: Linux on ml403
112777: 06/11/28: Hardware in the loop simulation for Altera design
112856: 06/11/29: Re: Hardware in the loop simulation for Altera design
139347: 09/03/27: PLL in Actel Igloo part
139360: 09/03/27: Re: PLL in Actel Igloo part
139365: 09/03/27: Re: PLL in Actel Igloo part
144366: 09/12/01: PMC or XMC based on Altera parts (preferably Stratix)
145423: 10/02/08: Progrmming a flash connected to a Stratix II GX
146399: 10/03/15: Nested interrupts in Nios system and hung system
JFMAHER:
1751: 95/08/24: For Sale: Chronology Package...
2138: 95/10/19: For Sale:Chronology Docutime
JG:
111547: 06/11/05: Spartan3E kit and BPI configuration problem.
112681: 06/11/27: What's the status regarding MicroBlaze, Lynuxworks and uClinux 2.6?
-jg:
114211: 07/01/07: Re: Problem with unused pin on Spartan 2E
114212: 07/01/07: Re: First Picture of Craignell Modules
114246: 07/01/08: Re: First Picture of Craignell Modules
114305: 07/01/11: Re: Quick question on Coolrunner II IO voltages
114334: 07/01/11: Re: inserting text into a video stream (from a pre-existing video source)
114336: 07/01/11: Re: picoblaze RS-232 using 62.5 MHz
114383: 07/01/13: Re: Will FPGAs suit my need?
114427: 07/01/15: Re: ISE 9.1i and partial reconfiguration
114465: 07/01/16: Re: interesting article FPGA routing field programmable nanowire interconnect (FPNI)
114467: 07/01/16: Re: microcode in verilog?
114587: 07/01/19: Re: Phasse Detector
114609: 07/01/20: Re: Phasse Detector
114681: 07/01/22: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114835: 07/01/24: Re: Does xiling cpld's need a power supply bypass cap?
114961: 07/01/27: Re: Minimal design for xilinx?
114962: 07/01/27: Re: Minimal design for xilinx?
115945: 07/02/26: Re: Spartan-3AN
115965: 07/02/26: Re: Spartan-3AN
116849: 07/03/19: Re: Altera introduces Cyclone III devices, ships 65nm
116860: 07/03/19: Re: Altera introduces Cyclone III devices, ships 65nm
117858: 07/04/11: =?iso-8859-1?q?Re:_CPLD_+_=B5C_with_reasonably-priced_tools=3F?=
117859: 07/04/11: Re: Measuring the period of a signal
117951: 07/04/14: Re: picoblaze C compiler download wanted
118361: 07/04/24: Re: FPGA and DAC for wave generation
127539: 08/01/01: Re: Where are the LCD or OLED bitmapped displays?
127546: 08/01/01: Re: Where are the LCD or OLED bitmapped displays?
127840: 08/01/09: Re: Real examples of metastability causing bugs
127844: 08/01/09: Re: Low Power CPU Implementation
127846: 08/01/09: Re: Processor in CPLD
127986: 08/01/11: Re: Real examples of metastability causing bugs
127995: 08/01/11: Re: Real examples of metastability causing bugs
127998: 08/01/11: Re: Real examples of metastability causing bugs
128012: 08/01/12: Re: Real examples of metastability causing bugs
128014: 08/01/12: Re: Real examples of metastability causing bugs
128030: 08/01/14: Re: Real examples of metastability causing bugs
128075: 08/01/14: Re: Real examples of metastability causing bugs
128089: 08/01/15: Re: Real examples of metastability causing bugs
128116: 08/01/15: Re: Debbuging a RISC processor on an FPGA
128266: 08/01/19: Re: Source of accurate frequency
128275: 08/01/19: Re: Source of accurate frequency
128283: 08/01/20: Re: Source of accurate frequency
128316: 08/01/22: Re: Source of accurate frequency
128353: 08/01/22: Re: Ballistic chronograph using a Spartan 3E starter board
128408: 08/01/24: Re: Virtex-4 driving a 5V CMOS
129824: 08/03/06: Re: Anyone to open "FPGA museum" ? Here is first item :)
130433: 08/03/24: Re: counterfeit Xilinx ?
131366: 08/04/20: Re: Problem writing quadrature decoder
131389: 08/04/20: Re: Problem writing quadrature decoder
131390: 08/04/21: Re: Problem writing quadrature decoder
131461: 08/04/21: Re: Problem writing quadrature decoder
131489: 08/04/22: Re: counterfeit Xilinx ?
131616: 08/04/26: Re: Problem writing quadrature decoder
131617: 08/04/26: Re: ATF750 for Proteus
131636: 08/04/27: Re: Problem writing quadrature decoder
131637: 08/04/27: Re: Problem writing quadrature decoder
133395: 08/06/26: Re: Beginner : Rotary switch (quad sw)
137619: 09/01/23: Re: Altera 3000A: Can I make a freq. generator (1 Hz to 2 kHz) ?
137620: 09/01/23: Re: Altera 3000A: Can I make a freq. generator (1 Hz to 2 kHz) ?
137633: 09/01/24: Re: Altera 3000A: Can I make a freq. generator (1 Hz to 2 kHz) ?
137829: 09/01/30: Re: Spartan-6
137934: 09/02/02: Re: Spartan-6
137935: 09/02/02: Re: Why the second flip-flop in Virtex-6?
137942: 09/02/02: Re: Spartan-6
137950: 09/02/02: Re: Spartan-6
138002: 09/02/03: Re: Why the second flip-flop in Virtex-6?
138003: 09/02/03: Re: Spartan-6
138004: 09/02/03: Re: Tabula - new kid on the FPGA block?
138021: 09/02/04: Re: Sixteen serial ports ?
138022: 09/02/04: Re: Spartan-6
138023: 09/02/04: Re: Why the second flip-flop in Virtex-6?
138025: 09/02/04: Re: Why the second flip-flop in Virtex-6?
138052: 09/02/04: Re: Antti-Brain issue 5 released
138053: 09/02/04: Re: Antti-Brain issue 5 released
138344: 09/02/16: Re: cpld 9572 xilinx
138420: 09/02/20: Re: Very fast counter in VirtexII
138521: 09/02/25: Re: Very fast counter in VirtexII
138599: 09/03/01: Re: New person to CPLD programming
138830: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138851: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138871: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138931: 09/03/15: Re: Getting started with FPGA
138989: 09/03/17: Re: Zero operand CPUs
139045: 09/03/19: Re: Documenting a simple CPU
139049: 09/03/19: Re: Documenting a simple CPU
139075: 09/03/19: Re: Documenting a simple CPU
139076: 09/03/19: Re: Documenting a simple CPU
139219: 09/03/23: Re: Silicon Blue last datesheet correct URL
139220: 09/03/23: Re: Silicon Blue last datesheet correct URL
139226: 09/03/23: Re: Silicon Blue last datesheet correct URL
139227: 09/03/23: Re: Silicon Blue last datesheet correct URL
139228: 09/03/23: Re: Silicon Blue last datesheet correct URL
139247: 09/03/24: Re: Silicon Blue last datesheet correct URL
139269: 09/03/24: Re: FPGAs in automotive apps (was Re: Silicon Blue last datesheet
139271: 09/03/24: Re: Antti Processor
139313: 09/03/26: Re: Looking for a low-cost development kit
139371: 09/03/27: Re: best soft core(s) that have C compiler support
139384: 09/03/27: Re: best soft core(s) that have C compiler support
139388: 09/03/27: Re: best soft core(s) that have C compiler support
139390: 09/03/28: Re: best soft core(s) that have C compiler support
139409: 09/03/28: Re: What does Xilinx mean by "Real 6-input look-up (LUT) technology"?
139437: 09/03/29: Re: best soft core(s) that have C compiler support
139512: 09/04/01: Re: Switching an AC power socket from an FPGA
139543: 09/04/02: Re: delays in XC95144XL CPLD
139559: 09/04/03: Re: delays in XC95144XL CPLD
139678: 09/04/08: Re: Two stage synchroniser,how does it work?
139679: 09/04/08: Re: ANN: Antti-Brain March issue released
139883: 09/04/18: Re: Dual-frequency quartz oscillator with a FPGA ?
139904: 09/04/18: Re: Dual-frequency quartz oscillator with a FPGA ?
139911: 09/04/18: Re: Dual-frequency quartz oscillator with a FPGA ?
140203: 09/05/03: Re: High-speed signals crossing a split-ground
140326: 09/05/08: Re: Can the complex DSP archetecture based on FPGA+DSP be replaced by
140451: 09/05/13: Re: cheapest FPGA?
140490: 09/05/14: Re: cheapest FPGA?
140492: 09/05/14: Re: Xilinx 5V FPGA available from distributors again???
140549: 09/05/16: Re: some soft-processors
140561: 09/05/17: Re: some soft-processors
140577: 09/05/18: Re: SD card bootstrap code in 55 instructions
140578: 09/05/18: Re: XILINX license model restricts longtime availability
140632: 09/05/20: Re: some soft-processors
140634: 09/05/20: Re: Open source processors
140867: 09/05/27: Re: Coolrunner II: what's wrong up here ?
140878: 09/05/27: Re: Old School Altera MAX 7000
140931: 09/05/29: Re: Coolrunner II: what's wrong up here ?
140933: 09/05/30: Re: Has ST's FPGA project GOSPL transformed to Morpheus ?
140992: 09/06/01: Re: phase locking a slow (2Mhz) signal.
141224: 09/06/11: Re: Latest Xilinx Discontinuations
141257: 09/06/12: Re: NTSC/PAL Encoder using FPGA and DAC
141537: 09/06/26: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
141549: 09/06/27: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
141550: 09/06/27: Re: 6/6 infos
141560: 09/06/27: Re: 6/6 infos
141636: 09/07/01: Re: FPGA as FM RADIO transmitter
142077: 09/07/23: Re: Strange FPGA behavior
142087: 09/07/23: Re: How do you handle build variants in VHDL?
142145: 09/07/26: Re: How to implementa an FSM in block ram
142205: 09/07/28: Re: cool chart
142232: 09/07/29: Re: cool chart
142241: 09/07/30: Re: How to implementa an FSM in block ram
142638: 09/08/23: Re: Soft Processor IP core report
142660: 09/08/24: Re: Soft Processor IP core report
142693: 09/08/26: Re: Reading from ADC and writing to DAC at same time
143046: 09/09/17: Re: WARP PLD's are back in new shape
143091: 09/09/19: Re: Actel dropped ARM7, when comes Xilinx ARM enabled silicon?
143092: 09/09/19: Re: Actel dropped ARM7, when comes Xilinx ARM enabled silicon?
143172: 09/09/23: Re: 8 phase clock output
143214: 09/09/25: Re: Super Small MIPS-compatible Altera-Based Soft Processor and
143229: 09/09/27: Re: USB programmable Open Source Hardware
143231: 09/09/27: Re: USB programmable Open Source Hardware
143238: 09/09/28: Re: USB programmable Open Source Hardware
143255: 09/09/28: Re: USB programmable Open Source Hardware
143258: 09/09/28: Re: USB programmable Open Source Hardware
143269: 09/09/29: Re: USB programmable Open Source Hardware
143370: 09/10/07: Re: Ideas for a pulse programmer needed
143418: 09/10/10: Re: Development boards for CPU development ?
143483: 09/10/12: Re: Implement ARM cores on a FPGA chip?
143528: 09/10/14: Re: FPGA on-die LVDS termination issues
143699: 09/10/21: Re: Can I use a crystal for the clock source for a Xilinx Spartan 3A
143734: 09/10/22: Re: Time stability of clock on FPGA board
143735: 09/10/22: Re: Time stability of clock on FPGA board
143774: 09/10/24: Re: Generating delay using logic gates
143910: 09/11/02: Re: 50+ pages fresh from Antti's brain
143911: 09/11/02: Re: Need some help creating a ring oscillator on a Spartan-3AN
143957: 09/11/04: Re: Cyclone IV announced
143992: 09/11/06: Re: CPLD + MCU SoC from Cypress, free samples too!
144010: 09/11/06: Re: CPLD + MCU SoC from Cypress, free samples too!
144032: 09/11/08: Re: Sinewave generation
144033: 09/11/08: Re: Sinewave generation
144035: 09/11/08: Re: OK Xilinx users, it's time I was let in on the joke...
144037: 09/11/09: Re: free software/open source projects and FPGA?
144062: 09/11/09: Re: CPLD + MCU SoC from Cypress, free samples too!
144066: 09/11/09: Re: XPLA3 coolrunner programming tool?
144091: 09/11/10: Re: XPLA3 coolrunner programming tool?
144094: 09/11/10: Re: XPLA3 coolrunner programming tool?
144096: 09/11/11: Re: XPLA3 coolrunner programming tool?
144110: 09/11/11: Re: OK Xilinx users, it's time I was let in on the joke...
144115: 09/11/11: Re: OK Xilinx users, it's time I was let in on the joke...
144116: 09/11/11: Re: XPLA3 coolrunner programming tool?
144120: 09/11/11: Re: XPLA3 coolrunner programming tool?
144121: 09/11/11: Re: XPLA3 coolrunner programming tool?
144136: 09/11/12: Re: max. sinking current of XC95144xl cpld
144299: 09/11/25: Re: 32KHz RTC for FPGA
144301: 09/11/25: Re: 32KHz RTC for FPGA
144306: 09/11/25: Re: 32KHz RTC for FPGA
144308: 09/11/25: Re: 32KHz RTC for FPGA
144312: 09/11/25: Re: 32KHz RTC for FPGA
144313: 09/11/25: Re: 32KHz RTC for FPGA
144317: 09/11/25: Re: 32KHz RTC for FPGA
144328: 09/11/26: Re: some issues with canned oscillators (was Re: 32KHz RTC for FPGA)
144330: 09/11/26: Re: some issues with canned oscillators (was Re: 32KHz RTC for FPGA)
144495: 09/12/10: Re: A new approach to FPGA and PCB System Development Platform, Santa
144753: 09/12/30: Re: Seeking some advice
144827: 10/01/06: Serial Flash reaches 104MHz Quad IO speeds
145020: 10/01/20: Re: Easy PC software tool - Bad experience
145030: 10/01/20: Re: Easy PC software tool - Bad experience
145040: 10/01/21: Re: Easy PC software tool - Bad experience
145073: 10/01/24: Re: timing properties of fpga devices at sub-clock frequencies
145166: 10/01/29: Re: synthesizing a completely empty design for an FPGA to measure
145169: 10/01/30: Re: synthesizing a completely empty design for an FPGA to measure
145171: 10/01/30: Re: synthesizing a completely empty design for an FPGA to measure
145180: 10/01/30: Re: synthesizing a completely empty design for an FPGA to measure
145467: 10/02/10: Re: To get higher clock frequencies at output using propagation
145538: 10/02/13: Re: 28nm FPGAs are coming...
145630: 10/02/16: Re: What is the basis on flip-flops replaced by a latch
145715: 10/02/20: Re: Unpredictable design
145736: 10/02/21: Re: Looking for Ultimate RISC/MISC that runs LINUX Website
145846: 10/02/25: Re: antti alive message
145886: 10/02/26: Re: Frustration with Vendors!
145888: 10/02/26: Re: Frustration with Vendors!
145891: 10/02/26: Re: Frustration with Vendors!
145896: 10/02/26: Re: Frustration with Vendors!
145912: 10/02/27: Re: Frustration with Vendors!
145913: 10/02/27: Re: Frustration with Vendors!
145937: 10/02/28: Re: Frustration with Vendors!
145938: 10/02/28: Re: Frustration with Vendors!
145943: 10/03/01: Re: Frustration with Vendors!
145944: 10/03/01: Spice simulation of IBIS details - model examples
145947: 10/03/01: Re: Spice simulation of IBIS details - model examples
145957: 10/03/01: Re: Spice simulation of IBIS details - model examples
145960: 10/03/01: Re: Spice simulation of IBIS details - model examples
145963: 10/03/01: Re: Spice simulation of IBIS details - model examples
145991: 10/03/02: Re: Spice simulation of IBIS details - model examples
145995: 10/03/02: Re: Tabula. (FPGA start up)
146000: 10/03/02: Re: Tabula. (FPGA start up)
146042: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
146044: 10/03/04: Re: Actel is now the only FPGA vendor with hard-core processor in the
146052: 10/03/04: Re: Actel is now the only FPGA vendor with hard-core processor in the
146058: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
146059: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
146063: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
146067: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
146068: 10/03/04: Re: Tabula. (FPGA start up)
146075: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
146118: 10/03/05: Re: Actel is now the only FPGA vendor with hard-core processor in the
146137: 10/03/06: Re: FSM in BlockRAM
146146: 10/03/06: Re: FSM in BlockRAM
146206: 10/03/08: Re: Tabula. (FPGA start up)
146275: 10/03/10: Re: Tier Logic introduces the world's first 3D FPGA
146277: 10/03/10: Re: Tier Logic introduces the world's first 3D FPGA
146281: 10/03/10: Re: Tier Logic introduces the world's first 3D FPGA
146286: 10/03/10: Re: Tier Logic introduces the world's first 3D FPGA
146293: 10/03/10: Re: Why doesn't this situation generate a latch?
146313: 10/03/11: Re: Tier Logic introduces the world's first 3D FPGA
146320: 10/03/11: Re: Tier Logic introduces the world's first 3D FPGA
146321: 10/03/11: Re: Tier Logic introduces the world's first 3D FPGA
146364: 10/03/14: Re: Tier Logic introduces the world's first 3D FPGA
146431: 10/03/17: Re: Xilinx Spartan6 Virtex6 Rollout
146437: 10/03/18: Re: Tabula. (FPGA start up)
146457: 10/03/18: Re: Xilinx Spartan6 Virtex6 Rollout
146461: 10/03/18: Re: Xilinx Spartan6 Virtex6 Rollout
146463: 10/03/18: Re: Xilinx Spartan6 Virtex6 Rollout
146647: 10/03/24: Re: Ring Oscillator -> counter differences
146729: 10/03/26: Re: Ring Oscillator -> counter differences
146730: 10/03/26: Re: PCB routing issues for sync SRAM
146742: 10/03/26: Re: Ring Oscillator -> counter differences
146743: 10/03/26: Re: Multipliers in CoolRunner Series?
146758: 10/03/27: Re: Multipliers in CoolRunner Series?
146873: 10/03/30: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
146897: 10/03/31: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
147035: 10/04/10: Re: I'd rather switch than fight!
147231: 10/04/19: Re: Need to run old 8051 firmware
147293: 10/04/22: Re: Polmaddie Family CPLD and FPGA Teaching Boards
147294: 10/04/22: Re: Polmaddie Family CPLD and FPGA Teaching Boards
147365: 10/04/23: Re: Need to run old 8051 firmware
147377: 10/04/24: Re: voltage divider calcs
147525: 10/04/29: Re: xilinx arm finally announced
147554: 10/05/01: Re: Cheap FPGAs for tutorial
147713: 10/05/18: Re: New 'standard' compact programming header needed!
147731: 10/05/19: Re: New 'standard' compact programming header needed!
147887: 10/05/29: Re: Last Xilinx Webpack that was big-brother free?
147910: 10/06/01: Re: Anyone else need bigger parts in small (low pin count) packages
147923: 10/06/02: Re: Anyone else need bigger parts in small (low pin count) packages
147929: 10/06/02: Re: Anyone else need bigger parts in small (low pin count) packages
147948: 10/06/03: Re: Anyone else need bigger parts in small (low pin count) packages
147954: 10/06/03: Re: Anyone else need bigger parts in small (low pin count) packages
147958: 10/06/04: Re: Anyone else need bigger parts in small (low pin count) packages
148052: 10/06/16: Re: How to detect a sync and start of a frame in an optimal way
148167: 10/06/24: Re: Please suggest NON Volatile FPGA Devices
148496: 10/07/27: Re: All Digital PLL
148734: 10/08/18: Re: CPLD development board with 8-bit wide Flash/EEProm
148909: 10/09/09: Re: PSOC3/5
148911: 10/09/09: Re: Want to get into FPGA
148915: 10/09/09: Re: PSOC3/5
149668: 10/11/15: Re: Cypres PSoC devices - hdl entry for digital sections?
149670: 10/11/15: Re: Maximum speed SPI on Spartan3a?
150835: 11/02/15: Re: why an FSM is not a counter?!
150836: 11/02/15: Re: lattice machXO2 VCCP pin
jg:
153920: 12/06/29: Re: Replacement for XC4005E
154306: 12/09/25: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
154429: 12/10/28: Re: Using LVDS Input for Delta Sigma ADC
154433: 12/10/29: Re: Using LVDS Input for Delta Sigma ADC
154440: 12/11/02: Re: production life of Spartan3A ?
154791: 13/01/10: Re: Lattice iCECube2 for iCE40 Devices
154901: 13/02/10: Re: Idea Hunt, FPGA + ARM Cortex-M3
154977: 13/03/07: Re: EPROM programmer erase
155149: 13/04/30: Re: Low cost and/or small size CPU in an FPGA
155570: 13/07/22: Re: Xilinx "Ultrascale" announcement leaves out low-cost devices
155571: 13/07/22: Re: Xilinx "Ultrascale" announcement leaves out low-cost devices
155704: 13/08/11: Re: Lattice Announces EOL for XP and EC/P Product Lines
155731: 13/08/23: Re: Lattice Announces EOL for XP and EC/P Product Lines
155747: 13/08/26: Re: Lattice Announces EOL for XP and EC/P Product Lines
155748: 13/08/26: Re: Lattice Announces EOL for XP and EC/P Product Lines
155749: 13/08/26: Re: Lattice Announces EOL for XP and EC/P Product Lines
155765: 13/08/29: Re: Lattice Announces EOL for XP and EC/P Product Lines
155813: 13/09/18: Re: Legal Issues Reproducing Old CPU
155826: 13/09/24: Re: Legal Issues Reproducing Old CPU
155845: 13/09/29: Re: Lattice diamond / MachXO2
156145: 13/12/12: Re: MachXO breakout board as a programmer
156746: 14/06/14: Re: 22V10 programmer
jg.campbell:
20983: 00/03/02: Re: Bit Serial Arithmetic De-mystified
<jgais@ws.estec.esa.nl>:
18204: 99/10/07: Free SPARC VHDL model available
25112: 00/08/26: Vacancy at European Space Agency
jgarrigo:
22922: 00/06/02: RE: Help with Coregen
<jgbreezer@gmail.com>:
156897: 14/07/24: Re: Chisel as alternative HDL
jgjhg ghjg:
16967: 99/06/21: XILINX PROG-PIN unconnected?
jgk2004:
152060: 11/06/29: Virtex 5 Rocket IO design for reading in ADC data.
152067: 11/06/30: Re: Virtex 5 Rocket IO design for reading in ADC data.
152069: 11/06/30: Re: Virtex 5 Rocket IO design for reading in ADC data.
152071: 11/06/30: Re: Virtex 5 Rocket IO design for reading in ADC data.
152075: 11/06/30: Re: Virtex 5 Rocket IO design for reading in ADC data.
jgknowla1:
84060: 05/05/11: Minimum circuit to get Spartan-3 running
84084: 05/05/12: Re: Minimum circuit to get Spartan-3 running
jgraham:
58959: 03/08/05: retiming with Synplify Pro
jhamz:
133445: 08/06/29: I-map Websolution...turning possibility into reality...
<jhirbawi@yahoo.com>:
10663: 98/06/09: Re: Multipliers on FPGA's
11037: 98/07/14: Re: Howto: CRC's and PRBS in Parallel
11086: 98/07/18: Re: Shift Invarient Bit Transform
11110: 98/07/20: Re: Shift Invarient Bit Transform
15384: 99/03/22: Re: Bit Error Rate Test
18084: 99/09/28: Re: Altera 20KE LVDS IO
19724: 00/01/10: Re: Decoding RSPC (Reed Solomon Product Code)
JHL:
39937: 02/02/22: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
39999: 02/02/24: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
Jhlw:
110874: 06/10/24: Bit order reversed in Xilinx post-translate simulation
110989: 06/10/26: Re: Bit order reversed in Xilinx post-translate simulation
111507: 06/11/03: Cleaning generated files in Xilinx 8.2 EDK and ISE
111524: 06/11/04: Re: Cleaning generated files in Xilinx 8.2 EDK and ISE
111549: 06/11/05: Re: Cleaning generated files in Xilinx 8.2 EDK and ISE
111974: 06/11/13: Running an application from external memory in Xilinx
112057: 06/11/15: Getting Xilinx DMA SG working with peripheral
114496: 07/01/17: Re: running applications from external memory
114503: 07/01/17: Re: running applications from external memory
114537: 07/01/18: Re: running applications from external memory
114538: 07/01/18: Re: running applications from external memory
<jhmccaskill@gmail.com>:
116398: 07/03/08: Re: Introducing picosecond delay between two output signals
Jhoberg:
116693: 07/03/15: Verilog DSP Examples (FFT With 32K-Point Transform Length, FIR, IIR, Discrete Cosine Transform (DCT), Convolution 2D)
116801: 07/03/18: ADC capture with FPGA Spartan3 in Verilg
118222: 07/04/19: Free Hardware
118259: 07/04/20: Re: Free Hardware
118312: 07/04/23: Re: Free Hardware
118314: 07/04/23: free architecture
118325: 07/04/23: Re: free architecture
jholley:
88118: 05/08/09: Re: Hiding data inside a FPGA
<Jhon12@hotmail.com>:
30795: 01/04/29: Speedup games, programs and get more FREE RAM
<jhon@geocities.com>:
8558: 98/01/08: Parallel port interface
<jhouse@btmd.com>:
105042: 06/07/12: Can't get my Verilog Peripheral to import into XPS! Any tricks?
105070: 06/07/12: Re: Can't get my Verilog Peripheral to import into XPS! Any tricks?
105089: 06/07/13: Re: Can't get my Verilog Peripheral to import into XPS! Any tricks?
jhuebner:
57756: 03/07/05: Re: PC-104 dev Boards
Ji Soon Kim:
120603: 07/06/11: Help with T-VPACK
Jialin:
111651: 06/11/07: How to send data/program to the memory of a Spartan 3 starter kit board
111713: 06/11/08: Re: How to send data/program to the memory of a Spartan 3 starter kit board
111714: 06/11/08: Re: How to send data/program to the memory of a Spartan 3 starter kit board
Jian F. Weng:
22897: 00/05/30: Implement LMS
22898: 00/05/30: Implement LMS
Jian Ju:
53773: 03/03/22: how to implement the bidir in Altera AHDL?
63631: 03/11/27: overshoot problem of EPM7128S
Jian Liang:
66827: 04/02/26: Question: size of Stratix??
Jian Lin:
24280: 00/08/02: Category : Subject
Jian Shen:
5957: 97/03/31: clock edge specification for Synopsys synthesis
Jian_Zhang:
9285: 98/03/05: Using Java for PLI?
9301: 98/03/05: Re: Using Java for PLI?
Jiang:
62912: 03/11/11: Are modules that are not floorplanned still functional?
62995: 03/11/12: Re: Are modules that are not floorplanned still functional?
jianghongtu@hotmail.com:
52051: 03/01/29: problem with JTAG downloading
jianhuawow:
152226: 11/07/24: About the setup time of BUFGMUX in Spartan6
Jianrong Wang:
46478: 02/08/31: A little question
Jianyong Niu:
27474: 00/11/23: survey of fpga application
27930: 00/12/15: kalman filter
45068: 02/07/11: Need a non-pipelined signed integer divider
46301: 02/08/25: Re: I2C BUS
46933: 02/09/12: Re: symplicity conv_integer problem
55276: 03/05/02: Re: IP Core for CAN communication
66481: 04/02/20: Power supply for the Xilinx Virtex Pro FF1152 Proto Board
70291: 04/06/11: Re: Xilinx System Generator
JianYong Niu:
28873: 01/01/26: what is the best FPGA development toolkit?
29099: 01/02/06: Xilinx Implementation Error! need help urgently
29113: 01/02/06: Re: Handel-C language.
30519: 01/04/12: *help* how to count clock cycles in a design? how can i know its maximum clock frequency?
32420: 01/06/26: Xilinx System Generator Simulation Problem
32535: 01/06/29: Re: Xilinx System Generator Simulation Problem
32536: 01/06/29: Error to execute vcom.do in ModelSim XE5.3d
33097: 01/07/17: Xilinx System Generator V1.0 question
33138: 01/07/18: Re: Project implementation
36471: 01/11/09: How to convert unsigned integer into std_logic_vector in VHDL design?
36560: 01/11/12: fixed-point number convert
36801: 01/11/20: Implementation problem with the codes generated from Xilinx System Generator
37516: 01/12/13: FPGA development board
JianyongNiu:
28806: 01/01/24: can not start coregen
28807: 01/01/24: Re: can not start coregen
28855: 01/01/26: Re: can not start coregen
46077: 02/08/16: Re: Divider in Xilinx System Generator
jicho:
64299: 03/12/26: LVPECL_33 to LVPECL_25 (virtex-II pro)
<jidan1@hotmail.com>:
106703: 06/08/17: Why is Spartan-3 more expensive than Cyclone?
107675: 06/08/30: Bypass Caps : XAPP623 vs Spartan-3 Starter Kit Board
108507: 06/09/12: Spartan-3: 5V -> 2.5V level shifting
108536: 06/09/12: Re: Spartan-3: 5V -> 2.5V level shifting
108593: 06/09/13: Re: Spartan-3: 5V -> 2.5V level shifting
108629: 06/09/14: Re: Spartan-3: 5V -> 2.5V level shifting
117207: 07/03/26: Minimal pins for JTAG configuration
117212: 07/03/26: Re: Minimal pins for JTAG configuration
117258: 07/03/27: Re: Minimal pins for JTAG configuration
117324: 07/03/28: Problems with Xilinx Parallel III Cable
117325: 07/03/28: Re: Minimal pins for JTAG configuration
117329: 07/03/28: Re: Problems with Xilinx Parallel III Cable
117332: 07/03/28: Re: Problems with Xilinx Parallel III Cable
117337: 07/03/28: Re: Problems with Xilinx Parallel III Cable
117338: 07/03/28: Re: Problems with Xilinx Parallel III Cable
117342: 07/03/28: Re: Problems with Xilinx Parallel III Cable
117346: 07/03/28: Re: Problems with Xilinx Parallel III Cable
117364: 07/03/29: Re: Problems with Xilinx Parallel III Cable
117365: 07/03/29: Re: Problems with Xilinx Parallel III Cable
117377: 07/03/29: Re: Problems with Xilinx Parallel III Cable
120205: 07/06/03: Microcontrollers have a better predictable time behaviour than FPGAs
120251: 07/06/04: Re: Microcontrollers have a better predictable time behaviour than FPGAs
125893: 07/11/08: Maximum current drive according to datasheet ?!
125897: 07/11/08: Re: Maximum current drive according to datasheet ?!
125930: 07/11/08: Re: Maximum current drive according to datasheet ?!
132464: 08/05/28: JTAG + PROM error!
132673: 08/06/05: Re: JTAG + PROM error!
132771: 08/06/06: Re: JTAG + PROM error!
132777: 08/06/06: Re: JTAG + PROM error!
132778: 08/06/06: Re: JTAG + PROM error!
<jigarmori@gmail.com>:
156386: 14/03/26: Re: Initializing color bars on CH7301
Jihan Zhu:
54449: 03/04/11: Dynamic Reconfigurable FPGAs
Jihoon:
92827: 05/12/07: Re: ML402 DDR SDRAM
92828: 05/12/07: Re: ML402 DDR SDRAM
Jila Nazari:
28207: 00/12/29: selecting tools a newbi question.
Jim:
4814: 96/12/17: How to get MORE ORDERS for ANYTHING you SELL!!!
14910: 99/02/24: JTAG HANG UP......
14937: 99/02/25: Re: JTAG HANG UP......
15006: 99/03/02: VECTORS FROM MEMEORY STRUCTURE
15150: 99/03/09: Re: Startup issues with 24c04 eeprom and I2C interface
15173: 99/03/10: Re: Startup issues with 24c04 eeprom and I2C interface
23252: 00/06/19: Does anyone know of a PC Card macro for Xilinx Spartan series?
35971: 01/10/25: Re: memory dump for Xilinx block ram
36235: 01/11/02: Re: XC6000
36236: 01/11/02: Re: JTAG problem
36351: 01/11/07: Re: Encoder timin question
36521: 01/11/10: Re: Can Xilinx recognize the critical path in the design
36532: 01/11/11: Re: Reconfigrable Routers
36599: 01/11/13: Re: Incrementing counter from state-machine
36698: 01/11/16: Re: jtag programming xilinx cpld
36744: 01/11/19: Re: jtag programming xilinx xc9572 cpld
44435: 02/06/20: Help!I can't use the programmer of Max-plus II on windows XP.
44619: 02/06/25: Re: Help!I can't use the programmer of Max-plus II on windows XP.
47259: 02/09/21: Re: Cheap development package for beginner?
52613: 03/02/16: Re: Help wanted on Installing Xilinx on Win NT
52773: 03/02/21: Re: Modelsim warnings about Spartan2 Block RAM read/write
52945: 03/02/26: Xilinx Coolrunner-II Dev Kit
52972: 03/02/27: Re: Xilinx Coolrunner-II Dev Kit
59210: 03/08/12: Re: Webpack sees 2 clocks when there is only one
66684: 04/02/25: Basic jitter from a CPLD (XC7500XL)
66697: 04/02/25: Re: Basic jitter from a CPLD (XC7500XL)
66701: 04/02/25: Re: Basic jitter from a CPLD (XC7500XL)
66702: 04/02/25: Re: Basic jitter from a CPLD (XC7500XL)
66709: 04/02/25: Re: Basic jitter from a CPLD (XC7500XL)
66753: 04/02/26: Re: Basic jitter from a CPLD (XC7500XL)
66800: 04/02/26: Re: Basic jitter from a CPLD (XC7500XL)
66834: 04/02/27: Re: Basic jitter from a CPLD (XC7500XL)
67409: 04/03/11: Re: Answering Machine RAM
67584: 04/03/15: Programmed ground pins v physical grounding (Xilinx CPLD)
69240: 04/05/02: frequency multiplication
70707: 04/06/24: DPLL in CPLD
70753: 04/06/26: Re: DPLL in CPLD
75801: 04/11/15: Help with Virtex II and 5v TTL
75811: 04/11/15: Re: Help with Virtex II and 5v TTL
103051: 06/05/25: ISE sends sensitive information to Xilinx site!
103211: 06/05/28: Specifying a non connected port
103356: 06/05/31: Using part of CPLD to Invert Own Clock
103412: 06/06/01: Using version control for Xilinx 8.1i ISE projects and source files
103434: 06/06/01: Re: Using part of CPLD to Invert Own Clock
103444: 06/06/01: Re: Using version control for Xilinx 8.1i ISE projects and source files
103475: 06/06/03: Re: FPGA board for USB experiments?
109277: 06/09/22: Re: Altera configuring/programming for FLEX10KE with EPC2 - sof or pof?
143220: 09/09/26: Re: ChipScope Pro, storing stimuli in ILA core
143223: 09/09/27: Re: ChipScope Pro, storing stimuli in ILA core
143262: 09/09/28: Re: ChipScope Pro, storing stimuli in ILA core
143371: 09/10/07: Re: Virtx 4 and FPGA programming
143480: 09/10/12: Re: integrating chipscope pro in EDK
152584: 11/09/15: clock enable for fixed interval
152597: 11/09/16: Re: clock enable for fixed interval
153265: 12/01/21: clock enable question
153268: 12/01/22: Re: clock enable question
jim:
29538: 01/02/25: answer
77694: 05/01/14: Configuring FPGA with AT91 (GNUarm settings)
113173: 06/12/07: testbench help
115936: 07/02/26: Virtex 4, how do I generate 100khz clock
Jim Antone:
49340: 02/11/10: PCI core
Jim Banks:
1291: 95/05/29: Design debug with Xilinx extra fine pitch parts
3102: 96/04/02: Re: XACT5.2 bit file length count changes
3095: 96/04/01: XACT5.2 bit file length count changes
Jim Bittman:
36572: 01/11/12: Re: Virtex 2 parts shipping = receiving
36574: 01/11/12: Xilinx s/w upgrade 4.1 problems
36635: 01/11/13: Re: Xilinx s/w upgrade 4.1 problems
36654: 01/11/14: Re: Xilinx s/w upgrade 4.1 problems
Jim Bock:
1605: 95/07/26: Lattice:pds+/Viewlogic Comments please
1784: 95/09/01: Re: VHDL Savy editors under UNIX?
Jim Brain:
76835: 04/12/14: Need help with CUPL
76983: 04/12/18: Re: Need help with CUPL
Jim Burnham:
8490: 97/12/22: Better Digital library for Visio 4
Jim Burns:
4375: 96/10/22: Re: Xilinx xchecker.exe and Windows NT
Jim Carlock:
69363: 04/05/07: Re: How to remove an unintended Right-click menu?
Jim Chase:
7283: 97/08/21: Re: Unbonded Pad Resources
7629: 97/09/29: FS Advin Pilot U84 Universal Programmer
7630: 97/09/29: FS Corelis PCI Probe Card
Jim Cohoon:
5031: 97/01/14: Design Automation Conference Scholarships
Jim Drew:
2719: 96/01/29: Re: GAL programming for hobby use...Is there no hope?
2740: 96/01/31: Re: GAL programming for hobby use...Is there no hope?
2741: 96/01/31: Re: GAL programming for hobby use...Is there no hope?
2745: 96/02/01: Re: GAL programming for hobby use...Is there no hope?
2758: 96/02/02: Re: GAL programming for hobby use...Is there no hope?
Jim E:
34555: 01/08/29: Re: Urgent Help Needed
34599: 01/08/30: Re: Urgent Help Needed
34600: 01/08/30: Re: Urgent Help Needed
Jim English:
61492: 03/10/05: Re: Spartan 2e implementation
Jim Flanagan:
58195: 03/07/16: Altera ByteBlaster Standalone Programming Utility
132934: 08/06/10: Dram Refresh Controller Tutorial wanted
133030: 08/06/14: Old Mits Dram Datasheet Search
133430: 08/06/28: Missing the simplest things - Active HDL - Beginners Questions
136335: 08/11/11: CPLD newbie questions
Jim Frenzel:
159: 94/09/02: Xilinx and 8.4 -- not!
176: 94/09/09: Re: Xilinx and 8.4 -- not!
515: 94/12/16: Industry FPGA Applications?
1132: 95/05/03: Re: Web/FTP site for FPGA based research
10727: 98/06/12: XC6000 VHDL models?
17445: 99/07/28: Partial Reconfiguration?
Jim George:
64145: 03/12/18: FIR Filter cores for Virtex-][
64177: 03/12/18: Re: FIR Filter cores for Virtex-][
64236: 03/12/21: Re: FIR Filter cores for Virtex-][
76797: 04/12/12: LUT and MUXF5 placement
76799: 04/12/12: Re: PLLs on biphase mark signals
76803: 04/12/12: Re: LUT and MUXF5 placement
76822: 04/12/13: Re: LUT and MUXF5 placement
77126: 04/12/23: Re: Using low-core-voltage devices in industrial applications
78498: 05/02/01: Virtex II Slice Design - ARGH!
78537: 05/02/02: Re: Virtex II Slice Design - ARGH!
80162: 05/03/02: Suppressing extra XST messages
80164: 05/03/02: Timing Error large enough to cause problems?
80165: 05/03/02: Re: Xilinx ISE7.1
80191: 05/03/02: Re: Xilinx ISE7.1
80193: 05/03/02: Re: PLL code
80755: 05/03/10: Re: RPM creation
80756: 05/03/10: Re: FIR Filter On FPGA
80757: 05/03/10: Re: low speed FIR filter in FPGA
80887: 05/03/13: Re: Xilinx ISE and IP cores
81950: 05/04/05: Re: ISE
81951: 05/04/05: Re: IBUFG and BUFG +xilinx
81953: 05/04/05: Re: Stupid question
82030: 05/04/05: Re: IBUFG and BUFG +xilinx
82180: 05/04/07: Linux VHDL Simulator
82822: 05/04/18: Re: LUT in fpga
83236: 05/04/26: ISE wishlist
83280: 05/04/26: Re: ISE wishlist
83403: 05/04/29: Map Error: "RLOC not supported for simple gates"
83454: 05/04/29: Re: Map Error: "RLOC not supported for simple gates"
83739: 05/05/05: Re: including components, i.e. SRL16
84597: 05/05/22: GHDL under x86_64 Linux
84778: 05/05/26: Async FIFO coregen wizard
84911: 05/05/31: Re: Magical Mystery Tour of ISE environment variables
84912: 05/05/31: Re: JTAG Programming Problem
85583: 05/06/11: Re: computer upgrade time.
86039: 05/06/20: Re: Xilinx MacFir5.0 - Block Ram requirenments
86278: 05/06/24: Re: DC Offset removal in FPGA
86279: 05/06/24: Re: using GUI and batch mode produces different results !
jim granville:
5059: 97/01/17: Re: ANNOUNCE 8051/8052 microcontroller model now available for FPGA
5060: 97/01/17: Re: Any PEEL22CV10A replacements with more capacity?
5256: 97/02/01: Re: Steven K. Knapp - no such article
5327: 97/02/07: Re: FPGA power dissipation
5791: 97/03/14: Re: Galileo... Leonardo... Renoir... ?
6092: 97/04/11: Re: Sole source
5992: 97/04/02: Re: New Technology
5999: 97/04/03: Re: 8051 core for XC40xx
7181: 97/08/11: Re: Price of Serial EPROM is Outrageous - Better Explanation
7245: 97/08/18: Re: Price of Serial EEPROM is Outrageous
7259: 97/08/19: Re: ISP Stories
7267: 97/08/19: Re: Price of Serial EEPROM is Outrageous
7270: 97/08/20: Re: 89c2051 Price & Capability (was Ourtageous Serial EEPROM $$)
7276: 97/08/20: Re: ISP Stories
7451: 97/09/11: SYNC RAM in XCilinx/Altera...
7491: 97/09/16: Re: Choosing a good pin assignment for multiple-xilinx prototype.
7509: 97/09/18: Re: 6809 discontinued
7540: 97/09/19: Re: Atmel 17256 serial config EEPROMs
7601: 97/09/25: HEX format prom files wanted
7899: 97/10/28: Re: Counter Problem
8185: 97/11/26: Re: Need Digital PLL in a Flex 10
8292: 97/12/06: Re: A suggestion for Xilinx
8486: 97/12/22: Re: Schmitt Trigger on ISP
8813: 98/01/28: Re: Opinions wanted on PLD selection
9023: 98/02/15: Re: Altera 5032 programming problems
9035: 98/02/17: Re: Why some CPLDS are slow to power-up?
9037: 98/02/17: Re: Why altera CPLDS are slow to power-up?
9162: 98/02/26: Re: Altera CPLD power-up procedure?
9668: 98/03/30: Re: USB bus interface (12 mbit/sec) in an FPGA - how difficult?
9704: 98/04/01: Re: Digital PLL's or Manual Synching?
10136: 98/04/29: Re: How to implement a UART use FPGA with less cells.
10364: 98/05/15: Re: vga gen
10402: 98/05/16: Re: vga gen
10844: 98/06/25: Re: Q: I squared C on an FPGA
11202: 98/07/25: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11385: 98/08/09: Re: Radiation and Relaibility
11680: 98/08/31: Re: A Johnson counter
12080: 98/09/28: Re: A Johnson counter
12128: 98/10/01: Re: Simple programmable device suggestions please?
12416: 98/10/12: Re: Need 100MHz Counter with 3 Comparators
12450: 98/10/13: Re: Digital Sine Generator
12451: 98/10/13: Re: Processor Cores
13715: 98/12/20: Re: Fast *Industrial* 22V10?
13737: 98/12/22: Re: Atmel's PLD
13738: 98/12/22: Re: Fast *Industrial* 22V10?
13875: 98/12/31: Re: 22V10 Metastability - help please
13877: 98/12/31: Re: 22V10 Metastability - help please
14354: 99/01/27: Re: Hysteresis on PLD Clock Inputs
14359: 99/01/27: Re: Hysteresis on ALL PLD Inputs
17149: 99/07/04: Re: FW: Xilinx Acquisition of CoolRunners
17747: 99/08/30: Re: Smallest Configurator for Xilinx
17748: 99/08/30: AMD Athlon CPU Speed at Simulates
18251: 99/10/10: Re: Altera 10K50V in-rush/temp problem...
19029: 99/11/25: Re: Obselete processor substitutes
19260: 99/12/09: Re: constraints between clock domains: can't advance
19620: 00/01/05: Re: Design security
19689: 00/01/08: Re: Design security
19713: 00/01/09: Re: Design security
20778: 00/02/22: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
20848: 00/02/24: Re: IEC 1131-3 i NEED HELP
64313: 03/12/28: Re: [Spartan-IIE] Exeeding max. input rise/fall time of signals ??
64319: 03/12/28: Re: [Spartan-IIE] Exeeding max. input rise/fall time of signals ??
64614: 04/01/09: Re: spartan 3 sample
64615: 04/01/09: Re: Anybody know what the REAL story is? Play it again? Sam? Oh
64647: 04/01/10: Re: min propagation delay in xilinx cpld
64648: 04/01/10: Re: Large/Fast static RAM
64817: 04/01/15: Re: ASMBL - hmmm ---- hmmmm -- Wow? -- "Hard-tocopy" rant -- skip
64818: 04/01/15: Re: translating .jed files to equations
64847: 04/01/15: Re: Altera Cyclone data is incomplete or messy
64848: 04/01/15: Re: Gray encoding for FSM
64956: 04/01/17: Re: Gray encoding for FSM
65073: 04/01/20: Re: WTD: info on AMD palce22v10
65127: 04/01/21: Re: BIST FPGA testing - Applying a test vector
65128: 04/01/21: Re: changing values in a fifo
65192: 04/01/22: Re: WTD: info on AMD palce22v10
65193: 04/01/22: Re: Soft failures (?) 9536XL
65194: 04/01/22: Re: xilinx 70% tracking rule
65301: 04/01/24: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65317: 04/01/25: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65346: 04/01/26: Re: changing values in a fifo
Jim Granville:
21047: 00/03/04: Re: New name: DLLs, PLLs and videotape...
21208: 00/03/10: Re: pal design using GAL22V10 and PROTEL
21514: 00/03/24: SPLD Usage ?
21629: 00/03/27: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
21648: 00/03/28: Re: FPGA & single point failure
22194: 00/05/01: Re: How to Prevent theft of FPGA design
22280: 00/05/04: Re: How to Prevent theft of FPGA design
22281: 00/05/04: Re: Why are there no "cheap" FPGAs?
22324: 00/05/05: Re: How to Prevent theft of FPGA design
22366: 00/05/06: Re: How to Prevent theft of FPGA design
22417: 00/05/09: Re: How to Prevent theft of FPGA design
22754: 00/05/23: Re: Xilinx tools
22883: 00/05/30: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22954: 00/06/06: Re: PLA to ABEL converter?
22973: 00/06/07: Re: 3.3V I/O TO 5V LOGIC?
22993: 00/06/08: TTL device Libraries
23012: 00/06/09: Re: TTL device Libraries
23021: 00/06/09: Re: TTL device Libraries
23123: 00/06/15: Re: PAR Times for XILINX Foundation Express Student Edition 1.5
23234: 00/06/19: Re: Problem copying text from the Spartan II data sheet
23262: 00/06/20: Re: cpld
23283: 00/06/21: Re: Problem copying text from the Spartan II data sheet
23508: 00/06/28: Re: I cant stand it any more.
23528: 00/06/29: Re: How to do ...?
23811: 00/07/11: Re: Xilinx buys LavaLogic
23817: 00/07/11: Re: phase lock different frequencies
24026: 00/07/24: Re: Q: PAL22V10 JEDEC file-toVHDL translators?
24526: 00/08/12: OPAL sw ex natsemi ?
24551: 00/08/14: Re: Virtex 2.5V part with 5V IO problems
24554: 00/08/14: Re: Virtex 2.5V part with 5V IO problems
24852: 00/08/21: Re: Metastability measurement
24863: 00/08/21: Re: Metastability measurement
24953: 00/08/23: Re: Some notes on metastability
25095: 00/08/26: Re: Why Aren't Anti-Fuse FPGAs The Biggest FPGAs In The World?
25124: 00/08/27: Re: Why Aren't Anti-Fuse FPGAs The Biggest FPGAs In The World?
25133: 00/08/27: Re: Balls!
25138: 00/08/28: Re: FPGA power pins decoupling <-> PCB autorouting
25157: 00/08/29: Re: Using a FPGA as I/O expansion on embedded PC ??
25522: 00/09/13: Re: Clock skew in XILINX CPLD
25934: 00/09/27: Re: hdl
25979: 00/09/29: Re: ABEL truth table for 8-1 Mux (The solution)
26126: 00/10/05: Re: Whoa, Noise on a digital output pin?, and Minor rant on XC9500 S/W, was Re: Simon,Floating Inputs
26044: 00/10/02: Re: Migrating PAL/TTL design to FPGA
26069: 00/10/03: Re: Synthesis failures
26315: 00/10/12: Re: palasm
26408: 00/10/15: Re: Sinusoidal PWM on Xilinx FPGA
26451: 00/10/17: Re: Low power cpld?
26582: 00/10/21: Re: CoolRunner news :(
26748: 00/10/27: Re: How safe is the algorithm implemented with FPGA?
26666: 00/10/24: Re: RS422 interfacing to a FPGA ?
26991: 00/11/07: Re: CoolRunner news :(
27610: 00/11/30: Re: Xilinx Coolrunner going on last time buy?
28126: 00/12/22: Re: really fast counter in SpartanXL?
28144: 00/12/23: Re: Virtex and metastability
28506: 01/01/16: Re: Virtex-II officially launched
28705: 01/01/22: Re: xc95108 funny behaviour
29010: 01/02/02: Re: 64-bit counter @ 200 MHz on FPGA?
29050: 01/02/04: Re: Encryption is supported in new Virtex II but.....
29127: 01/02/07: Re: Switching matrix, FPGA or CPLD? -
29263: 01/02/12: Re: any idea ?
29531: 01/02/26: Re: cpul vs vhdl
29591: 01/02/28: Re: cpul vs vhdl
30146: 01/03/26: Re: No inputs on XC9536XL
29671: 01/03/05: Re: Metastability, Asynchronous Signals, & Asynchronous design
29677: 01/03/05: Re: Metastability, Asynchronous Signals, & Asynchronous design
29710: 01/03/06: Re: Metastability, Asynchronous Signals, & Asynchronous design
29734: 01/03/07: Re: Parallel Port EPP
29851: 01/03/14: Re: 64 simultan A/D Converters in an SPARTAN-II
29859: 01/03/14: Re: 64 simultan A/D Converters in an SPARTAN-II
30086: 01/03/23: Re: frequency measurement?
30233: 01/03/29: Re: Recommended Oscillators for DLL's at 25 MHz
30320: 01/04/03: Re: pseudo random numbers
30382: 01/04/05: Re: High Speed PLA/FPGA
30411: 01/04/07: Re: Why FPGA/CPLDs draw a lot current?
30429: 01/04/08: Re: Why FPGA/CPLDs draw a lot current?
30491: 01/04/11: Re: Why FPGA/CPLDs draw a lot current?
30576: 01/04/18: Re: compression
30603: 01/04/19: Re: compression
30627: 01/04/20: Re: clocking on both edges
30656: 01/04/22: Re: WinCUPL still alive?
31299: 01/05/18: Re: interfacing:keyboard/displays
31451: 01/05/25: Re: frequency ramp
31518: 01/05/29: Re: Want to buy: Old copy of ABEL, Synario or ViewPLD
31543: 01/05/30: Re: Want to buy: Old copy of ABEL, Synario or ViewPLD
31853: 01/06/07: Re: one state machine
31899: 01/06/08: Re: Help in FIFO design
32554: 01/06/30: Re: clock speed in XC95288XL
32720: 01/07/06: Re: 8031 microcontroller on FPGA development board :-)
32721: 01/07/06: Re: XC9500 drive capability
33118: 01/07/18: Re: Working Design - Anyone
33119: 01/07/18: Re: Coolrunner: availability
33120: 01/07/18: Re: conditional expression optimization
33179: 01/07/19: Re: Working Design - Anyone
33531: 01/07/30: Re: finite defect statistics
33614: 01/08/01: Re: finite defect statistics
34003: 01/08/11: Re: Low Cost FPGA or PLD
34051: 01/08/13: Re: FPGA or CPLD data compression
34124: 01/08/15: Re: Building a clock out of a PLD
34139: 01/08/15: Re: Building a clock out of a PLD
34170: 01/08/16: Re: Building a clock out of a PLD
34253: 01/08/18: Re: Atmel CPLD - JEDEC to ABEL
34286: 01/08/19: Re: Atmel CPLD - JEDEC to ABEL
34338: 01/08/22: Re: protecting pins on xilinx xc95 cpld
34524: 01/08/29: Re: FPGA : USB in an FPGA, has anyone done it before?
34547: 01/08/29: Re: Version Control
34572: 01/08/30: Re: Version Control
34721: 01/09/05: Re: Clock Multiplication
34884: 01/09/13: Re: Programming Delays in ABEL
34917: 01/09/14: Re: configuration latency for PCI bridge in FPGA
35090: 01/09/21: Re: Maximum clock rate of various Xilinx families?
35095: 01/09/21: Re: Maximum clock rate of various Xilinx families?
35146: 01/09/24: Re: Clockin on rising AND falling edge
35506: 01/10/09: Re: ROM based FSMs
35567: 01/10/11: Re: Synplicity/Leonardo License Agreement Information
35674: 01/10/13: Re: Lattice discontinues all smaller MACH circuits and other devices
35766: 01/10/17: Re: LUT Glitches
35793: 01/10/18: Re: Recommended Newsgroup
35914: 01/10/24: Re: Are there any Coolrunner P5Z22V10 (PLCC) devices left anywhere?
35957: 01/10/25: Re: CPLD with built-in oscillator?
36001: 01/10/26: Re: GAL compiler
36002: 01/10/26: Re: GAL compiler
36378: 01/11/08: Re: Quadrature Encoder Sampling Time
36510: 01/11/10: Re: 18V8Z and Philips SNAP compiler
36542: 01/11/12: Re: Quadrature Encoder Sampling Time
36676: 01/11/15: Re: High Speed PWM?
36973: 01/11/28: Re: Creating a jitter free clock
37021: 01/11/29: Re: Creating a jitter free clock
37040: 01/11/29: Re: maximum output current on Spartan2
37051: 01/11/29: Re: maximum output current on Spartan2
37105: 01/11/30: Re: FPGA startup current
37464: 01/12/12: Re: ISP by JTAG using a microcontroller
37504: 01/12/13: Re: Initialization of RAM
37653: 01/12/19: Re: ISP by JTAG using a microcontroller
37807: 01/12/21: Re: Best-case timing?
37823: 01/12/21: Re: annoying problem and "simple and clever solution"
38121: 02/01/06: Re: Suitability of Atmel for project?
38131: 02/01/07: Re: Suitability of Atmel for project?
38162: 02/01/08: Re: Suitability of Atmel for project?
38296: 02/01/11: Re: EXPAL language ?
38397: 02/01/14: Re: Homebrew computers using FPGA?
38603: 02/01/19: Re: Audio time delay circuit
38955: 02/01/29: Re: FPGA or Micro-controller in Lowpower designs?
38957: 02/01/29: Re: Xilinx webpack
38960: 02/01/29: Re: Xilinx webpack
38963: 02/01/29: Soft errors climb in 0,13u SRAM
39001: 02/01/30: Re: The LUT puzzle, Iam on the way
39054: 02/01/31: Re: FPGA or Micro-controller in Lowpower designs?
39065: 02/01/31: Re: The LUT puzzle, Iam on the way
39168: 02/02/03: Re: LARGE ultra low power FPGA/CPLD recommendation
39230: 02/02/05: Re: Destroying a CPLD by JTAG
39231: 02/02/05: Re: Destroying a CPLD by JTAG
39244: 02/02/05: Re: FPGA or Micro-controller in Lowpower designs?
39245: 02/02/05: Re: LARGE ultra low power FPGA/CPLD recommendation
39306: 02/02/06: Re: Programming Altera PGAs.
39458: 02/02/11: Re: Multiple clock domein synchronization.
39585: 02/02/14: Re: Atmel CPLD chip design software?
39624: 02/02/15: Re: Lean serial communication processor
39790: 02/02/20: Re: Few pins but more gates
39905: 02/02/22: Re: Need largest CPLD devices?
39910: 02/02/22: Re: Coolrunner and ISP
39964: 02/02/23: Re: Coolrunner and ISP
39986: 02/02/23: Re: Coolrunner and ISP
39998: 02/02/24: Re: Coolrunner and ISP
40107: 02/02/28: Re: PAL to JEDEC convertor
40204: 02/03/02: Re: Beginner Altera Questions
40257: 02/03/04: Re: max3000a odd behavior -- is the bug in my vhdl code? help!
40287: 02/03/05: Re: max3000a odd behavior -- is the bug in my vhdl code? help!
40345: 02/03/06: Re: digital video PLL
40413: 02/03/07: Re: FPGA or DSP in a power supply?
40432: 02/03/07: Re: high active and low active reset signal mixed in a design
40437: 02/03/07: Re: FPGA or DSP in a power supply?
40493: 02/03/08: Re: Converting old Mach 5 project from DSL to VHDL
40587: 02/03/12: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40635: 02/03/12: Re: Mystery two wire interface, or am I being dense?
40761: 02/03/15: Re: Newbie choosing a language - Verilog, VHDL, or ABEL/CUPL
41109: 02/03/21: Re: FPGA or Micro-controller in Lowpower designs?
41219: 02/03/23: Re: Poor availability problems on Coolrunner
41236: 02/03/23: Re: Poor availability problems on Coolrunner
41373: 02/03/27: Re: Help with Xilinx CoolRunner Problem
41374: 02/03/27: Re: clock multiplier
41416: 02/03/28: Re: I2C complexity
41627: 02/04/04: Re: powerpc in virtex2pro
41677: 02/04/05: Re: hand placement
41725: 02/04/06: Re: Help: Design a crystal oscillator in a Xilinx XCR3256XL
41736: 02/04/06: Re: 32 bit accumulator/comparator PWM?
41773: 02/04/08: Re: 32 bit accumulator/comparator PWM?
41777: 02/04/08: Re: 32 bit accumulator/comparator PWM?
41814: 02/04/09: Re: 32 bit accumulator/comparator PWM?
42062: 02/04/15: Re: FPGA config without boot PROM???
42144: 02/04/17: Re: Synario v2.3
42231: 02/04/19: Re: 8051 Core for Motor Electronics
42476: 02/04/25: Re: Using PAL/GAL/FPGA to replace CPU's (correct news group?)
42507: 02/04/26: Re: Using PAL/GAL/FPGA to replace CPU's (correct news group?)
42517: 02/04/26: Re: Xilinx Easypath- Selling parts with known defects
42546: 02/04/27: Re: 8051 Core for Motor Electronics
42573: 02/04/28: Re: SpartanII design considerations...
42577: 02/04/28: Re: SpartanII design considerations...
42672: 02/05/01: Re: Xilinx Easypath- Selling parts with known defects
42674: 02/05/01: Re: power supply sequencer for Virtex II
42681: 02/05/01: Re: power supply sequencer for Virtex II
42682: 02/05/01: Re: Xilinx Easypath- Selling parts with known defects
42794: 02/05/03: Re: simultaneous switching of LVPECL outputs
42795: 02/05/03: Re: Frequency synthesiser
42797: 02/05/03: Re: simultaneous switching of LVPECL outputs
42868: 02/05/06: Re: Frequency synthesiser
42911: 02/05/07: Re: max 7000
42988: 02/05/09: Re: OP-AMP in FPGA
42996: 02/05/09: Re: More C things
43053: 02/05/11: Re: altera 7000's
43088: 02/05/14: Re: Architecture for high-level reconfigurable computing
43100: 02/05/14: Re: Architecture for high-level reconfigurable computing
43147: 02/05/15: Re: Architecture for high-level reconfigurable computing
43154: 02/05/15: Re: Architecture for high-level reconfigurable computing
43161: 02/05/15: Re: Frequency synthesiser
43187: 02/05/16: Re: Architecture for high-level reconfigurable computing
43287: 02/05/18: Re: Building a relaxation oscillator with a Xilinx 9536XL
43320: 02/05/19: Re: HardPath
43383: 02/05/21: Re: Using Impact with XCR5064 coolrunner?
43394: 02/05/21: Re: Spartan2 on a Compact Flash card
43408: 02/05/21: Re: fpga cpu
43463: 02/05/22: Re: What properties has FPGA?
43467: 02/05/22: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
43484: 02/05/22: Re: What properties has FPGA?
43653: 02/05/29: Re: Frequency synthesiser
43661: 02/05/29: Re: Frequency synthesiser
43779: 02/06/03: Re: Clock double trigger problem
43825: 02/06/04: Re: divide by 5
44011: 02/06/10: Re: Do you know a e-mail list where I can make questions about Handel-C?
44092: 02/06/12: Re: fpga and ultra highspeed counters
44112: 02/06/12: Re: Searching for high performance PLD
44162: 02/06/13: Re: Searching for high performance PLD
44204: 02/06/14: Re: Power supply caps on PCB
44213: 02/06/14: Re: Power supply caps on PCB
44324: 02/06/18: Re: Internal oscillator in CPLD?
44337: 02/06/18: Re: Seeking CPLD/FPGA recomendation
44378: 02/06/19: Re: Seeking CPLD/FPGA recomendation
44428: 02/06/20: Re: ATMEL CPLD
44520: 02/06/22: Re: Logic Minimization in Max+Plus II compiler
44545: 02/06/23: Re: Xilinx's 4.1i's Lastest webpack
44575: 02/06/24: Re: [Newbie] Help with 20L8 PAL
44679: 02/06/27: Re: 5V tolerance
44705: 02/06/28: Re: 32KHz oscilator in CPLD
44748: 02/06/29: Re: State machine and syncronous inputs
44752: 02/06/29: Re: Altera equivalent for GAL 16V8
44779: 02/07/01: Re: Timed Licenses and version control ( was 5V tolerance )
44857: 02/07/03: Re: Converting to Altera Quartus
44864: 02/07/03: Re: Converting to Altera Quartus
44921: 02/07/06: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
44939: 02/07/07: Re: Converting to Altera Quartus
44977: 02/07/09: Re: Are these design guideline safe ?
45382: 02/07/22: Re: TMS 1000
45462: 02/07/24: Re: Field Programmable SoC's
45507: 02/07/25: Re: 8bit Magnitude Comparator
45513: 02/07/25: Re: Another way to simulate
45587: 02/07/28: Re: can 555 be used as clock input to cplds
45709: 02/08/02: Re: Safe design speed
45823: 02/08/07: Re: CUPL S/N?
45857: 02/08/08: Re: CUPL S/N?
45930: 02/08/12: Re: articles about FPGA based DSP design
46131: 02/08/20: Re: "flip flop" and "register"
46139: 02/08/20: Re: Good documentation on CPLD
46214: 02/08/22: Re: I2C License
46227: 02/08/22: Re: to reduce the circuit design
46357: 02/08/27: Re: Anyone already on QUARTUS II V2.1 ?
46383: 02/08/28: Re: Any FSM optimizer?
46388: 02/08/28: Re: Any FSM optimizer?
46408: 02/08/29: Re: Any FSM optimizer?
46414: 02/08/29: Re: WebPack FSM woes...
46540: 02/09/03: Re: C/C++ to Verilog/VHDL ?!
46544: 02/09/03: Re: Actel Proto Boards
46651: 02/09/05: Re: What's wrong with clearLogic?
46652: 02/09/05: Re: What's wrong with clearLogic?
46695: 02/09/06: Re: question about quiescent current
46782: 02/09/09: Re: Metastability numbers
46783: 02/09/09: Re: Metastability numbers, even better!
46789: 02/09/09: Re: Metastability numbers
46815: 02/09/10: Re: XCR3384XL availability
46820: 02/09/10: Re: Metastability numbers
46823: 02/09/10: Re: Altera Stratix DSP Performance
46830: 02/09/10: Re: Are Xilinx CoolRunners / Atmel ATF15xx CPLD's flash-based?
46835: 02/09/10: Re: XCR3384XL availability
46842: 02/09/10: Re: XCR3384XL availability
46851: 02/09/10: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
46889: 02/09/11: Re: XCR3384XL availability
46892: 02/09/11: Re: C/C++ to Verilog/VHDL ?!
46894: 02/09/11: Re: FPGA comes with a DAC?
46895: 02/09/11: Re: XCR3384XL availability
46916: 02/09/12: Re: atmel CPLD documentation
46950: 02/09/13: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46994: 02/09/14: Re: 2-D resistor array
47001: 02/09/14: Re: 2-D resistor array
47025: 02/09/15: Re: Clcok divison : Rational clock divider
47046: 02/09/16: Re: 1.8V regulator needed for Spartan IIE
47071: 02/09/17: Re: Virtex II packaging, why no QFP?
47138: 02/09/19: Re: using CPLD's inverter in oscillator circuit
47267: 02/09/22: Re: external switch to CPLD input
47274: 02/09/22: Re: Can a fpga replace external inverters in a crystal osc ?
47321: 02/09/24: Re: external switch to CPLD input
47337: 02/09/24: Re: querries regarding cpld
47341: 02/09/24: Re: upcoming trened: analogue Fpga's?
47360: 02/09/25: Re: FPGA fail when Electrostatic discharge Occurs
47377: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
47397: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
47409: 02/09/25: Re: FPGA fail when Electrostatic discharge Occurs
47491: 02/09/27: Re: CPCNG project : website updated
47503: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47511: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47660: 02/10/02: Re: USB2 in FPGA?
47685: 02/10/02: Re: Implementing Delta-Sigma ADC and DAC in Spartan IIE
47770: 02/10/04: Re: Need advice wiring up a CPLD
47771: 02/10/04: Re: ANN: Embedded processor for Tcl language
47865: 02/10/06: Re: DDS in PLD?
47877: 02/10/07: Re: Implementing Delta-Sigma ADC and DAC in Spartan IIE
48045: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
48089: 02/10/11: Re: Why can Xilinx sw be as good as Altera's sw?
48237: 02/10/15: Re: Why can Xilinx sw be as good as Altera's sw?
48302: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48360: 02/10/17: Re: Xilinx microblaze vs. picoblaze
48529: 02/10/19: Re: FPGA breadboard with a SmartMedia Card to store the bit file.
48560: 02/10/21: Re: 6502 core available
48673: 02/10/23: Re: slow slew rate signal...
48702: 02/10/23: Re: LCD driver implement with FPGA
48749: 02/10/24: Re: slow slew rate signal...
48753: 02/10/24: Re: How do I measure power consumption?
48804: 02/10/25: Re: Xilinx POS Power On Surge Current
48923: 02/10/27: Re: cpld I/O modes
49060: 02/10/31: Chip for fine delays
49097: 02/11/01: Re: Concepts: What is "Clock Edge"?
49104: 02/11/01: Re: Concepts: What is "Clock Edge"?
49106: 02/11/01: Re: XC18VXX PROM Corruption
49112: 02/11/01: Re: XC18VXX PROM Corruption
49120: 02/11/01: Re: Metastability results are finally posted
49148: 02/11/02: Re: XC18VXX PROM Corruption
49191: 02/11/05: Re: C\C++ to HDL Converter, why not HDL -> C instead
49392: 02/11/12: Re: Silly FPGA Arch question...
49462: 02/11/13: Re: jedec
49610: 02/11/18: Re: CoolBlaze and PicoBlaze
49648: 02/11/19: Re: Metastability in FPGAs
49650: 02/11/19: Re: Metastability in FPGAs
49662: 02/11/19: Re: Metastability in FPGAs
49688: 02/11/19: Re: Metastability in FPGAs
49844: 02/11/22: Re: Metastability in FPGAs
49931: 02/11/26: Re: How do I measure power consumption?
49971: 02/11/27: Re: count based Frequency generator
49995: 02/11/28: Re: count based Frequency generator
49997: 02/11/28: Re: count based Frequency generator
50112: 02/12/03: Re: ESD problems
50148: 02/12/04: Re: ISA bus VGA
50166: 02/12/04: Re: ESD problems
50196: 02/12/05: Re: ESD problems
50326: 02/12/09: Re: Pierce Crystal Oscillator in Cypress 37128 CPLD
50450: 02/12/11: Re: Tiny Forth Processors
50481: 02/12/12: Re: Tiny Forth Processors
50499: 02/12/12: Re: Power consumption question
50507: 02/12/12: Re: Power consumption question
50585: 02/12/13: Re: JVM/.NET on FPGA (was Tiny Forth Processors)
50659: 02/12/16: Re: what makes an implementation a patent?
50746: 02/12/19: Re: A/D converter in FPGA
50748: 02/12/19: Re: How to asynchronously reset a flip-flop?
50758: 02/12/19: Re: A/D converter in FPGA
50798: 02/12/20: Re: A/D converter in FPGA
50801: 02/12/20: Re: Async RAM on an FPGA board
50890: 02/12/22: Re: Xmas Wish Lists ( was stupid rookie timing question )
50902: 02/12/23: Re: thermal issues on FPGA
51066: 02/12/30: Re: thermal issues on FPGA
51100: 03/01/01: Re: shift register implementation
51236: 03/01/08: Re: Co-simulation of Spice and Vhdl
51286: 03/01/10: Re: conversions and some assistance please
51289: 03/01/10: Re: Virtex-II Pro misfire?
51326: 03/01/11: Re: Virtex-II Pro misfire?
51327: 03/01/11: Re: Virtex-II Pro misfire?
51332: 03/01/11: Re: Virtex-II Pro misfire?
51335: 03/01/11: Re: Virtex-II Pro misfire?
51355: 03/01/12: Re: Help for Generating Video Clock synchronous to Hsync of the Video..........
51511: 03/01/15: Re: Open FPGA please!
51528: 03/01/16: Re: Open FPGA please!
52005: 03/01/29: Re: frequency matching of ring oscillators
52172: 03/02/04: Re: Voltage Creep ( was 3.3 Volt tolerance in Virtex II Pro...)
52532: 03/02/13: Re: Coolrunner II I/O speeds?
52563: 03/02/14: Re: Coolrunner II I/O speeds?
52698: 03/02/20: Re: ABEL Help!
52858: 03/02/25: Re: FPGA's at High Temperatures
52950: 03/02/27: Re: configuring xilinx fpga with nand flash
53176: 03/03/06: Re: EP310
53265: 03/03/09: Re: Implementation of latch in FPGA
53317: 03/03/11: Re: Altera Clock
53350: 03/03/12: Re: Cyclone power up problem
53367: 03/03/12: Re: Cyclone power up problem
53391: 03/03/13: Re: Cyclone power up problem
53393: 03/03/13: Re: Cyclone power up problem
53412: 03/03/13: Re: Cyclone power up problem
53450: 03/03/14: Re: Cyclone power up problem
53546: 03/03/16: Re: Cyclone power up problem - Summery
53552: 03/03/16: Re: Cyclone power up problem - Summery
53603: 03/03/18: Re: Help understanding 7408 and gate chip
53606: 03/03/18: Re: Cheapest Spartan II/IIE configuration flash EEPROM!
53613: 03/03/18: Re: new XC95xx global clock
53637: 03/03/19: Re: Low Power CPLD suggestion request...
53730: 03/03/21: Re: Altera ACEX 1K
53933: 03/03/28: Re: Differential LVPECL Inteface of Spartan IIE
53945: 03/03/28: Re: Differential LVPECL Inteface of Spartan IIE
54040: 03/04/01: Re: Xilinx announces 90nm sampling today!
54041: 03/04/01: Re: What would it take?
54051: 03/04/01: Re: What would it take?
54302: 03/04/08: Re: Coolrunner 2 's 16 pins output effect
54311: 03/04/08: Re: Spartan-3 in docsan Webpack release notes... a joke???
54606: 03/04/15: Re: 2.5V switching regulator for Spartan 2
54673: 03/04/16: Re: request for simple UART
54733: 03/04/17: Re: 2.5V switching regulator for Spartan 2
54907: 03/04/22: Re: Boycott All Xilinx products untill they correct all ISE software errors
54908: 03/04/22: Re: Very low pin count FPGA
54998: 03/04/24: Re: Very low pin count FPGA
55114: 03/04/28: Re: Low pin count SOC
55174: 03/04/30: Re: Low pin count SOC
55222: 03/05/01: Re: Low power, high temperature CPLD
55227: 03/05/01: Re: Low power, high temperature CPLD
55230: 03/05/01: Re: Low power, high temperature CPLD
55273: 03/05/02: Thermal Data for Logic Devices
55274: 03/05/02: Re: Low power, high temperature CPLD
55293: 03/05/03: Re: Thermal Data for Logic Devices
55343: 03/05/05: Re: PLL chips
55399: 03/05/07: Re: I want a 800 k gates FPGA in 40 pin DIL
55411: 03/05/07: Re: PLL chips
55435: 03/05/08: Re: I want a 800 k gates FPGA in 40 pin DIL
55465: 03/05/09: Re: Price of CPLDs
55488: 03/05/10: Re: Price of CPLDs
55570: 03/05/13: Re: Atmel, just another case of bad support?
55577: 03/05/13: Re: Atmel, just another case of bad support?
55643: 03/05/15: Re: how to calculate the gate count required for a FPGA design
55644: 03/05/15: Re: OK I am pissed off with Xilinx webpack.
55684: 03/05/16: Re: Low power, high temperature CPLD
55685: 03/05/16: Re: CollRunner-II EVB problems
55696: 03/05/16: Re: Low power, high temperature CPLD
55699: 03/05/16: Re: smallest embedded cpu.
55862: 03/05/22: Re: Asynchronous State Machines and HDLs
56003: 03/05/27: Re: Why is there a large gulf between CPLD and FPGA?
56009: 03/05/27: Re: Why is there a large gulf between CPLD and FPGA?
56040: 03/05/28: Re: Why is there a large gulf between CPLD and FPGA?
56100: 03/05/29: Re: FIFO Controller
56101: 03/05/29: Re: 5v TTL to 3.3v 2.5v 1.8v 1.2v LVTTL solution
56164: 03/05/30: Re: New version,Low Speed
56166: 03/05/30: Re: FIFO Controller
56167: 03/05/30: Re: FIFO Controller
56169: 03/05/30: Re: smallest embedded cpu....and the most pain?
56170: 03/05/30: Re: FPGA's an Flash
56193: 03/05/30: Re: smallest embedded cpu....and the most pain?
56104: 03/05/29: Re: 5v TTL to 3.3v 2.5v 1.8v 1.2v LVTTL solution
56307: 03/06/03: Re: FPGA's an Flash
56308: 03/06/03: Re: FPGA's an Flash
56309: 03/06/03: Re: New version,Low Speed
56424: 03/06/05: Re: FPGA's an Flash
56567: 03/06/10: Re: Controlling FPGA speed with VCCINT
56575: 03/06/10: Re: Balls! (676 of them)
56648: 03/06/11: Re: Controlling FPGA speed with VCCINT
56650: 03/06/11: Re: Cheap development tools
56708: 03/06/12: Re: DVI with a Virtex-II - summary
56733: 03/06/13: Re: Analog signals connected to xilinx spartan2
56739: 03/06/13: Re: How to Capture a VGA display EXTERNALLY
56777: 03/06/15: Re: Power consumed in a non configured FPGA?
56823: 03/06/17: Re: Power consumed in a non configured FPGA?
56829: 03/06/17: Re: An All Digital Phase Lock Loop
56909: 03/06/19: Re: FPGA to Custom ASIC ??
56910: 03/06/19: Re: Cyclone vs. Acex consumption?
56931: 03/06/19: Re: Power consumed in a non configured FPGA?
56967: 03/06/20: Re: Dr. Leaky responds
57107: 03/06/24: Re: Programmable Delay (not clock driven)
57108: 03/06/24: Re: Q: regarding I2C protocols
57171: 03/06/25: Re: PALs, GALs and ABEL
57219: 03/06/26: Re: GAL16V8 reverse compilation
57284: 03/06/27: Re: Xilinx Webpack bugs bugs bugs
57288: 03/06/27: Re: Free PAL synth tools (ABEL, PALASM, VHDL, etc.)?
57292: 03/06/27: Re: Low-power FPGA
57294: 03/06/27: Re: Abel et al Flows
57372: 03/06/29: Re: why so many problems Xilinx ?
57373: 03/06/29: Re: why so many problems Xilinx ?
57380: 03/06/29: Re: why so many problems Xilinx ?
57381: 03/06/29: Re: why so many problems Xilinx ?
57382: 03/06/29: Re: Xilinx Webpack bugs bugs bugs
57384: 03/06/29: Re: why so many problems Xilinx ?
57521: 03/07/02: Re: Cyclone vs Spartan-3
57596: 03/07/03: Re: Xilinx ISE drops support for more parts
57613: 03/07/03: Re: XPLA3 vs. MAX3000A
57692: 03/07/04: Re: XPLA3 vs. MAX3000A
57693: 03/07/04: Re: XPLA3 vs. MAX3000A
57734: 03/07/05: Re: XPLA3 vs. MAX3000A
57754: 03/07/06: Re: XPLA3 vs. MAX3000A
57758: 03/07/06: Re: XPLA3 vs. MAX3000A
57769: 03/07/07: Re: What About CPLD Standardization ?
57815: 03/07/08: Re: XPLA3 vs. MAX3000A
57872: 03/07/09: Re: phase noise in NCO
58281: 03/07/19: Re: Graduation Day: My first 4-layer PCB
58321: 03/07/21: Re: Phase / frequency detector types
58494: 03/07/25: Re: Pricing question....
58898: 03/08/04: Re: 5 volt tolerant Xilinx parts
58994: 03/08/06: Re: Design fits XC9536 but not XC9536XL
59002: 03/08/06: Re: 'Virtual Grounds'
59029: 03/08/07: Re: Design fits XC9536 but not XC9536XL
59081: 03/08/08: Re: Patent granted for "system on a chip" framework?
59090: 03/08/08: Re: Size does matter
59194: 03/08/12: Re: Upgrading OS or WebPack
59454: 03/08/20: Re: 22V10, ABEL & Current Design Tools?
59502: 03/08/21: Re: 22V10, ABEL & Current Design Tools?
59503: 03/08/21: Re: 22V10, ABEL & Current Design Tools?
59504: 03/08/21: Re: Legacy 4005 series and current Xilinx ISE offerings?
59506: 03/08/21: Re: Xilinx XC3000 with Xilinx ISE student edition 4.2i
59531: 03/08/21: Re: 22V10, ABEL & Current Design Tools?
59533: 03/08/21: Re: Legacy 4005 series and current Xilinx ISE offerings?
59569: 03/08/22: Re: 22V10, ABEL & Current Design Tools?
59570: 03/08/22: Re: 22V10, ABEL & Current Design Tools?
59669: 03/08/26: Re: Thinking out loud about metastability
59725: 03/08/27: Re: Thinking out loud about metastability
59819: 03/08/29: Re: Thinking out loud about metastability
59904: 03/09/01: Re: Thinking out loud about metastability
60041: 03/09/04: Re: Measuring metastability.
60088: 03/09/05: Re: New to FPGA, seeking advice
60196: 03/09/08: Re: CMOS camera w/ USB2 -- crazy?
60288: 03/09/10: Re: opinions are OK
60331: 03/09/11: Re: Metatstable Modeling
60334: 03/09/11: Re: Embedded/Microcontroller FPGA and Software Defined Radio
60351: 03/09/11: Re: Metatstable Modeling
60376: 03/09/12: Re: Metatstable Modeling
60401: 03/09/12: Re: Metatstable Modeling
60527: 03/09/16: Re: Original (5V) Xilinx Spartan ? ( Philip ? )
60633: 03/09/18: Re: opinions are OK
60724: 03/09/20: Re: Some question about using FPGA
60725: 03/09/20: Re: opinions are OK
60924: 03/09/25: Re: ISE 6.1 and Redhat 9
61319: 03/10/02: Re: Ask the hotline, you may be surprised and pleased
61409: 03/10/03: Re: CUPL documentation?
61411: 03/10/03: Re: Ask the hotline, you may be surprised and pleased
61468: 03/10/05: Re: Interesting article about FPGAs
61488: 03/10/06: Re: Interesting article about FPGAs
61886: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
61889: 03/10/15: Re: FPGA/CPLD With Analog Functions?
61890: 03/10/15: Re: Pass transistor logic in a FPGA
61898: 03/10/15: Re: SpartanXL
61900: 03/10/15: Re: How to program an XC5210
61908: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
61967: 03/10/16: Re: SpartanXL
61968: 03/10/16: Re: Electronic Dice ( 3 die ) In VHDL
61969: 03/10/16: Re: Power on problems
61971: 03/10/16: Re: FPGA/CPLD With Analog Functions?
62019: 03/10/17: Re: wincupl, winsim documentation?
62021: 03/10/17: Re: Electronic Dice ( 3 die ) In VHDL
62022: 03/10/17: Re: SpartanXL
62033: 03/10/17: Re: Spartan-3 non-ES availability, and misleading pricing info
62197: 03/10/22: Re: 74 logic to CPLD. how easy for a Newbie?
62393: 03/10/29: Re: Electronic Dice VHDL Program
62398: 03/10/29: Re: Are clock and divided clock synchronous?
62595: 03/11/03: Re: Minimalist RS232 on Cyclone
62815: 03/11/08: 0.13u device with 5V I/O
62828: 03/11/09: Re: 0.13u device with 5V I/O
62851: 03/11/11: Re: 0.13u device with 5V I/O
62880: 03/11/11: Re: 0.13u device with 5V I/O
62881: 03/11/11: Re: Home grown CPU core legal?
62955: 03/11/12: Re: Implementing a very fast counterin VirtexII
62960: 03/11/12: Re: Implementing a very fast counterin VirtexII
62965: 03/11/12: Re: Home grown CPU core legal?
62972: 03/11/12: Re: Home grown CPU core legal?
62973: 03/11/12: Re: Home grown CPU core legal?
63077: 03/11/14: Re: Frequency Doubler - VHDL/Verilog
63193: 03/11/18: Re: Do I need to connect all Vref in a bank together?
63259: 03/11/19: Re: Do I need to connect all Vref in a bank together?
63265: 03/11/19: Re: Thank you all for the replays.
63333: 03/11/20: Re: Small PLD choices
63334: 03/11/20: Re: Anyone use HDL as design tool for PCBs?
63340: 03/11/20: Re: State Machines....
63398: 03/11/21: Re: State Machines....
63423: 03/11/21: Re: Xilinx legacy situation
63516: 03/11/25: Re: Reconstructing source code from JED file
63520: 03/11/25: 5V I/O with 1.8V Core
63526: 03/11/25: Re: 5V I/O with 1.8V Core
63541: 03/11/25: Re: Slightly unmatched UART frequencies
63572: 03/11/26: Re: Slightly unmatched UART frequencies
63573: 03/11/26: Re: 5V I/O with 1.8V Core
63578: 03/11/26: Re: 5V I/O with 1.8V Core
63581: 03/11/26: Re: 5V I/O with 1.8V Core
63626: 03/11/27: Re: 5V I/O with 1.8V Core
63671: 03/11/28: Re: 5V I/O with 1.8V Core
63696: 03/12/01: Re: Slightly unmatched UART frequencies
63702: 03/12/01: Re: XC9500 design does not fit into Coolrunner
63942: 03/12/10: ASMBL - hmmm
63948: 03/12/10: Re: ASMBL - hmmm ---- hmmmm -- Wow?
63952: 03/12/10: Re: ASMBL - hmmm ---- hmmmm -- Wow?
63981: 03/12/11: Re: ASMBL - hmmm ---- hmmmm -- Wow?
64125: 03/12/18: Re: What is this ASMBL thing from Xilinx?
64166: 03/12/19: Re: www.fpga-faq.com
65405: 04/01/28: Re: FPGA Config Readback while run, gotchas etc
65536: 04/02/02: Re: Differences between Xilinx ISE and Altera Quartus software
65579: 04/02/03: Re: ASMBL
65582: 04/02/03: Re: ASMBL anxiety
65635: 04/02/04: Re: Stratix II NIOS sizes ?
65636: 04/02/04: Re: Is it possible that a Virtex II device performs below its spec?
65847: 04/02/08: Re: Pricing, 101, and sales seeding, and designers' radar modifiers...
65848: 04/02/08: Re: Stratix II NIOS sizes ?
65987: 04/02/11: Re: Pricing, 101
66044: 04/02/12: Re: negative hold time (Typ/max)
66045: 04/02/12: Re: Pricing, 101
66055: 04/02/12: Re: negative hold time (Typ/max)
66115: 04/02/13: Re: negative hold time
66116: 04/02/13: Re: Peter's 1Hz-640MHz Synth project
66123: 04/02/13: Re: Peter's 1Hz-640MHz Synth project
66134: 04/02/13: Re: Peter's 1Hz-640MHz Synth project
66138: 04/02/13: Re: Peter's 1Hz-640MHz Synth project
66140: 04/02/13: Re: Peter's 1Hz-640MHz Synth project
66197: 04/02/14: Re: Peter's 1Hz-640MHz Synth project
66198: 04/02/14: Re: Pricing, 101
66255: 04/02/16: Re: Dual-stack (Forth) processors
66289: 04/02/17: Re: 74ls193 in coolrunner
66297: 04/02/17: Re: 74ls193 in coolrunner
66440: 04/02/20: Re: Can FPGA bootstrap itself?
66566: 04/02/23: Re: Spartan 3 - avaliable in small quantities?
66594: 04/02/24: Re: Spartan 3 - avaliable in small quantities?
66598: 04/02/24: Re: Dual-stack (Forth) processors
66603: 04/02/24: Re: Spartan 3 - avaliable in small quantities?
66712: 04/02/26: Re: Basic jitter from a CPLD (XC7500XL)
66730: 04/02/26: Re: Stratix 2 / MAX II
66790: 04/02/27: Re: Altera ACEX chip wide reset
66793: 04/02/27: Re: Basic jitter from a CPLD (XC7500XL)
66803: 04/02/27: Re: Basic jitter from a CPLD (XC7500XL)
66995: 04/03/03: Re: Need to speed up Stratix compiles.
67015: 04/03/04: Re: Need to speed up Stratix compiles.
67128: 04/03/06: Re: PWM, PLD programming ,(up/down ramp frequency)
67139: 04/03/06: Re: PWM, PLD programming ,(up/down ramp frequency)
67173: 04/03/08: lattice metastable info
67175: 04/03/08: Re: Release asynchrounous resets synchronously
67180: 04/03/08: Re: Release asynchrounous resets synchronously
67212: 04/03/09: Re: NEWS: Xilinx announces acquisition of Triscend
67213: 04/03/09: Re: NEWS: Xilinx announces acquisition of Triscend
67214: 04/03/09: Re: HOW to Increase jitter in ALTERA PLL ?
67216: 04/03/09: Re: Release asynchrounous resets synchronously
67221: 04/03/09: Re: Release asynchrounous resets synchronously
67293: 04/03/10: Re: HOW to Increase jitter in ALTERA PLL ?
67294: 04/03/10: Re: Release asynchrounous resets synchronously
67367: 04/03/11: Re: copy protection on FPGA using embedded serial number
67492: 04/03/13: Re: PWM, PLD programming ,(up/down ramp frequency)
67511: 04/03/13: Re: PWM, PLD programming ,(up/down ramp frequency)
67512: 04/03/13: Re: PWM, PLD programming ,(up/down ramp frequency)
67543: 04/03/14: Re: PWM, PLD programming ,(up/down ramp frequency)
67607: 04/03/16: Re: low power Oscillator for Xilinx CoolrunnerII
67625: 04/03/16: Re: low power Oscillator for Xilinx CoolrunnerII
67666: 04/03/17: Re: ISE 6.2 (w/ SP#1) is 10+ times slower than 6.1
67872: 04/03/22: Re: Why It Is not Recommended to Infer latches in VLSI Design...
67946: 04/03/23: Re: Fried a XC2S200!
67961: 04/03/24: Re: How many times can I burn an FPGA?
67964: 04/03/24: Re: How many times can I burn an FPGA?
68032: 04/03/25: Re: Time measurement with Xilinx Spartan-3 - Help
68072: 04/03/26: Re: PWM, PLD programming ,(up/down ramp frequency)
68074: 04/03/26: Re: Clock divider preserving duty-cycle ?
68093: 04/03/26: Re: CPLD: assign pins first, or design content first?
68132: 04/03/27: Re: CPLD: assign pins first, or design content first?
68354: 04/04/02: Re: AHDL, VERILOG or VHDL??
68416: 04/04/04: Re: The Logic Behind License Renewal
68440: 04/04/05: Re: Which HVL is the most popular?
68464: 04/04/06: Re: ATMEL support / Are they serious ?
68465: 04/04/06: Re: ATMEL support / Are they serious ?
68790: 04/04/19: Re: DDS-Based PLL
68823: 04/04/20: Re: Clock Enables and Power
68869: 04/04/21: Re: calculate the number of logic gate in FPGA
68884: 04/04/21: Re: Issues on Shift Register in a Clockless UART
68913: 04/04/22: Re: cpld in plcc84 package
68927: 04/04/22: Re: Issues on Shift Register in a Clockless UART
68953: 04/04/23: Time domain/Delay line UARTs - high speeds
68986: 04/04/24: Re: OT - Generating a 20MHz clock that can be adjusted by +- 2%
68994: 04/04/24: Re: OT - Generating a 20MHz clock that can be adjusted by +- 2%
69000: 04/04/24: Re: transport applications
69009: 04/04/25: Re: Help implementing a 74273 flip flop in a 9536 cpld
69030: 04/04/26: Re: Looking for a USB-enabled flash-based microcontroller with CPLD/FPGA
69035: 04/04/26: Re: Xilinx CPLD - FSM - one hot - lost token...
69070: 04/04/27: Re: CPLD input
69071: 04/04/27: Re: Stretch Inc
69073: 04/04/27: Re: Stretch Inc
69124: 04/04/28: Re: Strange message from Xilinx 6.2.01i
69135: 04/04/28: Re: Altera EP320 to PAL16V8
69228: 04/05/01: Re: Correction
69238: 04/05/02: Re: Connecting a crystal to a Cyclone or Max PLD
69476: 04/05/12: Re: FPGA wanted
69494: 04/05/12: Re: Easypath
69516: 04/05/13: Re: Looking for Synario 3.0 (Lattice)
69520: 04/05/13: Re: Decompiler for GAL JEDEC fusemap
69537: 04/05/13: Re: Looking for Synario 3.0 (Lattice)
69557: 04/05/14: Re: Looking for Synario 3.0 (Lattice)
69570: 04/05/14: Re: Looking for Synario 3.0 (Lattice)
69639: 04/05/17: Re: Phase relationship management
69669: 04/05/18: Re: How to replace Triscend - Xilinx plans for the future
69671: 04/05/18: Atmel Zigbee solutions
69719: 04/05/19: Re: How to replace Triscend - Xilinx plans for the future
69735: 04/05/19: Re: Nios II Going Live...
69779: 04/05/20: Re: Nios II Going Live...
69780: 04/05/20: Re: Nios II Going Live...
69781: 04/05/20: Re: Nios II Going Live...
69783: 04/05/20: Re: How to replace Triscend - Xilinx plans for the future
69811: 04/05/21: Re: Nios II Going Live...
69850: 04/05/22: Re: Never right, always room for improvement
69890: 04/05/24: Re: strange behaviour of the design
69927: 04/05/25: Re: Driving fpga pin out over long cable
70006: 04/05/27: Re: What can I do if my chip can't meet timing?
70025: 04/05/28: Re: Driving fpga pin out over long cable
70028: 04/05/28: Re: Driving fpga pin out over long cable
70096: 04/06/03: Re: FPGA + A/D converter
70104: 04/06/03: Re: FPPTA?
70275: 04/06/11: Re: Avoid action on very short peak on input signal (Xilinx Spartan
70377: 04/06/15: Re: Atmel WinCupl
70407: 04/06/16: Progress in FPGA static Icc timeline degrade
70409: 04/06/16: Re: pulse generation using SRL16E on a Virtex-II
70488: 04/06/18: Re: compressing Xilinx bitstreams
70492: 04/06/18: Re: compressing Xilinx bitstreams
70502: 04/06/18: Re: compressing Xilinx bitstreams
70513: 04/06/18: Re: compressing Xilinx bitstreams
70544: 04/06/20: Re: CPLD mistery. Help.
70651: 04/06/23: Re: CPLD mistery. Problem Found... and is an interesting one !
70652: 04/06/23: Re: Family Photo Album
70658: 04/06/23: Re: Family Photo Album
70726: 04/06/25: Re: DPLL in CPLD
70759: 04/06/27: Re: DPLL in CPLD
70777: 04/06/28: Re: How to add clock delay in CPLD?
70799: 04/06/29: Re: Battle of the Vapours
70807: 04/06/29: Re: Family Photo Album
70809: 04/06/29: Re: Battle of the Vapours
70922: 04/07/02: Re: reduced power =?ISO-8859-1?Q?Xilinx=AE_Spartan-3=28TM=29_?=
70939: 04/07/02: Re: Does Xilinx have the worst web site on the planet?
70981: 04/07/04: Re: Multi-phase Motor Controller?
71016: 04/07/06: Re: FPGAs starting with incorrect bitstream !?
71088: 04/07/08: Re: FSM in illegal state
71096: 04/07/08: Re: FSM in illegal state
71097: 04/07/08: Re: RC Servo PWM Digital Capture in a Xilinx xc9500 CPLD?
71099: 04/07/08: Re: FSM in illegal state
71128: 04/07/09: Re: FSM in illegal state
71447: 04/07/19: Re: FPGAs starting with incorrect bitstream !?
71511: 04/07/21: Re: Low Power Applications - enumerate
71554: 04/07/22: Re: FPGA Selection--
71625: 04/07/26: Re: 1GHz FPGA counters
71630: 04/07/26: Re: 1GHz FPGA counters
71653: 04/07/27: Re: 1GHz FPGA counters
71654: 04/07/27: Re: 1GHz FPGA counters
71669: 04/07/27: Re: 1GHz FPGA counters
71690: 04/07/28: Re: 1GHz FPGA counters
71701: 04/07/28: Re: On-Chip Oscillator
71731: 04/07/29: Re: FPGA vs CPLD
71732: 04/07/29: Re: configuration SRAM cells in Xilinx/Altera FPGAs
71805: 04/07/31: Re: On-Chip Oscillator
71810: 04/07/31: Re: On-Chip Oscillator
71834: 04/08/02: Re: Fast Memories
71844: 04/08/02: Re: 1GHz FPGA counters
71859: 04/08/03: Re: DDR or SDR ? Memory controller in FPGA
71861: 04/08/03: Re: Compact FPGA Board?
71918: 04/08/04: Re: FPGA and RS422
71976: 04/08/05: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
72012: 04/08/06: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
72021: 04/08/06: Re: Comparing Quality of Results of FPGA CAD Tools
72067: 04/08/07: Re: Compact FPGA Board?
72075: 04/08/08: Re: ABEL support for legacy chips
72093: 04/08/09: Re: ABEL support for legacy chips
72142: 04/08/10: Re: Now I am really confused!
72143: 04/08/10: Re: ABEL support for legacy chips
72187: 04/08/11: Re: ABEL support for legacy chips
72233: 04/08/12: Re: new XILINX 9500XL datasheets
72443: 04/08/19: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72564: 04/08/25: Re: Altera MAX II
72588: 04/08/26: Re: ring oscillator calibration
72618: 04/08/27: Re: Altera MAX II
72639: 04/08/27: Re: ring oscillator calibration
72640: 04/08/27: Re: Altera MAX II
72814: 04/09/03: Re: Completed my first Virtex4 design
73724: 04/09/29: Re: NV on-chip memory?
73820: 04/09/30: Re: NV on-chip memory?
73821: 04/09/30: Re: DISCLOSURE : NV on-chip memory?
73836: 04/09/30: Re: ELABORATED DISCLOSURE and continued discussion : NV on-chip
73905: 04/10/01: Re: MicroBlaze is no available as Open-Source!! (from independant
73912: 04/10/01: Re: MicroBlaze is no available as Open-Source!! (from independant
73999: 04/10/02: Re: JOP on Spartan-3 Starter Kit
74005: 04/10/02: Re: FPGA vs ASIC area
74042: 04/10/03: Re: JOP on Spartan-3 Starter Kit
74058: 04/10/03: Re: FPGA vs ASIC area
72843: 04/09/05: Re: CPLD : Is there a way
72911: 04/09/08: Re: 1GHz FPGA counters
72948: 04/09/09: Re: 1GHz FPGA counters
73053: 04/09/13: Re: Need some help with some technical claims...
73077: 04/09/14: Re: Need some help with some technical claims...
73079: 04/09/14: Re: Virtex 4 released today
73081: 04/09/14: Re: Virtex 4 released today
73158: 04/09/15: Re: Virtex 4 released today
73208: 04/09/16: Re: Virtex 4 released today
73209: 04/09/16: Re: I/O state of max7000s during power-up?
73215: 04/09/16: Re: Xilinx DCMs
73254: 04/09/17: Re: beginner's question
73676: 04/09/28: Re: NV on-chip memory?
73681: 04/09/28: Re: Spartan-3 VCCIO ramp up time
74940: 04/10/22: Re: Async reset
75055: 04/10/26: Re: Assembler for PicoBlaze in Perl
75056: 04/10/26: Re: Low-power FPGAs?
75066: 04/10/26: Re: Low-power FPGAs?
75067: 04/10/26: Re: Assembler for PicoBlaze in Perl
75137: 04/10/27: Re: Low-power FPGAs?
75163: 04/10/28: Re: Low-power FPGAs?
75170: 04/10/28: Re: Low-power FPGAs?
75180: 04/10/28: Re: Low-power FPGAs?
75229: 04/10/30: Re: Low-power FPGAs?
75243: 04/10/31: Re: Low-power FPGAs?
75261: 04/11/01: Re: Low-power FPGAs?
75346: 04/11/03: Re: Low-power FPGAs?
74079: 04/10/04: Re: NV on-chip memory?
74080: 04/10/04: Re: M*Blaze in Cyclone ! End of What? ;)
74148: 04/10/05: Re: JOP on Spartan-3 Starter Kit
74262: 04/10/07: Re: DCM and CLKFX - is this allowed?
74321: 04/10/08: Re: DCM and CLKFX - is this allowed?
74364: 04/10/09: Re: Flex10K10A, I2C, MultiVolt IO, pull-ups
74371: 04/10/09: Re: PLL lock usage into Altera Stratix devices
74402: 04/10/11: Re: JOP on Spartan-3 Starter Kit
74404: 04/10/11: Re: JOP on Spartan-3 Starter Kit
74445: 04/10/12: Re: Temperature considerations of inactive logic blocks
74490: 04/10/13: Re: Actel Fusefile Reverse Engineering
74492: 04/10/13: Re: level converter for high frequencies
74600: 04/10/15: Re: Xilinx to Make Image Processing FPGA
74736: 04/10/18: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74781: 04/10/19: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74931: 04/10/22: Re: Async reset
75442: 04/11/06: Re: Number of FPGA users?
75444: 04/11/06: Re: Low-power FPGAs?
75527: 04/11/09: Re: Low-power FPGAs?
75591: 04/11/11: Re: Advice on Contemporary Low cost, Medium Density CPLDs
75600: 04/11/11: Re: Xilinx Tshirts in football package.....
75657: 04/11/12: Re: C Compiler for Picoblaze !!!!!
75659: 04/11/12: Re: Low-power FPGAs?
75668: 04/11/12: Re: asynchronous bus transfers
75712: 04/11/13: Re: Obsolete processors resurected in FPGAs
75745: 04/11/14: Re: Obsolete processors resurected in FPGAs
75751: 04/11/14: Re: Obsolete processors resurected in FPGAs
75753: 04/11/14: Re: Obsolete processors resurected in FPGAs
75909: 04/11/19: Re: 5V inputs with series resistor on Spartan-3
75939: 04/11/20: Re: NIOSII problems?
76050: 04/11/24: TSMC release 40V 0.18u process, MTP comming
76073: 04/11/24: Re: Spartan 3L - misleading info to potential customers
76106: 04/11/25: Re: Hierarchical PCB design.
76220: 04/11/29: Re: CPLD + CAN bus
76246: 04/11/30: Re: CPLD + CAN bus
76262: 04/11/30: Re: CPLD + CAN bus
76334: 04/12/01: Re: Pin connection doubts
76335: 04/12/01: Re: CMOS capacitive loads, transition probabilities and FPGAs
76352: 04/12/01: Re: CMOS capacitive loads, transition probabilities and FPGAs
76371: 04/12/01: Re: Stupid tools question...
76596: 04/12/07: Re: how to speed up my accumulator ??
76599: 04/12/07: Re: how to speed up my accumulator ??
76678: 04/12/09: Re: Open source FPGA EDA Tools
76854: 04/12/15: Re: Need help with CUPL
76985: 04/12/18: Re: Need help with CUPL
76991: 04/12/19: Re: GAL/PAL - Read the UES/AND-Array with burned Security Fuse???
77010: 04/12/20: Low Power FPGAs, Vcc control
77054: 04/12/21: Re: Using low-core-voltage devices in industrial applications
77071: 04/12/22: Re: Using low-core-voltage devices in industrial applications
77102: 04/12/23: Re: Using low-core-voltage devices in industrial applications
77547: 05/01/11: Re: Configuration devices
77634: 05/01/13: Re: Programming and copyright
77713: 05/01/15: Re: I2C --> SPI or Parallel Port Concentrator
77746: 05/01/16: Re: I2C --> SPI or Parallel Port Concentrator
77902: 05/01/20: Re: Comparison of LEON2, Microblaze and Openrisc processors
77939: 05/01/21: Re: Comparison of LEON2, Microblaze and Openrisc processors
78016: 05/01/23: Re: Microscope examination of a PLD
78056: 05/01/24: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
78096: 05/01/25: Re: 60Hz clock on XC9572
78117: 05/01/25: Re: 60Hz clock on XC9572
78186: 05/01/26: Re: 60Hz clock on XC9572
78196: 05/01/26: Re: Copying/Reverse Engineering PAL
78229: 05/01/27: Re: 60Hz clock on XC9572
78236: 05/01/27: Re: lowest-cost FPGA and CPLD
78241: 05/01/27: Re: =?ISO-8859-1?Q?ProASIC=A7_Released?=
78242: 05/01/27: Re: =?ISO-8859-1?Q?ProASIC=A7_Released?=
78246: 05/01/27: Re: =?ISO-8859-1?Q?ProASIC=A7_Released?=
78307: 05/01/29: New code FLASH memory
78438: 05/02/01: Re: could I drive Altera MAX II CPLD with LSTTL outputs?
78496: 05/02/02: Re: LVDS without termination
78506: 05/02/02: Re: See Peter's High-Wire Act next Tuesday
78597: 05/02/04: Re: See Peter's High-Wire Act next Tuesday
78603: 05/02/04: Re: See Peter's High-Wire Act next Tuesday
78605: 05/02/04: Re: See Peter's High-Wire Act next Tuesday
78615: 05/02/04: Re: See Peter's High-Wire Act next Tuesday
78640: 05/02/05: Re: See Peter's High-Wire Act next Tuesday
78649: 05/02/05: Re: Xilinx Virtex4 / Spartan3 High Speed Designs
78690: 05/02/06: Re: See Peter's High-Wire Act next Tuesday
78709: 05/02/07: Re: See Peter's High-Wire Act next Tuesday
78710: 05/02/07: Re: See Peter's High-Wire Act next Tuesday
78715: 05/02/07: Re: See Peter's High-Wire Act next Tuesday
78725: 05/02/07: Re: See Peter's High-Wire Act next Tuesday
78765: 05/02/08: Re: See Peter's High-Wire Act next Tuesday
78782: 05/02/08: Re: See Peter's High-Wire Act next Tuesday
78986: 05/02/11: Re: SimmStick FPGA module
79145: 05/02/15: Re: SimmStick FPGA module
79146: 05/02/15: Re: See the next high-wire act, this time on power consumption
79208: 05/02/16: Re: See the next high-wire act, this time on power consumption
79234: 05/02/16: Re: See the next high-wire act, this time on power consumption
79284: 05/02/17: Re: What do future FPGA's need?
79339: 05/02/18: Re: Updated Stratix II Power Specs & Explanation
79418: 05/02/19: Re: DNL and INL calculation
79531: 05/02/21: Re: hdl:lament
79553: 05/02/21: Re: difficult to build counter, some help please : (
79597: 05/02/22: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40
79602: 05/02/22: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40
79603: 05/02/22: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40
79646: 05/02/23: Re: SD Card and FPGA
79669: 05/02/23: Re: Is Altera Cyclone a good choice ?
79730: 05/02/24: Re: Hardcopy Vs ASIC
79820: 05/02/25: Re: cheapest CPLD
79838: 05/02/25: Re: Nios performance
79985: 05/02/28: Re: Prescalable counter
79990: 05/02/28: Re: I2C protocol to communicate between FPGAs
80028: 05/03/01: Re: Prescalable counter
80328: 05/03/04: Re: programming ATF750 in ABEL
80329: 05/03/04: Re: making an fpga hot - addendum
80400: 05/03/05: Re: Genlock
80439: 05/03/06: Re: using atmel fit2500 fitter for a atf750
80463: 05/03/07: Re: Help with 22v10 and WinCupl :(
80502: 05/03/08: Re: Asynchronous processor !?!
80510: 05/03/08: Re: Help with 22v10 and WinCupl :(
80511: 05/03/08: Re: state encoding in FSM for simple cases ?
80512: 05/03/08: Re: Surge in S2? ~3 amperes at cold for a millisecond
80578: 05/03/09: Re: Asynchronous processor !?!
80749: 05/03/11: Re: programing an ATF750 from VHDL
80860: 05/03/13: Re: (Stupid/Newbie) Question on UART
80886: 05/03/14: Re: (Stupid/Newbie) Question on UART
80929: 05/03/15: Re: XC3000 non-recoverable lockup problem
80955: 05/03/15: Re: (Stupid/Newbie) Question on UART
80983: 05/03/16: Re: XC3000 non-recoverable lockup problem
80988: 05/03/16: Re: XC3000 non-recoverable lockup problem
81087: 05/03/18: Re: XC3000 non-recoverable lockup problem
81121: 05/03/18: Re: Newbie: Slow FPGAs
81188: 05/03/19: Re: XC3000 non-recoverable lockup problem
81189: 05/03/19: Re: XC3000 non-recoverable lockup problem
81277: 05/03/21: Re: PAL problems (again)
81380: 05/03/23: Re: XC3000 non-recoverable lockup problem
81381: 05/03/23: Re: XC3000 non-recoverable lockup problem
81398: 05/03/23: Re: XC3000 non-recoverable lockup problem
81444: 05/03/24: Re: XC3000 non-recoverable lockup problem
81454: 05/03/24: Re: XC3000 non-recoverable lockup problem
81462: 05/03/24: Re: OT: EDA tools
81483: 05/03/25: Re: XC3000 non-recoverable lockup problem
81626: 05/03/29: Re: XC3000 non-recoverable lockup problem
81628: 05/03/29: Re: free 8 Channel Frequency meter for all FPGA owners :)
81629: 05/03/29: Re: some +. for Altera
81860: 05/04/03: Re: Achieving required speed in Virtex-II Pro FPGA
81932: 05/04/05: Re: XC3000 non-recoverable lockup problem
82026: 05/04/06: Re: ISA vs. patent/trademark
82119: 05/04/07: Re: Xilinx ISE 7.1i / stuck down XCR3064 outputs
82169: 05/04/08: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
82436: 05/04/13: Re: General question about soft CPUs
82536: 05/04/14: Re: "The ISE 7.1 Experience"
82765: 05/04/18: Re: Xilinx tools from the commandline
82880: 05/04/19: Re: Soft CPU vs Hard CPU's
82937: 05/04/20: Re: College Project
82978: 05/04/21: Re: Charge-pumps in FPGAs? Not Since 1998
83603: 05/05/04: Re: Patent issues in implementing embedded fpgas
83907: 05/05/10: Re: Altera: Maxplus rules!
84116: 05/05/13: Re: Virtex4 running at 360Mhz DDR
84137: 05/05/13: Re: V4 vs. Stratix-II...
84218: 05/05/15: Re: Stupid Question on the Urination Contest... Re: V4 vs. Stratix-II...
84233: 05/05/16: Re: Update Picoblaze Code in Bitstream
84353: 05/05/18: Re: V4 vs. Stratix-II...
84550: 05/05/21: Re: Bullshit Achieves Literary Status
84791: 05/05/27: Re: ISE 7.1 small advice about project files (.ISE extension)
85310: 05/06/08: Re: Lattice and Mentor seminar info pieces... & ST's new 'uC'+FPGA
85320: 05/06/08: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
85321: 05/06/08: Re: Pissed off with Xilinx - Spartan 3
85329: 05/06/08: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
85347: 05/06/08: Re: Lattice and Mentor seminar info pieces... & ST's new 'uC'+FPGA
85380: 05/06/09: Re: ISE/EDK 6.3 vs 7.1...
85382: 05/06/09: Re: General gripe session ....
85386: 05/06/09: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
85577: 05/06/11: Re: computer upgrade time.
85610: 05/06/12: Re: Best Practices for Hardware Designers
85734: 05/06/15: Re: Somewhat OT - falling behind the times ...
85857: 05/06/17: Re: AbusivepPricing information in marketing publications
85910: 05/06/18: Re: AbusivepPricing information in marketing publications
85938: 05/06/19: Re: CPLD fusemap data - why the secrecy?
85943: 05/06/19: Re: CPLD fusemap data - why the secrecy?
85983: 05/06/20: Re: Interesting question on CPLD
85985: 05/06/20: Re: FPGAs: Where will they go?
85986: 05/06/20: Re: Retrieving code from an old PAL
86095: 05/06/22: Re: FPGAs: Where will they go?
86126: 05/06/22: Re: FPGAs: Where will they go?
86129: 05/06/22: Re: FPGAs: Where will they go?
86195: 05/06/23: Re: FPGAs: Where will they go?
86196: 05/06/23: Re: FYI: Spartan-3 XC3S50 through XC3S1500 Back on Xilinx Online
86271: 05/06/24: Re: Xilinx webshop
86314: 05/06/25: Re: Xilinx webshop
86360: 05/06/27: Re: Xilinx webshop
86361: 05/06/27: Re: Chess & FPGAs
86368: 05/06/27: Re: Xilinx webshop
86546: 05/06/30: Re: Small FPGA
86614: 05/07/01: Re: Direct audio output from FPGA pins
86878: 05/07/08: Stacked Die devices
86934: 05/07/10: Re: Altera QII WE Tutorials
87546: 05/07/26: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
87550: 05/07/26: Re: Free 8 bit micro for fpga
87596: 05/07/27: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
87598: 05/07/27: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
87616: 05/07/27: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
87658: 05/07/28: Re: isplever and GAL
87699: 05/07/29: Re: Delay Generators in FPGAs
87860: 05/08/03: Re: 5V non-volatile reprogrammable FPGA/CPLD
87861: 05/08/03: Re: Programmable frequency synthesizer with Xilinx DCM
87868: 05/08/03: Re: Programmable frequency synthesizer with Xilinx DCM
87930: 05/08/04: Re: Programmable frequency synthesizer with Xilinx DCM
87990: 05/08/05: Re: Programmable frequency synthesizer with Xilinx DCM
88044: 05/08/08: AS Assembler support for Lattice Mico8
88166: 05/08/11: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
88174: 05/08/11: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
88299: 05/08/15: Re: ISE 7.1 'improvements' plus meandering....
88302: 05/08/15: Re: ISE 7.1 'improvements' plus meandering....
88305: 05/08/15: Re: ISE 7.1 'improvements' plus meandering....
88331: 05/08/16: Re: Peter Alfke's SPDT Switch Debouncer
88339: 05/08/16: Re: AHDL Abandoned in Quartus?
88345: 05/08/16: Re: Peter Alfke's SPDT Switch Debouncer
88380: 05/08/17: Re: Antti's last comp.arch.fpga posting
88418: 05/08/18: Re: super fast divide-by-N
88426: 05/08/18: Re: super fast divide-by-N
88833: 05/08/30: Re: CPLD Jitter
88835: 05/08/30: Re: Best FPGA for floating point performance
88838: 05/08/30: Re: Array of slope A/Ds in FPGA?
89024: 05/09/03: Re: gal16v8 CUPL problems
89030: 05/09/03: Re: CPLD CoolRunner-II - IO current limited to 8mA?
89046: 05/09/04: Re: High baud rate chips for RS232 protocol
89075: 05/09/05: Re: I2C "SCL" line problem
89164: 05/09/07: Re: Cyclone conf flash - 25p10 !
89197: 05/09/08: Re: Cyclone conf flash - 25p10 !
89238: 05/09/09: Re: Cyclone conf flash - 25p10 !
89366: 05/09/14: Re: Reading a PAL fusemap with a microscope
89368: 05/09/14: Re: 24 Counters on one board
89380: 05/09/14: Re: Is a CPLD appropriate for this triple PWM application?
89423: 05/09/15: Re: Is a CPLD appropriate for this triple PWM application?
89469: 05/09/16: Re: Is a CPLD appropriate for this triple PWM application?
89540: 05/09/19: Re: Reading a PAL fusemap with a microscope
89569: 05/09/20: Re: Is a CPLD appropriate for this triple PWM application?
89757: 05/09/25: Re: Question on Metastability
89791: 05/09/27: Re: Question on Metastability
89796: 05/09/27: Re: Question on Metastability
89845: 05/09/28: Re: Small C Compiler for Picoblaze
89917: 05/09/30: Re: Antti is back
90311: 05/10/10: Re: 16-bit microprocessor dore for Actel
90346: 05/10/11: Re: Virtex-4 FX20 PPC405 Startup Issue
90466: 05/10/14: Re: Distributed microcontroller computing
90493: 05/10/15: Re: How to Reduce Interconnects (VDD and VSS)
90546: 05/10/17: Re: Best Async FIFO Implementation
90552: 05/10/17: Re: Best Async FIFO Implementation
90567: 05/10/17: Re: ADC implementation on fpga? Information and procudures wanted.
90594: 05/10/18: Re: ADC implementation on fpga? Information and procudures wanted.
90595: 05/10/18: Re: Best Async FIFO Implementation
90599: 05/10/18: Re: Best Async FIFO Implementation
90603: 05/10/18: Re: Best Async FIFO Implementation
90629: 05/10/18: Re: Newbie question: XC3S400 Gate Count
90727: 05/10/20: Re: which is Low power FPGA?
90763: 05/10/21: Re: which is Low power FPGA?
90781: 05/10/21: Re: MAC Architectures
90881: 05/10/25: Re: SoC Processor design at gate level for edu
90990: 05/10/27: Re: state machine with 2 clock's
91041: 05/10/28: Re: another FPGA/asic vendor dead :(
91047: 05/10/28: Re: another FPGA/asic vendor dead :(
91048: 05/10/28: Re: another FPGA/asic vendor dead :(
91053: 05/10/28: Re: another FPGA/asic vendor dead :(
91055: 05/10/28: Re: 24 to 32 8-bit PWM outputs
91076: 05/10/29: Re: Cost to go from FPGA to ASIC
91131: 05/10/31: Re: ISE 8.1, EDK 8.1 any pre-release info available?
91160: 05/11/01: Re: Sigma-Delta A/D
91176: 05/11/01: Re: Sigma-Delta A/D
91177: 05/11/01: Re: Spartan-3E starter kit
91216: 05/11/02: Re: Antti's Logic Assembler ( was Spartan-3E starter kit )
91292: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91297: 05/11/03: Re: Xilinx trouble opening ml40x_emb_ref_xx
91298: 05/11/03: Re: Xilinx trouble opening ml40x_emb_ref_xx
91309: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91333: 05/11/04: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91345: 05/11/04: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91347: 05/11/04: Re: Spartan-3E starter kit
91391: 05/11/05: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91398: 05/11/05: Re: Spartan-3E starter kit
91431: 05/11/07: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91441: 05/11/07: Re: Why Spartan-3e is the best
91606: 05/11/10: Re: Best Case Timing Parameters
91681: 05/11/11: Re: fpga speed logic/density MIPS/FLOPS as compared to general purpose
91694: 05/11/11: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
91705: 05/11/11: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
91715: 05/11/11: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
91716: 05/11/11: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
91906: 05/11/17: Re: RoHS
91907: 05/11/17: Re: Rise time/fall time for Spartan3 clock inputs
92197: 05/11/24: Re: Case expression?
92251: 05/11/25: Re: XC2000
92264: 05/11/25: Re: FPGA ARM IP Core
92325: 05/11/28: Re: Virtex 4 Tapped Delay Lines
92427: 05/11/30: Re: Slow FIFO using external SRAM
92504: 05/12/01: Re: Virtex 4 Tapped Delay Lines
92678: 05/12/05: Re: Power Optimization NetSeminar: Wedesday, Dec. 7 at 11 am PST
92732: 05/12/06: Re: Is it legal to write an logical equation for a FPGA LUT in claims
92785: 05/12/07: Re: ISE 8.1 release delayed?
92841: 05/12/08: Re: I2C controller chipset to interface with FPGA
92846: 05/12/08: Re: I2C controller chipset to interface with FPGA
92890: 05/12/09: Re: I2C controller chipset to interface with FPGA
92893: 05/12/09: Re: I2C controller chipset to interface with FPGA
93002: 05/12/12: Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA,
93059: 05/12/13: Re: mixed signal flash FPGAs launched!
93095: 05/12/14: Re: Future of Microchip Development Tools?
93164: 05/12/15: Re: Hello PPl, is there a way of locking a design (NGC) to a particular
93372: 05/12/21: Re: Patents and (possible) Plagiarism, Anyone ever been in a similarsituation?
93417: 05/12/22: Re: Place and Route Algorithms
93440: 05/12/22: Re: Place and Route Algorithms: where's the fat?
93443: 05/12/22: Xilinbx Online store XC2C32A, XC2C64A missing ?
93474: 05/12/23: Re: Going insane - Xilinx VGA controller...
93479: 05/12/23: Re: Place and Route Algorithms: where's the fat?
93480: 05/12/23: Re: Place and Route Algorithms: where's the fat?
93798: 05/12/31: Re: Power Optimization: can the routing and placement really save
93799: 05/12/31: Re: Power Optimization: can the routing and placement really save
93822: 06/01/01: Re: Brute Force Examination of a PLD
93963: 06/01/04: Re: RTL for Z8000 series CPU?
94063: 06/01/05: Re: Xilinx new year Puzzle: binary counter 0,5,2,3,4,1,6,7...
94040: 06/01/05: Re: [ANNOUNCE] MyHDL 0.5 released
94116: 06/01/06: Re: [ANNOUNCE] MyHDL 0.5 released
94037: 06/01/05: Re: Schematic Entry, Xilinx or Altera?
94041: 06/01/05: Re: Schematic Entry, Xilinx or Altera?
94048: 06/01/05: Re: Schematic Entry, Xilinx or Altera?
94128: 06/01/06: Re: Schematic Entry, Xilinx or Altera?
94104: 06/01/06: Re: What kind of cpu is suit for me?
94105: 06/01/06: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94125: 06/01/06: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94197: 06/01/07: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94321: 06/01/10: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94208: 06/01/08: Re: FPGA -> ASIC`
94324: 06/01/10: Re: "failed to create empty document"
94812: 06/01/18: Re: Samples
94500: 06/01/13: Re: DSP soft processors
94632: 06/01/15: Re: DSP soft processors
94498: 06/01/13: Re: FPGA Journal Article
94647: 06/01/16: Re: FPGA Journal Article
94651: 06/01/16: Re: FPGA Journal Article
94720: 06/01/17: Re: FPGA Journal Article
94588: 06/01/14: Re: OT: RoHS and Lead?
94611: 06/01/14: Re: OT: RoHS and Lead?
94586: 06/01/14: Re: Attack of the clones
94630: 06/01/15: Re: Caution, Rant follows
94633: 06/01/15: Re: Caution, Rant follows
94786: 06/01/18: Re: Just want to program Xilinx CPLD device from JEDEC file using
94873: 06/01/19: Re: Selling Microblaze based Machines
94875: 06/01/19: Re: clock generation with DOPPLER shift
94959: 06/01/20: Re: Xilinx padding LC numbers, how do you feel about it?
94983: 06/01/20: Re: Quadrature Encoder ::
94990: 06/01/20: Re: Quadrature Encoder ::
95093: 06/01/21: Re: Just want to program Xilinx CPLD device from JEDEC file usingISE8.1
95569: 06/01/25: Re: Creating Multiple Configuration PROM File
95615: 06/01/25: Re: Creating Multiple Configuration PROM File
95455: 06/01/24: Re: Reconfigurable Array of Array
95461: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
95497: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
95756: 06/01/26: Re: Xilinx padding LC numbers, how do you really feel about it?
95617: 06/01/25: Re: Xilinx padding LC numbers, how do you really feel about it?
95534: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
95485: 06/01/24: =?ISO-8859-1?Q?Re=3A_obtaining_ABEL_code_from_schemati?=
95537: 06/01/24: Re: ISE8.1 Service Packs Schedule
95643: 06/01/25: Re: help:dual-edge flip-flop possible using Verilog?
95740: 06/01/26: Re: help:dual-edge flip-flop possible using Verilog?
95775: 06/01/26: Re: help:dual-edge flip-flop possible using Verilog?
95757: 06/01/26: Re: So what happened to JHDLBits?
95895: 06/01/27: Re: So what happened to JHDLBits?
95898: 06/01/27: Re: Spartan-3 Starter Board
95796: 06/01/26: Re: Stop. Go. Yield.
95892: 06/01/27: Re: So Xilinx, is XDL and related libraries an available open source
96011: 06/01/28: Re: Impact 8.1 problems with non xilinx device in chain
96012: 06/01/28: Re: Lattice high end FPGAs to be announced soon
96108: 06/01/31: Re: Xilinx Legal
96287: 06/02/02: Re: Back to max thermal and power for XC4VLX200's
96299: 06/02/02: Re: Back to max thermal and power for XC4VLX200's
96298: 06/02/02: Re: Back to max thermal and power for XC4VLX200's
96310: 06/02/02: Re: Back to max thermal and power for XC4VLX200's
96312: 06/02/02: Re: Back to max thermal and power for XC4VLX200's
96332: 06/02/02: Re: Back to max thermal and power for XC4VLX200's
96360: 06/02/03: Re: Die Area
96333: 06/02/02: Re: Spartan3 pullups
96387: 06/02/03: Re: BGA central ground matrix
96439: 06/02/04: Re: BGA central ground matrix
96442: 06/02/04: Re: BGA central ground matrix
96574: 06/02/07: Re: BGA central ground matrix
96663: 06/02/09: Re: MicroBlaze in Spartan 3 playing tuxchess :)
96664: 06/02/09: Re: MicroBlaze in Spartan 3 playing tuxchess :)
96676: 06/02/09: Async Processors
96677: 06/02/09: Re: NMEA Decoder/Display
96691: 06/02/09: Re: Async Processors
96702: 06/02/09: Re: BGA central ground matrix
96703: 06/02/09: Re: BGA central ground matrix
96736: 06/02/10: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest
96743: 06/02/10: Re: Async Processors
96753: 06/02/10: Re: Async Processors
96755: 06/02/10: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest
96797: 06/02/11: Re: Async Processors
96818: 06/02/11: Re: Async Processors
96824: 06/02/11: Re: Altera EPLD
96846: 06/02/12: Re: Async Processors
96875: 06/02/13: Re: Microblaze using SPI flash as instruction memory
96886: 06/02/13: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest
96926: 06/02/14: Re: Altera RoHS Irony
96946: 06/02/14: Re: I2C and posedge sampling
97005: 06/02/15: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
97021: 06/02/15: Re: Altera RoHS Irony
97127: 06/02/17: Maxim anounce MAX3421E SPI-USB Host/Peri
97131: 06/02/17: Re: User masks in HardCopy and HardCopy II
97393: 06/02/22: Re: FPGA - software or hardware -2-
97398: 06/02/22: Re: Is FPGA code called gateware?
97412: 06/02/22: Re: Is FPGA code called gateware?
97466: 06/02/23: Re: Input stage for VHF frequency counter in an FPGA?
97531: 06/02/24: Re: News from Embedded World in Nurnber
97548: 06/02/24: Re: 8051 IP core with JTAG debugger for FPGA?
97678: 06/02/26: Re: fpga to 5v ttl logic
97718: 06/02/27: Re: fpga to 5v ttl logic
97777: 06/02/28: Re: The 95108 cpld is getting heated when connected by CRO
97778: 06/02/28: Re: fpga to 5v ttl logic
97783: 06/02/28: Re: tricks to make large PLAs fast?
97804: 06/02/28: Re: tricks to make large PLAs fast?
97812: 06/02/28: Re: tricks to make large PLAs fast?
97861: 06/03/01: Re: FPGA communication, I2C and DAC
97864: 06/03/01: Re: tricks to make large PLAs fast?
97905: 06/03/02: Re: problem with ISE versions
97913: 06/03/02: Re: fpga to 5v ttl logic
97925: 06/03/02: Re: Pulse Shape in a functional simulation
98118: 06/03/06: Re: why use an FPGA when a CPLD will do ??
98174: 06/03/07: Re: Pullup questions on Spartan3
98253: 06/03/08: Re: Questions about counter in VHDL
98343: 06/03/09: Re: for all those who believe in ASICs....
98350: 06/03/09: Re: Questions about counter in VHDL
98352: 06/03/09: Re: for all those who believe in ASICs....
98417: 06/03/10: Re: a problem with coolrunner CPLD (XC2C256) GCK0 pin
98420: 06/03/10: Re: a problem with coolrunner CPLD (XC2C256) GCK0 pin
98427: 06/03/10: Re: for all those who believe in ASICs....
98428: 06/03/10: Re: for all those who believe in ASICs....
98462: 06/03/11: Re: for all those who believe in ASICs....
98465: 06/03/11: Re: a problem with coolrunner CPLD (XC2C256) GCK0 pin
98476: 06/03/11: Re: for all those who believe in ASICs....
98483: 06/03/11: Re: for all those who believe in ASICs....
98485: 06/03/11: Re: for all those who believe in ASICs....
98496: 06/03/11: Re: for all those who believe in ASICs....
98538: 06/03/13: Re: fpga to 5v ttl logic
98539: 06/03/13: Re:Low Icc FPGAs
98540: 06/03/13: Re: Low Icc FPGAs
98554: 06/03/13: Re: Combinatorial Division?
98620: 06/03/14: Re: Why does Xilinx hate version control?
98635: 06/03/14: Re: Why does Xilinx hate version control?
98686: 06/03/15: Re: Why Xilinx does not specify clock to output MINIMUM time???
98694: 06/03/15: Re: fpga to 5v ttl logic
98698: 06/03/15: Re: Why does Xilinx hate version control?
98705: 06/03/15: Re: Why does Xilinx hate version control?
98751: 06/03/16: Re: fpga to 5v ttl logic
98752: 06/03/16: Re: fpga to 5v ttl logic
98759: 06/03/16: Re: CoolRunner 2 CPLD
98800: 06/03/17: Re: for all those who believe in ASICs....
98802: 06/03/17: Re: Where are FPGA heading?
98828: 06/03/17: Re: Where are FPGA heading?
98902: 06/03/18: Re: for all those who believe in ASICs....
98920: 06/03/18: Re: Where are FPGA heading?
98922: 06/03/18: Re: fpga to 5v ttl logic
98961: 06/03/18: Re:Disk/LCD defect tolerant models for FPGA sales
99018: 06/03/19: Re: Disk/LCD defect tolerant models for FPGA sales
99058: 06/03/20: Re: for all those who have stopped listening, and are ranting now...
99142: 06/03/21: Re: PacoBlaze with multiply and 16-bit add/sub instructions
99158: 06/03/21: Re: PacoBlaze with multiply and 16-bit add/sub instructions
99159: 06/03/21: Re: PacoBlaze with multiply and 16-bit add/sub instructions
99161: 06/03/21: Re: Disk/LCD defect tolerant models for FPGA sales
99167: 06/03/21: Re: Disk/LCD defect tolerant models for FPGA sales
99221: 06/03/22: Re: for all those who believe in ASICs....
99240: 06/03/22: Smarter Power supplies arrive
99249: 06/03/22: Re: OpenSPARC released
99304: 06/03/23: Re: this JTAG thing is a joke
99381: 06/03/24: Re: this JTAG thing is a joke
99386: 06/03/24: Re: for all those who believe in ASICs....
99395: 06/03/24: Re: this JTAG thing is a joke
99405: 06/03/24: Re: for all those who believe in (structured) ASICs....
99406: 06/03/24: Re: Xilinx hi-speed interconnect/routing question
99416: 06/03/24: Re: this JTAG thing is a joke
99418: 06/03/24: Re: Xilinx hi-speed interconnect/routing question
99468: 06/03/25: Re: Lattice FPGA
99481: 06/03/25: Re: Lattice FPGA
99484: 06/03/25: Re: Xilinx hi-speed interconnect/routing question
99553: 06/03/27: Re: a problem with coolrunner CPLD (XC2C256) GCK0 pin
99570: 06/03/27: Re: Xilinx hi-speed interconnect/routing question
99585: 06/03/27: Re: Altera web site inaccessible
99602: 06/03/27: Re: Altera web site inaccessible
99637: 06/03/28: Re: Altera web site (in)accessible
99638: 06/03/28: Re: deglitching a clock
99659: 06/03/28: Re: deglitching a clock
99678: 06/03/28: Re: Microblaze using SPI flash as instruction memory
99739: 06/03/29: Re: Quartus Compiler as Quailty Check for WebPack
99831: 06/03/30: Re: deglitching a clock
99903: 06/03/31: Re: FpgaC developers wanted :)
99993: 06/04/01: Re: Atmel microcontroller
99994: 06/04/01: Re: deglitching a clock
100006: 06/04/01: Re: Atmel microcontroller
100066: 06/04/03: Re: Configuration pins on Spartan-3
100114: 06/04/04: Want HiSpeed USB on your FPGA ?
100169: 06/04/05: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan
100178: 06/04/05: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan
100197: 06/04/05: Re: interesting note -- altera C to hardware :)
100256: 06/04/06: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan
100259: 06/04/06: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan3
100266: 06/04/06: Re: LVDS in Cyclone-II
100279: 06/04/06: Re: LVDS in Cyclone-II
100330: 06/04/07: Re: USB Interface to Virtex-4
100331: 06/04/07: Re: Bizarre behaviour by Quartus?
100333: 06/04/07: Re: USB Interface to Virtex-4
100424: 06/04/09: Re: Compiler to FPSLIC
100450: 06/04/10: Re: Compiler to FPSLIC
100451: 06/04/10: Re: Compiler to FPSLIC
100452: 06/04/10: Re: Compiler to FPSLIC
100507: 06/04/11: Re: C-Compiler for free VHDL controller core ?
100517: 06/04/11: Re: Configuration Rate with multiple .bit files
100518: 06/04/11: Re: Configuration Rate with multiple .bit files
100520: 06/04/11: Re: very slow pull-up with CPLD design
100555: 06/04/12: Re: State Machine and Area Estimate Question
100618: 06/04/14: Re: Spartan3E readback, SPI programming
100657: 06/04/15: Re: humble suggestion for Xilinx
100665: 06/04/15: Re: humble suggestion for Xilinx
100679: 06/04/16: Re: Spartan 3 chips in power up
100682: 06/04/16: Re: Where is the xilinx online store gone?
100683: 06/04/16: Re: Where is the xilinx online store gone?
100684: 06/04/16: Re: Where is the xilinx online store gone?
100748: 06/04/18: Re: PLD610
100750: 06/04/18: Re: Which is the best way to measure low frequencies?
100835: 06/04/19: Re: PLD610
101118: 06/04/26: Re: Heating problem of the CPLD
101121: 06/04/26: Re: Simulated Quartus II delays are much greater than measured
101122: 06/04/26: Async FPGA ~2GHz
101126: 06/04/26: Re: Async FPGA ~2GHz
101154: 06/04/27: Re: Async FPGA ~2GHz
101157: 06/04/27: Re: Async FPGA ~2GHz
101172: 06/04/27: Re: Async FPGA ~2GHz
101179: 06/04/27: Re: The use of analog switches as level translators
101180: 06/04/27: Re: Picoblaze C Compiler
101185: 06/04/27: Re: Async FPGA ~2GHz
101229: 06/04/28: Re: LED Driver
101231: 06/04/28: Re: Picoblaze C Compiler
101251: 06/04/28: Re: LED Driver
101253: 06/04/28: Re: Async FPGA ~2GHz
101317: 06/04/29: Re: Xilinix SPI programming with USB Platform Cable
101322: 06/04/29: Re: Pull up resistors on Spartan 3 mode pins
101329: 06/04/29: Re: Working Altera USB-Blaster compatible design published underGPL
101377: 06/04/30: Re: Pull up resistors on Spartan 3 mode pins
101384: 06/04/30: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101387: 06/04/30: Re: Pull up resistors on Spartan 3 mode pins
101388: 06/04/30: Re: Pull up resistors on Spartan 3 mode pins
101413: 06/05/01: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101414: 06/05/01: Re: design optimization
101428: 06/05/01: Re: Pull up resistors on Spartan 3 mode pins
101469: 06/05/02: Re: Async FPGA ~2GHz
101470: 06/05/02: Re: ISE 8.1 Comment Bug, Very hideous
101478: 06/05/02: Re: Async FPGA ~2GHz
101541: 06/05/03: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
101543: 06/05/03: Re: bizzare unexplained random errors w/ Lattice 4256V CPLD
101547: 06/05/03: Re: ISE 8.1 Comment Bug, Very hideous
101569: 06/05/03: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
101606: 06/05/04: Re: Measuring Light with LED and FPGA
101613: 06/05/04: Re: Interfacing Spartan 3 board to PC parallel port??
101614: 06/05/04: Re: Unreactive Output Pins on Xilinx Virtex-II
101621: 06/05/04: Re: Measuring Light with LED and FPGA
101632: 06/05/04: Re: Interfacing Spartan 3 board to PC parallel port??
101678: 06/05/05: Re: 87C52 & 87C51 core
101694: 06/05/05: Re: LVDS inputs on Cyclone II
101695: 06/05/05: Re: LVDS inputs on Cyclone II
101705: 06/05/05: Re: LVDS inputs on Cyclone II
101758: 06/05/06: Re: Xilinx SelectMAP Question
101802: 06/05/07: Re: Spartan 3e starter kit & Multimedia
101809: 06/05/07: Re: Measuring Light with LED and FPGA
101811: 06/05/07: Re: flashing a led
101838: 06/05/08: Re: Funky experiment on a Spartan II FPGA
101840: 06/05/08: Re: Xilinx 3s8000?
101843: 06/05/08: Re: Funky experiment on a Spartan II FPGA
101845: 06/05/08: Re: Funky experiment on a Spartan II FPGA
101854: 06/05/08: Re: Xilinx 3s8000?
101933: 06/05/09: Putting the Ring into Ring oscillators
101934: 06/05/09: Re: Can an FPGA be operated reliably in a car wheel?
101962: 06/05/09: Re: Xilinx 3s8000?
101964: 06/05/09: Re: Xilinx 3s8000?
101974: 06/05/09: Re: Xilinx 3s8000?
101975: 06/05/09: Re: Putting the Ring into Ring oscillators
102017: 06/05/10: Re: Putting the Ring into Ring oscillators
102047: 06/05/10: Re: Superscalar Out-of-Order Processor on an FPGA
102112: 06/05/11: Re: CoolRunner XPLA3 getting axed?
102113: 06/05/11: Re: CoolRunner XPLA3 getting axed?
102114: 06/05/11: Re: Altera Equiv.
102121: 06/05/11: Re: Superscalar Out-of-Order Processor on an FPGA
102123: 06/05/11: Re: CoolRunner XPLA3 getting axed?
102127: 06/05/11: Re: CoolRunner XPLA3 thriving for many years to come
102144: 06/05/11: Re: Interrupt signal sampling (Level or edge?)
102219: 06/05/12: Re: reverse engineering ?
102379: 06/05/16: Re: Virtex 5 announced
102381: 06/05/16: Re: Virtex 5 announced and sampling ... and real!
102396: 06/05/16: Re: Power for Spartan 3
102398: 06/05/16: Re: Virtex 5 announced and sampling
102404: 06/05/16: Re: Virtex 5 announced and sampling ... and real!
102410: 06/05/16: Re: Virtex 5 announced and sampling
102466: 06/05/17: Re: Actel Fusion FPGAs
102467: 06/05/17: Re: Actel Fusion FPGAs
102575: 06/05/18: Re: disappointing 550Mhz performance of V5 DSP slices
102613: 06/05/18: Re: Make a signal free for glitches?
102630: 06/05/18: Re: ADC implementation on FPGA ?
102666: 06/05/19: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
102751: 06/05/20: Re: CPLD (CoolRunner failures)
102769: 06/05/20: Re: CPLD (CoolRunner failures)
102789: 06/05/21: Re: Why do the electronics manufacturers have to spam me?
102791: 06/05/21: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
102797: 06/05/21: Re: CPLD (CoolRunner failures)
102802: 06/05/21: Re: CPLD (CoolRunner failures)
102888: 06/05/23: Re: CPLD (CoolRunner failures)
102937: 06/05/24: Re: ISE 8.1SP4 PN doesnt start
103028: 06/05/25: Re: Most expensive 8051 in DIP40? here on my desk, labelled Virtex-4
103038: 06/05/25: Re: ISE 8.1SP4 PN doesnt start
103118: 06/05/26: Re: ISE sends sensitive information to Xilinx site!
103119: 06/05/26: Re: ISE sends sensitive information to Xilinx site!
103120: 06/05/26: Re: Remote Application delivery for EDA
103128: 06/05/26: Re: ISE sends sensitive information to Xilinx site!
103171: 06/05/27: Potential of the CELL Processor for Scientific Computing
103178: 06/05/27: Re: ISE sends sensitive information to Xilinx site!------ Only if
103256: 06/05/30: Re: Fast Serial I/O on Virtex-5
103315: 06/05/31: Re: Virtex 5 announced and sampling ... and real!
103323: 06/05/31: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103427: 06/06/02: Re: clockless arbiters on fpgas?
103613: 06/06/07: Re: Who's dying?
103617: 06/06/07: Re: Who's dying?
103661: 06/06/08: Re: Who's dying?
103670: 06/06/08: Re: STOP IT :)
103677: 06/06/08: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
103687: 06/06/08: Re: IOBDELAY's delay value
103699: 06/06/09: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
103771: 06/06/11: Re: Anyone with Xilinx SP305-board ?
103822: 06/06/13: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
103834: 06/06/13: Re: Looking for patent attorney specialized in programmable logic
103917: 06/06/15: Re: Time for a new "Largest FPGA with free tool support"?
103945: 06/06/16: Re: ARM cores in FPGA ?
103956: 06/06/16: Re: How to get lowest price for a ModelSim license?
103963: 06/06/16: Re: XPLA3 bidirectional bus
103973: 06/06/16: Re: ARM cores in FPGA ?
104026: 06/06/17: Re: Time for a new "Largest FPGA with free tool support"?
104035: 06/06/17: Re: Anyone get a Pictiva OLED to work?
104036: 06/06/17: Re: Anyone get a Pictiva OLED to work?
104179: 06/06/21: Re: FSM State Minimization on FPGAs
104182: 06/06/21: Re: FSM State Minimization on FPGAs
104293: 06/06/23: Re: keys to the Kingdom
104295: 06/06/23: Re: keys to the Kingdom
104324: 06/06/24: Re: keys to the Kingdom
104393: 06/06/27: Re: PicoBlaze and DDR Ram
104403: 06/06/27: Re: ISE WebPack 8.2
104489: 06/06/29: Re: Preserve patent materials through a notary
104522: 06/06/29: Re: keys to the Kingdom
104562: 06/06/30: Re: How to evaluate the space efficiency of a historic design.
104563: 06/06/30: Re: Stopping the clock for power management
104671: 06/07/04: Re: Chaos in FF metastability
104771: 06/07/06: Re: Chaos in FF metastability
104813: 06/07/07: Re: Chaos in FF metastability
104814: 06/07/07: Re: debouncing a switch (in hardware)
104827: 06/07/07: Re: Chaos in FF metastability
104832: 06/07/07: Re: debouncing a switch (in hardware)
104837: 06/07/07: Re: debouncing a switch (in hardware)
104875: 06/07/08: Re: Chaos in FF metastability
105202: 06/07/18: Re: ISE 8.2 WebPack does not support Virtex-5 at all?
105216: 06/07/18: Re: 2048 input or gate ?
105245: 06/07/19: Re: JED file translator
105252: 06/07/19: Re: ISE 8.2 - time to crash 20 minutes
105256: 06/07/19: Re: ISE 8.2 - time to crash 20 minutes
105301: 06/07/20: Re: corrupted data when accessing dual port bram in Cyclone II
105354: 06/07/21: Re: Virtex-5: SoftCore processors at 200MHz !
105373: 06/07/21: Re: Virtex-5: SoftCore processors at 200MHz !
105438: 06/07/23: Re: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
105550: 06/07/26: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105557: 06/07/26: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105595: 06/07/27: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105598: 06/07/27: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105638: 06/07/28: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105649: 06/07/28: Re: Guided MAP/PAR in ISE
105782: 06/08/01: Re: 100m JTAG cable
105838: 06/08/02: Re: 100m JTAG cable
105846: 06/08/02: Re: 100m JTAG cable
105854: 06/08/02: Re: Programmable pulse generator
105856: 06/08/02: Re: 100m JTAG cable
105870: 06/08/02: Re: Programmable pulse generator
105921: 06/08/03: Re: generating sine-like waveforms
106117: 06/08/08: Re: Microblaze, EDK, Spartan 3 and Webpack
106182: 06/08/09: Re: 100 Mbit manchester coded signal in FPGA
106183: 06/08/09: Re: 100 Mbit manchester coded signal in FPGA
106184: 06/08/09: Re: 100 Mbit manchester coded signal in FPGA
106211: 06/08/09: Re: 100 Mbit manchester coded signal in FPGA
106324: 06/08/12: Re: (uc)Linux support for Xilinx FPGAs is going to next level
106326: 06/08/12: Re: Embedded clocks
106332: 06/08/12: Re: Embedded clocks
106390: 06/08/13: Re: Embedded clocks
106406: 06/08/13: Re: Embedded clocks
106410: 06/08/13: Re: Embedded clocks
106419: 06/08/13: Re: Maximum Current Draw of FPGA
106449: 06/08/14: Re: Embedded clocks
106450: 06/08/14: Re: Embedded clocks
106461: 06/08/14: Re: Embedded clocks
106471: 06/08/14: Re: Embedded clocks
106478: 06/08/14: Re: Embedded clocks
106517: 06/08/15: Re: Embedded clocks
106518: 06/08/15: Re: Crystal input for FPGA
106521: 06/08/15: Re: Crystal input for FPGA
106524: 06/08/15: Re: Crystal input for FPGA
106535: 06/08/15: Re: Embedded clocks
106646: 06/08/17: Re: Simple state machine in CUPAL
106669: 06/08/17: Re: Simple state machine in CUPAL
106681: 06/08/17: Re: Simple state machine in CUPAL
106722: 06/08/18: Re: S3 starter kit, command-line
106741: 06/08/18: Re: Simple state machine in CUPAL
106744: 06/08/18: Re: Using an FPGA as USB HOST without PHY
106799: 06/08/20: Re: S3 starter kit, command-line
106803: 06/08/20: Re: S3 starter kit, command-line
106829: 06/08/21: Re: CPU design
106835: 06/08/21: Re: CPU design
106841: 06/08/21: Re: CPU design
106874: 06/08/22: Re: CPU design
106877: 06/08/22: Re: CPU design
106932: 06/08/23: Re: CPU design
106934: 06/08/23: Re: CPU design
106946: 06/08/23: Re: Running DDR below the min frequency
106950: 06/08/23: Re: CPU design
107025: 06/08/24: Re: CPU design
107116: 06/08/25: Re: Why No Process Shrink On Prior FPGA Devices ?
107150: 06/08/25: Re: fastest FPGA
107165: 06/08/25: Re: fastest FPGA
107263: 06/08/26: Re: fastest FPGA
107268: 06/08/26: Re: FPGA -> SATA?
107270: 06/08/26: Re: fastest FPGA
107286: 06/08/26: Re: fastest FPGA
107335: 06/08/27: Re: What is the truth about the Virtex5 ?
107336: 06/08/27: Re: fastest FPGA
107339: 06/08/27: Re: fastest FPGA
107416: 06/08/28: Re: Spartan-4 ?
107458: 06/08/29: Re: Spartan-4 ? - Igloo ?
107522: 06/08/30: Re: Undergrad project-8051 specifications??
107527: 06/08/30: Re: placing addiional caps across existing caps to reduce noise
107528: 06/08/30: Re: placing addiional caps across existing caps to reduce noise
107530: 06/08/30: Re: CPU design
107575: 06/08/30: Re: Spartan-4 ?
107903: 06/09/02: Re: Higher voltages input, quick check....
107906: 06/09/02: Re: Higher voltages input, quick check....
107908: 06/09/02: Re: Higher voltages input, quick check....
107937: 06/09/03: Re: Impossible to download WebPACK?
107942: 06/09/03: Re: Forth-CPU design
107954: 06/09/03: Re: Forth-CPU design
107996: 06/09/04: Re: Here are the URLs (was Re: Impossible to download WebPACK?)
108005: 06/09/04: Re: Forth-CPU design
108083: 06/09/05: Re: Forth-CPU design
108212: 06/09/07: Re: Forth-CPU design
108375: 06/09/10: Re: Can a FPGA work like a microprocessor ?
108540: 06/09/13: Re: Spartan-3: 5V -> 2.5V level shifting
108549: 06/09/13: Re: Spartan-3: 5V -> 2.5V level shifting
108568: 06/09/13: Re: SoC Development Board
108673: 06/09/15: Re: Spartan3 driving mosfets
108751: 06/09/16: Re: XIlinx Spartan 2E stuck in configuration mode
108752: 06/09/16: Re: Spartan3 driving mosfets
108757: 06/09/16: Re: XIlinx Spartan 2E stuck in configuration mode
108791: 06/09/17: Re: XIlinx Spartan 2E stuck in configuration mode
108792: 06/09/17: Re: XPLA3 going obsolete?
108798: 06/09/17: Re: XIlinx Spartan 2E stuck in configuration mode
108823: 06/09/18: Re: XIlinx Spartan 2E stuck in configuration mode
108882: 06/09/19: Re: New Lattice 32-bit Embedded Microprocessor Available Through
108885: 06/09/19: Re: Virtex4 Configuration ROM?
109554: 06/09/29: Re: Driving a 30 bit wide LVTTL bus at 160MHz
109947: 06/10/09: Re: An implementation of a clean reset signal
109963: 06/10/09: Re: Antifuse, lower cost?
109964: 06/10/09: Re: Spartan3A - internal flash configuration or not?
110010: 06/10/10: Re: Just a matter of time
110030: 06/10/10: Re: An implementation of a clean reset signal
110098: 06/10/11: Re: Antifuse, lower cost?
110162: 06/10/12: Re: Antifuse, lower cost?
110169: 06/10/12: Re: longest webcase record -- understandably so
110204: 06/10/12: Re: longest webcase record -- understandably so
110246: 06/10/13: Re: longest webcase record -- understandably so
110279: 06/10/13: Re: Last ISE version that supports XC95xxXL ?
110387: 06/10/15: Re: Xilinx FPGAs in battery-powered scenarios
110400: 06/10/15: Re: Xilinx FPGAs in battery-powered scenarios
110436: 06/10/16: Re: how to change cclk frequency ?
110438: 06/10/16: Re: Xilinx FPGAs in battery-powered scenarios
110453: 06/10/16: Re: virtex-5 sysmon, really nice to monitor supply and temp
111041: 06/10/28: Re: Survey: simulator usage
111055: 06/10/28: Re: A pre-emptive strike against blaming the chip
111061: 06/10/28: Re: A pre-emptive strike against blaming the chip
111068: 06/10/28: Re: Survey on Quartus SOPC/Nios-II
111093: 06/10/29: Re: Survey on Quartus SOPC/Nios-II
111120: 06/10/30: Re: Survey: simulator usage
111172: 06/10/31: Re: On the Futility of Documentation Webcases ( Was: Xilinx documentation
111189: 06/10/31: Re: How stable is the internal clock of a Xilinx CPLD?
111281: 06/11/01: Re: Dual Port RAM
111402: 06/11/03: Re: Spectre of Metastability Update
111420: 06/11/03: Re: Need just a few 5V Spartan
111432: 06/11/03: Re: Spectre of Metastability Update
111487: 06/11/04: Re: Spectre of Metastability Update
111490: 06/11/04: Re: Spectre of Metastability Update
111497: 06/11/04: Re: Spectre of Metastability Update
111528: 06/11/05: Re: Spectre of Metastability Update
111606: 06/11/07: Re: Spectre of Metastability Update
111827: 06/11/11: Re: Stratix-III announced
111864: 06/11/12: Re: Stratix-III announced
111912: 06/11/13: Re: Stratix-III announced
111913: 06/11/13: Re: Stratix-III announced
111915: 06/11/13: Re: Stratix-III announced
112076: 06/11/16: Re: 8080 FSGA model in an FPGA
112077: 06/11/16: Re: how to filter glitches and mutliple transitions?
112087: 06/11/16: Re: 8080 FSGA model in an FPGA
112138: 06/11/17: Re: Warnings in Xilinx 8.2i
112154: 06/11/17: Re: combinatorical divide by 2 in FPGA
112217: 06/11/18: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112257: 06/11/19: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112263: 06/11/19: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112274: 06/11/19: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112292: 06/11/20: Re: board - T562.jpg
112646: 06/11/27: Re: run a counter without a clock
112703: 06/11/28: Re: run a counter without a clock
112753: 06/11/29: Re: run a counter without a clock
112895: 06/12/01: Re: FPGA application field
113080: 06/12/06: Re: Altera starter kits
113120: 06/12/07: Re: Altera starter kits
113122: 06/12/07: Re: Spartan-3A launched
113136: 06/12/07: Re: Free Anydivider, Divide clock by any number
113292: 06/12/11: Re: approximation of an exponential ramp?
113397: 06/12/13: Re: Tarfessock1
113460: 06/12/14: Re: what are your current SoC design for ?
113493: 06/12/15: Re: abel to vhdl converter
113644: 06/12/19: Re: solder mask for fpga dissipation
113693: 06/12/20: Re: ANN: PicoBlaze C: compile to bitstream!
113806: 06/12/23: Re: Virtex-5 Webpack?
113809: 06/12/23: Re: Virtex-5 Webpack?
115082: 07/01/31: Re: 1 Gbps - state of the art?
115336: 07/02/08: Re: question about power dissipation
115451: 07/02/12: Re: CLOCK GENERATOR
115456: 07/02/12: Re: Weird problem with WP 9.1sp1 and XC95144XL
115514: 07/02/13: Re: Which is your favorite FPGA language?
115526: 07/02/13: Re: Building Coaxial transmission line on PCB?
115556: 07/02/14: Re: Which is your favorite FPGA language?
115557: 07/02/14: Re: Typical clock frequencies of FPGA designs
115561: 07/02/14: Re: Building Coaxial transmission line on PCB?
115564: 07/02/14: Re: Typical clock frequencies of FPGA designs
115569: 07/02/14: Re: Typical clock frequencies of FPGA designs
115640: 07/02/16: Re: Need fair opinions on choosing either Altera or Xilinx as main
115643: 07/02/16: Re: Do you like Virtex-5 ?
115702: 07/02/17: Re: Do you like Virtex-5 ?
115732: 07/02/19: Re: Do you like Virtex-5 ?
115758: 07/02/20: Re: ACTEL ProAsic Plus
115832: 07/02/22: Re: Determine error in asynchronous signal
115837: 07/02/22: Re: Determine error in asynchronous signal
115844: 07/02/22: Re: Determine error in asynchronous signal
115847: 07/02/22: Re: Determine error in asynchronous signal
115878: 07/02/23: Re: Structured ASIC players
115881: 07/02/23: Re: Structured ASIC players
116001: 07/02/28: Re: Spartan-3AN
116057: 07/03/01: Re: what does a 'blank check' do exactly
116063: 07/03/01: Re: Spartan-3AN
116114: 07/03/02: Re: Bypass caps, X2Y and 'puddles'.
116121: 07/03/02: Re: what does a 'blank check' do exactly
116122: 07/03/02: Re: XC3S400 and XC3S500E in PQ208
116195: 07/03/05: Re: Large power planes vs. power islands vs. slits for decoupling
116201: 07/03/05: Re: Large power planes vs. power islands vs. slits for decoupling
116248: 07/03/06: Re: Large power planes vs. power islands vs. slits for decoupling
116258: 07/03/06: Re: Large power planes vs. power islands vs. slits for decoupling
116310: 07/03/07: Re: Ideas for Masters Project.
116351: 07/03/08: Re: Spartan3AN - Roadmap
116358: 07/03/08: Re: Spartan3AN - Roadmap
116368: 07/03/08: Re: Spartan3AN - Roadmap - bigger questions may prevail...
116427: 07/03/09: Re: Spartan3AN - Roadmap
116470: 07/03/10: Re: Xilin X-Fest Lunacy
116472: 07/03/10: Re: Spartan3AN - Roadmap
116497: 07/03/11: Re: Are FPGAs go enough for clock dstribution
116612: 07/03/14: Re: WTF? - Spartan-3E starter kit with no printed board manual?
116853: 07/03/20: Re: Altera introduces Cyclone III devices, ships 65nm
116902: 07/03/21: Re: FPGA with 5V and PLCC package
116912: 07/03/21: Re: FPGA with 5V and PLCC package
116914: 07/03/21: Re: softcore CPU tools
116918: 07/03/21: Re: Why is Xilinx's WebPACK so inferior?
116927: 07/03/21: Re: Why is Xilinx's WebPACK so inferior?
116934: 07/03/21: Re: Off topic: what is the purpoe of XST?
116994: 07/03/22: Re: FPGA with 5V and PLCC package
117003: 07/03/22: Re: FPGA with 5V and PLCC package
117005: 07/03/22: Re: softcore CPU tools
117008: 07/03/22: Re: Off topic: what is the purpoe of XST?
117026: 07/03/22: Re: FPGA with 5V and PLCC package
117027: 07/03/22: Re: Off topic: what is the purpoe of XST?
117082: 07/03/23: Re: FPGA with 5V and PLCC package
117089: 07/03/23: Re: Altera introduces Cyclone III devices, 'ships' 65nm
117092: 07/03/23: Re: Off topic: what is the purpoe of XST?
117148: 07/03/24: Re: FPGA with 5V and PLCC package
117173: 07/03/26: Re: Where is Open Source for FPGA development?
117178: 07/03/26: Re: Where is Open Source for FPGA development?
117239: 07/03/27: Re: Open-source CPU-core for standard-cell ASIC?
117240: 07/03/27: Re: Open-source CPU-core for standard-cell ASIC?
117286: 07/03/28: Re: Lattice "Open IP" license is GPL-compatible?
117381: 07/03/30: Re: FPGA with 5V and PLCC package
117388: 07/03/30: Re: RISC implementation questions
117394: 07/03/30: Re: RISC implementation questions
117448: 07/03/31: Re: Help with a face recognition system
117547: 07/04/04: Re: FPGA with 5V and PLCC package
117619: 07/04/05: Re: having a state machine in a datapath element a bad design practice?
118165: 07/04/19: Re: 80000 Bit Shift Register
118260: 07/04/21: Re: DARNAW! - PGA Style FPGA Module
118261: 07/04/21: Re: FPGA Newbie
118277: 07/04/21: Re: FPGA Newbie
118291: 07/04/23: Re: Lattice pricing
118310: 07/04/24: Re: FPGA Newbie
118324: 07/04/24: Re: Ouputs during startup and Programming
118518: 07/04/29: Re: physical chip size
118521: 07/04/29: Re: driving Spartan-3 input from 74LS TTL
118539: 07/04/30: Re: debounce state diagram FSM
118567: 07/04/30: Re: driving Spartan-3 input from 74LS TTL
118609: 07/05/01: Re: debounce state diagram FSM
118666: 07/05/02: Re: debounce state diagram FSM
118691: 07/05/02: Re: DDR2 with Spartan-3A anybody having success??
118858: 07/05/05: Re: Spartan 3A Starter Kit Multiboot Demo Config 4 Display Problem
118864: 07/05/05: Re: Atom HDL
118865: 07/05/05: Re: Select pullup, pulldown or none via embedded S/W
118866: 07/05/05: Re: Select pullup, pulldown or none via embedded S/W
118941: 07/05/08: Re: Help with ATF750CL and WinCUPL
118943: 07/05/08: Re: V5 LVPECL Inputs
118945: 07/05/08: Re: Xilinx software quality - how low can it go ?!
119029: 07/05/10: Re: An Open-Source suggestion for Xilinx
119034: 07/05/10: Re: An Open-Source suggestion for Xilinx
119108: 07/05/12: =?ISO-8859-1?Q?Re=3A_power_consumption_of_integrated_c?=
119136: 07/05/13: Re: driving Spartan-3 input from 74LS TTL
119185: 07/05/15: Re: An Open-Source suggestion for Xilinx
119186: 07/05/15: Re: Xilinx software quality - how low can it go ?!
119187: 07/05/15: Re: An Open-Source suggestion for Xilinx
119188: 07/05/15: Re: An Open-Source suggestion for Xilinx
119251: 07/05/16: Re: How low DDR2 Clock Frequency can be? To make it work on FPGA.
119263: 07/05/16: Re: Power Consumption near Timing Failure Point
119328: 07/05/17: Re: Power Consumption near Timing Failure Point
119329: 07/05/17: Re: how to delay a signal in virtex FPGA
119330: 07/05/17: Re: how to delay a signal in virtex FPGA
119443: 07/05/19: Re: releasing some FPGA tools-ip as open-source
119515: 07/05/22: Atmel release Metal Programmable Cell Fabric uC ARM9
119518: 07/05/22: Re: Atmel release Metal Programmable Cell Fabric uC ARM9
119575: 07/05/23: Re: LVCMOSS33 I/O sink current
119604: 07/05/24: Re: LVCMOSS33 I/O sink current
119635: 07/05/24: Re: Altera Cyclone II - used in 100USD Laptop
119639: 07/05/24: Re: 6502 and CPU licences in general
119651: 07/05/24: Re: 6502 and CPU licences in general
119704: 07/05/25: Re: Altera Cyclone II - used in 100USD Laptop
119790: 07/05/26: Re: low speed communication
119820: 07/05/27: Re: Spartan3 LVCMOS33 Slew rate
119824: 07/05/27: Re: 6502 FPGA core
119827: 07/05/27: Re: 6502 FPGA core
119841: 07/05/28: Re: 6502 FPGA core
119869: 07/05/29: Re: 6502 FPGA core
119875: 07/05/29: Re: 6502 FPGA core
119884: 07/05/29: Re: PacoBlaze 2.2
119936: 07/05/30: Re: PacoBlaze 2.2
120055: 07/06/01: Re: LVDS termination scheme to nonstandard ribbon cable
120105: 07/06/01: Re: Actel Cortex M1, any info on license fee?
120207: 07/06/04: Re: Microcontrollers have a better predictable time behaviour than
120283: 07/06/05: Re: Lattice XP2 finally announced
120286: 07/06/05: Re: Power on Spartan 90nm process node
120289: 07/06/05: Re: Power on Spartan 90nm process node
120352: 07/06/06: Re: Lattice XP2 finally announced
120356: 07/06/06: Re: Lattice XP2 finally announced
120413: 07/06/07: Re: Virtex4 CLKX2 DCM Jitter
120426: 07/06/07: Re: asynchronous circuit design
120480: 07/06/08: Re: Lattce SC Purspeed I/O
120498: 07/06/08: Re: LVPECL output skew
120555: 07/06/10: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
120614: 07/06/12: Re: Power consumption problem
120646: 07/06/13: Re: Power consumption problem
120815: 07/06/18: Re: anyone know a FPGA designer?
120948: 07/06/21: Achronix Async FPGA Silicon available when ?
121150: 07/06/27: Re: Can FPGAs inputs detect low currents?
121193: 07/06/28: Re: another Forth CPU design
121198: 07/06/28: Re: Xilinx FPGA to interface to special I/O
121203: 07/06/28: Re: another Forth CPU design
121209: 07/06/28: Re: Analogue like signal interaction within cpld possible ????
121228: 07/06/29: Re: Analogue like signal interaction within cpld possible ????
121230: 07/06/29: Re: Xilinx FPGA to interface to special I/O
121241: 07/06/29: Execute from SPI flash
121242: 07/06/29: Re: Execute from SPI flash
121254: 07/06/29: Re: Execute from SPI flash
121343: 07/07/03: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121346: 07/07/03: Re: Analogue like signal interaction within cpld possible ????
121347: 07/07/03: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121354: 07/07/03: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121421: 07/07/04: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121539: 07/07/07: Re: Xilinx ISE, EDK and some ground roules in software development
121607: 07/07/10: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121653: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121697: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121698: 07/07/12: Re: Virtex-II Pro Flip-Flop Setup time
121701: 07/07/12: Altera MAX III Status ?
121706: 07/07/12: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121713: 07/07/12: Re: Virtex-II Pro Flip-Flop Setup time
121729: 07/07/12: Re: Altera MAX III Status ?
121758: 07/07/13: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121762: 07/07/13: Re: Altera MAX III Status ?
121765: 07/07/13: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121774: 07/07/13: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,Leon)?
121861: 07/07/14: Re: Counter ?
121862: 07/07/14: Re: Counter ?
121864: 07/07/14: Re: Counter ?
121867: 07/07/14: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121880: 07/07/14: Re: Image Resolution Rescaling
121903: 07/07/15: Re: ESR Meter - design contest
121905: 07/07/15: Re: ESR Meter - design contest
121909: 07/07/15: Re: ESR Meter - design contest
121983: 07/07/17: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121995: 07/07/17: Re: Xilinx XC9536 current draw ?
122022: 07/07/18: Re: Xilinx XC9536 current draw ?
122040: 07/07/18: Re: Xilinx XC9536 current draw ?
122041: 07/07/18: Re: Xilinx XC9536 current draw ?
122070: 07/07/19: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
122201: 07/07/24: Re: On I2C protocol
122253: 07/07/25: Re: On I2C protocol
122340: 07/07/26: Re: Documentation/leds/simulation
122347: 07/07/26: Re: Altera or Xilinx
122399: 07/07/27: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
122558: 07/07/31: Re: Looking for PLD with embedded memory
122581: 07/08/01: Re: Looking for PLD with embedded memory
122830: 07/08/08: Re: New Xilinx forum.
122831: 07/08/08: Re: New Xilinx forum.
122974: 07/08/13: Re: Xilinx 13th August opportunity
123038: 07/08/15: Re: Delaying a pulse train
123039: 07/08/15: Re: Delaying a pulse train
123045: 07/08/15: Re: Delaying a pulse train
123074: 07/08/16: Re: Delaying a pulse train
123081: 07/08/16: Re: Delaying a pulse train
123134: 07/08/17: Re: Delaying a pulse train
123258: 07/08/22: Re: Voltage translation question
123294: 07/08/23: Re: Power Reduction Strategy
123300: 07/08/23: Re: Power Reduction Strategy
123327: 07/08/24: Re: Voltage translation question
123608: 07/08/31: Re: An FPGA startup is seeking testcase from potential customers
123663: 07/09/01: Re: Die size, pitch size?
123775: 07/09/05: Re: Multiple CPLDs on a PCB.
123791: 07/09/05: Re: Multiple CPLDs on a PCB.
123924: 07/09/07: Re: VCCAUX too high on a Spartan 3 design
123982: 07/09/10: Re: Minimize power consumption
123985: 07/09/10: Re: Minimize power consumption
124024: 07/09/11: Re: Uses of Gray code in digital design
124039: 07/09/11: Re: Uses of Gray code in digital design
124041: 07/09/11: Re: Uses of Gray code in digital design
124088: 07/09/12: Re: Uses of Gray code in digital design
124090: 07/09/12: Re: Uses of Gray code in digital design
124106: 07/09/12: Re: Uses of Gray code in digital design
124251: 07/09/17: Re: Beginner Advice (Languages, tools etc.)
124252: 07/09/17: Re: Physical Design Contribution to FPGA/CPLD success
124280: 07/09/18: Re: Guess: what is the largest number of state machines in a current
124328: 07/09/19: Re: Guess: what is the largest number of state machines in a current
124330: 07/09/19: Re: Altera / Lattice / Xilinx CPLDs ?
124331: 07/09/19: Re: Altera / Lattice / Xilinx CPLDs ?
124335: 07/09/19: Re: Guess: what is the largest number of state machines in a current
124494: 07/09/25: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost
124544: 07/09/26: Re: Never buy Altera!!!!
124731: 07/10/02: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124732: 07/10/02: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124747: 07/10/03: Re: Test and Measurements - Large FPGA
124829: 07/10/06: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124830: 07/10/06: Re: Virtex 13?
124888: 07/10/10: Re: Legacy support of a Max 7000S
125033: 07/10/16: Re: FPGA quiz: what can be wrong
125056: 07/10/16: Re: FPGA quiz: what can be wrong
125067: 07/10/16: Re: FPGA quiz: what can be wrong
125075: 07/10/16: Re: FPGA quiz: what can be wrong
125145: 07/10/17: Re: FPGA quiz: what can be wrong
125149: 07/10/17: Re: FPGA quiz: what can be wrong
125168: 07/10/17: Re: FPGA quiz: what can be wrong
125188: 07/10/18: Re: FPGA quiz: what can be wrong
125189: 07/10/18: Re: FPGA quiz 1&2, we have the answers and winners
125222: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer
125265: 07/10/19: Re: FPGA pin swapping utility
125266: 07/10/19: Re: FPGA quiz3, or where Antti did give up and does not know answer
125275: 07/10/19: Re: mess around with supply voltage to cyclone III
125406: 07/10/25: Re: Changing refresh rate for DRAM while in operation?
125452: 07/10/26: Re: Signetics N82F101F
125506: 07/10/27: Re: Signetics N82F101F
125507: 07/10/27: Re: is Quartus 7.1 really that S*** !?
125547: 07/10/29: Re: Power supply filter capacitors
125551: 07/10/29: Re: Power supply filter capacitors
125589: 07/10/30: Re: Power supply filter capacitors
125600: 07/10/30: Re: Signetics N82F101F
125678: 07/11/01: Re: Ping Jim: The PFD is dead!
125679: 07/11/01: Re: Capability of a FPGA device.
125681: 07/11/01: Re: Ping Jim: The PFD is dead!
125712: 07/11/02: Re: can i use dual edge or two clocks?
125713: 07/11/02: Re: Another way to handle floating inputs.
125723: 07/11/02: Re: can i use dual edge or two clocks?
125753: 07/11/03: Re: Another way to handle floating inputs.
125811: 07/11/06: Re: not totally repulsive
125841: 07/11/07: Re: not totally repulsive
125849: 07/11/07: Re: not totally repulsive
125875: 07/11/08: Re: Non-volatile FPGA in a small package
125931: 07/11/09: Re: Maximum current drive according to datasheet ?!
125981: 07/11/11: Re: newbie to 16v8
125988: 07/11/12: Re: newbie to 16v8
125993: 07/11/12: Re: newbie to 16v8
125994: 07/11/12: Re: newbie to 16v8
126091: 07/11/15: Re: FPGA for hobby use
126121: 07/11/15: Re: Xilinx Virtex-II Newbie
126125: 07/11/15: Re: Xilinx Virtex-II Newbie
126128: 07/11/15: Re: Xilinx Virtex-II Newbie
126152: 07/11/16: Re: Xilinx Virtex-II Newbie
126237: 07/11/18: Re: Coolrunner in system programming - XAPP0058 - viable?
126242: 07/11/18: Re: Coolrunner in system programming - XAPP0058 - viable?
126262: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
126270: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
126275: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
126281: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
126311: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
126319: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
126321: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
126324: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
126325: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
126330: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
126333: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
126336: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
126346: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
126385: 07/11/21: Re: Coolrunner in system programming - XAPP0058 - viable?
126387: 07/11/21: Re: Coolrunner in system programming - XAPP0058 - viable?
126388: 07/11/21: Re: Coolrunner in system programming - XAPP0058 - viable?
126420: 07/11/22: Re: Measuring setup and hold time in Lab
126422: 07/11/22: Re: Measuring setup and hold time in Lab
126491: 07/11/25: Re: using fpga as programmable connection
126526: 07/11/27: Re: xilinx spartan 3 + 16 adc
126562: 07/11/28: Re: CPU design uses too many slices
126576: 07/11/28: Re: VHDL language is out of date! Why? I will explain.
126586: 07/11/28: Re: I/O short circuit protection?
126709: 07/11/30: Re: lossless compression in hardware: what to do in case of uncompressibility?
126857: 07/12/05: Re: XILINX XABEL
127062: 07/12/11: Re: GAL16V8
127088: 07/12/12: Re: Craignell and Darnaw1 Website Updates
127273: 07/12/17: Re: Why the core dynamic power isn't 0 when the toggle=?ISO-8859-1?Q?_rate_is_0??=
127334: 07/12/19: Re: VCCIO issue on Xilinx Spartan3E !
128630: 08/02/01: Re: Why use small resistor for Vcco voltage regulator
128657: 08/02/02: Re: Why use small resistor for Vcco voltage regulator
128661: 08/02/02: Re: Why use small resistor for Vcco voltage regulator
128668: 08/02/03: Re: Why use small resistor for Vcco voltage regulator
128682: 08/02/04: Re: My first Flash FPGA
128965: 08/02/12: Re: how to implement this...
129004: 08/02/13: Re: My first verilog/cpld project
129055: 08/02/14: Re: When are FPGAs the right choice?
129063: 08/02/14: Re: Newbie looking for guidance
129067: 08/02/14: Re: When are FPGAs the right choice?
129115: 08/02/15: Re: Rom Implementation in a CPLD
129124: 08/02/15: Re: Virtex-4 input pad failures
129209: 08/02/19: Re: Ballpark PLB frequency
129312: 08/02/21: Re: Using Lattice ispLEVER with VHDL libraries
129315: 08/02/21: Re: MicroBlaze simulator, software ownership rights for SALE
129318: 08/02/21: Re: FPGA Programming solution
129355: 08/02/22: Re: Random Number Generation in VHDL
129528: 08/02/27: Re: Convert some table into combinatorial circuit + optimization
129529: 08/02/27: Re: Picoblaze enhencement and assembler
129843: 08/03/07: Re: Blast from the past
129867: 08/03/08: SiliconBlue enters the FPGA fray
129871: 08/03/08: Re: SiliconBlue enters the FPGA fray
129911: 08/03/10: Re: XC3S50-4VQ100C fpga chip
130008: 08/03/13: Re: SiliconBlue enters the FPGA fray
130009: 08/03/13: Re: SiliconBlue enters the FPGA fray
130154: 08/03/17: Re: Designing CPU
130193: 08/03/18: Re: Designing CPU
130199: 08/03/18: Re: Designing CPU
130266: 08/03/19: Re: Optimizing an inferred counter
130269: 08/03/19: Re: A Challenge for serialized processor design and implementation
130292: 08/03/20: Re: A Challenge for serialized processor design and implementation
130302: 08/03/20: Re: A Challenge for serialized processor design and implementation
130306: 08/03/20: Re: A Challenge for serialized processor design and implementation
130463: 08/03/25: Re: A Challenge for serialized processor design and implementation
130464: 08/03/25: Re: A Challenge for serialized processor design and implementation
130507: 08/03/26: Re: counterfeit Xilinx ?
130590: 08/03/28: Re: A Challenge for serialized processor design and implementation
130665: 08/03/30: Re: async clk input, clock glitches
130666: 08/03/30: Re: async clk input, clock glitches
130667: 08/03/30: Re: async clk input, clock glitches
130669: 08/03/30: Re: async clk input, clock glitches
130670: 08/03/30: Re: ISE 10.1 - Initial experience
130696: 08/03/31: Re: async clk input, clock glitches
130704: 08/03/31: Re: async clk input, clock glitches
130705: 08/03/31: Re: async clk input, clock glitches
130747: 08/04/01: Re: ISE 10.1 - Initial experience
130762: 08/04/01: Re: ISE 10.1 - Initial experience
130801: 08/04/02: Re: now I can talk about it...
130826: 08/04/03: Re: counterfeit Xilinx ?
130830: 08/04/03: Re: counterfeit Xilinx ?
130864: 08/04/04: Re: A Challenge for serialized processor design and implementation
130883: 08/04/04: Re: A Challenge for serialized processor design and implementation
130910: 08/04/05: Re: Xilinx FPGA + SMPS
130915: 08/04/05: Re: Conterfeit parts guidance
130916: 08/04/05: Re: counterfeit Xilinx ?
130926: 08/04/05: Re: PLA datasheet - PLS161
130927: 08/04/05: Re: PLA datasheet - PLS161
130934: 08/04/06: Re: A Challenge for serialized processor design and implementation
130950: 08/04/07: Re: Xilinx inferred FIFOs
130956: 08/04/07: Re: Conterfeit parts guidance
130977: 08/04/08: Re: counterfeit Xilinx ?
131030: 08/04/09: Re: Intel plans to tackle cosmic ray threat (actually they have beenworking
131031: 08/04/09: Re: Modify POF with new ESB (ROM) content?
131039: 08/04/09: Re: A Challenge for serialized processor design and implementation
131048: 08/04/09: Re: 32 bit multiplier
131049: 08/04/09: Re: Disable optimisation - Ring oscillator
131076: 08/04/10: Re: A Challenge for serialized processor design and implementation
131084: 08/04/10: Re: 32 bit multiplier
131135: 08/04/12: Re: Xilinx tech Xclusive
131139: 08/04/12: Re: Xilinx tech Xclusive
131680: 08/04/29: Re: Problem writing quadrature decoder
131921: 08/05/08: Re: ANNC: FPGA Design Software Webcast
131924: 08/05/08: Re: Problem writing quadrature decoder
131937: 08/05/08: Re: Problem writing quadrature decoder
131965: 08/05/09: Re: ANNC: FPGA Design Software Webcast
132003: 08/05/10: Re: 5 V oscillator output to GCLK
132013: 08/05/10: Re: 5 V oscillator output to GCLK
132015: 08/05/10: Re: 5 V oscillator output to GCLK
132022: 08/05/10: Re: 5 V oscillator output to GCLK
132023: 08/05/10: Re: Problem writing quadrature decoder
132039: 08/05/11: Re: Problem writing quadrature decoder
132045: 08/05/12: Re: Problem writing quadrature decoder
132049: 08/05/12: Re: Problem writing quadrature decoder
132054: 08/05/12: Re: Problem writing quadrature decoder
132073: 08/05/13: Re: Problem writing quadrature decoder
132077: 08/05/13: Re: Problem writing quadrature decoder
132078: 08/05/13: Re: Problem writing quadrature decoder
132079: 08/05/13: Re: Problem writing quadrature decoder
132080: 08/05/13: Re: Problem writing quadrature decoder
132082: 08/05/13: Re: Programming XCR3064xl - voltage at output stuck at 0
132084: 08/05/13: Re: Problem writing quadrature decoder
132085: 08/05/13: Re: Problem writing quadrature decoder
132088: 08/05/13: Re: Problem writing quadrature decoder
132091: 08/05/13: Re: Problem writing quadrature decoder
132096: 08/05/14: Re: Problem writing quadrature decoder
132104: 08/05/14: Re: Problem writing quadrature decoder
132106: 08/05/14: Re: Problem writing quadrature decoder
132111: 08/05/14: Re: Problem writing quadrature decoder
132113: 08/05/14: Re: Yay! We're done with the quadrature encoder!
132124: 08/05/15: Re: Programming XCR3064xl - voltage at output stuck at 0
132250: 08/05/20: Re: Resetting FPGA Without watch dog timer
132255: 08/05/20: Re: Stratix IV Announced
132292: 08/05/21: Re: bizarre state machine behavior
132321: 08/05/22: Re: Stratix IV Announced
132322: 08/05/22: Re: Every newbie's favorite project: the Quadrature Rotary Encoder
132331: 08/05/22: Re: bizarre state machine behavior
132450: 08/05/28: Mathstar plans to discontinue FPOA development
132455: 08/05/28: Re: 'Nother one bites the dust
132490: 08/05/29: Re: Sequentially syncrhronous
132491: 08/05/29: Re: Sequentially syncrhronous
132492: 08/05/29: Re: Sequentially syncrhronous
132500: 08/05/29: Re: Are FPGAs headed toward a coarse granularity?
132654: 08/06/05: Re: Xilinx vs Altera
132657: 08/06/05: Re: Xilinx vs Altera
132659: 08/06/05: Re: Xilinx cuts 250 jobs.
132660: 08/06/05: A new FPGA company comes out of Stealth mode - SiliconBlue
132725: 08/06/06: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132727: 08/06/06: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
132730: 08/06/06: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
132735: 08/06/06: Re: Xilinx vs Altera
132750: 08/06/06: Re: ANNOUNCE: SiliconBlue Pioneers New FPGA Technology for Handheld,
132764: 08/06/06: Re: xilinx and jtag
132800: 08/06/07: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
132807: 08/06/07: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132925: 08/06/11: Re: Cheating the FPGA clock speed
133007: 08/06/13: Re: HELP: a Funny asynchronous input design
133016: 08/06/14: Re: CPLD beginner questions
133020: 08/06/14: Re: CPLD beginner questions
133027: 08/06/14: Re: HELP: a Funny asynchronous input design
133029: 08/06/14: Re: CPLD beginner questions
133040: 08/06/15: Re: FPGA IO Pin Unwanted Coupling
133133: 08/06/19: Re: =?windows-1252?Q?NVIDIA=92s_Tesla_T10P_Blurs_Some_?=
133400: 08/06/27: Re: NVRAM design in CPLD
133418: 08/06/28: Re: Standard forms for Karnaugh maps?
133424: 08/06/28: Re: Standard forms for Karnaugh maps?
133433: 08/06/29: Re: Standard forms for Karnaugh maps?
133500: 08/07/02: Re: Nintendo DS Screenshots / Video Capture
133512: 08/07/02: Re: How do I program an fpga once it has been designed and layout
133589: 08/07/05: Re: Single ended interface at 70Mhz for FPGAs
133634: 08/07/08: Re: Virtex 4 expected production end-of-life
133966: 08/07/21: Re: The littlest CPU
134142: 08/07/28: Re: vhdl code for debouncing push button
134178: 08/07/29: Re: vhdl code for debouncing push button
134179: 08/07/29: Re: vhdl code for debouncing push button
134189: 08/07/30: Re: vhdl code for debouncing push button
134294: 08/08/05: Altera sues Zilog - signs of desperation from Programmable Vendor
134341: 08/08/07: Re: Altera sues Zilog - signs of desperation from Programmable Vendor
134342: 08/08/07: Re: Downsizing Verilog synthesization.
134364: 08/08/08: Re: Downsizing Verilog synthesization.
134369: 08/08/08: Re: Downsizing Verilog synthesization.
134373: 08/08/08: Re: Downsizing Verilog synthesization.
134399: 08/08/09: Re: Downsizing Verilog synthesization.
134401: 08/08/09: Re: Downsizing Verilog synthesization.
134408: 08/08/09: Re: Coolrunner programming - best way?
134418: 08/08/10: Re: Downsizing Verilog synthesization.
134419: 08/08/10: Re: Downsizing Verilog synthesization.
134437: 08/08/11: Re: Downsizing Verilog synthesization.
134445: 08/08/11: Re: Altera question - MAX3000 vs MAX7000
134458: 08/08/12: Re: Downsizing Verilog synthesization.
134707: 08/08/27: Re: need fast FPGA suggestions
134720: 08/08/28: Re: need fast FPGA suggestions
134722: 08/08/28: Re: need fast FPGA suggestions
134752: 08/08/29: Re: need fast FPGA suggestions
134754: 08/08/29: Re: need fast FPGA suggestions
134759: 08/08/29: Re: crazy patent
134847: 08/09/04: Re: XST bug on illigal states of a FSM ?
135019: 08/09/11: Re: WinCupl Problem(s)
135064: 08/09/13: Re: Ultra low power FPGAs
135066: 08/09/13: Re: Seeking several async. SRAMs at 8ns ( IS61LV51216-8T or GS74116TP-8)
135085: 08/09/15: Re: Ultra low power FPGAs
135140: 08/09/18: Re: Random Mask Generation on FPGAs
135465: 08/10/03: Re: Standalone Altera production programmer
135641: 08/10/11: Re: Lattice vs Altera (Mico32 / NIOS)....or?
135701: 08/10/13: Re: Lattice vs Altera (Mico32 / NIOS)....or?
135777: 08/10/16: Re: free cpu 8051 verilog code
135779: 08/10/16: Re: sensitive fpga
135803: 08/10/16: Re: A couple of CPLD design challenges for the group
135804: 08/10/16: Re: A couple of CPLD design challenges for the group
135820: 08/10/17: Re: A couple of CPLD design challenges for the group
135823: 08/10/17: Re: A couple of CPLD design challenges for the group
135831: 08/10/17: Re: Using GCK pin as both clock and signal (Spartan 2)
135855: 08/10/18: Re: Using GCK pin as both clock and signal (Spartan 2)
135866: 08/10/19: Re: A couple of CPLD design challenges for the group
135873: 08/10/20: Re: Field update
136006: 08/10/27: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
136045: 08/10/29: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
136256: 08/11/08: Re: Tilera multicore replaces FPGA?
136407: 08/11/15: Re: What happened to the Cyclone IV?
136424: 08/11/16: Re: What happened to the Cyclone IV?
136658: 08/11/29: Re: EPLD - FPGA - Is there a difference
151370: 11/03/28: Re: MAX II CPLD and I2S Clock divider jitter
151372: 11/03/28: Re: MAX II CPLD and I2S Clock divider jitter
151603: 11/04/25: Re: Lattice Breakout Boards
152096: 11/07/05: Re: Delta-Sigma in an FPGA
152118: 11/07/10: Re: VHDL rollover of counter
152128: 11/07/11: Re: VHDL rollover of counter
152508: 11/08/29: Re: Very cheap Spartan3 board that can be configured by simple USB
152509: 11/08/29: Re: A free lunch
152512: 11/08/29: Re: Very cheap Spartan3 board that can be configured by simple USB
152563: 11/09/14: Re: Xilinx Tin Whiskers ?
152730: 11/10/13: Re: Spartan changes in glitch sensitivity
153137: 11/12/09: Re: Lattice buys SiBlue for $62 million
153445: 12/02/26: Re: What is a PLD/FPGA with serial or Ethernet port logic or block
153451: 12/02/27: Re: What is a PLD/FPGA with serial or Ethernet port logic or block
Jim Hamblen:
22086: 00/04/20: Re: VGA interface and VHDL
22095: 00/04/21: Re: MaxPlus9.5 License and Fitter problems
Jim Hearne:
11178: 98/07/23: Logic Lab Gal Programmer
Jim Horn:
159195: 16/08/30: Altera USB Blaster clone driver for STM32F1xx
Jim Hwang:
31771: 01/06/05: Re: XtremeDSP Ready for prime time?
43660: 02/05/28: Re: Addressable shift register
Jim Jones:
153649: 12/04/09: FPGAs directly plugged into CPU socket
Jim Kapcio:
2394: 95/11/28: Checksum from .pof file
Jim Kearney:
38979: 02/01/29: Re: The LUT puzzle, Iam on the way
39516: 02/02/12: Re: Spartan Program/Verify
39540: 02/02/13: Re: Spartan Program/Verify
39581: 02/02/13: Re: Altera's new family Stratix
40561: 02/03/10: Re: Xilinx Download Cable Connectors
40611: 02/03/11: Re: Xilinx Download Cable Connectors
45199: 02/07/15: Re: Which is best method for register with settable and clearable bits
54336: 03/04/08: Re: Xilinx Impact and USB/LPT ports
54362: 03/04/09: Re: Xilinx Impact and USB/LPT ports
59639: 03/08/25: Re: Reusing CCLK line after configuration for Spartan-II
59670: 03/08/25: Re: Reusing CCLK line after configuration for Spartan-II
Jim King:
14095: 99/01/13: Re: Problems with processes
14096: 99/01/13: Re: Problems with processes
14115: 99/01/14: Ratings for Synplicity Synplify
14120: 99/01/14: Re: Problem with reducing bus width / Foundation Series v1.5
14140: 99/01/15: General FPGA introduction needed
14656: 99/02/09: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14503: 99/02/02: Re: FPGA Express Evaluation...
Jim Kipps:
15958: 99/04/23: Re: fpga express stripping out Viewlogic busses
15959: 99/04/23: Re: Viewlogic FPGA Express vs Xilinx FPGA Express....any difference?
16184: 99/05/07: Re: [Q]Do you recommend Altera MAXPLUS II9.01 as a VHDL compiler for
16286: 99/05/13: Re: How synthesize tools concern with size of the design?
16313: 99/05/14: Re: How synthesize tools concern with size of the design?
16356: 99/05/18: Case study: Viewlogic's IntelliFlow
16409: 99/05/20: Re: Foundation FPGA Express
16410: 99/05/20: Re: Case study: Viewlogic's IntelliFlow
16467: 99/05/24: Re: How synthesize tools concern with size of the design?
16872: 99/06/15: Re: FPGA Express 3.00
16941: 99/06/18: Re: vhdl and viewlogic problem
17011: 99/06/24: Re: Viewdraw + Foundation Express design flow
17012: 99/06/24: Re: Synopsys FPGA Express vs. Compiler II
17013: 99/06/24: Re: Synopsys DC & FPGA Compiler
Jim Kruse:
553: 94/12/30: Re: LPM Docs & Resources
Jim LaLone:
294: 94/10/14: Re: Xilinx configuration
Jim Lewis:
13997: 99/01/06: Re: VHDL Bit String Literals
15989: 99/04/26: VHDL Class, May 26-27, Portland Or.
50164: 02/12/03: Re: register OR latch ? (source code)
50286: 02/12/07: Re: Warnings in FPGA express
50784: 02/12/19: Re: How to asynchronously reset a flip-flop?
50858: 02/12/20: Re: FPGA Supercomputing opportunity
51450: 03/01/13: Re: How to coerce a list of discrete signals to an array in VHDL
51770: 03/01/21: Re: A Request: VHDL Source of a 32bit Floating Point ALU - Still
54671: 03/04/15: Re: synthesis of a VHDL module in Xilinx
59338: 03/08/15: Re: Synthesisable fixed-point arithmetic package
61551: 03/10/06: Re: Implementing multiple registers with one single input output
62146: 03/10/20: Re: Subroutine in VHDL?
62184: 03/10/21: Re: 74 logic to CPLD. how easy for a Newbie?
62560: 03/11/01: Re: simulation stops preliminarily
62683: 03/11/04: Re: Video Scan Conversion Rate - Camera Input to DVI Display Output
62894: 03/11/10: Re: Reverse engineering an EDIF file?
64520: 04/01/06: Re: How do you initialize signals in VHDL?
64695: 04/01/11: Re: Synthesis in VHDL vs. Verilog
64696: 04/01/11: Re: Synthesis in VHDL vs. Verilog
64740: 04/01/12: Re: Synthesis in VHDL vs. Verilog
64783: 04/01/13: Re: Synthesis in VHDL vs. Verilog
64788: 04/01/13: Re: Synthesis in VHDL vs. Verilog
64931: 04/01/16: Re: Please help with Xilinx ISE Schematic question
65195: 04/01/21: Re: Soft failures (?) 9536XL
65262: 04/01/22: Re: Synthesizing pipelined multipliers in Synplify Pro
65351: 04/01/25: Re: VHDL newbie
65460: 04/01/29: Re: FPGA basics
65528: 04/02/01: Re: Syn. warning
67209: 04/03/08: Re: strange error
67347: 04/03/10: Re: very strange error
68030: 04/03/24: Re: study verilog or vhdl?
68059: 04/03/25: Re: study verilog or vhdl?
68143: 04/03/27: Re: study verilog or vhdl?
68187: 04/03/29: Re: study verilog or vhdl?
68451: 04/04/05: Re: VHDL: Use of literal '1' on an input port ?
68492: 04/04/06: Re: Which HVL is the most popular?
68534: 04/04/07: Re: VHDL: Use of literal '1' on an input port ?
68744: 04/04/16: Re: Bus interface?
68880: 04/04/20: Re: reading files in vhdl
69187: 04/04/29: Re: good starter kit
69306: 04/05/05: Re: How to drive record fields from procedure AND testbench?
69335: 04/05/06: Re: How to drive record fields from procedure AND testbench?
69337: 04/05/06: Re: How to drive record fields from procedure AND testbench?
69348: 04/05/07: Re: How to drive record fields from procedure AND testbench?
69401: 04/05/10: RAM inference and Standards
69402: 04/05/10: Re: Easypath question (was "Hard-tocopy" rant)
69408: 04/05/10: Re: Monolithic state machine or structured state machine?
69412: 04/05/10: Re: Monolithic state machine or structured state machine?
69617: 04/05/15: Re: One issue about free hardware
71292: 04/07/13: Re: FSM in illegal state (conclusion)
71314: 04/07/14: Re: FSM in illegal state (conclusion)
71325: 04/07/14: Re: FSM in illegal state (conclusion)
73774: 04/09/29: Re: Clock Edge notation
73449: 04/09/21: Re: combinatorial loops / feedback paths discussion
73603: 04/09/24: Re: Getting info from a digital line
75295: 04/11/01: Re: XST: suppressing incorrect optimizations in VHDL code
75329: 04/11/02: Re: "frying" FPGAs
75349: 04/11/02: Re: "frying" FPGAs
74751: 04/10/18: Re: VHDL code for Type and Components
74843: 04/10/20: Re: VHDL help needed ($)
75382: 04/11/03: Re: XILINX Webpack VHDL synthesis question (unnecessary MUX infered)
75405: 04/11/04: Re: XILINX Webpack VHDL synthesis question (unnecessary MUX infered)
75568: 04/11/09: Re: xilinx webpack simulation problem (latch in place of logic)
76197: 04/11/28: Re: dual-write port BRAM with XST/Webpack
76628: 04/12/07: Re: Verilog Book Recommendation
76643: 04/12/07: Re: "Hello World" project for an FPGA (on a Spartan3 board)
77076: 04/12/21: Re: low cost Altera MAX II development kit with more I/O pins?
77283: 05/01/03: Re: Recover FPGA Verilog or VHDL source from .SOF file
77335: 05/01/04: Re: Procedure exit on global signal
79053: 05/02/11: Re: ISE and IEEE.Fixed_pkg (fixed point math for synth?)
90431: 05/10/12: Re: VHDL : Use concatenation on port mapping
109278: 06/09/22: Call for Participation Accellera VHDL Verification Features
111987: 06/11/14: Re: Nested Generate Statement in VHDL
113986: 07/01/01: Re: Matlab (.m) to VHDL
114156: 07/01/05: Re: DC timing violation, what to do first?
115434: 07/02/10: Re: Setting VHDL standard in Xilinx ISE
116266: 07/03/05: Re: VHDL and Latch
116402: 07/03/08: Re: How to implement pipeline in this case?
116411: 07/03/08: Re: VHDL and Latch
116435: 07/03/08: Re: VHDL and Latch
116437: 07/03/08: Re: VHDL and Latch
117222: 07/03/26: Re: A suggestion for a new input interface for functions in VHDL:
117263: 07/03/27: Re: A suggestion for a new input interface for functions in VHDL:
117277: 07/03/27: Re: A suggestion for a new input interface for functions in VHDL:
117339: 07/03/28: Re: A suggestion for a new input interface for functions in VHDL:
117383: 07/03/29: RFC: Enhancing VHDL for OO, Randomization, Functional Coverage
117434: 07/03/30: Re: A suggestion for a new input interface for functions in VHDL:
117531: 07/04/03: RFC: VHDL testbench enhancements
117538: 07/04/03: Re: RFC: VHDL testbench enhancements
118733: 07/05/02: Re: debounce state diagram FSM - topical
119498: 07/05/21: Re: VHDL newbie: building sequential circuits with basic gates
119507: 07/05/21: Re: VHDL newbie: building sequential circuits with basic gates
123463: 07/08/28: Re: Null statement in VHDL
123465: 07/08/28: Re: New keyword 'orif' and its implications
123478: 07/08/28: Re: New keyword 'orif' and its implications
123576: 07/08/30: Re: New keyword 'orif' and its implications
123577: 07/08/30: Re: New keyword 'orif' and its implications
123594: 07/08/30: Re: New keyword 'orif' and its implications
123600: 07/08/30: Re: New keyword 'orif' and its implications
123601: 07/08/30: Re: New keyword 'orif' and its implications
123639: 07/08/31: Re: New keyword 'orif' and its implications
123672: 07/08/31: Re: New keyword 'orif' and its implications
123850: 07/09/05: Re: New keyword 'orif' and its implications
123851: 07/09/05: Re: New keyword 'orif' and its implications
124357: 07/09/19: Re: Guess: what is the largest number of state machines in a current
129465: 08/02/25: Re: Seed Values
129497: 08/02/26: Re: Seed Values
131322: 08/04/18: Re: Which to learn: Verilog vs. VHDL?
131323: 08/04/18: Re: Which to learn: Verilog vs. VHDL?
131777: 08/05/01: Re: sobel in vhdl
136480: 08/11/18: Re: Aligned PLL clocks in RTL simulation
136504: 08/11/19: Re: Aligned PLL clocks in RTL simulation
137526: 09/01/21: Re: Digilent USB Cable supported Devices
138389: 09/02/18: Re: VHDL long elsif state machine
156356: 14/03/17: Re: full functional coverage
156357: 14/03/17: Re: full functional coverage
156366: 14/03/19: Re: full functional coverage
156371: 14/03/19: Re: full functional coverage
156372: 14/03/19: Re: full functional coverage
156379: 14/03/20: Re: full functional coverage
157106: 14/10/13: Re: looking for systemC/TLM 2.0 courses
160157: 17/06/21: Re: VHDL or Verilog?
160387: 18/01/10: Re: HDL simple survey - what do you actually use
Jim Lewis, ASIC and HDL Consultant:
3865: 96/08/12: Technical Job posting ( and ads) not related to the newsgroup.
3866: 96/08/12: Technical Job posting ( and ads) not related to the newsgroup.
Jim Lyke:
15827: 99/04/15: subscribe
47380: 02/09/25: Where can I get XC6200 series FPGAs
Jim M.:
54597: 03/04/14: NIOS 3.0 Fmax and other Issues
54659: 03/04/15: Re: NIOS 3.0 Fmax and other Issues
54749: 03/04/17: Re: NIOS 3.0 Fmax and other Issues
54751: 03/04/17: Avalon Bus Master
54901: 03/04/21: Re: Avalon Bus Master
54902: 03/04/21: NIOS 3.0 Spurious Interrupts
54934: 03/04/22: Re: NIOS 3.0 Fmax and other Issues
54968: 03/04/23: Re: NIOS 3.0 Spurious Interrupts
55012: 03/04/24: Re: NIOS 3.0 Spurious Interrupts
55022: 03/04/24: Declaring variables with NIOS and GNUPro Tools
55024: 03/04/24: Re: NIOS 3.0 Fmax and other Issues
55128: 03/04/28: NIOS Development Board and Flash Protection
55163: 03/04/29: Re: NIOS Development Board and Flash Protection
55256: 03/05/01: Re: Schmitt Trigger an a Virtex
55387: 03/05/06: Re: MJL Stratix Dev Kit
57795: 03/07/07: Re: Problem with user defined logicinterface in Nios
Jim McCloskey:
10219: 98/05/05: 3.3V design conversion
Jim McGinnis:
45383: 02/07/21: Re: TMS 1000
Jim McGrath:
8873: 98/02/03: combining Altera .sof files
Jim McManus:
5407: 97/02/13: Re: PCI Prototyping board with a XC4013E or XC4013EX
6084: 97/04/10: Re: PCI and DRAM control - Xilinx 4000 -Verilog
7307: 97/08/24: Re: Xilinx PCI simulation problem...
17207: 99/07/08: Re: PCI interface
17222: 99/07/10: Re: PCI interface
17276: 99/07/15: Re: PCI interface
17277: 99/07/15: Re: PCI interface
18215: 99/10/07: Re: Virtex and PCI 5V?
18214: 99/10/07: Re: HOT II PCI Development System
19966: 00/01/20: Re: which PLD support Hot-swap
21094: 00/03/06: Re: PCI reflected wave switching spec ???
25101: 00/08/25: Re: PCI macros
Jim Mrowca:
5698: 97/03/07: Re: Introducing Renoir
Jim Patterson:
22521: 00/05/11: Info on using Reconfig feature of Virtex?
26788: 00/10/29: help on a simple ALU
26792: 00/10/29: Re: help on a simple ALU
46384: 02/08/28: Re: Anyone already on QUARTUS II V2.1 ?
46385: 02/08/28: Re: Stratix Experience
Jim Pennell:
28050: 00/12/19: Re: 3V -> 5V clock signal level conversion
Jim Peterson:
2977: 96/03/07: Re: Reconfigurable Computing Languages
9462: 98/03/15: Xilinx could gaurd its secrets better (Re: Strange Xilinx question?)
11524: 98/08/20: Re: half full flag in a xilinx async fifo?
11544: 98/08/21: Re: Big FPGA on PCI card with Linux support?
Jim Poder:
30926: 01/05/03: Re: Serial UART
Jim Ranlett:
55859: 03/05/21: Asynchronous State Machines and HDLs
Jim Raynor:
41949: 02/04/11: Price List ?
42084: 02/04/15: FPGA parameters
42299: 02/04/19: XC9500XL problem
44039: 02/06/10: Spartan II E -- BUFGDLL
44044: 02/06/10: BUFGDLL again
44090: 02/06/11: Multi Pass PAR
44737: 02/06/28: Re: blank CPLD
44975: 02/07/08: loading Spartan 2E configuration
45044: 02/07/11: Re: FPGA/CPLD Decision help?
45490: 02/07/24: vhdl dll question....help please
45499: 02/07/24: XST vs FPGA Express???
46417: 02/08/28: Problem: Spartan 2 E CCLK
51422: 03/01/13: Simulate Virtex Primitive using ModelSim
51435: 03/01/13: Re: Simulate Virtex Primitive using ModelSim
52324: 03/02/07: HELP NEEDED
Jim Robinson:
58407: 03/07/22: Re: Synplify syn_direct_enable doesn't work for me.
58497: 03/07/24: Re: Synplify syn_direct_enable doesn't work for me.
67919: 04/03/22: Free trial of Identify Lite RTL Debugger for Xilinx
Jim Roehn:
5348: 97/02/09: Re: X84 board VHDL examples
Jim Sackman:
3594: 96/07/02: Re: Need recommendation for PCI interface on 68332
Jim Stewart:
21089: 00/03/06: Stupid Foundation question
37259: 01/12/05: Re: For Sale: Huge Xilinx FPGA lots
44273: 02/06/15: Stupid WebPack question
44275: 02/06/15: Re: Stupid WebPack question
44277: 02/06/15: Re: Stupid WebPack question
44313: 02/06/17: Another stupid WebPack question
44627: 02/06/24: Re: too hot fpga device
54414: 03/04/10: Webpack 5.2 and Win98se
54428: 03/04/10: Re: Webpack 5.2 and Win98se
54436: 03/04/10: Re: Webpack 5.2 and Win98se
54494: 03/04/11: Re: Buying FPGAs from parts brokers
54874: 03/04/21: Re: Webpack 5.2 Install problems?
54878: 03/04/21: Re: Webpack 5.2 Install problems?
54974: 03/04/23: Re: Webpack 5.2 Install problems?
55144: 03/04/28: Re: Low pin count SOC
55209: 03/04/30: Re: Boycott All Xilinx products untill they correct all ISE softwareerrors
55250: 03/05/01: Re: Boycott All Xilinx products untill they correct all ISE softwareerrors
55449: 03/05/08: Re: Software and hardware monopoly is bad
55552: 03/05/12: Re: Price of CPLDs
73508: 04/09/22: Re: [ALTERA] NIOS-II + MMU + FPU
73649: 04/09/27: Re: embedded linux on FPGA?
74868: 04/10/20: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
95539: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95554: 06/01/23: Re: OT:Shooting Ourselves in the Foot
107531: 06/08/29: Re: September training?
108137: 06/09/05: Re: Please help me with (insert task here)
108217: 06/09/06: Re: Please help me with (insert task here)
108224: 06/09/06: Re: Please help me with (insert task here)
125360: 07/10/23: Re: Changing refresh rate for DRAM while in operation?
146539: 10/03/22: Re: Finally, selling my old Xilinx/Viewlogic software package
Jim Stockton:
55221: 03/04/30: Re: Low power, high temperature CPLD
Jim Sung:
3856: 96/08/09: An incompatible problem of ALTERA MAXPLUS2 Ver6.2, Ver 6.1 -- need your help
3877: 96/08/13: Re: An incompatible problem of ALTERA MAXPLUS2 Ver6.2, Ver 6.1 -- need your help
Jim Ternus:
8384: 97/12/11: Royalties Agreement
Jim Thomas:
43423: 02/05/21: Re: SDRAM pricing
109266: 06/09/22: Re: Dell Laptop for Embedded Work
Jim Thompson:
64377: 03/12/31: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
64414: 04/01/02: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
87908: 05/08/03: Re: System Engineering in the R/D World
87958: 05/08/04: Re: System Engineering in the R/D World
87959: 05/08/04: Re: System Engineering in the R/D World
93196: 05/12/15: Re: Xilinx' encrypted HPICE models in PSPICE
95587: 06/01/24: Re: Very OT: Americanized family names
95009: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95010: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95032: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95033: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95037: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95047: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95049: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95079: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95109: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95110: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95118: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95128: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95136: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95139: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95149: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95281: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95341: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95404: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95447: 06/01/23: Re: OT:Shooting Ourselves in the Foot
99879: 06/03/30: Re: deglitching a clock
99885: 06/03/30: Re: deglitching a clock
107655: 06/08/30: Re: Performance Appraisals
107656: 06/08/30: Re: Performance Appraisals
108098: 06/09/05: Re: Please help me with (insert task here)
112290: 06/11/19: Re: board - T562.jpg
112593: 06/11/25: Re: board - T562.jpg
112600: 06/11/25: Re: board - T562.jpg
112619: 06/11/26: Re: board - T562.jpg
112628: 06/11/26: Re: board - T562.jpg
112674: 06/11/27: Re: Was: board - T562.jpg, Now: Switched cap voltage regulator
114205: 07/01/07: Re: Basic questions about digital phase locked loop
129560: 08/02/27: Re: ADC to FPGA Interface Webcast
145461: 10/02/10: Re: Tieing Off Unused Pins in Quartus II Blocks
Jim Toerresen:
3331: 96/05/14: Evolvable HW
3369: 96/05/22: Re: Evolvable HW
3408: 96/05/25: Re: Evolvable HW
Jim Tompkins:
53: 94/08/04: Intel iFX questions
199: 94/09/19: PLD for async state machine?
1808: 95/09/05: FPGA to masked gate array conversion
Jim Wang:
72257: 04/08/12: Can PPC in V2P reconfig the FPGA slices?
72265: 04/08/12: Re: Attention Xilinx: command line tools would be useful [Was: Re: why?]
Jim Watts:
28772: 01/01/24: Re: APEX
28773: 01/01/24: Re: Fixing pins on Spartan II
28774: 01/01/24: Re: About programming cables
28775: 01/01/24: Re: VHDL question
Jim Weir:
2730: 96/01/31: Re: GAL programming for hobby use...Is there no hope?
11570: 98/08/24: Re: New Evolutionary Electronics Book
Jim West:
3283: 96/05/09: Re: What EPLD system to buy ?
Jim Wu:
52617: 03/02/16: Re: VITAL_primitives Library in Xilinx WebPack
52640: 03/02/17: Re: Measuring die temperature
52653: 03/02/18: Re: Xilinx Filter
52703: 03/02/19: Re: WebPack 4.2i and Block RAM instantiation
52705: 03/02/19: Re: crc implementation
52832: 03/02/24: Re: Program a Serial Data Flash - SPI - Interface through a CPLD via JTAG
52884: 03/02/25: Re: Program a Serial Data Flash - SPI - Interface through a CPLD via JTAG
53082: 03/03/03: Re: Bus Functional Model
53083: 03/03/03: Re: Startup latency...
53170: 03/03/05: Re: Startup latency
53172: 03/03/05: Re: Bus Functional Model
53231: 03/03/07: Re: JTAG
58566: 03/07/26: Re: Simple circuit / good design?
58943: 03/08/04: Re: how to protect own IP in Xilinx ISE
58981: 03/08/05: Re: model sim block ram sim
59024: 03/08/06: Re: How to use EAB in Altera FPGA?
59027: 03/08/06: Re: How to use EAB in Altera FPGA?
59032: 03/08/06: Does Xilinx Webpack 5.2 work on WinNT SP6?
59033: 03/08/06: Re: power saving condition test ?
59054: 03/08/07: Re: power saving condition test ?
59066: 03/08/07: Re: How to find the intersection of two vectors?
59151: 03/08/10: Re: a quick searching problem
59166: 03/08/11: Re: Upgrading OS or WebPack
59191: 03/08/11: Re: a quick searching problem
59197: 03/08/12: Data Structure Viewer
59251: 03/08/13: Re: Error please Help
59261: 03/08/13: Re: Error please Help
59363: 03/08/16: Re: xilinx PAR removing Logic
59378: 03/08/17: Re: custom memory array implementaion
59762: 03/08/28: Re: Help ! compxlib Error " mti_se not found" while Bulding XILINX libraries for ModelSim SE
59779: 03/08/28: Re: Implementing FIFO in Spartan-II
59943: 03/09/02: Re: how to design this datapath unit for DSP using VHDL/Verilog?
61624: 03/10/08: Re: ASIC/FPGA programming
63089: 03/11/14: Re: Reading back SRAM content via JTAG?
63139: 03/11/16: Re: Reading back SRAM content via JTAG?
67854: 04/03/21: Re: How do I read the INIT values in blockRAM?
67875: 04/03/22: Re: How do I read the INIT values in blockRAM?
68556: 04/04/08: Re: how to use a .ucf file?
68640: 04/04/12: Re: Problems installing ISE 6.2 under Linux
68915: 04/04/22: Re: Compiling library problem in Xilinx ISE4.0?
69314: 04/05/06: Re: bitgen progarm in ISE
69357: 04/05/07: Re: Error while simulation with XILINX DCM
69358: 04/05/07: Re: ChipScope Core Generator Flow
69554: 04/05/13: Re: program flash memory through JTAG on FPGA
69562: 04/05/14: Re: instantiate an edf module with ise
69870: 04/05/23: Re: Reg learning FPGA backend
71132: 04/07/09: Re: Synthesis failure Xilinx WebPack XST
71521: 04/07/21: Re: Area constraint on a sub-module
72245: 04/08/12: Looking for suggestions/recommendations on 64-bit Linux machine
72710: 04/08/29: Re: Floorplanner RPM question
72742: 04/08/31: Re: Installing Xilinx ISEWebPack under Wine
72784: 04/09/01: Re: Floorplanner RPM question
72831: 04/09/03: Re: Fanout Xilinx
73907: 04/09/30: Re: Xilinx Timing Constraints
73911: 04/09/30: Re: luts are optimized away
75868: 04/11/17: Re: Setup violation warning with constant signal in Modelsim/Webpack
75872: 04/11/17: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
75873: 04/11/17: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
75878: 04/11/17: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
75879: 04/11/17: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
75901: 04/11/18: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
75927: 04/11/19: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
76420: 04/12/01: Re: Stupid tools question...
78393: 05/01/31: Re: Listing unrouted nets in FPGA Editor
78591: 05/02/03: Re: Modifying a post PAR xilinx design
79265: 05/02/16: Re: How to display synplify_pro version in tcl command
79267: 05/02/16: Re: Orcad schematic and footprint libraries for Xilinx Spartan 3 FPGA's
79398: 05/02/18: Re: Input Timing Specification
79788: 05/02/24: Re: How to synthesize the xilinx ip core?
80966: 05/03/15: Re: Calling netlist module in a design
81074: 05/03/17: Re: Using XC2V6000 to send/receive test vectors.
81157: 05/03/18: Re: Using XC2V6000 to send/receive test vectors.
81604: 05/03/28: Re: Xilinx- Extract a pin layout
81605: 05/03/28: Re: using (verilog) reg as memory
81719: 05/03/30: Re: using (verilog) reg as memory
81720: 05/03/30: Re: Xilinx- Extract a pin layout
82108: 05/04/06: Re: Modelsim simulations without ISE
82250: 05/04/09: Re: ISE 7.1 for 64 bit Linux ???
82251: 05/04/09: Re: rules to assign pins to FPGA?
82283: 05/04/10: Re: ISE 7.1 for 64 bit Linux ???
82715: 05/04/16: Re: Xilinx tools from the commandline
83126: 05/04/24: Re: how to put an FIR in an FPGA?
84614: 05/05/23: Re: FSM stops working
86649: 05/07/01: Re: vhdl source code cross reference tool
86835: 05/07/07: Re: Has anybody run Virtex-4 FPGAs at 300MHz+ interface speed?
87374: 05/07/22: Re: DDR SDRAM on ML401
87614: 05/07/27: Re: Xilinx Foundation ISE and WinXP/x64?
87669: 05/07/27: Re: chipscope/impact Virtex4 problem
87706: 05/07/28: Re: XST and TCL support?
88428: 05/08/18: Re: Xilinx ISE on remtoe Display
89328: 05/09/13: Re: ISE 7.1i & Linux / reg code question
89330: 05/09/13: Re: reducing the number of IOBS in a design
91774: 05/11/12: Re: Add files to Xilinx ISE Project w/script
92674: 05/12/04: Re: Virtex 4 IDELAY implementation
93568: 05/12/24: Re: edif to vhd black box
94205: 06/01/07: Re: How to keep the design from Synplify or XST optimizing
94644: 06/01/15: Re: Directed routing in Xilinx V2PRO.
98444: 06/03/10: Re: Virtex-4 DCM CLKFX jitter
98445: 06/03/10: Re: since xilinx ise 8.1 support linux red hat 4.0 (with device Spartan-3 400k)
102122: 06/05/10: Re: Routing problem in PAR.
102194: 06/05/11: Re: Xilinx ISE 8.1 Makefile
102235: 06/05/12: Re: How to check IOB register packing?
102319: 06/05/15: Re: Assigning MGT's in sample Aurora Design
102562: 06/05/17: Re: Hold Time Violations in Virtex4
103529: 06/06/05: Re: Multi place and route
103543: 06/06/05: Re: Webpack larger than CDs
103598: 06/06/06: Re: ISE8.1 on OpenSUSE 64bit
103640: 06/06/07: Re: Problems with ISE logic optimization
103641: 06/06/07: Re: ISE8.1 on OpenSUSE 64bit
103984: 06/06/16: Re: Virtex2-Pro local clocking...
104774: 06/07/05: Re: Incorporating CoreGen files in EDK 8.1 peripheral
104828: 06/07/06: Re: Can a BUFGMUX drive a global clock in the Spartan-3?
104937: 06/07/10: Re: LUT4 INIT value to implement 2:1 MUX ?
105047: 06/07/12: Re: Diffenrential I/Os in Virtex-4
105672: 06/07/28: Re: 4VSX35 LOC placements?
105698: 06/07/28: Re: 4VSX35 LOC placements?
105757: 06/07/31: Re: Core Generator
105820: 06/08/01: Re: Usage of DDR IOBs
105988: 06/08/04: Re: RocketIO simulation in VCS
106068: 06/08/07: Re: How do I treat "default" case which is useless?
106507: 06/08/14: Re: RocketIO MGT Tile/Column Question
106769: 06/08/18: Re: Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE 8.2 SP2
106773: 06/08/18: Re: Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE 8.2 SP2
106780: 06/08/18: Re: Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE 8.2 SP2
106912: 06/08/22: Re: ModelSim SE PLUS 6.1B. Problem to simulate RocketIO in GT_CUSTOM mode
107601: 06/08/30: Re: Location of Virtex4 ASCII pinout tables
108695: 06/09/15: Re: General Tips of reading Verilog Code
108731: 06/09/15: Re: Critcal path in XILINX ISE (XST)
109698: 06/10/03: Re: How to create a library for a Xilinx project
109724: 06/10/04: Re: How to create a library for a Xilinx project
110929: 06/10/25: Re: Supported bus widths for RLDRAM on Virtex4?
111644: 06/11/07: Re: ISE/EDK project on a file server?
111760: 06/11/09: Re: Xilinx ISE ucf management
111761: 06/11/09: Re: tri0 GSR = glbl.GSR;
111958: 06/11/13: Re: MPMC2: MPMC2 with DDR2 SDRAM
111959: 06/11/13: Re: How to control the running of NC-Sim and Xilinx ISE under Unix?
111960: 06/11/13: Re: Xilinx ISE ucf management
112965: 06/12/02: Re: LUT input order
112967: 06/12/02: Re: LUT input order
113100: 06/12/06: Re: Clock phase shift
113132: 06/12/06: Re: Usage of BUFIO in Virtex 4?
113133: 06/12/06: Re: Usage of BUFIO in Virtex 4?
113187: 06/12/07: Re: Xilinx PAR crashing with 'make'
113223: 06/12/08: Re: source synchronous timing (Xilinx)
113653: 06/12/18: Re: jtag reset seq
113877: 06/12/27: Re: assigned a special pins in ISE
114189: 07/01/06: Re: dynamically created blockRAM contents?
114884: 07/01/25: Re: Any UK mirror for ISE 8.2i SP2?
114901: 07/01/25: Re: OrCAD symbol for the Xilinx V5LX50 FF676 device
114927: 07/01/26: Re: Forcing a LUT to not be optimized
115792: 07/02/20: Re: How to get the area/time results without IO mapping
115909: 07/02/24: Re: How to specify ISE INST constraint with GENERATE statements?
116127: 07/03/01: Re: Regional Clock Network and Large Designs
116157: 07/03/02: Re: Potential problem in batch files for Xilinx [was SCons build tool as an alternative to makefiles]
116256: 07/03/05: Re: Multiple devices within one ISE project
116293: 07/03/06: Re: Potential problem in batch files for Xilinx
116785: 07/03/18: Re: init of FPGA's Block-RAMs.
117045: 07/03/22: Re: Manual LUT - AND function mapping problem
117133: 07/03/23: Re: Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF
119536: 07/05/22: Re: SelectIO banking rules
119818: 07/05/26: Re: IOSTANDARD user constrain
120432: 07/06/06: Re: How many OSERDES per bufio
120485: 07/06/07: Re: How many OSERDES per bufio
120824: 07/06/18: Re: Xilinx FPGA Pinout spreadsheets
120892: 07/06/19: Re: .xco file and vcs verilog compiler
121631: 07/07/10: Re: DDR SDRAM simulation model, ML300, Infineon
123101: 07/08/16: Re: Virtex 4 IBUFG to DCM routing question
123127: 07/08/16: Re: Virtex 4 IBUFG to DCM routing question
123640: 07/08/31: Re: Is it possible to make bit files generated by Xilinx ISE readable?
126606: 07/11/28: Re: Global Reset using Global Buffer
126610: 07/11/28: Re: SLICEL : 92%,SLICEM 2%
127125: 07/12/12: Re: I try to Tri-Mode Embedded EMAC
127587: 08/01/03: Re: Xilinx, How to generate PAD file, from the UCF file
128175: 08/01/17: Re: Chipscope compatible with Synopsis or Cadence sythesise tools?
131398: 08/04/21: Re: How to instantiate macro in verilog
131399: 08/04/21: Re: Xilinx DDR2 Interface
133379: 08/06/26: Re: FPGA area use by module?
133390: 08/06/26: Re: mapping error
133391: 08/06/26: Re: mapping error
133784: 08/07/14: Re: How to prevent mapper stripping when synthesizing without IO
136063: 08/10/29: Re: MPMC and DDR2 Simulation
143785: 09/10/25: Re: looking for documents.
144239: 09/11/22: Re: How to script Xilinx ISE - xflow, batch file, tcl, ?
144709: 09/12/26: Re: Data2MEM - finding the blockrams after PAR?
145909: 10/02/27: Re: FPGA Editor - Post Route Simulation after changes in Ncd file
145915: 10/02/27: Re: Derived clock violation in Virtex4
147132: 10/04/14: Re: Module wise FPGA resource utilization report
151500: 11/04/14: Re: Virtex-5 GTP with oversampling
Jim-Green:
71047: 04/07/06: Re: Looking for Fax software
<jim.brakefield@ieee.org>:
157025: 14/09/03: Re: Know any good public FPGA projects to contribute to?
157027: 14/09/03: Re: Know any good public FPGA projects to contribute to?
157029: 14/09/03: Re: Know any good public FPGA projects to contribute to?
157034: 14/09/03: Re: Know any good public FPGA projects to contribute to?
157036: 14/09/04: Re: Know any good public FPGA projects to contribute to?
157038: 14/09/04: Re: Know any good public FPGA projects to contribute to?
157042: 14/09/05: Re: Know any good public FPGA projects to contribute to?
157368: 14/11/29: Re: Low-end FPGA mezzanine standard
157417: 14/12/03: Re: Which Altera to buy?
157610: 15/01/04: Re: Low-end FPGA mezzanine standard
157702: 15/02/07: Re: Topics for Projects on FPGA+Computer Archtecture
157849: 15/04/20: Re: Choosing the right FPGA board
158120: 15/08/11: Re: Finally! A Completely Open Complete FPGA Toolchain
158231: 15/09/26: Soft core processors: RISC versus stack/accumulator for equal FPGA resources
158239: 15/09/27: Re: Soft core processors: RISC versus stack/accumulator for equal
158240: 15/09/27: Re: Soft core processors: RISC versus stack/accumulator for equal
158242: 15/09/27: Re: Soft core processors: RISC versus stack/accumulator for equal
158319: 15/10/20: Re: Sum of 8 numbers in FPGA
158326: 15/10/22: Re: Sum of 8 numbers in FPGA
158947: 16/05/27: Re: Advice to a newbie
158967: 16/05/29: Re: Advice to a newbie
158976: 16/05/30: Re: Advice to a newbie
159361: 16/10/15: Re: CORDIC in a land of built-in multipliers
159428: 16/11/04: Re: Quad-Port BlockRAM in Virtex
159663: 17/01/26: Re: Hardware floating point?
159699: 17/02/12: Re: All-real FFT for FPGA
160399: 18/01/11: Re: HDL simple survey - what do you actually use
160567: 18/04/14: Re: FPGA selection recommendation
160580: 18/04/21: engineered data path versus inferred data path
160584: 18/04/27: Re: engineered data path versus inferred data path
160589: 18/04/30: Re: engineered data path versus inferred data path
160612: 18/05/25: Re: Very low pin count FPGA
160759: 18/11/10: Re: New(ish) FPGA Company
160864: 18/12/09: Re: Help with Pmod VGA on Altera
161086: 19/01/30: Re: Altera Cyclone replacement
161088: 19/01/30: Re: Altera Cyclone replacement
161476: 19/10/16: Re: Tiny CPUs for Slow Logic
161480: 19/10/25: Re: EDIF as machine language
161482: 19/10/25: Re: EDIF as machine language
161493: 19/11/08: Re: FPGA config sizes
161691: 20/04/16: Re: CPU Softcore Compendium
<Jim.Granville@gmail.com>:
114022: 07/01/02: Re: xilinx xc9536?
<jim.tavacoli@gmail.com>:
157171: 14/10/23: Re: USB PHY recommendations
157334: 14/11/24: Re: Program IO 1.2V
157611: 15/01/05: Re: Low-end FPGA mezzanine standard
158210: 15/09/14: Re: IMX6 Solo - FPGA Module
jim2345:
115449: 07/02/11: FPGA configuration direct from PLX
Jim_B:
102265: 06/05/12: Re: difference of variable and signal
106003: 06/08/04: Re: Synplify
Jim_L_Williams@hotmail.com:
101672: 06/05/04: New To FPGA, Program question
Jim_Thompson:
9942: 98/04/15: Re: MY SEMICONDUCTOR LINKPAGE
31446: 01/05/24: Re: frequency ramp
Jimbo:
57507: 03/07/01: Spartan-3 and Xilinx' PLB Gigabit Ethernet MAC
63951: 03/12/09: programming with sockets on Xilinx Virtex2Pro
<JimboD2@gmail.com>:
123489: 07/08/28: Problems with PLB_DDR2 core and soft reset
123510: 07/08/29: Re: Problems with PLB_DDR2 core and soft reset
126064: 07/11/13: REFCLK signal in Hard TEMAC core
126148: 07/11/15: V4FX: Cannot access EMAC1 of Dual MAC system
126149: 07/11/15: Re: V4FX: Cannot access EMAC1 of Dual MAC system
126178: 07/11/16: Re: V4FX: Cannot access EMAC1 of Dual MAC system
126203: 07/11/16: Re: V4FX: Cannot access EMAC1 of Dual MAC system
126209: 07/11/16: Re: V4FX: Cannot access EMAC1 of Dual MAC system
jimboluke:
69842: 04/05/21: USB HUB?
JimBrakefd:
3586: 96/07/01: Re: HELP:Foundation VHDL on WIN95
Jimcde:
4348: 96/10/18: price conversion from FPGA to gate array
jimgeorge at gmail dot com:
86575: 05/06/30: PROM Generation question
86590: 05/06/30: Re: PROM Generation question
86746: 05/07/05: Re: Ethernet FPGA development board
86747: 05/07/05: Re: interpolation in FPGA
JimLewis:
140295: 09/05/07: Re: Seeding random number generator
141985: 09/07/20: Re: Using OPEN in port map
142194: 09/07/28: Re: Using OPEN in port map
142368: 09/08/06: Re: Using OPEN in port map
142565: 09/08/17: Re: Using carry chain of counters for term count detect
142613: 09/08/20: Re: Using carry chain of counters for term count detect
147423: 10/04/26: Re: confusion with ADC/DAC interface implementation
148683: 10/08/17: Re: Dumb VHDL Question -- Type Conversion
<jimmeans@my-dejanews.com>:
10711: 98/06/11: Re: Are you looking for a good VHDL/Verilog Editor?
10755: 98/06/16: Re: AHDL vs. VHDL vs. Verilog HDl
10756: 98/06/16: Re: Wallace trees
10945: 98/07/06: Re: Consultants
11035: 98/07/13: Re: Howto: CRC's and PRBS in Parallel
Jimmie:
31376: 01/05/21: Maximum clock frequency to expect in Xilinx Virtex FPGA ?
Jimmy:
17949: 99/09/18: test
17966: 99/09/19: Located VCC & GND?
23542: 00/06/29: Maximum Speed on obtainable on FPGAs?
55582: 03/05/13: CLK_SIGNAL CONSTRAINT
55614: 03/05/14: Re: CLK_SIGNAL CONSTRAINT
64458: 04/01/05: maxplus 2 waveform simulation
69902: 04/05/24: VHDL simple question: is 2-D array synthesizable
69906: 04/05/24: Re: VHDL simple question: is 2-D array synthesizable
70052: 04/05/31: VHDL warning " Feedback mux " from synplify pro ...thx
70562: 04/06/21: VDHL implementation of RAM with serial input and parallel outpout ? thx
70711: 04/06/24: Divided by 11 in VHDL
70969: 04/07/03: VHDL in Xilinx : why this signal is regarded as Global Clock ?
71620: 04/07/25: Modelsim: No default binding for component
71626: 04/07/26: Re: Modelsim: No default binding for component
72680: 04/08/28: how can I simulate the vhdl and verilog mixed design in modelsim?
jimmy:
34092: 01/08/14: WinMe installation
34126: 01/08/15: Re: WinMe installation
51210: 03/01/07: Help for LeonardoSpectrum LS2002d_22
Jimmy Roberts:
24885: 00/08/21: Mealy vs Moore FSM model
24924: 00/08/22: Re: Mealy vs Moore FSM model
29086: 01/02/05: Re: who wants to work in France ????
jimmy roberts:
22227: 00/05/02: Foundation question.
jimmy siu:
34101: 01/08/14: Re: WinMe installation
Jimmy zhang:
73200: 04/09/15: adder VS increment
Jimmy Zhang:
40920: 02/03/18: questions from a newby
40960: 02/03/19: simple Free FPGA tool
41045: 02/03/20: low cost PCI spartan board needed
41046: 02/03/20: Re: low cost PCI spartan board needed
41082: 02/03/20: Re: low cost PCI spartan board needed
41115: 02/03/21: more questions
41116: 02/03/21: Re: more questions
41118: 02/03/21: Re: low cost PCI spartan board needed
41156: 02/03/21: PCI interface
41175: 02/03/22: another from newbie
41641: 02/04/04: hand placement
41695: 02/04/05: Re: hand placement
41697: 02/04/05: again this hand placement thing
53551: 03/03/16: 16 adder latency
53781: 03/03/22: synthesizability question
58307: 03/07/20: CRC questions
58326: 03/07/21: Re: CRC questions
58881: 03/08/04: Re: two questions
59085: 03/08/08: fast read, slow write memory
<jimmy75@my-deja.com>:
24356: 00/08/04: Virtex system gate count
24386: 00/08/06: Re: FPGA selection
24388: 00/08/06: Help!! Virtex system gate count.
24396: 00/08/06: Re: Help!! Virtex system gate count.
24455: 00/08/09: Re: Help!! Virtex system gate count.
28784: 01/01/24: Advice on FPGA board.
28835: 01/01/25: Re: Advice on FPGA board.
<jimmydunstan@yahoo.com>:
132342: 08/05/22: ISE 10.1 FPGA Editor
JimWall:
8343: 97/12/09: Re: what is metastability time of a flip_flop
<jimwalsh142@hotmail.com>:
105847: 06/08/01: Programmable pulse generator
105866: 06/08/02: Re: Programmable pulse generator
105880: 06/08/02: Re: Programmable pulse generator
jimwu88NOOOSPAM@yahoo.com:
87401: 05/07/22: Re: DDR SDRAM on ML401
87522: 05/07/25: Re: How to look inside a RAM memory
87729: 05/07/29: Re: GLCKs on Spartan3
94685: 06/01/16: Re: Directed routing in Xilinx V2PRO.
101210: 06/04/27: UCF-mode for Emacs
101277: 06/04/28: Re: Xilinx: Prohibit propagation of timing constraint through a mux
101472: 06/05/01: Re: ISE 8.1 Comment Bug, Very hideous
101655: 06/05/04: Re: Virtex 4 LX25
101735: 06/05/05: Re: Virtex 4 LX25
145939: 10/02/28: Re: free waveform drawing tool
Jimy:
57828: 03/07/07: wired downloading bitstream to spartan2
Jin Cheng:
74156: 04/10/04: Help on test RocketIO loopback
Jinan Lou:
6579: 97/06/03: Your recommendation needed
Jing:
52119: 03/02/01: Xilinx SwitchBox Structure
52120: 03/02/01: Xilinx's XDL
52152: 03/02/03: Re: Xilinx SwitchBox Structure
88371: 05/08/16: Re: XC5200 tool help needed
Jing Kwok:
1329: 95/06/02: Re: Appologies : Any company for conversion FPGA to ASIC?
<jing_pang@my-deja.com>:
25764: 00/09/19: GPS design with xilinx board
25766: 00/09/19: GPS design with xilinx board
Jingjing (Amy) Hu:
50288: 02/12/07: Virtex archtecture question
Jinhua Li:
30748: 01/04/26: Virtex-II: Clock-to-PAD Issue
<jinkeles@hotmail.com>:
124513: 07/09/25: Re: Never buy Altera!!!!
Jinsang Kim:
32530: 01/06/29: Clock Speed using Modern ASIC technology
JinSoo Kim:
46132: 02/08/19: Good documentation on CPLD
<jinyinglu@gmail.com>:
136643: 08/11/27: help! how to pipeline a non-restoring divider in verilog
136645: 08/11/27: Re: help! how to pipeline a non-restoring divider in verilog
Jiri Bucek:
89184: 05/09/07: Re: Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a
Jiri Gaisler:
23591: 00/07/02: Re: Anyone tried the Virtex dev. board from Avnet?
34285: 01/08/18: Re: Development boards
Jiri Plasil:
110950: 06/10/26: Re: FIR filter generic
jiri_gaisler:
77871: 05/01/19: Comparison of LEON2, Microblaze and Openrisc processors
77877: 05/01/19: Re: Comparison of LEON2, Microblaze and Openrisc processors
78026: 05/01/23: Re: Xilinx: xst internal error
78088: 05/01/24: Re: Comparison of LEON2, Microblaze and Openrisc processors
78344: 05/01/30: Re: i need xilinx edk
Jiten:
107678: 06/08/30: Number of Modules in a Verilog File
113419: 06/12/13: Maplib Error 661.
jitendra:
90412: 05/10/12: Re: DDR constraints in Xilinx/UCF, Synplicity?
122749: 07/08/06: new to the group
<jithinpremvas@gmail.com>:
130258: 08/03/18: problem with edk9.2
jj:
12155: 98/10/01: Re: Synthesis: Exemplar or Synopsys
12358: 98/10/09: Re: Software tool
27619: 00/11/30: Orca 3t sram gsr question
JJ:
70931: 04/07/02: Re: *RANT* Ridiculous EDA software "user license agreements"?
79845: 05/02/24: Re: Implementing Multi-Processor Systems in FPGAs
79909: 05/02/25: Re: Implementing Multi-Processor Systems in FPGAs
79958: 05/02/26: Re: Implementing Multi-Processor Systems in FPGAs
80609: 05/03/08: Re: Asynchronous processor !?!
80665: 05/03/09: Re: Xilinx vs Altera high-end solutions
80973: 05/03/15: Re: Memory gate count in ASIC and in FPGA
81013: 05/03/16: Re: Need recommendation on an FPGA board with a USB socket.
81053: 05/03/16: Re: Need recommendation on an FPGA board with a USB socket.
81071: 05/03/17: Re: Which HDL?
81167: 05/03/18: Re: Which HDL?
81430: 05/03/23: Re: PowerPC soft-core?
81601: 05/03/28: Re: C++ code to FPGA
81646: 05/03/29: Re: C++ code to FPGA
81774: 05/03/31: Re: FPGA board--host PC, need 20-50 Mbps speed, USB2, PCI or 1394?
81819: 05/04/01: Transputer delivery
81825: 05/04/01: Re: 4/1
81831: 05/04/01: Re: Transputer delivery
81945: 05/04/04: Re: can c++ code be loaded to a hardware PGA coprocessor card
81979: 05/04/05: Re: Reverse engineering ASIC into FPGA
81984: 05/04/05: Re: Structural vs Behavioral
81992: 05/04/05: Re: Structural vs Behavioral
81998: 05/04/05: Re: Book?
82027: 05/04/05: Re: ISA vs. patent/trademark
82117: 05/04/06: Re: ISA vs. patent/trademark
82137: 05/04/07: Re: Reverse engineering ASIC into FPGA
82155: 05/04/07: Re: Interesting article about Xilinx FPGAs in the new Cray
82167: 05/04/07: Re: ISA vs. patent/trademark
82285: 05/04/10: Re: Neural Networks in FPGA
82305: 05/04/10: Re: Neural Networks in FPGA
82435: 05/04/12: Re: General question about soft CPUs
82663: 05/04/15: Re: Hobby or job? (FPGA User's groups anyone?)
82722: 05/04/16: Re: The DLP from Texas Instruments...
82729: 05/04/16: Re: The DLP from Texas Instruments...
82751: 05/04/17: Re: Spartan 3E slower that Spartan 3?
82778: 05/04/17: Re: LUT in fpga
82809: 05/04/18: Re: Missing post
82862: 05/04/18: Re: Declining a job offer
82903: 05/04/19: Re: Declining a job offer
82933: 05/04/19: Re: College Project
83070: 05/04/22: Re: VHDL or Verilog
83118: 05/04/23: Re: CAM for FPGA ...
83401: 05/04/28: Re: How to implement this C function in FPGA
83453: 05/04/29: Re: How to implement this C function in FPGA
83668: 05/05/04: Re: Does this group allow JobPostings?
83670: 05/05/04: Re: Saturating an integer
84076: 05/05/12: Re: Xilinx versus Elixent; other radically different concepts?
84199: 05/05/14: Re: newbie question
84204: 05/05/14: Re: floorplanning
84205: 05/05/14: Re: floorplanning
84219: 05/05/15: Re: FPGA design under Mac OS X ?
84220: 05/05/15: Re: floorplanning
84221: 05/05/15: Re: floorplanning
84224: 05/05/15: Re: floorplanning
84246: 05/05/16: Re: Universal logic modules vs NAND-like modules
84389: 05/05/18: Re: FPGA design under Mac OS X ?
84450: 05/05/19: Re: Why do VHDL gate level models simulate slower than verilog
84736: 05/05/25: Re: VHDL vs. Schematic Capture
84878: 05/05/31: Re: What is a typical job scope when FPGAs are involved?
85050: 05/06/03: Re: Protecting IP in China
85239: 05/06/06: Re: Hope for OS X tools...
85265: 05/06/07: Re: Fast/low area Sorting hardware.
85595: 05/06/11: Re: computer upgrade time.
85599: 05/06/11: Re: Best Practices for Hardware Designers
85913: 05/06/17: Re: Idea exploration - Image stabilization by means of software.
85956: 05/06/18: Re: Ideal CPU for FPGA?
85969: 05/06/19: Re: Ideal CPU for FPGA?
86139: 05/06/22: Re: Ideal CPU for FPGA?
86350: 05/06/26: Chess & FPGAs
86400: 05/06/27: Re: FPGA PC104 development board
86472: 05/06/28: Re: proth siever in FPGA?
86510: 05/06/29: Re: proth siever in FPGA? [LONG]
86847: 05/07/07: Re: about fast adder
86930: 05/07/09: Re: Announce: Impulse C-to-RTL Version 2 now available
87231: 05/07/19: Re: Ones Count 64 bit on Xilinx in VHDL
87296: 05/07/20: Re: Ones Count 64 bit on Xilinx in VHDL
87369: 05/07/22: Re: Ones Count 64 bit on Xilinx in VHDL
87372: 05/07/22: Re: Ones Count 64 bit on Xilinx in VHDL
88006: 05/08/05: Re: Good intro books on OFDM?
88492: 05/08/19: Re: Best FPGA for floating point performance
88497: 05/08/19: Re: Best FPGA for floating point performance
88499: 05/08/19: Re: Best FPGA for floating point performance
88781: 05/08/28: Re: Best FPGA for floating point performance
88791: 05/08/28: Re: Best FPGA for floating point performance
88812: 05/08/29: Re: Best FPGA for floating point performance
88814: 05/08/29: Re: Best FPGA for floating point performance
88815: 05/08/29: Re: Best FPGA for floating point performance
88857: 05/08/30: Re: Best FPGA for floating point performance
88860: 05/08/30: Re: 8087 co-processor
88862: 05/08/30: Re: Embedded Processors/Serdes
88863: 05/08/30: Re: Fine grain vs. Coarse Grain Architectures
89342: 05/09/13: Re: CPU benchmark for Xilinx PAR
89343: 05/09/13: Re: P&R speed higher than synthesis
89461: 05/09/15: Re: Small (OEM-)Memory Modules (SRAM/FLASH/DRAM)
89524: 05/09/17: Re: Software tools for architectural diagrams and for timing diagram entry?
89726: 05/09/23: Re: C-to-gates experiences
90811: 05/10/21: Re: Implementing five stage pipeline
90834: 05/10/21: Re: Implementing five stage pipeline
90855: 05/10/23: Re: Implementing five stage pipeline
90857: 05/10/23: Re: Implementing five stage pipeline
90867: 05/10/24: Re: Implementing five stage pipeline
90877: 05/10/24: Re: verilog code
91021: 05/10/27: Re: Cost to go from FPGA to ASIC
92060: 05/11/21: Re: FFT on an FPGA
92490: 05/11/30: Re: systemC vs VHDL
93549: 05/12/24: Re: RTL for Z8000 series CPU?
93781: 05/12/30: Re: Can some give me some advice?
95764: 06/01/25: Very very OT but Floating Point FPU +> current news murder story
95773: 06/01/25: Re: Very very OT but Floating Point FPU +> current news murder story
96923: 06/02/13: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
97235: 06/02/19: Re: FPGA - software or hardware?
97248: 06/02/19: Re: FPGA - software or hardware?
97283: 06/02/20: Re: Cheating at homework (from "Re: FPGA - software or hardware?"t
97333: 06/02/20: Re: state-of-the-art schematic generation? [Was: SCHEMATICS ... ]
97383: 06/02/21: Re: Is FPGA code called firmware?
97424: 06/02/22: Re: FPGA - software or hardware -2-
97426: 06/02/22: Re: Is FPGA code called gateware?
97550: 06/02/23: Re: Is FPGA code called gateware?
97836: 06/02/28: Re: How do I make dual-port RAM from single port RAM?
97872: 06/02/28: Re: How do I make dual-port RAM from single port RAM?
97873: 06/03/01: Re: How do I make dual-port RAM from single port RAM?
97943: 06/03/02: Re: How do I make dual-port RAM from single port RAM?
98293: 06/03/08: ISE 8.1: simulation modelsm & tbw generated in Verilog instead of VHDL?!
98382: 06/03/09: Re: for all those who believe in ASICs....
98552: 06/03/12: Re: Question about multi write ports RAM in FPGA?
98656: 06/03/14: Re: Question about multi write ports RAM in FPGA?
98718: 06/03/15: Re: Question about multi write ports RAM in FPGA?
98720: 06/03/15: Re: Question about multi write ports RAM in FPGA?
98814: 06/03/16: Re: Urgent Help Needed!!!!!
98840: 06/03/17: Re: Urgent Help Needed!!!!!
98892: 06/03/17: Re: Urgent Help Needed!!!!!
99092: 06/03/20: Re: Urgent Help Needed!!!!!
99814: 06/03/29: Re: OpenSPARC released
99868: 06/03/30: Re: OpenSPARC released
99869: 06/03/30: Re: H.O.T. II - Virtual Computer Corp Hardware Object Technology Development System
100898: 06/04/20: Re: fpga space estimate
101285: 06/04/28: Opteron HT coprocessors
101298: 06/04/28: Re: Opteron HT coprocessors
101333: 06/04/28: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
101335: 06/04/28: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
101336: 06/04/28: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
101337: 06/04/28: Re: Opteron HT coprocessors
101794: 06/05/06: Re: FPGA-based hardware accelerator for PC
101795: 06/05/06: Re: Opteron HT coprocessors
101800: 06/05/06: Re: FPGA-based hardware accelerator for PC
101803: 06/05/06: Re: RFID chip has battary in it or not
101804: 06/05/06: Re: RFID chip has battary in it or not
101830: 06/05/07: Re: FPGA-based hardware accelerator for PC
101927: 06/05/08: Re: FPGA-based hardware accelerator for PC
101928: 06/05/08: Re: FPGA-based hardware accelerator for PC
101930: 06/05/08: Re: FPGA-based hardware accelerator for PC
101966: 06/05/08: Re: FPGA-based hardware accelerator for PC
101969: 06/05/08: Re: FPGA-based hardware accelerator for PC
101971: 06/05/08: Re: RFID chip has battary in it or not
102002: 06/05/09: Re: FPGA-based hardware accelerator for PC
102023: 06/05/09: Re: Superscalar Out-of-Order Processor on an FPGA
102024: 06/05/09: Re: Xilinx 3s8000?
102033: 06/05/09: Re: Superscalar Out-of-Order Processor on an FPGA
102045: 06/05/09: Re: Superscalar Out-of-Order Processor on an FPGA
102102: 06/05/10: Re: Superscalar Out-of-Order Processor on an FPGA
102104: 06/05/10: Re: Opteron HT coprocessors
102106: 06/05/10: Re: FPGA-based hardware accelerator for PC
102108: 06/05/10: Re: FPGA-based hardware accelerator for PC
102120: 06/05/10: Re: Superscalar Out-of-Order Processor on an FPGA
102126: 06/05/10: Re: Xilinx 3s8000?
102186: 06/05/11: Re: reverse engineering ?
102208: 06/05/11: Re: reverse engineering ?
102210: 06/05/11: Re: Multiple Write Port Register Files
102212: 06/05/11: Re: reverse engineering ?
102558: 06/05/17: Re: disappointing 550Mhz performance of V5 DSP slices
102577: 06/05/17: Re: disappointing 550Mhz performance of V5 DSP slices
102581: 06/05/17: Re: "disappointing" performance
102942: 06/05/23: Re: Superscalar Out-of-Order Processor on an FPGA
102955: 06/05/23: Re: Verilog vs VHDL
103031: 06/05/24: Re: Verilog vs VHDL
103795: 06/06/11: Re: from VHDL to FPGA
103799: 06/06/12: Re: from VHDL to FPGA
104221: 06/06/21: Re: cache aware programming
104568: 06/06/29: Re: How to evaluate the space efficiency of a historic design.
104608: 06/06/30: Re: Spartan3e starter kit vga mod
104674: 06/07/03: Re: Chaos in FF metastability
104809: 06/07/06: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104826: 06/07/06: Re: Fastest platform to run ISE?
104895: 06/07/08: Re: Fastest platform to run ISE?
105309: 06/07/19: Re: Sorting algorithm for FPGA availlable?
105350: 06/07/20: Re: Sorting algorithm for FPGA availlable?
105370: 06/07/20: Re: Hardware book like "Code Complete"?
106041: 06/08/06: Re: verilog versus vhdl
106187: 06/08/08: Re: verilog versus vhdl
106923: 06/08/22: Re: CPU design
109490: 06/09/27: Re: PERISHABLE PAPER RELATED TO FPGA!
110737: 06/10/20: Re: i486 FPGA replacement
111192: 06/10/30: Re: Fastest ISE Compile PC?
111427: 06/11/02: Re: Scientific Computing on FPGA
111482: 06/11/03: Re: Scientific Computing on FPGA
111489: 06/11/03: Re: Fastest ISE Compile PC?
111492: 06/11/03: Re: Scientific Computing on FPGA
111859: 06/11/11: Re: using FPGAs for synthesizing?
112085: 06/11/15: Re: 8080 FSGA model in an FPGA
112213: 06/11/17: Re: 8080 FSGA model in an FPGA
112804: 06/11/29: Re: FPGA workstation - should I wait for Window Vista?
113301: 06/12/10: Re: FPGA+Ethernet
114067: 07/01/03: Re: FPGA ROUTING
114112: 07/01/04: Re: iterative algorithms + tightly coupled CPU with cloud of logic in FPGA
<jj6WhhpEL@yahoo.com>:
<jj_okocha@my-deja.com>:
24529: 00/08/12: Help!! Bit serial Baugh-Wooley multiplier
24586: 00/08/14: Help!!! Bit serial Baugh-Wooley multiplier
24640: 00/08/16: Re: Help!!! Bit serial Baugh-Wooley multiplier
<jjchristman13@gmail.com>:
157867: 15/04/28: Interested in VHDL and FPGA Development?
159130: 16/08/15: BASYS 3 Board
Jjdur Ukfjg:
33508: 01/07/28: Re: The Continuing Saga of Installing Modelsim software on Windows 2000
33509: 01/07/28: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
<"jjfakas@erols.com"@erols.com>:
5434: 97/02/15: Re: X84 board VHDL examples
5435: 97/02/15: Re: HELP: XC4000 download cable
5436: 97/02/15: Re: HELP: XC4000 download cable
<jjfakas@erols.com>:
4614: 96/11/20: FPGA TEST BOARDS
jjl:
60134: 03/09/05: Low-cost FPGA Development Board with built-in Computer core
60220: 03/09/08: Re: Low-cost FPGA Development Board with built-in Computer core
60221: 03/09/08: Re: VGA display
jjlarkin:
18193: 99/10/06: Re: Altera 10K50V in-rush/temp problem...
18207: 99/10/07: Re: Multiplierless FIR filters in FPGAs
Jjletodoc:
77285: 05/01/03: Nios II & obj copy this Unknown!!!!!
<jjlhke@best2web.comNOSPAM>:
jjlindula@hotmail.com:
81031: 05/03/16: Using DSP Builder with Quartus
84809: 05/05/27: Incremental Compilation in Quartus 4.2
85598: 05/06/11: Best Practices for Hardware Designers
85627: 05/06/12: Re: Best Practices for Hardware Designers
86857: 05/07/07: Max Sample Rate for Signal Tap in Altera Quartus?
86902: 05/07/08: Re: Max Sample Rate for Signal Tap in Altera Quartus?
86941: 05/07/10: Re: Max Sample Rate for Signal Tap in Altera Quartus?
87012: 05/07/12: Safe State Machine Design in AHDL
87330: 05/07/21: Best Practices to Manage Complexity in Hardward/Software Design?
87595: 05/07/26: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87895: 05/08/03: Re: System Engineering in the R/D World
88139: 05/08/10: FPGA Programming using Block Design Files or Graphic Design Files
88151: 05/08/10: Re: FPGA Programming using Block Design Files or Graphic Design Files
88152: 05/08/10: Re: FPGA Programming using Block Design Files or Graphic Design Files
88319: 05/08/15: AHDL Abandoned in Quartus?
93145: 05/12/14: Incremental Compilation in Quartus 5.1?
103656: 06/06/07: Incrmental Compilation in Quartus 5.1
103675: 06/06/07: Rumor Control:: Will Quartus phase out supporting AHDL?
107625: 06/08/30: Performance Appraisals
108862: 06/09/18: Max Sample Rate using Signal Tap in Quartus 6.0?
109515: 06/09/27: Is it worth learning SOPC Builder, DSP Builder & Nios Processor?
112826: 06/11/29: Stratix II GX Transceivers
112896: 06/11/30: Re: Stratix II GX Transceivers
112905: 06/11/30: Re: Stratix II GX Transceivers
113222: 06/12/08: Implementing DVI EDID on Stratix II GX?
113790: 06/12/21: What next next big thing coming for HDL?
113868: 06/12/26: Re: What next next big thing coming for HDL?
113879: 06/12/27: Why AHDL didn't catch on like Verilog or VHDL?
113892: 06/12/28: Re: What next next big thing coming for HDL?
114044: 07/01/03: Using Altera's SerialLite to create a high-speed data link between Two or more FPGA's
114095: 07/01/04: Re: Using Altera's SerialLite to create a high-speed data link between Two or more FPGA's
114165: 07/01/05: Help Implementing an 1000Base-T Ethernet on Stratix II GX
118453: 07/04/26: Quartus Fitter Seed Setting
119675: 07/05/24: Dual Core or Quad Core when running Quartus 7.1
120395: 07/06/06: Quartus Advisors
120691: 07/06/13: Incremental Compilation in Altera Quartus II version 7.1
120715: 07/06/14: Re: Incremental Compilation in Altera Quartus II version 7.1
120716: 07/06/14: Using LogicLock in Altera Quartus II
121328: 07/07/02: Choosing the EPC16 or the EPCS64 for Stratix II
121876: 07/07/14: Image Resolution Rescaling
121888: 07/07/14: Re: Image Resolution Rescaling
131026: 08/04/08: Starting a PCI Express Application
131447: 08/04/21: Newbie: Testbench question
131449: 08/04/21: Re: Newbie: Testbench question
131474: 08/04/22: Re: Newbie: Testbench question
131564: 08/04/25: Re: Newbie: Testbench question
132285: 08/05/20: Instantiating an lpm dcfifo in Verilog
132293: 08/05/20: Re: Instantiating an lpm dcfifo in Verilog
136300: 08/11/10: Altera Quartus DDR2 Megacore function: local_address input: row, col,
136301: 08/11/10: Re: Altera Quartus DDR2 Megacore function: local_address input: row,
136305: 08/11/10: Re: Altera Quartus DDR2 Megacore function: local_address input: row,
136306: 08/11/10: Re: Altera Quartus DDR2 Megacore function: local_address input: row,
136311: 08/11/10: Re: Altera Quartus DDR2 Megacore function: local_address input: row,
144913: 10/01/14: SystemVerilog Verification Example using Quartus and ModelSim
144922: 10/01/15: Re: SystemVerilog Verification Example using Quartus and ModelSim
144923: 10/01/15: Re: SystemVerilog Verification Example using Quartus and ModelSim
144932: 10/01/15: Re: SystemVerilog Verification Example using Quartus and ModelSim
145026: 10/01/20: Re: SystemVerilog Verification Example using Quartus and ModelSim
<jjlindula@hotmail.com>:
87887: 05/08/03: System Engineering in the R/D World
87905: 05/08/03: Re: System Engineering in the R/D World
87914: 05/08/03: Re: System Engineering in the R/D World
87919: 05/08/03: Re: System Engineering in the R/D World
87920: 05/08/03: Re: System Engineering in the R/D World
87956: 05/08/04: Re: System Engineering in the R/D World
<jjohnson@cs.ucf.edu>:
78636: 05/02/04: PPC on Virtex2P: Jumpstart, recommended reading?
83496: 05/05/01: Virtex4 and ISE reality check?
87088: 05/07/14: Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?
88657: 05/08/24: Re: Good SystemC tutorials or books?
90221: 05/10/06: Re: matrix inversion in hardware
90223: 05/10/06: DDR constraints in Xilinx/UCF, Synplicity?
90225: 05/10/06: Virtex4 shift register layout: Horizontal or vertical?
90272: 05/10/07: Re: DDR constraints in Xilinx/UCF, Synplicity?
122400: 07/07/26: Best CPU platform(s) for FPGA synthesis
122447: 07/07/27: Re: Best CPU platform(s) for FPGA synthesis
122668: 07/08/02: Re: Best CPU platform(s) for FPGA synthesis
122677: 07/08/02: Re: Static Timing Analysis Using Primetime for FPGAs
122678: 07/08/02: Re: Altera-Xilinx interfacing SERDES transcievers problem
124827: 07/10/05: Opteron performance tuning (for Quartus / Linux)?
124859: 07/10/08: Re: Opteron performance tuning (for Quartus / Linux)?
<jjoker@aol.com>:
31512: 01/05/29: Make a little extra cash !!!
jjplaw:
146589: 10/03/23: Xilinx ISE Tcl Script Error
146617: 10/03/23: Re: Xilinx ISE Tcl Script Error
146651: 10/03/25: Re: Xilinx ISE Tcl Script Error
<jjumbo@netsystemsusa.cjb.net>:
JK:
115737: 07/02/18: best way to get 4xclk
115738: 07/02/18: Re: best way to get 4xclk
115739: 07/02/18: Re: best way to get 4xclk
115746: 07/02/19: Re: best way to get 4xclk
115866: 07/02/22: Re: porting virtex2-pro into virtex4. Performance!!
117096: 07/03/22: multiple clock domain issues
117146: 07/03/23: Re: multiple clock domain issues
119193: 07/05/14: Re: how to choose the perfect fpga support
123173: 07/08/18: Re: Routing JTAG pins thru FPGA
127342: 07/12/18: Re: multidimensional arrays in VHDL?
129437: 08/02/23: Re: Xilinx DCM for frequency synthesis -- newbie question
129525: 08/02/26: Re: Xilinx DCM for frequency synthesis -- newbie question
129687: 08/03/03: Re: Xilinx DCM for frequency synthesis -- newbie question
150792: 11/02/11: Re: Looking for Level Shifter supporting dual voltage 3.3V/2.9V and 1.8V
Jk:
146442: 10/03/18: Bus Master DMA with PCI Express
jk:
64417: 04/01/03: Newbie Question: Compiling VHDL in Mentor Graphics
64617: 04/01/09: Newbie Question: No Vsim, Vlib etc in my ModelSim
64751: 04/01/13: Re: Newbie Question: No Vsim, Vlib etc in my ModelSim
64752: 04/01/13: Integer or Binary Vector?
JKB:
63169: 03/11/17: ISE 4.2 sp3 (Solaris)
Jkkfjf:
37937: 01/12/26: Re: availability of VirtexII production silicon
jkljljklk:
129444: 08/02/24: Re: Problem with PINs XC3S700A-4FG484
129445: 08/02/24: Re: Problem with PINs XC3S700A-4FG484
129464: 08/02/25: Re: Problem with PINs XC3S700A-4FG484
130028: 08/03/13: Re: Matlab, RS-232, Ethernet
131539: 08/04/24: Re: the order in which some switches are turned on
146596: 10/03/23: Re: Standard cell library help
<jkrshnan.v@gmail.com>:
156332: 14/03/11: Re: Ball-park price of Xilinx Virtex 7 FPGA?
jku:
33967: 01/08/09: Re: Virtex-II prototyping board
JL:
94861: 06/01/18: How to NON_CLK pin that messes my clock
94863: 06/01/18: Re: How to NON_CLK pin that messes my clock
94867: 06/01/18: Re: How to NON_CLK pin that messes my clock
94919: 06/01/19: Re: How to NON_CLK pin that messes my clock
94918: 06/01/19: Re: How to NON_CLK pin that messes my clock
94943: 06/01/19: Re: How to NON_CLK pin that messes my clock
96344: 06/02/02: Modelsim error when doing: port map(a => not(b))
96345: 06/02/02: Re: Modelsim error when doing: port map(a => not(b))
96412: 06/02/03: Xilinx: generic tristates and multiplexers
96433: 06/02/03: Re: Xilinx: generic tristates and multiplexers
96561: 06/02/06: Arbiter for several wires competing
96593: 06/02/07: Re: Arbiter for several wires competing
96651: 06/02/08: Re: Arbiter for several wires competing
104722: 06/07/05: Weird timing failure
<jlamontagne@my-deja.com>:
19639: 00/01/05: FPGA and SW Engineering opportunities in CT
<jlamorie@engsoc.carleton.ca>:
20631: 00/02/16: How to manage projects with Xilinx?
20669: 00/02/17: Re: How to manage projects with Xilinx?
20774: 00/02/21: Re: Advanced Digital Design book
<jlarkin@highlandsniptechnology.com>:
161498: 19/11/09: Re: FPGA config sizes
jleslie48:
136411: 08/11/14: rank beginner here, need to know where to start to get RS232 comm's
136419: 08/11/15: Re: rank beginner here, need to know where to start to get RS232
136455: 08/11/17: Re: rank beginner here, need to know where to start to get RS232
136466: 08/11/18: Re: rank beginner here, need to know where to start to get RS232
137232: 09/01/05: beginner synthesize question - my debounce process won't synthesize.
137243: 09/01/05: Re: beginner synthesize question - my debounce process won't
137244: 09/01/05: Re: beginner synthesize question - my debounce process won't
137247: 09/01/05: Re: beginner synthesize question - my debounce process won't
137254: 09/01/06: Re: beginner synthesize question - my debounce process won't
137265: 09/01/06: Re: beginner synthesize question - my debounce process won't
137267: 09/01/06: Re: beginner synthesize question - my debounce process won't
137284: 09/01/07: Re: beginner synthesize question - my debounce process won't
137286: 09/01/07: Re: beginner synthesize question - my debounce process won't
137310: 09/01/08: Re: beginner synthesize question - my debounce process won't
137312: 09/01/08: Re: beginner synthesize question - my debounce process won't
137324: 09/01/08: Re: beginner synthesize question - my debounce process won't
137388: 09/01/13: Re: beginner synthesize question - my debounce process won't
137400: 09/01/14: Re: beginner synthesize question - my debounce process won't
137405: 09/01/14: Re: beginner synthesize question - my debounce process won't
137523: 09/01/21: Re: rank beginner here, need to know where to start to get RS232
137524: 09/01/21: Re: rank beginner here, need to know where to start to get RS232
137529: 09/01/21: Re: rank beginner here, need to know where to start to get RS232
137568: 09/01/22: Re: rank beginner here, need to know where to start to get RS232
137574: 09/01/22: Re: rank beginner here, need to know where to start to get RS232
137581: 09/01/22: Re: Problems when I download and install Xilinx ISE 10.1. Help
137613: 09/01/23: problem with test bench should be an easy one.
137614: 09/01/23: Re: problem with test bench should be an easy one.
137648: 09/01/26: Got UART Working!!! need syntax help with using ascii/buffer
137651: 09/01/26: Re: Got UART Working!!! need syntax help with using ascii/buffer
137652: 09/01/26: Re: Got UART Working!!! need syntax help with using ascii/buffer
137654: 09/01/26: Re: Got UART Working!!! need syntax help with using ascii/buffer
137657: 09/01/26: Re: Got UART Working!!! need syntax help with using ascii/buffer
137672: 09/01/27: Re: Got UART Working!!! need syntax help with using ascii/buffer
137673: 09/01/27: Re: Got UART Working!!! need syntax help with using ascii/buffer
137683: 09/01/27: Re: Got UART Working!!! need syntax help with using ascii/buffer
137686: 09/01/27: Re: Got UART Working!!! need syntax help with using ascii/buffer
137687: 09/01/27: Re: Got UART Working!!! need syntax help with using ascii/buffer
137688: 09/01/27: now what is this? iMPACT:2356 - Platform Cable USB firmware must be
137689: 09/01/27: Re: now what is this? iMPACT:2356 - Platform Cable USB firmware must
137692: 09/01/27: Re: now what is this? iMPACT:2356 - Platform Cable USB firmware must
137694: 09/01/27: Re: now what is this? iMPACT:2356 - Platform Cable USB firmware must
137705: 09/01/27: Re: Got UART Working!!! need syntax help with using ascii/buffer
137741: 09/01/28: UART RS232 "hello world" program trial and terror.
137745: 09/01/28: new source wizard doesn't seem to work.
137778: 09/01/29: Re: new source wizard doesn't seem to work.
137779: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
137785: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
137786: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
137787: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
137788: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
137790: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
137799: 09/01/29: Re: new source wizard doesn't seem to work.
137807: 09/01/29: Re: new source wizard doesn't seem to work.
137818: 09/01/30: Re: new source wizard doesn't seem to work.
137820: 09/01/30: Re: new source wizard doesn't seem to work.
137825: 09/01/30: Re: UART RS232 "hello world" program trial and terror.
137830: 09/01/30: Re: UART RS232 "hello world" program trial and terror.
137842: 09/01/31: semi OT: FPGA and Paper models.
137967: 09/02/03: rs232 uart: testbench vs real world, and the missing first letter.
137970: 09/02/03: Re: rs232 uart: testbench vs real world, and the missing first
137980: 09/02/03: Re: rs232 uart: testbench vs real world, and the missing first
137981: 09/02/03: Re: rs232 uart: testbench vs real world, and the missing first
137986: 09/02/03: Re: rs232 uart: testbench vs real world, and the missing first
137989: 09/02/03: Re: rs232 uart: testbench vs real world, and the missing first
137991: 09/02/03: Re: rs232 uart: testbench vs real world, and the missing first
137992: 09/02/03: Re: rs232 uart: testbench vs real world, and the missing first
137993: 09/02/03: Re: rs232 uart: testbench vs real world, and the missing first
137995: 09/02/03: Re: rs232 uart: testbench vs real world, and the missing first
138031: 09/02/04: Re: rs232 uart: testbench vs real world, and the missing first
138054: 09/02/04: Re: rs232 uart: testbench vs real world, and the missing first
138077: 09/02/05: Re: rs232 uart: testbench vs real world, and the missing first
138081: 09/02/05: Re: rs232 uart: testbench vs real world, and the missing first
138083: 09/02/05: Re: rs232 uart: testbench vs real world, and the missing first
138102: 09/02/06: Re: rs232 uart: testbench vs real world, and the missing first
138114: 09/02/06: Re: rs232 uart: testbench vs real world, and the missing first
138121: 09/02/06: Re: rs232 uart: testbench vs real world, and the missing first
138142: 09/02/07: Re: rs232 uart: testbench vs real world, and the missing first
138238: 09/02/10: Re: rs232 uart: testbench vs real world, and the missing first
138243: 09/02/10: Re: rs232 uart: testbench vs real world, and the missing first
138247: 09/02/10: Re: rs232 uart: testbench vs real world, and the missing first
138249: 09/02/10: Re: rs232 uart: testbench vs real world, and the missing first
138271: 09/02/11: Re: rs232 uart: testbench vs real world, and the missing first
138275: 09/02/11: Re: rs232 uart: testbench vs real world, and the missing first
138298: 09/02/13: "ERROR:Simulator - Failed to link the design. Check to see if any
138300: 09/02/13: Re: "ERROR:Simulator - Failed to link the design. Check to see if any
138302: 09/02/13: UART RS232 "hello world" really taking shape now.
138328: 09/02/16: Re: UART RS232 "hello world" really taking shape now.
138335: 09/02/16: Re: UART RS232 "hello world" really taking shape now.
138340: 09/02/16: "Type of xxx is incompatible with type of yyy." typecasting error.
138343: 09/02/16: Re: "Type of xxx is incompatible with type of yyy." typecasting
138355: 09/02/17: Re: "Type of xxx is incompatible with type of yyy." typecasting
138398: 09/02/19: RS232 UART: Hello world program finally done.
138503: 09/02/25: VHDL programmer position available in Northern NJ-- westwood, NJ
139095: 09/03/20: How big is my vhdl and am I approaching some size limitation on the
139098: 09/03/20: Re: How big is my vhdl and am I approaching some size limitation on
139099: 09/03/20: Re: How big is my vhdl and am I approaching some size limitation on
139107: 09/03/20: Re: How big is my vhdl and am I approaching some size limitation on
139110: 09/03/20: Re: How big is my vhdl and am I approaching some size limitation on
139121: 09/03/21: Re: How big is my vhdl and am I approaching some size limitation on
139125: 09/03/21: Re: How big is my vhdl and am I approaching some size limitation on
139126: 09/03/21: Re: How big is my vhdl and am I approaching some size limitation on
139127: 09/03/21: Re: How big is my vhdl and am I approaching some size limitation on
139129: 09/03/21: Re: How big is my vhdl and am I approaching some size limitation on
139139: 09/03/21: Re: How big is my vhdl and am I approaching some size limitation on
139140: 09/03/21: Re: How big is my vhdl and am I approaching some size limitation on
139147: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139148: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139154: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139157: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139158: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139174: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139176: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139181: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139183: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139184: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139188: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139528: 09/04/02: Spectrum digital's xds510 usb jtag VS Xilinx Platform Cable USB are
139529: 09/04/02: Re: Can I capture the jtag TDO pin of a Spartan3AN
139545: 09/04/02: clock multipliers, dividers, and more clocks...
139548: 09/04/02: Re: clock multipliers, dividers, and more clocks...
139554: 09/04/02: Re: clock multipliers, dividers, and more clocks...
139701: 09/04/09: warning:impact:2217 error shows in the status register, CRC Error Bit
139743: 09/04/11: Re: warning:impact:2217 error shows in the status register, CRC Error
139746: 09/04/11: Re: warning:impact:2217 error shows in the status register, CRC Error
139865: 09/04/17: fpga locks up with slow signal, spartan chip, pin type issues.
139869: 09/04/17: even with re-run all old elements are still in there using ISE 10.1?
139871: 09/04/17: Re: even with re-run all old elements are still in there using ISE
139874: 09/04/17: Re: warning:impact:2217 error shows in the status register, CRC Error
139875: 09/04/17: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139891: 09/04/18: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139903: 09/04/18: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139905: 09/04/18: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139915: 09/04/19: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139945: 09/04/20: FPGA lockup with pinout report view. was: fpga locks up with slow
139946: 09/04/20: Re: FPGA lockup with pinout report view. was: fpga locks up with slow
139949: 09/04/20: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139955: 09/04/20: Re: FPGA lockup with pinout report view. was: fpga locks up with slow
139957: 09/04/20: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139962: 09/04/20: Re: FPGA lockup with pinout report view. was: fpga locks up with slow
139970: 09/04/21: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139972: 09/04/21: partial workaround found! was:Re: fpga locks up with slow signal,
139975: 09/04/21: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139976: 09/04/21: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139996: 09/04/22: Re: fpga locks up with slow signal, spartan chip, pin type issues.
140002: 09/04/23: Re: fpga locks up with slow signal, spartan chip, pin type issues.
140010: 09/04/23: Re: fpga locks up with slow signal, spartan chip, pin type issues.
140099: 09/04/28: a basics question: using input pins, pullup, short to ground vs
140104: 09/04/28: Re: a basics question: using input pins, pullup, short to ground vs
140105: 09/04/28: Re: a basics question: using input pins, pullup, short to ground vs
140106: 09/04/28: Re: a basics question: using input pins, pullup, short to ground vs
140107: 09/04/28: Re: a basics question: using input pins, pullup, short to ground vs
140108: 09/04/28: Re: a basics question: using input pins, pullup, short to ground vs
140109: 09/04/28: Re: a basics question: using input pins, pullup, short to ground vs
140113: 09/04/28: Re: a basics question: using input pins, pullup, short to ground vs
140114: 09/04/28: Re: a basics question: using input pins, pullup, short to ground vs
140721: 09/05/22: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140723: 09/05/22: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140730: 09/05/22: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140799: 09/05/26: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140813: 09/05/26: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140847: 09/05/27: phase locking a slow (2Mhz) signal.
140861: 09/05/27: Re: phase locking a slow (2Mhz) signal.
140862: 09/05/27: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140884: 09/05/28: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140887: 09/05/28: Re: phase locking a slow (2Mhz) signal.
140890: 09/05/28: Re: phase locking a slow (2Mhz) signal.
140894: 09/05/28: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140910: 09/05/29: Re: phase locking a slow (2Mhz) signal.
140916: 09/05/29: Re: phase locking a slow (2Mhz) signal.
140920: 09/05/29: Re: phase locking a slow (2Mhz) signal.
140956: 09/05/31: Re: phase locking a slow (2Mhz) signal.
140982: 09/06/01: Re: phase locking a slow (2Mhz) signal.
141018: 09/06/02: Re: phase locking a slow (2Mhz) signal.
142013: 09/07/21: building a card reader into a virtex 2 or 5 based FPGA device.
142060: 09/07/23: Re: building a card reader into a virtex 2 or 5 based FPGA device.
152649: 11/09/22: comparing Xilinx XC3S500E-4CPG132C vs Altera Cyclone IV FPGA
152656: 11/09/23: Re: comparing Xilinx XC3S500E-4CPG132C vs Altera Cyclone IV FPGA
jluisky:
97729: 06/02/26: Re: VGA specification
JM:
9412: 98/03/11: Xilinx M1.4 tools on DEC Alpha based NT PCs ?
160254: 17/08/29: Re: Microsemi FPGAs
<jma@gotham.super.org>:
2036: 95/10/05: >Received: by digitech.co.nz (UUPC/extended 1.12o);
3519: 96/06/13: >Received: from mailserv.esat.kuleuven.ac.be by netcomsv.netcom.com with SMTP (8.6.12/SMI-4.1)
jmariano:
100543: 06/04/11: spartan-3 starter kit board
100572: 06/04/12: Re: spartan-3 starter kit board
101420: 06/04/30: Microblaze GPIO (basic) question
101896: 06/05/08: Installing BFM toolkit
102160: 06/05/11: Re: Installing BFM toolkit
103589: 06/06/06: GPIO problem
103947: 06/06/15: Re: GPIO problem
104220: 06/06/21: Spartan-3 starter kit strange problem
104264: 06/06/22: Re: Spartan-3 starter kit strange problem
118439: 07/04/26: Sscanf replacement for xilinx EDK
118468: 07/04/27: Re: Sscanf replacement for xilinx EDK
119058: 07/05/10: Accessing SRAM on the Spartan-3 Starter Board
119090: 07/05/11: Re: Accessing SRAM on the Spartan-3 Starter Board
143367: 09/10/06: Ideas for a pulse programmer needed
147627: 10/05/09: I hit the wall
148962: 10/09/15: interrupt handler arguments
148996: 10/09/20: Re: interrupt handler arguments
153952: 12/07/02: accumulator (again)
153965: 12/07/05: Re: accumulator (again)
153970: 12/07/05: Re: accumulator (again)
153992: 12/07/09: Re: accumulator (again)
157869: 15/05/01: Spartan-3 stater kit
157871: 15/05/01: Re: Spartan-3 starter kit
157874: 15/05/02: Re: Spartan-3 stater kit
157877: 15/05/06: Re: Spartan-3 starter kit
JMB_FPGA:
80069: 05/03/01: Has anyone tried the "LogicPort" 34 channel 500MHz logic analyzer?
80070: 05/03/01: Re: Has anyone tried the
<jmcdonald@eg3.com>:
23785: 00/07/08: FPGA Internet Resources - Updated
<jmcgibbon@aics.net>:
10804: 98/06/21: Re: [Question] Xilinx Foundation FPGA Express..
jmdrake:
66761: 04/02/26: Re: Dual-stack (Forth) processors
66762: 04/02/26: Re: Dual-stack (Forth) processors
66809: 04/02/26: Re: Dual-stack (Forth) processors
jmfbahciv:
145455: 10/02/10: Re: using an FPGA to emulate a vintage computer
145475: 10/02/11: Re: using an FPGA to emulate a vintage computer
145496: 10/02/12: Re: using an FPGA to emulate a vintage computer
145701: 10/02/19: Re: using an FPGA to emulate a vintage computer
jmiles@pop.net:
140497: 09/05/15: Re: FPGA+FX2 API for Digilent Nexys 2 (was Programming... from Linux)
144589: 09/12/17: Re: TCP/IP offload in hardware
144993: 10/01/18: Re: XST is driving me mad.
145219: 10/02/01: Re: Connecting ADC chip to sparta 3 a dsp
146648: 10/03/25: Re: Digilent Nexys2 board
149050: 10/09/27: Re: Xilinx XST and a State Machine - A Mystery
jmn:
29551: 01/02/26: Re: Rijndael
JMN:
41895: 02/04/10: Re: Compiling the addone.c example from DK1
jmorken:
15450: 99/03/24: Re: big/little endian mishap
15454: 99/03/24: Re: big/little endian mishap
15455: 99/03/24: Re: big/little endian mishap
jmoui:
114576: 07/01/19: Re: Beginner VHDL questions
<jms019@gmail.com>:
88489: 05/08/19: Kingston module structure
<jms@geriatrix.circlesXXXXXquared.com>:
28686: 01/01/21: UK parts
jmthorne:
984: 95/04/07: Looking for informition
jmunir:
145135: 10/01/29: In system memory editor of Altera for Xilinx
145147: 10/01/29: Re: In system memory editor of Altera for Xilinx
<jneil@harris.com>:
78998: 05/02/10: RocketIO in 32-bit Mode
<jnewton@embeddedsol.com>:
23025: 00/06/09: VirtexE Readback Parameters
Jo:
22446: 00/05/09: FPGA Development - EDA Administration
23821: 00/07/11: Electronic Design Automation - UK
40915: 02/03/18: simulating Core in ISE 4.1, + ModelSim
Jo Dale Carothers:
3474: 96/06/05: Low Power Special Issue
3476: 96/06/05: New Deadline---IPCCC'97 CFP
Jo Depreitere:
192: 94/09/16: Re: Address of VIRTUAL COMPUTERS Inc ???
1011: 95/04/13: Re: I-Cube - contact information ?
1707: 95/08/18: Re: high pinout - low logic devices
3545: 96/06/18: CLB size
11050: 98/07/15: Re: high-speed place and route
11059: 98/07/16: Re: high-speed place and route
13307: 98/11/25: Foundation Schematic Entry
15117: 99/03/08: Foundation Express: Edit Constraints
15121: 99/03/08: Re: Foundation Express: Edit Constraints
15246: 99/03/16: Inferring IO's
15248: 99/03/16: Re: Inferring IO's
15250: 99/03/16: Re: Inferring IO's
15274: 99/03/17: Re: Inferring IO's
15275: 99/03/17: Re: Inferring IO's
15546: 99/03/30: Re: VHDL source code
15773: 99/04/13: Placement constraints on LOGIBLOX instances
20068: 00/01/26: Re: Anyone changed an NT disk serial number?
Jo Kenens:
35447: 01/10/05: Xilinx XST synthesis signal naming
Jo Kenens (no_spam no_spam no_spam):
52924: 03/02/26: configuring xilinx fpga with nand flash
52933: 03/02/26: Re: configuring xilinx fpga with nand flash
53228: 03/03/07: Re: PCMCIA to IDE interface
Jo Parmer:
31101: 01/05/11: FPGA Design Engineer-Austin, TX
Jo Pletinckx:
63991: 03/12/11: ISE5.2i strange behavior in PAR (command-line)
64016: 03/12/12: Re: ISE5.2i strange behavior in PAR (command-line)
71357: 04/07/15: MUXCY-based multiplexers
71359: 04/07/15: Re: MUXCY-based multiplexers
Jo Schambach:
88488: 05/08/19: USB Blaster
Jo Van Langendonck:
17187: 99/07/07: PCI interface
Jo?o M. P. Cardoso:
72424: 04/08/18: CFP: International Workshop on Applied Reconfigurable Computing (ARC 2005)
74288: 04/10/07: International Workshop on Applied Reconfigurable Computing (ARC): 2nd call for papers
77932: 05/01/20: International Workshop on Applied Reconfigurable Computing ARC2005 - CALL FOR PARTICIPATION
Joachim:
55439: 03/05/08: SystemC and Virtex-E
joachim:
116725: 07/03/16: Re: How to generate sgmii interface?
Joachim =?ISO-8859-1?Q?F=F6rster?=:
140294: 09/05/07: Re: OpenCores CAN/Ethernet cores
Joachim =?iso-8859-1?Q?Str=F6mbergson?=:
30551: 01/04/15: Getting license for Modelsim in Xilinx webpack?
Joachim Hoch:
22484: 00/05/10: Re: Xilinx Student Edition 1.5 License.dat
Joachim Mann:
61760: 03/10/10: Problems with PCI-CardbusCard (interface is an FPGA) on Windows
Joachim Schueth:
41510: 02/03/31: Re: Homebuilt Altera-programmer totally dead...
Joachim Strombergson:
8955: 98/02/09: x86 soft cores?
14033: 99/01/08: Re: =?iso-8859-1?Q?G=F6mmer=20gris=F6ron=2E=2E=2E?=
26487: 00/10/18: Re: Announce: Free HC11 CPU Core
26523: 00/10/19: More errata. (Was: Re: Announce: Free HC11 CPU Core)
Joachim Strömbergson:
6058: 97/04/08: Reconfig computing and multimedia?
7398: 97/09/06: Hard-soft development for reconfig computing?
joan rodo:
53843: 03/03/25: Programming fpga
Joan@Actel:
148617: 10/08/06: Re: Generic parameters in Actel Libero SmartDesign Components
Joanne Moores:
77284: 05/01/03: Re: PCBs for modern FPGAs.
Joao Geada:
1969: 95/09/26: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
Joao Manuel Paiva Cardoso:
16437: 99/05/21: Re: High Speed Reconfigurability
<job@amontec.com>:
128615: 08/01/31: Re: Design security for pre-Virtex2 parts ?
128693: 08/02/04: forcing "Unused IOB Pin -> " from .ucf
129198: 08/02/18: Re: Antti needs a job
129590: 08/02/28: Re: DCM Simulation : Input Clock Cycle Jitter
129619: 08/02/29: Re: Is there any way to disable JTAG for Sptantan3AN
129952: 08/03/11: Re: BRAM synthesis question
129955: 08/03/11: Re: BRAM synthesis question
130050: 08/03/14: Re: Actel PA3 with DirectC or SVF, anybody had any success?
130058: 08/03/14: Re: Actel PA3 with DirectC or SVF, anybody had any success?
130060: 08/03/14: Re: Actel PA3 with DirectC or SVF, anybody had any success?
130064: 08/03/14: Re: Actel PA3 with DirectC or SVF, anybody had any success?
130321: 08/03/20: Re: Configure Spartan-3E w SD-Card?
130327: 08/03/20: Re: Configure Spartan-3E w SD-Card?
130648: 08/03/29: Re: async clk input, clock glitches
130652: 08/03/29: Re: ISE 10.1 - Initial experience
130700: 08/03/30: Re: async clk input, clock glitches
130761: 08/04/01: Re: Simple (?) timing constraint for output pins
130792: 08/04/01: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
131181: 08/04/14: Re: Actel Cortex
137342: 09/01/09: Re: OpenOCD / FTDI2232 / JTAG/ Virtex
137343: 09/01/09: Re: JTAG USB interface
<job_mine@my-deja.com>:
25723: 00/09/18: Empoyment
<jobeck@imtek.de>:
124726: 07/10/02: Virtex4: ISERDES -> FIFO -> BlockRAM fails
<jobs@chrysal.com>:
3441: 96/05/30: ASIC/FPGA ENGINEERS WANTED
Jochen:
57238: 03/06/26: Re: Everything need a reset?
79781: 05/02/24: Re: Multiple addition(2)
80280: 05/03/03: Re: IBUFG as ? component
82140: 05/04/07: Re: DCM LOCKED as reset
82556: 05/04/13: Re: "The ISE 7.1 Experience"
82576: 05/04/14: Re: Fitting functionality in an XC2VP30 FPGA.
82640: 05/04/15: Re: different I/O buffers available inXilinx FPGA
83949: 05/05/10: Re: true dual port memory v/s simple dual port memory
84374: 05/05/18: Re: VHDL array question
84448: 05/05/19: Re: Xilinx V2Pro DCM config and settling time questions
84461: 05/05/19: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
85341: 05/06/07: Re: Lattice and Mentor seminar info pieces... & ST's new 'uC'+FPGA
85416: 05/06/09: Re: Can I use a 18k ram as 2 single-port ram?
91265: 05/11/02: Re: clock detection
92237: 05/11/24: Re: Xilinx DCM_ADV 280MHz no lock
101495: 06/05/02: Re: Reset
103627: 06/06/06: Re: Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5
105135: 06/07/14: Re: Need for reset in FPGAs
126085: 07/11/14: Re: Xilinx ISE Timing Report Question
128039: 08/01/14: Re: BRAM Readback
134839: 08/09/03: Re: XST bug on illigal states of a FSM ?
134858: 08/09/04: Re: Strange Spartan2 behaviour
134905: 08/09/06: Re: Strange Spartan2 behaviour
135003: 08/09/10: Re: Are Xilinx tools that bad, or am I missing something?
135157: 08/09/18: Re: Moving to Altera from Xilinx
135158: 08/09/18: Re: Xilinx build system
Jochen Frensch:
55544: 03/05/12: Re: PLL in fpga
75860: 04/11/17: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
81498: 05/03/25: Re: Problem with flip-flops on Spartan 3
Jochen Gruber:
11646: 98/08/28: [Fwd: Online education in Mathematical Sciences]
11645: 98/08/28: Online education in Mathematical Sciences
11719: 98/09/03: [Fwd: online education in quantitative sciences]
11718: 98/09/03: online education in quantitative sciences
11820: 98/09/11: Online education in quantitative sciences
Jochen Karrer:
3688: 96/07/16: XC3195 serial-EEPROM dissassembler ?
Jock:
39651: 02/02/15: Modelsim Logo
42408: 02/04/23: Maximum Usage in a Virtex FPGA
49374: 02/11/11: Re: Xilinx POS Power On Surge Current
51551: 03/01/16: Xilinx Constraint Problem
51560: 03/01/16: Re: Xilinx Constraint Problem
51603: 03/01/17: Re: Xilinx Constraint Problem
51759: 03/01/21: Re: Xilinx Constraint Problem
53715: 03/03/20: Configuration of data and clock lines on Flex6016
55238: 03/05/01: Schmitt Trigger an a Virtex
55445: 03/05/08: Re: Schmitt Trigger an a Virtex
63034: 03/11/13: Archiving Projects
75032: 04/10/25: PLL Clocks on Cyclone Devices
75083: 04/10/26: Re: PLL Clocks on Cyclone Devices
74123: 04/10/04: Is it possible to Reverse-Engineer an FPGA Output file?
74527: 04/10/13: Re: simprim errors
80546: 05/03/08: What's the Altera Equivalent of a Xilinx .rbt file?
80618: 05/03/09: Re: What's the Altera Equivalent of a Xilinx .rbt file?
89554: 05/09/19: Reverse Engineering Output Files
<jodoan@my-deja.com>:
21316: 00/03/16: Atmel A29 Series Software Erase
Joe:
19538: 99/12/29: Re: USB2 core call for Volunteers
24801: 00/08/18: Xilinx Xact & Alliance
25997: 00/09/29: Re: Xilinx and CD databooks (rant)
26382: 00/10/13: ModelTech's VHDL Vsim and Xilinx's old XACT place/route
32121: 01/06/14: Re: FPGA comparsion
32122: 01/06/14: Re: From EDF to VHDL?
33399: 01/07/25: Re: Design entry
33400: 01/07/25: Re: PCI arbiter core
33403: 01/07/25: Re: XC4010 ! help please
33482: 01/07/27: Re: XC4010 ! help please
33985: 01/08/09: Re: Which is the best Design Toolchain?
38608: 02/01/18: Shift Register question
43541: 02/05/23: Xact Design Editor 5.1 or later needed!
43695: 02/05/29: Re: How can I create an encrypted netlist for Altera?
49767: 02/11/20: Re: What combinational logic will produce a falling edge only.
49869: 02/11/22: Re: What combinational logic will produce a falling edge only.
53316: 03/03/10: Are there any FPGA magazines/journals?
53362: 03/03/11: Re: Are there any FPGA magazines/journals?
53981: 03/03/29: Re: DSP-FPGA interface
59401: 03/08/18: Re: serial communication between pc and altera fpga
68070: 04/03/25: Re: study verilog or vhdl?
68536: 04/04/07: EDK 6.1: User Logic
69251: 04/05/03: Fast multiplication with Nios and C (Altera Stratix)
69517: 04/05/13: Re: One issue about free hardware
71127: 04/07/08: Re: spartan3 board for newbie: xilinx XC3S200 starter kit or nu-horizons
71431: 04/07/18: Re: Memory width on Spartan-3 boards
71434: 04/07/18: Re: Memory width on Spartan-3 boards
71444: 04/07/18: Re: Memory width on Spartan-3 boards
71883: 04/08/03: Re: adding real UART to xilinx ultracontroller design.
71884: 04/08/03: Re: adding real UART to xilinx ultracontroller design.
71885: 04/08/03: Re: adding real UART to xilinx ultracontroller design.
71886: 04/08/03: Re: adding real UART to xilinx ultracontroller design.
71968: 04/08/04: Re: Manipulation on netlist for faster simulation.
72007: 04/08/05: Re: VGA Signals
73135: 04/09/14: Re: AHB-Slave
74498: 04/10/12: Re: VHDL code for Type and Components
74939: 04/10/21: Re: interfacing a PC based program with a FPGA
75440: 04/11/05: Re: how to get SDF file from netlist
76141: 04/11/25: Re: 386 IP Core
84972: 05/06/02: USB interface With AMBA AHB
85102: 05/06/04: Re: USB interface With AMBA AHB
85132: 05/06/05: Re: USB interface With AMBA AHB
85133: 05/06/05: Re: Basics FPGA
85177: 05/06/06: Re: USB interface With AMBA AHB
85258: 05/06/07: Re: USB interface With AMBA AHB
120704: 07/06/14: LogicSim v3.0 Verilog Simulator is Here!
122379: 07/07/26: LogicSim 3.1 Verilog Simulator Released!
122889: 07/08/09: Re: High Speed ADC
130655: 08/03/29: Announcement: Releasing LogicSim 3.3 and WaveProbe 1.1
joe:
64420: 04/01/03: Response to ALuPin@web.de on high level simulation
64495: 04/01/06: Followup to those that downloaded SeaHDL/SimHDL
68584: 04/04/08: Re: EDK 6.1: User Logic
71387: 04/07/16: Re: Xilinx EDK PCI
126485: 07/11/24: using fpga as programmable connection
126551: 07/11/27: Re: using fpga as programmable connection
Joe Bender:
14940: 99/02/25: Bus Interface
Joe Blake:
3911: 96/08/19: Virtual ISA Proto Board
3923: 96/08/20: Striphex Utility
4703: 96/12/03: Memory Requirements
5055: 97/01/17: Xilinx swap space
joe blogs:
Joe Brunsberger:
11198: 98/07/24: Re: Schematic Symbol Generation
Joe Buck:
701: 95/02/09: Re: [shin]Anyone ported or have patches for OCTTOOLS to Linux?
2042: 95/10/05: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
3935: 96/08/22: Re: INDUSTRY GADFLY: EDA Goes OJ
6082: 97/04/10: Re: prep benchmarks for FPGAs
Joe C.:
29378: 01/02/16: Altera process change....
Joe Chan - łŻ Ä~ ŻŞ:
6841: 97/07/02: Re: HackÉA°o¤X?
Joe Chisolm:
61259: 03/09/30: Re: USB 1.1/2.0 Implementation
93791: 05/12/30: Re: S3e starter kits available
93793: 05/12/30: Re: S3e starter kits available
147445: 10/04/27: Re: Booting Linux from my own bootloader
147889: 10/05/30: Re: Last Xilinx Webpack that was big-brother free?
153596: 12/04/03: Re: Expectations from newly minted EE?
154965: 13/03/04: Re: Farnell increased price on Spartan 6
155831: 13/09/27: Re: Legal Issues Reproducing Old CPU
157185: 14/10/28: Re: XILINX PCIe read of slow device
157243: 14/11/06: Re: practical experience with GPL IP core in commercial product
157252: 14/11/08: Re: practical experience with GPL IP core in commercial product
158804: 16/04/11: Re: Altera HSMC connector
160559: 18/04/14: Re: FPGA selection recommendation
160570: 18/04/15: Re: FPGA selection recommendation
161075: 19/01/30: Re: ARM + FPGA CPU Module running Yocto Linux?
161083: 19/01/30: Re: ARM + FPGA CPU Module running Yocto Linux?
joe christensen:
34113: 01/08/14: Re: finite defect statistics
34114: 01/08/14: Re: finite defect statistics
Joe DeLaere:
71955: 04/08/04: Re: On-Chip Oscillator
Joe Durusau:
27242: 00/11/16: Re: ANNOUNCE: Checksum and CRC Code/Article
Joe Fox:
63080: 03/11/13: Altera MAX3000 device required.
Joe Frese:
48725: 02/10/23: How full is too full?
49051: 02/10/30: How important is simulation?
49135: 02/11/01: Re: How important is simulation?
49136: 02/11/01: Re: UCF files how to use???
51197: 03/01/06: Re: Warnings in FPGA...
55849: 03/05/21: FPGA design: firmware or hardware?
Joe G (Home):
145973: 10/03/03: Re: Help with avoiding ground-loops on my PCB+external
Joe G. Thompson:
2541: 95/12/29: Re: Programmable Interconnect ICs - Repost
Joe Gallegos:
12355: 98/10/09: Re: Verilog Vs VHDL
12351: 98/10/09: Re: clock divider chips
12597: 98/10/19: Re: More: What's wrong at this Address decoder?
13173: 98/11/18: Re: which programing
Joe Gentile, III:
31319: 01/05/18: FPGA consultant needed
Joe Hass:
3043: 96/03/20: Low-power FPGA or EPLD
21668: 00/03/28: Re: FPGA & single point failure
29026: 01/02/02: Re: How different is FPGA design from IC design
62533: 03/10/31: Re: Electronic News Article on 90 nm soft error FUD
Joe Hinrichs:
4853: 96/12/20: Re: ASICs Vs. FPGA in Safety Critical Apps.
Joe Lancaster:
77482: 05/01/07: Synthesis problem
Joe Lavelle:
23876: 00/07/13: Category : Simple UART in VHDL
Joe Lawrence:
45172: 02/07/14: Sensitivity list (VHDL) & FPGA pin assignment
53266: 03/03/09: Extending Existing Micro(controller/processor) Core
61795: 03/10/11: RAM in Xilinx Spartan II
61870: 03/10/14: Re: RAM in Xilinx Spartan II
Joe Linoff:
21662: 00/03/28: Re: Altering Xilinx FPGA version/ID after PAR
Joe Maloney:
637: 95/01/25: Re: Xilinx Marketing Knuckleheads
45962: 02/08/12: Re: BLUETOOTH newbie
Joe Mogenoff:
6045: 97/04/07: test
Joe Peniston:
21713: 00/03/29: redundant multiplier
Joe Pfeiffer:
28284: 01/01/04: Re: Nondeterministic FSMs in hardware?
28318: 01/01/05: Re: Nondeterministic FSMs in hardware?
28319: 01/01/05: Re: Nondeterministic FSMs in hardware?
82042: 05/04/06: Re: ISA vs. patent/trademark
82059: 05/04/06: Re: ISA vs. patent/trademark
82099: 05/04/06: Re: ISA vs. patent/trademark
145413: 10/02/08: Re: using an FPGA to emulate a vintage computer
145417: 10/02/08: Re: using an FPGA to emulate a vintage computer
145808: 10/02/24: Re: using an FPGA to emulate a vintage computer
145809: 10/02/24: Re: using an FPGA to emulate a vintage computer
145854: 10/02/25: Re: using an FPGA to emulate a vintage computer
145884: 10/02/26: Re: using an FPGA to emulate a vintage computer
145953: 10/03/01: Re: using an FPGA to emulate a vintage computer
145977: 10/03/02: Re: using an FPGA to emulate a vintage computer
146114: 10/03/05: Re: using an FPGA to emulate a vintage computer
146144: 10/03/06: Re: using an FPGA to emulate a vintage computer
146155: 10/03/06: Re: using an FPGA to emulate a vintage computer
146187: 10/03/07: Re: using an FPGA to emulate a vintage computer
146190: 10/03/07: Re: using an FPGA to emulate a vintage computer
146223: 10/03/09: Re: using an FPGA to emulate a vintage computer
Joe Sabater:
61820: 03/10/13: Debugging software in an ACEX device with Nios 32 via JTAG
Joe Samson:
599: 95/01/16: Re: ViewLogic simulation without master reset
2185: 95/10/27: Re: Xilinx Configuration Memory Hacking
2352: 95/11/22: Re: Xilinx XACT Windows Version
3086: 96/03/28: Re: Low-power FPGA or EPLD
3113: 96/04/04: Re: Does X-BLOX Work?
4646: 96/11/25: Re: How to utilize XC4000e IOB FFs in Synopsys?
4654: 96/11/26: Re: How to utilize XC4000e IOB FFs in Synopsys?
4967: 97/01/06: Re: wir2xnf problem with NT 4.0 network
Joe Schmo:
6234: 97/04/30: Re: ISP CPLD from AMD or Cypress???
Joe Schulingkamp:
168: 94/09/07: Re: Xilinx and 8.4 -- not!
183: 94/09/14: Re: Xilinx and 8.4 -- not!
Joe Seigh:
82242: 05/04/09: Re: Reverse engineering masked ROMs, PLAs
Joe Thompson:
62755: 03/11/06: Re: Altera "my support" :-(
Joe Troxel:
2436: 95/12/05: Altera Verilog Problems
2836: 96/02/14: re-routing with locked pinout
Joe Vanderwall:
69290: 04/05/04: How to drive record fields from procedure AND testbench?
Joe Vornbrock:
7519: 97/09/18: Re: Atmel 17256 serial config EEPROMs
Joe Wetstein:
22921: 00/06/02: SPICE simulation of circuit board design
22948: 00/06/05: SPICE help
27768: 00/12/06: verilog and arch
30540: 01/04/13: not IOB
32404: 01/06/26: STARTUP block
32406: 01/06/26: Re: IOB FF in Synplicity
Joe Wright:
104815: 06/07/06: Re: How much time does it need to sort 1 million random 64-bit/32-bit
Joe Z:
159535: 16/12/05: Re: Help finding Xilinx software for HW-130 programmer
<joe.delaere@gmail.com>:
89316: 05/09/12: Re: Reprogramming one MAXII EPM1270 vs security bit set
joe4702:
77447: 05/01/06: Re: Xilinx 6.2 to 6.3 upgrade brakes soc
78262: 05/01/27: Re: What's new in MicroBlaze 3.00a?
84181: 05/05/13: Re: Whats going on here?
87340: 05/07/21: Re: EDK 7.1 with ML401 (paging Antti)
89570: 05/09/19: Re: how to set OPB EMC for flash use?
110977: 06/10/26: Re: OPB to SPI clock frequency ratio
110995: 06/10/26: Re: OPB to SPI clock frequency ratio
110996: 06/10/26: Re: OPB to SPI clock frequency ratio
132701: 08/06/05: Re: Xilinx cuts 250 jobs.
<joebird>:
2516: 95/12/22: Re: Gated Clock Problem in Xilinx FPGA Implementation
JoeG:
26793: 00/10/29: I need some VHDL/Synthesis Design BOOK recommendations!!
38614: 02/01/19: Re: Shift Register question
38626: 02/01/19: Re: Shift Register question
56303: 03/06/02: Re: FPGA design: firmware or hardware?
56305: 03/06/02: Re: I want a 800 k gates FPGA in 40 pin DIL
56306: 03/06/02: Re: Need help with Xilinx ISE
56916: 03/06/18: Re: Drive Capabilities of the FPGA
57514: 03/07/01: Re: Xilinx ISE drops support for more parts
59448: 03/08/19: 22V10, ABEL & Current Design Tools?
59450: 03/08/19: Legacy 4005 series and current Xilinx ISE offerings?
59485: 03/08/20: Re: Legacy 4005 series and current Xilinx ISE offerings?
59486: 03/08/20: Re: 22V10, ABEL & Current Design Tools?
59493: 03/08/20: Re: Legacy 4005 series and current Xilinx ISE offerings?
59505: 03/08/20: Re: Legacy 4005 series and current Xilinx ISE offerings?
59532: 03/08/21: Re: Legacy 4005 series and current Xilinx ISE offerings?
62091: 03/10/19: Re: Ph.inisheD.
62092: 03/10/19: Re: To our future engineers, smart and otherwise...
63210: 03/11/18: Re: Xilinx Design entry via Schematic Capture - What tool to use
63211: 03/11/18: Re: Xilinx Design entry via Schematic Capture - What tool to use
65158: 04/01/21: Re: QUES: Where can I find Xilinx M1 tools
82678: 05/04/16: Technical Journals on FPGAs
82769: 05/04/18: Re: salary ballpark please guys
83812: 05/05/07: Re: Using capacitor to slow the rise time.
83832: 05/05/07: Re: Clock delay vs. clock skew
84515: 05/05/20: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84566: 05/05/21: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84567: 05/05/21: Re: VHDL vs. Schematic Capture
84853: 05/05/31: Re: VHDL vs. Schematic Capture
85116: 05/06/05: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
Joel:
84495: 05/05/19: Serial Input Review and Questions
95028: 06/01/20: Re: S3e starter kits available
94103: 06/01/05: XC3S100/250/500E Availability?
102013: 06/05/09: Re: Anyone use Xilinx ppc405 profiling tools?
103403: 06/06/01: Using ChipScope with EDK flow?
103416: 06/06/01: Re: Using ChipScope with EDK flow?
114119: 07/01/04: LatticeMico32 Problem
116740: 07/03/16: Xilinx Synthesis Attribute usage
116754: 07/03/16: Re: Xilinx Synthesis Attribute usage
116758: 07/03/16: Re: Xilinx Synthesis Attribute usage
150164: 10/12/22: Re: Simple ISE Microblaze with GPIO and custom logic example?
150166: 10/12/22: Re: Simple ISE Microblaze with GPIO and custom logic example?
Joel A. Seely:
66340: 04/02/17: Re: makefile to generate memory contents in Altera SOPC Builder
69810: 04/05/20: Re: Nios II Going Live...
Joel BRUNEAU:
20297: 00/02/04: RECHERCHE
Joel Darnauer:
857: 95/03/14: Re: FPGA multi-chip modules ?
Joel Garry:
2757: 96/02/02: Re: Chosing VHDL or Verilog Does Have An Impact For U.S. Engineers
Joel Glickman:
502: 94/12/12: Re: driving PCI
547: 94/12/29: PCI with Xilinx XC3100 series
Joel Hardy:
69336: 04/05/06: Which board to buy? Status of open source tools?
Joel Kolstad:
5786: 97/03/14: Re: Accolade
7380: 97/09/04: Re: ISP Stories
8980: 98/02/11: Re: Can XACT6 run in a NT4 DOS box?
9461: 98/03/15: Suggestions on synthesis/simulation packages under $10K
9495: 98/03/18: Re: Suggestions on synthesis/simulation packages under $10K
11619: 98/08/26: Re: CPLD/FPGA software
11620: 98/08/26: Busses in Xilinx Foundation's schematic capture program
11741: 98/09/06: Re: 22V10 programming
11943: 98/09/20: Dynamic pattern matching in Xilinx FPGAs
12078: 98/09/27: Re: Dynamic pattern matching in Xilinx FPGAs
12079: 98/09/27: Re: Dynamic pattern matching in Xilinx FPGAs
12972: 98/11/08: Why doesn't Xilinx's simulator work?
13693: 98/12/18: Re: Fast *Industrial* 22V10?
14092: 99/01/12: Re: cypress isp cable?
14919: 99/02/25: Re: Xilinx ABEL?
14920: 99/02/25: Where do I connect my reset pins to?
14930: 99/02/25: Re: Where do I connect my reset pins to?
14950: 99/02/26: Re: Xilinx ABEL?
15019: 99/03/03: Clock divider: 100MHz->40MHz
15020: 99/03/03: Asynchronous resets: How tricky?
15029: 99/03/03: Re: Clock divider: 100MHz->40MHz
15043: 99/03/03: Re: Clock divider: 100MHz->40MHz
15124: 99/03/08: Re: Foundation Express: Edit Constraints
15519: 99/03/28: Re: Free Xilinx Vendor Tools ... NOT :-(
15596: 99/04/01: Re: FPGAs with ECL-compatible I/Os
15769: 99/04/12: Re: viterbi/trellis decoder
18804: 99/11/16: Re: How to connect a Xilinx Virtex FPGA to a TI DSP ?
18805: 99/11/16: Re: Xilinx M2.1i SP2?
18856: 99/11/18: Re: implementing TCP/IP on PLD
19138: 99/12/01: Re: FPGA vs DSP vs PENTIUM MMX
19416: 99/12/20: Re: Dumb question springing from a discussion about chess on a chip...
19417: 99/12/20: Re: How to include SpartanXL code in C souce code?
19435: 99/12/21: Re: Speed grade
19437: 99/12/21: Re: fpga cost
19572: 00/01/01: Re: PCI slot 3.3V pins.
19573: 00/01/01: Re: code error in active vhdl
19582: 00/01/02: Re: Design security
19585: 00/01/02: Re: Design security
19698: 00/01/08: Re: Newbie question on CPU's
19716: 00/01/09: Re: Disable clockbuffer for only a single flip-flop
19810: 00/01/12: Re: SDRAM controller ?
19811: 00/01/12: Re: SDRAM controller ?
20062: 00/01/25: Re: How to access standard sdram ?
20177: 00/01/29: Re: Program Xilinx Through TI DSP Serial McBSP
20190: 00/01/30: Re: Which FPGA to learn with?
20237: 00/02/01: Re: Which FPGA to learn with?
20407: 00/02/08: Re: Why does Virtex has no EPROM support like XC4000
20406: 00/02/08: Re: Xilinx "WebCD" gripes
21107: 00/03/06: Re: Design security
21201: 00/03/09: Re: Virtex and Virtex E package availability
21351: 00/03/17: Re: Is there a cheaper alternative to ByteblasterMV?
21470: 00/03/22: Re: Giving fpga's unique id
21914: 00/04/06: Re: JTAG programming
22051: 00/04/15: Re: FPGA/PLD design tools?
22058: 00/04/17: Re: Handshaking in Xilinx Foundation Express ???
22187: 00/04/30: Re: How to Prevent theft of FPGA design
22195: 00/04/30: Re: How to Prevent theft of FPGA design
22423: 00/05/08: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22582: 00/05/12: Re: Future of FPGAs?
22584: 00/05/12: Re: Do you know xilinx FPGAs well?
22776: 00/05/23: Re: FPGA implementation of LCD controller
23200: 00/06/17: Re: Hand soldering a PQ208 - It looks tough to do.
23589: 00/07/01: Re: PLXMon sources
23598: 00/07/02: Re: How much would a PCI core be worth?
23818: 00/07/10: Re: Xilinx buys LavaLogic
24196: 00/07/28: Re: Arithmetic Operators
24198: 00/07/28: Re: Power PC with Xilinx - what do you think?
24538: 00/08/12: Re: Fast (> 100Mb) serial link to PC
25262: 00/09/03: Re: Balls!
25511: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
25648: 00/09/16: Re: FPGA Express Strikes Again!
25649: 00/09/16: Re: FPGA Express Strikes Again!
25776: 00/09/20: Re: Complaint: Xilinx functional simulation libraries
26218: 00/10/09: Re: Help me! the limit of a signal's drive capacity
26675: 00/10/24: Re: XILINX Download cable with USB
27356: 00/11/19: Re: Synthesizable VHDL
27385: 00/11/20: Re: Synthesis & Routing speed
27487: 00/11/24: Re: Virtex-PCI-Boards
27488: 00/11/24: Re: Xilinx XC4000** Speed Grades
27543: 00/11/28: Re: Fifo design problem
27573: 00/11/29: Re: Fifo design problem
27576: 00/11/29: Re: Fifo design problem
27592: 00/11/29: Re: Synplify Benchmarks
27617: 00/11/30: Re: Fifo design problem
27665: 00/12/01: Re: Synplify Benchmarks
27850: 00/12/12: Re: Synplify PRO 6.1 + Foundation 3.1i
27953: 00/12/17: Re: Help configuring Spartan II using processor
28154: 00/12/23: Re: Methodology
28218: 01/01/01: Re: Verilog or VHDL
29566: 01/02/27: Re: cpul vs vhdl
29646: 01/03/03: Re: Bad Xilinx bitstream=big bang?
33483: 01/07/27: Re: PCI-Interface
63536: 03/11/25: Re: Slightly unmatched UART frequencies
63560: 03/11/25: Re: Slightly unmatched UART frequencies
63563: 03/11/25: Re: Slightly unmatched UART frequencies
63595: 03/11/25: Re: Slightly unmatched UART frequencies
63700: 03/11/30: Re: Slightly unmatched UART frequencies
63724: 03/12/01: Re: Slightly unmatched UART frequencies
63826: 03/12/04: Re: Slightly unmatched UART frequencies
80814: 05/03/11: Trying to find some Actel A54SX16P FPGAs to purchase
83013: 05/04/21: Re: DSP-PC architectural advice needed.
86807: 05/07/06: Actel vs. Xilinx and Altera
86900: 05/07/08: Re: Actel vs. Xilinx and Altera
87185: 05/07/18: Re: EHLO, board designers
87390: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87731: 05/07/29: Re: VHDL 200x? when?
88592: 05/08/23: Re: Stdin / stdout through RS232
89433: 05/09/14: Re: PCI configuration questions.
91057: 05/10/27: Re: another FPGA/asic vendor dead :(
103027: 06/05/24: Re: PCI 64/66 fpga eval boards
103086: 06/05/25: Re: PCI 64/66 fpga eval boards
103087: 06/05/25: Re: PCI 64/66 fpga eval boards
107709: 06/08/31: Re: Performance Appraisals
107890: 06/09/01: Re: Performance Appraisals
112322: 06/11/20: Re: board - T562.jpg
112323: 06/11/20: Re: board - T562.jpg
112324: 06/11/20: Re: board - T562.jpg
112325: 06/11/20: Re: board - T562.jpg
114433: 07/01/15: Re: Registered?
115074: 07/01/30: Re: 1 Gbps - state of the art?
115455: 07/02/11: Re: 1 Gbps - state of the art?
115499: 07/02/12: Re: Building Coaxial transmission line on PCB?
Joel Koltner:
127545: 08/01/01: Re: Split Plane
131289: 08/04/17: Re: Survey: FPGA PCB layout
131291: 08/04/17: Re: Survey: FPGA PCB layout
131303: 08/04/18: Re: Survey: FPGA PCB layout
131305: 08/04/18: Re: Survey: FPGA PCB layout
131313: 08/04/18: Re: Survey: FPGA PCB layout
131316: 08/04/18: Re: Survey: FPGA PCB layout
131318: 08/04/18: Re: Survey: FPGA PCB layout
131321: 08/04/18: Re: Survey: FPGA PCB layout
131427: 08/04/21: Re: Survey: FPGA PCB layout
131428: 08/04/21: Re: Survey: FPGA PCB layout
131437: 08/04/21: Re: Survey: FPGA PCB layout
131570: 08/04/25: Re: Survey: FPGA PCB layout
131571: 08/04/25: Re: Survey: FPGA PCB layout
135750: 08/10/14: Re: XMOS XC-1 kits are shipping
139455: 09/03/30: Re: added jitter on FPGAs
141015: 09/06/02: Re: Tektronix vs. Agilent, probes
142198: 09/07/28: Re: cool chart
142203: 09/07/28: Re: cool chart
147378: 10/04/24: Re: voltage divider calcs
150474: 11/01/24: Re: Xilinx news
150567: 11/01/26: Re: Xilinx news
150596: 11/01/27: Re: Xilinx news
Joel Seely:
106948: 06/08/22: Re: Video - DSP Eval board with Altera
Joel Smith:
27855: 00/12/12: Fpga Newbie
63961: 03/12/10: Soldering of FPGAs
Joel W. Kolstad:
6905: 97/07/08: Re: Generating Sine/Cosine digitally
7272: 97/08/20: Re: ISP Stories
Joel Williams:
150754: 11/02/09: Re: Good FPGA dev kit for a student who is not a complete newbie?
150790: 11/02/11: Re: Good FPGA dev kit for a student who is not a complete newbie?
150804: 11/02/14: Re: Cyclone Based FPGA Dev Board With USB Cable Program Path
151068: 11/03/04: Re: Xilinx FPGA Clocking resources and design implementation.
151078: 11/03/04: Re: Video Framebuffer using Nexys2 (Spartan-3E)
151098: 11/03/07: Re: Video Framebuffer using Nexys2 (Spartan-3E)
151285: 11/03/21: Re: Video Framebuffer using Nexys2 (Spartan-3E)
151302: 11/03/22: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of
151633: 11/04/28: Re: Ethernet MAC on Virtex 4
151742: 11/05/14: Re: Counter clocks on both edges sometimes, but not when different
151756: 11/05/15: Re: Counter clocks on both edges sometimes, but not when different
151762: 11/05/16: Re: spartan 3a ethernet
151892: 11/06/02: Re: FFT using logic gates only
153191: 12/01/06: Re: Trying to select a development board, can somebody help me make
153303: 12/01/30: Re: =?ISO-8859-1?Q?Post-synth=E8se_simulation?=
154361: 12/10/15: Re: FPGA-Board for Ethernet
<Joel.Kolstad@USA.Net>:
11471: 98/08/18: Where are the multiple drivers?
15428: 99/03/24: Re: Free Xilinx Vendor Tools ... NOT :-(
15475: 99/03/25: Re: Free Xilinx Vendor Tools ... NOT :-(
<joel.pigdon@gmail.com>:
111379: 06/11/02: Quartus synthesising out signals?
121624: 07/07/09: Re: LiveDesign, Altium [opinion]
130057: 08/03/14: Xilinx S3DSP + EDK Board, too good to be true?
<joel.weddick@lmco.com>:
103022: 06/05/24: XdmHelpers:662
Joelle:
68419: 04/04/03: iMPACT "Programming Failed"
Joelmir Jose Lopes:
79682: 05/02/23: Virtex-4 FPGA with Jbits3.0?
JoeP:
151405: 11/04/03: Re: Ideal FPGA Development Kit
151413: 11/04/04: Re: Ideal FPGA Development Kit
Joerg:
78601: 05/02/04: Re: Exportability of EDA industry from North America?
78637: 05/02/04: Re: Exportability of EDA industry from North America?
84910: 05/06/01: Re: need a book: Hilbert transform
85010: 05/06/02: Re: need a book: Hilbert transform
85013: 05/06/02: Re: need a book: Hilbert transform
85014: 05/06/02: Re: need a book: Hilbert transform
88793: 05/08/29: Re: CPLD Jitter
88821: 05/08/29: Re: CPLD Jitter
88834: 05/08/30: Re: CPLD Jitter
88836: 05/08/30: Re: Array of slope A/Ds in FPGA?
88865: 05/08/30: Re: Array of slope A/Ds in FPGA?
88882: 05/08/30: Re: Array of slope A/Ds in FPGA?
88883: 05/08/30: Re: Array of slope A/Ds in FPGA?
88924: 05/08/31: Re: Array of slope A/Ds in FPGA?
95490: 06/01/23: Re: PE licunsure: was Shooting Ourselves in the Foot
95083: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95130: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95135: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95138: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95142: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95147: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95151: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95250: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95252: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95254: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95255: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95256: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95257: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95261: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95358: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95360: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95363: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95365: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95450: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95459: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95467: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95480: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95529: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95532: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95535: 06/01/24: Re: OT:Shooting Ourselves in the Foot
95542: 06/01/24: Re: OT:Shooting Ourselves in the Foot
95599: 06/01/24: Re: OT:Shooting Ourselves in the Foot
95611: 06/01/24: Re: OT:Shooting Ourselves in the Foot
95622: 06/01/24: Re: OT:Shooting Ourselves in the Foot
99707: 06/03/28: Re: deglitching a clock
99827: 06/03/30: Re: deglitching a clock
99897: 06/03/30: Re: deglitching a clock
99984: 06/04/01: Re: deglitching a clock
100031: 06/04/01: Re: deglitching a clock
100059: 06/04/02: Re: deglitching a clock
107631: 06/08/30: Re: Performance Appraisals
107641: 06/08/30: Re: Performance Appraisals
107657: 06/08/30: Re: Performance Appraisals
107658: 06/08/30: Re: Performance Appraisals
107662: 06/08/30: Re: Performance Appraisals
107698: 06/08/31: Re: Performance Appraisals
107741: 06/08/31: Re: Performance Appraisals
107742: 06/08/31: Re: Performance Appraisals
107752: 06/09/01: Re: Performance Appraisals
107808: 06/09/01: Re: Performance Appraisals
107809: 06/09/01: Re: Performance Appraisals
107823: 06/09/01: Re: Performance Appraisals
107828: 06/09/01: Re: Performance Appraisals
107833: 06/09/01: Re: Performance Appraisals
107840: 06/09/01: Re: Performance Appraisals
107845: 06/09/01: Re: Performance Appraisals
107850: 06/09/01: Re: Performance Appraisals
107851: 06/09/01: Re: Performance Appraisals
107854: 06/09/01: Re: Performance Appraisals
107856: 06/09/01: Re: Performance Appraisals
107870: 06/09/01: Re: Performance Appraisals
107871: 06/09/01: Re: Performance Appraisals
107873: 06/09/01: Re: Performance Appraisals
107882: 06/09/01: Re: Performance Appraisals
107886: 06/09/01: Re: Performance Appraisals
107888: 06/09/01: Re: Performance Appraisals
107935: 06/09/02: Re: Performance Appraisals
107979: 06/09/03: Re: Performance Appraisals
108045: 06/09/04: Re: Performance Appraisals
109184: 06/09/21: Re: Dell Laptop for Embedded Work
109189: 06/09/21: Re: Dell Laptop for Embedded Work
109204: 06/09/22: Re: Dell Laptop for Embedded Work
109270: 06/09/22: Re: Dell Laptop for Embedded Work
109271: 06/09/22: Re: Dell Laptop for Embedded Work
110324: 06/10/13: Re: OT: Internships?
110334: 06/10/13: Re: OT: Internships?
120686: 07/06/13: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
120727: 07/06/14: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
131272: 08/04/17: Re: Survey: FPGA PCB layout
131290: 08/04/17: Re: Survey: FPGA PCB layout
131292: 08/04/18: Re: Survey: FPGA PCB layout
131301: 08/04/18: Re: Survey: FPGA PCB layout
131306: 08/04/18: Re: Survey: FPGA PCB layout
131311: 08/04/18: Re: Survey: FPGA PCB layout
131315: 08/04/18: Re: Survey: FPGA PCB layout
131317: 08/04/18: Re: Survey: FPGA PCB layout
131330: 08/04/19: Re: Survey: FPGA PCB layout
131331: 08/04/19: Re: Survey: FPGA PCB layout
131335: 08/04/20: Re: Survey: FPGA PCB layout
131351: 08/04/20: Re: Survey: FPGA PCB layout
131353: 08/04/20: Re: Survey: FPGA PCB layout
131365: 08/04/20: Re: Survey: FPGA PCB layout
131412: 08/04/21: Re: Survey: FPGA PCB layout
131433: 08/04/21: Re: Survey: FPGA PCB layout
131446: 08/04/21: Re: Survey: FPGA PCB layout
131455: 08/04/21: Re: Survey: FPGA PCB layout
131456: 08/04/21: Re: Survey: FPGA PCB layout
131560: 08/04/25: Re: Survey: FPGA PCB layout
131562: 08/04/25: Re: Survey: FPGA PCB layout
131575: 08/04/25: Re: Survey: FPGA PCB layout
131576: 08/04/25: Re: Survey: FPGA PCB layout
131606: 08/04/25: Re: Survey: FPGA PCB layout
131621: 08/04/26: Re: Survey: FPGA PCB layout
131639: 08/04/27: Re: Survey: FPGA PCB layout
131641: 08/04/27: Re: Survey: FPGA PCB layout
131642: 08/04/27: Re: Survey: FPGA PCB layout
131644: 08/04/27: Re: Survey: FPGA PCB layout
135662: 08/10/11: Re: XMOS XC-1 kits are shipping
135665: 08/10/11: Re: XMOS XC-1 kits are shipping
135721: 08/10/13: Re: XMOS XC-1 kits are shipping
135729: 08/10/13: Re: XMOS XC-1 kits are shipping
139410: 09/03/28: Re: added jitter on FPGAs
139420: 09/03/28: Re: added jitter on FPGAs
139428: 09/03/29: Re: added jitter on FPGAs
139429: 09/03/29: Re: added jitter on FPGAs
139433: 09/03/29: Re: added jitter on FPGAs
141487: 09/06/25: Re: 720 Mhz IF Processing
141505: 09/06/25: Re: 720 Mhz IF Processing
145983: 10/03/02: Re: Help with avoiding ground-loops on my PCB+external
156091: 13/11/22: Re: microZed adventures
160533: 18/03/16: Re: the FPGA one-shot
160537: 18/03/16: Re: the FPGA one-shot
160539: 18/03/16: Re: the FPGA one-shot
Joerg Fischer:
62680: 03/11/04: Re: Voila: Nedit macro to produce verilog module instantiations
62753: 03/11/06: Re: Voila: Nedit macro to produce verilog module instantiations
Joerg Langwald:
14418: 99/01/29: Q: Lucent OR3TP12 evaluation board available?
Joerg RiTTer:
18518: 99/10/28: Re: Xilinx F1.5 VHDL Sim. Libs for Synopsys
18654: 99/11/05: Re: Analog FPGA ?!
21897: 00/04/06: hwdebugr vs. jtag
Joerg Ritter:
31061: 01/05/10: Re: Waveforms painting
31174: 01/05/14: Re: Waveforms painting
31530: 01/05/29: Re: Fragen zu PCI und FPGA
31531: 01/05/29: Re: Help for PCI and FPGA
65826: 04/02/07: XC2V2000 + System Ace + Reconfig
69956: 04/05/25: ise 6.2 + linuxdrivers.tar.gz + kernel 2.6
70618: 04/06/22: Re: New: read/write to D2SB fpga
70683: 04/06/23: Re: New: read/write to D2SB fpga
78867: 05/02/09: Re: Impact with Linux Kernel 2.6.x
78933: 05/02/10: Re: Impact with Linux Kernel 2.6.x
79407: 05/02/18: edk and xilinx multimedia board
Joerg Schneide:
43412: 02/05/21: Xilinx WP test vectors in Jedec file
43457: 02/05/21: Re: Xilinx WP test vectors in Jedec file
44747: 02/06/28: XC9572 VCCIO change
Joerg Schoeppe:
5175: 97/01/29: Synthesizing fast counter (carry look ahead adder)
Joerg Siemers:
64120: 03/12/17: Initialising LPM_ROM
Joerg Wittenberger:
1403: 95/06/15: Need Help with Altera FLEX programing.
1522: 95/07/07: Q: Need help with MAX+plus reading EDIF
<joerg@zilium.de>:
115268: 07/02/05: Re: or1k on spartan 3, 400K gate version
115295: 07/02/06: Re: DDR FPGA Design
115996: 07/02/27: Re: Xilinx ISE webpack in Ubuntu?
117006: 07/03/21: Re: softcore CPU tools
117042: 07/03/22: Re: softcore CPU tools
124789: 07/10/04: xup-v2p: Only USB 1.1
125083: 07/10/16: Re: FPGA quiz: what can be wrong
125085: 07/10/16: Re: FPGA quiz: what can be wrong
Joey:
83062: 05/04/22: OCM interface to SDRAM
83067: 05/04/22: Re: OCM interface to SDRAM
83153: 05/04/25: Re: Executing program from external memory
83217: 05/04/26: Bus Frequency !!
83363: 05/04/28: Change OCM Clock
83364: 05/04/28: Re: Change OCM Clock
83520: 05/05/02: Frequency Limit !!
83528: 05/05/02: Re: Change OCM Clock
84016: 05/05/11: Frequency limitations?
84948: 05/06/01: Re: How to speed up float computing
84949: 05/06/01: Re: Accessing Bram
84976: 05/06/02: Re: Accessing Bram
84980: 05/06/02: How to add a lib to the core used
85512: 05/06/10: Re: re:How to add a lib to the core used
85517: 05/06/10: XPS : Body of function not found
85645: 05/06/13: Re: Body of function not found
85646: 05/06/13: Re: re:How to add a lib to the core used
85999: 05/06/20: How to reset a PLB/OPB Peripheral
86294: 05/06/24: PLB registers
86440: 05/06/28: Re: PLB registers
86441: 05/06/28: Control IPIF signals
86514: 05/06/29: synthesis problem
86564: 05/06/30: Re: synthesis problem
86755: 05/07/06: PowerPC interrupt
86756: 05/07/06: Program from external memory
86757: 05/07/06: Re: Program from external memory
86766: 05/07/06: Re: Program from external memory
86783: 05/07/06: Re: PowerPC interrupt
86823: 05/07/07: Re: Program from external memory
86833: 05/07/07: Re: PowerPC interrupt
86888: 05/07/08: Re: Program from external memory
86889: 05/07/08: Running prog from PROM
86898: 05/07/08: Re: Running prog from PROM
86958: 05/07/11: Re: Running prog from PROM
joey:
64514: 04/01/06: VirtexE DLL locked range
Joey Martin:
87083: 05/07/14: Reciprocal of improper fraction by using Divider ipcore
Joey Nelson:
40224: 02/03/02: Embedding counting in an FSM.
40560: 02/03/10: Re: Audio project with an FPGA?
45204: 02/07/15: Design Techniques for Memory Mapped Registers.
45258: 02/07/17: Re: Design Techniques for Memory Mapped Registers.
45278: 02/07/17: Re: LVDS interface cable recommendation sought
Joey Oravec:
32742: 01/07/06: FPGA Express search path
34168: 01/08/15: Slowing PCI for FPGA
34332: 01/08/21: Re: Slowing PCI for FPGA
34373: 01/08/22: Re: Slowing PCI for FPGA
34675: 01/09/03: Re: How to connect a clock to a non-clock pad ?
34787: 01/09/07: Re: Selection of a suitable FPGA board
Joey Y. Chen:
3657: 96/07/09: Xilinx XC4000E Availability
3658: 96/07/09: FPGA capacity comparison
<joey899244@yahoo.cn>:
154712: 12/12/28: Re: Which to learn: Verilog vs. VHDL?
<joey@joescan.com>:
102571: 06/05/17: Cyclone II PCI & Pin Swapping
jogendersaini:
147626: 10/05/09: repeting outputs of counter
jogging:
142428: 09/08/11: algorithm implementation in IC
142487: 09/08/12: Re: algorithm implementation in IC
143631: 09/10/19: where can price list of FPGA be found?
143657: 09/10/20: Re: where can price list of FPGA be found?
Johan:
55848: 03/05/21: CLKDLL: Dividing
55913: 03/05/23: Re: CLKDLL: Dividing
56011: 03/05/27: Re: CLKDLL: Dividing
94399: 06/01/11: FPGA and video generation
94419: 06/01/11: Re: FPGA and video generation
Johan Bernspang:
96003: 06/01/27: Re: XilNet server data streaming problem from PPC
115395: 07/02/09: Re: Digital AM/FM Receiver
Johan Bernspĺng:
62325: 03/10/27: ChipScope problems
64445: 04/01/05: connecting tristates
65055: 04/01/20: Re: Trouble using ChipsCope Pro with MicroBlaze
Johan Ditmar:
17525: 99/08/06: carry logic for implementing wide logic functions
17896: 99/09/16: rloc problem
19173: 99/12/03: Problems with routing Virtex device
30078: 01/03/22: Re: Virtex Em on a board?
34551: 01/08/29: global VHDL signals and FPGA express
35074: 01/09/20: problem with location constraints in Verilog
35666: 01/10/12: how do I avoid glitches in this design?
45328: 02/07/19: black box components with parameters in Synplify
45386: 02/07/22: Re: black box components with parameters in Synplify
52899: 03/02/25: Initializing multi-ported memories using MIF
Johan Eriksson Thelin:
43114: 02/05/14: LGPL 32bits RISC CPU Core
Johan Frödin:
17613: 99/08/14: Re: Virtx' Configuration with the Xchecker cable
Johan Galston:
75887: 04/11/18: --New-- ArmXF ARM+FPGA Blocks Development Platform
Johan Kortenhoeven:
8560: 98/01/08: Mach211 fpga programming
Johan Kwisthout:
22432: 00/05/09: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22492: 00/05/10: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22493: 00/05/10: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22563: 00/05/12: Re: OT ANNOUNCE: Embedded Systems Glossary and Bibliography
Johan Küstner:
22607: 00/05/13: Altera Schematic
22619: 00/05/14: Re: Altera Schematic
22735: 00/05/21: Re: Creating custom flip-flops in Altera MAX+Plus II
Johan Petersson:
25287: 00/09/05: Re: StateCAD ?
25289: 00/09/05: Re: More than 4 clocks in virtex
25294: 00/09/05: Re: Balls!
25295: 00/09/05: Re: run time doubled with Xilinx 3.1i upgrade
25486: 00/09/12: Re: More than 4 clocks in virtex
25276: 00/09/04: Re: Slow routing of PWR/GND (Virtex)
25286: 00/09/05: Re: Slow routing of PWR/GND (Virtex)
25292: 00/09/05: Re: Error during synthesis
25472: 00/09/12: Re: DCT implementation using FPGA
25474: 00/09/12: Re: How do I mix vhdl and verilog source files in Synplify?
25487: 00/09/12: Re: OUTs after synthesis?
25494: 00/09/12: Re: CPLD: Basic informations
25497: 00/09/12: Re: flipflops/statemachine/fifos and timing
25492: 00/09/12: Re: virtex shape
25493: 00/09/12: Re: Code distribution without loss of IP?
25892: 00/09/25: Re: Category : tri state data bus
25893: 00/09/25: Re: Is correct code?
25894: 00/09/25: Re: Multi-Arch, Moderately High performance VHDL FPGA Code?
25923: 00/09/26: Re: Paranoid...
25928: 00/09/26: Re: Coregen
25964: 00/09/28: Re: SV: hdl
25965: 00/09/28: Re: Category : Subject
25970: 00/09/28: Re: Synthesiser comparisons (was: FPGA Express strikes again)
32823: 01/07/10: Re: VHDL FFT core: where?
32824: 01/07/10: Re: xapp258 question
32826: 01/07/10: Re: Modlesim5.5
32827: 01/07/10: Re: How to specify Spartan2 GSR/GTS for Synthesis
32828: 01/07/10: Re: Handel-C
Johan Riesbeck:
87102: 05/07/15: Xilinx MPEG
Johan Van Dyck:
19363: 99/12/16: Re: State machine ok with binary encoding but unstable with one hot encoding
35934: 01/10/24: Re: Fpga Synthesis Process
Johann Glaser:
36085: 01/10/28: University project: DSO
39440: 02/02/09: Xilinx EDIF to BIT transation
39448: 02/02/10: Re: Xilinx EDIF to BIT transation
39453: 02/02/10: Re: Xilinx EDIF to BIT transation
39608: 02/02/14: Re: SpartanXL & VHDL -- free software?
39683: 02/02/15: Re: SpartanXL & VHDL -- free software?
39884: 02/02/21: EDIF to .bit file conversion for Xilinx Spartan XCS10
39901: 02/02/21: Re: EDIF to .bit file conversion for Xilinx Spartan XCS10
40386: 02/03/06: Re: exceeding 2GB limits in xilinx
40997: 02/03/19: Re: Webpack + XC4000
41192: 02/03/22: Re: which is the fastest FPGA ?
42109: 02/04/16: Re: Looking for SpartanXL demo board
42305: 02/04/19: Re: Xilinx Easypath- Selling parts with known defects
42328: 02/04/20: Re: Xilinx Easypath- Selling parts with known defects
42705: 02/05/01: Re: Xilinx: delete file problem
43110: 02/05/14: Re: Architecture for high-level reconfigurable computing
43502: 02/05/22: Re: Time for a new computer. Suggestions?
43772: 02/06/02: Re: Looking for FPGA board with USB interface
44522: 02/06/22: Re: Xilinx's 4.1i's Lastest webpack
45113: 02/07/12: Accurate Oscillator
45127: 02/07/13: Re: Accurate Oscillator
45128: 02/07/13: Re: Accurate Oscillator
45134: 02/07/13: Re: Accurate Oscillator
45135: 02/07/13: Re: Accurate Oscillator
45138: 02/07/13: Re: Accurate Oscillator
45143: 02/07/13: Re: Accurate Oscillator
45151: 02/07/13: Re: Accurate Oscillator
45163: 02/07/14: Re: Accurate Oscillator
45164: 02/07/14: Re: Accurate Oscillator
46855: 02/09/10: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
47460: 02/09/26: Re: FPGA programming via microcontroller
48023: 02/10/09: Re: Booting a FPGA via USB
48566: 02/10/21: Re: modelsim and linux help
52636: 03/02/17: Re: About automatically programming my FPGA
134471: 08/08/12: Re: RTL Schematic as EDIF
Johann Klammer:
154253: 12/09/17: Re: Looking for an extremely cheap FPGA board (in quantity, academic
155594: 13/07/27: vtr and at40k
156728: 14/06/09: Re: 22V10 programmer
156733: 14/06/09: Re: 22V10 programmer
156738: 14/06/10: Re: 22V10 programmer
157190: 14/10/29: The EDIF variant used by fit150X.exe
157191: 14/10/29: Re: The EDIF variant used by fit150X.exe
157253: 14/11/09: How to get optimized/correct PLA or SOP output from abc with selectable
157269: 14/11/12: Re: How to get optimized/correct PLA or SOP output from abc with
157697: 15/02/05: [WTF] Hierarchical designs and ATMELs CPLD fitters
158009: 15/06/26: SVF test vector injection - generating SVF files
158011: 15/06/28: Re: SVF test vector injection - generating SVF files
158012: 15/06/29: Re: SVF test vector injection - generating SVF files
158156: 15/08/26: Re: Q: CPLD input mux structure
158366: 15/10/24: Re: Found: an FPGA with internal tri-states
158650: 16/02/26: How do I instantiate an FGEN instance for Atmels Figaro IDS in EDIF?
158656: 16/02/29: what are the semantics of yosys $alu and $macc cells?
158657: 16/02/29: Re: what are the semantics of yosys $alu and $macc cells?
158658: 16/03/03: Re: How do I instantiate an FGEN instance for Atmels Figaro IDS in
158816: 16/04/14: Atmels product selector
159058: 16/07/22: Re: Lattice Diamond 3.7 and Synplify
159078: 16/07/26: Re: Xilinx Platform cable USB and impact on linux without windrvr
159106: 16/07/30: Re: Constant Mult: The State of High Level Synth (Part II)
159318: 16/10/06: How do I preserve Hazard safety terms?
159320: 16/10/06: Re: How do I preserve Hazard safety terms?
159322: 16/10/06: Re: How do I preserve Hazard safety terms?
159327: 16/10/06: Re: How do I preserve Hazard safety terms?
159751: 17/02/24: Re: designing a fpga
Johann Streitwieser:
150936: 11/02/23: Re: Programming FPGAs with Quartus under Linux
Johann Waldherr:
73703: 04/09/28: Boot : Sram Problem
Johann Zendik:
Johannes:
49241: 02/11/06: fir filter mit xilinx coregen
149077: 10/09/29: SDRAM for specific use - performance and timing questions
149079: 10/09/29: Re: SDRAM for specific use - performance and timing questions
149081: 10/09/29: Re: SDRAM for specific use - performance and timing questions
149091: 10/09/30: Re: SDRAM for specific use - performance and timing questions
149093: 10/09/30: Re: SDRAM for specific use - performance and timing questions
149106: 10/10/01: Re: SDRAM for specific use - performance and timing questions
149162: 10/10/05: Re: SDRAM for specific use - performance and timing questions
Johannes Hausensteiner:
106128: 06/08/08: Newbie question
106206: 06/08/09: Newcomer question
106210: 06/08/09: Re: Newcomer question
106221: 06/08/09: Re: Newbie question
106222: 06/08/09: Re: Newbie question
109016: 06/09/20: Lattice .bit file format
109020: 06/09/20: Re: Lattice .bit file format
109027: 06/09/20: Re: Lattice .bit file format
109237: 06/09/22: Re: Lattice .bit file format
113613: 06/12/18: unpredictable FPGA behaviour
118694: 07/05/02: prevent ROM inferration
118705: 07/05/02: Re: prevent ROM inferration
118719: 07/05/02: Re: prevent ROM inferration
118828: 07/05/04: Re: prevent ROM inferration
Johannes Sandvall:
52155: 03/02/03: Modules in a large design
52156: 03/02/03: Coregenerator Accum place problem (constraints)
Johannes Soelhusvik:
5870: 97/03/21: 8-bit divider in FPGA
5895: 97/03/24: Re: 8-bit divider in FPGA
5984: 97/04/02: Re: 8-bit divider in FPGA
Johannes Sřlhusvik:
7570: 97/09/23: Efficient test design for XC4000 devices ?
8829: 98/01/30: How to design 3-staged pipelined multiplier in VHDL for Xilinx 4000XL
8854: 98/02/02: Re: How to design 3-staged pipelined multiplier in VHDL for Xilinx 4000XL
<johannes.jansen@gmx.de>:
134769: 08/08/29: Format of Actel's SVF files
Johanus Breeman:
75194: 04/10/28: clk warning
JohhnyNorthener:
63733: 03/12/02: Quartus generics and vhdl
65656: 04/02/04: Quartus II and Synthesis
65934: 04/02/10: Re: Quartus II and Synthesis
73007: 04/09/10: Simulation probs with Altera LPM_FIFO+
73062: 04/09/13: Re: Simulation probs with Altera LPM_FIFO+
John:
10437: 98/05/18: XABLE
10509: 98/05/25: Re: Problem with loading XC4000E configuration from 8051
10584: 98/06/03: Re: Xilinx 5200 - XACT 6.0.1 vs. M1.4
10951: 98/07/07: Re: Consultants
13495: 98/12/05: Re: Is it normal to have to edit the xnf file???
14144: 99/01/15: Crosstalking
14585: 99/02/05: Re: ASIC or Digital Board Design in the UK - choice?
20911: 00/02/27: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
27411: 00/11/21: Re: Using FPGA as PCI target
34186: 01/08/16: Development boards
34713: 01/09/04: Re: SpartanII: non clock pad drives clock net ?
34714: 01/09/04: Give me some information!
36825: 01/11/21: XC4000EX Logiblox Clock Distribution
36827: 01/11/21: XC4000EX Logiblox Clock Distribution
40776: 02/03/15: Re: DES implementation in Handel C
43822: 02/06/03: Re: divide by 5
43864: 02/06/04: Re: divide by 5
44260: 02/06/14: Re: clock gating by any other name...
45858: 02/08/07: Re: lots of shift registers
46642: 02/09/04: Re: why the need for HIGH speed design?
46693: 02/09/05: question about quiescent current
46821: 02/09/09: differences between CoolRunner XPLA3 and CoolRunner-II?
46825: 02/09/09: Are Xilinx CoolRunners / Atmel ATF15xx CPLD's flash-based?
47108: 02/09/17: Can I run a 3.3V CPLD off of 3V?
47109: 02/09/17: termination of JTAG pins
47134: 02/09/18: using CPLD's inverter in oscillator circuit
47176: 02/09/19: XCV600 Version and Firmware
47234: 02/09/20: pulldown resistor value for Xilinx CPLD
47264: 02/09/21: external switch to CPLD input
47318: 02/09/23: Re: external switch to CPLD input
47348: 02/09/24: Re: Question about IOB, BUFG, IBUF and IBUG.
47955: 02/10/08: Setting initial flipflop values?
48148: 02/10/12: FS: ByteBlaster Cable for Altera FPGA
48752: 02/10/23: How do I measure power consumption?
50262: 02/12/06: Re: How do I measure power consumption?
50272: 02/12/06: CPLD current measurement
50513: 02/12/11: Re: hardware image processing - log computation
50615: 02/12/13: Re: Suggestions required for Handel-C code
50759: 02/12/18: What voltage level is considered as "floating"?
52449: 03/02/11: Disabling XC9500XL write protection?
55013: 03/04/24: ADC input
56712: 03/06/11: FPGA CPU Development Board
56787: 03/06/15: Spartan3 in WebPack
57821: 03/07/07: Re: Rant mode ON
57822: 03/07/07: Re: User Core OPB Problem (EDK3.2)
57823: 03/07/07: Re: How to Tristate!!! when not reading
57824: 03/07/07: Re: EDK/XPS/Virtex2Pro - TFT core not avaialble
57825: 03/07/07: Re: [DLL Virtex/Spartan-II] Which is the right feedback in x1 and
57826: 03/07/07: Re: [DLL usage Virtex/Spartan-II] HowTo drive CLKDV Div 2 off Chip
57844: 03/07/08: Re: Rant mode ON
57882: 03/07/09: Re: Rant mode <OFF>
58998: 03/08/06: How to use EAB in Altera FPGA?
59893: 03/08/31: How to use Modelsim-Altera to do the timing simulation?
59919: 03/09/01: Are there any free version uCOSII for Nios?
60189: 03/09/07: Re: CMOS camera w/ USB2 -- crazy?
60661: 03/09/18: Re: divide by on spartan3?
60687: 03/09/19: Re: divide by on spartan3?
60693: 03/09/19: Re: divide by on spartan3?
61774: 03/10/10: Re: Counting ones
61790: 03/10/10: Re: Counting ones
61839: 03/10/13: Xilinx Logic Handbook
61920: 03/10/14: Unsupported predefined attribute
61970: 03/10/15: Re: Counting ones
64318: 03/12/28: Re: advantages of ethernet MAC ip core
64321: 03/12/29: Re: advantages of ethernet MAC ip core
64331: 03/12/29: How to use write flash on board?
67507: 04/03/12: Device/Board Selection (CPU Design)
67537: 04/03/13: Re: Device/Board Selection (CPU Design)
67538: 04/03/13: Re: Device/Board Selection (CPU Design)
67549: 04/03/14: Re: Device/Board Selection (CPU Design)
67566: 04/03/14: Re: Device/Board Selection (CPU Design)
67611: 04/03/15: Re: Device/Board Selection (CPU Design)
67630: 04/03/16: Re: Device/Board Selection (CPU Design)
67655: 04/03/16: Re: Device/Board Selection (CPU Design)
67706: 04/03/17: Re: Device/Board Selection (CPU Design)
71819: 04/08/01: Downloading program to Nios
71838: 04/08/01: Re: Downloading program to Nios
71868: 04/08/02: Clock generator
71869: 04/08/02: Re: Downloading program to Nios
71889: 04/08/03: Re: Clock generator
72686: 04/08/28: Re: 6.1 vs. 6.2
75024: 04/10/25: Low-power FPGAs?
75217: 04/10/29: Re: Strange XST error in ISE 6.3.02i
74386: 04/10/10: Re: DCM and CLKFX - is this allowed?
74389: 04/10/10: Re: Coregen difficulties with DCT
74601: 04/10/14: Re: direct calculation of the modulus ?
74696: 04/10/16: Re: direct calculation of the modulus ?
75418: 04/11/05: Re: Low-power FPGAs?
75563: 04/11/09: Re: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have tool
76468: 04/12/03: Cylone Problem with Large Shift Register
76542: 04/12/06: Re: Cylone Problem with Large Shift Register
76543: 04/12/06: Re: Cylone Problem with Large Shift Register
77195: 04/12/28: BRAM timing problem
82398: 05/04/12: How do I disable Microblaze on-chip hw debug
82401: 05/04/12: Re: How do I disable Microblaze on-chip hw debug
82413: 05/04/12: Re: How do I disable Microblaze on-chip hw debug
82462: 05/04/13: Re: How do I disable Microblaze on-chip hw debug
83111: 05/04/23: READ/WRITE files using TEXTIO using Quartus
83281: 05/04/26: RocketIO attribute for TLK3101 or TLK2501?
85578: 05/06/10: FPGA or SSE2 ?
85593: 05/06/11: Re: FPGA or SSE2 ?
93088: 05/12/13: fiddling directly with LUT bits on Xilinx
100809: 06/04/18: RIO Reference clock oscillator part
101019: 06/04/24: Re: Xilinx EDK 8.1 DDR controller behavior
106108: 06/08/07: Re: DDR2 SRAM Stratix II questions
108359: 06/09/08: Re: Altera CPLD 7128S heating up
108480: 06/09/12: Re: simplyrisc-s1 free core
108628: 06/09/14: Re: SoC Development Board
110107: 06/10/11: Q on sync resets (yes, again!)
113063: 06/12/05: Timing constraings: min delay?
113064: 06/12/05: Re: Timing constraings: min delay?
113123: 06/12/06: How do I delay signal to pad?
113363: 06/12/11: Virtex4 : cleaner signals?
113443: 06/12/13: Re: Virtex4 : cleaner signals?
113485: 06/12/14: Re: Virtex4 : cleaner signals?
114106: 07/01/04: Virtex 4 FIFO question
114108: 07/01/04: Re: Virtex 4 FIFO question
114239: 07/01/08: Variable clock using Virtex 4?
114257: 07/01/09: Delaying signal
114258: 07/01/09: Re: Delaying signal
114491: 07/01/17: Process on both edges
128823: 08/02/07: Re: function/process to generate sine and cosine wave
136696: 08/12/01: Use Chipscope libCseJtag.dll
136740: 08/12/03: Re: Use Chipscope libCseJtag.dll
139354: 09/03/27: Re: FIFO controlled loop, PLL, FLL or something else?
139377: 09/03/27: Re: FIFO controlled loop, PLL, FLL or something else?
141307: 09/06/16: Re: QPSK demod development: Integration problems
144111: 09/11/11: Re: Having trouble with Xilinx timing constraints
john:
38025: 01/12/31: Actel 54sx series clock doubler
38198: 02/01/08: Actel Simulations
67197: 04/03/08: HOW to Increase jitter in ALTERA PLL ?
67253: 04/03/09: Re: HOW to Increase jitter in ALTERA PLL ?
67318: 04/03/10: Re: HOW to Increase jitter in ALTERA PLL ?
67886: 04/03/22: Re: 64bit cpu on Xilinx
68050: 04/03/25: Clock divider preserving duty-cycle ?
69828: 04/05/21: DS-BD-V2M1000 datasheets?
69829: 04/05/21: Re: How to handle different proccessing speeds?
69847: 04/05/22: Re: DS-BD-V2M1000 datasheets?
70451: 04/06/17: Re: DCM in Xilinx
75435: 04/11/05: USB2.0
88903: 05/08/31: modular design: can one use long lines
91648: 05/11/10: Can't pack into OLOGIC
91654: 05/11/10: Re: Can't pack into OLOGIC
91655: 05/11/10: Re: Can't pack into OLOGIC
91656: 05/11/10: Re: Can't pack into OLOGIC
91662: 05/11/10: Re: Can't pack into OLOGIC
91807: 05/11/14: Re: Can't pack into OLOGIC
93175: 05/12/15: How to simulate a .NMC macro?
93180: 05/12/15: Re: How to simulate a .NMC macro?
93514: 05/12/23: Image processing libraries and VHDL
94160: 06/01/06: Asynch. signal
94174: 06/01/06: Asynch. signal
94347: 06/01/10: Re: Asynch. signal
94360: 06/01/10: Re: Asynch. signal
94750: 06/01/17: CPLD serial buffer problem
101025: 06/04/24: Heating problem of the CPLD
101032: 06/04/24: Re: Heating problem of the CPLD
105829: 06/08/01: FPGA LABVIEW programming
105835: 06/08/01: Re: FPGA LABVIEW programming
112998: 06/12/04: XEM3010
113137: 06/12/06: XSA3S1000 board and SDRAM
140860: 09/05/27: Re: Error in Verilog Code
141139: 09/06/08: Re: Virtex 5 LUT Outpus
141165: 09/06/09: Re: Xilinx Block RAM Sim
141179: 09/06/10: Re: async. SRAM control signal generation
141222: 09/06/11: ISE 10.1 Free Downlaod Web Install
141349: 09/06/19: Re: FDRSE Spartan 3A - Active high/low set/reset
159950: 17/05/02: Re: RISC-V Support in FPGA
160273: 17/10/07: Artix-7 boards
160275: 17/10/07: Re: Artix-7 boards
160293: 17/10/26: graphics for FPGA design
160300: 17/11/06: Re: Using LUTs to create a phase delayed clock - is it reproducible?
160384: 18/01/10: HDL simple survey - what do you actually use
160394: 18/01/11: Re: HDL simple survey - what do you actually use
160512: 18/03/07: Re: Lattice or Microsemi?
160992: 19/01/09: Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
161338: 19/03/30: Re: Replaceme EPROM by CPLD/FPGA
161347: 19/04/15: FPGA board on ebay
John Morgan:
58767: 03/08/01: Re: Spartan 3 support in Webpack
john williams:
64810: 04/01/14: translating .jed files to equations
John A. Harding:
5498: 97/02/20: Reverse Engineering FPGAs
John Abt:
14701: 99/02/11: HDTV SMPTE 292 FPGA Parallel de-scrambler
36885: 01/11/22: Urgent need - PCI Bus Analyzer
John Adair:
35774: 01/10/17: Re: Xilinx 64 Point FFT Core Problem
36185: 01/11/01: Re: Virtex 2 or E Evaluation Board
36611: 01/11/13: Re: Clock Divider or Multiplier ???
36650: 01/11/14: Re: interleaver delay question
36751: 01/11/19: Re: Prototyping Board
37704: 01/12/19: Re: DCM stability in Virtex2 -ES
45436: 02/07/23: Re: Clock-gating in Virtex-E parts
46929: 02/09/12: Re: problem with tri state bus
63794: 03/12/04: Re: Ideal Development Machine Specifications
64116: 03/12/17: Re: What is this ASMBL thing from Xilinx?
64181: 03/12/19: Re: What is this ASMBL thing from Xilinx?
64452: 04/01/05: Re: please help! state machine
64511: 04/01/06: Re: Installation of Xlinx
64584: 04/01/08: Re: min propagation delay in xilinx cpld
64765: 04/01/13: Re: min propagation delay in xilinx cpld
65149: 04/01/21: Re: Xilinx design process....
65217: 04/01/22: Re: Synthesis errors?
65431: 04/01/29: Re: Asking about FPGA-SPARTAN error in synthizer
65959: 04/02/10: Re: Synchronization of signals
66071: 04/02/12: Re: How many PCB layers ?
66154: 04/02/13: Re: Verilog and VHDL mix
66323: 04/02/17: Re: IOB's
66327: 04/02/17: Re: GSR in Spartan3 ?
66329: 04/02/17: Re: GSR in Spartan3 ?
66339: 04/02/17: Re: IOB's
66534: 04/02/21: Re: Lead Free Packages
66742: 04/02/26: Re: Modular Design in WebPack
66767: 04/02/26: Re: Done Pin Remains Low after JTAG Configuration of V2Pro
67004: 04/03/03: Re: Design never finish routing?
67044: 04/03/04: Re: XST ff merging - how do I "preserve" flip flops
67181: 04/03/08: Re: FPGA hangs
67327: 04/03/10: Re: Very strange Xilinx timing report.
67342: 04/03/10: Re: fpga
67344: 04/03/10: Re: Very strange Xilinx timing report.
67399: 04/03/11: Re: Clock and data synchronization
67676: 04/03/17: Re: Difficulties fitting a design into a Xinlinx Virtex-II XC2V6000 FPGA.
68102: 04/03/26: Re: Estimate the gate sizes between ASIC and Virtex-2...
68255: 04/03/31: Re: Where to source CPLD XC2C256-7TQFP144I
68515: 04/04/07: Re: how to get XST to infer 8:1 mux or just hard code it?
68742: 04/04/16: Re: Spartan 3 POR Spec?
68940: 04/04/22: Re: FPGA within demonstration
69693: 04/05/18: Re: Low cost FPGA dev board with high speed i/f?
69831: 04/05/21: Re: XIlinx V2P7: DCM won't lock
69900: 04/05/24: Re: XIlinx V2P7: DCM won't lock
69901: 04/05/24: Re: FPGA Board with Flash Memory
70180: 04/06/08: Re: Virtex-4 FX transceiver jitter
70285: 04/06/11: Re: Xilinx: infering dual port ROM in VHDL
70357: 04/06/14: Free Seminar
70454: 04/06/17: Re: help for finding a company which can provide FPGA based PCI board with ethernet port
70510: 04/06/18: Re: Xilinx XST synthesis removes input pin even though it's LOCed
70615: 04/06/22: Re: Xilinx XST synthesis removes input pin even though it's LOCed
70972: 04/07/03: Re: FPGA SDRAM prototyping
70973: 04/07/03: Re: How to add clock delay in CPLD?
70974: 04/07/03: Re: Compact FPGA Board?
71379: 04/07/16: Re: Spartan3 Dev Boards
71419: 04/07/18: Re: FPGA Development board with onboard Ethernet PHY
71423: 04/07/18: Re: Memory width on Spartan-3 boards
71432: 04/07/18: Re: Memory width on Spartan-3 boards
71433: 04/07/18: Re: Memory width on Spartan-3 boards
71435: 04/07/18: Re: Memory width on Spartan-3 boards
71468: 04/07/19: Re: Memory width on Spartan-3 boards
71469: 04/07/19: Re: Memory width on Spartan-3 boards
71491: 04/07/20: Re: fpga board with audio in/out (xilinx fpga) ?
71824: 04/08/01: Re: FPGA prototype board with ethernet interfaces
72043: 04/08/06: Re: Acceleration
74967: 04/10/22: Re: Experiences with SPARTAN3?
74968: 04/10/22: Re: Webpack 6.3i support for Spartan 3
75028: 04/10/25: Re: Low-power FPGAs?
75183: 04/10/28: Re: information about Nuhorizon Spartan-3 Development Board ?
76003: 04/11/22: Re: Spartan 3 output voltage level
76005: 04/11/22: Re: 5V PCI interface using Spartan3
76217: 04/11/29: Re: When JTAG programming Xilinx FPGA, should other pins be constrained?
76234: 04/11/29: Re: fpga prices
76431: 04/12/02: Re: 99% Utilisation !
76438: 04/12/02: Re: Does Easypath make sense for a XC2S15 @ 20K units?
76546: 04/12/06: Re: Dev board to experiment with pci interface?
76548: 04/12/06: Re: JTAG recognise xcv50e instead of xc2s50e
76549: 04/12/06: Re: internal tristates and busses
77967: 05/01/21: Re: Asic prototyping in Fpga - prototyping the gates.
78072: 05/01/24: Re: Asic prototyping in Fpga - prototyping the gates.
78203: 05/01/26: Re: Spartan III place fails
78865: 05/02/09: Re: xilinx parallel cable IV
78872: 05/02/09: Re: laptop for fpga design - acer ferrari?
80283: 05/03/03: Re: spartan3 development board in Europe?
80372: 05/03/04: Re: 1,5Mhz Clock
80374: 05/03/04: Re: RAM Address Calculating
80619: 05/03/09: Re: SPROM for Spartan II
80703: 05/03/10: Re: Spontaneous Board Reset
80777: 05/03/11: Re: looking for PCI board with fpga and 1394 interface
80900: 05/03/14: Re: looking for PCI board with fpga and 1394 interface
80915: 05/03/14: Re: XCF01's in the UK
81007: 05/03/16: Re: Need recommendation on an FPGA board with a USB socket.
81524: 05/03/26: Re: cheap Xilinx tricks
81547: 05/03/27: Re: Multi-FPGA PCB data aggregation?
81576: 05/03/28: Re: Mixing synchronous and asynchronous reset
81764: 05/03/31: Re: FPGA board--host PC, need 20-50 Mbps speed, USB2, PCI or 1394?
81773: 05/03/31: Re: FPGA board--host PC, need 20-50 Mbps speed, USB2, PCI or 1394?
82126: 05/04/07: Re: Hey Xilinx
82127: 05/04/07: Re: LVDS PCI card is needed
82397: 05/04/12: Re: LVDS PCI card is needed
83358: 05/04/28: Re: RocketIO decoupling
83432: 05/04/29: Re: Nuhorizons alternatives for Xilinx parts?
83548: 05/05/02: Re: Decoupling V2P
83578: 05/05/03: Re: JTAG without parallel port
83745: 05/05/06: Re: including components, i.e. SRL16
83828: 05/05/07: Re: FPGA choice advice needed
83834: 05/05/07: Re: including components, i.e. SRL16
83872: 05/05/09: Re: FPGA choice advice needed
83878: 05/05/09: Re: Xilinx VIIPro mixed configuration voltages
84000: 05/05/11: Re: 2.5/3.3 LVPECL in Virtex
84005: 05/05/11: Re: Any Virtex 4 development/prototyping boards out there???
84203: 05/05/14: Re: Virtex-II Switch Matrix Performance
84244: 05/05/16: Re: Xilinx : Clock Swallowing
84346: 05/05/17: Re: Virtex-2 JTAG problem
84378: 05/05/18: Re: Which Simulators
84455: 05/05/19: Re: Spartan 3 CPI
84459: 05/05/19: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84460: 05/05/19: Pushing PicoBlaze
84494: 05/05/19: Re: Coloring by clock?
84531: 05/05/20: Re: Memec Virtex-4 LX25 LC
84573: 05/05/21: Re: VHDL vs. Schematic Capture
84610: 05/05/23: Re: FSM stops working
84624: 05/05/23: Re: CPLD Fitting problem
84666: 05/05/24: Re: Xilinx Answer Record 21127
84674: 05/05/24: Re: Programmer + Cable
84786: 05/05/27: Re: 2:1 mux in one LUT
84795: 05/05/27: Re: Xilinx Parallel Cable III flying lead repair
84844: 05/05/30: Re: Xilinx Spartan 3 SSO Guidelines for 3.3V LVCMOS when using "series DCI"
84864: 05/05/31: Re: Magical Mystery Tour of ISE environment variables
84983: 05/06/02: Re: PCI master clock trace
85251: 05/06/07: Re: Pissed off with Xilinx - Spartan 3
85257: 05/06/07: Re: Pissed off with Xilinx - Spartan 3
85494: 05/06/10: Re: Gated clock question
85496: 05/06/10: Re: X-Fest devkit order leadtimes & software silliness....
85507: 05/06/10: Re: X-Fest devkit order leadtimes & software silliness....
85530: 05/06/10: Re: ISE7.1 PAR Warinng: excessive skew because 1 NON-CLK pins...
85568: 05/06/11: Re: computer upgrade time.
85864: 05/06/17: Re: BGA Rework/Prototype Placement Anyone?
85868: 05/06/17: Re: Availability of Spartan3
85882: 05/06/17: Re: Xlinix configuration: DONE pin too early?
85886: 05/06/17: Re: Xlinix configuration: DONE pin too early?
85989: 05/06/20: Re: BGA Rework/Prototype Placement Anyone?
86223: 05/06/23: Re: Xilinx Powe Requirements V2PRO complaint
86437: 05/06/28: Re: FPGA for video processing
86438: 05/06/28: Re: FPGA for video processing
86439: 05/06/28: Re: FPGA PC104 development board
86445: 05/06/28: Re: FPGA PC104 development board
86890: 05/07/08: Re: Running prog from PROM
86949: 05/07/11: Re: Search for FPGA
86950: 05/07/11: Re: design does not fit in device
86963: 05/07/11: Re: Search for FPGA
86995: 05/07/12: Re: Xilinx Conversion 3.1 --> 6.1
87165: 05/07/18: Re: Lab machine xmd/debugger install?
87199: 05/07/19: Re: EHLO, board designers
87200: 05/07/19: Re: pricing of Virtex-4
87241: 05/07/20: Re: Using unregistered inputs in FSM
87749: 05/07/30: Re: ISE webpack doesnt support Spartan xcs10, solution??
87839: 05/08/02: Re: Spartan3 with WebPack?
88590: 05/08/23: Re: Xilinx place and route cost table
88596: 05/08/23: FPGA Development Board Wish List
88601: 05/08/23: Re: FPGA Development Board Wish List
88602: 05/08/23: Re: 10 Gigabit Ethernet FPGA boards...
88610: 05/08/23: Re: FPGA Development Board Wish List
88611: 05/08/23: Re: FPGA Development Board Wish List
88652: 05/08/24: Re: FPGA Development Board Wish List
88686: 05/08/25: Re: FPGA Development Board Wish List
88726: 05/08/26: Re: FPGA Development Board Wish List
88786: 05/08/28: Re: mails from Aman Mediratta
88905: 05/08/31: Re: Low Power RTL Design
89023: 05/09/02: Re: FPGA Development Board Wish List
89026: 05/09/02: Re: CPLD CoolRunner-II - IO current limited to 8mA?
89027: 05/09/02: Re: Spartan-3 LVDS driving TFT LCD panel..?
89028: 05/09/02: Re: Lot of 60 XCV1000 FPGAs
89338: 05/09/13: Re: CPU benchmark for Xilinx PAR
89945: 05/09/30: Prevue - FPGA Dev Board Sale
89984: 05/10/01: Re: Prevue - FPGA Dev Board Sale
89994: 05/10/01: Re: Prevue - FPGA Dev Board Sale
90220: 05/10/06: Raggedstone1
90294: 05/10/09: Re: 3rd party JTAG cables/controllers for Virtex-4
90328: 05/10/10: Re: How many decoupling capacitors need on one device?
90523: 05/10/16: Re: 3.3v<->5V
90538: 05/10/16: Re: 3.3v<->5V
90540: 05/10/16: Re: Mixed voltage in JTAG chain.
90541: 05/10/16: Re: Anyone remember the really early Xilinx FPGAs?
91640: 05/11/10: Re: Spartan 3e is slower than Virtex 2p
91731: 05/11/11: Re: fastest possible USB
91732: 05/11/11: MicroBlaze Seminar UK
91772: 05/11/12: Re: AVNET's Spartan3 400 dev board & PCI
91787: 05/11/13: Re: Viretx4 FX chip availability
91788: 05/11/13: Re: fastest possible USB
91864: 05/11/15: Re: Rise time/fall time for Spartan3 clock inputs
91898: 05/11/16: Raggedstone1, MINI-CAN - Low Cost Carriage
91932: 05/11/17: Re: Raggedstone1, MINI-CAN - Low Cost Carriage
91967: 05/11/18: Re: Parallel Cable IV not detecting
92028: 05/11/20: Re: Asynchronous design
92030: 05/11/20: Re: CLK input DOES NOT use clk pin ( Altera Stratix II)
92234: 05/11/24: Re: Memory in VHDL
92253: 05/11/24: Re: Memory in VHDL
92274: 05/11/25: Re: Speed of programming for xc18v04?
92301: 05/11/26: Re: Distributed RAMs / SRL: Why not, Altera?
92312: 05/11/27: Re: Distributed RAMs / SRL: Why not, Altera?
92313: 05/11/27: Re: VLSI Processor Cores
92406: 05/11/29: Re: first time managing a project
92539: 05/12/01: Re: Any fpga tutorials online?
92619: 05/12/02: Re: Curious about FPGAs
92620: 05/12/02: Re: Virtex-4 FX60 based products are already shipping now !
92634: 05/12/02: Re: What if....
92635: 05/12/02: Re: Any fpga tutorials online?
92662: 05/12/03: Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model
92672: 05/12/04: Re: how to build 32X32 LUT ROM
92804: 05/12/07: Free Seminars - UK
92936: 05/12/09: Re: ISE purchase
92990: 05/12/11: Re: ISE purchase
93089: 05/12/13: Re: fiddling directly with LUT bits on Xilinx
93141: 05/12/14: Re: FPGA-pci communication
93356: 05/12/20: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
93414: 05/12/21: Re: Buffers/Line drivers for 6pin JTAG?
93732: 05/12/29: Re: FSM goes into invalid state after reset...
93810: 05/12/31: Re: call for papers,Expresscard specification?
93811: 05/12/31: Re: Low cost PCI FPGA cards for reconfigurable computing
93812: 05/12/31: Re: Newbie question - using library "design elements"
93815: 05/12/31: Re: Virtex 4 desing : ChipScope insertion impacts my timing problem debug
93817: 05/12/31: Re: Newbie question - using library "design elements"
93889: 06/01/03: Re: Clock generation
93941: 06/01/03: Re: Xilinx upgrade issues
93977: 06/01/04: Re: Remapping from Virtex-II to Virtex-4
93985: 06/01/04: Re: DCM spartan 3 variable frequency divider
93991: 06/01/04: Re: DCM spartan 3 variable frequency divider
94171: 06/01/06: Re: Virtex-4 FX12 EMAC with ISE WebPack
94145: 06/01/06: Re: PCI compliance ?
94170: 06/01/06: Re: Chipscope Pro
94216: 06/01/08: Re: CRC error correction
94215: 06/01/08: Re: DMA with powerspan II -Fpga card
94284: 06/01/09: Re: DMA with powerspan II -Fpga card
94294: 06/01/09: Re: Xilinx USB Platform Cable not working anymore
94544: 06/01/13: Re: FPGA Journal Article
94534: 06/01/13: Re: FPGA Journal Article
94616: 06/01/14: Re: FPGA Altair Advice
94618: 06/01/14: Student Pricing Now on our Website
94634: 06/01/15: Re: Student Pricing Now on our Website
94701: 06/01/16: Re: Xilinx HW-SPAR3_CPLD-DK kit
94797: 06/01/17: Re: Raggedstone specifications ...
94796: 06/01/17: Re: Raggedstone specifications ...
94823: 06/01/18: Re: Raggedstone specifications ...
94950: 06/01/19: Re: Raggedstone specifications ...
94997: 06/01/20: Re: Raggedstone specifications ...
95354: 06/01/22: Re: Raggedstone specifications ...
95749: 06/01/25: Re: Raggedstone specifications ...
95192: 06/01/21: Re: Hi :-) Someone build a parallel JTAG cable like the xilinx one ?
95347: 06/01/22: Re: Starting with LVDS
95351: 06/01/22: Re: Starting with LVDS
95661: 06/01/25: Re: FPGA board with High Speed LVDS
95660: 06/01/25: Re: How to handle the "gate count" issue?
95705: 06/01/25: Re: Spartan-3 Starter Board
95725: 06/01/25: Re: Spartan-3 Starter Board
95735: 06/01/25: Re: Spartan-3 Starter Board
95843: 06/01/26: Re: Spartan-3 Starter Board
95970: 06/01/27: Re: EDK 8.1 ... delay
96066: 06/01/29: Re: EDK 8.1 ... delay
96067: 06/01/29: Competition to win Raggedstone1 RS1-1500 Spartan-3 FPGA Board
96286: 06/02/01: Re: Maximum system frequency on FPGA/CPLD
96374: 06/02/02: Re: Microblaze question
96528: 06/02/06: Re: VGA and framebuffer interface (Waste of BlockRAM)
96611: 06/02/07: Re: why does speed grade effect VHDL program??
96831: 06/02/11: Re: which one among the available FPGAs is best for a fresher?
96832: 06/02/11: Re: Xilinx 1.5v HSTL-I for QDR-II. Anybody successful with it?
96864: 06/02/12: Re: which one among the available FPGAs is best for a fresher?
96865: 06/02/12: Re: which one among the available FPGAs is best for a fresher?
96902: 06/02/13: Re: spartan3 starter kit.
97077: 06/02/16: EDl Lab
97199: 06/02/18: Re: Xilinx development board
97200: 06/02/18: PC104+ Card
97223: 06/02/19: Re: What is the best price you have gotten on for these FPGAs?
97228: 06/02/19: FPGA Board Competition
97281: 06/02/20: Re: Xilinx development board
97470: 06/02/23: Re: Input stage for VHF frequency counter in an FPGA?
97471: 06/02/23: Re: JTAG problem
97505: 06/02/23: Re: virtex 4
97543: 06/02/23: Raggedstone1 - New Worldwide postage
97579: 06/02/24: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
97589: 06/02/24: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
97684: 06/02/26: Re: Low power consumption board with memory
97743: 06/02/27: Re: miniuart
97757: 06/02/27: Re: tricks to make large PLAs fast?
97774: 06/02/27: Re: miniuart
97837: 06/02/28: Re: conv_integer
97960: 06/03/02: Re: coregen on webpack 8.1
97993: 06/03/02: Broaddown4 - Ultimate Virtex-4 Development Board
98100: 06/03/04: Hollybush1 - PC104+ Board
98115: 06/03/05: Re: Par error in Spartan-3
98446: 06/03/10: Re: 5v Xilinx development board
98598: 06/03/13: Re: Soldering SMT/BGA
98605: 06/03/13: Re: Soldering SMT/BGA
98670: 06/03/14: Re: Spartan 3 DCM
98682: 06/03/14: Re: Soldering SMT/BGA
98758: 06/03/16: Re: CoolRunner 2 CPLD
98762: 06/03/16: Re: Purchasing Virtex-4 FPGAs
98791: 06/03/16: Re: Where are FPGA heading?
99123: 06/03/20: Re: Xilinx programming cable; Linux notebook w/o parallel port; Am I doomed?
99438: 06/03/24: Re: Raggedstone specifications ...
99589: 06/03/27: Re: Spartan 3e Starter Kit finally available? No, not really.
99622: 06/03/27: Re: Variable Bus Input/Output Fifo
99626: 06/03/27: Re: Spartan 3e Starter Kit finally available? No, not really.
99936: 06/03/31: Re: JTAG program failed
99941: 06/03/31: Re: Xilinx Webpack vs Foundation ?
100136: 06/04/04: Re: Virtex II Pro
100137: 06/04/04: Re: How fast is YOUR ise8.1?
100351: 06/04/07: Re: OPB master
100362: 06/04/07: Re: OPB master
100920: 06/04/21: Raggedstone1 and Opencores PCI
102313: 06/05/15: Re: Raggedstone IO bracket ?
102314: 06/05/15: Re: Power for Spartan 3
102335: 06/05/15: Re: Power for Spartan 3
102801: 06/05/21: Re: [Newbie] Suitable FPGA for my project
102858: 06/05/22: Re: xilinx pricing discrepancy
102874: 06/05/22: Re: xilinx pricing discrepancy
102969: 06/05/24: Re: FPGA delay generator
102987: 06/05/24: Re: FPGA delay generator
103059: 06/05/25: Re: FPGA delay generator
103061: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
103235: 06/05/29: Re: fpga uclinux, good starter board ?
103291: 06/05/30: Re: fpga uclinux, good starter board ?
103295: 06/05/30: OVERCOAT - FPGA Development Arrays
103394: 06/06/01: Re: Virtex4 FX12 - maximum frequency for Picoblaze
103456: 06/06/02: Free Tools
103533: 06/06/05: Re: FPGA board for USB experiments?
103583: 06/06/06: Re: FPGA board for USB experiments?
103657: 06/06/07: Re: Anyone with Xilinx SP305-board ?
103761: 06/06/10: Re: R: xilinx cable 3 doesn't talk with pc,but test ok
104017: 06/06/16: Re: bga routing
104106: 06/06/19: Re: Newbie to FPGA
104124: 06/06/19: Re: Newbie to FPGA
104165: 06/06/20: For Broaddown2 Owners
104200: 06/06/21: Re: comp.arch.fpga : Selection of Device
104260: 06/06/22: Re: Detachable Virtex-II Pro/Virtex-4 FX module with Rocket I/O
104350: 06/06/25: Re: newbie wants to do VHDL on an FPGA
104357: 06/06/25: Re: newbie wants to do VHDL on an FPGA
104387: 06/06/26: Raggedstone1 Brackets
104492: 06/06/28: Re: Virtex5 Availability
104974: 06/07/11: Development Boards -Your chance to suggest features
104985: 06/07/11: Re: Development Boards -Your chance to suggest features
104991: 06/07/11: Re: Development Boards -Your chance to suggest features
105009: 06/07/11: Re: Development Boards -Your chance to suggest features
105010: 06/07/11: Re: Development Boards -Your chance to suggest features
105020: 06/07/12: Re: Development Boards -Your chance to suggest features
105021: 06/07/12: Re: Development Boards -Your chance to suggest features
105058: 06/07/12: Re: Development Boards -Your chance to suggest features
105082: 06/07/13: Raggedstone1 Ethernet Modules Available
105115: 06/07/13: Re: Development Boards -Your chance to suggest features
105116: 06/07/13: Re: Development Boards -Your chance to suggest features
105126: 06/07/14: Re: Development Boards -Your chance to suggest features
105161: 06/07/15: Re: Data Logging / FPGA Dev board
105168: 06/07/16: Re: An idea for a product (FPGA/ASIC based)
105176: 06/07/16: Re: 2048 input or gate ?
105203: 06/07/17: Re: Development Boards -Your chance to suggest features
105212: 06/07/18: Re: Virtex 4, LVDS I/O: Sanity check please
105319: 06/07/20: Last Chance for Tarfessock1 Features
105345: 06/07/20: Re: High-speed ADC+ Rocket I/O capability FPGA board
105383: 06/07/21: Re: Last Chance for Tarfessock1 Features
105384: 06/07/21: Re: Last Chance for Tarfessock1 Features
105385: 06/07/21: Re: Last Chance for Tarfessock1 Features
105403: 06/07/21: Re: Last Chance for Tarfessock1 Features
105405: 06/07/21: Re: Creating EDIF from Verilog, then using VHDL wrapper
105406: 06/07/21: Re: HW Debug tools
105412: 06/07/22: Re: Last Chance for Tarfessock1 Features
105413: 06/07/22: Re: Last Chance for Tarfessock1 Features
105415: 06/07/22: Re: Virtex 4, LVDS I/O: Sanity check please
105416: 06/07/22: Re: Last Chance for Tarfessock1 Features
105695: 06/07/28: Re: Spartan3 5V PCI
105749: 06/07/31: Low Cost FPGA Charge Pump Power supply
105756: 06/07/31: Re: Low Cost FPGA Charge Pump Power supply
105889: 06/08/02: Re: Virtex-4 RocketIO
105990: 06/08/04: Raggedstone1 ADV7202 Module
106242: 06/08/09: Development Board Offers
106655: 06/08/16: Re: Large Spartan3 vs. Small V5
108290: 06/09/07: Re: Xilinx LogiCORE PCI32
108365: 06/09/09: Re: Can a FPGA work like a microprocessor ?
108369: 06/09/09: Re: Virtex4FX12 and Spartan3 lead time
108558: 06/09/12: Re: Spartan-3: 5V -> 2.5V level shifting
108708: 06/09/15: Re: Spartan3 driving mosfets
108804: 06/09/17: Re: Board Opinions TS7300
108805: 06/09/17: Re: http://www.srisc.com ?
108806: 06/09/17: Re: USB programming cables
108826: 06/09/17: Re: Board Opinions TS7300
108848: 06/09/18: Re: SoC Development Board
108852: 06/09/18: Re: USB programming cables
109014: 06/09/20: Re: maximum life of FPGA based products ????
109118: 06/09/20: Re: maximum life of FPGA based products ????
109122: 06/09/20: Re: Lattice ispMACH4000 eval boards
109123: 06/09/20: Re: Lattice ECP2/M
109133: 06/09/21: Re: xilinx or altera?
109221: 06/09/21: Re: Dell Laptop for Embedded Work
109269: 06/09/22: Re: Fast Platform for ISE?
109336: 06/09/24: Re: Spartan 3 or 3E ?
109509: 06/09/27: Re: Driving a 30 bit wide LVTTL bus at 160MHz
109687: 06/10/03: Re: JTAG cable @ 2.5 V - where?
109701: 06/10/03: Re: JTAG cable @ 2.5 V - where?
109712: 06/10/04: Re: TTL signal to an FPGA I/O pin?
109797: 06/10/05: Re: How to accelerate bitstream file generation?
109892: 06/10/06: Re: Design of a programmable delay line
109920: 06/10/08: Re: Spartan 3 Starter Kit I/O ports
109926: 06/10/08: Enterpoint PCI Core
110149: 06/10/11: Re: 75Mhz Spartan3e microblaze
110218: 06/10/12: Re: XPLA3 going obsolete?
110272: 06/10/12: Re: Which Xilinx FPGA/board?
110290: 06/10/13: Re: Spartan-3/3E Board
110364: 06/10/14: Re: FPGA comparision
110568: 06/10/17: Re: Newbie : Please give me an idea about programming an FPGA
110590: 06/10/18: Re: Virtex-5 LXT launched today !
110598: 06/10/18: Re: Cheapest FPGA board to study VHDL on
110636: 06/10/18: Re: Learner
110638: 06/10/18: Re: Meeting Timing Constraint
110749: 06/10/21: Re: Code synthesizes to one FPGA but not to another?
110750: 06/10/21: Re: i486 FPGA replacement
110759: 06/10/21: Re: Code synthesizes to one FPGA but not to another?
110775: 06/10/22: Re: Potential problem w/EDK's Microblaze and the Spartan-3E Starter Kit?
110932: 06/10/25: Re: can someone recommend a board?
110934: 06/10/25: Re: can someone recommend a board?
111099: 06/10/29: Re: Virtex-4 & Wifi
111128: 06/10/29: Re: Stratix to PC communication
111255: 06/10/31: Re: FPGA's for Ethernet?
111380: 06/11/02: Re: Quartus synthesising out signals?
111521: 06/11/04: Re: PCI
111522: 06/11/04: Re: JTAG connection for chipscope
111666: 06/11/07: Re: Upgrading spartan-II: possible?
111766: 06/11/09: Re: drive LVDS clocks with a spartan3
111786: 06/11/09: Re: abel to vhdl converter
111823: 06/11/10: Re: Area Constraints in Xilinx
112005: 06/11/14: Re: Influence of temperature and manufacturing to propagation delay
112095: 06/11/16: Re: Old Spartan-II, worth prototyping?
112102: 06/11/16: Re: 8080 FSGA model in an FPGA
112216: 06/11/17: Re: PCMCIA interface
112278: 06/11/19: Re: PCMCIA interface
112432: 06/11/21: Re: ISE 8.2 & XC9500XL family
112579: 06/11/25: Re: run a counter without a clock
112605: 06/11/26: Re: Dev Kit Shipping Costs
112801: 06/11/29: Re: XC3020-50 board documentation
112874: 06/11/30: Re: ISE on a cluster?
113348: 06/12/11: Tarfessock1
113399: 06/12/12: Re: Tarfessock1
114203: 07/01/07: Re: WANTED: FPGA Development Board w/ Virtex-4 LX160/200 and 2 10/100 Ethernet PHYs
114206: 07/01/07: First Picture of Craignell Modules
114308: 07/01/11: Re: First Picture of Craignell Modules
114400: 07/01/14: Re: First Picture of Craignell Modules
114501: 07/01/17: Re: PCI Card with FPGA
114522: 07/01/18: Re: Xilinx website login problems
114712: 07/01/23: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114722: 07/01/23: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114865: 07/01/25: Re: Any UK mirror for ISE 8.2i SP2?
115328: 07/02/07: Re: Questions about pci transactions in my core
115730: 07/02/18: Re: Where to start???
116579: 07/03/13: Re: Heatsink on FPGA?
116756: 07/03/16: Re: Virtex5 LXT and synthesis..
116783: 07/03/18: Re: Eval board advice
116830: 07/03/19: Re: DDR2 and SDRAM modules for Raggedstone 1
116832: 07/03/19: Re: Eval board advice
116904: 07/03/20: Re: FPGA with 5V and PLCC package
117050: 07/03/22: Re: FPGA with 5V and PLCC package
117495: 07/04/02: Re: Standard PCI Xilinx board with Ethernet port
117496: 07/04/02: Re: Spartan-3A XC3S1400A development board?
117658: 07/04/06: Re: PCI FPGA Dev Board Suggestions
117692: 07/04/06: Re: PCI FPGA Dev Board Suggestions
117707: 07/04/07: Re: raggedstone + xc3sprog?
117729: 07/04/09: Re: raggedstone + xc3sprog? (solution and PHY question)
117767: 07/04/10: Re: raggedstone + xc3sprog? (solution and PHY question)
118211: 07/04/19: Re: Any recommendations for FPGA PCI development board?
118229: 07/04/20: DARNAW! - PGA Style FPGA Module
118233: 07/04/20: Re: DARNAW! - PGA Style FPGA Module
118242: 07/04/20: Re: FPGA Newbie
118274: 07/04/21: Re: DARNAW! - PGA Style FPGA Module
118275: 07/04/21: Re: Looking for a spartan 3 board
118276: 07/04/21: Re: DARNAW! - PGA Style FPGA Module
118283: 07/04/21: Raggedstone1 LVDS Oscillator
118421: 07/04/26: Re: DARNAW! - PGA Style FPGA Module
119045: 07/05/10: Darnaw1 - PGA Spartan-3E Module
119048: 07/05/10: Re: Darnaw1 - PGA Spartan-3E Module
119051: 07/05/10: Re: Darnaw1 - PGA Spartan-3E Module
119052: 07/05/10: Craignell - Spartan-3E DIL Module
119061: 07/05/10: Re: Darnaw1 - PGA Spartan-3E Module
119532: 07/05/22: Re: Xilinx doesn't detect setup/hold violations on synchronous reset
120200: 07/06/03: Raggedstone1 Brackets
120241: 07/06/04: Re: Lattice XP2 finally announced
120370: 07/06/05: Re: XILINX IPCore
120562: 07/06/10: Spartan3A-DSP Development Board
120621: 07/06/12: Re: UK shop - FPGA boards + chips.
120663: 07/06/13: Re: Stolen Spartan 3E-1600 Development Board
120814: 07/06/17: Re: anyone know a FPGA designer?
120929: 07/06/20: Re: Suggestions for Xilinx based evaluation board for image processing
120930: 07/06/20: Re: DFS to generate Frequencies slightly apart
120932: 07/06/20: Re: Interesting problems about high performance computing
121036: 07/06/23: Re: Reshipping spartan3 PCIE board to England
121079: 07/06/25: Re: Desperate to find the right FPGA board
121355: 07/07/03: Re: Xilinx PCI Express solutions
121434: 07/07/03: Re: Hobbyist trying to decide which device to start with...
121724: 07/07/12: Re: LiveDesign, Altium [opinion]
122050: 07/07/18: Re: Req: (Free) Embedded Platforms for Education
122100: 07/07/19: Enterpoint Web Site
122317: 07/07/25: Re: PC104+ communication with FPGA using Xilinx IPCore
122319: 07/07/25: Re: tiny Spartan 3 module?
122775: 07/08/06: Re: new to the group
123700: 07/09/02: Re: Spartan 3E starter kit (Rev.D) modification : 3E500 -> 3E1200
123701: 07/09/02: Re: PCIe question
124428: 07/09/21: Enterpoint Web Site
124642: 07/09/28: Re: job inquiry; entry/trainee FPGA/ASIC designer
124643: 07/09/28: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124666: 07/09/29: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124736: 07/10/02: Re: Basic VHDL Development kit
124924: 07/10/10: Re: UK Supplier XILINX spartan 3 development board??
126055: 07/11/13: Re: Structured way of changing eg time constants for real world build / simulation?
126076: 07/11/14: Re: FPGA for hobby use
126096: 07/11/14: Re: FPGA for hobby use
126313: 07/11/19: Re: TPS75003 Spartan-3(E) Regulator Design
126374: 07/11/20: Re: Virtex5 Evaluation Board
126376: 07/11/20: Re: Virtex5 Evaluation Board
126652: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126758: 07/12/01: Re: Traffic Light with counter
126897: 07/12/05: Drigmorn1 - The Cheapest FPGA Development Board???
126936: 07/12/06: Re: Drigmorn1 - The Cheapest FPGA Development Board???
126938: 07/12/06: Re: Drigmorn1 - The Cheapest FPGA Development Board???
126971: 07/12/07: Re: Drigmorn1 - The Cheapest FPGA Development Board???
126983: 07/12/07: Re: selecting FPGA
127002: 07/12/08: Drigmorn1 More Info
127086: 07/12/11: Craignell and Darnaw1 Website Updates
127090: 07/12/11: Re: Craignell and Darnaw1 Website Updates
127114: 07/12/12: Drigmorn1 User Manual
127146: 07/12/12: Re: FPGA Board design basics
127173: 07/12/13: Darnaw1 User Manual
127252: 07/12/15: Re: Getting started guide for Digilent Spartan 3E Starter Board?
127254: 07/12/15: LVDS on Drigmorn1
127301: 07/12/17: Tarfessock1 - FPGA Cardbus Development Board
127319: 07/12/18: Re: Darnaw module
127349: 07/12/19: Re: Darnaw module
127395: 07/12/20: Re: Routing Vccint on four-layer PCB
127429: 07/12/24: Darnaw1 - PGA FPGA Module
127449: 07/12/26: Re: Core Generators...
127469: 07/12/27: Re: Xilinx XST questions
127521: 08/01/01: Re: Sparkfun FPGA board ?
127847: 08/01/09: Re: Spartan3 vs cyclone
127983: 08/01/11: Re: FPGA evaluation board with > 32K slices
128160: 08/01/17: Re: Documentation on Insight VIRTEX-E Reference Board
128298: 08/01/20: Re: Sparkfun Spartean3e Board
128389: 08/01/24: Craignell FPGA DIL Module
128416: 08/01/25: Re: Virtex-4 driving a 5V CMOS
128419: 08/01/25: Craignell FPGA DIP Module
128439: 08/01/25: Re: Craignell FPGA DIP Module
128456: 08/01/27: Re: buying fpga kits in denmark
128638: 08/02/01: Re: Why use small resistor for Vcco voltage regulator
128899: 08/02/09: Re: Looking for a development board
129478: 08/02/25: Re: Xilinx parallel cable 4 clone
130120: 08/03/15: Re: Xilinx Tristate Registration
130395: 08/03/21: Re: Spartan 3E intefacing for dummies
130408: 08/03/22: Raggedstone1 OEM Pricing now released.
130470: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
131277: 08/04/17: Re: Survey: FPGA PCB layout
131328: 08/04/19: Re: Has anyone dealt with Avnet? or NuHorizons when trying to
131523: 08/04/24: Re: Turning off the DLL to run DDR2 at very low frequency
131669: 08/04/28: Darnaw1 Schematics
131823: 08/05/02: Re: Old FPGA question
131913: 08/05/07: Re: FPGA dev kit with 4-8 Cyclones or Spartans
132248: 08/05/19: Stratix IV Announced
132271: 08/05/20: Re: Stratix IV Announced
132469: 08/05/28: Re: Need comparison table about Xilinx ISE WebPack 10.1i vs ISE
133658: 08/07/08: Re: SBC with ADC, 1GE, and SATA2?
134131: 08/07/27: Re: Spartan-3A DSP 1800A Dev Board JTAG Cable and Programming
134469: 08/08/12: Re: Development board with SD card.
134592: 08/08/20: Re: Xilinx extends Spartan 3A series
135614: 08/10/09: Re: Those FPGA boards
135884: 08/10/20: Re: Looking for a FPGA board for starter
135957: 08/10/24: Hollybush2 - Soft Core Processor Board
135967: 08/10/24: Re: Small FPGA boards with USB/Ethernet
136008: 08/10/27: Re: Hollybush2 - Soft Core Processor Board
136081: 08/10/30: Polmaddie1 - For Traffic Lights Junkies
136084: 08/10/30: Re: Polmaddie1 - For Traffic Lights Junkies
136223: 08/11/07: Re: Tiny JTAG connector
136326: 08/11/11: Polmaddie1 - VHDL and Verilog Training Board
136350: 08/11/12: Re: Polmaddie1 - VHDL and Verilog Training Board
136410: 08/11/14: Polmaddie Development Board Family
136427: 08/11/16: Re: What happened to the Cyclone IV?
136444: 08/11/17: Re: Spartan-3E SDRAM interface
136561: 08/11/22: Re: Student FPGAs
136606: 08/11/25: Re: Student FPGAs
136919: 08/12/13: Re: dsp boards with multiple AD channels question
136927: 08/12/14: Re: new to FPGA
136986: 08/12/17: Re: Gigabit Ethernet PHY without NDA?
137182: 08/12/30: Re: Digilent
137327: 09/01/08: Re: How to contact SiliconBlue ?
137556: 09/01/22: Re: How to add some SDRAM to a FPGA board ?
137682: 09/01/27: Re: What software do you use for PCB with FPGA ?
137873: 09/02/01: Re: Selecting a starter FPGA board
137894: 09/02/02: Re: Selecting a starter FPGA board
138085: 09/02/05: Cheap Darnaw1 - PGA FPGA Module
138153: 09/02/08: Re: PLDShell Plus V5.1
138382: 09/02/18: Re: DDR3 with Spartan-3
138444: 09/02/23: Re: Spartan 3E Slave Serial problems
138446: 09/02/23: Re: Spartan 3E Slave Serial problems
138536: 09/02/26: Re: Send data from FPGA to PC via USB
138637: 09/03/02: New Boards
138641: 09/03/02: Re: New Boards
138642: 09/03/02: Re: New Boards
138643: 09/03/02: Re: New Boards
138665: 09/03/03: New Boards
138666: 09/03/03: New Boards
138667: 09/03/03: Craignell2 and Mulldonnoch2
138678: 09/03/04: Warning Search Engine Links
138684: 09/03/04: Re: Warning Search Engine Links
138696: 09/03/05: Re: Warning Search Engine Links
138946: 09/03/16: Re: Getting started with FPGA
138951: 09/03/16: Re: Getting started with FPGA
139118: 09/03/21: Re: How big is my vhdl and am I approaching some size limitation on
139120: 09/03/21: Re: R/A FX2 connectors for S3A board - anyone have a couple spare?
139165: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139175: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139185: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139209: 09/03/23: Re: Looking for a low-cost development kit
139214: 09/03/23: Re: Looking for a low-cost development kit
139218: 09/03/23: Re: low-power, high capacity data queue design ideas
139297: 09/03/25: Re: Using SelectIO LVDS to drive 40 inch backplane trace
139533: 09/04/02: Re: SSO
139578: 09/04/05: Re: clock multipliers, dividers, and more clocks...
139762: 09/04/12: Re: buy XSA-50
139887: 09/04/18: Re: FPGA Buying
139888: 09/04/18: Re: Dual-frequency quartz oscillator with a FPGA ?
140130: 09/04/29: Re: FPGA evaluation board for SD/SDHC Host controller
140375: 09/05/11: Re: Getting started with FPGA
140536: 09/05/16: Re: Cheap Ethernet PHY boards?
141308: 09/06/16: Re: 5.0V and 3.3V PCI interfacing with Altera Cyclone III
141589: 09/06/28: Re: Spartan3E or Cyclone III ?
141605: 09/06/29: Re: Spartan3E or Cyclone III ?
141824: 09/07/10: Re: Suzaku SZx30 or similar
141974: 09/07/20: Re: Suzaku SZx30 or similar
142031: 09/07/22: Re: Suzaku SZx30 or similar
142139: 09/07/26: Merrick1
142142: 09/07/26: Re: Merrick1
142143: 09/07/26: Re: How to start FPGA development
142400: 09/08/09: Spartan-6 Boards - Your Wish List
142404: 09/08/09: Re: Spartan-6 Boards - Your Wish List
142405: 09/08/09: Re: Spartan-6 Boards - Your Wish List
142410: 09/08/10: Re: Spartan-6 Boards - Your Wish List
142411: 09/08/10: Re: Spartan-6 Boards - Your Wish List
142418: 09/08/10: Re: Spartan-6 Boards - Your Wish List
142419: 09/08/10: Re: Spartan-6 Boards - Your Wish List
142424: 09/08/10: Re: Spartan-6 Boards - Your Wish List
142425: 09/08/10: Re: Spartan-6 Boards - Your Wish List
142433: 09/08/11: Re: Spartan-6 Boards - Your Wish List
142446: 09/08/11: Re: Spartan-6 Boards - Your Wish List
142447: 09/08/11: Re: Spartan-6 Boards - Your Wish List
142448: 09/08/11: Re: Spartan-6 Boards - Your Wish List
142462: 09/08/12: Re: Spartan-6 Boards - Your Wish List
142466: 09/08/12: Re: Spartan-6 Boards - Your Wish List
142467: 09/08/12: Re: Spartan-6 Boards - Your Wish List
142478: 09/08/12: Re: Spartan-6 Boards - Your Wish List
142600: 09/08/19: Re: Emulation of highly complex superscaler processor using FPGAs
142761: 09/08/30: Re: Selection of external clocks for FPGA system and bus interfacing
142762: 09/08/30: Re: Selection of external clocks for FPGA system and bus interfacing
142777: 09/08/31: Re: Selection of external clocks for FPGA system and bus interfacing
142988: 09/09/13: Spartan-6 - Pre-release Information on Drigmorn3.
142991: 09/09/13: Re: Spartan-6 - Pre-release Information on Drigmorn3.
143015: 09/09/14: Re: 8 phase clock output
143072: 09/09/18: Spartan-6 - Drigmorn3 Board Picture
143285: 09/09/29: Re: Searching for cost effective PCI express x1 core..
143319: 09/10/01: Drigmorn3 Update
143416: 09/10/10: Re: Development boards for CPU development ?
143448: 09/10/12: Re: Development boards for CPU development ?
143623: 09/10/19: Re: Any interest in a group Xilinx FPGA board build/buy ??
143630: 09/10/19: Re: Any interest in a group Xilinx FPGA board build/buy ??
143632: 09/10/19: Re: where can price list of FPGA be found?
143706: 09/10/22: Re: Time stability of clock on FPGA board
143775: 09/10/25: Re: Virtex 5 I/O
143852: 09/10/29: Re: Trouble in booting V5 FPGA from SPI flash.
143858: 09/10/30: Re: Trouble in booting V5 FPGA from SPI flash.
143900: 09/11/02: Drigmorn3 Update
143952: 09/11/04: Re: problem fpga aera optimization
144013: 09/11/06: Re: Does anyone ever use placement?
144124: 09/11/12: Re: Ethernet PCIe boards and PHY daughter cards?
144143: 09/11/13: Drigmorn2 - Spartan-3A Board
144238: 09/11/22: Cameralink
144267: 09/11/23: Re: PCI card unrecognized
144408: 09/12/04: Re: Where to go when Spartan-3A DSP 3400 is full?
144452: 09/12/08: Re: Cheapest way to get a chipscope compatible cable?
144456: 09/12/08: Re: Cheapest way to get a chipscope compatible cable?
144460: 09/12/09: Re: FPGA kit
144474: 09/12/09: No Reserve Board Sales
144511: 09/12/12: Re: Cheapest way to get a chipscope compatible cable?
144513: 09/12/12: Re: Does a 1-bit mux glitch if only one input is known to change at
144574: 09/12/15: Re: Best "bang for buck" Student Starter board for image/video
144596: 09/12/19: Re: Questions about Spartan 3A
144597: 09/12/19: Re: Trouble with Xilinx DCM - Spartan3
144601: 09/12/19: Re: Trouble with Xilinx DCM - Spartan3
144711: 09/12/27: Re: Info on heritage Nallatech board?
144763: 09/12/30: Enterpoint Moving Shipping Offer
144790: 10/01/03: Re: Cable autodetection failed
144800: 10/01/05: Re: Cable autodetection failed
144858: 10/01/07: Re: Difference among Virtex Families, FPGA Books
145044: 10/01/21: Re: Networking Board Recommendation
145277: 10/02/04: Prog3 - USB Programming Solution for Xilinx
145278: 10/02/04: Re: Board layout for FPGA
145282: 10/02/04: Re: Prog3 - USB Programming Solution for Xilinx
145394: 10/02/08: Re: different JTAG programming cables
145880: 10/02/26: Drigmorn3 - Spartan-6 Board Update
146128: 10/03/06: Re: Looking for a USB JTAG cable
146130: 10/03/06: Re: Display Control Application Using Spartan FPGA
146131: 10/03/06: Re: Ethernet development kit
146132: 10/03/06: Re: Laptop for FPGA design?
146164: 10/03/07: Re: Laptop for FPGA design?
146750: 10/03/27: Re: Multipliers in CoolRunner Series?
146751: 10/03/27: Re: Version of Xilinx ISE for Spartan 6 FPGAs
146753: 10/03/27: Re: PCB routing issues for sync SRAM
146925: 10/04/02: Re: FMC Boards ?
146927: 10/04/02: Raggedstone2 - PCIe Spartan-6 Board - Pre-release information
147000: 10/04/09: Enterpoint Moving
147013: 10/04/09: Re: Spartan-3 dsp FG676 Vccint decoupling caps
147243: 10/04/20: Raggedstone2 Spartan-6 Board Update
147265: 10/04/21: Polmaddie Family CPLD and FPGA Teaching Boards
147272: 10/04/21: Re: Polmaddie Family CPLD and FPGA Teaching Boards
147297: 10/04/22: Re: Polmaddie Family CPLD and FPGA Teaching Boards
147384: 10/04/25: Craignell2-48 - 48 Pin FPGA DIL Module
147392: 10/04/25: Re: Craignell2-48 - 48 Pin FPGA DIL Module
147393: 10/04/25: Re: Craignell2-48 - 48 Pin FPGA DIL Module
147687: 10/05/15: Re: Spartan 6 schedule
147688: 10/05/15: Craignell1 FPGA DIL Module - No reserve on Ebay
147705: 10/05/17: Re: using ChipScope to debug external design
147779: 10/05/23: Re: Xilinx Xact software for XC2018 Logic Cell Array
147790: 10/05/24: Re: Xilinx Xact software for XC2018 Logic Cell Array
147796: 10/05/24: Re: Xilinx Xact software for XC2018 Logic Cell Array
147892: 10/05/31: Re: Anyone else need bigger parts in small (low pin count) packages
148009: 10/06/13: Prog4 - Altera Programming Cable and a development board in one.
148038: 10/06/15: Re: Prog4 - Altera Programming Cable and a development board in one.
148041: 10/06/15: Re: Decoupling for Altera Cyclone II 2C8
148103: 10/06/21: Re: Xilinx BULLSHITIX-8, when?
148130: 10/06/22: Polmaddie Low Cost CPLD/FPGA Boards Update
148279: 10/07/04: Re: xilinx leadtimes
148283: 10/07/04: Re: xilinx leadtimes
148331: 10/07/07: Re: Programmer for Spartan-6
148341: 10/07/09: Craignell1 - No reserve
148379: 10/07/16: Drigmorn4 - Spartan-6 Board
148594: 10/08/04: Re: A question from a VHDL beginner
148731: 10/08/18: Re: Getting started with FPGA
148741: 10/08/19: Re: FPGA PCI BOARD .. Few Questions
148761: 10/08/19: Re: FPGA PCI BOARD .. Few Questions
148774: 10/08/20: Re: FPGA PCI BOARD .. Few Questions
148779: 10/08/20: Re: CPLD development board with 8-bit wide Flash/EEProm
148844: 10/09/02: Re: Want to get into FPGA
149048: 10/09/24: Re: Virtex5 minimodule
149067: 10/09/28: Re: FPGA For Image Processing[Economical]
149070: 10/09/28: Re: FPGA For Image Processing[Economical]
149082: 10/09/29: Re: SDRAM for specific use - performance and timing questions
149135: 10/10/04: Re: Actel bought by Microsemi
149140: 10/10/04: Re: Actel bought by Microsemi
149168: 10/10/05: Re: Xilinx Artix 7 - When?
149228: 10/10/10: Spartan-6 Boards
149236: 10/10/11: Re: Spartan-6 Boards
149238: 10/10/11: Re: Spartan-6 Boards
149244: 10/10/11: Re: Is Spartan 6 good for this project?
149260: 10/10/12: Re: Spartan-6 Boards
149455: 10/10/26: Re: using FPGA editor to set IOSTANDARD
149456: 10/10/26: Re: Using LVPECL_25 inputs in Spartan3e problem
149564: 10/11/05: Re: Good Dev Board
149598: 10/11/09: Re: INIT_B stays low
149637: 10/11/12: Re: Design chaos
149730: 10/11/21: Re: Spartan3 device with long availability
149743: 10/11/22: Re: Spartan3 device with long availability
149917: 10/12/02: Re: Help for a embeded system with SPARTAN-6 project
149931: 10/12/02: Re: What should I use for highspeed/low latency communication beteen
149985: 10/12/05: Re: FPGA BOARD QUESTION
150145: 10/12/19: Re: FPGA modules/cards with peripheral functions
150148: 10/12/20: Re: FPGA modules/cards with peripheral functions
150151: 10/12/20: Re: FPGA modules/cards with peripheral functions
150280: 11/01/07: Re: Cheap Altera dev board with LVDS-compatible connector?
150281: 11/01/07: Re: spartan 3 xc3s1000 not getting programmed
150282: 11/01/07: Re: spartan 3 xc3s1000 not getting programmed
150291: 11/01/08: Re: Cheap Altera dev board with LVDS-compatible connector?
150446: 11/01/21: Re: Overview for non-technicals.
150663: 11/02/01: Re: PCI Express Transfer
150667: 11/02/02: Re: PCI Express Transfer
150718: 11/02/06: Re: Why is the Cyclone IV so expensive?
150730: 11/02/07: Re: Looking for off-the-shelf 3.3 <--> 5v level shifter
150731: 11/02/07: Re: Why is the Cyclone IV so expensive?
150732: 11/02/07: Re: Why is the Cyclone IV so expensive?
150734: 11/02/07: Re: Looking for off-the-shelf 3.3 <--> 5v level shifter
150765: 11/02/09: Re: Good FPGA dev kit for a student who is not a complete newbie?
150766: 11/02/09: Re: Power consumption of Spartan-3A XC3SD1800A
150772: 11/02/10: Re: Good FPGA dev kit for a student who is not a complete newbie?
150776: 11/02/10: Re: Good FPGA dev kit for a student who is not a complete newbie?
150786: 11/02/10: Re: Good FPGA dev kit for a student who is not a complete newbie?
150848: 11/02/16: Re: PLD suggestions for classroom use
151083: 11/03/04: Re: Finding cheap PCI-E FPGA board for a student
151244: 11/03/17: Re: FPGA boards
151284: 11/03/20: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
151396: 11/04/02: Re: Ideal FPGA Development Kit
151404: 11/04/03: Re: Ideal FPGA Development Kit
151408: 11/04/03: Re: Ideal FPGA Development Kit
151498: 11/04/14: Re: Desperately looking for XC5VFX30T-3FFG665
151617: 11/04/26: Re: advice needed for FPGA chip selection
151650: 11/05/02: Raggedstone3 - Altera PCIe Development Board
151651: 11/05/02: XC3SD3400A Coprocessor Module
151664: 11/05/03: Re: XC3SD3400A Coprocessor Module
151678: 11/05/04: Re: Raggedstone3 - Altera PCIe Development Board
151868: 11/05/26: Re: PCI Express Cable
151943: 11/06/11: Re: Area Optimization
152016: 11/06/21: Re: Xilinx or Altera
152021: 11/06/22: Re: Xilinx or Altera
152038: 11/06/24: Re: Determine latency of GTX links vs Aurora+LVDS
152129: 11/07/12: XC6SLX150 Coprocessor Modules
152138: 11/07/13: Re: XC6SLX150 Coprocessor Modules
152144: 11/07/13: Re: Looking for a FPGA board
152159: 11/07/14: Enterpoint Recruiting
152243: 11/07/26: Re: Question on PCI-express verssus Standard PCI performance
152438: 11/08/23: Re: MAXDELAY constraint
152505: 11/08/29: Re: Very cheap Spartan3 board that can be configured by simple USB
152654: 11/09/23: Re: comparing Xilinx XC3S500E-4CPG132C vs Altera Cyclone IV FPGA
152668: 11/09/26: Re: FPGA + TVP70025i Board
152697: 11/10/03: Re: most stable version of ISE ?
152956: 11/11/04: Re: PCI Express development board
152960: 11/11/05: Re: Choose between Cyclone II and Spartan II
153011: 11/11/13: Enterpoint New Boards
153015: 11/11/14: Re: Enterpoint New Boards
153211: 12/01/08: Re: voltage drop on STRATIX FPGA supply planes
153213: 12/01/08: Re: Trying to select a development board, can somebody help me make
153217: 12/01/09: Re: voltage drop on STRATIX FPGA supply planes
153349: 12/02/04: Re: Xilinx Artix-7 availability
153435: 12/02/23: Re: What is a PLD/FPGA with serial or Ethernet port logic or block
153499: 12/03/15: Re: Internal BUS design: MUX or OR-GATE?
153581: 12/04/01: Re: Low latency FPGA options
153613: 12/04/04: Free Seminars/Labs - Implementing PCI Express Designs in FPGAs
153619: 12/04/05: Re: Free Seminars/Labs - Implementing PCI Express Designs in FPGAs
153621: 12/04/05: Re: Free Seminars/Labs - Implementing PCI Express Designs in FPGAs
153645: 12/04/09: Re: Best FPGA for algorithmic acceleration
153651: 12/04/10: Re: Watchdog reset for fpga designs
153681: 12/04/17: Re: Free Seminars/Labs - Implementing PCI Express Designs in FPGAs
153682: 12/04/18: Re: Free Seminars/Labs - Implementing PCI Express Designs in FPGAs
153693: 12/04/24: New Merrick6 Version
156867: 14/07/14: Re: Using FPGA as dual ported ram
John Aderseen:
102932: 06/05/23: Re: PCI 64/66 fpga eval boards
102933: 06/05/23: Re: PCI 64/66 fpga eval boards
103020: 06/05/24: Re: PCI 64/66 fpga eval boards
103054: 06/05/25: Re: PCI 64/66 fpga eval boards
103109: 06/05/25: Re: PCI 64/66 fpga eval boards
124779: 07/10/04: Re: Companies that Manufacture Multi-FPGA Hardware
127297: 07/12/17: Re: Xilinx MAC experience ?
127351: 07/12/19: Xilinx's ML505
131176: 08/04/14: Actel Cortex
John Ahlstrom:
4702: 96/12/03: Re: Addressbility.
John Allan Janusson:
3121: 96/04/08: new
John Andreasen:
6413: 97/05/22: X3000 Timing simulation with QVPRO testbench
John Archambeault:
7275: 97/08/20: Unbonded Pad Resources
7386: 97/09/05: Re: daisy-chained bitstreams
7378: 97/09/04: Re: daisy-chained bitstreams
7486: 97/09/16: Re: Choosing a good pin assignment for multiple-xilinx prototype.
7487: 97/09/16: Re: how generate xilinx 3020 EPROM?
7498: 97/09/17: Re: Choosing a good pin assignment for multiple-xilinx prototype.
7520: 97/09/18: Re: Atmel 17256 serial config EEPROMs
8120: 97/11/19: Re: changing default eprom output in MaxPlusII
8196: 97/11/26: Re: AT17C256 problems
John Ayer:
27308: 00/11/17: Re: COREGEN ROM in VHDL... How do I use it?
27713: 00/12/04: Re: which I/O pin belongs to each bank
27771: 00/12/07: Re: Need help regarding Partial reconfiguration
29171: 01/02/08: Re: First XILINX PCI core project
John B:
90648: 05/10/18: Re: LSI RAPIDCHIP
90651: 05/10/18: Re: LSI RAPIDCHIP
93454: 05/12/22: Re: real-time compression algorithms on fpga
John B. McCluskey:
1630: 95/08/08: Re: AT&T ORCA: Using register input mux?
1629: 95/08/08: Post: VHDL Source for 5x5 Image convolver in ORCA FPGA
1908: 95/09/19: Will Protel EDIF output work as input to Neocad?
2005: 95/10/01: Re: AT&T ORCA usable gate count?
John B. Sampson:
24717: 00/08/17: Re: Implementing an All Digital PLL in FPGA
John Becich:
18005: 99/09/22: Reasonable out-of-circuit programming platform desired
18010: 99/09/23: basic Altera simulation questions
18039: 99/09/24: How can I use an Altera .gdf file in my text file?
18043: 99/09/25: Re: basic Altera simulation questions
18048: 99/09/25: Altera hierarchical design
John Birkner:
8123: 97/11/19: Re: What is the difference between CPLD and FPGA ?
8127: 97/11/19: Re: ? State Machine Design
8242: 97/12/02: Re: what is metastability time of a flip_flop
8250: 97/12/03: Re: what is metastability time of a flip_flop
8254: 97/12/03: Re: what is metastability time of a flip_flop
8293: 97/12/05: Re: what is metastability time of a flip_flop
John Black:
66465: 04/02/19: Is this a bug in MAP?
67422: 04/03/11: System Ace: can not program Avnet V2P7 board
67663: 04/03/16: clock rising edge alignment
67754: 04/03/18: Virtex2P OCM is not cachable?
67820: 04/03/19: What's the flow V2P SysAce handles the software inside the ACE file
75663: 04/11/11: Virtex2P: lock down DCM and Global buffer
John Blaine:
44794: 02/07/01: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
45938: 02/08/12: Re: Power saving with Clock gating
45989: 02/08/13: Re: Power saving with Clock gating
45990: 02/08/13: Re: Advice regarding clock gating
62412: 03/10/29: Re: Power calculation using Xpower
John Blyler:
81663: 05/03/29: Looking for an FPGA blogger
132097: 08/05/13: Need help on ASIC/ASSP FGPA-based prototyping and verification survey
141229: 09/06/11: ASIC Proto and Verif with FPGA survey - Gift Certificate to Amazon
149145: 10/10/04: Why did Microsemi buy Actel?
John Bowen:
59144: 03/08/10: FPGA for a Newcomer
59196: 03/08/11: Re: FPGA for a Newcomer
John Branthoover:
35907: 01/10/23: Newbie: Need Help With Xilinx State Machine Using ABEL.....
35909: 01/10/23: Re: Newbie: Need Help With Xilinx State Machine Using ABEL.....
John Braun:
68188: 04/03/29: CLB usage: Xilinx XCS20 and Foundation 3.1
John Breslin:
20478: 00/02/11: re: Looking for a small, fast CPU core for FPGA
John Butler:
144723: 09/12/28: fsm coding question
John C:
98766: 06/03/16: Where are FPGA heading?
John C. Hart:
749: 95/02/22: Re: Real-time fractal gen in h/w
John C. Peck, Jr.:
4437: 96/10/29: Re: Question on Wavelet implementation
5814: 97/03/17: Re: Synopsys -> Altera (maxplus2) interface
John C. Randolph:
116513: 07/03/11: Need help bringing up PCIe at the physical layer.
116533: 07/03/12: Re: Xilin X-Fest Lunacy
John Cain:
492: 94/12/06: New Low Cost IC Design Software L-EDIT SE (PC)
15782: 99/04/13: Re: Lowest power for DSP
15801: 99/04/14: Re: Lowest power for DSP
17982: 99/09/20: Re: Problems with Lattice download
18166: 99/10/04: Re: ABEL for CPLD Design
19576: 00/01/01: Re: Design security
19583: 00/01/02: Re: Design security
19599: 00/01/03: Re: Design security
19603: 00/01/03: Re: Design security
19630: 00/01/04: Re: fpga cost
74925: 04/10/21: Re: strange behavior in lpm_counter
86470: 05/06/28: WTB FutureElectronics Cyclone NiosII Kit
John Campbell:
59119: 03/08/08: reconfiguration time
John Cappello:
72951: 04/09/08: Xilinx Virtex2: Erroneous DCM "Tap" Position after Reset
72996: 04/09/09: Re: Xilinx Virtex2: Erroneous DCM "Tap" Position after Reset
73059: 04/09/13: Re: Xilinx Virtex2: Erroneous DCM "Tap" Position after Reset
John Carter:
71404: 04/07/17: FPGA in a Compact Flash format.
John Cavazos:
6267: 97/05/06: CFP: Computing Surveys Tutorial Paper Contest
John Chambers:
7071: 97/07/29: MEM_CS16 TIMING (repeat)
7089: 97/07/30: Re: Quick prototyping? Best solution?
8723: 98/01/22: PCI Bus
10154: 98/04/30: Lattice 1016 Design Fit
10593: 98/06/04: LATTICE 2032 problems
11331: 98/08/05: Re: PCI Core In FPGA
13559: 98/12/09: Lattice Pin Drive Capability
13638: 98/12/15: Re: Parallel Port Pass Through Specs?
13954: 99/01/05: Re: 22V10 Metastability - help please
14640: 99/02/08: PLX9050 Dev. Software
21858: 00/04/04: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
24169: 00/07/28: 5V Lattice 1032E and 3.3V compatability
29866: 01/03/14: Re: Parallel Port EPP (again)
30152: 01/03/26: Re: Senior I/O Designer - Canada
John Cooley:
428: 94/11/15: Help: Seeking Your Opinion of EDN Article
474: 94/11/29: PLD's, FPGA's & VITAL
560: 95/01/04: What's Up At ViewLogic?
623: 95/01/20: 3 Verilog/FPGA Designers Needed For OVI Panel
624: 95/01/20: Quickie International Verilog Conference Info
706: 95/02/13: Free PCI Design Kit For Altera Customers
720: 95/02/16: Review of Two New Synopsys Tools
725: 95/02/17: YIKES! -- Cheapskate SNUG Deadline & Mini-DAC's
787: 95/03/02: IST Drying Up In North America
844: 95/03/10: SNUG 95 in 12 Days! OVI in 17 Days!
871: 95/03/17: Clarification of SNUG '95 Design Contest
1016: 95/04/14: $40 Million For NeoCAD & A New FPGA Synthesis Tool
1042: 95/04/19: SIS & MIS Public Domain Synth Tools
1049: 95/04/20: See Newborn Lambs Plus Meet The Real Aart & Harvey
1054: 95/04/21: Free WinEDA / PLD Con Evening Discussion
1055: 95/04/21: Re: See Newborn Lambs Plus Meet The Real Aart & Harvey
1186: 95/05/12: Verilog Won & VHDL Lost? -- You Be The Judge!
1216: 95/05/16: ---- Re: "Verilog Won & VHDL Lost?" ----
1313: 95/05/31: REPOST: "Verilog Won & VHDL Lost; You Be The Judge!"
1333: 95/06/02: Biblical Influences At PLD Con/WinEDA '95
1372: 95/06/08: ** Last Year: "DAC & The Grateful Dead" **
1377: 95/06/09: Forbidden DAC Panels, Free Lunch, Chrono & Exemplar
1408: 95/06/17: VHDL vs. Verilog happened at SNUG not IVC
1441: 95/06/23: ** Call For DAC Opinions For ESNUG Awards **
1493: 95/06/29: ## Sleep Deprivation, MacGyver & DAC'95 ##
1547: 95/07/13: Dog Food Drive For Joe Costello
1585: 95/07/21: Re: Dog Food Drive For Joe Costello
1598: 95/07/25: Re: Dog Food Drive For Joe Costello
1636: 95/08/09: Re: Dog Food Drive For Joe Costello
1652: 95/08/10: SNUG Europe 1995 Invite & Registration
1654: 95/08/11: Re: VHDL/FPGAs/PLDs help
1703: 95/08/17: Obscuring Code For Customers (was VHDL Obfuscators)
1714: 95/08/18: Re: Obscuring Code For Customers (was VHDL Obfuscators)
1716: 95/08/18: Re: Obscuring Code For Customers (was VHDL Obfuscators)
1786: 95/09/01: Re: Help Needed-FPGA Apps Eng.-Allentown,PA.-Recruiter
1788: 95/09/01: Re: Help Needed-FPGA Product Engineer-Allentown,Pa.-Recruiter
1787: 95/09/01: Re: Help Needed-FPGA Technical Engineer-Allentown,Pa.-Recruiter
1789: 95/09/01: Re: Need Help-FPGA Dev/Des.Eng.
1785: 95/09/01: Re: Help Needed-Technical Marketing Eng.FPGA-Allantown,Pa.-Recruiter
1834: 95/09/07: Jury Verdict + Test Benches
1868: 95/09/12: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
1880: 95/09/15: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
1954: 95/09/24: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
1990: 95/09/29: *** NEED HELP ON 'Cadence: The Good, The Bad, and The Ugly' ***
1992: 95/09/29: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
2034: 95/10/04: !!! Trolling For User Oriented DAC Ideas !!!
2137: 95/10/19: #### PANIC! Need Help On USE/DA Mentor Survey !! ####
2285: 95/11/17: Re: request for RTL netlists
2286: 95/11/17: NeoCAD and AT&T vs. Xilinx
2287: 95/11/17: Re: [q][Reverse Engineering Protection]
2288: 95/11/17: Vendors For Verilog On The PC
2302: 95/11/17: Re: X-Blox...The good, bad and ugly
2316: 95/11/19: Re: NeoCAD and AT&T vs. Xilinx
2323: 95/11/20: Rorschach Testing 273 Engineers With The Verilog-VHDL Contest
2326: 95/11/20: Re: [q][Reverse Engineering Protection]
2388: 95/11/27: Re: NeoCAD and AT&T vs. Xilinx
2407: 95/12/01: INDUSTRY GADFLY: The Fall(ing) VIUF '95
2450: 95/12/06: FBI Raids "Avant!" ("ArcSys") For Alleged Cadence Source Code Theft
2473: 95/12/12: **** YIKES! Need Help On Synopsys Report Card! ****
2577: 96/01/05: Advanced Program & Registration For SNUG '96
2578: 96/01/05: INDUSTRY GADFLY: SpeedSim's Three Dark Clouds
2581: 96/01/05: ** Reminder: USE/DA Lunch Meeting In Silicon Valley On Monday **
2583: 96/01/06: Re: INDUSTRY GADFLY: SpeedSim's Three Dark Clouds
2584: 96/01/06: Re: [q][Reverse Engineering Protection]
2585: 96/01/06: Re: INDUSTRY GADFLY: SpeedSim's Three Dark Clouds
2666: 96/01/22: How Big Chips Will Be Designed In The Not Too Distant Future
2667: 96/01/22: Chosing VHDL or Verilog Does Have An Impact For U.S. Engineers
2705: 96/01/26: ** ASIC Designers Wanted For Next Week's Great ESDA Shootout **
2713: 96/01/28: Re: Chosing VHDL or Verilog Does Have An Impact For U.S. Engineers
3014: 96/03/13: INDUSTRY GADFLY: "From Beirut To Bosnia" + Reader Response
3074: 96/03/27: (VHDL) Testbenches For The Great ESDA Shootout
3073: 96/03/27: (Verilog) Testbenches For The Great ESDA Shootout
3256: 96/05/03: Re: FPGA leaders - Who are they? Xilinx, Altera, Actel?
3306: 96/05/11: Re: [Q] SYNOPSYS, XILINX, VHDL mailing list ?
3343: 96/05/16: *** The Great ESDA Shootout ***
3344: 96/05/16: REPOST: Verilog Testbenches For "The Great ESDA Shootout"
3345: 96/05/16: REPOST: VHDL Testbenches For "The Great ESDA Shootout"
3366: 96/05/21: INDUSTRY GADFLY: "Barbarians At tHe Gate"
3436: 96/05/30: INDUSTRY GADFLY: Synopsys Redeemed; Summit Rises
3444: 96/05/31: REPOST: Sleep Deprivation, MacGyver & DAC '95
3448: 96/05/31: LAST MINUTE DAC NOTES
3500: 96/06/11: %% Trolling For DAC Dirt... From Users & The "Dark Side" %%
3575: 96/06/28: INDUSTRY GADFLY "Why I Hate Wally"
3596: 96/07/02: Re: INDUSTRY GADFLY "Why I Hate Wally"
3614: 96/07/03: Their Own Words: Cadence vs. Avant! (Cadence's Side Part 2)
3613: 96/07/03: Their Own Words: Cadence vs. Avant! (Cadence's Side Part 1)
3615: 96/07/03: Their Own Words: Cadence vs. Avant! (Avant!'s Side)
3651: 96/07/09: Re: why? internal error in VSS when simulting
3668: 96/07/10: Their Own Words: Cadence vs. Avant! (Avant!'s Court Filings 1/3)
3669: 96/07/10: Their Own Words: Cadence vs. Avant! (Avant!'s Court Filings 2/3)
3670: 96/07/10: Their Own Words: Cadence vs. Avant! (Avant!'s Court Filing 3/3)
3732: 96/07/22: ### 7 Quick Multiple Choice Questions ###
3784: 96/07/31: Re: Job posting
3792: 96/08/02: Re: US-NH FPGA Design Engineer, Avionics
3870: 96/08/12: Re: ### 7 Quick Multiple Choice Questions ###
3892: 96/08/15: Re: Technical Job posting ( and ads) not related to the newsgroup.
3924: 96/08/20: INDUSTRY GADFLY: EDA Goes OJ
3968: 96/08/26: Re: INDUSTRY GADFLY: EDA Goes OJ
3972: 96/08/27: Re: INDUSTRY GADFLY: EDA Goes OJ
3976: 96/08/28: Re: INDUSTRY GADFLY: EDA Goes OJ
4034: 96/09/04: Re: INDUSTRY GADFLY: EDA Goes OJ
4098: 96/09/10: ## Cadence: The Good, The Bad, & The Ugly ##
4119: 96/09/13: Re: INDUSTRY GADFLY: EDA Goes OJ
4709: 96/12/04: Re: What Does ASIC Stand For?
4743: 96/12/10: Re: ASICs Vs. FPGA in Safety Critical Apps.
6590: 97/06/04: + Last Year's (1996) DAC Trip Report +
6704: 97/06/17: ++ Trolling For DAC Dirt & Voices From The Dark Side ++
7374: 97/09/03: ### SNUG '98 CALL FOR PAPERS ###
7598: 97/09/25: Yikes! Only 4 Working Days Left For The SNUG'98 CFP Dealine!
8096: 97/11/17: REPOST: "Rorschach Test 273 Engineers With The Verilog/VHDL Contest"
8095: 97/11/17: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
8137: 97/11/20: Cooley's Great-Gobs-Of-Guilt-6-Months-After-DAC'97 DAC Survey
8194: 97/11/26: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
8195: 97/11/26: Re: Cooley's Great-Gobs-Of-Guilt-6-Months-After-DAC'97 DAC Survey
8324: 97/12/08: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
8325: 97/12/08: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
8340: 97/12/09: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
8382: 97/12/11: Pre-Reg Required For Free On-Line "Deep Submicron" Seminar
8750: 98/01/23: SNUG'98 Registration Is Now Open
8801: 98/01/27: Early Registration For EuroSNUG'98 (Paris) Ends In 7 Days
9465: 98/03/16: Re: Suggestions on synthesis/simulation packages under $10K
9582: 98/03/24: Need Your Help Reviewing The SNUG'98 / OVI/VIUF'98 Conferences
10055: 98/04/24: Why Altera & Cypress Software Clashes (was: VHDL compiler differences?)
10516: 98/05/26: Re: COMPARISON SYNTHESIS
10749: 98/06/15: Re: subscribe ESNUG
11508: 98/08/20: "Mike Barnicle, Plagiarism, & DAC'98" (Part 1 of 2)
11883: 98/09/16: SNUG '99 Call For Papers, DATE CHANGE, & Prelim Schedule
12716: 98/10/24: Re: Looking for Love in ALL the Wrong Places???
12752: 98/10/27: Wed. Night: "How To BS Your Way To Fame & Fortune In Consulting"
15807: 99/04/15: SNUG'99 Boston -- Call For Papers
16049: 99/04/29: One Sheep Farmer's Impressions of SNUG'99
16130: 99/05/05: Re: One Sheep Farmer's Impressions of SNUG'99
16218: 99/05/10: Re: One Sheep Farmer's Impressions of SNUG'99
16361: 99/05/18: Yikes! Only 2 Days Left For The Boston SNUG Call-For-Papers !
16874: 99/06/15: Re: delay line in FPGA / ASIC with VHDL
17363: 99/07/22: The User Written "DAC Trip Report" Is At http://www.DeepChip.com
17537: 99/08/07: Re: comparison with xxxx
18243: 99/10/09: Re: Mentor on a Laptop
18287: 99/10/12: SNUG'00 'Abstracts' Deadline Moved From Oct. 11th To Oct. 15th
23964: 00/07/18: 104 Page Collective DAC'00 Trip Report Up
24006: 00/07/20: Re: 104 Page Collective DAC'00 Trip Report Up
John Craven:
70811: 04/06/28: Answer Record # 18857 compiling modelsim library
John Crighton:
64427: 04/01/04: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
John D. Davis:
87295: 05/07/20: Creating Variable Delay for output signals in an XCV1000
87336: 05/07/21: Re: Creating Variable Delay for output signals in an XCV1000
88074: 05/08/08: Re: Creating Variable Delay for output signals in an XCV1000
88079: 05/08/08: No submodule instantiation as seen in FPGA Editor
88145: 05/08/10: Re: No submodule instantiation as seen in FPGA Editor
94821: 06/01/18: Data2Mem with CRC for Virtex FPGAs
94881: 06/01/18: Re: Data2Mem with CRC for Virtex FPGAs
95590: 06/01/24: Re: Data2Mem with CRC for Virtex FPGAs
John Daae:
44708: 02/06/27: Generate loop and RLOC
47411: 02/09/25: Clock balancing in DDR SDRAM design
50715: 02/12/18: Avoiding SRL16 in Synplify
55535: 03/05/12: Exploting the DDR input registers in Virtex2
55656: 03/05/15: Re: Exploting the DDR input registers in Virtex2
55756: 03/05/19: Re: Exploting the DDR input registers in Virtex2
John Dalmau:
484: 94/12/01: Altera VHDL Option Performance ?
485: 94/12/01: Altera VHDL Opt..Second Try!
John David Birch:
78206: 05/01/26: Xinx, FPGA Simulink Freeware/shareware ?
John Davidson:
78904: 05/02/09: newbie question
John Davis:
13021: 98/11/11: Test - Ignore2
13036: 98/11/12: Re: Test - Ignore
13037: 98/11/12: Re: Test - Ignore
John de Papp:
14412: 99/01/28: Mixed configuration daisy chain
John DeHaven:
1679: 95/08/15: Re: Xilinx FPGAs ---> Xilinx EPLDs
John DeRoo:
3414: 96/05/27: Re: impossible for Synthesizer to optimize FSM??!
John Derrick:
6001: 97/04/03: Re: PCI Bus Problems
John Devereux:
18836: 99/11/18: Re: Actel FPGA prices
115666: 07/02/16: Re: Building Coaxial transmission line on PCB?
125858: 07/11/07: Re: not totally repulsive
130324: 08/03/20: Re: A Challenge for serialized processor design and implementation
133940: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
141011: 09/06/02: Re: Tektronix vs. Agilent, probes
156261: 14/01/25: Re: my first microZed board
John Dimtsios:
59828: 03/08/28: Re: 5 volt tolerant Xilinx parts
John Doe:
18778: 99/11/14: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
18789: 99/11/15: Lattice LXOR2 Question
18967: 99/11/22: Re: VHDL vs. schematic entry
18968: 99/11/22: Leonardo Spectrum Printing Problem
22065: 00/04/17: Re: FPGA/PLD design tools?
136593: 08/11/24: Re: FMC/VITA 57
136596: 08/11/24: Re: FMC/VITA 57
john Doef:
92227: 05/11/24: Re: Case expression?
92241: 05/11/24: Re: Case expression?
John Doty:
69868: 04/05/22: Re: Transputer on FPGA
69876: 04/05/22: Re: Transputer on FPGA
John E. Chausse:
1353: 95/06/05: HELP AT6000
John E. Derrick:
41842: 02/04/09: Re: equivalence checking with FPGA
41979: 02/04/12: Re: prototyping an ASIC
42051: 02/04/14: Re: prototyping an ASIC
John E. Kuslich:
22951: 00/06/05: Re: SPICE help
John E. Perry:
23308: 00/06/21: Re: Designing a narrowband bandpass filter to pass a tone (analog
John E. Winkler:
1888: 95/09/15: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
John Eaton:
1631: 95/08/08: Re: Actel Place and Route response
3887: 96/08/14: Re: Xilinx XC3090 intermittent place/route problem
7044: 97/07/26: Re: PCI burst transfers
10384: 98/05/15: Re: Minimal ALU instruction set.
18823: 99/11/17: Actel FPGA prices
22767: 00/05/23: Re: Actel Pro Asic ?
27858: 00/12/12: Re: ActelDeskTop Macro fanout problem
33335: 01/07/23: Re: EDN
34375: 01/08/22: Re: Logic Emulation
41728: 02/04/05: Re: Free6502 ops
43824: 02/06/04: Re: FPGA destruction possible?
43892: 02/06/05: Re: FPGA destruction possible?
44968: 02/07/08: Re: Jtag extest
45658: 02/07/30: Re: lots of shift registers
45882: 02/08/08: Re: ... milk for free, Opencores?
46202: 02/08/21: Re: Huge discrepanzcy between gate-array and standard cell synthesis
46734: 02/09/06: Re: Actel Proto Boards
51097: 03/01/01: Re: BP programmer questions, prices, alternatives
53600: 03/03/17: Re: Help understanding 7408 and gate chip
53634: 03/03/18: Re: RESET --- Synchronous Vs Asynchronous
56153: 03/05/29: Re: Antifuse and SRAM FPGA
59180: 03/08/11: Re: Q: async flip-flop reset by a signal from a different clock domain
137236: 09/01/05: Re: DFFR using DFF (only, may be extra gates)
137240: 09/01/05: Re: DFFR using DFF (only, may be extra gates)
137289: 09/01/07: Re: DFFR using DFF (only, may be extra gates)
137353: 09/01/10: Re: Linux friendly FPGA dev board
137363: 09/01/11: Re: spartan 3an usb connection issue
138149: 09/02/07: Re: Recommended Xilinx USB JTAG cable?
138151: 09/02/07: Re: clk synchronization of reset signal
138216: 09/02/09: Re: Recommended Xilinx USB JTAG cable?
138227: 09/02/09: Re: Recommended Xilinx USB JTAG cable?
138775: 09/03/09: Re: Timing requirements for generating off-chip clock with DDR register
138786: 09/03/10: Re: Timing requirements for generating off-chip clock with DDR register
139514: 09/04/01: Re: Programming Digilent Nexys 2 from Linux
139593: 09/04/06: xilinx webpack on ubuntu jaunty jackalope beta
139730: 09/04/10: Re: Programming Digilent Nexys 2 from Linux
139750: 09/04/11: Re: Programming Digilent Nexys 2 from Linux
141608: 09/06/29: Re: usefulness of Virtex-II devices
John Edelman:
4307: 96/10/12: Re: help: max+ edif input problems
John Eppler:
8692: 98/01/20: Re: bypass for 68 pin PLCC
John Evans:
136490: 08/11/19: USB JTAG
John F Gostomski:
18807: 99/11/17: FPGA to ASIC conversion
18931: 99/11/22: Re: Virtex: Getting flip-flops into the pads
19101: 99/11/29: Re: Xilinx Virtex design (xcv-800) into production
John F. Eldredge:
12837: 98/11/01: Re: New Evolutionary Electronics Book
John Fielden:
20601: 00/02/15: Re: FPGA Express/XC4KXLA annoyance
22554: 00/05/11: Reccomend an ASIC emulation board
23469: 00/06/26: Virtex Demo Board
25819: 00/09/21: Uart core?
John Fields:
14123: 99/01/14: Re: *** FOR STEVE WALZ ONLY - PRIVATE AND PERSONAL - *** Re: FOR JOHN WOODGATE ONLY: ==> Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
31436: 01/05/23: Re: frequency ramp
112471: 06/11/22: Re: board - T562.jpg
112486: 06/11/23: Re: board - T562.jpg
112508: 06/11/23: Re: board - T562.jpg
112517: 06/11/23: Re: board - T562.jpg
112537: 06/11/24: Re: board - T562.jpg
112557: 06/11/24: Re: board - T562.jpg
112566: 06/11/24: Re: board - T562.jpg
112568: 06/11/24: Re: board - T562.jpg
112577: 06/11/25: Re: board - T562.jpg
112578: 06/11/25: Re: board - T562.jpg
112591: 06/11/25: Re: board - T562.jpg
112592: 06/11/25: Re: board - T562.jpg
112601: 06/11/25: Re: board - T562.jpg
112604: 06/11/26: Re: board - T562.jpg
112608: 06/11/26: Re: board - T562.jpg
112614: 06/11/26: Re: board - T562.jpg
115469: 07/02/12: Re: Building Coaxial transmission line on PCB?
115492: 07/02/12: Re: Building Coaxial transmission line on PCB?
115532: 07/02/13: Re: Building Coaxial transmission line on PCB?
150462: 11/01/23: Re: Xilinx news
John Fitzpatrick:
4238: 96/10/03: QuickLogic
John Forrest:
395: 94/11/06: Re: about downloading FPGAs
409: 94/11/10: Re: about downloading FPGAs
520: 94/12/18: Re: L-Edit and Benchmarks
540: 94/12/28: Problem with Flexlogic and PLDshell+
545: 94/12/29: Re: Which FPGA should I be looking at
546: 94/12/29: Re: Which FPGA should I be looking at
954: 95/04/03: Xilinx software upgrade problem
1061: 95/04/23: Re: Need "fusemap" information from vendor, likely?
1063: 95/04/23: Re: Intel Flex Download Cable
1261: 95/05/23: Re: FLEXlogic opinions?
1278: 95/05/25: Re: Altera Flex Logic & Other Problems
1449: 95/06/23: Re: Low cost FlexLogic programmer
1531: 95/07/10: Xilinx 5200 Software
1672: 95/08/14: Re: Xilinx xc4013 routing problems ??
1673: 95/08/14: Timespecs in XNF format
1701: 95/08/17: Re: external connections for efficient internal routing
2009: 95/10/02: Re: Xilinx Flash FPGA ??
2061: 95/10/08: Re: Programming a daisy chain of XC4000
2069: 95/10/10: Re: FPGA for a 20k gates micro-controller.
2094: 95/10/13: URL for UMIST Software Acceleration Work
2160: 95/10/23: Re: My own hard macro in VHDL?
2165: 95/10/23: Re: FPGAs as a substitute for glue logic?
John Francis:
145403: 10/02/08: Re: using an FPGA to emulate a vintage computer
145792: 10/02/24: Re: using an FPGA to emulate a vintage computer
146139: 10/03/06: Re: using an FPGA to emulate a vintage computer
146182: 10/03/07: Re: using an FPGA to emulate a vintage computer
146193: 10/03/08: Re: using an FPGA to emulate a vintage computer
146203: 10/03/08: Re: using an FPGA to emulate a vintage computer
John Funnell:
11531: 98/08/21: Big FPGA on PCI card with Linux support?
11970: 98/09/22: Efficient max-function architecture?
John G. Wohlbier:
5443: 97/02/16: Implementing Phase Comparator in XC7354
John Gallagher:
22592: 00/05/12: Re: Reccomend an ASIC emulation board
John Godden:
1871: 95/09/13: Newbie question about PLDshell
John Grant:
51806: 03/01/22: Re: SpartanII DLL lock issue
John Grider:
28599: 01/01/17: Re: About programming cables
28809: 01/01/24: Spartan-II serial vs. parallel configuration
30169: 01/03/26: Re: Alternatives for Xilinx Spartan-II configuration PROM
John Gulbrandsen:
117790: 07/04/10: Available: Detailed RISC CPU IP Core Design Documentation
John Hagerman:
3707: 96/07/18: Re: Hardware sort?
John Handwork:
36541: 01/11/11: Re: Quadrature Encoder Sampling Time
38819: 02/01/25: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
59187: 03/08/11: Re: a quick searching problem
59737: 03/08/27: Re: fixed point divider help
59740: 03/08/27: Re: Max finding
John Harrop:
13348: 98/11/29: Re: Looking for a good documentation on FPGA
13349: 98/11/29: Re: Looking for a good documentation on FPGA
13497: 98/12/06: CPLD with extended temperature (almost mil temp range)
John Hascall:
5388: 97/02/12: Re: DES Challenge
John Herman:
93083: 05/12/13: Re: How can I surpress noise in an ADC board?
John Heslip:
16765: 99/06/07: Altera 10K I/O's
John Hesse:
6375: 97/05/19: Re: Cadence or World Technology, or other NT vendors...
John Hovell:
44940: 02/07/06: Newbie FPGA recommedation
45237: 02/07/17: Simulating Xilinx Block RAM with ModelSim
45271: 02/07/17: Re: Simulating Xilinx Block RAM with ModelSim
45453: 02/07/23: Re: delay pipes in verilog for spartan IIe?
john hovey:
13244: 98/11/21: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13245: 98/11/21: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13246: 98/11/21: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13247: 98/11/21: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13269: 98/11/22: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
John Hsiu:
48162: 02/10/12: FPGA breadboard with a SmartMedia Card to store the bit file.
John Hu:
68507: 04/04/06: Re: Virtex II Pro vs Stratix
John Huang:
9042: 98/02/17: Viewlogic/Speedwave
10040: 98/04/24: Altera 10K20 Configuration problem
10095: 98/04/27: Re: Altera 10K20 Configuration problem
10322: 98/05/12: Altera 3.3V and 5V
10530: 98/05/28: SpeedWave Problem
10532: 98/05/28: SpeedWave problem
10601: 98/06/05: TESTBENCH
11976: 98/09/23: fpga-asic
11989: 98/09/23: Re: fpga-asic
12009: 98/09/24: Which FPGA tool is better
12095: 98/09/29: Fastest Add
12313: 98/10/09: LCELL delay of Altera 10K's
12329: 98/10/09: Re: LCELL delay of Altera 10K's
12425: 98/10/12: Re: VHDL Tool
13031: 98/11/12: WorkView office Library files need
13048: 98/11/13: Re: WorkView office Library files need
13066: 98/11/14: Help! ViewSynther Error
13085: 98/11/16: Help, Workview error!
13157: 98/11/18: Help for WorkView Office
13158: 98/11/18: Help for WorkView office
13749: 98/12/22: [Question] How to make Random in VHDL
14679: 99/02/11: Current of I/O driver
John Hubbard:
32394: 01/06/25: Re: XPower
32423: 01/06/26: Re: XPower
50412: 02/12/10: Re: CPLD current measurement
John Ireland:
22129: 00/04/26: Re: High Gate count?
John J. Hovey:
13206: 98/11/19: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
John J. Lee:
56425: 03/06/05: Re: ANN: Confluence -> Python for Hardware Verification
John Jacob:
50078: 02/11/30: Interfacing DSP to PCI bridge using a FPGA
50084: 02/11/30: Re: Interfacing DSP to PCI bridge using a FPGA
50085: 02/11/30: Re: Interfacing DSP to PCI bridge using a FPGA
50093: 02/12/01: Re: Interfacing DSP to PCI bridge using a FPGA
50101: 02/12/02: Re: Interfacing DSP to PCI bridge using a FPGA
50117: 02/12/02: Re: Interfacing DSP to PCI bridge using a FPGA
50203: 02/12/04: Re: Interfacing DSP to PCI bridge using a FPGA
50204: 02/12/04: Re: Interfacing DSP to PCI bridge using a FPGA
50206: 02/12/04: Re: Interfacing DSP to PCI bridge using a FPGA
John Jacobs:
70975: 04/07/03: Multi-phase Motor Controller?
john jakson:
49189: 02/11/04: Re: C\C++ to HDL Converter, why not HDL -> C instead
49210: 02/11/05: Re: C\C++ to HDL Converter, why not HDL -> C instead
49212: 02/11/05: Re: FPGA convert to ASIC
50089: 02/12/01: Re: Anybody know of vendors of PCI boards with FPGAs?
50382: 02/12/09: Re: vlsi implementation of multipliers
50735: 02/12/18: Re: MPEG FPGA
50736: 02/12/18: Re: Is it true that if you have a clock routed to non-clock resources then you are not allowed to use the clock nets?
50776: 02/12/19: Re: vlsi training in austria, greece, romania or hungary?
50951: 02/12/23: Re: FPGA Supercomputing opportunity
50952: 02/12/23: Re: distributed computing with Modesim
50955: 02/12/23: FPGA accelerated FPGA/ASIC tools
50978: 02/12/24: Re: FPGA Supercomputing opportunity
50998: 02/12/25: Re: FPGA accelerated FPGA/ASIC tools
51026: 02/12/26: Re: distributed computing with Modesim
51030: 02/12/26: Re: Want to buy an board with Xilinx FPGA Virtex II
51064: 02/12/29: Re: Future of VLSI in developing countries
51168: 03/01/04: Re: How can you tell if your clock signals are on the clock net?
51343: 03/01/10: Re: Virtex-II Pro misfire?
51344: 03/01/10: Re: VLSI training and prospects?
51385: 03/01/12: Re: Open FPGA please!
51392: 03/01/12: Re: Open FPGA please!
51394: 03/01/12: Re: Virtex-II Pro misfire?
51400: 03/01/12: Re: SChematic design approach compared to VHDL entry approach
51429: 03/01/13: Re: FPGA to ASIC migration - Help
51434: 03/01/13: Re: filter coefficient multiplication in vhdl
51549: 03/01/16: Re: SChematic design approach compared to VHDL entry approach
51576: 03/01/16: Re: Off Topic: Single Board Computers?
51596: 03/01/16: Re: SChematic design approach compared to VHDL entry approach
51601: 03/01/16: Re: quality of software tools in general
51665: 03/01/17: Re: quality of software tools in general
51666: 03/01/17: Re: quality of software tools in general
51676: 03/01/18: Re: quality of software tools in general
51716: 03/01/20: Re: New Language Generates Verilog, VHDL, and C
51746: 03/01/20: Re: frequency matching of ring oscillators
51747: 03/01/20: Re: Multi Project DIE
51802: 03/01/22: Re: VHDL or Verilog?
51890: 03/01/24: Re: free x86 core ip
51969: 03/01/27: Re: New to FPGA world...need guidline/help
52141: 03/02/02: Re: FPGA Overclocking
52411: 03/02/08: Re: Multicontext FPGA
52427: 03/02/09: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
52470: 03/02/10: Re: Multicontext FPGA
52490: 03/02/11: Re: Multicontext FPGA
52767: 03/02/20: Re: Gate boosting
53143: 03/03/04: Re: Mac Os X for FPGA design
53147: 03/03/04: Re: Implementation of latch in FPGA
53214: 03/03/06: Re: Issues in Outsourcing?
53215: 03/03/06: Re: Need help! Any experienced Handel-C user?
53226: 03/03/06: Re: Annapolis Microsystems Wildcard
53241: 03/03/07: Re: Implementation of latch in FPGA
53349: 03/03/11: Re: Interested in FPGA programming using systemc
53353: 03/03/11: Re: Are there any FPGA magazines/journals?
53358: 03/03/11: Re: FIR Filter from Xilinx
53366: 03/03/11: Re: Help understanding 7408 and gate chip
53529: 03/03/14: Re: Help understanding 7408 and gate chip
53531: 03/03/14: Re: About VLCT
53533: 03/03/14: Re: Integrating an VHDL component in a project in Handel-C
53594: 03/03/17: Re: FPGA dev boards
53599: 03/03/17: Re: Help understanding 7408 and gate chip
53645: 03/03/18: Increased Wafer yield by row adjusted placement
53648: 03/03/18: Re: how to calculate many CRC in FPGA ?
53726: 03/03/20: Re: Using FPGAs as coprocessors in a PC
53775: 03/03/22: Re: how do implement the algorithm in verilog?
53788: 03/03/23: Re: Using FPGAs as coprocessors in a PC - findings
53789: 03/03/23: Re: how do implement the algorithm in verilog?
53848: 03/03/25: Re: FPGA FFT Questions
53861: 03/03/25: Re: Increased Wafer yield by row adjusted placement
53905: 03/03/26: Re: Increased Wafer yield by row adjusted placement
53969: 03/03/28: Re: Quartus Synthesis
53973: 03/03/28: Re: XILINX FPGA as SUN Sparc coprocessor
53998: 03/03/30: Re: Increased Wafer yield by row adjusted placement
54005: 03/03/30: Re: $4000 FPGAs
54085: 03/04/02: Re: What would it take?
54191: 03/04/04: Re: More FFT Questions
54251: 03/04/05: Re: gated clock
54355: 03/04/08: Re: Hammond FPGA board
54504: 03/04/11: Re: An Improvement for the Booth multiplier
54508: 03/04/11: Re: Dynamic Reconfigurable FPGAs
54542: 03/04/13: Re: An Improvement for the Booth multiplier
54543: 03/04/13: Re: Hardware acceleration for raytracing purposes
56216: 03/05/30: Re: need help on sending 500Mbit/s data through 100 feet of cable, Giga-Ethernet?
56577: 03/06/09: Re: PC-104 dev Boards
58580: 03/07/27: Re: VHDL Book Recommendations Please
58644: 03/07/29: Re: Pricing question....
60090: 03/09/04: Re: New to FPGA, seeking advice
60200: 03/09/07: Re: CMOS camera w/ USB2 -- crazy?
62156: 03/10/20: Re: To our future engineers, smart and otherwise...
62157: 03/10/20: Re: Italy is out of FPGA world?
62553: 03/10/31: Re: Floating Point support
62616: 03/11/03: Re: Building the 'uber processor'
62693: 03/11/04: Re: Building the 'uber processor'
62727: 03/11/05: Re: Building the 'uber processor'
62734: 03/11/05: Re: Linux and FPGA compatibility
62762: 03/11/06: Re: Building the 'uber processor'
62763: 03/11/06: Re: Announcement
62818: 03/11/07: Re: FPGAs and DRAM bandwidth
62820: 03/11/07: Re: ASIC speed
62821: 03/11/08: Re: Building the 'uber processor'
62822: 03/11/08: Re: Building the 'uber processor'
64138: 03/12/18: Re: What is this ASMBL thing from Xilinx?
64140: 03/12/18: Re: From FPGA to ASIC these days
64425: 04/01/03: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
64644: 04/01/09: Re: Large/Fast static RAM
65013: 04/01/18: Re: Hardware to test (FPGA-based) prototype?
65014: 04/01/18: Re: Faster than a speeding bullet...
65015: 04/01/18: Re: Spartan XC2S200 - how many BlockRAMs ?
66552: 04/02/22: Re: Spartan 3 - avaliable in small quantities?
66562: 04/02/22: Re: Spartan 3 - avaliable in small quantities?
66565: 04/02/22: Re: Spartan 3 - avaliable in small quantities?
66581: 04/02/23: Re: Spartan 3 - avaliable in small quantities?
66585: 04/02/23: Re: Spartan 3 - avaliable in small quantities?
66599: 04/02/23: Re: Spartan 3 - avaliable in small quantities?
66626: 04/02/24: Re: Spartan 3 - avaliable in small quantities?
66640: 04/02/24: Re: Spartan 3 - avaliable in small quantities?
66757: 04/02/26: Re: difference btw H/W & S/W implementations !!
66840: 04/02/27: Re: Stratix 2 ALUT architecture patented ?
66842: 04/02/27: Re: Suggestions: Eval/Demo Board.
66879: 04/02/28: Re: FPGA implementation of ARM and IA32 ISA
67172: 04/03/07: Re: Implementing a reliable counter inside SDRAM memory mapped device
67339: 04/03/10: Re: novice for FPGA
67374: 04/03/10: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67375: 04/03/10: Re: Quartus II version 4 (Web Edition) DOES NOT WORK AT ALL !?
67407: 04/03/11: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67410: 04/03/11: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67412: 04/03/11: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67432: 04/03/11: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67435: 04/03/11: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67436: 04/03/11: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67439: 04/03/11: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67440: 04/03/11: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67441: 04/03/11: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67504: 04/03/12: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67505: 04/03/12: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67506: 04/03/12: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67514: 04/03/12: Re: Answering Machine RAM
67517: 04/03/13: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67519: 04/03/13: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67520: 04/03/13: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67521: 04/03/13: Re: Device/Board Selection (CPU Design)
67529: 04/03/13: Re: Device/Board Selection (CPU Design)
67553: 04/03/14: Re: Device/Board Selection (CPU Design)
67554: 04/03/14: Re: Device/Board Selection (CPU Design)
67556: 04/03/14: Re: Device/Board Selection (CPU Design)
67567: 04/03/14: Re: Board with all modules
67568: 04/03/14: Re: copy protection on FPGA using embedded serial number
67572: 04/03/14: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67575: 04/03/15: Re: copy protection on FPGA using embedded serial number
67585: 04/03/15: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67681: 04/03/17: Re: Schematic Edition Tool : Suggestions
67719: 04/03/17: Re: ISE 6.2 (w/ SP#1) is 10+ times slower than 6.1
67721: 04/03/17: Re: Device/Board Selection (CPU Design)
67724: 04/03/17: Re: Schematic Edition Tool : Suggestions
67726: 04/03/17: Re: PC104 Evaluation Board
67740: 04/03/18: Re: newbie question about fpga internals
67741: 04/03/18: Re: Spartan III availability
67839: 04/03/20: Re: Why It Is not Recommended to Infer latches in VLSI Design...
67893: 04/03/22: Re: 64bit cpu on Xilinx
68023: 04/03/24: Re: study verilog or vhdl?
68103: 04/03/26: Re: Estimate the gate sizes between ASIC and Virtex-2...
68139: 04/03/27: Re: study verilog or vhdl?
68151: 04/03/27: Re: study verilog or vhdl?
68152: 04/03/27: Re: study verilog or vhdl?
68153: 04/03/27: Re: study verilog or vhdl?
68201: 04/03/29: Re: study verilog or vhdl?
68203: 04/03/29: Re: FPGA Engineer w/clearance - where do you look for a job?
68297: 04/03/31: Re: Metastablility
68329: 04/04/01: Re: FPGA Engineer w/clearance - where do you look for a job?
68356: 04/04/01: Re: The mapper is getting rid of all my logic!!
68357: 04/04/01: Re: How to advertise in www.fpga-faq.com/FPGA_Boards.shtml
68436: 04/04/04: Re: AHDL, VERILOG or VHDL??
68535: 04/04/07: Re: how to get XST to infer 8:1 mux or just hard code it?
68598: 04/04/08: Re: how to get XST to infer 8:1 mux or just hard code it?
68631: 04/04/11: Re: Help need writing Single Port Block Ram in verilog
68642: 04/04/12: Re: Help need writing Single Port Block Ram in verilog
68747: 04/04/16: Re: Osborne [Was: Apples to Apples? Stratix II <> Virtex-II Pro]
68914: 04/04/21: Re: calculate the number of logic gate in FPGA
68954: 04/04/22: Re: Best Xilinx toolchains for under $2,000 ?
69018: 04/04/25: Re: Newbie question: which choice is right for my engineering project?
69020: 04/04/25: Re: transport applications
69053: 04/04/26: Re: ASIC RTL and FPGA RTL
69054: 04/04/26: Re: Inferring Dynamic shift registers in XST
69107: 04/04/27: Re: transport applications
69108: 04/04/27: Re: Inferring Dynamic shift registers in XST
69131: 04/04/27: Re: transport applications
69178: 04/04/29: Re: VHDL / Verilog circuits work in 1-V still correct?
69253: 04/05/03: Re: Cheap SRAM?
69340: 04/05/07: Re: Which board to buy? Status of open source tools?
69573: 04/05/14: Re: Simple way to generate random netlists of ALU cells
69600: 04/05/14: Re: One issue about free hardware
69610: 04/05/15: Re: Simple way to generate random netlists of ALU cells
69611: 04/05/15: Re: Clueless newbie question -- what has changed to make moisture such an issue?
69615: 04/05/15: Re: Effects of moisture on CPLD
69848: 04/05/21: Re: Never right, always room for improvement
69849: 04/05/21: Re: Never right, always room for improvement
69869: 04/05/22: Re: Transputer on FPGA, was: Re: Never right, always room for improvement
69873: 04/05/22: Re: Transputer on FPGA
69874: 04/05/22: Re: Reg learning FPGA backend
69875: 04/05/22: Re: Transputer on FPGA
69882: 04/05/23: Re: Transputer on FPGA
69915: 04/05/24: Re: Transputer on FPGA
69992: 04/05/26: Re: Never right, always room for improvement
70164: 04/06/07: Re: Quick question
70235: 04/06/09: Re: Good SDRAM Controller
70332: 04/06/12: Re: SDRAM
70581: 04/06/21: Re: >Math Skills = >Engineer ?
70626: 04/06/22: Re: system verilog
70819: 04/06/29: Re: FPGA jobs in Germany
70908: 04/07/01: Re: Compact FPGA Board?
70950: 04/07/02: Re: Why this statement renders TWO multipliers in XST?
71385: 04/07/16: Re: FPGA with fully asynchronous RAM
71461: 04/07/19: Re: FPGA with fully asynchronous RAM
71542: 04/07/21: Re: FPGA with fully asynchronous RAM
72022: 04/08/05: Re: What is the future of superconducting circuits
72603: 04/08/26: Re: DSP/FPGA/video board?
72734: 04/08/30: Re: FPGA Floating Point Multiplier Design
72777: 04/09/01: Re: FPGA Floating Point Multiplier Design
73041: 04/09/11: Re: Need some help with some technical claims...
73620: 04/09/26: Re: FPGA -> ASIC
74200: 04/10/05: Re: Sine function implementation in FPGA??
74436: 04/10/11: Re: CAche memory
74502: 04/10/12: Re: Actel Fusefile Reverse Engineering
76078: 04/11/23: Re: TSMC release 40V 0.18u process, MTP comming
76361: 04/11/30: Re: 99% Utilisation !
76439: 04/12/02: Re: 99% Utilisation !
76473: 04/12/03: Re: Searching for rad tolerant, non-volatile (once programmable) FPGA (or CPLD).
John Jakson:
32542: 01/06/29: Re: Is the Grass Greener for an Engineer in the USA?
35661: 01/10/12: Re: Small FPGA proto boards
35894: 01/10/22: Re: Verilog vs. VHDL
36708: 01/11/16: Re: Prototyping Board
37916: 01/12/24: Re: You take the low road and I'll ......
38148: 02/01/07: Re: PCI Solution: LogiCore?
42612: 02/04/29: Re: Xilinx Programmable World 2002 - Review
45798: 02/08/06: Xilinx hiring practises
45814: 02/08/06: Re: Xilinx hiring practises
46805: 02/09/09: Re: C/C++ to Verilog/VHDL ?!
50833: 02/12/20: FPGA Supercomputing opportunity
50853: 02/12/20: Re: FPGA Supercomputing opportunity
50862: 02/12/21: Re: FPGA Supercomputing opportunity
54617: 03/04/15: Re: error correcting codes
John Janssen:
27755: 00/12/06: Re: Issues with Spartan II
31209: 01/05/15: Where to get a FREE IP-core for PCI 2.1 ?
John Janusson:
15955: 99/04/23: Re: Xilinx Spartan experience?
16001: 99/04/27: Re: Digital Phase Locked Loop
16158: 99/05/06: Re: How do I design this ?
17000: 99/06/22: Re: Exhaustedly I come for Digital PLL help
19382: 99/12/17: Re: How to include SpartanXL code in C souce code?
19614: 00/01/04: Re: Decoding RSPC (Reed Solomon Product Code)
20234: 00/02/01: Xilinx Virtex Decoupling Cap Guidelines
20361: 00/02/07: Re: Xilinx vs Altera
21034: 00/03/03: Re: SpartanXL route and place
22891: 00/05/30: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
24886: 00/08/21: Re: Distributor attitude !!
27110: 00/11/11: Re: Configuring Xilinx FPGA using PIC16F84
27316: 00/11/17: Re: Schematics & VHDL
john jardine:
115504: 07/02/12: Re: Building Coaxial transmission line on PCB?
115559: 07/02/13: Re: Building Coaxial transmission line on PCB?
115563: 07/02/13: Re: Building Coaxial transmission line on PCB?
John Jardine:
67547: 04/03/14: Re: ANN: new Pulsonix version 3 PCB software released
John Jardine.:
95276: 06/01/21: Re: OT:Shooting Ourselves in the Foot
John Jerz:
59366: 03/08/16: SynplifyPro Mapper runs endlessly
John K.:
57047: 03/06/22: What's the difference between ASIC and FPGA?
60119: 03/09/05: Schematic simulation and then FPGA programming?
60147: 03/09/05: Re: Schematic simulation and then FPGA programming?
60191: 03/09/07: Re: Schematic simulation and then FPGA programming?
John Kennedy:
12973: 98/11/09: help xc3000 series
13946: 99/01/04: Bit-Serial Multiplier
JOHN KENNEDY:
12955: 98/11/07: How to determine macro size in Xilinx Foundation?
John Kortink:
21293: 00/03/15: Re: Atmel censors web access
21353: 00/03/18: Re: Is there a cheaper alternative to ByteblasterMV?
25945: 00/09/27: Altera EPM3256ATC144 equivalents
108394: 06/09/10: Can someone erase my EPM7064s ?
110780: 06/10/23: How do I erase an Altera EPM7064 with JTAG lockout
111052: 06/10/28: Re: A spectre is haunting this newsgroup, the spectre of metastability
John Kramer:
6679: 97/06/13: Re: Power consumption (Xilinx FPGA) questions
6711: 97/06/18: test - don't read
6710: 97/06/18: test - don't read
John L. Bass:
69032: 04/04/25: Need last service pack for Xilinx ISE 4.2i
John L. Smith:
4163: 96/09/20: Re: FPGAs design tools for PC
4204: 96/09/25: Re: 4800 baud serial input to xc4000
4273: 96/10/08: Reversible LFSR?
4297: 96/10/11: Re: FPGA Web Links
4315: 96/10/14: Re: Async with FPGA?
4588: 96/11/18: Re: VHDL adder: how do I get at the carry bit?
4726: 96/12/06: Re: Name this chip !!
4777: 96/12/13: Re: ASICs Vs. FPGA in Safety Critical Apps.
4803: 96/12/16: Re: ASICs Vs. FPGA in Safety Critical Apps.
4866: 96/12/20: Re: I2C Bus Interface in FPGAs
4987: 97/01/08: Re: FAQ
5118: 97/01/24: Re: XC6200 Announcement by VCC
5131: 97/01/25: Re: FPGA & division
5132: 97/01/25: Re: Processorless FPGA computer help
5375: 97/02/11: Re: Random Number Generators with Xilinx FPGA xc4000 series
5376: 97/02/11: Re: Random Number Generators with Xilinx FPGA xc4000 series
5597: 97/02/27: Re: Xilinx or Altera?
5736: 97/03/11: Re: Xilinx FPGA & SIMMs
6010: 97/04/04: Re: New Technology
8040: 97/11/10: Re: Division using FPGAs
8473: 97/12/18: Re: md5 in a FPGA?
10855: 98/06/25: Re: How to Double Clk Freq in the FPGA design
10884: 98/06/27: Re: Xilinx Foundation simulator problem?
10643: 98/06/08: Re: XC4000: post routing "customization"
10644: 98/06/08: Re: XC4000: post routing "customization"
11414: 98/08/11: Re: Combinatoric Divide-by-3 Algorithm
11418: 98/08/11: Re: Combinatoric Divide-by-3 Algorithm
11448: 98/08/14: Re: FFT-Speed
11454: 98/08/15: Re: FFT-Speed
11505: 98/08/19: Re: Help on Xilinx !
11515: 98/08/20: Re: vector product minimization problem
11591: 98/08/25: Re: vector product minimization problem
11606: 98/08/26: Re: vector product minimization problem
11627: 98/08/27: Re: Busses in Xilinx Foundation's schematic capture program
11790: 98/09/09: Re: 22V10 programming
11807: 98/09/10: Re: Need Permutation generator
11866: 98/09/15: Re: ASIC -> FPGA async issues
11867: 98/09/15: Re: ASIC -> FPGA async issues
12542: 98/10/15: Re: Digital Sine Generator
12618: 98/10/20: Re: Schematic entry?
12982: 98/11/09: Xilinx Floorplanner Support for Virtex?
13746: 98/12/21: Re: Xilinx FlowEngine vs Batch file?
14294: 99/01/23: 8x8 (x8 -> 11) DCT Implementation Results?
15848: 99/04/16: Re: High speed reconfigurability
16008: 99/04/27: Re: Storage of 32Bit-Vectors
16077: 99/04/30: Re: Storage of 32Bit-Vectors
16079: 99/04/30: Re: High speed PLL inside FPGA
19280: 99/12/09: Re: Is there two-read one-write asynchronous SRAM in FPGA?
19284: 99/12/09: Re: Is there two-read one-write asynchronous SRAM in FPGA?
19415: 99/12/20: Re: Dumb question springing from a discussion about chess on a chip...
19837: 00/01/13: Re: PCI Bus Problems with Burst Transfers
20231: 00/02/01: Re: Count 1's algorithm...
21155: 00/03/08: Re: Q: Hitachi FPGA HD61J215P: Searching Infos!!!
21225: 00/03/10: Re: Virtex and Virtex E package availability
21917: 00/04/06: Re: PCI Bridge to Xilinx XCV*E
24481: 00/08/10: Re: Can i see Gate-delay and Interconnection-delay of circuit on FPGA
24483: 00/08/10: Further FPGA metastability questions
25092: 00/08/25: Is there any way to configure the Virtex BRAM outputs as direct, i.e.,
25359: 00/09/07: Re: XC3000A Configuration data
25435: 00/09/11: Re: Clock skew in XILINX CPLD
25503: 00/09/12: Re: computing difference between Gray values?
25602: 00/09/14: Whoa, Noise on a digital output pin?, and Minor rant on XC9500 S/W, was
25638: 00/09/15: Re: hardware compatibility and patent infringement
25700: 00/09/17: Re: virtex shape
26148: 00/10/05: Re: Whoa, Noise on a digital output pin?, and Minor rant on XC9500 S/W,
26944: 00/11/03: I2C Recieved by Xilinx, was Re: I2C bus driven by Xilinx
27199: 00/11/14: Re: CRC, LFSR and scramblers
28387: 01/01/10: Re: grey code counters
28754: 01/01/23: Re: Xilinx XCell is not on-line?
John L. Smith, Principal Engineer:
3504: 96/06/11: Re: FPGA Companies
John Larkin:
13977: 99/01/06: CRC16 maybe?
14037: 99/01/08: Re: fpga socket
14164: 99/01/16: Re: Xilinx Bitstream
14281: 99/01/23: Re: Q: Counting GHz pulses - ?
14622: 99/02/06: Xilinx de-compiler
14628: 99/02/07: Thank You
14636: 99/02/07: Re: Xilinx de-compiler
14841: 99/02/19: Xilinx config from MC68332
18249: 99/10/09: test
18367: 99/10/20: Re: New to FPGA
18770: 99/11/13: Re: How many bits in an FPGA bitstream?
18816: 99/11/17: Re: COM1-FPGA communication
18886: 99/11/19: Re: How many bits in an FPGA bitstream?
18940: 99/11/22: Re: PADS Experience?
18976: 99/11/22: Re: VHDL vs. schematic entry
18999: 99/11/23: Re: VHDL vs. schematic entry
19025: 99/11/24: Re: VHDL vs. schematic entry
19032: 99/11/24: Re: VHDL vs. schematic entry
19601: 00/01/03: Actel repair assistance
19720: 00/01/09: Re: Make thousands$$$$ form only $6!!!!!!!!!!!!!!!!!
19897: 00/01/16: Re: Random Number Generator
19928: 00/01/18: Re: Random Number Generator
19941: 00/01/19: Re: Random Number Generator
19967: 00/01/20: Re: Random Number Generator
19968: 00/01/20: Re: WebFitter???
20005: 00/01/22: Re: Virtex Fine Pitch BGA pcb layout
20009: 00/01/22: Re: Virtex Fine Pitch BGA pcb layout
20015: 00/01/23: Re: Virtex Fine Pitch BGA pcb layout
20061: 00/01/25: Re: Virtex Fine Pitch BGA pcb layout
20072: 00/01/26: Re: Virtex Fine Pitch BGA pcb layout
20328: 00/02/05: Re: Xilinx "WebCD" gripes
20512: 00/02/12: Re: xilinx
20527: 00/02/13: Re: xilinx
20532: 00/02/13: Re: xilinx
21101: 00/03/06: Re: Design security
21433: 00/03/22: Re: Foundation 2.1: Prevent Optimizing away of open Signals/Pins ?
21575: 00/03/25: Re: FPGA & single point failure
21763: 00/03/30: Re: What's so good about antifuse???
22326: 00/05/04: Re: Q: simplest FPGA structure for novel technology demonstration
22901: 00/05/30: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
23044: 00/06/10: math help needed
23215: 00/06/17: Re: Problem copying text from the Spartan II data sheet
23229: 00/06/17: Re: Problem copying text from the Spartan II data sheet
23237: 00/06/18: Re: Problem copying text from the Spartan II data sheet
23263: 00/06/19: Re: Problem copying text from the Spartan II data sheet
23379: 00/06/23: Re: What tools do people use for Xilinx FPGAs?
23585: 00/07/01: Re: Which notebook is for you?
23588: 00/07/01: Re: Which notebook is for you?
23608: 00/07/02: Re: Remedies after the Fathers' Day Massacre
23609: 00/07/02: Re: why???
23628: 00/07/03: Re: Altera Ships Largest PLD
23810: 00/07/10: PCI to dual-port memory
23994: 00/07/19: Re: Xilinx Logic Cell counts and carry chains
25115: 00/08/26: Balls!
25140: 00/08/27: Re: FPGA power pins decoupling <-> PCB autorouting
25180: 00/08/29: Re: Xilinx and CD databooks (rant)
25189: 00/08/29: Re: Xilinx and CD databooks (rant)
24917: 00/08/21: Re: Some notes on metastability
25267: 00/09/03: Re: Balls!
26330: 00/10/11: Re: palasm
27303: 00/11/17: Xilinx config bits
27330: 00/11/17: Re: In the news
27369: 00/11/19: Re: Xilinx config bits
27570: 00/11/28: Re: Newsgroup : Accessing through Netscape Navigator
27143: 00/11/12: Re: HOW TO TURN $6 INTO $6,000!!!!!!
27950: 00/12/16: Re: Help configuring Spartan II using processor
28169: 00/12/23: Re: Power consumption FPGA...
28254: 01/01/03: Re: Fixing pins on Spartan II
29269: 01/02/11: Re: OT: IEEE & Floating point
29517: 01/02/24: Re: Is anybody using Quicklogic PCI/FPGA devices?
29518: 01/02/24: Re: Soldering and Unsoldering PQFP by hand ...
30968: 01/05/05: Re: High resolution time measurement?
30974: 01/05/06: Re: High resolution time measurement?
31076: 01/05/10: Spartan Annoyances
31158: 01/05/13: Re: Spartan Annoyances
32994: 01/07/14: Re: Downloading file to Xilinx (Vertex_E) FPGA.
32995: 01/07/14: Re: Pins state on Spartan XL before config.
33224: 01/07/19: Re: Working Design - Anyone
34342: 01/08/21: Re: hardware damage to a Virtex or Spartan-II?
34418: 01/08/23: Re: Latest Maxim bit serializer-deserializer chip announcements
34457: 01/08/25: Re: Latest Maxim bit serializer-deserializer chip announcements
35354: 01/09/30: Re: future Xilinx products wish list ...
36616: 01/11/13: Re: ideas
36879: 01/11/22: Re: Decoupling capacitors on Virtex II
36898: 01/11/23: Re: Decoupling capacitors on Virtex II
37583: 01/12/16: Re: annoying problem
42145: 02/04/16: FPGA Timing Problem
42873: 02/05/05: Re: Xilinx IOBUF?
42877: 02/05/05: Re: Xilinx IOBUF?
42895: 02/05/06: Re: Xilinx IOBUF?
42912: 02/05/06: Re: Opinions on FPGA cores - best for a commercial project?
43298: 02/05/18: Re: HardPath
44478: 02/06/20: Re: Power supply caps on PCB
44724: 02/06/27: Silly questions about configuring Spartan 2's
45232: 02/07/16: Re: LVDS interface cable recommendation sought
45357: 02/07/19: Re: spiral / waterfall /watersluice : Which are your methods?
45366: 02/07/20: Re: spiral / waterfall /watersluice : Which are your methods?
45371: 02/07/20: Re: spiral / waterfall /watersluice : Which are your methods?
45372: 02/07/20: Re: spiral / waterfall /watersluice : Which are your methods?
45656: 02/07/30: lots of shift registers
45916: 02/08/10: unloading a fast ADC
46166: 02/08/20: TQFP 176 socket
46187: 02/08/21: Re: "Tall Thin Engineer"
47853: 02/10/05: Re: Moving average filter
48555: 02/10/20: Re: Number of Fpga posts vs dsp..
49098: 02/10/31: Re: How important is simulation?
49151: 02/11/02: Re: How important is simulation?
49152: 02/11/02: Re: Asynchronous clock enable with stable data
49334: 02/11/09: Re: new to fpga, what language is better to start with
51396: 03/01/12: Re: SChematic design approach compared to VHDL entry approach
51647: 03/01/17: Re: Lecroy Research Systems - what happened?
51657: 03/01/17: Re: Lecroy Research Systems - what happened?
52844: 03/02/24: Xilinx FPGA on PCI board
53379: 03/03/12: Re: footprints
54243: 03/04/05: Re: 2.5V switching regulator for Spartan 2
56574: 03/06/09: Balls! (676 of them)
62013: 03/10/16: Configuration Blues
62088: 03/10/18: Re: Configuration Blues
70485: 04/06/17: compressing Xilinx bitstreams
70495: 04/06/17: Re: compressing Xilinx bitstreams
70536: 04/06/19: Re: compressing Xilinx bitstreams
70550: 04/06/20: Re: compressing Xilinx bitstreams
75740: 04/11/13: Re: Digital LP filter in multiplier free FPGA
75742: 04/11/13: Re: Digital LP filter in multiplier free FPGA
75743: 04/11/13: Re: Digital LP filter in multiplier free FPGA
81518: 05/03/25: cheap Xilinx tricks
81531: 05/03/26: Re: cheap Xilinx tricks
81534: 05/03/26: Re: cheap Xilinx tricks
81610: 05/03/28: Re: cheap Xilinx tricks
81745: 05/03/30: Re: Instantiate RAM in Spartan3
81792: 05/03/31: Re: cheap Xilinx tricks
81793: 05/03/31: Re: LVPECL, Virtex II and the EP445
82268: 05/04/09: Re: Neural Networks in FPGA
82348: 05/04/11: Re: DC component removal in FPGA
82378: 05/04/11: Re: DC component removal in FPGA
82613: 05/04/14: Re: Reading old F2.1i schematics
82831: 05/04/18: Re: Declining a job offer
82930: 05/04/19: Re: Declining a job offer
82939: 05/04/19: Re: Declining a job offer
83511: 05/05/01: Re: Decoupling V2P
84370: 05/05/17: Re: Bullshit Achieves Literary Status
84907: 05/05/31: need a book: Hilbert transform
84913: 05/05/31: Re: need a book: Hilbert transform
84937: 05/06/01: Re: need a book: Hilbert transform
84938: 05/06/01: Re: need a book: Hilbert transform
84939: 05/06/01: Re: need a book: Hilbert transform
85009: 05/06/02: Re: need a book: Hilbert transform
85012: 05/06/02: Re: need a book: Hilbert transform
85550: 05/06/10: Re: computer upgrade time.
85552: 05/06/10: Re: pcb layers on BGAs Spartan-3
85553: 05/06/10: Re: pcb layers on BGAs Spartan-3
85569: 05/06/10: Re: pcb layers on BGAs Spartan-3
85605: 05/06/11: Re: Best Practices for Hardware Designers
85682: 05/06/13: Re: pcb layers on BGAs Spartan-3
85756: 05/06/15: Re: pcb layers on BGAs Spartan-3
85757: 05/06/15: Re: Best Practices for Hardware Designers
85906: 05/06/17: Re: pcb layers on BGAs Spartan-3
87359: 05/07/21: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87478: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87509: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87664: 05/07/27: Re: Delay Generators in FPGAs
87896: 05/08/03: Re: System Engineering in the R/D World
87907: 05/08/03: Re: System Engineering in the R/D World
88029: 05/08/06: Re: System Engineering in the R/D World
88039: 05/08/07: Re: System Engineering in the R/D World
88300: 05/08/14: Re: Spartan-3 configuration -- peculiar problem
88341: 05/08/15: Re: Spartan-3 configuration -- peculiar problem
88346: 05/08/15: Re: Spartan-3 configuration -- peculiar problem
88384: 05/08/16: Re: Spartan-3 configuration -- peculiar problem
88386: 05/08/16: Re: Spartan-3 configuration -- peculiar problem
88420: 05/08/17: Re: Spartan-3 configuration -- peculiar problem
88421: 05/08/17: Re: Spartan-3 configuration -- peculiar problem
88473: 05/08/18: Re: Spartan-3 configuration -- peculiar problem
88868: 05/08/30: Re: Array of slope A/Ds in FPGA?
88971: 05/09/01: current!
88985: 05/09/01: Re: current!
90476: 05/10/13: Re: How many decoupling capacitors need on one device?
90527: 05/10/15: Re: 3.3v<->5V
90529: 05/10/15: Re: 3.3v<->5V
93939: 06/01/03: Xilinx upgrade issues
93944: 06/01/03: Re: Xilinx upgrade issues
93949: 06/01/03: Re: Xilinx upgrade issues
93988: 06/01/04: Re: Xilinx upgrade issues
94132: 06/01/05: Re: Schematic Entry, Xilinx or Altera?
94184: 06/01/06: Re: Schematic Entry, Xilinx or Altera?
94513: 06/01/12: Re: Schematic Entry, Xilinx or Altera?
94211: 06/01/07: Re: Schematic Entry, Xilinx or Altera?
94331: 06/01/09: Re: spartan3 differential I/O
94553: 06/01/13: Re: FPGA Journal Article
94570: 06/01/13: Re: FPGA Journal Article
95425: 06/01/23: Re: ISE BaseX customers
96283: 06/02/01: Spartan3 pullups
96326: 06/02/01: Re: Spartan3 pullups
94974: 06/01/19: Re: OT:Shooting Ourselves in the Foot
95023: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95027: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95039: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95041: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95062: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95064: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95084: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95085: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95129: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95221: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95289: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95334: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95336: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95339: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95419: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95541: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95549: 06/01/23: Re: OT:Shooting Ourselves in the Foot
97571: 06/02/23: Re: Input stage for VHF frequency counter in an FPGA?
99633: 06/03/27: deglitching a clock
99640: 06/03/27: Re: deglitching a clock
99643: 06/03/27: Re: deglitching a clock
99652: 06/03/27: Re: deglitching a clock
99657: 06/03/27: Re: deglitching a clock
99658: 06/03/27: Re: deglitching a clock
99670: 06/03/27: Re: deglitching a clock
99699: 06/03/28: Re: deglitching a clock
99716: 06/03/28: Re: deglitching a clock
99717: 06/03/28: Re: deglitching a clock
99725: 06/03/28: Re: deglitching a clock
99727: 06/03/28: Re: deglitching a clock
99738: 06/03/28: Re: deglitching a clock
99795: 06/03/29: Re: deglitching a clock
99832: 06/03/29: Re: deglitching a clock
99833: 06/03/29: Re: deglitching a clock
99834: 06/03/29: Re: deglitching a clock
99865: 06/03/30: Re: deglitching a clock
99892: 06/03/30: Re: deglitching a clock
99893: 06/03/30: Re: deglitching a clock
99920: 06/03/30: Re: Xilinx Schematic Entry
99921: 06/03/30: Re: Xilinx Schematic Entry
99952: 06/03/31: Re: deglitching a clock
99966: 06/03/31: Re: deglitching a clock
99968: 06/03/31: Re: Xilinx Schematic Entry
99989: 06/03/31: Re: deglitching a clock
100021: 06/04/01: Re: deglitching a clock
100025: 06/04/01: Re: deglitching a clock
100027: 06/04/01: Re: deglitching a clock
100028: 06/04/01: Re: PCB Bypass Caps
100029: 06/04/01: Re: Xilinx Schematic Entry
100053: 06/04/02: Re: deglitching a clock
100055: 06/04/02: Re: deglitching a clock
100056: 06/04/02: Re: PCB Bypass Caps
100122: 06/04/03: Re: PCB Bypass Caps
100147: 06/04/04: Re: PCB Bypass Caps
100148: 06/04/04: Re: PCB Bypass Caps
100158: 06/04/04: Re: PCB Bypass Caps
100239: 06/04/05: Re: Xilinx Schematic Entry
100265: 06/04/05: Re: Xilinx Schematic Entry
100301: 06/04/06: Re: Xilinx Schematic Entry
100635: 06/04/13: humble suggestion for Xilinx
100644: 06/04/14: Re: humble suggestion for Xilinx
100645: 06/04/14: Re: humble suggestion for Xilinx
100659: 06/04/14: Re: humble suggestion for Xilinx
100663: 06/04/14: Re: humble suggestion for Xilinx
100673: 06/04/15: Re: humble suggestion for Xilinx
101376: 06/04/29: Re: Pull up resistors on Spartan 3 mode pins
101423: 06/04/30: Re: Pull up resistors on Spartan 3 mode pins
101424: 06/04/30: Re: Spartan 3 documentation confusing...
101618: 06/05/03: Re: Measuring Light with LED and FPGA
101957: 06/05/08: Re: Putting the Ring into Ring oscillators
103084: 06/05/25: Re: FPGA delay generator
104606: 06/06/30: Re: Carry-chain based tapped delay line in Spartan3 - resolution? PVT variability?
104707: 06/07/04: Re: Chaos in FF metastability
107762: 06/08/31: Re: placing addiional caps across existing caps to reduce noise
107764: 06/08/31: Re: placing addiional caps across existing caps to reduce noise
107805: 06/09/01: Re: placing addiional caps across existing caps to reduce noise
107811: 06/09/01: Re: placing addiional caps across existing caps to reduce noise
108061: 06/09/04: Re: Please help me with (insert task here)
108669: 06/09/14: Spartan3 driving mosfets
108670: 06/09/14: Re: XIlinx Spartan 2E stuck in configuration mode
108677: 06/09/14: Re: Spartan3 driving mosfets
108678: 06/09/14: Re: Spartan3 driving mosfets
108747: 06/09/15: Re: Spartan3 driving mosfets
108748: 06/09/15: Re: XIlinx Spartan 2E stuck in configuration mode
108785: 06/09/16: Re: XIlinx Spartan 2E stuck in configuration mode
108797: 06/09/16: Re: XIlinx Spartan 2E stuck in configuration mode
108818: 06/09/17: Re: XIlinx Spartan 2E stuck in configuration mode
108824: 06/09/17: Re: XIlinx Spartan 2E stuck in configuration mode
108987: 06/09/19: Re: Hilbert Transform in verilog or VHDL -- it has got to be out there somewhere
109387: 06/09/25: Re: Hilbert Transform in verilog or VHDL -- it has got to be out there somewhere
109431: 06/09/26: Re: Hilbert Transform in verilog or VHDL -- it has got to be out there somewhere
112255: 06/11/18: Re: board - T562.jpg
112264: 06/11/18: Re: board - T562.jpg
112268: 06/11/18: Re: board - T562.jpg
112293: 06/11/19: Re: board - T562.jpg
112297: 06/11/19: Re: board - T562.jpg
112300: 06/11/19: Re: board - T562.jpg
112329: 06/11/20: Re: board - T562.jpg
112421: 06/11/21: Re: board - T562.jpg
112425: 06/11/21: Re: board - T562.jpg
112429: 06/11/21: Re: board - T562.jpg
112455: 06/11/22: Re: board - T562.jpg
112620: 06/11/26: Re: board - T562.jpg
112629: 06/11/26: Re: board - T562.jpg
112632: 06/11/26: Re: board - T562.jpg
112641: 06/11/26: Re: board - T562.jpg
113455: 06/12/13: Re: approximation of an exponential ramp?
113543: 06/12/15: Re: electrical level conversion
113829: 06/12/23: Re: solder mask for fpga dissipation
114379: 07/01/13: Re: xc3sprog
114380: 07/01/13: Re: Will FPGAs suit my need?
115485: 07/02/12: Re: Building Coaxial transmission line on PCB?
115542: 07/02/13: Re: Building Coaxial transmission line on PCB?
115544: 07/02/13: Re: Building Coaxial transmission line on PCB?
115577: 07/02/13: Re: audio low pass filtering in FPGA
115593: 07/02/14: Re: Building Coaxial transmission line on PCB?
115625: 07/02/15: Re: Loss Diagram
115628: 07/02/15: Re: Building Coaxial transmission line on PCB?
115667: 07/02/16: Re: Loss Diagram
115670: 07/02/16: Re: Building Coaxial transmission line on PCB?
115671: 07/02/16: Re: Building Coaxial transmission line on PCB?
115674: 07/02/16: Re: Loss Diagram
115679: 07/02/16: Re: Building Coaxial transmission line on PCB?
115681: 07/02/16: Re: Building Coaxial transmission line on PCB?
115720: 07/02/17: Re: Building Coaxial transmission line on PCB?
115724: 07/02/17: Re: Loss Diagram
115726: 07/02/17: Re: Building Coaxial transmission line on PCB?
118654: 07/05/01: Re: debounce state diagram FSM
118658: 07/05/01: Re: debounce state diagram FSM
118659: 07/05/01: Re: debounce state diagram FSM
118731: 07/05/02: Re: debounce state diagram FSM
118741: 07/05/02: Re: debounce state diagram FSM - topical
118781: 07/05/03: Re: debounce state diagram FSM - topical
119105: 07/05/11: Re: power consumption of integrated circuit in 0.13µm CMOS technology
119609: 07/05/23: clarification: clock doubling in Spartan 3
119610: 07/05/23: Re: clarification: clock doubling in Spartan 3
119615: 07/05/23: Re: clarification: clock doubling in Spartan 3
119695: 07/05/24: Re: LVDS termination scheme to nonstandard ribbon cable
119696: 07/05/24: Re: LVDS termination scheme to nonstandard ribbon cable
119711: 07/05/24: Re: LVDS termination scheme to nonstandard ribbon cable
119793: 07/05/25: Re: LVDS termination scheme to nonstandard ribbon cable
119811: 07/05/26: Re: Spartan3 LVCMOS33 Slew rate
119828: 07/05/26: Re: Spartan3 LVCMOS33 Slew rate
119842: 07/05/27: Re: Spartan3 LVCMOS33 Slew rate
119845: 07/05/27: Re: Spartan3 LVCMOS33 Slew rate
119915: 07/05/29: Re: Spartan3 LVCMOS33 Slew rate
121281: 07/06/29: Re: Analogue like signal interaction within cpld possible ????
121289: 07/06/30: Re: Bidirectional LVDS
121810: 07/07/13: Re: Designing the right clock tree for a multi-FPGA setup
121899: 07/07/14: Re: ESR Meter - design contest
121904: 07/07/14: Re: ESR Meter - design contest
121906: 07/07/14: Re: ESR Meter - design contest
121926: 07/07/15: Re: ESR Meter - design contest
122076: 07/07/18: Re: ESR Meter - design contest
122079: 07/07/18: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122115: 07/07/19: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122127: 07/07/19: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
123235: 07/08/20: Re: Voltage translation question
123296: 07/08/22: Re: Voltage translation question
123299: 07/08/22: Re: Power Reduction Strategy
123320: 07/08/23: Re: Voltage translation question
123328: 07/08/23: Re: Voltage translation question
123456: 07/08/28: Re: PCB Layers
123682: 07/09/01: Re: PCB Impedance Control
123704: 07/09/02: Re: PCB Impedance Control
123705: 07/09/02: Re: PCB Impedance Control
123714: 07/09/02: Re: V5 Configuration via SPI
123765: 07/09/04: Re: PCB Impedance Control
123766: 07/09/04: Re: PCB Impedance Control
123789: 07/09/04: Re: PCB Impedance Control
123798: 07/09/04: Re: Multiple CPLDs on a PCB.
123801: 07/09/04: Re: PCB Impedance Control
123812: 07/09/05: Re: PCB Impedance Control
123832: 07/09/05: Re: PCB Impedance Control
123842: 07/09/05: Re: PCB Impedance Control
123843: 07/09/05: Re: PCB Impedance Control
123883: 07/09/06: Re: PCB Impedance Control
123890: 07/09/06: Re: PCB Impedance Control
123957: 07/09/07: Re: VCCAUX too high on a Spartan 3 design
124226: 07/09/14: Re: Spartan-3E Slave Serial Configuration
125666: 07/10/31: Re: Ping Jim: The PFD is dead!
125674: 07/10/31: Re: Ping Jim: The PFD is dead!
125680: 07/10/31: Re: Ping Jim: The PFD is dead!
125809: 07/11/05: not totally repulsive
125828: 07/11/06: Re: not totally repulsive
125831: 07/11/06: Re: not totally repulsive
125836: 07/11/06: Re: not totally repulsive
125845: 07/11/06: Re: not totally repulsive
125853: 07/11/06: Re: not totally repulsive
125854: 07/11/06: Re: not totally repulsive
125912: 07/11/08: Re: not totally repulsive
125927: 07/11/08: Re: not totally repulsive
125942: 07/11/09: Re: not totally repulsive
126649: 07/11/28: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126676: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126711: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126742: 07/11/30: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126743: 07/11/30: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
127036: 07/12/09: Re: DDS generator with interpolated samples for Spartan3E development board
127041: 07/12/10: Re: DDS generator with interpolated samples for Spartan3E development board
127068: 07/12/10: Re: DDS generator with interpolated samples for Spartan3E development board
127102: 07/12/11: Re: DDS generator with interpolated samples for Spartan3E development board
127136: 07/12/12: Re: DDS generator with interpolated samples for Spartan3E development board
127164: 07/12/12: Re: spartan 3e VQ100 serious question
127229: 07/12/14: Re: spartan 3e VQ100 serious question
127230: 07/12/14: Re: spartan 3e VQ100 serious question
127244: 07/12/15: Re: Using LVDS_25 with 3.3V Vcco.
127255: 07/12/15: Re: Using LVDS_25 with 3.3V Vcco.
127384: 07/12/19: Re: Routing Vccint on four-layer PCB
127387: 07/12/19: Re: Routing Vccint on four-layer PCB
127529: 08/01/01: Re: Where are the LCD or OLED bitmapped displays?
127532: 08/01/01: Re: Split Plane
127540: 08/01/01: Re: Split Plane
127542: 08/01/01: Re: Where are the LCD or OLED bitmapped displays?
127559: 08/01/02: Re: Split Plane
127569: 08/01/02: Re: Where are the LCD or OLED bitmapped displays?
127570: 08/01/02: Re: Where are the LCD or OLED bitmapped displays?
127573: 08/01/02: Re: Split Plane
127600: 08/01/03: Re: Split Plane
127655: 08/01/04: Re: Where are the LCD or OLED bitmapped displays?
127693: 08/01/05: Re: rbt to C array
128294: 08/01/20: Re: Source of accurate frequency
128358: 08/01/22: Re: FPGA decoupling calculation
128380: 08/01/23: Re: FPGA decoupling calculation
128381: 08/01/23: Re: Pwm Sine Generation
128392: 08/01/24: Re: FPGA decoupling calculation
128410: 08/01/24: Re: Virtex-4 driving a 5V CMOS
128475: 08/01/27: Re: FPGA decoupling calculation
128476: 08/01/27: Re: FPGA decoupling calculation
129522: 08/02/26: Re: Typical jitter of high frequency oscillators?
131294: 08/04/17: Re: Survey: FPGA PCB layout
131352: 08/04/20: Re: Survey: FPGA PCB layout
131356: 08/04/20: Re: Survey: FPGA PCB layout
131357: 08/04/20: Re: Survey: FPGA PCB layout
131376: 08/04/20: Re: Survey: FPGA PCB layout
131444: 08/04/21: Re: Survey: FPGA PCB layout
131445: 08/04/21: Re: Survey: FPGA PCB layout
131918: 08/05/07: Re: ANNC: FPGA Design Software Webcast
131929: 08/05/07: Re: ANNC: FPGA Design Software Webcast
131930: 08/05/07: Re: ANNC: FPGA Design Software Webcast
131935: 08/05/07: Re: ANNC: FPGA Design Software Webcast
131960: 08/05/08: Re: ANNC: FPGA Design Software Webcast
131972: 08/05/08: Re: ANNC: FPGA Design Software Webcast
133048: 08/06/16: Re: FPGA to solve the two most annoying problems on usenet - Suggestions Welcome
134676: 08/08/25: Re: need fast FPGA suggestions
134701: 08/08/26: Re: need fast FPGA suggestions
134721: 08/08/27: Re: need fast FPGA suggestions
134723: 08/08/27: Re: need fast FPGA suggestions
137573: 09/01/22: Re: Brushing up on theory: Butterworth LCR filter design?
137609: 09/01/23: Re: Brushing up on theory: Butterworth LCR filter design?
139333: 09/03/26: Re: added jitter on FPGAs
139336: 09/03/26: Re: added jitter on FPGAs
139339: 09/03/26: Re: added jitter on FPGAs
139414: 09/03/28: Re: added jitter on FPGAs
139417: 09/03/28: Re: added jitter on FPGAs
139418: 09/03/28: Re: added jitter on FPGAs
139434: 09/03/29: Re: added jitter on FPGAs
139441: 09/03/29: Re: added jitter on FPGAs
139447: 09/03/30: Re: added jitter on FPGAs
139456: 09/03/30: Re: added jitter on FPGAs
142004: 09/07/21: Spartan 3 and DDR2
142044: 09/07/22: Re: Laser marking / custom graphics on blank FPGA?
142104: 09/07/24: Re: Almost everything about Virtex-6 in one location
142111: 09/07/24: Re: Spartan 3 and DDR2
142141: 09/07/26: Re: Merrick1
142197: 09/07/28: cool chart
142200: 09/07/28: Re: cool chart
142202: 09/07/28: Re: cool chart
142209: 09/07/28: Re: cool chart
142250: 09/07/30: Re: cool chart
142594: 09/08/19: Re: Help with crystal oscillator (MG-7010SA replacement)?
142610: 09/08/20: Re: Help with crystal oscillator (MG-7010SA replacement)?
146415: 10/03/16: Re: Xilinx Spartan6 Virtex6 Rollout
146421: 10/03/17: Re: Xilinx Spartan6 Virtex6 Rollout
146434: 10/03/17: Re: Xilinx Spartan6 Virtex6 Rollout
146452: 10/03/18: Re: Xilinx only on Avnet now
146643: 10/03/24: Re: PROM for Spartan 6 FPGA
147375: 10/04/24: Re: voltage divider calcs
147798: 10/05/24: Re: Software bloat (Larkin was right)
147810: 10/05/25: Re: Software bloat (Larkin was right)
148091: 10/06/20: Re: Newer Model Instrumentation Amp
148099: 10/06/21: Re: Newer Model Instrumentation Amp
148108: 10/06/21: Re: Xilinx BULLSHITIX-8, when?
148137: 10/06/22: Re: Xilinx BULLSHITIX-8, when?
148168: 10/06/24: fooling the compiler
148175: 10/06/25: Re: fooling the compiler
148176: 10/06/25: Re: fooling the compiler
148178: 10/06/25: Re: fooling the compiler
148180: 10/06/25: Re: fooling the compiler
148192: 10/06/25: Re: fooling the compiler
148264: 10/07/02: Re: SPI Flash configuration and data access rate
148267: 10/07/03: Re: Xilinx BULLSHITIX-8, when?
148268: 10/07/03: Re: fooling the compiler
148333: 10/07/07: Re: Xilinx BULLSHITIX-8, when?
149613: 10/11/11: Re: cool BGA pattern
149630: 10/11/12: Re: cool BGA pattern
149640: 10/11/12: Re: cool BGA pattern
149649: 10/11/12: Re: cool BGA pattern
149654: 10/11/13: Re: cool BGA pattern
149661: 10/11/15: Re: cool BGA pattern
150448: 11/01/22: Xilinx news
150450: 11/01/22: Re: Xilinx news
150460: 11/01/23: Re: Xilinx news
150473: 11/01/24: Re: Xilinx news
150475: 11/01/24: Re: Xilinx news
150493: 11/01/24: Re: Xilinx news
150494: 11/01/24: Re: Xilinx news
150563: 11/01/26: Re: Xilinx news
150575: 11/01/26: Re: Xilinx news
150633: 11/01/30: Re: Discrete time PID control
151859: 11/05/25: PCI Express Cable
151863: 11/05/25: Re: PCI Express Cable
151865: 11/05/25: Re: Scoping a glitch
151869: 11/05/26: Re: PCI Express Cable
151872: 11/05/26: Re: PCI Express Cable
152465: 11/08/27: cheating Arria FPGA i/o count
152466: 11/08/27: Re: Bitstream compression
152471: 11/08/27: Re: cheating Arria FPGA i/o count
152480: 11/08/28: Re: cheating Arria FPGA i/o count
152481: 11/08/28: Re: cheating Arria FPGA i/o count
152482: 11/08/28: Re: cheating Arria FPGA i/o count
152483: 11/08/28: Re: cheating Arria FPGA i/o count
152486: 11/08/28: Re: cheating Arria FPGA i/o count
152751: 11/10/18: Altera FPGA weirdness
152756: 11/10/19: Re: Altera FPGA weirdness
152761: 11/10/19: Re: Altera FPGA weirdness
152764: 11/10/19: Re: Altera FPGA weirdness
152889: 11/10/30: Re: Altera FPGA weirdness
152925: 11/11/01: Re: Altera FPGA weirdness
153200: 12/01/06: Re: voltage drop on STRATIX FPGA supply planes
153201: 12/01/06: Re: voltage drop on STRATIX FPGA supply planes
153214: 12/01/08: Re: voltage drop on STRATIX FPGA supply planes
153458: 12/03/02: configuring an Altera Cyclone 3
153462: 12/03/02: Re: configuring an Altera Cyclone 3
153466: 12/03/03: Re: configuring an Altera Cyclone 3
153494: 12/03/12: Re: configuring an Altera Cyclone 3
154169: 12/08/25: Altera GX45 to GX95 upgrade
154403: 12/10/26: Altera delivery
154412: 12/10/27: Re: Altera delivery
154469: 12/11/07: pci express reference clock step down
154471: 12/11/07: Re: pci express reference clock step down
155003: 13/03/26: Re: Where to move for an embedded software engineer.
155766: 13/08/29: FPGA temperature measurement
155770: 13/08/29: Re: FPGA temperature measurement
155772: 13/08/29: Re: FPGA temperature measurement
155776: 13/08/29: Re: FPGA temperature measurement
156021: 13/11/10: Re: Zynq devices, boards and suppliers
156027: 13/11/11: Re: Zynq devices, boards and suppliers
156074: 13/11/22: microZed adventures
156082: 13/11/22: Re: microZed adventures
156085: 13/11/22: Re: microZed adventures
156086: 13/11/22: Re: microZed adventures
156095: 13/11/22: Re: microZed adventures
156102: 13/11/22: Re: microZed adventures
156106: 13/11/23: Re: microZed adventures
156204: 14/01/17: my first microZed board
156209: 14/01/17: Re: my first microZed board
156212: 14/01/17: Re: my first microZed board
156219: 14/01/17: Re: my first microZed board
156220: 14/01/17: Re: my first microZed board
156224: 14/01/18: Re: my first microZed board
156229: 14/01/19: Re: my first microZed board
156254: 14/01/24: Re: my first microZed board
156454: 14/04/08: on-chip bypass caps
156457: 14/04/08: Re: on-chip bypass caps
156458: 14/04/08: Re: on-chip bypass caps
156481: 14/04/09: Re: on-chip bypass caps
156496: 14/04/10: Re: on-chip bypass caps
157696: 15/02/04: another MicroZed project
157887: 15/05/11: ZYNQ temperature
157889: 15/05/11: Re: ZYNQ temperature
157890: 15/05/11: Re: ZYNQ temperature
157892: 15/05/11: Re: ZYNQ temperature
157921: 15/05/12: Re: ZYNQ temperature
157925: 15/05/13: Re: ZYNQ temperature
157928: 15/05/14: Re: ZYNQ temperature
157932: 15/05/14: Re: ZYNQ temperature
157936: 15/05/15: Re: ZYNQ temperature
157938: 15/05/15: Re: ZYNQ temperature
157968: 15/06/08: PCIe card with FPGA and DAC
159141: 16/08/24: PADS part for ZYNQ
159220: 16/09/04: eliminating a DDS
159222: 16/09/04: Re: eliminating a DDS
159241: 16/09/06: Re: eliminating a DDS
159246: 16/09/07: Re: eliminating a DDS
159248: 16/09/07: Re: eliminating a DDS
159250: 16/09/07: Re: eliminating a DDS
159373: 16/10/17: Re: Microsoft's FPGA Translates Wikipedia in less than a Tenth of a Second
159424: 16/11/03: cool science thing
159425: 16/11/03: Re: cool science thing
159738: 17/02/16: cmos delay vs temperature
159787: 17/03/03: temperature sense diodes in Xilinx 7 series
159788: 17/03/03: Re: temperature sense diodes in Xilinx 7 series
159794: 17/03/04: Re: temperature sense diodes in Xilinx 7 series
159800: 17/03/08: Re: temperature sense diodes in Xilinx 7 series
159813: 17/03/11: Re: Analog to digital converters
159838: 17/04/10: FPGA as heater
159840: 17/04/10: Re: FPGA as heater
159843: 17/04/10: Re: FPGA as heater
159847: 17/04/11: Re: FPGA as heater
159848: 17/04/11: Re: FPGA as heater
159851: 17/04/11: Re: FPGA as heater
159856: 17/04/11: Re: FPGA as heater
159857: 17/04/11: Re: fan speed controller
159859: 17/04/11: Re: FPGA as heater
159861: 17/04/11: Re: FPGA as heater
159865: 17/04/12: Re: FPGA as heater
159871: 17/04/12: Re: FPGA as heater
159877: 17/04/12: Re: FPGA as heater
159881: 17/04/13: Re: FPGA as heater
159885: 17/04/14: Re: fan speed controller
159889: 17/04/15: Re: fan speed controller
160242: 17/08/16: Microsemi FPGAs
160330: 17/12/13: FPGA one-shot
160332: 17/12/13: Re: FPGA one-shot
160343: 17/12/14: Re: FPGA one-shot
160346: 17/12/14: Re: FPGA one-shot
160364: 17/12/19: Re: FPGA one-shot
160531: 18/03/16: the FPGA one-shot
160535: 18/03/16: Re: the FPGA one-shot
160536: 18/03/16: Re: the FPGA one-shot
160538: 18/03/16: Re: the FPGA one-shot
160541: 18/03/16: Re: the FPGA one-shot
160548: 18/03/22: Re: the FPGA one-shot
161363: 19/06/12: bare-metal ZYNQ
161365: 19/06/12: Re: bare-metal ZYNQ
161369: 19/06/13: Re: bare-metal ZYNQ
161370: 19/06/13: Re: bare-metal ZYNQ
161489: 19/11/08: FPGA config sizes
John Lazzaro:
112: 94/08/16: Re: FPGA Hobbyist and their software/programmer/hardware
2196: 95/10/30: Re: Xilinx Configuration Memory Hacking
2349: 95/11/22: Re: Xilinx Configuration Memory Hacking
2420: 95/12/02: Re: NeoCAD and AT&T vs. Xilinx
2889: 96/02/24: Re: Floating Point and Reconfigurable Architectures
2935: 96/03/02: Re: Comp.Arch.FPGA
John Ledford:
45309: 02/07/18: Re: Design Techniques for Memory Mapped Registers.
John Lee:
44170: 02/06/13: About Programming CPLD using Xilinx Programming Cable IV
59771: 03/08/27: pricing, cyclone or spartan
John LeVieux:
77022: 04/12/20: Re: Using low-core-voltage devices in industrial applications
77026: 04/12/20: Re: RAM programming by JTAG (i need some serious help)
125948: 07/11/09: Re: FPGA Clock signal
129507: 08/02/26: Re: Xilinx DCM for frequency synthesis -- newbie question
137404: 09/01/14: Re: ttl compatible
John Linn:
49567: 02/11/15: Re: Microblaze
John Little:
5422: 97/02/15: Financial Aid
John Lockwood:
21711: 00/03/29: I/O characteristics of Xilinx 1804 PROM
John Lull:
2531: 95/12/28: Re: [q][Reverse Engineering Protection]
John Lundgren:
6360: 97/05/18: Re: Need Address/Phone/Fax List of Semiconductor Companies
John M:
51775: 03/01/21: Virtex II: noise on Vcco causing loss of DCM lock
51813: 03/01/22: Re: Virtex II: noise on Vcco causing loss of DCM lock
51845: 03/01/23: Re: Virtex II: noise on Vcco causing loss of DCM lock
72203: 04/08/11: Automated Macro Grid to RPM Grid?
74178: 04/10/05: Hash algorithm for hardware?
74251: 04/10/06: Re: Hash algorithm for hardware?
83441: 05/04/29: Re: Lvds input problem urgent
83478: 05/04/30: Re: Trace length from FPGA to USB PHY
83608: 05/05/03: Re: VHDL help with adding modules
83757: 05/05/06: Re: FPGA choice advice needed
83900: 05/05/09: Re: dcm's for increasing clock speed
83902: 05/05/09: Re: TRACE and Modelsim Timing Help
84152: 05/05/13: Re: V4 vs. Stratix-II...
84452: 05/05/19: Re: Virtex4 running at 360Mhz DDR
85451: 05/06/09: Synplify/Quartus used to support direct to Hardcopy?
89557: 05/09/19: Re: USB tranciever + controller in FPGA
John M. Moore:
8047: 97/11/11: Re: Heed converter
8634: 98/01/14: Re: serial conf. PROMS
John Maher:
4369: 96/10/21: VHDL Aware Editor
4617: 96/11/21: Re: VHDL code editor for Windows NT.
4676: 96/11/28: Free Evaluation VHDL Editor
4704: 96/12/03: Re: Free Evaluation VHDL Editor
7867: 97/10/25: VHDL or VERILOG Editior for Windows
8358: 97/12/10: VHDL/Verilog Editor for Windows, your change to choose features.
10694: 98/06/11: Are you looking for a good VHDL/Verilog Editor?
10712: 98/06/12: Re: Are you looking for a good VHDL/Verilog Editor?
10713: 98/06/12: Re: Are you looking for a good VHDL/Verilog Editor?
12689: 98/10/23: Re: Need VHDL tools for Win NT/ Win 95
14053: 99/01/10: Advanced VHDL Editor Available
78776: 05/02/07: MAP problem
John Mashey:
82158: 05/04/07: Re: ISA vs. patent/trademark
82161: 05/04/07: Re: ISA vs. patent/trademark
82174: 05/04/07: Re: ISA vs. patent/trademark
John Massoth:
36: 94/08/02: Re: Welcome new XILINX users
110: 94/08/16: Re: Actel Act3 Speeds (measured?)
John Matrix:
73166: 04/09/15: New VHDL (Xilinx) Website
John McBride:
78031: 05/01/23: Re: Master's Project
John McCaskill:
83640: 05/05/04: Re: embedded linux for v2pro PPC?
86262: 05/06/23: Re: Issues with Xilinx xapp635: Interface for TigerSharc Link Ports.
86308: 05/06/24: Re: Issues with Xilinx xapp635: Interface for TigerSharc Link Ports.
88542: 05/08/22: Re: XST Help - Device Utilization Woes
89311: 05/09/12: Re: Has anyone successfully used opencores PCI in FPGA desings?
92552: 05/12/01: Re: Xilinx 'unconstrained period' problem
92561: 05/12/01: Re: Supplier of Xilinx XC2V1000 or 2V250?
93539: 05/12/23: Re: Spartan3e and ChipScope
93541: 05/12/23: Re: Is there anybody that have ported the linux to the nios or microblaze?
94362: 06/01/10: Re: FPGA configuration time for PCI identification ?
94840: 06/01/18: Re: clock generation with DOPPLER shift
96488: 06/02/04: Re: multi-processor linux on xilinx
96781: 06/02/10: Re: EDK - PLB/OPB Bus questions.
98767: 06/03/16: Re: ADC Interleaving
99021: 06/03/18: Re: Can one use MGT clock input for global clock in Virtex4
99103: 06/03/20: Re: Looking for a V4FX development board
103609: 06/06/06: Re: EDK: TCL scripts in pcores directories
104304: 06/06/23: Re: is picoblaze worth in my project?
105118: 06/07/14: Re: PLB slaves
110797: 06/10/23: Re: PowerPC somehow unstable at 300 MHz
112104: 06/11/16: Re: In defence of Austin and Xilinx
113058: 06/12/05: Re: Usage of BUFIO in Virtex 4?
114191: 07/01/06: Re: Does Modelsim XE support coreconnect BFM simulation?
114192: 07/01/06: Re: Surface mount ic's
114424: 07/01/15: Re: Gigabit Ethernet UDP/IP
114733: 07/01/23: Re: Good hardware design code re-use strategies, reference book
115372: 07/02/08: Re: ISE 9.1 sp1 and EDK 8.2 sp2
115409: 07/02/09: Re: Need advice to help improve timing on V4 FX
115413: 07/02/09: Re: Need advice to help improve timing on V4 FX
115611: 07/02/14: Re: Xilinx Platform Studio adding Xilinx coreGen IP
116082: 07/03/01: Re: Regional Clock Network and Large Designs
116099: 07/03/01: Re: XPS (NGCBUILD) fails when creates netlist: "failed to copy to implementation"
116178: 07/03/03: Re: How to get the area/time results without IO mapping
116181: 07/03/03: Re: Instance Name Being Removed?
116405: 07/03/08: Re: Spartan3AN - Roadmap - bigger questions may prevail...
116442: 07/03/08: Re: Spartan3AN - Roadmap - bigger questions may prevail...
116461: 07/03/09: Re: Virtex 4 FX12 - where are the EMACs and PPC core located?
116526: 07/03/12: Re: EDK & custom board definitions
116532: 07/03/12: Re: Virtex 4 FX12 - where are the EMACs and PPC core located?
116557: 07/03/12: Re: Design report does not show BRAM usage
116644: 07/03/14: Re: Xilinx Netlist
116663: 07/03/14: Re: Xilinx Netlist
116781: 07/03/17: How to find pcore directory from within EDK TCL script?
117155: 07/03/24: Re: shift register with distributed ram
117158: 07/03/24: Re: shift register with distributed ram
117165: 07/03/25: Re: EDK and Custom Peripheral: error occur when generating bitstream
117369: 07/03/29: Re: EDK and Custom Peripheral: error occur when generating bitstream
117391: 07/03/29: Re: "undeclared here" error and undesired file persistance in Xilinx Platform Studio
117392: 07/03/29: Re: Complex Baseband
117441: 07/03/30: Re: ModelSim VHDL Pragmas
117551: 07/04/03: Re: Looking for Memory Recommendation for Spartan 3E 1200
117570: 07/04/04: Re: Can I boot PowerPC without JTAG?
117677: 07/04/06: Re: Transition from ASIC to FPGA
117793: 07/04/10: Re: is there any opensource alternatives to platformstudio and microblaze development?
117802: 07/04/10: =?iso-8859-1?q?Re:_CPLD_+_=B5C_with_reasonably-priced_tools=3F?=
118052: 07/04/16: Re: EDK and Custom Peripheral: error occur when generating bitstream
118073: 07/04/17: Re: EDK and Custom Peripheral: error occur when generating bitstream
118212: 07/04/19: Re: Question about reset signal for several DCMs in EDK design.
121311: 07/07/02: Re: 32bit multiplication in a PowerPC405 of a VirtexIIPro
121314: 07/07/02: Re: 32bit multiplication in a PowerPC405 of a VirtexIIPro
122148: 07/07/20: Re: Xilinx fpgas...
122737: 07/08/05: Re: Area report
122931: 07/08/10: Re: EDK speed issue
123823: 07/09/05: Re: high bandwitch ethernet communication
123879: 07/09/06: Re: high bandwitch ethernet communication
123887: 07/09/06: Re: load/read/ commands assembly PowerPC. Help Needed!
123895: 07/09/06: Re: high bandwitch ethernet communication
123898: 07/09/06: Re: Problem locking a DCM driven by FX output of another DCM
123900: 07/09/06: Re: Problem locking a DCM driven by FX output of another DCM
123904: 07/09/06: Re: Problem locking a DCM driven by FX output of another DCM
123908: 07/09/06: Re: Problem locking a DCM driven by FX output of another DCM
123949: 07/09/07: Re: Problem locking a DCM driven by FX output of another DCM
123951: 07/09/07: Re: load/read/ commands assembly PowerPC. Help Needed!
123952: 07/09/07: Re: high bandwitch ethernet communication
124336: 07/09/18: Re: Population Count circuit
124339: 07/09/18: Re: Peripheral Trouble!
124549: 07/09/26: Re: XST corrupts my state machine. Only disabling FSM encoding helps
124668: 07/09/29: Re: job inquiry; entry/trainee FPGA/ASIC designer
124857: 07/10/08: Re: JTAG interconnect testing, prototypes
124913: 07/10/10: Re: HELP, how to time constraint part of a design?
125234: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
125384: 07/10/24: Re: Addresses of subsystems
125388: 07/10/24: Re: Addresses of subsystems
125396: 07/10/24: Re: Addresses of subsystems
125625: 07/10/30: Re: FFT for an arbitrary number of points (not power of 2)
125725: 07/11/01: Re: fpga based designs
126015: 07/11/12: Re: EDK 8.2 tool : simulator set up
126400: 07/11/21: Re: Xilinx XST 8.2, Error on multi-source, bug?
126424: 07/11/21: Re: EDK + Modelsim simulation : Memory allocation failure
126677: 07/11/29: Re: lossless compression in hardware: what to do in case of
126683: 07/11/29: Re: EDK IPIF development workflow
126904: 07/12/05: Re: Mixed language design
126917: 07/12/05: Re: Mixed language design
127188: 07/12/13: Re: Newbee Microblaze system BRAM utlization confusion
127362: 07/12/19: Re: Xilinx EDK PPC405+FSL
127568: 08/01/02: Re: OpenCores tracker and forum doesn't work?
127701: 08/01/05: Re: Ethernet on recent FPGAs
127704: 08/01/05: Re: Ethernet on recent FPGAs
127715: 08/01/06: Re: Ethernet on recent FPGAs
127818: 08/01/08: Re: Warning 'clock has been changed'
127865: 08/01/09: Re: Real examples of metastability causing bugs
127880: 08/01/09: Re: How to program FPGA permanently?
127893: 08/01/09: Re: Creation of BUGMUX from non clock signals
127967: 08/01/11: Re: Cant capture data with Chipscope 7.1
127984: 08/01/11: Re: opb_emc_v1_10_b
128002: 08/01/12: Re: opb_emc_v1_10_b
128041: 08/01/14: Re: BRAM Readback
128096: 08/01/15: Re: Help! Micriblase + plbv46_pci in Virtex5
128185: 08/01/17: Re: CynApps Cynlib
128199: 08/01/17: Re: Two's complement Coregen gone?
128244: 08/01/18: Re: Source of accurate frequency
128252: 08/01/18: Re: Source of accurate frequency
128292: 08/01/20: Re: VHDL Micron memorymodel.
128470: 08/01/27: Re: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
128473: 08/01/27: Re: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
128497: 08/01/28: Re: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
128521: 08/01/29: Re: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
128690: 08/02/04: Re: OFFSET In and hold time
129937: 08/03/11: Re: Virtex-4 VLX25 DCM problem
130855: 08/04/03: Re: Protecting design from being downloaded on other (similar) FPGA
130870: 08/04/03: Re: counterfeit Xilinx ?
132030: 08/05/10: Re: Anyway to secure a Xilinx NGC file ?
132383: 08/05/24: Re: Software instabilities with EDK 10.01 and PPC405?!??!!!
133386: 08/06/26: Re: FPGA area use by module?
133556: 08/07/03: Re: Constraints for router
133906: 08/07/18: Re: Additional Hardware Module with Xilinx MicroBlaze Processor
133911: 08/07/18: Re: The littlest CPU
133912: 08/07/18: Re: The littlest CPU
134081: 08/07/24: Re: Quartus2 pin assignment
134325: 08/08/06: Re: Downsizing Verilog synthesization.
134335: 08/08/06: Re: Downsizing Verilog synthesization.
134344: 08/08/06: Re: Downsizing Verilog synthesization.
134350: 08/08/07: Re: how to change the system clk in EDK project
134375: 08/08/07: Re: how to change the system clk in EDK project
134395: 08/08/08: Re: Development board with SD card.
134575: 08/08/19: Re: Multicore OS
134693: 08/08/26: Re: need fast FPGA suggestions
135719: 08/10/13: Re: writing files to micro-SD with spartan 3e
136183: 08/11/04: Re: Learning programming an FPGAs
137262: 09/01/06: Re: NGC and RTL into the same FPGA device
138159: 09/02/08: Re: C-NIT source
140523: 09/05/15: Re: XILINX license model restricts longtime availability
142506: 09/08/13: Re: Mixed language simulation on the cheap
142979: 09/09/11: Re: How to get two PLB slave burst interfaces into custom core with
144222: 09/11/20: Re: Error:Place:645 on a non-clock pin.
144468: 09/12/09: Re: Multiport BRAM for custom CPUs
144630: 09/12/21: Re: Please help, Xilinx FIFO problem!
144662: 09/12/21: Re: Please help, Xilinx FIFO problem!
144681: 09/12/22: Re: Please help, Xilinx FIFO problem!
144683: 09/12/22: Re: Please help, Xilinx FIFO problem!
145069: 10/01/24: Re: How to connect two BNC connectors to FPGA board?
145091: 10/01/26: Re: timing properties of fpga devices at sub-clock frequencies
145458: 10/02/10: Re: Reading UDP with FPGA
145806: 10/02/24: Re: Xilinx iodelay
146331: 10/03/12: Re: Question Rdging xilinx chipscope pro triggering
147195: 10/04/17: Re: Which 32 bit cores support full Linux?
147196: 10/04/17: Re: Microblaze and DDR2
147657: 10/05/13: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
147663: 10/05/13: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
147668: 10/05/13: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
147729: 10/05/19: Re: Problems inferring blockram in ISE12.1
147745: 10/05/21: Re: Xilinx FIFO cannot be written
147930: 10/06/02: Re: Spartan-6 hold time problems (multipost to Xilinx forums)
148149: 10/06/23: Re: Spartan-3E starter kit USB schematics ? (again)
148189: 10/06/25: Re: how to know that SRL16 was infered on xilinx?
148323: 10/07/07: Re: SPF+ useable signalling range
148332: 10/07/07: Re: Controlling Path Delay with Constraints?
148348: 10/07/12: Re: manual Route before PAR starts in xilinx ISE 12
148616: 10/08/06: Re: Vendor Tool Stability
148643: 10/08/10: Re: Spartan3a: improving DCM performance and "To achieve optimal
148666: 10/08/16: Re: How to use VIO and core inserter at the same time.
148672: 10/08/17: Re: How to use VIO and core inserter at the same time.
148958: 10/09/15: Re: Preventing timing warnings
149000: 10/09/20: Re: Xilinx XST and a State Machine - A Mystery
149005: 10/09/20: Re: Xilinx XST and a State Machine - A Mystery
149016: 10/09/20: Re: Xilinx XST and a State Machine - A Mystery
149380: 10/10/20: Re: Happy birthday, Bernie!
149510: 10/11/01: Re: Timing error for EDK project using a DCM?
149636: 10/11/12: Re: cool BGA pattern
149705: 10/11/18: Re: test peripheral example in xilinx XPS
150335: 11/01/10: Re: FPGA to PHY/MAC chip
150338: 11/01/10: Re: FPGA to PHY/MAC chip
150378: 11/01/13: Re: FPGA to PHY/MAC chip
151333: 11/03/23: Re: Problems connecting with Xilinx Spartan-6 FPGA
151642: 11/04/29: Re: same RTL on two same boards giving different behaviour
151687: 11/05/05: Re: remove Xilinx webtalk
John McCluskey:
1618: 95/08/02: Re: HW VIDEO ALGORITHMS
1638: 95/08/09: Re: AT&T ORCA: Using register input mux?
1639: 95/08/09: Repost: VHDL Source for 5x5 Image convolver in ORCA FPGA
2234: 95/11/07: Re: X-Blox...The good, bad and ugly
8850: 98/02/01: Re: VHDL vs schematics, I vote for VHDL and this is why...
9141: 98/02/24: Re: Correlation implementation...
9450: 98/03/14: Re: Please share ur knowledge of Multipliers ( datapath elements)
11100: 98/07/18: Re: Floorplanning Intro: Here's how I floorplan in VHDL
11831: 98/09/11: Re: Design Security Question (another solution)
12509: 98/10/14: Gray Code counter in ORCA FPGA (4 methods) vp_gray.vhd
14653: 99/02/08: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
16688: 99/06/02: Re: Evolutionary computation
16903: 99/06/16: Re: Recursive Structures under Aldec AVHDL3.3
16917: 99/06/16: Re: Recursive Structures under Aldec AVHDL3.3
23712: 00/07/05: ORCA4 (was Re: Altera Ships Largest PLD)
25220: 00/08/30: Re: Large amount of Interconnect between FPGAs (Lucent FPSC solution
39316: 02/02/06: Re: Xilinx synthesis tools
76880: 04/12/15: Re: Linking FPGAs with RocketIOs
80173: 05/03/02: Re: Missing Virtex4 Speedfile
85831: 05/06/16: Automagic Circuit Pipelining (was: Re: Auto pipeline logic?? )
89533: 05/09/18: Re: ISE 7.1i & Linux / reg code question
89535: 05/09/18: Re: XilinX MAC FIR
90620: 05/10/17: Re: Storing a file onto FPGA (the last word)
90833: 05/10/22: Re: Storing a file onto FPGA (the last word)
91796: 05/11/13: Re: ISE 8.1 news--BaseX going away, but WebPack gains devices and features
John McDougall:
4450: 96/10/30: Anyone experience Altera 10k
4449: 96/10/30: Re: Altera Configuration EPROM Equivalents
6574: 97/06/03: Re: Fine Pitch PQFP : anyone any hassles?
6691: 97/06/15: Re: Don't Design With Altera Parts... Altera Obsolete Parts
7326: 97/08/27: Re: .vho file creation in MaxplusII
7812: 97/10/17: Re: Xilinx delay reports?
7863: 97/10/24: Re: Xilinx 4000 on an ISA bus...
8463: 97/12/17: Re: bus design in Altera 10K, how to increase speed -- Check out Xilinx
9143: 98/02/24: Re: buft and bufe
John McGibbon:
5345: 97/02/09: Re: Serial Communication Controller Design
6533: 97/05/31: Re: In circuit programming of flash with Xilinx devices??
7868: 97/10/25: Re: Anyone know of an I2C Controller design for an FPGA?
7873: 97/10/26: Re: Xilinx Adder Trees in Viewlogic
8768: 98/01/25: Re: UART Spec
JOHN MCGIBBON:
7454: 97/09/12: Re: Text Book and VHDL Simulator $50.00
John McGrath:
78097: 05/01/24: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
84425: 05/05/18: Re: Which Simulators
84869: 05/05/31: Re: Problems with SDRAM and Altera Cyclone
86054: 05/06/21: Re: Microblaze address space and variables
86481: 05/06/28: Re: Two Verilog FSM style compare
97703: 06/02/26: Re: ERROR:MapLib:482
99248: 06/03/21: Re: OpenSPARC released
99429: 06/03/24: Re: Xilinx hi-speed interconnect/routing question
102240: 06/05/12: Re: Xilinx 3s8000?
103223: 06/05/29: Re: ISE 8.1 with 7.1
106951: 06/08/22: Re: Newbie frustration
106986: 06/08/23: Re: Newbie frustration
109170: 06/09/21: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109253: 06/09/22: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109359: 06/09/25: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
112081: 06/11/15: Re: how to filter glitches and mutliple transitions?
112140: 06/11/16: Re: how to filter glitches and mutliple transitions?
116354: 07/03/07: Re: Spartan3AN - Roadmap
116798: 07/03/18: Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*
116821: 07/03/19: Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*
116823: 07/03/19: Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*
117235: 07/03/26: Re: Open-source CPU-core for standard-cell ASIC?
118036: 07/04/16: Re: par [placer] consistency
123273: 07/08/22: Re: ML401 (Virtex 4 development board) as a USB peripheral
123281: 07/08/22: Re: ML401 (Virtex 4 development board) as a USB peripheral
123290: 07/08/22: Re: ML401 (Virtex 4 development board) as a USB peripheral
123292: 07/08/22: Re: ML401 (Virtex 4 development board) as a USB peripheral
133362: 08/06/25: Re: FPGA area use by module?
151763: 11/05/15: Re: Best syntheses
John McLean:
68285: 04/03/31: Re: Spartan3 hot-swap configuration issue
John McMiller:
50972: 02/12/24: HSTL standards
50995: 02/12/25: Re: HSTL standards
60247: 03/09/09: frequency constraint changes routability
John Milbanks:
54594: 03/04/14: Re: error correcting codes
54668: 03/04/15: Re: error correcting codes
54670: 03/04/15: Re: Search for most relevant FPGA sites on the net
54765: 03/04/17: Re: Boycott All Xilinx products untill they correct all ISE software errors
54817: 03/04/18: Reason Xess discontinued XSV prototyping boards?
John Miles:
86710: 05/07/04: Re: Low cost altera board
149210: 10/10/07: Re: help with bad synchronous description error
149843: 10/11/26: Re: Pack:2309 - Too many bonded comps of type
149913: 10/12/01: Re: What should I use for highspeed/low latency communication beteen
150768: 11/02/09: Re: Good FPGA dev kit for a student who is not a complete newbie?
150798: 11/02/11: Re: Good FPGA dev kit for a student who is not a complete newbie?
152015: 11/06/21: Re: Xilinx or Altera
152491: 11/08/28: Re: Very cheap Spartan3 board that can be configured by simple USB
152497: 11/08/29: Re: Very cheap Spartan3 board that can be configured by simple USB
153264: 12/01/20: Re: Xilinx virtex-5 pitfalls
155863: 13/10/05: Re: Video Framebuffer using Nexys2 (Spartan-3E)
156233: 14/01/19: Re: Math is hard
156598: 14/05/07: Re: The USB FPGA?
158095: 15/08/05: Re: Finally! A Completely Open Complete FPGA Toolchain
158097: 15/08/05: Re: Finally! A Completely Open Complete FPGA Toolchain
John Monro:
91125: 05/10/30: Re: Sigma-Delta A/D
91142: 05/10/31: Re: Sigma-Delta A/D
91189: 05/11/01: Re: Sigma-Delta A/D
91230: 05/11/02: Re: Sigma-Delta A/D
99023: 06/03/19: Re: Urgent Help Needed!!!!!
John Moore:
34786: 01/09/07: Re: ISE 4.1
36352: 01/11/07: Re: Fifo books
John Morris:
34288: 01/08/18: Asia-Pacific Computer Systems Architecture Conference - CFP
John Murray:
2818: 96/02/12: Re: Xilinx FPGA's with Mentor Tools?
John Nangreaves:
11144: 98/07/21: Wanted: CPLD Primer
John Newton:
23727: 00/07/06: Re: which pci board?
John Noll:
593: 95/01/13: Re: ViewLogic simulation without master reset
2000: 95/09/29: Re: FFT in FPGAs ?
John O'Flaherty:
118536: 07/04/29: Re: debounce state diagram FSM
john oatis:
6848: 97/07/02: Free 5 Page Commercial Web Site
John Obenauf:
1650: 95/08/10: Xilinx PROMs
john ong:
68624: 04/04/10: problems iwth I/O pins
68838: 04/04/20: Configurating multiple devices(FPGA and CPLD) with different Vccs through the JTAG
john orlando:
63067: 03/11/13: Xilinx UART Macro ERROR???
63250: 03/11/18: Re: Xilinx UART Macro ERROR???
John Oyler:
122143: 07/07/20: Xilinx fpgas...
122147: 07/07/20: Re: Xilinx fpgas...
122325: 07/07/25: Anyone know any good vhdl ethernet tutorials?
122373: 07/07/26: Re: Anyone know any good vhdl ethernet tutorials?
john p:
160401: 18/01/12: Re: HDL simple survey - what do you actually use
160418: 18/01/17: Re: HDL simple survey - what do you actually use
John Patrick:
66238: 04/02/15: Xilinx DB-01 info?
66245: 04/02/16: Re: Xilinx DB-01 info?
john paul:
55655: 03/05/14: multiplexing resources in xilinx fpga
John Payson:
2359: 95/11/22: Re: Industry Trends
John Penton:
51943: 03/01/27: Re: AMBA AHB compliant core
93288: 05/12/19: Re: Inverter Chain Synthesis Problem
John Perry:
3694: 96/07/17: Cheap/free fpga/cpld programming software
3736: 96/07/23: Cheap/free fpga/cpld software
John Pham:
57967: 03/07/10: Xilinx FPGA module
58149: 03/07/16: Re: Xilinx FPGA module
58155: 03/07/16: Re: Looking for DIMM format FPGA board
John Phillips:
1180: 95/05/11: Re: How to choose an FPGA vendor
1553: 95/07/13: Re: Flex 8000: Locking down pins
58029: 03/07/12: Actel ProAsic+ APA -> User's Clock speed??
John Plows:
66372: 04/02/18: FFT on Virtex-II (Desperation Imminent)
John Popelish:
108047: 06/09/04: Re: Please help me with (insert task here)
118535: 07/04/29: Re: debounce state diagram FSM
118537: 07/04/29: Re: debounce state diagram FSM
118548: 07/04/29: Re: debounce state diagram FSM
118552: 07/04/29: Re: debounce state diagram FSM
118553: 07/04/29: Re: debounce state diagram FSM
118600: 07/04/30: Re: debounce state diagram FSM
118604: 07/04/30: Re: debounce state diagram FSM
118652: 07/05/01: Re: debounce state diagram FSM
John Providenza:
51821: 03/01/22: Xilinx Spartan2 with more than 4 clocks
51848: 03/01/23: Re: Xilinx Spartan2 with more than 4 clocks
52100: 03/01/31: Re: More than four clocks within a spartan-ii device?
52749: 03/02/20: Re: WebPack 4.2i and Block RAM instantiation
52753: 03/02/20: Re: Verilog failed,please help
60311: 03/09/10: Re: Xilinx clk to out variation
60328: 03/09/10: What clock domain is a Xilinx DCM LOCK signal in?
60385: 03/09/11: Re: What clock domain is a Xilinx DCM LOCK signal in?
60577: 03/09/16: Re: USB transceiver for FPGA
60629: 03/09/17: Re: Webpack Vs. ISE
61288: 03/10/01: Looking for recent Altera Quartus Verilog synthesis experience
61622: 03/10/07: Xilinx DCMs, DDR, CLK0, and CLK180
61661: 03/10/08: Re: Problem with PCI cards
61671: 03/10/08: syncing the CLK0 outputs of two DCMs if they use CLKIN_DIVIDE_BY_2
61716: 03/10/09: Re: syncing the CLK0 outputs of two DCMs if they use CLKIN_DIVIDE_BY_2
61936: 03/10/15: Re: DCM driving multiple OBUF's ... skew in between ...
61941: 03/10/15: Xilinx XAPP265 and 800Mb/sec data input....
63809: 03/12/04: Xilinx DDR output with tri-state....
63842: 03/12/05: Re: Xilinx DDR output with tri-state....
65251: 04/01/22: Xilinx LVDS_25_DT termination issues????
65302: 04/01/23: Re: Xilinx LVDS_25_DT termination issues????
66810: 04/02/26: V2Pro config problems with HSTL_II_DCI pads...
68982: 04/04/23: Xilinx XST problems packing signals into IOB registers...
68991: 04/04/23: Re: Xilinx XST problems packing signals into IOB registers...
69298: 04/05/05: XST, Virtex2-Pro, odd PAR counter timing failure
69326: 04/05/06: Re: XST, Virtex2-Pro, odd PAR counter timing failure
69498: 04/05/12: Re: Easypath question (was "Hard-tocopy" rant)
70121: 04/06/03: Virtex-II Pro slave serial configuration problem....
70213: 04/06/09: Re: Virtex-II Pro slave serial configuration problem....
70354: 04/06/14: Re: Virtex-II Pro slave serial configuration problem....
71463: 04/07/19: Using Verilog to embed the synthesis date and time
71550: 04/07/21: Re: Using Verilog to embed the synthesis date and time
72529: 04/08/23: Re: Virtex II LVDS plus DDR?
72580: 04/08/25: Re: Xilinx version ROM with automatic increment
John R Fulton:
264: 94/10/08: Xilinx FPGA Pics: LCA, CLB etc.?
John Ragnvald Walliker:
1282: 95/05/26: Re: FLEXlogic opinions?
1506: 95/07/05: Re: Who makes low-power 22v10-type PLDs?
9007: 98/02/13: Philips P5Z22V10 wanted
John Renvar:
21340: 00/03/17: Re: Is there a cheaper alternative to ByteblasterMV?
John Retta:
49755: 02/11/20: Spartan IIe - DLL Max Input Clock Frequency
50291: 02/12/07: Re: memory in VHDL
51499: 03/01/14: Re: How to run XST from command line?
57552: 03/07/02: Xilinx Methodology Questions : Unconstrained Paths and DLL output phase alignment.
60199: 03/09/08: Re: switching problem
61935: 03/10/15: Hot Swap Considerations
64107: 03/12/16: Re: advantages of ethernet MAC ip core
64112: 03/12/17: Re: advantages of ethernet MAC ip core
64234: 03/12/22: Re: How to use differential clock pin of SpartanIIE?
64235: 03/12/22: Re: Spartan II Block Ram
64252: 03/12/22: Re: Spartan II Block Ram
64259: 03/12/22: Re: Spartan II Block Ram
64262: 03/12/23: Re: Spartan II Block Ram
64645: 04/01/10: Re: FPGA Size
64900: 04/01/16: Re: mapper optimization
65240: 04/01/22: Re: Why is router software not multi-threaded?
65607: 04/02/03: Re: Is it possible that a Virtex II device performs below its spec?
66467: 04/02/20: Re: Is there an easy way to get a list of unused pin in ML300?
68326: 04/04/01: Re: The mapper is getting rid of all my logic!!
68327: 04/04/01: Re: FPGA Engineer w/clearance - where do you look for a job?
69160: 04/04/28: Re: Xilinx Block RAM Init
70105: 04/06/03: Re: How can I get an output clock phased align with the input clock.
70173: 04/06/08: Re: comp.arch.fpga: reset strategy
70558: 04/06/21: Re: 8 ch countdown timer - doable in a CPLD?
72552: 04/08/24: Re: SSO and decoupling relationship
75677: 04/11/12: Re: asynchronous bus transfers
81408: 05/03/23: Re: Xilinx ISE 7.1 - Can this get any worse?
81570: 05/03/28: Re: Block RAM in Xilinx Spartan 3
81845: 05/04/02: Re: RAM Synthesized away
82857: 05/04/19: Re: source control and Xilinx ISE 6 and 7
88648: 05/08/24: Re: Xilinx place and route cost table
92671: 05/12/04: Re: how to build 32X32 LUT ROM
102014: 06/05/09: Re: Xilinx ISE 8.1 Makefile
109314: 06/09/23: Re: Help with webpack/ISE 8.2
113928: 06/12/29: Re: ChipScope - impact on design or not?
120224: 07/06/04: Re: Xilinx CIC core in Spartan 3?
120358: 07/06/06: Re: Virtex4 CLKX2 DCM Jitter
121577: 07/07/09: Re: fifo counter in virtex-4
122473: 07/07/28: Re: Question about GSR?
122727: 07/08/05: Re: Confused about my behavioral simulation under ISE 9.1
122868: 07/08/09: Re: Specifying LVDS I/O's in Xilinx FPGA's
122944: 07/08/11: Re: How to locate the internal state machine in timing simulation
122946: 07/08/11: Re: How to locate the internal state machine in timing simulation
123000: 07/08/14: Re: Design Behavior affected by use of Chipscope
123191: 07/08/19: Re: Xilinx / ISE multi-cycle path constraint pitfall
123197: 07/08/19: Re: Xilinx / ISE multi-cycle path constraint pitfall
123371: 07/08/25: Re: Xilinx / ISE multi-cycle path constraint pitfall
123459: 07/08/28: Re: Xilinx Virtex IOB Regiters and Noise???
124416: 07/09/20: Re: hardware software codesign
124461: 07/09/22: Re: Does Modelsim work under Windows Vista?
124462: 07/09/22: Re: Answer: maximum number of state machines in a current chip: > 500k
125532: 07/10/27: Re: Selecting I/O pins
125554: 07/10/28: Re: Xilinx xflow for the ISE Quickstart Tutorial project?
125568: 07/10/29: Re: Xilinx xflow for the ISE Quickstart Tutorial project?
125937: 07/11/09: Re: FIFO interface design
125966: 07/11/10: Re: FIFO interface design
126236: 07/11/17: Re: simulating xilinx block ram with modelsim
126816: 07/12/03: Re: Xilinx ISE Bugs
128614: 08/01/31: Re: I need a SDRAM controller
128670: 08/02/02: Re: Internal signal names in ModelSim
128743: 08/02/05: Re: How to optimize my design area to fit?
128792: 08/02/06: Re: Simple Memory Read problem, help appreciated
128801: 08/02/06: Re: Single Top FPGA Tips
128838: 08/02/07: Re: Single Top FPGA Tips
John Rible:
5138: 97/01/26: Re: FPGA Lab.
10406: 98/05/16: Re: Minimal ALU instruction set.
20693: 00/02/17: Re: Suggested prototyping boards < $200
79233: 05/02/15: Questions about multiple rom instances in Quartus II
79254: 05/02/15: Re: Questions about multiple rom instances in Quartus II
79299: 05/02/16: Re: Questions about multiple rom instances in Quartus II
91168: 05/10/31: Re: Quartus II Simulation
126643: 07/11/28: Re: Quartus memory init file
John Rinck:
4623: 96/11/21: Electronics question
John Robertson:
159890: 17/04/15: Re: FPGA as heater
159892: 17/04/15: Re: FPGA as heater
John Sampson:
112735: 06/11/28: Re: Digital PLL and FM demodulation
John Savard:
11427: 98/08/12: Re: Combinatoric Divide-by-3 Algorithm
43738: 02/05/31: Re: LFSR with 2^n instead of (2^n)-1
83996: 05/05/11: Xilinx versus Elixent; other radically different concepts?
84074: 05/05/12: Re: Xilinx versus Elixent; other radically different concepts?
John Schewel:
449: 94/11/19: Reconfigurable Computer wins Technology of the Year Award
777: 95/02/28: Call for Papers (2)
778: 95/02/28: Call for Papers
974: 95/04/05: Call for Papers
1720: 95/08/18: Design protection
2850: 96/02/16: CALL FOR PAPERS
3107: 96/04/03: Call for Papers
3352: 96/05/17: Re: Comp.Arch.FPGA Reflector V1 #541
4166: 96/09/20: Starter Boards
7036: 97/07/25: Hardware/Software Co-Design
8861: 98/02/02: Configurable Computing -- CALL for Papers
13870: 98/12/30: Reconfigurable Technology -- Call for Papers
14129: 99/01/14: FPGA/core PCI interface system
14270: 99/01/22: Re: FPGA/core PCI interface system
14271: 99/01/22: Re: FPGA development system
14447: 99/01/29: Re: FPGA/core PCI interface system
14845: 99/02/19: Final CP Reconfigurable Technology: FPGAs for Computing and Applications
15165: 99/03/10: New! Virtex Workbench
16920: 99/06/16: Re: Virtex Boards
20060: 00/01/25: CFP - Reconfigurable Technology
27983: 00/12/18: Reconfigurable Technology CFP
42511: 02/04/25: CPF - Late Breaking Papers for RTC 2002
John Schmitz:
123386: 07/08/27: Re: DDR2 controller V4 vs V5 differences ?
123475: 07/08/28: Re: DDR2 controller V4 vs V5 differences ?
127741: 08/01/06: Re: Xilinx MIG onm Solaris
John Schultz:
John Seney:
1721: 95/08/19: Digital Scope.FAQ
John Sievert:
6471: 97/05/26: Re: FPGA gate counting: No truth in advertising
6535: 97/05/31: Re: FPGA gate counting: No truth in advertising
6620: 97/06/05: Re: FPGA gate counting: No truth in advertising
John Smith:
5414: 97/02/14: Lucent Orcas ...
10862: 98/06/26: Re: I need PCI2.1 Verilog source for Xilinx.
22994: 00/06/08: difference between fpga and epld
33080: 01/07/17: processor core
33166: 01/07/18: Re: processor core
35801: 01/10/18: Xilinx PCI core and XST
60485: 03/09/15: About two open source 32bit MCU
62613: 03/11/03: Re: Shannon Entropy for Black Holes
62663: 03/11/04: Re: Shannon Entropy for Black Holes
62775: 03/11/07: Re: Shannon Entropy for Black Holes
68134: 04/03/27: Re: counter design
68142: 04/03/27: Re: AHDL, VERILOG or VHDL??
68377: 04/04/02: Re: vcom in modelsim
71170: 04/07/10: Re: Nios - Ethernet Frame Format
72016: 04/08/05: Comparing Quality of Results of FPGA CAD Tools
72702: 04/08/29: Re: Counter counting on both clock edges.
74177: 04/10/05: Re: question on interfacing FPGA with a sensor
74248: 04/10/06: Re: question on interfacing FPGA with a sensor
74249: 04/10/06: Re: Is the Xilinx's silicon better than Altera's?
74390: 04/10/10: Re: Sine function implementation in FPGA
74918: 04/10/21: Re: interfacing a PC based program with a FPGA
103650: 06/06/07: Re: LVTTL, LVCMOS or 3.3V-PCI?
103652: 06/06/07: Anyone with Xilinx SP305-board ?
103737: 06/06/10: Re: Anyone with Xilinx SP305-board ?
103738: 06/06/10: Re: Anyone with Xilinx SP305-board ?
103740: 06/06/10: Re: xilinx cable 3 doesn't talk with pc,but test ok
103741: 06/06/10: Re: Anyone with Xilinx SP305-board ?
103742: 06/06/10: Re: Anyone with Xilinx SP305-board ?
103744: 06/06/10: Re: Anyone with Xilinx SP305-board ?
103748: 06/06/10: Re: Anyone with Xilinx SP305-board ?
103750: 06/06/10: Re: Anyone with Xilinx SP305-board ?
103751: 06/06/10: Re: Anyone with Xilinx SP305-board ?
103753: 06/06/10: Re: xilinx cable 3 doesn't talk with pc,but test ok
103768: 06/06/11: Re: Anyone with Xilinx SP305-board ?
103769: 06/06/11: Re: Anyone with Xilinx SP305-board ?
103770: 06/06/11: Re: Anyone with Xilinx SP305-board ?
103775: 06/06/11: Re: Anyone with Xilinx SP305-board ?
103776: 06/06/11: Re: Anyone with Xilinx SP305-board ?
103777: 06/06/11: Re: Anyone with Xilinx SP305-board ?
103778: 06/06/11: Re: Anyone with Xilinx SP305-board ?
103779: 06/06/11: Re: Anyone with Xilinx SP305-board ?
104023: 06/06/16: Re: S3E Starter Kit webcast
104056: 06/06/18: Re: LVTTL or LVCMOS for PCI Signaling?
104057: 06/06/18: Re: Anyone with Xilinx SP305-board ?
149697: 10/11/17: Using a single port SRAM
149811: 10/11/24: System Verilog 2D input port?
151529: 11/04/17: [MODELSIM] How to add signals to wave which is a child of the module
John Smithhhhh:
22989: 00/06/07: Synplify constrains
John Solo:
6665: 97/06/11: Re: Fine Pitch PQFP : anyone any hassles?
6749: 97/06/23: Re: PCMCIA CardBus controller...
John Souders:
2520: 95/12/24: Re: [q][Reverse Engineering Protection]
John Speth:
141353: 09/06/19: Lookup table in VHDL?
141361: 09/06/20: Re: Lookup table in VHDL?
143295: 09/09/30: USB IP block vendors?
144188: 09/11/18: NIOS and ftoa()
144203: 09/11/19: Re: NIOS and ftoa()
148181: 10/06/25: Binary integer to ASCII string in HDL?
148228: 10/06/30: Re: Binary integer to ASCII string in HDL?
148344: 10/07/09: HDL float to string (sprintf %.3E)?
150443: 11/01/21: Re: Overview for non-technicals.
150761: 11/02/09: Re: Designing in Altium
150811: 11/02/14: Re: Cyclone Based FPGA Dev Board With USB Cable Program Path
153132: 11/12/08: Re: Horsepower On Tap
154147: 12/08/21: Re: recruit FPGA design engineer in Scotland
155203: 13/06/04: Re: [ANN] XMODZ-Fast modulo reduction VHDL IPs
156586: 14/05/05: Re: The USB FPGA?
157814: 15/04/01: Re: Intel in Talks to buy Altera
157950: 15/05/20: Re: AHDL VS. VHDL
158617: 16/02/03: Re: watermarking on FPGA
John Stein:
127120: 07/12/12: Xilinx RocketIO problems
127147: 07/12/12: Re: Xilinx RocketIO problems
127179: 07/12/13: Re: Xilinx RocketIO problems ->solved
John Stewart:
22437: 00/05/09: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
John T.:
59940: 03/09/02: EDK problem!
59974: 03/09/03: Re: EDK problem!
60120: 03/09/05: Re: EDK problem!
John Tan:
51379: 03/01/12: SChematic design approach compared to VHDL entry approach
53044: 03/03/01: Design consideration of high datarate wireless system
John Tasgal:
27758: 00/12/06: Re: FPGA starter kit
john tra:
160057: 17/05/17: Spartan 6 Digital controlled oscillator
John Troch:
15998: 99/04/27: Digital Phase Locked Loop
John Vickers:
4313: 96/10/14: Seeking 16V8: Vcc=3.0-5.0V: Zero standby power.
John Vincent:
3224: 96/04/29: Re: ECL, PECL gate arrays or FPGA's
4710: 96/12/04: Re: FPGA Gate Counts: No Truth in Advertising?
8715: 98/01/21: Graphical VHDL tools and FPGA design
John W. Curtis:
3265: 96/05/07: Re: so little posts about PCI :(
6656: 97/06/10: Re: What is M1?
John W. Lockwood:
84069: 05/05/11: Tutorial on debug of packet processing in FPGA hardware using Identify
John W. Schwegler:
3617: 96/07/03: Re: FPGA Companies
John Walton:
970: 95/04/05: Re: Xilinx simulation models for synopsys..
1386: 95/06/12: Re: Low cost ISA board
1656: 95/08/11: Re: VHDL/FPGAs/PLDs help
1811: 95/09/05: Re: FPGA to masked gate array conversion
4772: 96/12/13: Re: ASICs Vs. FPGA in Safety Critical Apps.
4828: 96/12/18: Re: ASICs Vs. FPGA in Safety Critical Apps.
4829: 96/12/18: Re: ASICs Vs. FPGA in Safety Critical Apps.
4878: 96/12/23: Re: New CAD tools for new Xilinx XC6200 FPGA
John Watson:
73230: 04/09/16: Xilinx Prototype Board with CAN controller
John Wertenbaker:
33366: 01/07/24: Re: Schematic libraries in webpack ?
John Wettroth:
7105: 97/07/31: Re: digitizer design, high speed
John Williams:
475: 94/11/30: Re: Help: Seeking Your Opinion of EDN Article
1722: 95/08/19: Re: Obscuring Code For Customers (was VHDL Obfuscators)
2812: 96/02/12: Re: Chosing VHDL or Verilog Does Have An Impact For U.S. Engineers
3027: 96/03/16: Re: INDUSTRY GADFLY: "From Beirut To Bosnia" + Reader Response
40126: 02/02/28: Simulation Question
40154: 02/03/01: Re: Simulation Question
40955: 02/03/19: XESS parallel cable
40956: 02/03/19: Webpack + XC4000
42689: 02/05/01: XC4000 readback woes
42690: 02/05/01: Re: Hack an bitstream file for AT40Kxx
42798: 02/05/03: Re: XC4000 readback woes
42940: 02/05/08: State machine synthesis
43001: 02/05/09: Re: State machine synthesis
43071: 02/05/13: Re: State machine synthesis
43089: 02/05/14: Re: Architecture for high-level reconfigurable computing
43091: 02/05/14: Re: Architecture for high-level reconfigurable computing
43095: 02/05/14: Re: Architecture for high-level reconfigurable computing
43401: 02/05/21: Addressable shift register
43404: 02/05/21: Re: Addressable shift register
43406: 02/05/21: Re: Addressable shift register
43554: 02/05/24: XC4000 series pin compatability
43625: 02/05/28: avoiding resynthesis
43657: 02/05/29: Re: avoiding resynthesis
43663: 02/05/29: Re: Addressable shift register
43668: 02/05/29: Re: Addressable shift register
43785: 02/06/03: Pipelining
43786: 02/06/03: Re: Pipelining
43818: 02/06/04: Re: Pipelining
43827: 02/06/04: FPGAs used to crack Xbox security
43875: 02/06/05: OFFSET timing contraints
44153: 02/06/13: clock gating by any other name...
44166: 02/06/13: Re: clock gating by any other name...
44208: 02/06/14: Re: compatibility between F3.1 and F4.1
44681: 02/06/27: Re: why not pipeline by default?
44887: 02/07/04: Fixed point arithmetic
44945: 02/07/08: Re: Fixed point arithmetic
45016: 02/07/10: Re: anyone get email about www.cradle.com ???
45056: 02/07/11: Re: anyone get email about www.cradle.com ???
45058: 02/07/11: Re: Read Delay
45085: 02/07/12: Re: FPGA CPU?
45443: 02/07/24: Re: Do you know a parallel algorithym for 2D convolution
46022: 02/08/15: Modelsim VHDL problem
46063: 02/08/16: Re: Modelsim VHDL problem
46133: 02/08/20: Re: onboard reconfiguration of Xilinx FPGA
46776: 02/09/09: minimalist FPGA system
46826: 02/09/10: Re: minimalist FPGA system
46840: 02/09/10: Re: minimalist FPGA system
47043: 02/09/16: Re: ieee.math_real for presynthesis table calculation in vhdl
48607: 02/10/22: Re: Ms-DOS formatting in an CompactFlash card?
48617: 02/10/22: Re: Ms-DOS formatting in an CompactFlash card?
48630: 02/10/22: Re: Ms-DOS formatting in an CompactFlash card?
48631: 02/10/22: Re: Ms-DOS formatting in an CompactFlash card?
48772: 02/10/24: Microblaze
49402: 02/11/12: Associative memory and multiport memories
49472: 02/11/13: Re: functional test for Xilinx virtex II Pro
49508: 02/11/14: Re: Registering inputs or outputs of modules
49510: 02/11/14: Re: Registering inputs or outputs of modules
50518: 02/12/12: Re: hardware image processing - log computation
50563: 02/12/13: Re: READBACK black box...
50564: 02/12/13: Re: READBACK black box...
50576: 02/12/13: Re: Single Event Upset in One Time PROM configuring FPGA
51448: 03/01/14: Re: Open FPGA please!
51451: 03/01/14: Re: Open FPGA please!
51486: 03/01/15: Re: Open FPGA please!
51862: 03/01/24: Re: Celoxica RC100 Demo Board: Video In
52078: 03/01/31: Microblaze - triggering exceptions
52083: 03/01/31: Re: Microblaze - triggering exceptions
52138: 03/02/03: Proper OS for Microblaze [was Re: Microblaze - triggering exceptions]
52233: 03/02/05: Re: Clock Enables
52850: 03/02/25: Re: Looking for Virtex2Pro and Linux (PPC)
52957: 03/02/27: Re: XILINX MICROBLAZE ERRORS
52996: 03/02/28: Re: XILINX MICROBLAZE ERRORS
53223: 03/03/07: Re: Need help! Any experienced Handel-C user?
53275: 03/03/10: Re: Need help! Any experienced Handel-C user?
53407: 03/03/13: Re: line counter
53409: 03/03/13: Re: line counter
53646: 03/03/19: Re: Increased Wafer yield by row adjusted placement
53731: 03/03/21: Re: Increased Wafer yield by row adjusted placement
53825: 03/03/25: Re: Does Xilinx have self-boot option like Cypress?
53830: 03/03/25: Re: triple des
53865: 03/03/26: Microblaze:Timing constraints
53866: 03/03/26: Re: Microblaze:Timing constraints
53871: 03/03/26: Re: Microblaze:Timing constraints
53872: 03/03/26: Re: Microblaze:Timing constraints
53942: 03/03/28: Re: XILINX FPGA as SUN Sparc coprocessor
53999: 03/03/31: Re: microblaze gnu tool info ?
54000: 03/03/31: Re: microblaze gnu tool info ?
54067: 03/04/02: Re: Looking for Virtex2Pro and Linux (PPC)
54079: 03/04/02: [ANN] uClinux on Xilinx Microblaze
54270: 03/04/07: Xilinx Impact and USB/LPT ports
54313: 03/04/08: Re: Xilinx Impact and USB/LPT ports
54357: 03/04/09: Re: Xilinx Impact and USB/LPT ports
54358: 03/04/09: Re: Xilinx Impact and USB/LPT ports
54364: 03/04/09: Re: Xilinx Impact and USB/LPT ports
54390: 03/04/10: Re: Xilinx Impact and USB/LPT ports
55611: 03/05/14: EDK under linux/wine - xflow problem
55647: 03/05/15: Re: EDK under linux/wine - xflow problem
55648: 03/05/15: Re: EDK under linux/wine - xflow problem
55901: 03/05/23: Virtex2 DCM CLKIN_PERIOD
55980: 03/05/26: Re: about the uclinux in Altera Nios
55981: 03/05/26: attributes and generics
55982: 03/05/26: Re: attributes and generics
55984: 03/05/26: Re: attributes and generics
56004: 03/05/27: Re: xilinix edk 3.2 and webpack
56113: 03/05/29: Re: why xflow?
56176: 03/05/30: Re: FIFO Controller
56649: 03/06/11: Re: Xilinx gdb
57876: 03/07/09: Re: FPGA device + CPU
58056: 03/07/14: Re: DCM CLKFX simulation
58090: 03/07/15: Re: DCM CLKFX simulation
58150: 03/07/16: JTAG and Xilinx
58151: 03/07/16: Re: JTAG and Xilinx
58192: 03/07/17: Re: vertex2 pci pinout
58246: 03/07/18: Re: EDK - - -XMD: Can't establish connection with Stub
58332: 03/07/21: Xilinx GCLK voltages
58360: 03/07/22: Re: Xilinx GCLK voltages
58377: 03/07/22: Re: Xilinx GCLK voltages
58414: 03/07/23: iMPACT batch mode
58445: 03/07/24: Re: iMPACT batch mode
58452: 03/07/24: Re: Use ICAp iwth a soft IP core to decompress!!!!
58467: 03/07/24: Re: Pricing question....
58515: 03/07/25: Re: Use ICAp iwth a soft IP core to decompress!!!!
58516: 03/07/25: Re: Reseting the whole thing
58626: 03/07/30: Re: Spartan IIE max pin switching
58632: 03/07/30: Re: Handel C
58634: 03/07/30: Re: Spartan IIE max pin switching
58937: 03/08/05: Re: Xuart Lite Linux driver
58940: 03/08/05: [ANN] uClinux Microblaze Update
58944: 03/08/05: Re: Xuart Lite Linux driver
58988: 03/08/06: Re: Xuart Lite Linux driver
58989: 03/08/06: Re: Xuart Lite Linux driver
58997: 03/08/06: Re: Xuart Lite Linux driver
59281: 03/08/14: Re: Update on Virtex II Pro Linux
59292: 03/08/14: Re: Update on Virtex II Pro Linux
59414: 03/08/19: "sniffing" signals
59616: 03/08/25: [ann] Microblaze uClinux Demo released
59660: 03/08/26: Re: [ann] Microblaze uClinux Demo released
59687: 03/08/26: Re: [ann] Microblaze uClinux Demo released
59688: 03/08/26: Re: [ann] Microblaze uClinux Demo released
59720: 03/08/27: Re: How to listen to music through an FPGA pin?
60029: 03/09/04: Re: [ann] Microblaze uClinux Demo released
60092: 03/09/05: Re: New to FPGA, seeking advice
60379: 03/09/12: Re: Xilinx-gdb Sources publicly available?
60380: 03/09/12: Re: Xilinx-gdb Sources publicly available?
60381: 03/09/12: Re: DDR in EDK 3.2sp2...
60389: 03/09/12: Re: Xilinx-gdb Sources publicly available?
60475: 03/09/15: Re: Spartan 3 ICAP primitive
60480: 03/09/15: Re: Spartan 3 ICAP primitive
60520: 03/09/16: spartan3 pin tables
60524: 03/09/16: Re: spartan3 pin tables
60525: 03/09/16: Re: Spartan 3 ICAP primitive
60585: 03/09/17: platform flash as storage?
60628: 03/09/18: Re: spartan3 pin tables
60752: 03/09/22: Re: Parallel JTAG cable on a USB-only W2K laptop?
60863: 03/09/24: Re: FPGA implementation in (V)HDL
61398: 03/10/03: Re: Evaluation time of Emac Core?
61679: 03/10/09: Re: MICROBLAZE: Using external instruction memory
61680: 03/10/09: Re: MICROBLAZE: Using external instruction memory
61700: 03/10/09: Re: MICROBLAZE: Using external instruction memory
61745: 03/10/10: Re: MICROBLAZE: Using external instruction memory
61751: 03/10/10: Re: MICROBLAZE: Using external instruction memory
62107: 03/10/20: Re: MICROBLAZE: executing program from external memory
62151: 03/10/21: Re: MICROBLAZE: executing program from external memory
62277: 03/10/24: Re: OPB write actions
62590: 03/11/03: Re: Microblaze & ucLinux for XSV800
62591: 03/11/03: Vendor supplied symbol/part models?
62596: 03/11/03: Re: Vendor supplied symbol/part models?
62639: 03/11/04: Re: Vendor supplied symbol/part models?
62640: 03/11/04: Re: Building the 'uber processor'
62689: 03/11/05: Xilinx platform flash VCCO/VCCJ
62890: 03/11/11: Re: Home grown CPU core legal?
62891: 03/11/11: Re: Home grown CPU core legal?
63026: 03/11/13: Re: System generator and Microblaze
63518: 03/11/25: Re: 400 Mb/s ADC
63519: 03/11/25: Re: Laptop without serial/parallel port
63623: 03/11/27: Re: 5V I/O with 1.8V Core
64087: 03/12/16: Re: Extracting timing from a demo board (V2MB1000)
64131: 03/12/18: Re: Xilinx 6.1i Tools and Newer Redhat Linux OSes
64169: 03/12/19: Re: interfacing a WishBone IP core to a CoreConnect bus
65687: 04/02/05: Re: Experiences with Microblaze and Nios
65693: 04/02/05: Re: binary file to bram tool
65718: 04/02/05: Re: Xilinx PAD name to (X,Y) RPM coordinate
65756: 04/02/06: Re: Reconfiguring at runtime internally?
65912: 04/02/10: Partial reconfig flow
66057: 04/02/12: Re: debug with opb mdm for microblaze system
66076: 04/02/12: Re: Partial reconfig flow
66136: 04/02/13: Re: Xilinx FPGA Editor - can one see the switch box detail?
66144: 04/02/13: Re: Partial reconfig flow
66296: 04/02/17: Re: Partial Reconfig - PAR fails with ISE 6.1 SP3
66347: 04/02/18: Re: Partial Reconfig - PAR fails with ISE 6.1 SP3
66948: 04/03/02: Re: DesignCon 2002 Paper
66957: 04/03/02: Re: DesignCon 2002 Paper
67039: 04/03/04: Re: EDK and LMB peripherals...
67376: 04/03/11: Re: fpga
67389: 04/03/11: Re: CORDIC vs. LUT
67869: 04/03/22: Re: Virtex2
67929: 04/03/23: Re: quick opb bus questions
67938: 04/03/23: Re: How many times can I burn an FPGA?
68163: 04/03/29: Re: study verilog or vhdl?
68243: 04/03/31: Re: speed vs. temperature
68433: 04/04/05: Re: Constant (K) Coded Programmable State Machine for Spartan-II
68469: 04/04/06: Re: Real-time Image Process on FPGA
68731: 04/04/16: Re: ICAP with microblaze
69331: 04/05/07: Re: Partial Reconfiguration
69523: 04/05/13: Re: Compact Flash FPGA card
71018: 04/07/06: Re: uClinux on MicroBlaze
71516: 04/07/21: Re: FPGA in a Compact Flash format.
71837: 04/08/02: Re: uLinux for Memec-Insight VP20 board ?
71839: 04/08/02: Re: NCD difference
71925: 04/08/04: Re: NCD difference
72019: 04/08/06: Re: Comparing Quality of Results of FPGA CAD Tools
72037: 04/08/06: Re: Comparing Quality of Results of FPGA CAD Tools
72102: 04/08/09: Re: Newbie Question: Unused pins in the constraint file
72103: 04/08/09: Re: xilinx edk6.2.03i simulation with ncsim
72104: 04/08/09: Re: Microblaze opb_emc
72136: 04/08/10: Re: xilinx edk6.2.03i simulation with ncsim
72137: 04/08/10: Re: Impact running on wine?
72225: 04/08/12: Re: why?
72229: 04/08/12: Re: Primitve 3D Graphics Library
72280: 04/08/13: Re: Dual Microblaze System
72281: 04/08/13: Re: vertex-II configuration architecture
72335: 04/08/16: Re: Dual Microblaze System
72441: 04/08/19: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72519: 04/08/23: Re: XC2V250 protoboard
72694: 04/08/29: Re: using GNU to compile for PPC405?
72695: 04/08/29: Re: EDK core wrapping and include files
73909: 04/10/01: Re: MicroBlaze is no available as Open-Source!! (from independant
73338: 04/09/20: Re: How intimidating is Xilinx's EDK?
73513: 04/09/23: Re: [ALTERA] NIOS-II + MMU + FPU
74936: 04/10/22: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
75018: 04/10/25: Re: Assembler for PicoBlaze in Perl
75021: 04/10/25: Re: Active Rece\onfiguration of Xilinx FPGAs
75058: 04/10/26: Re: Assembler for PicoBlaze in Perl
75060: 04/10/26: Re: Assembler for PicoBlaze in Perl
75077: 04/10/26: Re: PacoBlaze 1.3b
75140: 04/10/27: Re: OPB in Verilog
75202: 04/10/29: Re: Newbie: Read from Compact Flash using System ACE
75345: 04/11/03: Re: Low-power FPGAs?
75347: 04/11/03: Re: Low-power FPGAs?
74084: 04/10/04: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74087: 04/10/04: Re: M*Blaze in Cyclone ! End of What? ;)
74099: 04/10/04: Re: M*Blaze in Cyclone ! End of What? ;)
74205: 04/10/06: Re: Uploading data to the DDR memory on the ML300 board
74263: 04/10/07: Re: DCM and CLKFX - is this allowed?
74400: 04/10/11: Re: DCM and CLKFX - is this allowed?
74405: 04/10/11: Re: Use Xilinx VP20 with 2 ppc and one DRAM chip
74412: 04/10/11: Re: Use Xilinx VP20 with 2 ppc and one DRAM chip
74556: 04/10/14: Re: JBits and Spartan
74568: 04/10/14: Re: JBits and Spartan
74711: 04/10/17: Re: ModelSim
74773: 04/10/19: Re: ModelSim
74885: 04/10/21: Re: Active Rece\onfiguration of Xilinx FPGAs
74635: 04/10/15: Re: EP1C12 or XC3S400?
74676: 04/10/15: Re: EP1C12 or XC3S400?
74677: 04/10/15: Re: Was EP1C12 or XC3S400? : Is Altium eval board
74692: 04/10/16: Re: Was EP1C12 or XC3S400? : Is Altium eval board
74700: 04/10/16: Re: Was EP1C12 or XC3S400? : Is Altium eval board
75383: 04/11/04: Re: need an fpga board
75493: 04/11/08: Re: FPGA Network Encryption Engine
75598: 04/11/11: Re: Xilinx Tshirts in football package.....
75846: 04/11/17: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
75852: 04/11/17: Re: ISO Free cores repository
75854: 04/11/17: Re: ISO Free cores repository
75877: 04/11/18: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
76102: 04/11/25: Re: Hierarchical PCB design.
76105: 04/11/25: Re: Hierarchical PCB design.
77339: 05/01/05: Re: LEON2 or microblaze
78045: 05/01/24: Re: Comparison of LEON2, Microblaze and Openrisc processors
78055: 05/01/24: Re: imported ip
78106: 05/01/25: Re: trouble setting up ISE 6.3i in linux
79079: 05/02/14: Re: In need of some life-changing advice
79372: 05/02/18: Re: thread programming support in EDK?
79373: 05/02/18: Printing in ChipScope
79557: 05/02/21: Re: Printing in ChipScope
79672: 05/02/23: Re: FPGA board with best cost/CLB ratio?
81326: 05/03/22: Re: Downloading problems [Memec DS-BD-V2MB1000 Virtex-II board].
81410: 05/03/23: Chipscope and Virtex4 LX25 ES
82311: 05/04/11: Re: Neural Networks in FPGA
82365: 05/04/12: Re: EDK: Microblaze with XMdstub
82451: 05/04/13: Re: General question about soft CPUs
82623: 05/04/15: Re: Xilinx TMRTool price
82916: 05/04/20: Re: Xilinx tools from the commandline
82931: 05/04/20: Re: Linux, ISE 7.1, problems, problems, problems ....
84071: 05/05/12: Re: DDR speed of the XUPV2P Board from Digilent
84231: 05/05/16: Re: Update Picoblaze Code in Bitstream
84232: 05/05/16: Re: microblaze and 64 bit memory over PLB bus
84236: 05/05/16: Re: Update Picoblaze Code in Bitstream
84239: 05/05/16: Re: DDR speed of the XUPV2P Board from Digilent
84904: 05/06/01: Re: Accessing Bram
84905: 05/06/01: Re: Configuration-Frames for Virtex-II (Pro)
85228: 05/06/07: Re: Microblaze 4.0 with uClinux is ok or not?
85473: 05/06/10: Re: Ml40x Reference Design not working with EDK 7.1?
85479: 05/06/10: Re: Question for Alex Gibson
85677: 05/06/14: Re: linker script!!!
85725: 05/06/15: Memec S3-1500 board + P160 comms 2
85728: 05/06/15: Re: Memec S3-1500 board + P160 comms 2
85732: 05/06/15: Re: Somewhat OT - falling behind the times ...
85775: 05/06/16: Re: Memec S3-1500 board + P160 comms 2
85987: 05/06/20: Re: Microblaze address space and variables
86101: 05/06/22: Re: comp.arch.fpga.<mfr>
86192: 05/06/23: Re: Need some help with understanding MDM
86555: 05/06/30: Re: multiprocessing with microblaze ?
87190: 05/07/19: Re: EDK 7.1 with ML401 (paging Antti)
88335: 05/08/16: Re: Virtex-2 Pro: Configuration Frames
91926: 05/11/17: Re: Add files to Xilinx ISE Project w/script
91959: 05/11/18: Re: ml310 DDR problem
92136: 05/11/23: Re: Flip-flop state extraction out of reaback stream in Virtex-II/Pro
92142: 05/11/23: Re: Microblaze and custom peripherals
92741: 05/12/06: Re: Is it legal to write an logical equation for a FPGA LUT in claims
94130: 06/01/06: Re: URGENT: Virtex-II Pro X - Clock correction questions
94389: 06/01/11: Re: how to speed up the program running in ddr sdram
94509: 06/01/13: Re: best evm for virtex-4 and linux
94646: 06/01/16: Re: best evm for virtex-4 and linux
94713: 06/01/17: Re: best evm for virtex-4 and linux
94799: 06/01/18: Re: best evm for virtex-4 and linux
95526: 06/01/24: Re: EDK 8.1, Finally!
95912: 06/01/27: Re: [OT]Re: encryption
96120: 06/01/31: Re: Impact 8.1 problems with non xilinx device in chain
96073: 06/01/30: Re: Connection between FSL and XCL
96118: 06/01/31: Re: Virtex4 : Audio Codec AC97 LM4550
96127: 06/01/31: Re: Xilinx Legal
96138: 06/01/31: Re: Xilinx Legal
96145: 06/01/31: Re: Xilinx Legal
96209: 06/02/01: Re: Impact 8.1 problems=> uClinux rules on MicroBlaze !!!
96295: 06/02/02: Re: Impact 8.1 problems=> uClinux rules on MicroBlaze !!!
96509: 06/02/06: Re: multi-processor linux on xilinx
96510: 06/02/06: Re: usb gadgets and xilinx
96514: 06/02/06: Re: question for the EDK users out there...
96563: 06/02/07: Re: microblaze xmd question..
96564: 06/02/07: Re: usb gadgets and xilinx
96566: 06/02/07: Re: microblaze xmd question..
96571: 06/02/07: Re: microblaze xmd question..
96638: 06/02/08: Re: Software reset for the MicroBlaze
96740: 06/02/10: Re: question for the EDK users out there...
96741: 06/02/10: Re: Software reset for the MicroBlaze
96878: 06/02/13: Re: SMP on virtex-ii pro
97462: 06/02/23: Re: "par.exe" halted without error (partial configuratio)
97808: 06/02/28: Re: PCI configuration for ML310
97851: 06/03/01: Re: PCI configuration for ML310
97852: 06/03/01: Re: PPC Linux SoC on Virtex4 in 4 hours !?
98119: 06/03/06: Re: PCI configuration for ML310
99072: 06/03/20: Re: replacement of opb_mdm core for ML401 kit: opb_mdm_v2_01_a
99075: 06/03/20: Re: HWICAP with the Virtex II Pro. Anybody? Bueller?
99559: 06/03/27: Re: linux on memec fx12 mini-module?
99822: 06/03/30: Re: FSL to VHDL interface
99907: 06/03/31: Re: FSL to VHDL interface
100345: 06/04/07: Re: Accessing compact flash?????????
101113: 06/04/26: Re: Smallest uClinux configuration
102029: 06/05/10: Re: ml-403 and USB
102591: 06/05/18: Re: USB2 camera to Xilinx ML40x boards
103679: 06/06/08: Re: Can ILMB and DLMB of Microblaze be 24kByte?
104712: 06/07/05: Re: next EDK service pack release date?
105206: 06/07/18: Re: OPB or FSL?
107042: 06/08/24: Re: uclinux on spartan-3e starter kit
108319: 06/09/08: Re: ddr with multiple users
108484: 06/09/12: Re: uclinux on spartan-3e starter kit
108543: 06/09/13: Re: uclinux on spartan-3e starter kit
108607: 06/09/14: Re: uclinux on spartan-3e starter kit
109193: 06/09/22: Re: Verification errors using Xilinx Spartan 3E board
109194: 06/09/22: Re: Dell Laptop for Embedded Work
109337: 06/09/25: Re: uBlaze : -m compile directives...
110168: 06/10/12: Re: EDK Bug
110779: 06/10/23: Re: Microblaze uclinux Kernel panic
112765: 06/11/29: Re: MPMC2: MPMC2 with DDR2 SDRAM
112842: 06/11/30: Re: MPMC2: MPMC2 with DDR2 SDRAM
112843: 06/11/30: Re: opb master kills linux?
112907: 06/12/01: Re: MPMC2: MPMC2 with DDR2 SDRAM
113400: 06/12/13: Re: MPMC2: MPMC2 with DDR2 SDRAM
113714: 06/12/20: Re: uClinux bootloader on Spartan-3e Starter Kit
113773: 06/12/21: Re: Soft processor Microblaze vs embedded core PowerPC
113774: 06/12/21: Re: Spartan 3E Starter Kit Woes
114635: 07/01/22: Re: Correction for hwicap_v1_00_a code
114839: 07/01/25: Re: uClinux on Spartan 3
114987: 07/01/29: Re: uClinux on Spartan 3
115032: 07/01/30: Re: uClinux on Spartan 3
115033: 07/01/30: Re: Linux on Virtex 4?
115097: 07/01/31: Re: USB 2.0 Streaming using FPGAs
115149: 07/02/01: plb_gemac SerDes mode on V4-FX?
115285: 07/02/06: Re: uClinux on Spartan 3
115307: 07/02/07: Re: Multiple MicroBlaze based Multiprocessor system
115341: 07/02/08: Re: Compile uCLinux for Spartan 3e
115379: 07/02/09: Re: Compile uCLinux for Spartan 3e
115381: 07/02/09: Re: Read CLB information from NCD file
115509: 07/02/13: Re: PETALINUX-COPY-AUTOCONFIG ERROR
115573: 07/02/14: Re: IP to OPB FIFO
115612: 07/02/15: Re: Can't get the ACE to run software apps on the ML403
115759: 07/02/20: Re: MPD Files
115968: 07/02/27: Re: Virtex 4
116070: 07/03/01: Re: Spartan MicroBlaze
116206: 07/03/05: Re: Boot uClinux from RAM without flash
117808: 07/04/11: Re: SetJmp/LongJmp for Microblaze
118605: 07/05/01: Re: Problem cascading 2 DCMs
119333: 07/05/17: Re: seeking insights for potential reconfigurable computing application
119934: 07/05/30: Re: Linux device driver for FPGA Xilinx Virtex-4
119935: 07/05/30: Re: Looking for experiences with SUZAKU SZ010/SZ030
120354: 07/06/06: Re: Build error for multiprocessor sytem.
120729: 07/06/15: Re: c code to initialize a peripheral
120902: 07/06/20: [Announce] Linux 2.6.20 on MicroBlaze now available
120946: 07/06/21: Re: Linux 2.6.20 on MicroBlaze now available
121106: 07/06/26: Re: How to choose FPGA for a huge computation?
121304: 07/07/02: Re: How to pass several commands inside xps from script?
121576: 07/07/09: Re: Debugging in EDK
122025: 07/07/18: Re: Req: (Free) Embedded Platforms for Education
122204: 07/07/24: Re: watchdog timer: interrupt handler: microblaze
122821: 07/08/08: Re: Microblaze GPIO interrupt
122822: 07/08/08: Re: TEMAC Performance Issues with Virtex 4FX
122905: 07/08/10: Re: EDK speed issue
123136: 07/08/17: Re: about mb-gcc error???
123486: 07/08/29: Re: VGA controller in the EDK ?
123975: 07/09/10: Re: Help getting sdram running with EDK.
124072: 07/09/12: Re: microblaze toolchain compilation question
124188: 07/09/14: Re: MicroBlaze Tutorial
125276: 07/10/19: Re: xilinx Edititons
125641: 07/10/31: Re: debugging ppc + mb
125914: 07/11/09: Re: debugging ppc + mb
126707: 07/11/30: Re: EDK 9.2 Woes
126956: 07/12/07: Re: Using FSL with Interrupts
127742: 08/01/07: Re: MicroBlaze floating point precision issues
129075: 08/02/14: Re: ML505 with Petalinux
129275: 08/02/20: Re: Which Linux Distro to use for Xilinx tools
129520: 08/02/27: Re: About John Williams' ICAP driver?
129521: 08/02/27: Re: Which Linux Distro to use for Xilinx tools
129848: 08/03/07: MicroBlaze MMU support test release now available
130218: 08/03/18: SGMII, xps_ll_temac and MDIO / MCD
130301: 08/03/19: Re: FSL or DMA w/ FIFO?
130545: 08/03/26: Re: SGMII, xps_ll_temac and MDIO / MCD
130598: 08/03/28: Re: Linux 2.6 PCI Device Driver on Virtex 4
132749: 08/06/06: Re: using hard tri-mode ethernet MAC and MPMC on virtex 5
John Willoughby:
454: 94/11/21: Re: Help: Seeking Your Opinion of EDN Article
10848: 98/06/25: Re: TESTBENCH
12122: 98/09/30: Re: Which FPGA tool is better
12491: 98/10/13: Re: VHDL Tool
12783: 98/10/29: Re: Need VHDL tools for Win NT/ Win 95
John Wiseman:
8090: 97/11/17: QEX article on FPGA application...
9131: 98/02/23: MPEG video tutorial
john wo:
85660: 05/06/13: never seen XST error
John Woodgate:
8373: 97/12/11: Re: what is metastability time of a flip_flop
8374: 97/12/11: Re: what is metastability time of a flip_flop
8375: 97/12/11: Re: what is metastability time of a flip_flop
8389: 97/12/12: Re: what is metastability time of a flip_flop
8407: 97/12/12: Re: what is metastability time of a flip_flop
8418: 97/12/13: Re: what is metastability time of a flip_flop
8426: 97/12/14: Re: what is metastability time of a flip_flop
8352: 97/12/10: Re: what is metastability time of a flip_flop
8361: 97/12/10: Re: what is metastability time of a flip_flop
11575: 98/08/25: Re: New Evolutionary Electronics Book
11598: 98/08/26: Re: New Evolutionary Electronics Book
13924: 99/01/02: Re: Can a cross coupled latch "oscillate"? was Re: ..........
13973: 99/01/05: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
13974: 99/01/05: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14000: 99/01/06: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14001: 99/01/06: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14022: 99/01/07: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14032: 99/01/08: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14047: 99/01/09: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14074: 99/01/11: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
23184: 00/06/16: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
64404: 04/01/02: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
64405: 04/01/02: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
76945: 04/12/16: Re: Exportability of EDA industry from North America?
78614: 05/02/04: Re: Exportability of EDA industry from North America?
107706: 06/08/31: Re: Performance Appraisals
107772: 06/09/01: Re: Performance Appraisals
107818: 06/09/01: Re: Performance Appraisals
107819: 06/09/01: Re: Performance Appraisals
107822: 06/09/01: Re: Performance Appraisals
107825: 06/09/01: Re: Performance Appraisals
107838: 06/09/01: Re: Performance Appraisals
107844: 06/09/01: Re: Performance Appraisals
107846: 06/09/01: Re: Performance Appraisals
107847: 06/09/01: Re: Performance Appraisals
107853: 06/09/01: Re: Performance Appraisals
107855: 06/09/01: Re: Performance Appraisals
107863: 06/09/01: Re: Performance Appraisals
107865: 06/09/01: Re: Performance Appraisals
107866: 06/09/01: Re: Performance Appraisals
107867: 06/09/01: Re: Performance Appraisals
107868: 06/09/01: Re: Performance Appraisals
107878: 06/09/01: Re: Performance Appraisals
107879: 06/09/01: Re: Performance Appraisals
107880: 06/09/01: Re: Performance Appraisals
107909: 06/09/02: Re: Performance Appraisals
107911: 06/09/02: Re: Performance Appraisals
107912: 06/09/02: Re: Performance Appraisals
107956: 06/09/03: Re: Performance Appraisals
107965: 06/09/03: Re: Performance Appraisals
108053: 06/09/04: Re: Please help me with (insert task here)
108057: 06/09/04: Re: Please help me with (insert task here)
108058: 06/09/04: Re: Please help me with (insert task here)
108225: 06/09/06: Re: Please help me with (insert task here)
108427: 06/09/11: Re: Performance Appraisals
108770: 06/09/16: Re: Performance Appraisals
<john.deepu@gmail.com>:
80180: 05/03/02: Need suggestion abt FFs without RST for pipelined datapath.
81501: 05/03/25: Onchip SRAM Vs Registers
85138: 05/06/06: 32/16 divider, ASIC(Designware) Vs Xilinx FPGA(Coregen)
85140: 05/06/06: Re: 32/16 divider, ASIC(Designware) Vs Xilinx FPGA(Coregen)
85252: 05/06/07: Fast/low area Sorting hardware.
85255: 05/06/07: Re: Fast/low area Sorting hardware.
85268: 05/06/07: Re: Fast/low area Sorting hardware.
john.lv:
141364: 09/06/20: How to access Plx 8311 doorbell register?
<john.m.oyler@gmail.com>:
121392: 07/07/03: Hobbyist trying to decide which device to start with...
121402: 07/07/03: Re: Hobbyist trying to decide which device to start with...
john.orlando@gmail.com:
116353: 07/03/07: Re: Where do I find CMOS image sensors and lenses?
137255: 09/01/06: Re: beginner synthesize question - my debounce process won't
141042: 09/06/03: Re: Xilinx GbE performance
146939: 10/04/02: Re: FMC Boards ?
147069: 10/04/12: Re: Virtex-5 FPGA PCIe card
149231: 10/10/10: Re: Spartan-6 Boards
149480: 10/10/28: [ANN] Bitshark FMC-1RX software-defined RF receiver in an FMC card
<john.orlando@gmail.com>:
89566: 05/09/19: Reprogramming FPGA over PCI???
89694: 05/09/22: Re: Reprogramming FPGA over PCI???
89813: 05/09/27: Re: lwip sockets on spartan 3 microblaze? Any examples?
90800: 05/10/21: Re: Avnet Technical Support Terrible!!!
92960: 05/12/09: Re: ISE purchase
93280: 05/12/18: Re: FPGA-pci communication
104607: 06/06/30: Re: Problem to extend Xilinx GSRD Design
<john.pallazola@earthtron.com>:
159630: 17/01/23: Re: Ball-park price of Xilinx Virtex 7 FPGA?
<john.windish@gmail.com>:
114452: 07/01/16: Synchronizing four phase-offset clock domains
john1529:
142733: 09/08/28: sharing sdram and parallel nor flash address/data bus using xilinx
<john@axt.com>:
6898: 97/07/07: Who was Spamming Who
<john@griessen.com>:
122565: 07/07/31: Re: completely open source fpga toolchain
<john@jjdesigns.fsnet.co.uk>:
111272: 06/10/31: Re: Question about bandwidth of scope?
john_griessen:
137164: 08/12/29: Re: FPGA > ASIC
137865: 09/02/01: Re: Actel CoreABC not working in Libero 8.5
John_H:
31043: 01/05/09: Re: Xilinx Constraints Editor ?
31111: 01/05/11: Re: Asynchronous Compare
31181: 01/05/14: Re: Nasty "register ordering" in map
31339: 01/05/19: Re: Digital PLL (DPLL) design help
31356: 01/05/20: Re: Counter problem in Altera AHDL...
31375: 01/05/21: Re: FPGA consultant needed
31411: 01/05/22: Re: Counter problem
31579: 01/05/30: Re: Help: RAM clear in one clock cycle
31613: 01/05/31: Re: Barrel shifter in Xilinx Virtex-E
31614: 01/05/31: Re: PAD to PAD Timing Constraints. (Xilinx)
31961: 01/06/09: Re: [Xilinx] Spartan II Devices ..internal tristate busses ...
32047: 01/06/12: Re: Gray Code Guard bits (was Re: Help in FIFO design)
32048: 01/06/12: Re: Gray Code Guard bits (was Re: Help in FIFO design)
32057: 01/06/12: Re: High Speed Sampling Oscilloscope in an FPGA
32147: 01/06/15: Re: efficient CAM in Virtex or Spartan II?
32261: 01/06/21: Re: Two's Complement conversion for FIR coefficients
32269: 01/06/21: Re: synplicity 6.2.4 'optimizing' instantiated designs
32314: 01/06/22: Re: Verilog or VHDL?
32424: 01/06/26: Re: Xilinx logic usage
32425: 01/06/26: Re: IOB FF in Synplicity
32441: 01/06/26: A start...
32480: 01/06/27: Cheap ECL-TTL translator
32792: 01/07/09: Re: Online threshold limit counter
32795: 01/07/09: Re: Shift and Add Multiplier With Signed Numbers
32804: 01/07/09: oops
32808: 01/07/09: Re: What chip!?
32809: 01/07/09: Re: Shift and Add Multiplier With Signed Numbers - just a bit more
32845: 01/07/10: Re: Two's complement to binary translation problem
32853: 01/07/10: Re: Adder/Subtracter Core???
32864: 01/07/10: Re: Online threshold limit counter
32873: 01/07/10: Re: Adder/Subtracter Core???
32904: 01/07/11: Re: Need to speed up VHDL accumulator on Xilinx
32905: 01/07/11: Re: Online threshold limit counter
32953: 01/07/12: Re: DLL Phase Locking in Division Mode
32977: 01/07/13: Re: Design entry
33017: 01/07/15: Re: Which Chip Family?
33018: 01/07/15: Re: Design entry
33019: 01/07/15: Re: Shift and Add Multiplier With Signed Numbers
33059: 01/07/16: Re: Fixing routing in a Virtex FPGA
33106: 01/07/17: Re: regarding the constraints while writing VHDL code
33222: 01/07/19: Re: Working Design - Anyone
33229: 01/07/19: Re: 30 m cable reception with APEX LVDS I/O ?????
33290: 01/07/22: Re: I needs a saturable adder.
33297: 01/07/22: Re: I needs a saturable adder.
33321: 01/07/23: Re: I needs a saturable adder.
33445: 01/07/26: Re: prospects for tiny FPGA supercomputer?
33532: 01/07/29: Re: Jitter Added by FPGA counter
33533: 01/07/29: Re: Reset during accumulation
33552: 01/07/30: Re: How to add carry optimizations
33645: 01/08/01: Re: Err with this AHDL code
33646: 01/08/01: Re: Vitex-II prototyping board
33690: 01/08/02: Re: Err with this AHDL code
33716: 01/08/02: Re: Simple Division by Shift/Add (2nd try)
33717: 01/08/02: Re: Err with this AHDL code
33723: 01/08/03: Re: Clock skew with Xilinx DLLs...
34022: 01/08/11: Re: how to acheive high frquency in Xinlinx Virtex E
34212: 01/08/16: Re: DPLL frequency synthesis
34365: 01/08/22: Re: How does For Loop works in AHDL
34377: 01/08/22: Re: How does For Loop works in AHDL
34477: 01/08/27: Re: Help needed: simulation OK, synthesis OK, but doesnt work :-<
34478: 01/08/27: Re: Spartan-II & clock
34582: 01/08/29: Re: Urgent Please
34627: 01/08/31: Re: Ugly signal output...
34834: 01/09/10: Re: To mix frequency with a FPGA
34854: 01/09/11: Re: Missing bits Part 2!
34942: 01/09/14: Re: A vs. X
34981: 01/09/17: Re: Virtex-2 availability
34982: 01/09/17: Re: Carry Chain: Delay
34985: 01/09/17: Re: using BlockRAM
35033: 01/09/18: Re: Increase routing delay in XILINX FPGA editor
35054: 01/09/19: Re: Synplicity logic replication
35088: 01/09/20: Re: Maximum clock rate of various Xilinx families?
35092: 01/09/20: Re: Virtex-2 availability
35112: 01/09/21: Re: Stopping a DLL
35121: 01/09/21: Re: Stopping a DLL
35122: 01/09/21: Re: Virtex Clock Enable and Synplify
35228: 01/09/26: Re: how to dublicate logic?
35312: 01/09/28: Re: how to dublicate logic?
35408: 01/10/03: Re: Virtex II DCM: Phase Shifting
35837: 01/10/19: Re: Digital mixers,complex multipliers
36035: 01/10/26: Re: How to make an implementable big counter?
36436: 01/11/08: Re: Quadrature Encoder Sampling Time
36443: 01/11/09: A Quadrature Encoder to binary counter
36570: 01/11/12: Re: Quadrature Encoder Sampling Time
36766: 01/11/19: Re: Decoupling capacitors on Virtex II
36965: 01/11/27: Re: Creating a jitter free clock
37011: 01/11/28: Re: Creating a jitter free clock
37193: 01/12/03: Re: What do you like/dislike about place and route tools?
37207: 01/12/04: Re: Phase noise (jitter) of XILINX logic elements - ?
37237: 01/12/04: Re: What do you like/dislike about place and route tools?
37238: 01/12/04: Re: What do you like/dislike about place and route tools?
37490: 01/12/12: Re: Crosstalk on clocks
38186: 02/01/08: Re: 128 bit compare delay kill me!
38196: 02/01/08: Re: latch vs. register
38238: 02/01/09: Re: function generators of Xilinx XCVxxxxE series
38700: 02/01/22: Re: Signal processing using FPGAs
38798: 02/01/25: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38814: 02/01/26: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
39277: 02/02/05: Re: FPGA vs GAL : Lattice
39411: 02/02/08: Re: Xilinx DCM question anyone? (or Peter if he is there?)
39412: 02/02/08: Re: Xilinx ISE 3.3 upgrade to 4.1
39484: 02/02/11: Re: Altera's new family Stratix
39529: 02/02/12: Re: Newbie SpartanII Block Ram question
39538: 02/02/12: Re: Altera's new family Stratix
39660: 02/02/15: Re: Newbie question Synchronous RAM
39661: 02/02/15: Re: RAM CORE result that I did not understand
40034: 02/02/25: Re: Virtex-II and SDRAM Controller at 133MHz
40190: 02/03/01: Re: Clock multiplier/ADPLL in PLD
40191: 02/03/01: Re: Altera FPGAs
40211: 02/03/02: Re: Clock multiplier/ADPLL in PLD
40278: 02/03/04: Re: What FPGA to use?
40280: 02/03/04: Re: phantom timing constraints in ISE 4.1
40336: 02/03/05: Re: digital video PLL
40337: 02/03/05: Re: Need Help
40349: 02/03/05: Re: digital video PLL
40414: 02/03/06: Re: Mutual Clock Synchronization
40421: 02/03/06: Re: Mutual Clock Synchronization
40466: 02/03/07: Re: Mutual Clock Synchronization
40475: 02/03/07: Re: Mutual Clock Synchronization
40516: 02/03/08: Re: GATE ARRAY PROJECT
40585: 02/03/11: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40603: 02/03/11: Re: Logic levels
40663: 02/03/12: Re: Pins levels on Spartan.
40664: 02/03/12: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40713: 02/03/13: Re: How do I infer a carry-chain parity generator in XST?
40714: 02/03/13: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40718: 02/03/13: Re: digital video PLL
40724: 02/03/14: Re: digital video PLL
40801: 02/03/15: Re: High speed clock routing
40812: 02/03/16: Re: High speed clock routing
40932: 02/03/18: Re: Hardware : How to set the RESET signal...
41061: 02/03/20: Re: FIFO general question
41084: 02/03/20: Re: MAX7000 bypass capasitances
41086: 02/03/20: Re: FIFO general question
41104: 02/03/21: Re: FIFO general question
41135: 02/03/21: Re: RAM initialization
41136: 02/03/21: Re: Difference between two mulplications?
41139: 02/03/21: Re: High speed clock routing
41145: 02/03/21: Re: Maximum device usage for successful PAR
41147: 02/03/21: Re: High speed clock routing
41207: 02/03/22: Any DDR SDRAM controller stories?
41212: 02/03/22: Re: Pipelined sorting algorithms...
41230: 02/03/22: Re: Pipelined sorting algorithms...
41302: 02/03/25: Re: question on LFSR
41429: 02/03/28: Re: Pipelined sorting algorithms...
41478: 02/03/29: Re: position
41487: 02/03/29: Re: pipelined correlation block on Virtex2000?
41526: 02/04/01: Re: Data Compression in FPGAs
41527: 02/04/01: Re: Update: A petition for Synplify's new fature (FPGA synthesis tool)
41538: 02/04/01: Re: Data Compression in FPGAs
41616: 02/04/03: Re: Signals pollution.
41617: 02/04/03: Re: how to synchronise asynchronous inputs?
41633: 02/04/03: Re: powerpc in virtex2pro
41713: 02/04/05: Re: hand placement
41716: 02/04/05: Re: hand placement
41826: 02/04/08: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
41866: 02/04/09: Re: uniquifying a synplicity netlist
41893: 02/04/10: Re: FPGA Partioning
41995: 02/04/12: Re: DDR SDRAM Controller
42078: 02/04/15: Re: virtex2 bufgce or not bufgce
42246: 02/04/18: Re: Understanding clock routing (or not)
42248: 02/04/18: Re: 1000 I/O Pins -- What is cheapest FPGA?
42250: 02/04/18: Re: 1000 I/O Pins -- What is cheapest FPGA?
42254: 02/04/18: Re: fpga limitation
42308: 02/04/19: Re: 1000 I/O Pins -- What is cheapest FPGA?. What about Route and place
42386: 02/04/22: Re: fpga limitation
42478: 02/04/25: Re: Using 74HCT245N between Spartan-II and ISA
42978: 02/05/08: Re: trace report
42981: 02/05/08: Re: Timing of XC2S200E-6FG456C compared to XC2S200E-6FG456I
42985: 02/05/08: Re: Timing of XC2S200E-6FG456C compared to XC2S200E-6FG456I
43121: 02/05/14: Re: 50 mA sink
43169: 02/05/15: Re: Frequency synthesiser
43216: 02/05/16: Re: Frequency synthesiser
43254: 02/05/17: Re: What properties has FPGA?
43255: 02/05/17: Re: Frequency synthesiser
43362: 02/05/20: Re: How to generate fractional-N clock ?
43365: 02/05/20: Re: button & 3 LED's
43368: 02/05/20: Re: virtex 2 block rams
43370: 02/05/20: Re: SDRAM pricing
43372: 02/05/20: Re: How to generate fractional-N clock ?
43374: 02/05/20: Re: How to generate fractional-N clock ?
43378: 02/05/20: Re: virtex II : CLB with two clocks
43431: 02/05/21: Re: Shift register or state machine
43437: 02/05/21: Re: Synchronous Single Clock Designs
43442: 02/05/21: Re: button & 3 LED's
43469: 02/05/21: Re: What properties has FPGA?
43544: 02/05/23: Re: How to generate fractional-N clock ?
43577: 02/05/24: Re: Small FIFOs in Spartan
43642: 02/05/28: Re: Frequency synthesiser
43646: 02/05/28: Re: Frequency synthesiser
43652: 02/05/28: Re: Frequency synthesiser
43655: 02/05/28: Re: Frequency synthesiser
43659: 02/05/28: Re: Frequency synthesiser
43665: 02/05/28: Re: Frequency synthesiser
43676: 02/05/29: Re: Frequency synthesiser
43693: 02/05/29: Re: Frequency synthesiser
43706: 02/05/30: Re: Frequency synthesiser
43723: 02/05/31: Re: Frequency synthesiser
43733: 02/05/31: Re: Do I have metastability issues?
43739: 02/05/31: Re: LFSR with 2^n instead of (2^n)-1
43758: 02/05/31: Re: LFSR with 2^n instead of (2^n)-1
43816: 02/06/03: Re: divide by 5
43832: 02/06/03: Re: divide by 5
43855: 02/06/04: Re: divide by 5
43865: 02/06/04: Re: VirtexE DLL Output clock phase
43891: 02/06/05: Re: OFFSET timing contraints
43893: 02/06/05: Re: Do I have metastability issues?
43897: 02/06/05: Re: virtex 2 : init values
43929: 02/06/06: Re: Do I have metastability issues?
43967: 02/06/07: Re: Help - Xilinx SRL16 primitive gives 'X's in simulation
43981: 02/06/07: Re: OFFSET timing contraints
43982: 02/06/07: Re: Do I have metastability issues?
43985: 02/06/07: Re: Do I have metastability issues?
43988: 02/06/08: Re: Do I have metastability issues?
44004: 02/06/09: Re: OFFSET timing contraints
44008: 02/06/09: Re: Inserting flops to help timing (in Virtex-II)
44031: 02/06/10: Re: Power supply caps on PCB
44037: 02/06/10: Re: synthesis query: Xilinx + Synplify
44043: 02/06/10: Re: synthesis query: Xilinx + Synplify
44065: 02/06/11: Re: synthesis query: Xilinx + Synplify
44068: 02/06/11: Re: 20,000 gates?
44069: 02/06/11: Re: Busses & permutations
44070: 02/06/11: Re: surely this is mad? (clock rate issues)
44073: 02/06/11: Re: 20,000 gates?
44076: 02/06/11: Re: synthesis query: Xilinx + Synplify
44085: 02/06/11: Re: Problems initialising an FPGA - SPARTAN II
44086: 02/06/11: Re: synthesis query: Xilinx + Synplify
44095: 02/06/11: Re: fpga and ultra highspeed counters
44129: 02/06/12: Re: Digital FM demodulator in FPGA-continue
44139: 02/06/12: Re: synthesis query: Xilinx + Synplify
44140: 02/06/12: Re: Power supply caps on PCB
44148: 02/06/12: Re: Digital FM demodulator in FPGA-continue
44149: 02/06/12: Re: MAP problem with RLOC'ed macros
44151: 02/06/12: Re: MAP problem with RLOC'ed macros
44189: 02/06/13: Re: MAP problem with RLOC'ed macros
44190: 02/06/13: Re: MAP problem with RLOC'ed macros
44191: 02/06/13: Re: Busses & permutations
44197: 02/06/13: Re: Power supply caps on PCB
44209: 02/06/13: Re: Power supply caps on PCB
44216: 02/06/14: Re: MAP problem with RLOC'ed macros
44238: 02/06/14: Re: BGA package
44239: 02/06/14: Re: MAP problem with RLOC'ed macros
44245: 02/06/14: Re: Power supply caps on PCB
44305: 02/06/17: Re: Power supply caps on PCB
44317: 02/06/17: Re: Which Synthesis tool for XILINX
44319: 02/06/17: Re: Which Synthesis tool for XILINX
44321: 02/06/17: Re: Internal oscillator in CPLD?
44329: 02/06/17: Re: Internal oscillator in CPLD?
44358: 02/06/18: Re: Which Synthesis tool for XILINX
44460: 02/06/20: Re: How to generate a valid EDIF netlist?
44564: 02/06/23: Re: CLK/2
44595: 02/06/24: Re: virtex2 : ALT_VRP / ALT_VRN
44680: 02/06/26: Re: why not pipeline by default?
44791: 02/07/01: Re: combine the Verilog code
44831: 02/07/02: Re: Virtex II - Assigning Pins before routing?
44966: 02/07/08: Re: Are these design guideline safe ?
44988: 02/07/08: Xilinx adder RLOCs
45006: 02/07/09: Re: LUT and Xilinx Distributed SelectRam
45011: 02/07/09: Re: Xilinx adder RLOCs
45014: 02/07/10: Re: Xilinx adder RLOCs
45040: 02/07/10: Re: LUT and Xilinx Distributed SelectRam
45042: 02/07/10: Re: DPLL
45052: 02/07/10: Re: How to locate the combinational loop in RTL source
45076: 02/07/11: Re: Using DLL's for 90 Degree Phase Shift
45083: 02/07/12: Xilinx RPMs before Virtex-II
45149: 02/07/13: Re: Accurate Oscillator
45158: 02/07/14: Re: What proportion of an FPGA's configuration data is used for routing?
45248: 02/07/17: Re: LVDS interface cable recommendation sought
45266: 02/07/17: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45268: 02/07/17: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45279: 02/07/17: Re: problem porting sync write, async read RAM to Xilinx...
45437: 02/07/23: Re: xilinx v ti
45446: 02/07/24: Re: delay pipes in verilog for spartan IIe?
45452: 02/07/23: Re: How to implement efficient wide word comparator?
45467: 02/07/24: Re: delay pipes in verilog for spartan IIe?
45468: 02/07/24: Re: delay pipes in verilog for spartan IIe?
45478: 02/07/24: Re: 8bit Magnitude Comparator
45494: 02/07/24: Re: 8bit Magnitude Comparator
45527: 02/07/25: Re: hold time
45528: 02/07/25: More: How to implement efficient wide word comparator?
45529: 02/07/25: Re: LVDS interface cable recommendation sought
45534: 02/07/25: Re: hold time
45559: 02/07/26: Re: logic elements v/s logic cells
45563: 02/07/26: Re: logic elements v/s logic cells
45584: 02/07/27: Re: logic elements v/s logic cells
45655: 02/07/30: Re: Impedance Measureing
45708: 02/08/02: Re: Safe design speed
45731: 02/08/02: Re: spartan i/o
45748: 02/08/03: Re: About CMUcam Vision Sensor
45984: 02/08/13: Re: capacitance
46047: 02/08/15: Re: Resetting Spartan II FPGA
46087: 02/08/16: Re: CLOCK DLL IN SPARTAN2E Timing question
46293: 02/08/24: Re: Help for Schematic Components
46381: 02/08/27: Re: Any FSM optimizer?
46411: 02/08/28: Re: Any FSM optimizer?
46498: 02/09/01: Re: Virtex/E/2/2P area efficient addmux, reiterating PAR timing modeler enhancement request
46499: 02/09/01: Re: Multiplexing a tristate bus?
46541: 02/09/02: Re: synthesizing hard coded numbers
46559: 02/09/03: Re: Logic on Virtex CLB, what's the YB and XB used for?
46569: 02/09/03: Re: Logic on Virtex CLB, what's the YB and XB used for?
46681: 02/09/05: Re: why the need for HIGH speed design?
46683: 02/09/05: Re: Question for Verilog
46684: 02/09/05: Re: MAP problem: Trivial RPM fails
46697: 02/09/06: Re: What's wrong with clearLogic?
46719: 02/09/06: Re: Performance degradation when put on an FPGA ?
46743: 02/09/06: Re: why the need for HIGH speed design?
46836: 02/09/10: Re: FPGA comes with a DAC?
46913: 02/09/11: Re: Virtex/E/2/2P area efficient addmux, reiterating PAR timing modeler
46951: 02/09/12: Re: Xilinx TBUFs
47063: 02/09/16: Re: Question about Virtex-II DCM's jitter
47081: 02/09/16: Re: Multiple divide by 10
47103: 02/09/17: Re: Multiple divide by 10
47110: 02/09/18: Re: termination of JTAG pins
47349: 02/09/24: Re: Xilinx: Marking some latches for pass-thru timing
47432: 02/09/25: Re: Clock balancing in DDR SDRAM design
47434: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
47495: 02/09/27: Re: Looking for a dead Virtex
47553: 02/09/28: Re: Block Ram maximum speed
47847: 02/10/05: Re: DDS in PLD?
47849: 02/10/05: Re: DCM outputs skew question
48095: 02/10/11: Re: Sync Reset without clocks
48165: 02/10/12: Re: Sync Reset without clocks
48166: 02/10/12: Re: programming the FPGA by a microcontroller
48167: 02/10/12: Re: FPGA breadboard with a SmartMedia Card to store the bit file.
48272: 02/10/15: Re: Sync Reset without clocks
48309: 02/10/15: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48320: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48604: 02/10/21: Re: Newbie Questions - Jan Gray XSOC
48664: 02/10/22: Re: Decoupling BF957 Virtex II package
48691: 02/10/22: Re: Newbie Questions - Jan Gray XSOC
49153: 02/11/02: Re: Asynchronous clock enable with stable data
49357: 02/11/10: Re: VersaRing
49469: 02/11/13: Re: How to disable IOB register packing?
49581: 02/11/15: Re: FPGA board random error
49833: 02/11/22: Re: "new" Xilinx IOB timing paramter "Tiotp"
49834: 02/11/22: Re: Spartan IIe - DLL Max Input Clock Frequency
49946: 02/11/26: Re: Timing with ISE5.1i
49947: 02/11/26: Re: Fast Digital Synthesis Generator
49949: 02/11/26: Re: Frequency multiplier with digital h/w
49993: 02/11/27: Re: Fast Digital Synthesis Generator
49994: 02/11/27: Re: count based Frequency generator
50028: 02/11/28: Re: count based Frequency generator
50110: 02/12/02: Re: question about series termination resistors and VIAS
50149: 02/12/03: Re: block and distributed RAM
50261: 02/12/06: Re: series termination question
50303: 02/12/08: Re: Virtex archtecture question
50522: 02/12/12: Re: When to use CLKDLL vs. DCM in Virtex devices
50524: 02/12/12: Re: question about fft vs. cross corelation in fpga
51233: 03/01/07: Re: dualport ram instantiation in Spartan IIE
51257: 03/01/09: Re: 4-bit excess-3 counter with parallel load
51313: 03/01/10: Re: Spartan-2 reset: sync or async?
51424: 03/01/13: Re: Bidirectional Digital Switch in CPLD ?
51490: 03/01/14: Re: Open FPGA please!
51717: 03/01/20: Re: Parsing Xilinx Timing Reports
51863: 03/01/23: Re: dualport ram instantiation in Spartan IIE
51930: 03/01/26: Re: Extending a Virtex-II block RAM?
51931: 03/01/26: Re: registered bi-directional IOB?
51932: 03/01/26: Re: Why so many pins?
51956: 03/01/27: Re: Carry Logic propagation delay
51993: 03/01/28: Re: Clock Feedback for DDR-SDRAM (XApp200)
51997: 03/01/28: Re: Carry Logic propagation delay
52137: 03/02/02: Re: Static Timing Analysis
52136: 03/02/02: Re: Xilinx SwitchBox Structure
52264: 03/02/05: Re: Help needed
52265: 03/02/05: Re: Xilinx ISE optimization
52310: 03/02/06: Re: Clock Enables
52372: 03/02/07: Re: Divide clock frequency by 1.5: output duty cycle is not 50%
52374: 03/02/07: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
52388: 03/02/07: Re: low pass FIR filter in FPGA
52420: 03/02/08: Re: Overclock Xilinx Coolrunner 2 ?
52468: 03/02/11: Fast BlockRAM updates
52484: 03/02/11: Re: Fast BlockRAM updates
52560: 03/02/13: Re: Coolrunner II I/O speeds?
52661: 03/02/18: Re: PCB Design for a Xilinx Spartan-II FPGA
52897: 03/02/25: Re: help me figure out this problem?
53028: 03/02/28: Re: 10 MHz Clock out of 30 MHz
53138: 03/03/04: Re: Newbie: Help
53299: 03/03/10: Re: Static Tming Analysis
53314: 03/03/10: Re: Using divided clock
53847: 03/03/25: Re: Programming fpga
53858: 03/03/25: Re: Permanent Local Damage to FPGA
54032: 03/03/31: Re: connecting 2 FPGAs
54296: 03/04/07: Re: Spartan-IIE pinout spreadsheet?
54349: 03/04/08: Re: Constraints for high speed I/O signals.
54356: 03/04/08: Clock Doubled domain
54445: 03/04/10: Re: Balanced Presentation
54524: 03/04/12: Re: Clock Doubled domain
54653: 03/04/15: Re: Clock Doubled domain
54748: 03/04/17: Re: Clock Doubled domain
54770: 03/04/17: Re: spartan2e vs cyclone
54976: 03/04/23: Re: Problem : Simulating SRL16 with webpack 5.2 and modelsim 5.6e starter
55053: 03/04/25: Re: Large adder placement / synthesis
55054: 03/04/25: Re: Challenge: (n mod 3) in hardware???
55063: 03/04/25: Re: Xilinx has released SpartanIII
55087: 03/04/25: Re: Altera Flex 8K not holding configuration after power down.
55107: 03/04/26: Re: visualising a shift register using an LUT
55187: 03/04/29: Re: general: vhdl
55188: 03/04/29: Re: Two RAMs in one slice
55369: 03/05/05: Re: buffering
55402: 03/05/06: Re: PLL chips
55883: 03/05/22: Re: Asynchronous State Machines and HDLs
56340: 03/06/03: Re: FPGA's an Flash
56625: 03/06/10: Re: Shift registers
56851: 03/06/17: Re: XST verilog problem
57002: 03/06/20: Re: No longer talking about power consumption....
57257: 03/06/26: Re: Free PAL synth tools (ABEL, PALASM, VHDL, etc.)?
57258: 03/06/26: Re: Everything need a reset?
57346: 03/06/28: Re: Configure an FPGA from the PCs Parallel port. A solution.
57560: 03/07/02: Re: Xilinx Methodology Questions : Unconstrained Paths and DLL output phase alignment.
57561: 03/07/02: Re: Why not DDR in FPGAs?
57806: 03/07/07: Re: Pulse stretching
57848: 03/07/08: Re: phase noise in NCO
57873: 03/07/09: Re: phase noise in NCO
58023: 03/07/12: Re: VIRTEX switching IO voltage 3.3V / 2.5V
58066: 03/07/14: Re: Post-fit simulation question
58067: 03/07/14: Re: phase noise in NCO
58156: 03/07/16: Re: Graduation Day: My first 4-layer PCB
58236: 03/07/17: Re: state machine generator
58263: 03/07/18: Re: Graduation Day: My first 4-layer PCB
58268: 03/07/18: Re: bit to rbt conversion
58388: 03/07/22: Re: Xilinx WebPack support "dual edge clock" ??
58403: 03/07/22: Re: FPGA Editor
58436: 03/07/23: Re: asynchronous FIFO
58816: 03/08/01: Re: DDS question. How to generate a square from a sine wave?
58818: 03/08/01: Re: PLL / DPLL phase question
59060: 03/08/07: Re: How to find the intersection of two vectors?
59395: 03/08/18: Re: Translate: Map
59405: 03/08/18: Re: DDFS question
59437: 03/08/19: Re: DDFS question
59446: 03/08/19: Re: DDFS question
59499: 03/08/20: Re: Synchronous FSM
59546: 03/08/21: Re: DCM vs state machine
59586: 03/08/22: Re: Question about slew rate for SpartanII using ISE5.1
59638: 03/08/25: Re: Thinking out loud about metastability
59808: 03/08/28: Re: Selecting between two clock signals
59856: 03/08/29: Re: pricing, cyclone or spartan
59952: 03/09/02: Re: Input comparator
60138: 03/09/05: Re: Disable Pull up
60426: 03/09/12: Re: Metatstable Modeling
60698: 03/09/19: Re: divide by on spartan3?
60773: 03/09/22: Re: Synchronous counter enable pulse length
60792: 03/09/22: Re: Synchronous counter enable pulse length
60894: 03/09/24: Re: Xilinx S3 I/O robustness question
60968: 03/09/26: Re: Reducing Clock Speed
60972: 03/09/25: Re: Reducing Clock Speed
61009: 03/09/26: Re: pullup on inputs
61010: 03/09/26: Re: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
61145: 03/09/29: Re: Counting ones
61219: 03/09/30: Re: pullup on inputs
61246: 03/09/30: Digesting runs of ones or zeros "well"
61299: 03/10/01: Re: Digesting runs of ones or zeros "well"
61363: 03/10/02: Re: Digesting runs of ones or zeros "well"
61364: 03/10/02: Re: Digesting runs of ones or zeros "well"
61365: 03/10/02: Re: Digesting runs of ones or zeros "well"
61367: 03/10/02: Re: Digesting runs of ones or zeros "well"
61397: 03/10/02: Re: Digesting runs of ones or zeros "well"
61424: 03/10/03: Re: Digesting runs of ones or zeros "well"
61463: 03/10/04: Re: Digesting runs of ones or zeros "well"
61464: 03/10/04: Re: Digesting runs of ones or zeros "well"
61477: 03/10/05: Re: Digesting runs of ones or zeros "well"
61520: 03/10/06: Re: Digesting runs of ones or zeros "well"
61539: 03/10/06: Re: Timing from 1x to 2x and back
61541: 03/10/06: Re: Digesting runs of ones or zeros "well"
61543: 03/10/06: Re: Digesting runs of ones or zeros "well"
61590: 03/10/07: Re: More RPM / RLOC fun
61665: 03/10/08: Re: Xilinx DCMs, DDR, CLK0, and CLK180
61720: 03/10/09: Re: Placing FF's Relative to RAMB4s (xilinx)
61729: 03/10/09: Re: Digesting runs of ones or zeros "well"
61786: 03/10/10: Re: Counting ones
61787: 03/10/10: Re: Counting ones
61821: 03/10/13: Re: ISE6.1i RPM's, Multipliers and grids
61832: 03/10/13: Re: mp3 project
61861: 03/10/14: Re: ISE6.1i RPM's, Multipliers and grids
61945: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
62260: 03/10/23: Re: Another strage timing problem
62270: 03/10/23: Re: Are clock and divided clock synchronous?
62279: 03/10/23: Re: Searching for 802.11a phy IP
62311: 03/10/25: Re: Searching for 802.11a/g implementations
62389: 03/10/28: Re: Are clock and divided clock synchronous?
62435: 03/10/29: Re: Memory for FPGA based LCD Driver/Controller
62797: 03/11/07: Re: FPGA & handling reset of a logic block while running
62873: 03/11/10: Re: FPGAs and DRAM bandwidth
62938: 03/11/11: Re: Transforming vector position to binary value
62940: 03/11/11: Re: Layout examples
62941: 03/11/11: Re: Implementing a very fast counterin VirtexII
62947: 03/11/11: Re: Layout examples
63047: 03/11/13: Re: Xilinx Virtex2 tristate support
63051: 03/11/13: Re: Transforming vector position to binary value
63195: 03/11/17: Re: SRL16 as synchronizer
63241: 03/11/18: Re: SRL16 as synchronizer
63395: 03/11/20: Re: avoiding GCLK
63661: 03/11/27: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
63844: 03/12/05: Re: Dual-port and single-port BlockRAM instantiation
63885: 03/12/07: Re: Skew between the output of a DCM ?
63945: 03/12/09: Re: BUFT resources in Spartan II
63980: 03/12/10: Re: Soldering of FPGAs
64479: 04/01/05: Re: is this a good idea
64635: 04/01/09: Re: min propagation delay in xilinx cpld
65034: 04/01/19: Re: Which version of ISE Webpack has FPGA Editor on it?
65742: 04/02/05: Re: A small clock synchronization challenge with Virtex E
65743: 04/02/05: Re: The fastest interface between FPGA's
65799: 04/02/06: Re: How may I restrain the P&R to only a small area...
65876: 04/02/09: Re: Pricing, 101
65880: 04/02/09: Re: Pricing, 101
65881: 04/02/09: Re: A small clock synchronization challenge with Virtex E
65890: 04/02/09: Re: Virtex 2 Fastest MUX performance
66184: 04/02/13: Re: Peter's 1Hz-640MHz Synth project
66596: 04/02/23: Re: Why does Xilinx keep saying LVPECL_2.5 and _3.3V are identical?
67265: 04/03/09: Re: Reg..How to use BUFGMUX in Spartan 2 family
67274: 04/03/09: Re: sorting need help as soon as possible
67353: 04/03/10: Re: A hardware question?
67825: 04/03/19: Re: Spartan III availability
67950: 04/03/23: Re: Virtex-4
68025: 04/03/24: Re: Bus width between registers in IIR
68028: 04/03/24: Re: Time measurement with Xilinx Spartan-3 - Help
68055: 04/03/25: Re: Clock divider preserving duty-cycle ?
68077: 04/03/25: Re: Clock divider preserving duty-cycle ?
68105: 04/03/26: Re: Clock divider preserving duty-cycle ?
68332: 04/04/01: Re: REGISTER as a COUNTER in hardware
68346: 04/04/01: Re: does V2p support tristate
68488: 04/04/06: Re: Fast Carry Chains in Xilinx SpartanII FPGA's
68500: 04/04/06: Re: Fast Carry Chains in Xilinx SpartanII FPGA's
68540: 04/04/07: Re: how to get XST to infer 8:1 mux or just hard code it?
68579: 04/04/08: Re: how to get XST to infer 8:1 mux or just hard code it?
68664: 04/04/13: Re: Layout problem
68703: 04/04/14: Re: DDS-Based PLL
68750: 04/04/16: Re: DDS-Based PLL
68759: 04/04/16: Re: DDS-Based PLL
68825: 04/04/19: Re: Image-reject IF downmixing
68941: 04/04/22: Re: Issues on Shift Register in a Clockless UART
69002: 04/04/24: Re: multiply by 1.5 in xilinx Virtex2 FPGA
69123: 04/04/27: Re: CPLD input
69151: 04/04/28: Re: Stupid question
69153: 04/04/28: Re: Clock frequency converter from 1.544MHz to 2.048MHz (or multiples)
69157: 04/04/28: Re: Comment on my code style
69258: 04/05/03: Re: Cheap SRAM?
69278: 04/05/04: Re: Not enough sites to place MULT18X18?
69507: 04/05/12: Re: Easypath
69662: 04/05/17: Re: Clock Generation from Asynchronous Data Stream
69697: 04/05/18: Re: Atmel Zigbee solutions
69706: 04/05/18: Re: Meaning of output value?
69717: 04/05/18: Re: Webpack 6.1, ISEexamples, and CoreGen
69949: 04/05/25: Re: Driving fpga pin out over long cable
70167: 04/06/07: Re: Quick question
70215: 04/06/09: Re: Quick question
70293: 04/06/11: Re: Virtex4: I don't understand their thinking....
70372: 04/06/14: Re: RAM in Altera EABs and Xilinx Block Rams
70468: 04/06/17: Re: Synplify_pro
70491: 04/06/17: Re: compressing Xilinx bitstreams
70582: 04/06/21: Re: Spartan/SpartanXL Device Selection
70583: 04/06/21: Re: 8 ch countdown timer - doable in a CPLD?
70584: 04/06/21: Re: Inferring dual-port RAM from VHDL with BlockRAM
70600: 04/06/21: Re: RAM in Altera EABs and Xilinx Block Rams
70628: 04/06/22: Re: Spartan/SpartanXL Device Selection
70690: 04/06/23: Re: Division in Xilinx
70718: 04/06/24: Re: Divided by 11 in VHDL
70854: 04/06/30: Re: FPGA with fully asynchronous RAM
70952: 04/07/02: Re: Does Xilinx have the worst web site on the planet?
71072: 04/07/07: Re: Place & route question in Xilinx...
71095: 04/07/07: Re: RC Servo PWM Digital Capture in a Xilinx xc9500 CPLD?
71759: 04/07/29: Re: Spartan 2E FG456 package file
71787: 04/07/30: Re: 1GHz FPGA counters
72061: 04/08/06: Re: Comparing Quality of Results of FPGA CAD Tools
72133: 04/08/09: Re: Now I am really confused!
72134: 04/08/09: Re: Now I am really confused!
72221: 04/08/11: Re: DDR Lines on FPGA : Physical considerations
72227: 04/08/11: Re: Request for 28 BIT ADDER maximum clock rates for Virtex II FPGAs
72723: 04/08/30: Re: Counter counting on both clock edges.
73698: 04/09/28: Re: fast adder and equal
73709: 04/09/28: Re: Xilinx Read First Write First
73713: 04/09/28: Re: Xilinx FIFOs
73714: 04/09/28: Re: Xilinx Read First Write First
73777: 04/09/29: Re: luts are optimized away
73805: 04/09/29: Re: Pricing info for Synplify Pro Xilinx...
73877: 04/09/30: Re: Spartan-3 VCCIO ramp up time
72886: 04/09/07: Re: how to get the data from ADC
72934: 04/09/08: Re: vhdl error ?? - [code included]
72946: 04/09/08: Re: vhdl error ?? - [code included]
73119: 04/09/14: Re: spartan-3 I/O timing
73150: 04/09/14: Re: spartan-3 I/O timing
73204: 04/09/15: Re: Looking for a Design for a Small FPGA Board
73242: 04/09/16: Re: VHDL Design for running sorter
73279: 04/09/17: Re: VHDL Design for running sorter
73291: 04/09/17: Re: Virtex 4 released today
73361: 04/09/20: Re: USER RESET in XILINX FPGA
73362: 04/09/20: Re: Looking for a Design for a Small FPGA Board
73408: 04/09/21: Re: Stratix II vs. Virtex 4 - power
73409: 04/09/21: Re: Stratix II vs. Virtex 4 - availability & fab partnership
73412: 04/09/21: Re: Mr. Greenfield, spare us the propaganda !
73493: 04/09/22: Re: spartan-3 sram
73551: 04/09/23: Re: equal to zero
73552: 04/09/23: Re: MUXCY and XORCY local outputs (LO)
73581: 04/09/24: Re: Mr. Greenfield, spare us the propaganda !
74971: 04/10/22: Re: Spartan 3 - Internal busses & tristate ?
75338: 04/11/02: Re: FPGA & DDR-SDRAM
74127: 04/10/04: Re: Removing set/reset logic for shift register (HDL ADVISOR )
74131: 04/10/04: Re: FPGA vs ASIC area
74137: 04/10/04: Re: question on interfacing FPGA with a sensor
74151: 04/10/04: Re: FPGA vs ASIC area
74345: 04/10/08: Re: Xilinx DCM and Timing Constraints
74346: 04/10/08: Re: DCM and CLKFX - is this allowed?
74352: 04/10/08: Re: Xilinx DCM and Timing Constraints
74362: 04/10/08: Re: Xilinx DCM and Timing Constraints
74480: 04/10/12: Re: Reading RAM while
74533: 04/10/13: Re: HDL-Models of CLB/Slice
74539: 04/10/13: Re: 1.2V
74576: 04/10/14: Re: Where to buy cheap MAXII CPLD?
74587: 04/10/14: Re: Metastability pipeline causes bad juju
74595: 04/10/14: Re: Metastability pipeline causes bad juju
74632: 04/10/15: Re: spartan 3 on 4 layers
74669: 04/10/16: Re: BCD to bin convertor
74909: 04/10/21: Re: Async reset
74910: 04/10/21: Re: Anyone routing signals between balls in FBGA?
74912: 04/10/21: Re: Virtex-4 Slower than V2Pro?
75365: 04/11/03: Re: FPGA & DDR-SDRAM
75372: 04/11/03: Re: comparator problem
75554: 04/11/09: Re: Accessing rows in bank
76266: 04/11/29: Re: How to subscribe to the newsgroup comp.arch.fpga
76275: 04/11/29: Re: Xilinx and Altera -- maximum total bitrate for high-speed serial I/O
76284: 04/11/29: Re: lowest-cost FPGA
76317: 04/11/30: Re: 99% Utilisation !
76318: 04/11/30: Re: Adder Tree Placement
76565: 04/12/06: Re: how to speed up my accumulator ??
76591: 04/12/06: Re: how to speed up my accumulator ??
76636: 04/12/08: Re: how to speed up my accumulator ??
76732: 04/12/09: Re: how to speed up my accumulator ??
76927: 04/12/16: Re: Digital clock synthesis
76970: 04/12/17: Re: Digital clock synthesis
76976: 04/12/17: Re: Digital clock synthesis
77886: 05/01/19: Re: video decoder for altera dev. board
77891: 05/01/19: Re: Very Stupid XST verilog synthesis question...
77949: 05/01/21: Re: Xilinx Sum in VHDL
77950: 05/01/21: Re: Xilinx Sum in VHDL
77977: 05/01/21: Re: Xilinx Sum in VHDL
78519: 05/02/02: Re: Virtex II Slice Design - ARGH!
78558: 05/02/03: Re: Virtex II Slice Design - ARGH!
78752: 05/02/07: Re: ambiguous number of BLOCK RAM in SPARTAN3
78828: 05/02/08: Re: Input Timing Specification
79033: 05/02/11: Re: Variable phase shift on Spartan3 DCMs. Does it work?
79041: 05/02/11: Re: Variable phase shift on Spartan3 DCMs. Does it work?
79108: 05/02/14: Re: clock division / multiplication in xilinx cpld
79131: 05/02/14: Re: Updated Stratix II Power Specs & Explanation
79220: 05/02/15: Re: Cyclone clock
79221: 05/02/15: Re: Updated Stratix II Power Specs & Explanation
79295: 05/02/16: Re: DNL and INL calculation
79417: 05/02/18: Re: Xilinx: Pitfalls of chaining DLLs
79434: 05/02/19: Re: Xilinx: Pitfalls of chaining DLLs
79634: 05/02/22: Re: virtex II register file
79636: 05/02/22: Re: hdl:lament
79808: 05/02/24: Re: The real performance leader: V4
79888: 05/02/25: Re: Virtex-4 performance, where is it?
79889: 05/02/25: Re: Can't create Bus-Tap in Xilinx' ECS
80500: 05/03/07: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
80583: 05/03/08: Re: Surge in S2? ~3 amperes at cold for a millisecond
80726: 05/03/10: Re: Xilinx vs Altera high-end solutions
80737: 05/03/11: Re: SPROM for Spartan II
80815: 05/03/11: Re: Over-Sampling
80980: 05/03/15: Re: Register file with LUTs in a SPARTAN3
81037: 05/03/16: Re: Xilinx webpack map/route questions
81038: 05/03/16: REPOST: Re: Xilinx webpack map/route questions
81090: 05/03/17: Re: Newbie: Slow FPGAs
81106: 05/03/17: Re: Newbie: Slow FPGAs
81373: 05/03/22: Re: Power Net Seminar Announcement
81510: 05/03/26: Re: divide by 2^n, n=21..37 ==> 3 Virtex Slices !!
81589: 05/03/28: Re: divide by 2^n, n=21..37 ==> 3 Virtex Slices !!
81599: 05/03/28: Re: divide by 2^n, n=21..37 ==> 3 Virtex Slices !!
81641: 05/03/29: Re: divide by 2^n, n=21..37 ==> 3 Virtex Slices !!
81658: 05/03/29: Re: newbie verilog question
81661: 05/03/29: Re: XC3000 non-recoverable lockup problem
81670: 05/03/29: Re: Dividing a 24 bit std_logic_vector by a decimal number
81676: 05/03/29: Re: Dividing a 24 bit std_logic_vector by a decimal number
81925: 05/04/04: Re: RAMB16_S9
81942: 05/04/04: Re: RAMB16_S9
81976: 05/04/05: Re: Structural vs Behavioral
81982: 05/04/05: Re: RAMB16_S9
82009: 05/04/05: Re: RAMB16_S9
82020: 05/04/05: Re: RAMB16_S9
82220: 05/04/08: Re: Clock Jitter on Xilinx FPGA
82221: 05/04/08: Re: FPGA Layout question
82586: 05/04/14: Re: Verilog problems with SelectRAM clocking within a finite state machine
82664: 05/04/15: Re: Hobby or job? (FPGA User's groups anyone?)
82838: 05/04/18: Re: Spartan 3E availability
83015: 05/04/21: Re: Bug in DDR template in Lattice FPGAs ?
83026: 05/04/21: Re: CAM for FPGA ...
83417: 05/04/29: Re: Sync + FIFO
83434: 05/04/29: Re: Sync + FIFO
83449: 05/04/29: Re: Sync + FIFO
83480: 05/04/30: Re: Sync + FIFO
83630: 05/05/04: Re: Gated clock problem
83632: 05/05/04: Re: I got it!
83654: 05/05/04: Re: Newbie VHDL/FPGA question
83704: 05/05/05: Re: I got it!
83767: 05/05/06: Re: Using capacitor to slow the rise time.
83886: 05/05/09: Re: Uart16550 can't receive data over 16byte a time
83895: 05/05/09: Re: dcm's for increasing clock speed
83978: 05/05/10: Re: Virtex4 running at 360Mhz DDR
83982: 05/05/11: Re: Virtex4 running at 360Mhz DDR
84046: 05/05/11: Re: Uart16550 can't receive data over 16byte a time
84407: 05/05/18: Re: CORDIC bit-serial vs. bit-parallel
84498: 05/05/19: Re: Bullshit Achieves Literary Status
84502: 05/05/19: Re: Bullshit Achieves Literary Status
84581: 05/05/21: Re: How to make a 1.44MHz clock?
84618: 05/05/23: Re: How to make a 1.44MHz clock?
84626: 05/05/23: Re: How to make a 1.44MHz clock?
84641: 05/05/23: Re: System Reset / GSR with Virtex 2 & Virtex 4
84685: 05/05/24: Re: System Reset / GSR with Virtex 2 & Virtex 4
84687: 05/05/24: Re: VHDL vs. Schematic Capture
84704: 05/05/24: Re: Altera Apex20KE PLL output jitter problem
84740: 05/05/25: Re: lpm_counter bug?
84773: 05/05/26: Re: What's the difference between Altera EPM1270T144C5 and EPM1270T144C5N?
84885: 05/05/31: Xilinx DDR output registers
84897: 05/05/31: Re: Implementing sin function in fpga
84903: 05/05/31: Re: Xilinx DDR output registers
84947: 05/06/01: Re: Xilinx DDR output registers
84984: 05/06/02: Re: Clock Generation : FPGA
85046: 05/06/03: Re: Clock Generation : FPGA
85066: 05/06/03: Re: Clock Generation : FPGA
85067: 05/06/03: Re: keypad scanner
85068: 05/06/03: Re: Clock Generation : FPGA
85151: 05/06/06: Re: 32/16 divider, ASIC(Designware) Vs Xilinx FPGA(Coregen)
85178: 05/06/06: Re: Clock Generation : FPGA
85275: 05/06/07: Re: Fast/low area Sorting hardware.
85307: 05/06/07: Re: faster Spartan III adder
85333: 05/06/08: Re: [Verilog] How to write a barrel shifter?
85432: 05/06/09: Re: faster Spartan III adder
85506: 05/06/10: Re: I2C clock stretching(XILINX reference design)
85542: 05/06/10: Re: pcb layers on BGAs Spartan-3
85600: 05/06/12: Re: Best Practices for Hardware Designers
85752: 05/06/15: Re: Auto pipeline logic??
85823: 05/06/16: Re: Availability of Spartan3
85829: 05/06/16: Re: Availability of Spartan3
85887: 05/06/17: Re: AbusivepPricing information in marketing publications
85889: 05/06/17: Re: comp.arch.fpga.<mfr>
86227: 05/06/23: Re: DC Offset removal in FPGA
86403: 05/06/27: Re: Poor PCI performance during read accesses (in master mode)
86595: 05/06/30: Re: Coverting .mcs file to .bit file
86834: 05/07/07: Re: about fast adder
86996: 05/07/12: Re: Unrolled Pipeline Implementation
87085: 05/07/14: Re: Doubts on Xilinx FPGA
87086: 05/07/14: Re: Modulo division in Verilog
87087: 05/07/14: Re: Virtex 300: what could cause pin to short?
87096: 05/07/15: Re: Modulo division in Verilog
87113: 05/07/15: Re: Doubts on Xilinx FPGA
87114: 05/07/15: Re: Modulo division in Verilog
87136: 05/07/16: Re: Doubts on Xilinx FPGA
87226: 05/07/19: Re: Ones Count 64 bit on Xilinx in VHDL
87261: 05/07/20: Re: Design is too large for the device! xc3s400
87262: 05/07/20: Re: Ones Count 64 bit on Xilinx in VHDL
87293: 05/07/20: Re: Ones Count 64 bit on Xilinx in VHDL
87913: 05/08/03: Re: Doubts on Xilinx FPGA
88600: 05/08/23: Re: FPGA Development Board Wish List
88605: 05/08/23: Re: FPGA Development Board Wish List
88734: 05/08/26: Re: Issues with Synplify Pro 7.7 synthesis
88822: 05/08/29: Re: CPLD Jitter
88825: 05/08/29: Re: Array of slope A/Ds in FPGA?
88827: 05/08/29: Re: CPLD Jitter
88829: 05/08/29: Re: Array of slope A/Ds in FPGA?
88975: 05/09/01: Re: current!
88976: 05/09/01: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
88977: 05/09/01: Re: A strange behavior
89002: 05/09/02: Re: Multidimensional port.
89003: 05/09/02: Re: CPLD - SimuCAD S/W CD
89004: 05/09/02: Re: current!
89009: 05/09/02: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
89029: 05/09/03: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
89040: 05/09/03: Re: Spartan 3 Ram Instantiation
89041: 05/09/03: Re: SI considerations for single chip memory configurations
89060: 05/09/04: Re: Logic??
89096: 05/09/05: Re: Spartan 3 Ram Instantiation
89097: 05/09/05: Re: I2C "SCL" line problem
89231: 05/09/08: Re: Spartan 3 Ram Instantiation
89319: 05/09/12: Re: reducing the number of IOBS in a design
89374: 05/09/13: Re: FIFO design using Virtex-II block ram..
89410: 05/09/14: Re: CPU benchmark for Xilinx PAR
89493: 05/09/16: Re: DCM question
89641: 05/09/21: Re: Count "1" bit in bit stream
89873: 05/09/28: Re: Sythesis software for Virtex-4
90095: 05/10/04: Re: How to make XST understand to pack mux(A,B,A+B) in a single level ?
90144: 05/10/05: Re: How to make XST understand to pack mux(A,B,A+B) in a single level ?
90151: 05/10/05: Re: How to make XST understand to pack mux(A,B,A+B) in a single level ?
90378: 05/10/11: Re: How to Reduce Interconnects (VDD and VSS)
90426: 05/10/12: Re: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4
90483: 05/10/14: Re: How to Reduce Interconnects (VDD and VSS)
90485: 05/10/14: Re: How to Reduce Interconnects (VDD and VSS)
90496: 05/10/14: Re: How to Reduce Interconnects (VDD and VSS)
90660: 05/10/18: Re: Xilinx USB cable
90662: 05/10/18: Re: Carry Chain Design
90670: 05/10/18: Re: Xilinx USB cable
90673: 05/10/18: Re: Xilinx USB cable
90678: 05/10/18: Re: Carry Chain Design
90692: 05/10/19: Re: using i2c core
90712: 05/10/19: Re: using i2c core
90750: 05/10/20: Re: using i2c core
90790: 05/10/21: Re: using i2c core
90878: 05/10/24: Re: verilog code
90891: 05/10/24: Re: using i2c core
90984: 05/10/26: Re: state machine with 2 clock's
90986: 05/10/26: Re: state machine with 2 clock's
91158: 05/10/31: Re: Integrator
91255: 05/11/02: Re: FPGA : PCI-CORE
91263: 05/11/02: Re: FPGA : PCI-CORE
91274: 05/11/02: Re: FPGA : PCI-CORE
91282: 05/11/02: Re: FPGA : PCI core needed
91395: 05/11/04: Re: Anybody understand this ISE 7.1 error, and what to do about it???
91410: 05/11/05: Re: Anybody understand this ISE 7.1 error, and what to do about it???
91432: 05/11/06: Re: Anybody understand this ISE 7.1 error, and what to do about it???
91460: 05/11/07: Re: Adder synthesis
91495: 05/11/07: Re: Spartan-3E starter kit
91547: 05/11/08: Re: Wirelength information from Xilinx ISE 6.1
91941: 05/11/17: Re: Data recovery (XAPP224)
92011: 05/11/19: Re: Oh no! Resets Again? Yes, but it could be important.
92115: 05/11/22: Re: Disabling Xilinx clock enable usage...
92362: 05/11/28: Re: ChipScope 7.1 w/ EDK 7.1 data port bit ordering issue
92567: 05/12/01: Re: Virtex 4 FIFO16 blocks - Corruption ?
92948: 05/12/09: Re: No, not FIFOs again...
93029: 05/12/12: Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?)
93099: 05/12/13: Re: fiddling directly with LUT bits on Xilinx
93218: 05/12/16: Re: Inverter Chain Synthesis Problem
93241: 05/12/16: Re: Inverter Chain Synthesis Problem
93242: 05/12/16: Re: Avnet hav2 s3e starter kit?
93260: 05/12/16: Re: Avnet hav2 s3e starter kit?
93349: 05/12/20: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93425: 05/12/21: Re: Place and Route Algorithms: where's the fat?
93438: 05/12/22: Re: Place and Route Algorithms: where's the fat?
93748: 05/12/29: Re: S3e starter kits available
93863: 06/01/02: Re: Start up condition of flip flops in FPGA?
93903: 06/01/03: Re: My design to big for the FPGA or not?
93940: 06/01/03: Re: S3e starter kits available
94034: 06/01/04: Re: CORDIC for digital downconversion
94090: 06/01/05: Re: Do you name your FPGA?
94088: 06/01/05: Re: Virtex2 I/O state in configure phase
94297: 06/01/09: Re: How to keep the design from Synplify or XST optimizing
94295: 06/01/09: Re: dma on fpga pci card
95754: 06/01/26: Re: dma on fpga pci card
94292: 06/01/09: Re: tcam implemented in fpga
94343: 06/01/10: Re: tcam implemented in fpga
94440: 06/01/11: Re: Yet Another Misleading Post from Austin, a Xilinx(R) Employee
94599: 06/01/14: Re: Don't even get me started on lead,
94598: 06/01/14: Re: how do I minimize the logic in this function?
94853: 06/01/18: Re: S3e slower than S3
94848: 06/01/18: Re: How to set Xilinx compiling parameters to get PCI setup time right
94954: 06/01/19: Re: Xilinx padding LC numbers, how do you feel about it?
95050: 06/01/20: Re: Quadrature Encoder ::
95090: 06/01/20: Re: need for a group FAQ?
95596: 06/01/24: Re: Irrelevant, stupid, racist, and worse.
95432: 06/01/23: Re: SSOs and Vcco on Spartan3
95597: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
95584: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
95528: 06/01/23: Re: Xilinx padding LC numbers, how do you really feel about it?
95589: 06/01/24: Re: Very OT: Americanized family names
95602: 06/01/24: Re: Verilog tutorial by John Sanguinetti
95886: 06/01/26: Re: DDR2 SDRAM controller
95888: 06/01/26: Re: Reverse Engineering or Modification?
95962: 06/01/27: Re: tristate to logic conversion
95985: 06/01/27: Re: tristate to logic conversion
96071: 06/01/29: Re: tristate to logic conversion
96100: 06/01/30: Re: tristate to logic conversion
95977: 06/01/27: Re: Impact 8.1 problems with non xilinx device in chain
95983: 06/01/27: Re: Impact 8.1 problems with non xilinx device in chain
96256: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
96550: 06/02/06: Re: VGA and framebuffer interface (Waste of BlockRAM)
96556: 06/02/06: Re: VGA and framebuffer interface (Waste of BlockRAM)
96605: 06/02/07: Re: Verilog 2's Complement Shifter
96606: 06/02/07: Re: why does speed grade effect VHDL program??
96607: 06/02/07: Re: input signals in ISE simulator
96723: 06/02/09: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest
96725: 06/02/09: Re: Need help with generating video patterns using VHDL
96764: 06/02/10: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest
96948: 06/02/14: Re: spartan-3e starter kit
96949: 06/02/14: Re: I2C and posedge sampling
97000: 06/02/14: Re: Need help with generating video patterns using VHDL
97154: 06/02/17: Re: Xilinx Tight packing : Map error, the tools don't get it ...
97157: 06/02/17: Re: what's would your requirments be for ESL (Electronic System Level) flows?
97168: 06/02/17: Re: equivalent time sampling
97203: 06/02/18: Re: equivalent time sampling
97209: 06/02/18: Re: equivalent time sampling
97217: 06/02/19: Re: equivalent time sampling
97256: 06/02/20: Re: Parameterized Comparator Verilog Code
97326: 06/02/20: Re: Implementing a two-modulus PLL divider in Altera Stratix II
97557: 06/02/24: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
97765: 06/02/27: Re: Virtex-4 RAMB16 relative placement
97769: 06/02/27: Re: tricks to make large PLAs fast?
97771: 06/02/27: Re: fpga to 5v ttl logic
97823: 06/02/28: Re: How do I make dual-port RAM from single port RAM?
97907: 06/03/01: Re: Pulse Shape in a functional simulation
97910: 06/03/01: Re: Pulse Shape in a functional simulation
97920: 06/03/01: Re: Pulse Shape in a functional simulation
97965: 06/03/02: Re: Help wanted
97977: 06/03/02: Re: Help wanted
97978: 06/03/02: Re: coregen on webpack 8.1
97981: 06/03/02: Re: How do I make dual-port RAM from single port RAM?
97987: 06/03/02: Re: Help wanted
98040: 06/03/03: Re: Simple ADS5273 -> Xilinx Interconnect Model
98067: 06/03/04: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
98071: 06/03/04: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
98108: 06/03/05: Re: How do I make dual-port RAM from single port RAM?
98157: 06/03/06: Re: Par error in Spartan-3
98231: 06/03/07: Re: Internal pull down on the FPGA.....
98336: 06/03/08: Re: using handles
98357: 06/03/08: Re: Shift Register synthesis??
98410: 06/03/09: Re: FIFO Simulation Oddities!
98413: 06/03/09: Re: FIFO Simulation Oddities!
98419: 06/03/09: Re: a problem with coolrunner CPLD (XC2C256) GCK0 pin
98455: 06/03/10: Re: FIFO Simulation Oddities!
98469: 06/03/10: Re: a problem with coolrunner CPLD (XC2C256) GCK0 pin
98470: 06/03/10: Re: for all those who believe in ASICs....
98477: 06/03/10: Re: (no subject)
98559: 06/03/12: Re: Question about multi write ports RAM in FPGA?
98566: 06/03/13: Re: Question about multi write ports RAM in FPGA?
98604: 06/03/13: Re: Question about multi write ports RAM in FPGA?
98673: 06/03/14: Re: for all those who believe in ASICs....
98724: 06/03/15: Re: Question about multi write ports RAM in FPGA?
98815: 06/03/16: Re: Measuring pulse width in ModelSim simulation without using cursors and writing the widths to a text file
98886: 06/03/17: Re: Urgent Help Needed!!!!!
98887: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
98889: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
98894: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
98910: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
98915: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
98938: 06/03/17: Re: Urgent Help Needed!!!!!
98948: 06/03/18: Re: Urgent Help Needed!!!!!
98950: 06/03/18: Re: for all those who believe in ASICs....and can't stop ranting
99000: 06/03/18: Re: for all those who believe in ASICs....but may soon stop ranting
99011: 06/03/18: Re: Spartan 3 Power Supply Design
99049: 06/03/19: Re: Virtex-4 BRAM control signal inversion
99050: 06/03/19: Re: PCI Configuration access and Target State Machine...
99051: 06/03/19: Re: Support software for XC3042
99078: 06/03/20: Re: FPGA FIR advice
99096: 06/03/20: Re: Urgent Help Needed!!!!!
99110: 06/03/20: Re: Urgent Help Needed!!!!!
99113: 06/03/20: Re: DDS
99114: 06/03/20: Re: DDS
99115: 06/03/20: Re: PCI Configuration access and Target State Machine...
99117: 06/03/20: Re: Instantiating addsub, comparators in Xilinx
99122: 06/03/20: Re: ignore thread
99124: 06/03/20: Re: PCI Configuration access and Target State Machine...
99289: 06/03/22: Re: Lattice FPGA
99290: 06/03/22: Re: Going from CLK1X to CLK2X.. really safe?
99312: 06/03/22: Re: Spartan2 and Spartan3 BlockRAMS Can they work thesame?
99314: 06/03/22: Re: Going from CLK1X to CLK2X.. really safe?
99377: 06/03/23: Re: Lattice FPGA
99646: 06/03/27: Re: deglitching a clock
99668: 06/03/28: Re: deglitching a clock
99676: 06/03/28: Re: spartan FPGA with PLCC package
99703: 06/03/28: Re: combinatorial always blocks + for-loops in XST
99709: 06/03/28: Re: combinatorial always blocks + for-loops in XST
99715: 06/03/28: Re: combinatorial always blocks + for-loops in XST
99732: 06/03/28: Re: combinatorial always blocks + for-loops in XST
99742: 06/03/28: Re: combinatorial always blocks + for-loops in XST
99873: 06/03/30: Re: USB Interface to Virtex-4
99960: 06/03/31: Re: deglitching a clock
100024: 06/04/01: Re: PCB Bypass Caps
100093: 06/04/03: Re: Discrete
100097: 06/04/03: Spartan3E data sheets
100144: 06/04/04: Re: PCB Bypass Caps
100168: 06/04/04: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
100230: 06/04/05: Re: Delay value for FDDRCPE in Virtex-II Pro FGPA
100231: 06/04/05: Re: Compressing DVI stream
100242: 06/04/05: LVDS in Cyclone-II
100247: 06/04/05: Re: initializing arrays with Verilog and XST
100249: 06/04/05: Re: LVDS in Cyclone-II
100273: 06/04/06: Re: LVDS in Cyclone-II
100274: 06/04/06: Re: LVDS in Cyclone-II
100375: 06/04/07: Re: what is architectural diffrence between block ram & distributed
100383: 06/04/07: Re: LVDS in Spartan-3E
100385: 06/04/07: Re: Infer dual-clock block RAM for Xilinx
100487: 06/04/10: Re: ROM resource sharing
100488: 06/04/10: Re: location constraint doubt
100493: 06/04/10: Re: Very basic question
100506: 06/04/10: Re: ROM resource sharing
100538: 06/04/11: Re: timing constraints ?
100539: 06/04/11: Re: want technical assistance in making toner chips
100540: 06/04/11: Re: Area Constraints in Xilinx
100541: 06/04/11: Re: reading vhdl files
100547: 06/04/11: Re: PCI speed.
100569: 06/04/12: Spartan3E readback, SPI programming
100574: 06/04/12: Re: Spartan3E readback, SPI programming
100579: 06/04/12: Re: Spartan3E readback, SPI programming
100586: 06/04/12: Re: Spartan3E readback, SPI programming
100588: 06/04/12: Re: Spartan3E readback, SPI programming
100590: 06/04/12: Re: virtex II and powerpc core
100591: 06/04/12: Re: Spartan3E readback, SPI programming
100593: 06/04/12: Re: Spartan3E readback, SPI programming
100611: 06/04/13: Re: Spartan3E readback, SPI programming
100612: 06/04/13: Re: PCB Stack
100629: 06/04/13: Re: Spartan 3E Starter Kit is finally here!
100636: 06/04/14: Re: humble suggestion for Xilinx
100643: 06/04/14: Re: PCB Stack
100727: 06/04/17: Re: How to apply timing constrains for large bus
100741: 06/04/17: Re: PLD610
100751: 06/04/17: Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!
100752: 06/04/17: Re: PLD610
100789: 06/04/18: Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!
100790: 06/04/18: Re: Implementation of cascadable shift register in virtex FPGA
100802: 06/04/18: Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!
100803: 06/04/18: Re: Spartan 3 chips in power up
100823: 06/04/18: Re: driving high speed ADC using an FPGA
100849: 06/04/19: Re: want technical assistance in making toner chips
100856: 06/04/19: Re: XST issues with loop code
100857: 06/04/19: Re: How is the max clock rate of a device fixed?
100863: 06/04/19: Re: Xilinx FPGA status after configuration.
100890: 06/04/20: For those looking for the Spartan3E starter board...
100897: 06/04/20: Re: fpga space estimate
100906: 06/04/20: Re: Multiple Independent Circuits on a Single FPGA
100938: 06/04/21: Re: Video circle generator
100953: 06/04/21: Re: CAM, TCAM in Stratix
100955: 06/04/21: Re: fpga space estimate
100959: 06/04/21: Re: Why Edge is required to read from Block RAM of V4
100961: 06/04/21: Re: fpga space estimate
101010: 06/04/24: Re: CAM, TCAM in Stratix
101026: 06/04/24: Re: regarding memories using megafunction wizard(altera)
101027: 06/04/24: Re: How to avoid this waring in ISE 8.1?
101030: 06/04/24: Re: Microblaze & Linux tools. (repost)
101031: 06/04/24: Re: CAM, TCAM in Stratix
101037: 06/04/24: Re: Heating problem of the CPLD
101038: 06/04/24: Re: How to avoid this waring in ISE 8.1?
101078: 06/04/25: Re: CAM, TCAM in Stratix
101086: 06/04/25: Re: Virtex 2 Config Times
101115: 06/04/25: Re: clock multiplication
101138: 06/04/26: Re: expanding multipliers, problem
101139: 06/04/26: Re: Spartan 3E Starter Board Question
101141: 06/04/26: Re: Async FPGA ~2GHz
101152: 06/04/26: Re: Async FPGA ~2GHz
101219: 06/04/27: Re: CLock Issue
101220: 06/04/27: Re: Xilinx PCI 64/32 bits IP
101227: 06/04/27: Re: CLock Issue
101243: 06/04/28: Re: Synplify is not translating xilinx template for block ram
101302: 06/04/28: Re: Pull up resistors on Spartan 3 mode pins
101339: 06/04/29: Re: Spartan 3 documentation confusing...
101372: 06/04/30: Re: Pull up resistors on Spartan 3 mode pins
101403: 06/04/30: Re: Pull up resistors on Spartan 3 mode pins
101406: 06/04/30: Re: Pull up resistors on Spartan 3 mode pins
101448: 06/05/01: Re: ERROR:iMPACT:1210 - '1':Boundary-scan chain test failed at bit position '1'
101468: 06/05/01: Re: Book Software for XC3190A?
101510: 06/05/02: Re: Spartan 3 documentation confusing...no more
101524: 06/05/02: Re: Spartan 3 documentation confusing...no more
101619: 06/05/04: Re: ports of multidimentional arrays in verilog.
101763: 06/05/05: Re: Xilinx 3s8000?
101764: 06/05/05: Re: Xilinx 3s8000?
101859: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
101894: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
101911: 06/05/08: Re: PCI Express and DMA
101915: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
101931: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
102028: 06/05/09: Re: Funky experiment on a Spartan II FPGA
102032: 06/05/09: Re: constraints for DDR bus with 133MHz write and 66Mhz read clocks
102043: 06/05/10: Re: constraints for DDR bus with 133MHz write and 66Mhz read clocks
102242: 06/05/12: Re: Multiple Write Port Register Files
102250: 06/05/12: Re: How to decide Fanout limit?
102251: 06/05/12: Re: How to check IOB register packing?
102290: 06/05/14: Re: How to decide Fanout limit?
102372: 06/05/15: Re: Virtex 5 announced and sampling ... and real!
102406: 06/05/15: Re: Virtex 5 announced and sampling ... and real!
102407: 06/05/15: Re: Virtex 5 announced and sampling
102566: 06/05/17: Re: DCM
102748: 06/05/19: Xilinx/Synplicity LUT Placement
102792: 06/05/21: Re: initial block processing in XST 8.1
102867: 06/05/22: Re: Building a board with Spartan 3 FPGA.
102870: 06/05/22: Re: Building a board with Spartan 3 FPGA.
102885: 06/05/22: Re: Building a board with Spartan 3 FPGA.
102938: 06/05/23: Re: FPGA delay generator
103029: 06/05/24: Re: FPGA delay generator
103156: 06/05/26: Re: Xilinx/Synplicity LUT Placement
103172: 06/05/27: Re: ISE sends sensitive information to Xilinx site!------ Only if
103173: 06/05/27: Re: Xilinx/Synplicity LUT Placement
103318: 06/05/31: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103319: 06/05/30: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103341: 06/05/31: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103342: 06/05/31: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103362: 06/05/31: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103493: 06/06/04: Re: Documentation miss? (sp3/xilinx)
103495: 06/06/04: Re: Documentation miss? (sp3/xilinx)
103812: 06/06/12: Re: Xilinx timing viloations
103848: 06/06/13: Re: Xilinx timing viloations
103865: 06/06/13: S3E Starter Kit webcast
104006: 06/06/16: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
104007: 06/06/16: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
104028: 06/06/16: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
104089: 06/06/19: Re: High speed differential to single ended
104090: 06/06/19: Re: --.-Low Cost High quality pcb prototype and Assembly manufacturer(CHINA).
104111: 06/06/19: Re: High speed differential to single ended
104329: 06/06/23: Re: Spartan3 or 3E pins to GND
104490: 06/06/28: Re: Synplify prepending Z's to top level signal names in Verilog
104496: 06/06/28: Re: DDR2 at 125MHz or lower with Cyclone2
104536: 06/06/29: Re: NCO Clock driven Designs in FPGA
104573: 06/06/30: Re: Carry-chain based tapped delay line in Spartan3 - resolution?
104598: 06/06/30: Re: Spartan3e starter kit vga mod
104802: 06/07/06: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104805: 06/07/06: Re: Can I use all 18bits of a BlockRAM?
104857: 06/07/07: Re: PCI IOs, tiofoi, source sampling bypass
104860: 06/07/07: Re: The difference betweeen SLICEM and SLICEL
104870: 06/07/07: Re: PCI IOs, tiofoi, source sampling bypass
104902: 06/07/09: Re: Mystery CLKDLL, IBUFG, BUFG modules in verilog src (ISE 6.3.03i)
104939: 06/07/10: Re: LUT4 INIT value to implement 2:1 MUX ?
104951: 06/07/10: Re: LUT4 INIT value to implement 2:1 MUX ?
105039: 06/07/12: Re: how to implement multi-port memory
105112: 06/07/14: Re: Separate enable on address for ram blocks
105142: 06/07/14: Re: Where are you heading?
105144: 06/07/14: Re: Separate enable on address for ram blocks
105146: 06/07/14: Re: Need for reset in FPGAs
105188: 06/07/17: Re: 2048 input or gate ?
105194: 06/07/17: Re: 2048 input or gate ?
105199: 06/07/17: Re: 2048 input or gate ?
105200: 06/07/17: Re: ISE 8.2 WebPack does not support Virtex-5 at all?
105207: 06/07/18: Re: 2048 input or gate ?
105346: 06/07/20: Re: Using DCM-Virtex-II Pro
105394: 06/07/21: Re: Last Chance for Tarfessock1 Features
105408: 06/07/21: Re: Last Chance for Tarfessock1 Features
105409: 06/07/21: Re: Last Chance for Tarfessock1 Features
105537: 06/07/25: Re: An idea for a product (FPGA/ASIC based)
105561: 06/07/26: Re: Spartan 3 clock to output tristate timing
105593: 06/07/26: Re: An idea for a product (FPGA/ASIC based)
105614: 06/07/27: Re: Spartan 3 clock to output tristate timing
105639: 06/07/27: Re: Rocket IO as a high speed sampler
105646: 06/07/27: Re: OT (2nd try): do you get paid for your travel time?
105676: 06/07/28: Re: Verilog case statements
105684: 06/07/28: Re: Verilog case statements
105852: 06/08/01: Re: Programmable pulse generator
105853: 06/08/01: Generate statements for I/O list
105890: 06/08/02: Re: Programmable pulse generator
105892: 06/08/02: Re: FPGA LABVIEW programming
105900: 06/08/02: Re: generating sine-like waveforms
105910: 06/08/02: Re: generating sine-like waveforms
105914: 06/08/02: Re: generating sine-like waveforms
105931: 06/08/03: Re: Generate statements for I/O list
105932: 06/08/03: Re: How can we fully utilize available BRAMs...
105960: 06/08/03: Re: generating sine-like waveforms
105989: 06/08/04: Re: Xilinx PCI Core burst problem
105998: 06/08/04: Re: Synplify
106045: 06/08/07: Re: How do I treat "default" case which is useless?
106190: 06/08/08: Re: Spartan 3 StarterKit Weirdness
106260: 06/08/10: Re: 100 Mbit manchester coded signal in FPGA
106322: 06/08/11: Re: 100 Mbit manchester coded signal in FPGA
106323: 06/08/11: Re: 100 Mbit manchester coded signal in FPGA
106333: 06/08/11: Re: 100 Mbit manchester coded signal in FPGA
106388: 06/08/12: Re: 100 Mbit manchester coded signal in FPGA
106395: 06/08/12: Re: 100 Mbit manchester coded signal in FPGA
106420: 06/08/13: Re: 100 Mbit manchester coded signal in FPGA
106500: 06/08/14: Re: synthesis intelligence of quartus regarding range of values
106502: 06/08/14: Re: synthesis intelligence of quartus regarding range of values
106861: 06/08/21: Re: Need some assistance with ISE OFFSET constraint.
106863: 06/08/21: Re: Need some assistance with ISE OFFSET constraint.
106928: 06/08/22: Re: OFFSET with DCM NET or derived NET?
106929: 06/08/22: Re: Xilinx FPGA editor error ISE8.2
106957: 06/08/23: Re: DCM vs. PLL
107008: 06/08/23: Re: DQPs
107009: 06/08/23: Re: fastest FPGA
107032: 06/08/23: Re: DQPs
107099: 06/08/24: Re: DDR controller on Spartan-3e 500
107285: 06/08/26: Re: fastest FPGA
107318: 06/08/26: Re: FPGA -> SATA?
107319: 06/08/26: Re: fastest FPGA
107337: 06/08/26: Re: fastest FPGA
107425: 06/08/28: Re: Spartan-4 ?
107489: 06/08/29: Re: placing addiional caps across existing caps to reduce noise
107503: 06/08/29: Re: placing addiional caps across existing caps to reduce noise
107524: 06/08/29: Re: placing addiional caps across existing caps to reduce noise
107674: 06/08/31: Re: Spartan 3 PCI-X 133Mhz
107676: 06/08/31: Re: Bypass Caps : XAPP623 vs Spartan-3 Starter Kit Board
107687: 06/08/31: Re: placing addiional caps across existing caps to reduce noise
107699: 06/08/31: Re: placing addiional caps across existing caps to reduce noise
107700: 06/08/31: Re: placing addiional caps across existing caps to reduce noise
107722: 06/08/31: Re: PCI/PCI-X IDSEL
107723: 06/08/31: Re: placing addiional caps across existing caps to reduce noise
107725: 06/08/31: Re: placing addiional caps across existing caps to reduce noise
107760: 06/09/01: Re: placing addiional caps across existing caps to reduce noise
107766: 06/09/01: Re: spartan 3e starter kit usb cable
107767: 06/09/01: Re: placing addiional caps across existing caps to reduce noise
107997: 06/09/04: Re: How to resolve a Xilinx 8.1 BlockRAM problem
108030: 06/09/04: Re: Virtex2Pro: Xilinx PCI core mapping error
108110: 06/09/05: Re: fastest FPGA
108128: 06/09/05: Re: Serial I/O Question
108144: 06/09/06: Re: fastest FPGA
108229: 06/09/06: Re: fastest FPGA
108251: 06/09/07: Re: fastest FPGA
108278: 06/09/07: Re: Xilinx LogiCORE PCI32
108371: 06/09/09: Re: FPGA Devices' stability and process parameters
108534: 06/09/12: Re: fastest FPGA
108551: 06/09/13: Re: fastest FPGA
108557: 06/09/13: Re: fastest FPGA
108611: 06/09/14: Re: resets on synplicity inferred RAMs
108700: 06/09/15: Re: problems with IOSTANDARD
108713: 06/09/15: Re: USB programming cables
108739: 06/09/15: Re: Parallel P&R
108849: 06/09/18: Re: Little help for Spartan 2 and 3 Programmer
108858: 06/09/18: Lattice ECP2/M
108871: 06/09/18: Re: Lattice ECP2/M
108951: 06/09/19: Re: resets on synplicity inferred RAMs
109142: 06/09/21: Re: DDR2 Memory Controller : IOSTANDARD
109409: 06/09/26: Re: Migration from Spartan-2E to Spartan-3E
109410: 06/09/26: Re: An algorithm with Minimum vertex cover without considering its
109473: 06/09/27: Re: Publishable paper related to FPGA
109492: 06/09/27: Re: Configuration of Spartan 3 devices
109493: 06/09/27: Re: Addressing DDR-RAM
109595: 06/09/29: Re: Migration from Spartan-2E to Spartan-3E
109620: 06/10/01: Re: Migration from Spartan-2E to Spartan-3E
109622: 06/10/01: Re: Are you ready for Virtex-5? We are...
109688: 06/10/03: Re: JTAG cable @ 2.5 V - where?
109693: 06/10/03: Re: logarithm look-up table
109767: 06/10/05: Re: Xilinx Virtex-2 Pro MUXCY does not drive local FF
109869: 06/10/06: Re: Design of a programmable delay line
109889: 06/10/06: Re: Design of a programmable delay line
109937: 06/10/08: Re: Spartan 3 Starter Kit I/O ports
110037: 06/10/09: Re: FPGA and ZBT/NoBL SRAM timing issue
110143: 06/10/11: Re: Virtex 4 RAMB16 Clock: optional inverter missing
110175: 06/10/12: Re: Xilinx MicroBlaze 4.00.a source codes released by Xilinx !?
110312: 06/10/13: Re: Xilinx FPGAs in battery-powered scenarios
110377: 06/10/14: Re: FPGA comparision
110378: 06/10/14: Re: longest webcase record -- understandably so
110391: 06/10/15: Re: Xilinx FPGAs in battery-powered scenarios
110397: 06/10/15: Re: Xilinx FPGAs in battery-powered scenarios
110495: 06/10/16: Re: Virtex-5 LXT launched today !
110529: 06/10/17: Re: Virtex-5 LXT launched today !
110809: 06/10/23: Re: iMPACT:923 - Can not find cable, check cable setup !
111006: 06/10/27: Re: a new spartan3E 1600 starter kit available ?
111139: 06/10/30: Re: Dual Port RAM
111169: 06/10/30: Re: On the Futility of Documentation Webcases ( Was: Xilinx documentation typos )
111187: 06/10/31: Re: FFT help
111196: 06/10/31: Re: FFT help
111271: 06/11/01: Re: Need just a few 5V Spartan
111273: 06/11/01: Re: filter design for low-pass
111290: 06/11/01: Re: filter design for low-pass
111498: 06/11/03: Re: Missing constraints [Re: a new spartan3E 1600 starter kit available ?]
111583: 06/11/06: Re: Interface standards (was Re: Dual Port RAM)
111673: 06/11/08: Re: How to send data/program to the memory of a Spartan 3 starter kit board
111721: 06/11/09: Re: How to send data/program to the memory of a Spartan 3 starter kit board
111752: 06/11/09: Re: How to send data/program to the memory of a Spartan 3 starter
111773: 06/11/09: Re: XUP-V2Pro banking rule problem
111778: 06/11/09: Re: XUP-V2Pro banking rule problem
111815: 06/11/10: Re: I look for a wideband SERDES chip
111839: 06/11/11: Re: Xilinx Partition for EDIF Flow (synthesis synplify)
111860: 06/11/11: Re: I look for a wideband SERDES chip
111861: 06/11/11: Re: Virtex-5 Webpack?
111886: 06/11/12: Re: Power-on reset
111905: 06/11/13: Re: Power-on reset
112000: 06/11/14: Re: Influence of temperature and manufacturing to propagation delay
112014: 06/11/14: Re: In defence of Austin and Xilinx
112043: 06/11/15: Re: How to configure Block RAMs with constant values
112044: 06/11/15: Re: Influence of temperature and manufacturing to propagation delay
112055: 06/11/15: Re: Old Spartan-II, worth prototyping?
112142: 06/11/17: Re: Spartan 3/3E to Standard TTL/Low power devices
112164: 06/11/17: Re: FPGA board
112165: 06/11/17: Re: combinatorical divide by 2 in FPGA
112318: 06/11/20: Re: Spartan-3E slice resources
112370: 06/11/21: Re: pulse jitter due to clock
112382: 06/11/21: Re: pulse jitter due to clock
112458: 06/11/22: Re: Virtex 4 Internal Tristate (BUFT)?
112459: 06/11/22: Re: Spartan 3E-Kit
112477: 06/11/22: Re: Division of a (rather large) Gate level Combinational Design
112510: 06/11/23: Re: DCM Jitter
112512: 06/11/23: Re: Voltage prorating for Spartan 3
112521: 06/11/24: Re: DCM Jitter
112570: 06/11/25: Re: Spartan 3E-Kit
112573: 06/11/25: Re: Spartan 3E-Kit
112751: 06/11/28: Re: Bus structures question (Spartan 3)
112769: 06/11/28: Re: Spartan3 Configuration Puzzler
112823: 06/11/29: Re: Spartan3 Configuration Puzzler
112830: 06/11/29: Re: Spartan3 Configuration Puzzler
112831: 06/11/29: Re: ISE on a cluster?
112841: 06/11/29: Re: Spartan3 Configuration Puzzler
112915: 06/12/01: Re: DCM jitter (again)
112966: 06/12/03: Re: LUT input order
113035: 06/12/05: Re: RLOC weirdness
113139: 06/12/06: Re: How to reduce jitter of 30-bit accumulator
113151: 06/12/07: Re: Clock phase shift
113242: 06/12/08: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
113262: 06/12/09: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
113264: 06/12/09: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
113288: 06/12/10: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
113289: 06/12/10: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
113290: 06/12/10: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
113428: 06/12/13: Re: BLVDS_25 @ SPARTAN3
113439: 06/12/13: Re: GUI Based vs. Manual Instantiation of Components
113447: 06/12/13: Re: Virtex4 : cleaner signals?
113452: 06/12/14: Re: How does FPGA tools infer FIFO
113475: 06/12/14: Re: CMI Coder/ Decoder
113501: 06/12/14: Re: Adding Jitter
113640: 06/12/18: Re: solder mask for fpga dissipation
113885: 06/12/28: Re: Why AHDL didn't catch on like Verilog or VHDL?
114055: 07/01/03: Re: newbie needs help
114145: 07/01/05: Re: Spartan3E minimum clock-to-output (hold time)
114250: 07/01/08: Re: Problem with unused pin on Spartan 2E
114273: 07/01/10: Re: crossing clock domain ??
114287: 07/01/10: Re: crossing clock domain ??
114315: 07/01/11: Re: picoblaze RS-232 using 62.5 MHz
114546: 07/01/18: Re: "Gate" = ???
114841: 07/01/25: Re: Aligning data with clock
114944: 07/01/27: Re: Forcing a LUT to not be optimized
115128: 07/01/31: Re: cpld version?
115140: 07/01/31: Re: DDR FPGA Design
115141: 07/01/31: Re: cpld version?
115148: 07/02/01: Re: cpld version?
115159: 07/02/01: Re: cpld version?
115170: 07/02/01: Re: Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?
115180: 07/02/01: Re: Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?
115195: 07/02/02: Re: Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?
115199: 07/02/02: Re: ISE 9.1 SAY YOURS OPINION
115208: 07/02/02: Re: ISE 9.1 SAY YOURS OPINION
115232: 07/02/04: Re: ISE 9.1 SAY YOURS OPINION
115233: 07/02/04: Re: Differential pairs per Bank
115275: 07/02/05: Re: moving data from slower to faster clock domain
115279: 07/02/05: Re: Is Digilent still in business ???
115281: 07/02/05: Re: Is Digilent still in business ???
115447: 07/02/11: Re: substracting a whole array of values at once
115493: 07/02/12: Re: How to develop STM-16 framer in FPGA
115497: 07/02/12: Re: substracting a whole array of values at once
115608: 07/02/14: Re: Spartan 3 Output Driver Issue
115633: 07/02/15: Re: Spartan 3 Output Driver Issue
115635: 07/02/15: Re: Spartan 3 Output Driver Issue
115689: 07/02/16: Re: Does Xilinx XST synthesize combinational divider?
115690: 07/02/16: Re: LUT based virtex multiplier
115776: 07/02/20: Re: can I convert DPRAM to SPRAM?
115787: 07/02/20: Re: can I convert DPRAM to SPRAM?
115810: 07/02/21: Re: can I convert DPRAM to SPRAM?
115828: 07/02/21: Re: nets vs. pads ; constraints question
115836: 07/02/22: Re: Determine error in asynchronous signal
115838: 07/02/22: Re: Determine error in asynchronous signal
115839: 07/02/22: Re: Determine error in asynchronous signal
115845: 07/02/22: Re: Determine error in asynchronous signal
115858: 07/02/22: Re: Xilinx Platform Studio Evaluation Trial Expired (included in
115863: 07/02/22: Re: Determine error in asynchronous signal
115877: 07/02/22: Structured ASIC players
115894: 07/02/23: Re: SystemVerilog?
115896: 07/02/23: Re: Small FPGA Dev Board with Ethernet
115967: 07/02/26: Re: Redundancy
116012: 07/02/27: Re: Making a 32KB BRAM block, virtex-4
116013: 07/02/27: Re: Spartan-3AN
116054: 07/02/28: Re: what does a 'blank check' do exactly
116087: 07/03/01: Re: what does a 'blank check' do exactly
116105: 07/03/01: Re: what does a 'blank check' do exactly
116108: 07/03/01: Re: xilinx block ram synthesis
116118: 07/03/01: Re: what does a 'blank check' do exactly
116147: 07/03/02: Re: xilinx block ram synthesis
116179: 07/03/03: Re: Multiplication operation
116182: 07/03/03: Re: Multiplication operation
116207: 07/03/05: Re: Multiplication operation
116212: 07/03/05: Re: Multiplication operation
116244: 07/03/05: Re: Multiplication operation
116282: 07/03/06: Re: Block RAM in VirtexE FPGA - 'Read-after-Write' and 'No-Read-on-Write'
116345: 07/03/07: Re: VHDL and Latch
116352: 07/03/07: Re: VHDL and Latch
116363: 07/03/07: Re: Introducing picosecond delay between two output signals
116397: 07/03/08: Re: Introducing picosecond delay between two output signals
116488: 07/03/10: Re: Addressing scheme in Block RAM
116509: 07/03/12: Re: Xilinx: Case Statements
116564: 07/03/12: Re: Dual edge detection
116585: 07/03/13: Re: Addressing scheme in Block RAM
116587: 07/03/13: Re: Dual edge detection
116588: 07/03/13: Re: xilinx block ram synthesis
116596: 07/03/13: Re: sum of array
116598: 07/03/13: Re: WTF? - Spartan-3E starter kit with no printed board manual?
116602: 07/03/13: Re: sum of array
116603: 07/03/13: Re: Dual edge detection
116608: 07/03/13: Re: sum of array
116614: 07/03/13: Re: WTF? - Spartan-3E starter kit with no printed board manual?
116639: 07/03/14: Re: Clearing fpga internal memory...
116650: 07/03/14: Re: Clearing fpga internal memory...
116651: 07/03/14: Re: sum of array
116657: 07/03/14: Re: SEC:U Problem with bit latch warnings
116738: 07/03/16: Re: sum of array
116739: 07/03/16: Re: init of FPGA's Block-RAMs.
116752: 07/03/16: Re: Xilinx Synthesis Attribute usage
116788: 07/03/18: Re: Use of both positive reference and negative reference of the
116842: 07/03/19: Re: a project work
116870: 07/03/20: Re: Altera introduces Cyclone III devices, ships 65nm
116871: 07/03/20: Re: Xilinx ISE Inferred block rams
116874: 07/03/20: Re: timing in xilinx fpga
116884: 07/03/20: Re: Altera introduces Cyclone III devices, 'ships' 65nm
116885: 07/03/20: Re: Xilinx ISE Inferred block rams
116958: 07/03/21: Re: Virtex-II block RAM problem
116968: 07/03/21: Re: LZW compression and decompression in vhdl
116983: 07/03/21: Re: how to shift mutiple bytes in an array in one clock cycle?
116984: 07/03/21: Re: Manual LUT - AND function mapping problem
116997: 07/03/21: Re: Why is Xilinx's WebPACK so inferior?
117011: 07/03/21: Re: Off topic: what is the purpoe of XST?
117056: 07/03/22: Re: Virtex-II block RAM problem
117057: 07/03/22: Re: Parallel Cable IV in Spartan 3E???
117065: 07/03/22: Re: Altera introduces Cyclone III devices, 'ships' 65nm
117069: 07/03/22: Re: Parallel Cable IV in Spartan 3E???
117086: 07/03/22: Re: Altera introduces Cyclone III devices, 'ships' 65nm
117125: 07/03/23: Re: URGENT HELP NEEDED: LVDS
117126: 07/03/23: Re: Austin the Altera Mole
117157: 07/03/24: Re: shift register with distributed ram
117175: 07/03/26: Re: shift register with distributed ram
117196: 07/03/26: Re: Small memories in Cyclone
117205: 07/03/26: Re: how to read a sequence of video
117206: 07/03/26: Re: how to read a sequence of video
117260: 07/03/27: Re: how to read a sequence of video
117262: 07/03/27: Re: PCI-Express drivers with Xilinx FPGA?
117271: 07/03/27: Re: PCI-Express drivers with Xilinx FPGA?
117288: 07/03/27: Re: What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L
117330: 07/03/28: Re: Problems with Xilinx Parallel III Cable
117343: 07/03/28: Re: suggestion for choosing the right FPGA for gigabit transciever
117347: 07/03/28: Re: Problems with Xilinx Parallel III Cable
117380: 07/03/29: Re: Problems with Xilinx Parallel III Cable
117387: 07/03/29: Re: suggestion for choosing the right FPGA for gigabit transciever
117460: 07/04/01: Re: Spartan-3A XC3S1400A development board?
117507: 07/04/02: Re: Does the XC3S250E-VQ100 exist?
117513: 07/04/03: Re: Implement IIR Filter on FPGA
117546: 07/04/03: Re: Looking for Memory Recommendation for Spartan 3E 1200
117584: 07/04/04: Re: high number of multipliers / low cost
117610: 07/04/04: Re: Gray code in asynchronous FIFO design
117611: 07/04/04: Re: Gray code in asynchronous FIFO design
117630: 07/04/05: Re: fifo occupancy bigger than fifo size?
117638: 07/04/05: Re: Gray code in asynchronous FIFO design
117639: 07/04/05: OT Re: Gray code in asynchronous FIFO design
117643: 07/04/05: Re: OT Re: Gray code in asynchronous FIFO design
117683: 07/04/06: Re: Transition from ASIC to FPGA
117731: 07/04/09: Re: Xilinx ISE constanly asking to regenerate a core file.
117734: 07/04/09: Re: Clocking data into a shift register on positive AND negative edges
117735: 07/04/09: Re: Measuring the period of a signal
117748: 07/04/09: Re: Clocking data into a shift register on positive AND negative edges
117749: 07/04/09: Re: Looking for Xilinx fpga board that works in Linux and has Ethernet card
117756: 07/04/09: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
118395: 07/04/25: Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
118423: 07/04/26: Re: Timing constraints with asynchronous clocks
118490: 07/04/27: Re: Killed a Stratix-II Nios II Altera devkit, How to repair?
118584: 07/04/30: Re: Please help me fast !!!!!
118673: 07/05/02: Re: Xilinx tools concern
118807: 07/05/03: Re: Select pullup, pulldown or none via embedded S/W
118862: 07/05/04: Re: Select pullup, pulldown or none via embedded S/W
118893: 07/05/06: Re: V5 LVPECL Inputs
118940: 07/05/07: Re: V5 LVPECL Inputs
118973: 07/05/08: Re: V5 LVPECL Inputs
118974: 07/05/08: Re: First MicroBlaze demo design for Spartan-3A Starterkit
119025: 07/05/09: Re: Where can I find the pass transistor's working curve under 1.2V?
119130: 07/05/12: Re: how to choose the perfect fpga support
119180: 07/05/14: Re: Timing constraint question
119183: 07/05/14: Re: Timing constraint question
119239: 07/05/15: Re: Power Consumption Estimation for PCI card, any advice?
119335: 07/05/16: Re: Global ressource problem
119368: 07/05/17: Re: clock wide pulse transfer b/w clock domains
119387: 07/05/17: Re: clock wide pulse transfer b/w clock domains
119392: 07/05/17: Re: Proper/recommended method for driving clock out from FPGA
119489: 07/05/21: Re: Timing not met but working on board
119497: 07/05/21: Re: SelectIO banking rules
119502: 07/05/21: Re: Does FPGA need CPU for processing a packet/frame
119521: 07/05/22: Re: Xilinx doesn't detect setup/hold violations on synchronous reset
119535: 07/05/22: Re: SelectIO banking rules
119550: 07/05/22: Re: Does FPGA need CPU for processing a packet/frame
119561: 07/05/22: Re: how 33-bit BRAM?
119562: 07/05/22: Re: JTAG FPGA Debugging
119564: 07/05/22: Re: System-synchronous interface clocking between FPGA's
119592: 07/05/23: Re: How the synthesizer acutally works.
119612: 07/05/23: Re: clarification: clock doubling in Spartan 3
119660: 07/05/24: Re: How the synthesizer acutally works.
119662: 07/05/24: Re: How the synthesizer acutally works.
119664: 07/05/24: Re: LVDS termination scheme to nonstandard ribbon cable
119679: 07/05/24: Re: LVDS termination scheme to nonstandard ribbon cable
119680: 07/05/24: Re: LVDS termination scheme to nonstandard ribbon cable
119682: 07/05/24: Re: Dual Core or Quad Core when running Quartus 7.1
119698: 07/05/24: Re: LVDS termination scheme to nonstandard ribbon cable
119703: 07/05/24: Re: LVDS termination scheme to nonstandard ribbon cable
119745: 07/05/25: Re: How the synthesizer acutally works.
119756: 07/05/25: Re: IOSTANDARD user constrain
119769: 07/05/25: Re: low speed communication
119904: 07/05/29: Re: How to calculate IFFT based on FFT result?
119981: 07/05/30: Re: Spartan-3E DIG-3E1600 Development Board Kit
119983: 07/05/30: Re: Xilinx Coregen 2.3 problem
120012: 07/05/31: Re: LVDS termination scheme to nonstandard ribbon cable
120029: 07/05/31: Re: Chain of LUTs is being removed during par
120034: 07/05/31: Re: LVDS termination scheme to nonstandard ribbon cable
120040: 07/05/31: Re: Chain of LUTs is being removed during par
120084: 07/06/01: Re: Spartan-3E DIG-3E1600 Development Board Kit
120178: 07/06/02: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
120268: 07/06/04: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
120412: 07/06/06: Re: What should be taken care of when two FPGA broad connected together?
120425: 07/06/06: Re: Virtex4 CLKX2 DCM Jitter
120467: 07/06/07: Re: What's wrong with CoreGen 7.0: dynamic coef multiplier (port B = constant /w reloadable)
120471: 07/06/07: Re: What's wrong with CoreGen 7.0: dynamic coef multiplier (port B = constant /w reloadable)
120472: 07/06/07: Re: Lattce SC Purspeed I/O
120476: 07/06/07: Re: What's wrong with CoreGen 7.0: dynamic coef multiplier (port B = constant /w reloadable)
120477: 07/06/07: Re: Virtex4 CLKX2 DCM Jitter
120496: 07/06/08: Re: LVPECL output skew
120531: 07/06/08: Re: Newbie Question: Using Includes in Verilog
120549: 07/06/09: Re: Affordable pcie card ?
120591: 07/06/11: Re: Unused clock pins tied inactive?
120636: 07/06/12: Re: Programming Question
120755: 07/06/15: Re: what is the correct way to capture ADC using fpga
120762: 07/06/15: Re: virtex-II DCM phase shift problems
120769: 07/06/15: Re: what is the correct way to capture ADC using fpga
120792: 07/06/16: Re: what is the correct way to capture ADC using fpga
120804: 07/06/17: Re: what is the correct way to capture ADC using fpga
120941: 07/06/20: Re: Can anyone identify the manufacturer of this Chip ?
121095: 07/06/25: Re: Xilinx FPGA: "after 10ns" constraint
121146: 07/06/26: Re: Can FPGAs inputs detect low currents?
121199: 07/06/28: Re: Xilinx FPGA to interface to special I/O
121213: 07/06/28: Re: Xilinx FPGA to interface to special I/O
121222: 07/06/28: Re: Xilinx FPGA to interface to special I/O
121227: 07/06/28: Re: Xilinx FPGA to interface to special I/O
121235: 07/06/28: Re: d-link router?
121265: 07/06/29: Re: Xilinx FPGA to interface to special I/O
121271: 07/06/29: Re: Latches
121295: 07/06/30: Re: Xilinx programmer, many unknown devices...
121298: 07/07/01: Re: Multiplier in Xilinx
121321: 07/07/02: Re: Multiplier in Xilinx
121371: 07/07/03: Re: Metastability in very slow clock domains
121388: 07/07/03: Re: MPC 8321E DDR2 interface
121430: 07/07/04: Re: How to choose FPGA for a huge computation?
121444: 07/07/04: Re: Simulation problem
121446: 07/07/04: Re: Rocket IO clocking
121451: 07/07/04: Re: Change PicoBlaze ROM Code on Spartan 3E Development Board
121476: 07/07/05: Re: Simulation problem
121477: 07/07/05: Re: Does synplify 8.8 can support xilinx virtex5?
121479: 07/07/05: Re: Spartan-3A: 200A & 400A Image problems / variance...
121563: 07/07/08: Re: fifo counter in virtex-4
121571: 07/07/08: Re: Question on Virtex2p DCMs usability
121613: 07/07/09: Re: Synplify Problem
121641: 07/07/10: Re: ISE 9.1i - Process Map Fail without any Error messages
121680: 07/07/11: Re: Strange warning message from ise8.2i ?
121693: 07/07/11: Re: Strange warning message from ise8.2i ?
121704: 07/07/11: Re: Strange warning message from ise8.2i ?
121708: 07/07/12: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121717: 07/07/12: Re: New board JTAG error
121748: 07/07/12: Re: highly-parallel highspeed connection between two FPGA boards
121764: 07/07/12: Re: CML output swing for V5
121784: 07/07/13: Re: CML output swing for V5
121803: 07/07/13: Re: CML output swing for V5
121805: 07/07/13: Re: Counter ?
121837: 07/07/13: Re: Counter ?
121838: 07/07/13: Re: CML output swing for V5
121846: 07/07/13: Re: CML output swing for V5
121859: 07/07/13: Re: Counter ?
121860: 07/07/13: Re: Counter ?
121863: 07/07/13: Re: Seeing failures when clocking system-synchronous inter-FPGA interfaces at lower clock rates
121865: 07/07/13: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121871: 07/07/13: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121889: 07/07/14: Re: Image Resolution Rescaling
121922: 07/07/15: Re: Newbie's first FPGA board !
121941: 07/07/15: Re: Which embedded O/S for a 32-bit RISC microcontroller?
121956: 07/07/16: Re: Newbie's first FPGA board !
121963: 07/07/16: Re: Newbie's first FPGA board !
121969: 07/07/16: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121986: 07/07/16: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
122004: 07/07/17: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
122012: 07/07/17: Re: BD
122016: 07/07/17: Re: Actel. Libero. Synplify
122074: 07/07/18: Re: or1200 uses more than 100% of resources. how to reduce?
122102: 07/07/19: Re: BD
122103: 07/07/19: Re: Can multiple Ferrite Beads be used to connect ...?
122113: 07/07/19: Re: Xilinx XST 9.2i.01 - still incomplete support for always @*
122114: 07/07/19: Re: Can multiple Ferrite Beads be used to connect ...?
122159: 07/07/21: Re: Can multiple Ferrite Beads be used to connect ...?
122166: 07/07/21: Re: Can multiple Ferrite Beads be used to connect ...?
122188: 07/07/23: Re: On I2C protocol
122228: 07/07/24: Re: On I2C protocol
122230: 07/07/24: Re: 3 input adder in Spartan 3E
122239: 07/07/24: Re: 3 input adder in Spartan 3E
122266: 07/07/24: Re: On I2C protocol
122293: 07/07/25: Re: Beginners question
122311: 07/07/25: Re: 3 input adder in Spartan 3E
122339: 07/07/25: Re: On I2C protocol
122344: 07/07/25: Re: Beginners question
122353: 07/07/26: Re: Altera or Xilinx
122384: 07/07/26: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
122392: 07/07/26: Re: DCM with Xilinx Spartan 3E and Precision
122453: 07/07/27: Re: Question about GSR?
122460: 07/07/27: Re: Question about GSR?
122464: 07/07/27: Re: Question about GSR?
122466: 07/07/27: Re: Question about GSR?
122469: 07/07/27: Re: Question about GSR?
122708: 07/08/03: Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
122767: 07/08/06: Re: Need suggestion for my project
122814: 07/08/07: Re: Can multiple Ferrite Beads be used to connect ...?
122817: 07/08/07: Re: EDK 8.1
122829: 07/08/08: Re: New Xilinx forum.
122861: 07/08/08: Re: Specifying LVDS I/O's in Xilinx FPGA's
122919: 07/08/10: Re: Amount of wire and logic
122933: 07/08/10: Re: How to locate the internal state machine in timing simulation
122956: 07/08/12: Re: How to locate the internal state machine in timing simulation
122959: 07/08/12: Re: How to locate the internal state machine in timing simulation
122981: 07/08/13: Re: regarding the clock issues in the fpga...
122982: 07/08/13: Re: New Xilinx forum.
123018: 07/08/14: Re: regarding the clock issues in the fpga...
123032: 07/08/14: Re: Delaying a pulse train
123036: 07/08/14: Re: Delaying a pulse train
123080: 07/08/15: Re: Delaying a pulse train
123084: 07/08/16: Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits
123169: 07/08/17: Re: Minimal power?
123171: 07/08/17: Re: Minimal power?
123332: 07/08/23: Re: Annoying
123440: 07/08/28: Re: Xilinx Virtex IOB Regiters and Noise???
123543: 07/08/29: Re: Output signals not synchronized
123604: 07/08/30: Re: PCB Impedance Control
123629: 07/08/31: Re: Is it possible to make bit files generated by Xilinx ISE readable?
123637: 07/08/31: Re: PCB Impedance Control
123653: 07/08/31: Re: Chip Designing made Easy
123655: 07/08/31: Re: PCB Impedance Control
123662: 07/08/31: Re: Die size, pitch size?
123833: 07/09/05: Re: PCB Impedance Control
123870: 07/09/06: Re: PCB Impedance Control
123885: 07/09/06: Re: Is it possible to perform gate level simulation on a design without a reset?
123903: 07/09/06: Re: Problem locking a DCM driven by FX output of another DCM
123905: 07/09/06: Re: PCB Impedance Control
123910: 07/09/06: Re: Problem locking a DCM driven by FX output of another DCM
123972: 07/09/08: Re: Is it possible to perform gate level simulation on a design without
123979: 07/09/10: Re: Minimize power consumption
123988: 07/09/10: Re: Minimize power consumption
123993: 07/09/10: Re: Is it possible to perform gate level simulation on a design without a reset?
123994: 07/09/10: Re: Minimize power consumption
124005: 07/09/10: Re: What is called carry chain structure in FPGA is called in IC?
124006: 07/09/10: Re: What is the name of Altera latest and most advanced chip serial that is compatible in technology with Virtex-5 in terms of system strucute(LUT6...)
124008: 07/09/10: Re: Is it possible to perform gate level simulation on a design without a reset?
124016: 07/09/11: Re: What is called carry chain structure in FPGA is called in IC?
124053: 07/09/11: Re: Uses of Gray code in digital design
124065: 07/09/11: Re: Minimize power consumption
124067: 07/09/11: Re: PCI byte enalbes in read cycles
124172: 07/09/13: Re: PCI byte enalbes in read cycles
124179: 07/09/13: Re: Problem with Microblaze max clocking
124278: 07/09/17: Re: Altera / Lattice / Xilinx CPLDs ?
124289: 07/09/17: Re: Altera / Lattice / Xilinx CPLDs ?
124321: 07/09/18: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124329: 07/09/18: Re: Population Count circuit
124333: 07/09/18: Re: Population Count circuit
124346: 07/09/19: Re: Guess: what is the largest number of state machines in a current
124376: 07/09/20: Re: Guess: what is the largest number of state machines in a current
124413: 07/09/20: Re: Comparing Adder synthesis techniques
124414: 07/09/20: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124431: 07/09/21: Re: baord for learning softcore processor
124533: 07/09/26: Re: Never buy Altera!!!!
124564: 07/09/26: Re: Inferring wide adders comprising multiple DSP48s
124574: 07/09/26: Re: Logic minimization software with LUT6 support?
124589: 07/09/27: Re: Bug in Synplify?
124619: 07/09/28: Re: FPGA NTSC signal with 2 resistors and PWM
124670: 07/09/29: Re: XUPV2P from digilentinc
124671: 07/09/29: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124702: 07/10/01: Re: Synplicity and the Xilinx MAP Memory Monster
124791: 07/10/04: Re: xup-v2p: Only USB 1.1
124804: 07/10/04: Re: Daisy chaining FPGA with CPLDs
124806: 07/10/04: Re: How to do one hot state machine in verilog for Xilinx V5 using XST
124821: 07/10/05: Re: XUPV2P from digilentinc
124871: 07/10/09: Re: Need suggestion on FPGA kit
124964: 07/10/12: Re: NgdBuild:455 Multiple Drivers
125196: 07/10/17: Re: Reason for LUT1_L buffer insertion in Synplify EDIFs?
125215: 07/10/18: Re: Reason for LUT1_L buffer insertion in Synplify EDIFs?
125502: 07/10/26: Re: FPGA vs ASIC
125538: 07/10/27: Re: Power supply filter capacitors
125545: 07/10/28: Re: Power supply filter capacitors
125590: 07/10/29: Re: FPGA Configuration
125619: 07/10/30: Re: FFT for an arbitrary number of points (not power of 2)
125672: 07/10/31: Re: Capability of a FPGA device.
125689: 07/11/01: Re: FPGA vs ASIC
125724: 07/11/01: Re: fpga based designs
125743: 07/11/02: Re: Synthesizing with specific primitive-elements
125782: 07/11/05: Re: Xilinx PCI-express coregen
125864: 07/11/07: Re: FPGA Clock signal
125904: 07/11/08: Re: Maximum current drive according to datasheet ?!
125906: 07/11/08: Re: Non-volatile FPGA in a small package
125936: 07/11/09: Re: Maximum current drive according to datasheet ?!
125945: 07/11/09: Re: What the 'c2p' and 'c2o' stand for?
125968: 07/11/10: Re: FIFO interface design
126020: 07/11/12: Re: Programming connection
126021: 07/11/12: Re: Spartan3E Slave Serial Daisy chain
126056: 07/11/13: Re: Spartan3E Slave Serial Daisy chain
126167: 07/11/15: Re: Lattice Semi
126287: 07/11/19: Re: Lattice Semi
126412: 07/11/21: Re: Measuring setup and hold time in Lab
126428: 07/11/22: Re: Unable to scan device chain
126603: 07/11/28: Re: Global Reset using Global Buffer
126604: 07/11/28: Re: I/O short circuit protection?
126642: 07/11/29: Re: FPGA not in boundary scan
126671: 07/11/29: Re: FPGA not in boundary scan
126687: 07/11/29: Re: lossless compression in hardware: what to do in case of
126702: 07/11/29: Re: FPGA not in boundary scan
126817: 07/12/03: Re: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same
126863: 07/12/04: Re: clock lines
126882: 07/12/05: Re: BUFGCE
126933: 07/12/06: Re: BUFGCE
126952: 07/12/06: Re: For God's sake !! It did not work at all !!!
126968: 07/12/07: Re: usb cable driver
126980: 07/12/07: Re: usb cable driver
127046: 07/12/10: Re: keep_hierarchy attribute equivalent for Lattice/Synplicity?
127060: 07/12/10: Re: keep_hierarchy attribute equivalent for Lattice/Synplicity?
127078: 07/12/11: Re: DDS generator with interpolated samples for Spartan3E development
127083: 07/12/11: Re: keep_hierarchy attribute equivalent for Lattice/Synplicity?
127087: 07/12/11: Re: Craignell and Darnaw1 Website Updates
127089: 07/12/11: Re: Craignell and Darnaw1 Website Updates
127096: 07/12/11: Re: Craignell and Darnaw1 Website Updates
127121: 07/12/12: Re: Poor quality Xilinx boards ? Your experience ?
127135: 07/12/12: Re: Poor quality Xilinx boards ? Your experience ?
127141: 07/12/12: Re: FPGA Board design basics
127151: 07/12/12: Re: Spartan 3e pin question
127187: 07/12/13: Re: Poor quality Xilinx boards ? Your experience ?
127196: 07/12/13: Re: Poor quality Xilinx boards ? Your experience ?
127247: 07/12/15: Re: Using LVDS_25 with 3.3V Vcco.
127248: 07/12/15: Re: Getting started guide for Digilent Spartan 3E Starter Board?
127249: 07/12/15: Re: Spartan-3E starter kit, what's "J8" 6-pin for?
127256: 07/12/15: Re: Using LVDS_25 with 3.3V Vcco.
127259: 07/12/16: Re: serial ATA question
127269: 07/12/16: Re: Spartan-3E starter kit, what's "J8" 6-pin for?
127270: 07/12/16: Re: Getting started guide for Digilent Spartan 3E Starter Board?
127271: 07/12/16: Re: [help]SAS with FPGAs
127309: 07/12/17: Xilinx DCM outputs for DDR
127326: 07/12/18: Re: Xilinx DCM outputs for DDR
127332: 07/12/18: Re: Virtex BRAM Configuration
127340: 07/12/18: Re: Xilinx DCM outputs for DDR
127366: 07/12/19: Re: Xilinx DCM outputs for DDR
127367: 07/12/19: Re: sampling error between 2 clocks
127372: 07/12/19: Re: Xilinx DCM outputs for DDR
127373: 07/12/19: Re: sampling error between 2 clocks
127376: 07/12/19: Re: Xilinx DCM outputs for DDR
127380: 07/12/19: Re: Xilinx DCM outputs for DDR
127388: 07/12/20: Re: help with rising edge matching
127434: 07/12/24: Re: FPGA Project Support
127538: 08/01/01: Re: Split Plane
127556: 08/01/02: Re: Split Plane
127557: 08/01/02: Re: Where are the LCD or OLED bitmapped displays?
127658: 08/01/04: Re: Split Plane
127665: 08/01/04: Re: Split Plane
127683: 08/01/05: Re: Cyclone II short-circuit failure mode
127758: 08/01/07: Re: Processor in CPLD
127762: 08/01/07: Re: Processor in CPLD
127777: 08/01/07: Re: Where are the LCD or OLED bitmapped displays?
127825: 08/01/08: Re: Real examples of metastability causing bugs
127853: 08/01/09: Re: Spartan3 vs cyclone
127855: 08/01/09: Re: Real examples of metastability causing bugs
127866: 08/01/09: Re: Real examples of metastability causing bugs
127885: 08/01/09: Re: Real examples of metastability causing bugs
127939: 08/01/10: Re: Connecting different FPGAs using LVDS
127972: 08/01/11: Re: Connecting different FPGAs using LVDS
127980: 08/01/11: Re: Timing constraints not applied, ISE & SynplifyPro
127997: 08/01/11: Re: Real examples of metastability causing bugs
128005: 08/01/12: Re: Real examples of metastability causing bugs
128013: 08/01/12: Re: Real examples of metastability causing bugs
128018: 08/01/13: Re: Real examples of metastability causing bugs
128053: 08/01/14: Re: fpga pin to pin conecting
128105: 08/01/15: Re: speed... CORDIC vs. pure arithmetic expression
128110: 08/01/15: Re: speed... CORDIC vs. pure arithmetic expression
128114: 08/01/15: Re: User inputs into Spartan-3E starter board?
128164: 08/01/17: Re: effect of xray on fpga electronic circuits
128246: 08/01/18: Re: Source of accurate frequency
128263: 08/01/19: Re: Source of accurate frequency
128265: 08/01/19: Re: SRL16x2 in Virtex5
128290: 08/01/20: Re: Source of accurate frequency
128293: 08/01/20: Re: Sparkfun Spartean3e Board
128305: 08/01/20: Re: How FPGA downconvert Giga SPS ADC data?
128351: 08/01/22: Re: Ballistic chronograph using a Spartan 3E starter board
128477: 08/01/27: Re: Synplicy and Xilinx - no PAR
128962: 08/02/11: Re: Xilinx ISE and XP home,possible?
128964: 08/02/11: Re: how to implement this...
128989: 08/02/12: Re: Does PC-FPGA communication requires a driver?
129000: 08/02/12: Re: My first verilog/cpld project
129001: 08/02/12: Re: Virtex4FX over-voltage
129112: 08/02/14: Re: Virtex-4 input pad failures
129146: 08/02/15: Re: distorted sine wave
129147: 08/02/15: Re: how to implement this...
129157: 08/02/15: Re: distorted sine wave
129238: 08/02/19: Re: FPGA Programming solution
129359: 08/02/21: Re: Software Defined Radio auf Xilinx Virtex 4
129362: 08/02/21: Re: Interview questions
129378: 08/02/22: Re: Reconfiguration (on the fly) using SPARTAN 3A
129466: 08/02/25: Re: Xilinx parallel cable 4 clone
129675: 08/03/02: Re: FPGA/CPLD group on LinkedIn
129703: 08/03/03: Re: clock distribution accross boards
129751: 08/03/04: Re: clock distribution accross boards
129834: 08/03/06: Re: PCI Timing Contraints ignored
129838: 08/03/06: Re: Blast from the past
129860: 08/03/07: Re: Spartan-3A DSP Starter: JX Connector Part number
129880: 08/03/07: Re: Danger of having JTAG TAP controller always enabled in Xilinx
129924: 08/03/10: Re: SiliconBlue enters the FPGA fray
129995: 08/03/12: Re: infer block ram with mismatched port width
130047: 08/03/13: Re: Design entries for FSM
130069: 08/03/14: Re: Design entries for FSM
130072: 08/03/14: Re: Xilinx S3DSP + EDK Board, too good to be true?
130075: 08/03/14: Re: Design entries for FSM
130079: 08/03/14: Re: DDR3 speed, Altera vs Xilinx
130080: 08/03/14: Re: Xilinx S3DSP + EDK Board, too good to be true?
130103: 08/03/14: Re: Xilinx Tristate Registration
130136: 08/03/16: Re: Need help in SDR
130182: 08/03/17: Re: dual clock fifo
130189: 08/03/17: Re: dual clock fifo
130190: 08/03/17: Re: Designing CPU
130194: 08/03/17: Re: dual clock fifo
130224: 08/03/18: Re: dual clock fifo
130231: 08/03/18: Re: dual clock fifo
130357: 08/03/20: Re: Synoplify ???
130454: 08/03/24: Re: PCI Express Configuration Testing
130636: 08/03/28: Re: quick question
130907: 08/04/04: Re: counterfeit Xilinx ?
131007: 08/04/08: Re: OBUF gate delay
131080: 08/04/09: Re: Specifying strict setup constraint in ISE
131152: 08/04/12: Re: high noise/signal in a simple serial to mono dac module
131202: 08/04/15: Re: Pre and Post Synthesis Simulation mismatch
131204: 08/04/15: Re: Snythesis error
131410: 08/04/21: Re: Problem writing quadrature decoder
131439: 08/04/21: Re: Problem writing quadrature decoder
131448: 08/04/21: Re: Problem writing quadrature decoder
131598: 08/04/25: Re: -. . .-- ... --. .-. --- ..- .--.
131600: 08/04/25: Re: How to arrange these SRL16 in a straight column
131699: 08/04/29: Re: Debounce in Verilog?
131703: 08/04/29: Re: FPGA comeback
131844: 08/05/03: Re: Using SRL16
131919: 08/05/07: Re: ANNC: FPGA Design Software Webcast
131934: 08/05/07: Re: ANNC: FPGA Design Software Webcast
131968: 08/05/08: Re: Spartan 3 Mapping Problem
131970: 08/05/08: Re: Spartan 3 Mapping Problem
131996: 08/05/09: Re: 5 V oscillator output to GCLK
132038: 08/05/10: Re: Problem writing quadrature decoder
132053: 08/05/11: Re: Problem writing quadrature decoder
132063: 08/05/12: Re: Problem writing quadrature decoder
132074: 08/05/12: Re: Problem writing quadrature decoder
132081: 08/05/12: Re: Problem writing quadrature decoder
132086: 08/05/12: Re: Problem writing quadrature decoder
132090: 08/05/12: Re: Problem writing quadrature decoder
132094: 08/05/13: Re: Problem writing quadrature decoder
132105: 08/05/13: Re: Problem writing quadrature decoder
132110: 08/05/13: Yay! We're done with the quadrature encoder!
132279: 08/05/20: Re: synthesis...
132485: 08/05/28: Re: FIFO verses RAMB
132568: 08/05/31: Re: cutoff frequency
132589: 08/06/02: Re: xilinx and jtag
132622: 08/06/03: Re: xilinx and jtag
132625: 08/06/03: Re: Timing closure problem --- how to make the QII fitter smarter
132737: 08/06/05: Re: Xilinx cuts 250 jobs.
132738: 08/06/05: Re: FPGA clock frequency
132742: 08/06/05: Re: Xilinx cuts 250 jobs.
132751: 08/06/05: Re: ANNOUNCE: SiliconBlue Pioneers New FPGA Technology for Handheld,
132781: 08/06/06: Re: Xilinx cuts 250 jobs.
132853: 08/06/09: Re: FPGA clock frequency
132860: 08/06/09: Re: FPGA clock frequency
132914: 08/06/10: Re: Digital VSB (Vestigial Side Band) Modulator for Analog TV
132916: 08/06/10: Whitepapers are taking over the lost TechXclusives
132922: 08/06/10: Re: Digital VSB (Vestigial Side Band) Modulator for Analog TV
132936: 08/06/10: Re: Trouble programming V4FX40
132939: 08/06/10: Re: Trouble programming V4FX40
132950: 08/06/11: Re: Trouble programming V4FX40
133120: 08/06/18: Re: Mapping the DCM clock output onto a global buffer
133131: 08/06/18: Re: Mapping the DCM clock output onto a global buffer
133161: 08/06/19: Re: Fixed point number hardware implementation
133167: 08/06/19: Re: Synplify beeping
133176: 08/06/19: Re: Mapping the DCM clock output onto a global buffer
133255: 08/06/22: Re: Altera, Cyclone III, PCI, LVCMOS, & 3.3V
133278: 08/06/23: Re: virtex-5: can't use DCM (too low input frequency)
133292: 08/06/23: Re: virtex-5: can't use DCM (too low input frequency)
133342: 08/06/25: Re: Beginner : Rotary switch (quad sw)
133604: 08/07/05: Re: Single ended interface at 70Mhz for FPGAs
133764: 08/07/13: Re: Mismatch simulation & post sythese results
133828: 08/07/16: Re: unified protocol
134004: 08/07/21: Re: Xilinx FPGA editor tips?
134008: 08/07/21: Re: Xilinx FPGA editor tips?
134067: 08/07/23: Re: Xilinx mapper errors out when placing an RLOCed distributed ram
134100: 08/07/25: Re: SD Card Controller
134201: 08/07/30: Re: Getting on the Spartan3e carry chain.
134203: 08/07/30: Re: Getting on the Spartan3e carry chain.
134252: 08/08/01: Re: question about fifo
134323: 08/08/06: Re: Downsizing Verilog synthesization.
134339: 08/08/06: Re: Downsizing Verilog synthesization.
134411: 08/08/09: Re: Downsizing Verilog synthesization.
134451: 08/08/11: Re: spartan sa dcm maximal frequency
134452: 08/08/11: Re: Block Rams
134472: 08/08/12: Re: Block Rams
134560: 08/08/18: Re: More work, less posts
134669: 08/08/25: Re: need fast FPGA suggestions
134702: 08/08/26: Re: need fast FPGA suggestions
134719: 08/08/27: Re: need fast FPGA suggestions
134749: 08/08/28: Re: need fast FPGA suggestions
134762: 08/08/28: Re: How many mux input on a Xilinx V4 are pratical
134773: 08/08/29: Re: need fast FPGA suggestions
134819: 08/09/02: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
134823: 08/09/02: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
134840: 08/09/03: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
134882: 08/09/04: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
134925: 08/09/07: Re: Are Xilinx tools that bad, or am I missing something?
134959: 08/09/08: Re: Some feedback on the Xilinx web site
134983: 08/09/09: Re: Some feedback on the Xilinx web site
135137: 08/09/17: Re: Xilinx Spartan E
135138: 08/09/17: Re: SDRAM question
135145: 08/09/17: Re: Xilinx Spartan E
135146: 08/09/17: Re: SDRAM question
135148: 08/09/17: Re: Xilinx Spartan E
135159: 08/09/18: Re: security system password by voice recognition commands
135188: 08/09/19: Re: Peter says Good Bye
135255: 08/09/23: Re: duty cycle significance
135308: 08/09/25: Re: FPGA Lab Liquidation Sale
135488: 08/10/04: Re: Video processing in FPGA
135527: 08/10/06: Re: A question about the use of FPGA
135693: 08/10/12: Re: DDR FLOP?
135731: 08/10/13: Re: sensitive fpga
135793: 08/10/15: Re: Distributed Dual-Port RAM
135858: 08/10/17: Re: Xilinx: FDR and FD inference in Synplify_pro
135908: 08/10/21: Re: How to synthesize a delay of around 10 ns in FPGA?
135984: 08/10/25: Re: How to synthesize a delay of around 10 ns in FPGA?
136167: 08/11/04: Re: Critical Path
136200: 08/11/05: Re: Critical Path
136221: 08/11/06: Re: face recognition
136257: 08/11/07: Re: Tilera multicore replaces FPGA?
136258: 08/11/07: Re: Xilinx Floorplaner X,y Coordinates
136514: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
136529: 08/11/20: Re: Spartan3 SRL16 + SliceFF, LUT stability
136545: 08/11/21: Re: Student FPGAs
136546: 08/11/21: Re: Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell
136558: 08/11/21: Small adders in XST?
136712: 08/12/02: Re: how to read images from a microSD card ?
136713: 08/12/02: Re: reading registers
144658: 09/12/21: Re: Please help, Xilinx FIFO problem!
144674: 09/12/22: Re: Please help, Xilinx FIFO problem!
144675: 09/12/22: Re: Please help, Xilinx FIFO problem!
144677: 09/12/22: Re: Please help, Xilinx FIFO problem!
144773: 10/01/01: Re: verilog multiplexer
144774: 10/01/01: Re: Xilinx and Multi-port memories
144775: 10/01/01: Re: Xilinx and Multi-port memories
144776: 10/01/01: Re: Video Processing
144783: 10/01/02: Re: Xilinx and Multi-port memories
144784: 10/01/02: Re: NOR-based Flash Memory - Design
144803: 10/01/05: Re: Video Processing
144806: 10/01/05: Re: Video Processing
144816: 10/01/06: Re: Databus crossing clock domains with data freeze
144817: 10/01/06: Re: ADC problem on spartan3E
144844: 10/01/07: Re: Video Processing
144888: 10/01/12: Re: E1 clock problem...
144889: 10/01/12: Re: XC2V2000-5FF896C or XC2V2000-6FF896C Virtex II
145025: 10/01/20: Re: A construction of FPGA based design by a beginner
145042: 10/01/21: Re: State Machine Initialization in Synplify Pro
145048: 10/01/22: Re: State Machine Initialization in Synplify Pro
145049: 10/01/22: Re: Spartan 3E Starter Kit - Power problem
145077: 10/01/25: Re: timing properties of fpga devices at sub-clock frequencies
145088: 10/01/26: Re: timing properties of fpga devices at sub-clock frequencies
145103: 10/01/27: Re: timing properties of fpga devices at sub-clock frequencies
145124: 10/01/28: Re: timing properties of fpga devices at sub-clock frequencies
145182: 10/01/31: Re: vhdl divider
145320: 10/02/05: Re: DONE_cycle:6 setting neccessary in bitgen
145532: 10/02/13: Re: VHDL vs Verilog
145533: 10/02/13: Re: What is the basis on flip-flops replaced by a latch
145542: 10/02/13: Re: What is the basis on flip-flops replaced by a latch
145556: 10/02/14: Re: What is the basis on flip-flops replaced by a latch
145557: 10/02/14: Re: 28nm FPGAs are coming...
145575: 10/02/14: Re: 28nm FPGAs are coming...
145902: 10/02/27: Re: Place and Route
145914: 10/02/27: Re: Frustration with Vendors!
146006: 10/03/03: Re: Laptop for FPGA design?
146267: 10/03/10: Re: Tier Logic introduces the world's first 3D FPGA
146296: 10/03/10: Re: Tabula. (FPGA start up)
146303: 10/03/11: Re: Tier Logic introduces the world's first 3D FPGA
146304: 10/03/11: Re: Tier Logic introduces the world's first 3D FPGA
146336: 10/03/12: Re: When do you pin out?
146348: 10/03/13: Re: Tier Logic introduces the world's first 3D FPGA
146478: 10/03/19: Re: Update init data in dualport BRAM without re-run anything?
146488: 10/03/19: Re: Update init data in dualport BRAM without re-run anything?
146597: 10/03/23: Re: Why hardware designers should switch to Eclipse
146645: 10/03/24: Re: EMC discussion
146646: 10/03/24: Re: Ring Oscillator -> counter differences
146661: 10/03/25: Re: EMC discussion
146666: 10/03/25: Re: EMC discussion
146681: 10/03/25: Re: EMC discussion
146706: 10/03/26: Re: baud rates etc
146707: 10/03/26: Re: result on hyperterminal is not displayed
146724: 10/03/26: Re: Ring Oscillator -> counter differences
146736: 10/03/26: Re: PCB routing issues for sync SRAM
146737: 10/03/26: Re: Ring Oscillator -> counter differences
146746: 10/03/27: Re: Multipliers in CoolRunner Series?
146749: 10/03/27: Re: Multipliers in CoolRunner Series?
146763: 10/03/27: Re: PCB routing issues for sync SRAM
146777: 10/03/28: Re: Maximum output rate
146778: 10/03/28: Re: PCB routing issues for sync SRAM
146779: 10/03/28: Re: PCB routing issues for sync SRAM
146788: 10/03/28: Re: PCB routing issues for sync SRAM
146789: 10/03/28: Re: Maximum output rate
146840: 10/03/29: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
146841: 10/03/29: Re: PCB routing issues for sync SRAM
146872: 10/03/30: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
146878: 10/03/30: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
146895: 10/03/31: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
146908: 10/04/01: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
146921: 10/04/01: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
146950: 10/04/03: Re: Is there a way to implement division by variables other than 2 in
146977: 10/04/07: Re: Case with HEX value ...
146980: 10/04/07: Re: Case with HEX value ...
147257: 10/04/21: Re: Efficient Multi-Ported Memories for FPGAs
147299: 10/04/22: Re: Absolute value of a two's complement number
147324: 10/04/22: Re: Efficient Multi-Ported Memories for FPGAs
147390: 10/04/25: Re: Efficient Multi-Ported Memories for FPGAs
147396: 10/04/26: Re: Efficient Multi-Ported Memories for FPGAs
147419: 10/04/26: Re: Efficient Multi-Ported Memories for FPGAs
147458: 10/04/27: Re: Efficient Multi-Ported Memories for FPGAs
147460: 10/04/27: Re: Efficient Multi-Ported Memories for FPGAs
147652: 10/05/12: Re: what is the fmax of the simple dual port ram in the altera fpga
147760: 10/05/22: Last Xilinx Webpack that was big-brother free?
147761: 10/05/22: Re: Last Xilinx Webpack that was big-brother free?
147769: 10/05/23: Re: Last Xilinx Webpack that was big-brother free?
147781: 10/05/24: Re: Xilinx Xact software for XC2018 Logic Cell Array
147782: 10/05/24: Re: Last Xilinx Webpack that was big-brother free?
147821: 10/05/25: Re: Advice on Xilinx Spelunking
147830: 10/05/26: Re: BRAM with output register using ram_style attribute
147864: 10/05/28: Re: Advice on Xilinx Spelunking
147901: 10/06/01: Re: Graphical User Interface project on Spartan-3 FPGA
147902: 10/06/01: Re: Block RAM unusually long setup time ?
148107: 10/06/21: Re: Xilinx BULLSHITIX-8, when?
148172: 10/06/25: Re: fooling the compiler
148212: 10/06/29: Re: Require a solution - LVDS support +RJ45 connectors
148369: 10/07/15: Re: help regarding daisy chained fpgas
148373: 10/07/16: Re: help regarding daisy chained fpgas
148422: 10/07/21: Re: How to create a LVPECL_25 output pair (Spartan3, ISE 9.1)
148660: 10/08/13: Re: Spartan3a: improving DCM performance and
148825: 10/08/29: Re: FPGA DAC Interface
<john_stiekema@my-deja.com>:
27699: 00/12/04: Re: ANNOUNCE: Checksum and CRC Code/Article
<johnb@teachers.org>:
27058: 00/11/08: WTB: old Digital DEC PDP-8 computer or software
<johnbean_uk@hotmail.com>:
142563: 09/08/17: Re: Virtex 4 package code
<johnbeekley@yahoo.com>:
10660: 98/06/09: Re: FPGA Conversion
johnblake2000@gmail.com:
123970: 07/09/08: Help getting sdram running with EDK.
124156: 07/09/12: Re: Help getting sdram running with EDK.
124157: 07/09/12: Re: Help getting sdram running with EDK.
johnd:
13018: 98/11/11: Test - please ignore!
13020: 98/11/11: Test - please ignore!
13025: 98/11/11: Test - please ignore!
<johnd1489@my-dejanews.com>:
13022: 98/11/11: Test - Ignore
JohnG:
156846: 14/07/08: Re: Linux driver for Xilinx axi_10g_ethernet_0_ten_gig_eth_mac core?
<johngalil@hotmail.com>:
91359: 05/11/03: Clock J4
91412: 05/11/05: Re: Clock J4
<johngreer2003@yahoo.com>:
156954: 14/08/04: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
JohnM:
37110: 01/11/30: Re: Modelsim
Johnny:
22123: 00/04/25: Re: Xilinx Virtex problem (schematic)
23728: 00/07/06: IBIS model for the XCV400E
57963: 03/07/11: wireless 802.11
Johnny Cavazos:
6268: 97/05/06: CFP: Computing Surveys Tutorial Paper Contest
Johnny Fu:
44499: 02/06/21: Logic Minimization in Max+Plus II compiler
44511: 02/06/21: Logic Minimization in Max+Plus II
Johnny Smooth:
13160: 98/11/18: Re: Synthesizeablel fifo
13188: 98/11/18: Re: Synthesizeablel fifo
13261: 98/11/22: Re: Synthesizeablel fifo
Johnny Wang:
40085: 02/02/26: Implementation failed cause of sourceless signals
40086: 02/02/26: Re: Implementation failed cause of sourceless signals
40088: 02/02/26: Is ISE3.1 a good one?
Johnnyick:
10070: 98/04/25: PLD & FPGA Conference and Exhibition 12/5/98
10212: 98/05/04: Reminder - The PLD & FPGA Conference & Exhibition 12/5/98
10256: 98/05/07: PLD & FPGA Conference & Exhibition 12/5/98
15895: 99/04/19: PLD & FPGA Conference and Exhibition 1999
16119: 99/05/04: PLD & FPGA Conference & Exhibition 12/05/99
<johnnynorthener@yahoo.co.uk>:
104198: 06/06/21: PCI Express - Root Complex Emulation
JohnOD:
136453: 08/11/17: Xilinx-3E Starter Kit - USB connection with Linux
136467: 08/11/18: Re: Xilinx-3E Starter Kit - USB connection with Linux
johnp:
77063: 04/12/21: Re: Programming Virtex II in slave select MAP mode?
81655: 05/03/29: Re: divide by 2^n, n=21..37 ==> 3 Virtex Slices !!
81789: 05/03/31: Re: newbie verilog question
82028: 05/04/05: Xilinx V2-Pro + Select Map programming
82061: 05/04/06: Re: Xilinx V2-Pro + Select Map programming
82170: 05/04/07: Re: Xilinx V2-Pro + Select Map programming
82488: 05/04/13: Re: Simulation and actual FPGA implementation, how different it is?
83395: 05/04/28: Re: Sync + FIFO
83412: 05/04/29: Re: Sync + FIFO
83475: 05/04/30: Re: VGA sync signals
83778: 05/05/06: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
83893: 05/05/09: Re: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
83968: 05/05/10: Re: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
84086: 05/05/12: Re: Looking for Rapid prototyping system, ?Quickturn ASIC-Emulator?
85306: 05/06/07: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
87543: 05/07/25: Virtex4 local clock timing
87733: 05/07/29: Re: Virtex4 local clock timing
87862: 05/08/02: Re: Programmable frequency synthesizer with Xilinx DCM
88193: 05/08/11: Re: Delays in verilog
88290: 05/08/14: Re: XST (ISE 6.1i): Error: It's interesting and surprising
88692: 05/08/25: Re: i need some help ASAP !!! (DLL - Spartan-IIE)
88919: 05/08/31: Re: Gated clock for FPGA (verilog)???
89134: 05/09/06: Re: Modelsim XE and multi-file Verilog projects
89263: 05/09/09: Re: Post synthesis simulation errors
89427: 05/09/14: Re: USB tranciever + controller in FPGA
89718: 05/09/23: Re: downlaoding bit files to Xilinx FPGA
89719: 05/09/23: Re: downlaoding bit files to Xilinx FPGA
90105: 05/10/04: Re: EasyPath, demystified
90336: 05/10/10: Re: Eliminates meta stability (yes or no)?
91031: 05/10/27: Re: ASIC HDL coding styles
91740: 05/11/11: Re: fastest possible USB
91939: 05/11/17: Re: Rise time/fall time for Spartan3 clock inputs
92074: 05/11/21: Re: Verilog Editor.
92107: 05/11/22: Disabling Xilinx clock enable usage...
92118: 05/11/22: Re: Disabling Xilinx clock enable usage...
92131: 05/11/22: Re: Disabling Xilinx clock enable usage...
92303: 05/11/26: Xilinx timing constraint question
92371: 05/11/28: Xilinx 'unconstrained period' problem
92441: 05/11/29: Re: Xilinx 'unconstrained period' problem
92562: 05/12/01: Re: Help : Code works in synthesizer (silos), but warnings w/ webpack
92578: 05/12/01: Re: Help : Code works in synthesizer (silos), but warnings w/ webpack
92786: 05/12/06: Re: Virtex 4 FIFO16 blocks - Corruption ?
93027: 05/12/12: Re: ISE = Intelligent Synthesis Expectable :-)
93246: 05/12/16: Re: Interfacing externally clocked data to an FPGA (Spartan 3)
93264: 05/12/16: Re: Interfacing externally clocked data to an FPGA (Spartan 3)
93347: 05/12/20: Re: More beginner's verilog questions
93348: 05/12/20: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93400: 05/12/21: Re: More beginner's verilog questions
93426: 05/12/21: Re: More beginner's verilog questions
93645: 05/12/27: USB 2.0 testbench available?
93661: 05/12/27: Re: USB 2.0 testbench available?
94429: 06/01/11: Webpack 8.1 device support
94432: 06/01/11: Re: Webpack 8.1 device support
94548: 06/01/13: WebPack 8.1 report viewing
95998: 06/01/27: Re: Virtex-4 ISERDES and ADS527X ADCs
96327: 06/02/01: Re: Die Area
96352: 06/02/02: Re: Die Area
96330: 06/02/01: Re: Spartan3 pullups
96328: 06/02/01: Re: Mixing and matching related clocks question.
97297: 06/02/20: Xilinx 8.1.02i map failure
97400: 06/02/21: Re: Xilinx 8.1.02i map failure
98257: 06/03/07: Re: recommendation for JTAG Boundary Scan software??
98331: 06/03/08: XST synthesis gripe/sub-optimization
98641: 06/03/13: Re: Why does Xilinx hate version control?
99291: 06/03/22: Xilinx RAM16_S9.V model syntax problem
99310: 06/03/22: Difference between Xilinx shift_extract and shreg_extract constraints?
99318: 06/03/22: Re: Xilinx RAM16_S9.V model syntax problem
99393: 06/03/23: Xilinx hi-speed interconnect/routing question
99399: 06/03/23: Re: Xilinx hi-speed interconnect/routing question
99451: 06/03/24: Re: Xilinx hi-speed interconnect/routing question
99561: 06/03/26: Re: Xilinx hi-speed interconnect/routing question
99880: 06/03/30: Re: USB Interface to Virtex-4
99916: 06/03/30: Re: USB Interface to Virtex-4
100022: 06/04/01: Re: KEEP_HIERARCHY
100023: 06/04/01: Re: USB Interface to Virtex-4
100043: 06/04/01: Re: KEEP_HIERARCHY
100514: 06/04/10: Re: Simulating TFT core in EDK
100943: 06/04/21: Xilinx Map & Physical Synthesis dies...
100951: 06/04/21: More Xilinx S/W problems... ISE won't start
100954: 06/04/21: Re: More Xilinx S/W problems... ISE won't start
101108: 06/04/25: Xilinx Map vs IOB tri-state with clock enable...
101110: 06/04/25: Re: Xilinx Map vs IOB tri-state with clock enable...
101367: 06/04/29: Re: Quartus and source control
101740: 06/05/05: Re: Quartus and source control
101833: 06/05/07: Re: Xilinx 3s8000?
101905: 06/05/08: Re: Programming the JTAG flash in circuit
102790: 06/05/20: Re: Signal 2 clocks long but only one clock possible
102845: 06/05/22: Re: Signal 2 clocks long but only one clock possible
102846: 06/05/22: Re: ispLEVER Starter 6.0 FPGA Design Software Available
102875: 06/05/22: Re: ispLEVER Starter 6.0 FPGA Design Software Available
102925: 06/05/23: Re: ISE 8.1SP4 PN doesnt start
102998: 06/05/24: Re: Signal 2 clocks long but only one clock possible
103901: 06/06/14: Re: Xilinx XST Error
103941: 06/06/15: Virtex2-Pro local clocking...
103989: 06/06/16: Re: Current from FPGA pins to ADC
103998: 06/06/16: Re: Virtex2-Pro local clocking...
104002: 06/06/16: Re: Virtex2-Pro local clocking...
104123: 06/06/19: Xilinx bitgen vs output file name
104289: 06/06/22: Xilinx RocketIO receiver reset problem
104290: 06/06/22: Re: Xilinx RocketIO receiver reset problem
104908: 06/07/09: Re: Mystery CLKDLL, IBUFG, BUFG modules in verilog src (ISE 6.3.03i)
105602: 06/07/26: Re: Which PCI core for Cyclone II board?
105653: 06/07/27: Re: Guided MAP/PAR in ISE
105828: 06/08/01: Re: Usage of DDR IOBs
106098: 06/08/07: Re: verilog versus vhdl
107604: 06/08/30: FPGA support for DDR3 and GDDR3
108281: 06/09/07: Re: RTL deisgn for Blocking and Nonblocking
109481: 06/09/27: Re: Pack registers (from submodule) into IOB for bidirectionnal signal
109696: 06/10/03: unexpected Xilinx TNM constraint behaviour
109808: 06/10/05: Re: a clueless bloke tells Xilinx to get a move on
113143: 06/12/06: Xilinx PAR crashing with 'make'
113545: 06/12/15: Xilinx PMCD+DCM reset question...
113549: 06/12/15: Re: Xilinx PMCD+DCM reset question...
113550: 06/12/15: Re: Xilins ISE Re-Creating Projects
113559: 06/12/16: Re: Simple questions on IDELAYCTRL vs DCM
113594: 06/12/17: Re: Xilins ISE Re-Creating Projects
113630: 06/12/18: Re: Simple questions on IDELAYCTRL vs DCM
113635: 06/12/18: Re: Simple questions on IDELAYCTRL vs DCM
113835: 06/12/23: Re: Simple questions on IDELAYCTRL vs DCM
115066: 07/01/30: Re: USB 2.0 Streaming using FPGAs
115206: 07/02/02: Re: ISE 9.1 SAY YOURS OPINION
115862: 07/02/22: Re: Using Xilinx DCM FX output without DLL
116688: 07/03/15: Re: Xilinx FPGA, OFFSET OUT AFTER
116712: 07/03/15: XIlinx 9.2 'partition' mode problem - s/w dies....
116750: 07/03/16: Re: Xilinx FPGA, OFFSET OUT AFTER
117745: 07/04/09: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
117751: 07/04/09: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
117862: 07/04/11: XST and Verilog $readmemh
117886: 07/04/12: Re: XST and Verilog $readmemh
119227: 07/05/15: Re: How low DDR2 Clock Frequency can be? To make it work on FPGA.
119601: 07/05/23: Project Navigator / Verilog / +define
119749: 07/05/25: Re: Use BRAM as ROM (Xilinx)
120608: 07/06/11: Re: Optical RocketIO
120639: 07/06/12: XIlinx tools question - how to quickly identify unconstrained paths
120641: 07/06/12: Re: XIlinx tools question - how to quickly identify unconstrained paths
120648: 07/06/12: Re: XIlinx tools question - how to quickly identify unconstrained paths
120844: 07/06/18: Re: want to pay for DCM active phase shift controller.
122614: 07/08/01: Re: Fatal Error ISE 9.1
123518: 07/08/29: Re: intialize memory in fpga
124089: 07/09/11: Re: Uses of Gray code in digital design
124665: 07/09/29: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
127219: 07/12/14: Re: `ifdef XST?
127413: 07/12/21: Re: sampling error between 2 clocks
127450: 07/12/26: Re: TechXclusives from Xilinx
127490: 07/12/28: Re: TechXclusives from Xilinx
128597: 08/01/31: Re: Xilinx BSCAN primitives proper use
128609: 08/01/31: Low Pin Count (LPC) bus code available?
128654: 08/02/01: Re: Low Pin Count (LPC) bus code available?
141650: 09/07/02: Re: USB Book
142840: 09/09/03: Re: Choice of Language for FPGA programming
142868: 09/09/04: Re: Choice of Language for FPGA programming
142962: 09/09/10: Re: UART testbench debug
143320: 09/10/01: Re: Up-counter with async load/clear and overflow detection (Verilog)
143328: 09/10/02: Re: Up-counter with async load/clear and overflow detection (Verilog)
144142: 09/11/13: Re: An incomplete Mux and Latch?
144151: 09/11/13: Re: An incomplete Mux and Latch?
144554: 09/12/14: Re: Does a 1-bit mux glitch if only one input is known to change at
144999: 10/01/19: Re: XST is driving me mad.
145665: 10/02/17: Re: Unpredictable design
145832: 10/02/25: Re: EDK spi ip core
145853: 10/02/25: Re: EDK spi ip core
149038: 10/09/23: Re: Xilinx dropping Modelsim XE
149476: 10/10/28: Re: FPGA and ethernet phy problem
149479: 10/10/28: Re: FPGA and ethernet phy problem
151033: 11/03/01: Re: Count bits in VHDL, with loop and unrolled loop produces
151546: 11/04/18: Re: Help with Verilog Code
151891: 11/06/01: Re: Random Reset calls
152278: 11/08/02: Re: DVI-decoder clock question
152342: 11/08/10: Verilog, VHDL, sync and async resets
153418: 12/02/21: Re: gigabit ethernet problem
153654: 12/04/10: Re: Data Transfer from PC to FPGA through USB
153709: 12/04/28: Re: VHDL syntheses timestamp
154044: 12/07/19: FPGA + HDMI 1080P
154054: 12/07/22: Re: FPGA + HDMI 1080P
Johnschool:
84521: 05/05/20: A Short Pulse Catcher
84541: 05/05/20: Re: A Short Pulse Catcher
84653: 05/05/24: Re: A Short Pulse Catcher
84788: 05/05/27: Re: A Short Pulse Catcher
101989: 06/05/09: Using vector condition at transition in StateCAD
<johnsimpson@postmaster.co.uk>:
17220: 99/07/10: MayanSports Sportsbook offers NASCAR & Golf betting
Johnson:
63488: 03/11/22: Aurora_401 reference allows 8B/10B bypass?
76209: 04/11/28: FPGA design sample for Compact Flash peripheral
76244: 04/11/29: Re: FPGA design sample for Compact Flash peripheral
76261: 04/11/29: How to subscribe to the newsgroup comp.arch.fpga
76277: 04/11/29: lowest-cost FPGA
76355: 04/11/30: Re: How to subscribe to the newsgroup comp.arch.fpga
76356: 04/11/30: Re: lowest-cost FPGA
76392: 04/12/01: Compact Flash Peripheral Design with FPGA
76406: 04/12/01: Sleep mode of Compact Flash Peripheral
76422: 04/12/01: Re: How to subscribe to the newsgroup comp.arch.fpga
142784: 09/09/01: Wants an update on FPGA development IDE/toolchains
142787: 09/09/01: Re: Wants an update on FPGA development IDE/toolchains
142849: 09/09/03: Re: Wants an update on FPGA development IDE/toolchains
142855: 09/09/03: Re: Wants an update on FPGA development IDE/toolchains
johnson edward eric:
3549: 96/06/19: Xilinx CLB allocation question
Johnson L:
139190: 09/03/22: Looking for a low-cost development kit
139213: 09/03/23: Re: Looking for a low-cost development kit
139233: 09/03/23: Re: Looking for a low-cost development kit
139234: 09/03/23: Re: Looking for a low-cost development kit
139235: 09/03/23: Re: Looking for a low-cost development kit
139265: 09/03/24: Re: Looking for a low-cost development kit
139302: 09/03/25: Re: Looking for a low-cost development kit
139910: 09/04/18: Re: Looking for a low-cost development kit
Johnson Lee:
75458: 04/11/06: Data Swtich from LPT to LCD Module!
75494: 04/11/07: Re: Data Swtich from LPT to LCD Module!
75508: 04/11/08: Re: Data Swtich from LPT to LCD Module!
75573: 04/11/09: Re: Data Swtich from LPT to LCD Module!
80698: 05/03/10: State Machine Coding?
80759: 05/03/10: Re: State Machine Coding?
Johnson Liuis:
78235: 05/01/26: lowest-cost FPGA and CPLD
86040: 05/06/20: FPGA Filter Design
86094: 05/06/21: Re: FPGA Filter Design
86404: 05/06/27: Re: FPGA Filter Design
Johnson Wu:
3532: 96/06/16: To subscribe
Johnsons. Joe:
83059: 05/04/22: Speed acceleration !!!
Johnsonw10:
31653: 01/06/01: Re: [Q]setup-time violation
34308: 01/08/20: Need help: CLKDLLE.v does not work in simulation.
36869: 01/11/22: Re: read only version register usinga generic
36873: 01/11/22: Re: Altera Quartus fork bus on block diagram
37932: 01/12/25: Re: Where could I get a signal waveform editor?
42037: 02/04/13: Re: synplify, quartus II 2.0
42148: 02/04/17: Re: Source code for a NIOS instruction set simulator?
<johnt246@yahoo.com>:
38136: 02/01/06: Celoxica DK1 and Handel C
<johnzulu>:
111084: 06/10/29: Re: i486 FPGA replacement
124654: 07/09/29: XUPV2P from digilentinc
124663: 07/09/29: Re: XUPV2P from digilentinc
124688: 07/09/30: Re: XUPV2P from digilentinc
124823: 07/10/06: Re: XUPV2P from digilentinc
124840: 07/10/06: Re: XUPV2P from digilentinc
Joji John:
66627: 04/02/24: SHARC 21062/21060 link port implementation on Virtex 2 FPGA
66628: 04/02/24: Re: SHARC 21062/21060 link port implementation on Virtex 2 FPGA
jok:
16139: 99/05/05: Bugs in place and route s/w....XLINX???
16918: 99/06/16: Re: Synopsys DC & Modelsim
17090: 99/06/29: Re: Exhaustedly I come for Digital PLL help
22012: 00/04/12: pci bus, critical path
Joko:
71666: 04/07/27: Re: IOBs in NGC - problem with OBUFT
Jolly Joker:
35485: 01/10/07: Re: Video processing
Jon:
33044: 01/07/16: Re: conditional expression optimization
33393: 01/07/25: Re: FPGA Express or Spectrum?
33395: 01/07/25: Re: In-Circuit Power Supply Verification of Xilinx Chips
33592: 01/07/31: Re: multi-context FPGA
34967: 01/09/17: Altera survey
42541: 02/04/26: 4005XL and 4010XL compatibility
42627: 02/04/29: Re: 4005XL and 4010XL compatibility
57870: 03/07/08: Re: Books
57918: 03/07/09: Re: how can I use a signal defined in one Architecture to another Architecture
58146: 03/07/15: Re: how to remove this error
63164: 03/11/17: Architecture desing using national serializer and deserialiser
68813: 04/04/19: Clock Enables and Power
73133: 04/09/14: Help with Coregen ROM in ISE 6.2.03i
94259: 06/01/09: Re: Help! FIR Filter - MATLAB fdatool - VHDL
96711: 06/02/09: Re: How to gnerate VCD file with hex outputs.
98423: 06/03/09: Problems with Output pins on XUP board
98719: 06/03/15: Re: DSP Builder @ System Generator
99470: 06/03/24: Re: Problems with Output pins on XUP board
100511: 06/04/10: Simulating TFT core in EDK
100516: 06/04/10: Re: Simulating TFT core in EDK
103406: 06/06/01: ModelSim: Different SimPrim libraries needed for different Xilinx families?
120592: 07/06/11: Re: System Generator vs Synplify DSP vs Simulink HDL Coder
141313: 09/06/17: Re: Do you know how aggressive the patent fighting between Xilinx and
142317: 09/08/04: Re: File I/O read in verilog
142429: 09/08/11: Re: algorithm implementation in IC
142496: 09/08/13: Re: JTAGkey-Tiny with Altera/Xilinx FPGA?
142607: 09/08/20: Re: FPGA to ASIC conversion
142886: 09/09/05: Re: Choice of Language for FPGA programming
143313: 09/10/01: Re: Implement ARM cores on a FPGA chip?
143324: 09/10/02: Re: Implement ARM cores on a FPGA chip?
143417: 09/10/10: Re: Development boards for CPU development ?
148106: 10/06/21: RAM issues with Plasma CPU on Nexys 2
148353: 10/07/14: Re: WTD: WISHBONE SDRAM interface or some Vlog HDL synthesizing...
153868: 12/06/15: Re: Fpga to Asic conversion, firm list and prices.
154085: 12/08/01: Re: how much costs the Artix 7 devices?
154197: 12/09/05: Re: Delay in Verilog for Asics design which is synthesizable
154350: 12/10/12: Re: ise 32b or 64b?
154355: 12/10/13: Re: My First CPU but.. one problem
154512: 12/11/22: Re: Set-up and hold times and metastability
154827: 13/01/16: Re: IP core implementation of multiplier on FPGA Spartan 3e
154960: 13/03/04: Re: Xilinx XST and initializing block RAMs
154974: 13/03/06: Re: Xilinx XST and initializing block RAMs
jon:
22758: 00/05/23: Actel Pro Asic ?
22757: 00/05/23: Actel Pro Asic ?
28268: 01/01/04: how do you design with + compile separate entity +architecture files
124562: 07/09/26: Stratix GX
124592: 07/09/27: Re: Stratix GX
128956: 08/02/11: XC5VLX85-2FFG1153C
128980: 08/02/12: Re: XC5VLX85-2FFG1153C
129786: 08/03/05: Virtex 5
130523: 08/03/26: Re: counterfeit Xilinx ?
131025: 08/04/08: Re: Conterfeit parts guidance
131962: 08/05/08: Virtex XCV1000E-6FG860C
132001: 08/05/09: Re: Virtex XCV1000E-6FG860C
133085: 08/06/17: Altera Cyclone II EP2C20F484C6N
133116: 08/06/18: Re: Altera Cyclone II EP2C20F484C6N
133802: 08/07/15: Xilinx Virtex 4
134365: 08/08/07: Altera Cyclone and Stratix II
134505: 08/08/14: 512MB DDR2 533mhz registered dimms
143687: 09/10/21: Stratix II
144108: 09/11/11: XC5VLX50-1FFG676C Virtex 5
144887: 10/01/12: XC2V2000-5FF896C or XC2V2000-6FF896C Virtex II
Jon Anderson:
99714: 06/03/28: EDK/Xilinx : Insertion of ECC capability into BRAM controller
Jon Beniston:
46150: 02/08/20: PS/2 Keyboard Interface in a Virtex-E
48335: 02/10/16: Re: Operations / sec FPGA v/s DSP
55678: 03/05/15: Re: Do Service Pack of Xilinx really fixed the problems?
55741: 03/05/18: Re: SID chip describtion
55787: 03/05/19: Re: downloading a VHDL design on a XSV board ?
55788: 03/05/19: Re: about simulation
55818: 03/05/20: Re: problem with modelsim 5.7d on winXP system
55999: 03/05/26: Re: Pos Phys L4
56032: 03/05/27: Re: Multiply 19.44MHz with Virtex-II DCM
57341: 03/06/27: Re: ASIC divider in FPGA?
57366: 03/06/28: Re: why so many problems Xilinx ?
57448: 03/06/30: Re: Benchmarking FPGA CPU's
61386: 03/10/02: MicroBlaze size
61428: 03/10/03: Re: MicroBlaze size
62675: 03/11/04: Re: Prototyping board with 4+ MB SRAM?
62778: 03/11/07: Re: ASIC speed
62779: 03/11/07: Re: Announcement
62780: 03/11/07: Re: Announcement
62781: 03/11/07: Re: Announcement
62808: 03/11/07: Re: Announcement
63057: 03/11/13: Re: linker script
63755: 03/12/03: 1.2V Voltage Regulators for Spartan III
64117: 03/12/17: Re: From ASIC to FPGA these days
66399: 04/02/18: Source code for NIOS GNU toolchain
66412: 04/02/19: Re: Source code for NIOS GNU toolchain
66419: 04/02/19: Microblaze instruction timings
66422: 04/02/19: Re: Source code for NIOS GNU toolchain
66449: 04/02/19: Re: Source code for NIOS GNU toolchain
66480: 04/02/20: Dhrystone figures - Was: Microblaze instruction timings
66528: 04/02/21: Re: Dhrystone figures - Was: Microblaze instruction timings
66575: 04/02/23: Re: Spartan 3 - avaliable in small quantities?
66614: 04/02/24: Re: Spartan 3 - avaliable in small quantities?
66618: 04/02/24: Spartan 3 / XCF02S JTAG problem
66636: 04/02/24: Re: Spartan 3 / XCF02S JTAG problem
66925: 04/03/01: Re: FPGA implementation of ARM and IA32 ISA
67400: 04/03/11: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67464: 04/03/12: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67466: 04/03/12: Re: Does XST handles //synopsys parallel_case?
67899: 04/03/22: Re: 64bit cpu on Xilinx
67947: 04/03/23: How many gates are required to implement a Xilinx slice
68480: 04/04/06: Re: Which HVL is the most popular?
68481: 04/04/06: Re: AHDL, VERILOG or VHDL??
69339: 04/05/07: Re: Which board to buy? Status of open source tools?
69387: 04/05/10: Re: Floating Point With Xilinx EDK (PPC)?
69431: 04/05/11: Re: One issue about free hardware
69441: 04/05/11: Re: Floating Point With Xilinx EDK (PPC)?
69442: 04/05/11: Re: Bootloader question
69477: 04/05/11: Re: One issue about free hardware
69511: 04/05/12: Re: One issue about free hardware
69569: 04/05/14: Re: One issue about free hardware
69589: 04/05/14: Re: best fpga development board?
69590: 04/05/14: Re: One issue about free hardware
69591: 04/05/14: Re: ISE 6.2i Synopsys Design Compiler libraries?
69599: 04/05/14: Re: One issue about free hardware
69608: 04/05/15: Re: One issue about free hardware
69690: 04/05/18: Re: Atmel Zigbee solutions
69709: 04/05/18: Re: Malfunctioning dual port block ram.
69718: 04/05/18: Re: Atmel Zigbee solutions
69749: 04/05/19: Re: Nios II Going Live...
69750: 04/05/19: Re: Initialize Blockram from file
69769: 04/05/19: Re: Malfunctioning dual port block ram.
69785: 04/05/19: Re: Atmel Zigbee solutions
69930: 04/05/25: Re: Nios II = Microblaze
69944: 04/05/25: Re: Nios II = Microblaze
69945: 04/05/25: Re: Nios II = Microblaze
69947: 04/05/25: Re: What can I do if my chip can't meet timing?
69965: 04/05/25: Re: Nios II = Microblaze
69967: 04/05/25: Re: Nios II = Microblaze
70324: 04/06/12: Re: Costs of IPs
70337: 04/06/13: Re: a newbie question
70634: 04/06/22: Re: Unused signals in Modelsim
70680: 04/06/23: Re: Division in Xilinx
70894: 04/07/01: Re: Xilinx $99 Spartan-3 kit
72342: 04/08/16: Re: xilinx Synthesis report - please help..
72377: 04/08/17: Re: New cache
72478: 04/08/20: Re: NIOS II Sim
72611: 04/08/26: Re: X propagation in Timing Simulation
72612: 04/08/26: Re: JTAG software
73754: 04/09/29: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
73853: 04/09/30: Re: MicroBlaze is now available as Open-Source!! (from independant 3rd party)
73933: 04/10/01: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
73934: 04/10/01: Re: FPGA vs ASIC area
73935: 04/10/01: Re: FPGA vs ASIC area
73967: 04/10/01: Re: FPGA vs ASIC area
73106: 04/09/14: Re: Virtex 4 released today
73146: 04/09/14: Re: Virtex 4 released today
73168: 04/09/15: Re: Virtex 4 released today
73503: 04/09/22: NIOS II / Cyclone II - Multiply, Barrel Shift and Divide
73557: 04/09/23: Re: How to design a programming parallel cable
73594: 04/09/24: Re: bin hot gray jedi encoding in ISE
73619: 04/09/26: Re: FPGA -> ASIC
73669: 04/09/27: Re: MicroBlaze & SRAM
74081: 04/10/03: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
74083: 04/10/03: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
74104: 04/10/04: Re: XST - undeterministic synthesis
74236: 04/10/06: Re: FPGA vs ASIC area -- the crucial issue is power consumption
74300: 04/10/07: Re: XILINX SHIPS ONE MILLION SPARTAN-3 FPGAS
74522: 04/10/13: Re: multiplexing clocks
74746: 04/10/18: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
74788: 04/10/19: Re: NI*S II-verilog in Virtex FPGA
75637: 04/11/11: Re: VHDL is correct but when burn into chip is not correct. Help me to solve this problem please
76300: 04/11/30: Re: Verilog newbie with clocking question
76376: 04/12/01: Re: 99% Utilisation !
77131: 04/12/24: Re: mb-gcc bug ?
77460: 05/01/07: Re: xil_printf not working as expected
77830: 05/01/18: Re: FPGA Board with RF Front end
77920: 05/01/20: Re: C programmer, what does this syntax mean?
79327: 05/02/17: Re: thread programming support in EDK?
79400: 05/02/18: Re: Question about microblaze C complier
79572: 05/02/21: Re: NIOS2 toolchain rebuild...
79860: 05/02/25: Re: NiosII Vs MicroBlaze
79884: 05/02/25: Re: NiosII Vs MicroBlaze
82047: 05/04/06: Re: ISA vs. patent/trademark
82125: 05/04/07: Re: Hey Xilinx
82128: 05/04/07: Re: ISA vs. patent/trademark
82589: 05/04/14: Re: tools used for ASIC synthesis
82590: 05/04/14: Re: Embedded MicroBlaze solution
82665: 05/04/15: Re: Soft CPU vs Hard CPU's
82788: 05/04/18: Re: Microblaze Functions (Xilinx Specific)
82806: 05/04/18: Re: Spartan 3E slower that Spartan 3?
82872: 05/04/19: Re: Soft CPU vs Hard CPU's
84078: 05/05/12: Re: Slice Virtex II = Equivalent gates ??
84530: 05/05/20: Re: Bullshit Achieves Literary Status
84537: 05/05/20: Re: Synopsys Designware IP... can be used for Xilinx FPGA??
84737: 05/05/25: Re: Synopsys Designware IP... can be used for Xilinx FPGA??
84753: 05/05/26: Re: Ethernet / digital logic questions
84758: 05/05/26: Re: ARC A4
84824: 05/05/28: Re: Synplify 8.1 vs. Quartus II 5.0 QoR
84921: 05/06/01: Re: How to speed up float computing
84952: 05/06/01: Re: How to speed up float computing
85146: 05/06/06: Re: Generating linker script for Altera desgn
85147: 05/06/06: Re: 32/16 divider, ASIC(Designware) Vs Xilinx FPGA(Coregen)
85150: 05/06/06: Re: Generating linker script for Altera desgn
85428: 05/06/09: Re: How to convert Matlab to HDL?
85492: 05/06/10: Re: Gated clock question
85871: 05/06/17: Re: comp.arch.fpga.<mfr>
86058: 05/06/21: Re: damage Atmel AT40k/AT94k with wrong bitstream?
86713: 05/07/05: Re: nios2 toolchain sources...
86753: 05/07/06: Re: fastest FPGA speed grade?
86754: 05/07/06: Re: nios2 toolchain sources...
86767: 05/07/06: Re: fastest FPGA speed grade?
87030: 05/07/13: Re: edif version generated by xilinx ISE 6.2
87569: 05/07/26: Re: Free 8 bit micro for fpga
87769: 05/08/01: Re: struggling with general digital design
87785: 05/08/01: Re: GNU Linker (MicroBlaze) / debugging problem
88442: 05/08/18: Re: Modelsim on a remote display
89087: 05/09/05: Re: bare die (non packaged) FPGA, CPLD, controllers ?
90868: 05/10/24: Re: EDK on Virtex4 FX using embedded ethernet MAC
91015: 05/10/27: Re: Cost to go from FPGA to ASIC
91140: 05/10/31: SystemACE parts wanted
91810: 05/11/14: Re: Viretx4 FX chip availability
91816: 05/11/14: Re: Viretx4 FX chip availability
92229: 05/11/24: Re: Wishbone comments
93285: 05/12/19: Re: where can i get a release copy of ISE 8i?
93567: 05/12/24: Re: re:Virtex-4FX and ethernet mac
94093: 06/01/05: Re: What kind of cpu is suit for me?
96347: 06/02/02: Re: BPSK modulation on Xilinx FPGA
97086: 06/02/16: Re: 8.1i SP2 download problems
97878: 06/03/01: Re: Microblaze on Spartan3
98663: 06/03/14: Re: Spartan 3 DCM
99691: 06/03/28: Re: Nios II - VHDL Source Code, Licensing
101451: 06/05/01: Re: Async FPGA ~2GHz
101474: 06/05/01: Re: Async FPGA ~2GHz
102389: 06/05/15: Re: Virtex 5 announced and sampling
102528: 06/05/17: SystemACE bootloader for PowerPC on Virtex4 FX
102544: 06/05/17: Re: SystemACE bootloader for PowerPC on Virtex4 FX
102556: 06/05/17: Re: SystemACE bootloader for PowerPC on Virtex4 FX
102559: 06/05/17: Re: SystemACE bootloader for PowerPC on Virtex4 FX
102627: 06/05/18: Re: SystemACE bootloader for PowerPC on Virtex4 FX
102628: 06/05/18: Re: SystemACE bootloader for PowerPC on Virtex4 FX
102688: 06/05/19: Re: Ethernet & ML401
102713: 06/05/19: Re: SystemACE bootloader for PowerPC on Virtex4 FX
102836: 06/05/22: Re: Have someone implementate the cpu86 or sparc embeded processor in the v-2 fpga
102944: 06/05/23: Re: Verilog vs VHDL
102946: 06/05/23: Re: Verilog vs VHDL
103392: 06/06/01: Xilinx MapLib:661 errors
104211: 06/06/21: Re: cache aware programming
104212: 06/06/21: Re: Actel FUSIN chips are real !
104419: 06/06/27: Re: Webpack ISE 8 and Vertex4 XC4VLX60
108428: 06/09/11: Re: simplyrisc-s1 free core
108904: 06/09/19: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109025: 06/09/20: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109028: 06/09/20: Re: Tools that support ECO
109061: 06/09/20: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109068: 06/09/20: Re: MicroFpga = program an FPGA as it would be a MCU !
109076: 06/09/20: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109155: 06/09/21: Re: NIOS speed
109156: 06/09/21: Re: Fast Platform for ISE?
109157: 06/09/21: Re: Are you ready for Virtex-5? We are...
109173: 06/09/21: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109175: 06/09/21: Re: Are you ready for Virtex-5? We are...
109181: 06/09/21: Re: Are you ready for Virtex-5? We are...
109182: 06/09/21: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109232: 06/09/22: Re: Fast Platform for ISE?
109234: 06/09/22: Re: Fast Platform for ISE?
109235: 06/09/22: Re: i2c,ahb,apb
109255: 06/09/22: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109425: 06/09/26: Re: Newbee question - how to upgrade to Xilinx ISE/EDK 8.2 from 8.1
109641: 06/10/02: Re: LatticeMico32 extremly poor performance without caches
109645: 06/10/02: Re: LatticeMico32 extremly poor performance without caches
109654: 06/10/02: Re: LatticeMico32 extremly poor performance without caches
109776: 06/10/05: Re: Are you ready for Virtex-5? We are...
109821: 06/10/05: Re: Virtex-5 FX when ?
110108: 06/10/11: Re: Xilinx MicroBlaze 4.00.a source codes released by Xilinx !?
110111: 06/10/11: Re: ARMv6 ISA doc required plz help
110208: 06/10/12: Re: LatticeMico32 extremly poor performance without caches
110239: 06/10/12: Re: Xilinx MicroBlaze 4.00.a source codes released by Xilinx !?
111657: 06/11/07: Re: ISE/EDK project on a file server?
111921: 06/11/13: Re: How to control the running of NC-Sim and Xilinx ISE under Unix?
112036: 06/11/15: Re: Software Compile : gcc command not found
112548: 06/11/24: Re: Verilog problem: default case to set signal xxxx
112563: 06/11/24: Re: Verilog problem: default case to set signal xxxx
112622: 06/11/26: Re: Mico32, how good is it?
112704: 06/11/27: Re: Mico32, how good is it?
112705: 06/11/27: Re: Mico32, how good is it?
112750: 06/11/28: Re: verilog 2 VHDL translator
112972: 06/12/03: Re: Buggy behaviour in Modelsim, when reading from pipe?
113023: 06/12/05: Re: Spartan-3A launched
113171: 06/12/07: Re: RTL Hardware design issue: Count Leading Zeros CLZ
113420: 06/12/13: Re: what are your current SoC design for ?
113421: 06/12/13: Re: Maplib Error 661.
113757: 06/12/20: Re: New user help required
113766: 06/12/20: Re: Soft processor Microblaze vs embedded core PowerPC
113782: 06/12/21: Re: XILKERNEL and MICROBLAZE (how to probe this)
113801: 06/12/22: Re: Virtex-II Pro: Reading/Writing data with Compact Flash
113955: 06/12/30: Re: (Improve Verilog skill) Recommend CPU core with good document and coding?
114032: 07/01/03: Re: FPGA-CPU THROUG ETHERNET
114121: 07/01/04: Re: LatticeMico32 Problem
114173: 07/01/06: Re: data transfer from fast APB clock domain.
114286: 07/01/10: Re: LWIP EXAMPLE??
114307: 07/01/11: Re: Interlock and stall in CPU design?
114408: 07/01/15: Re: SDK 8.2 error 127
114478: 07/01/17: Re: Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use
114511: 07/01/18: Re: ARM AHBA 1Kbyte boundary issue
114693: 07/01/23: Re: low speed USB interface for FPGAs
115508: 07/02/12: Re: Which is your favorite FPGA language?
115531: 07/02/13: Re: Which is your favorite FPGA language?
116253: 07/03/05: Re: EDK 9.1 when?
116274: 07/03/06: Re: EDK 9.1 when?
117041: 07/03/22: Re: softcore CPU tools
117773: 07/04/10: Re: SetJmp/LongJmp for Microblaze
118592: 07/04/30: Re: synthesis tools
118834: 07/05/04: Re: lwIP RAW mode support for V4 temac
118837: 07/05/04: Re: Select pullup, pulldown or none via embedded S/W
118838: 07/05/04: Re: Select pullup, pulldown or none via embedded S/W
120114: 07/06/01: Re: FIR ON FPGA
120294: 07/06/05: Re: Lattice XP2 finally announced
120308: 07/06/05: Re: How to Access CompactFlash by using SystemACE?
120445: 07/06/07: Re: verilog HDL problem
120580: 07/06/11: Re: synthesis - design compiler or synplify pro?
120702: 07/06/14: Re: synthesis - design compiler or synplify pro?
121082: 07/06/25: Re: corgen cic = terrible efficiency?
121267: 07/06/29: Re: Latches
121363: 07/07/03: Metastability in very slow clock domains
121373: 07/07/03: Re: Metastability in very slow clock domains
121374: 07/07/03: Re: Metastability in very slow clock domains
121375: 07/07/03: Re: Metastability in very slow clock domains
121470: 07/07/05: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121656: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121657: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121663: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121668: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121675: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121688: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121696: 07/07/11: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121793: 07/07/13: Re: Counter ?
121798: 07/07/13: Re: Counter ?
121816: 07/07/13: Re: Counter ?
121828: 07/07/13: Re: Counter ?
121839: 07/07/13: Re: Counter ?
121845: 07/07/13: Re: Counter ?
121872: 07/07/13: Re: Counter ?
122435: 07/07/27: Re: Best CPU platform(s) for FPGA synthesis
122448: 07/07/27: Re: Best CPU platform(s) for FPGA synthesis
122624: 07/08/01: Re: Static Timing Analysis Using Primetime for FPGAs
122649: 07/08/02: Re: Best CPU platform(s) for FPGA synthesis
122973: 07/08/13: Re: Xilinx 13th August opportunity
123009: 07/08/14: Re: xst fails...
123010: 07/08/14: Re: mixed Verilog/VHDL in ispLever 7.0 broken
123052: 07/08/15: Re: Multiplication Problem on Microblaze Software
123116: 07/08/16: Re: FPGA :'define not allowed in ISE ?
123311: 07/08/23: Re: comparison with embedded processor
123358: 07/08/24: Re: Implementing MIPS Memory Hiarchy
123364: 07/08/24: Re: Implementing MIPS Memory Hiarchy
123558: 07/08/30: Re: modelsim
123618: 07/08/31: Re: SDF File basics
123745: 07/09/03: Re: Low-level FPGA programming?
124305: 07/09/18: Re: Tristate bus on spartan FPGA
124519: 07/09/25: Re: Own soft-processor
124936: 07/10/11: Re: Compiler Options
125940: 07/11/09: Re: is marked OBSOLETE????
126177: 07/11/16: Re: Lattice Semi
127507: 07/12/30: Re: How to inhibit a timing warning
127649: 08/01/04: Re: converting floating point number to integer and vice versa
128045: 08/01/14: Re: sine and cosine wave generation
128161: 08/01/17: Re: effect of xray on fpga electronic circuits
128174: 08/01/17: Re: Chipscope compatible with Synopsis or Cadence sythesise tools?
129372: 08/02/22: Re: scanf problem in EDk 9.1i (Microbaze)
129381: 08/02/22: Re: Interview questions
130178: 08/03/17: Re: Wondering about "LatticeMico32 Open Source Licensing"
130179: 08/03/17: Re: Wondering about "LatticeMico32 Open Source Licensing"
130273: 08/03/19: Re: ISE 10.0 finally with multi-threading and SV support ?
130611: 08/03/28: Re: Sorry to Those Who Deem This to be Spam: Employment or
130779: 08/04/01: Re: now I can talk about it...
130785: 08/04/01: Re: now I can talk about it...
130961: 08/04/07: Re: system level language: why all this fuss about
131302: 08/04/18: Re: New to FPGA : Timing Closure
131757: 08/05/01: Re: ARM Cortex for Altera available
132304: 08/05/21: Re: Stratix IV Announced
132369: 08/05/23: Re: asic gate count
132479: 08/05/28: Re: HDL - simulation vs synthesis
132672: 08/06/05: Re: Xilinx cuts 250 jobs.
132759: 08/06/06: Re: Xilinx cuts 250 jobs.
132956: 08/06/11: Re: FPGA to solve the two most annoying problems on usenet -
133228: 08/06/21: Re: help using lwIP with xilinx EMAC
133269: 08/06/23: Re: FPGA based database searching
133860: 08/07/17: Re: UTMI
133885: 08/07/18: Re: verilog code
134039: 08/07/22: Re: help needed for Virtex-4
134076: 08/07/24: Re: Any good forum devoted to digital systems design?
134297: 08/08/05: Re: Altera sues Zilog - signs of desperation from Programmable Vendor
134315: 08/08/06: Re: Altera sues Zilog - signs of desperation from Programmable Vendor
134322: 08/08/06: Re: Altera sues Zilog - signs of desperation from Programmable Vendor
134324: 08/08/06: Re: Altera sues Zilog - signs of desperation from Programmable Vendor
134337: 08/08/06: Re: processor clk and bus clk in edk
134683: 08/08/26: Re: AES decryption (ASIC)
134685: 08/08/26: Re: AES decryption (ASIC)
134715: 08/08/27: Re: Genode FPGA graphics project launched
134729: 08/08/28: Re: Genode FPGA graphics project launched
134734: 08/08/28: Re: Genode FPGA graphics project launched
134735: 08/08/28: Re: Genode FPGA graphics project launched
134742: 08/08/28: Re: Genode FPGA graphics project launched
134743: 08/08/28: Re: Genode FPGA graphics project launched
134832: 08/09/03: Re: Open source licenses for hardware
134864: 08/09/04: Re: Open source licenses for hardware
134901: 08/09/05: Re: need sme help on data encryption based on fpga
134948: 08/09/08: Re: Signed multiplication
134955: 08/09/08: Re: Signed multiplication
135007: 08/09/10: Re: Can Soft microprocessor replace DSP's
135053: 08/09/12: Re: Quartus II compile speedup with New Quad Core Intel machine
135087: 08/09/15: Re: Moving to Altera from Xilinx
135101: 08/09/16: Re: Compiler Options
135111: 08/09/16: Re: Compiler Options
135642: 08/10/10: Re: Lattice vs Altera (Mico32 / NIOS)....or?
135648: 08/10/11: Re: Looking for a soft core 32 bit processor in VHDL
135751: 08/10/14: Re: Lattice vs Altera (Mico32 / NIOS)....or?
135809: 08/10/16: Re: CPU Model for Co-simulation
135824: 08/10/16: Re: Comparing power consumption of two different processor designs
135945: 08/10/23: Re: Soft core processor + CAD choose.Again
136215: 08/11/06: Re: TCP/IP 3 way handshake
136369: 08/11/13: Re: Virtex5 XC5VFX70T
136638: 08/11/27: Re: Caches & FPGAs
136791: 08/12/05: Re: Equivalent ASIC Gate Estimate
136990: 08/12/17: Re: LEON3 processor
137326: 09/01/08: Re: How to contact SiliconBlue ?
137869: 09/02/01: Re: Rotate video
138097: 09/02/06: Re: Experiencing problems when moving an FPGA-based implementation to
138265: 09/02/11: Re: Read a PS2 Keyboard input
143571: 09/10/16: Re: What is the basis on flip-flop replaced by a latch
143962: 09/11/05: Re: Cyclone IV announced
144459: 09/12/09: Re: Multiport BRAM for custom CPUs
144613: 09/12/21: Re: Please help, Xilinx FIFO problem!
146165: 10/03/07: Re: Question in verilog testbench
146351: 10/03/13: Re: Comparing FPGA with ASIC implementations
146494: 10/03/20: Re: Xilinx only on Avnet now
146934: 10/04/02: Re: Microblaze and DDR2
146973: 10/04/06: Re: A few LatticeMico32 questions
146976: 10/04/07: Re: A few LatticeMico32 questions
147202: 10/04/18: Re: Which 32 bit cores support full Linux?
147277: 10/04/21: Re: Quartus II under Windows7?
147373: 10/04/24: Re: Quartus II under Windows7?
147693: 10/05/17: Re: Spartan 6 schedule
147834: 10/05/26: Re: crc16 with 16 bit inputs
151723: 11/05/10: Re: Soft Processors and Licensing
153023: 11/11/16: Re: ASIC design job vs FPGA design job
153241: 12/01/16: Re: Effective square root algorithms implemented on FPGAs already
Jon C Russo:
108: 94/08/16: QuickTurn
Jon Cummings:
9585: 98/03/25: Digital Diplexers Exist?
9956: 98/04/17: Survey of RTOS?
10189: 98/05/03: Suggestions for micron sizing for diplexers
16610: 99/05/31: just a test - an ISP check
Jon Dohnson:
76236: 04/11/29: jtag / platform flash/ spartan 3 config questions
Jon Elson:
22272: 00/05/03: Re: How to Prevent theft of FPGA design
22273: 00/05/03: Re: How to Prevent theft of FPGA design
22363: 00/05/05: Re: edif
22387: 00/05/07: Re: edif
22415: 00/05/08: Re: Programming FPGA
22416: 00/05/08: Re: Virtex clock buffers
32745: 01/07/06: Re: Downloading FPGA (XBN) bitstream to XCV50E
38273: 02/01/10: Re: how do i program a Spartan FPGA
38274: 02/01/10: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
40762: 02/03/14: Re: Error in Foundation 4.1i
40763: 02/03/14: Re: How can I install Xilinx ISE 4.1i under Linux?
40764: 02/03/14: Re: high active and low active reset signal mixed in a design
40765: 02/03/14: Re: Virtex-II : Temperature Sensing Diodes
41316: 02/03/25: Re: Help with Xilinx CoolRunner Problem
41317: 02/03/25: Re: Poor availability problems on Coolrunner
41376: 02/03/26: Re: failure rate of Xilinx chips
41377: 02/03/26: Re: Help with Xilinx CoolRunner Problem
41424: 02/03/27: Re: XC9500 low temp. problem
44206: 02/06/13: Re: Xilinx JTAG verification failed
47366: 02/09/24: Re: MTBF
47367: 02/09/24: Re: FPGA fail when Electrostatic discharge Occurs
47536: 02/09/27: Re: My CPLD (XC9536) is overheated
47835: 02/10/04: Re: FPGA with an EPROM on it?
48592: 02/10/21: Re: Delay elements using the schematic editor (Xilinx)
50107: 02/12/02: ESD problems
50158: 02/12/03: Re: ESD problems
50197: 02/12/04: Re: ESD problems
50198: 02/12/04: Re: ESD problems
50199: 02/12/04: Re: FPGA Actual Power Measurement
56493: 03/06/06: Re: Protel DXP or other schematic entry?
56494: 03/06/06: Re: Xilinx Spartan download with Parallel III cable
56643: 03/06/10: Re: Pseudo random shift register - > DAC
56644: 03/06/10: Re: XC95288 programming problem
58012: 03/07/11: Re: Graduation Day: My first 4-layer PCB
58141: 03/07/15: Re: An All Digital Phase Lock Loop
58730: 03/07/31: Re: DDS question. How to generate a square from a sine wave?
58731: 03/07/31: Re: Parallel Port EPP in FPGA
58803: 03/08/01: Re: Size does matter
58804: 03/08/01: Re: How to use a TFT screen
58933: 03/08/04: Re: Gates Counting?
59193: 03/08/11: Xilinx ISE error
59453: 03/08/19: Re: Parallel interface to an FPGA
59558: 03/08/21: Re: Converstion from foundation4 to ISE 5.2
59559: 03/08/21: Re: Xilinx FPGA pin locking/assignment
59561: 03/08/21: EDIF input to Xilinx ISE
59599: 03/08/22: Re: Thinking out loud about metastability
59606: 03/08/23: Re: Thinking out loud about metastability
59648: 03/08/25: Re: EDIF input to Xilinx ISE
59667: 03/08/25: Re: Thinking out loud about metastability
59753: 03/08/27: Re: Max finding
59955: 03/09/02: Re: Xilinx Foundation Series 2.1i on Linux
59956: 03/09/02: Re: Parallel Cable III Problems
60034: 03/09/04: Re: How to extend a pulse width without clock!
60140: 03/09/05: Original (5V) Xilinx Spartan ?
60158: 03/09/05: Re: Original (5V) Xilinx Spartan ?
60159: 03/09/05: Re: Schematic simulation and then FPGA programming?
60160: 03/09/05: Re: Schematic simulation and then FPGA programming?
60447: 03/09/13: need help with Xilinx ISE 4.2i software
60448: 03/09/13: Re: Z-busses and synthesis
60503: 03/09/15: Re: need help with Xilinx ISE 4.2i software
60532: 03/09/16: Re: need help with Xilinx ISE 4.2i software
60556: 03/09/16: Xilinx source dragonsources
60618: 03/09/17: Re: Xilinx source dragonsources
60715: 03/09/19: Re: LVDS in Xilinx (Spartan-3)
60853: 03/09/23: Re: IEEE 1284 Core for Xilinx
60905: 03/09/24: Re: Regulator for Spartan 2
60906: 03/09/24: Re: IEEE 1284 Core for Xilinx
61439: 03/10/03: Re: Graphics rendering revisited
61667: 03/10/08: Re: Visualizing VHDL
61694: 03/10/09: Re: Visualizing VHDL
61784: 03/10/10: Re: Graphics rendering revisited
61785: 03/10/10: Re: Graphics rendering revisited
61892: 03/10/14: Re: Graphics rendering revisited
61893: 03/10/14: Re: Universities that focus on IC design
61895: 03/10/14: Re: Xilinx "Programming failed" message
62072: 03/10/17: Re: Xilinx "Programming failed" message
62199: 03/10/22: Re: 74 logic to CPLD. how easy for a Newbie?
62200: 03/10/22: Re: Altium DXP for designing Xilinx FPGA
62326: 03/10/27: Re: Configuration Blues
63070: 03/11/13: Re: using extra eeprom space
63105: 03/11/14: Re: Floating Point support
64072: 03/12/15: Re: Soldering of FPGAs
64074: 03/12/15: Re: Soldering of FPGAs
64423: 04/01/03: HDL Bencher question
64568: 04/01/07: Wierd problem with Xilinx XC9572 ID code
65463: 04/01/29: Re: Is FPGA fully static?
65815: 04/02/06: Re: Newbie question about VHDL & Xilinx CoolrunnerII kit...
65816: 04/02/06: Re: Do Xilinx Fix Their Prices?
66348: 04/02/17: Re: GZIP algorithm in FPGA
69665: 04/05/17: Re: load on a clock signal in FPGA
69666: 04/05/17: Re: Effects of moisture on CPLD
70026: 04/05/27: Re: What can I do if my chip can't meet timing?
70482: 04/06/17: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
71580: 04/07/22: Re: Xilinx XC9500 CPLD internal pull-up??
73141: 04/09/14: Re: Adding a Delay2
76006: 04/11/22: Re: Spartan-3 configuring problem
76347: 04/11/30: Re: two I/O markers on the same wire
77035: 04/12/20: Re: PLCC84
77387: 05/01/05: Re: Spartan-3 PQ/TQ/VQ SSO guidelines
77545: 05/01/10: Re: Xilinx CPLD configuration under Linux ?
77995: 05/01/21: Re: Configuring FPGA using PROM/uP
78532: 05/02/02: Re: Temat:Re: Actel A54SX72A - FF with clear and preset? Necessary
78596: 05/02/03: Re: Source of reset for synchronous reset can lead to metastability?
78993: 05/02/10: Re: Source of reset for synchronous reset can lead to metastability?
80324: 05/03/03: Re: making an fpga hot - addendum
80595: 05/03/08: SPROM for Spartan II
80731: 05/03/10: Re: SPROM for Spartan II
80732: 05/03/10: Re: SPROM for Spartan II
80824: 05/03/11: Re: SPROM for Spartan II
80827: 05/03/11: Re: XC3000 non-recoverable lockup problem
81784: 05/03/31: Re: Achieving required speed in Virtex-II Pro FPGA
84625: 05/05/23: Re: VHDL vs. Schematic Capture
84810: 05/05/27: Re: VHDL vs. Schematic Capture
85388: 05/06/08: Re: Pissed off with Xilinx - Spartan 3
85676: 05/06/13: Re: General gripe session ....
86092: 05/06/21: Re: FPGA Filter Design
87092: 05/07/14: Re: Virtex 300: what could cause pin to short?
89663: 05/09/21: Re: Xilinx Webpack Schematic
90382: 05/10/11: Re: Question regarding FPGA startup ROMs
90383: 05/10/11: Re: converting 12v signal to 3.3v
90736: 05/10/19: Re: Implementation of 1024 point FFT in Actel FPGA
91054: 05/10/27: Re: Cost to go from FPGA to ASIC
91609: 05/11/09: Re: old xilinx components
91610: 05/11/09: Re: old xilinx components
91611: 05/11/09: Re: Suggestions/Recommendations with CPLD's and Software
91612: 05/11/09: Re: Delay insertion in Xilinx Verilog
91912: 05/11/16: Re: RoHS
92435: 05/11/29: Re: Q-bus or Unibus bus transactions in FPGA?
92511: 05/11/30: Re: Q-bus or Unibus bus transactions in FPGA?
92512: 05/11/30: Re: Q-bus or Unibus bus transactions in FPGA?
93103: 05/12/13: Re: xilinx constraint
93371: 05/12/20: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar
93429: 05/12/21: Re: Patents and (possible) Plagiarism, Anyone ever been in a similarsituation?
93795: 05/12/30: Re: Going insane - Xilinx VGA controller...
93947: 06/01/03: Re: Clock generation
94579: 06/01/13: Re: How to create a delay BUF?
94581: 06/01/13: Re: FPGA Journal Article
96214: 06/01/31: Re: Wanted Help on All Digital PLL
98252: 06/03/07: Re: Xilinx LVDS
98354: 06/03/08: Re: 5v Xilinx development board
98618: 06/03/13: Re: Soldering SMT/BGA
98627: 06/03/13: Re: Soldering SMT/BGA
98629: 06/03/13: Re: Soldering SMT/BGA
99380: 06/03/23: Re: this JTAG thing is a joke
99906: 06/03/30: Re: Xilinx Schematic Entry
100749: 06/04/17: Re: Petition about the xilinx online store ?
100811: 06/04/18: Re: Where is the xilinx online store gone?
100900: 06/04/20: Re: Reliability CPLD/FPGA vs Microcontroller
100902: 06/04/20: Re: Multiple Independent Circuits on a Single FPGA
101228: 06/04/27: Re: How are constants stored ?
101673: 06/05/04: Re: New To FPGA, Program question
101675: 06/05/04: Re: CPU resource type
102878: 06/05/22: Re: Building a board with Spartan 3 FPGA.
103431: 06/06/01: Re: clockless arbiters on fpgas?
105546: 06/07/25: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
108660: 06/09/14: Re: Spartan3: Multiplier Madness
108662: 06/09/14: Need a couple XCS30-3TQ144C
108734: 06/09/15: Re: problems with IOSTANDARD
108735: 06/09/15: Re: Spartan3 driving mosfets
109556: 06/09/28: Re: Configuration of Spartan 3 devices
110925: 06/10/25: Re: OT: FPGA soft-core humor
111242: 06/10/31: Need just a few 5V Spartan
111288: 06/11/01: Re: Need just a few 5V Spartan
111289: 06/11/01: Re: Need just a few 5V Spartan
111323: 06/11/01: Re: Need just a few 5V Spartan
111324: 06/11/01: Re: Need just a few 5V Spartan
111349: 06/11/01: Re: Need just a few 5V Spartan
111350: 06/11/01: Re: Need just a few 5V Spartan
111418: 06/11/02: Re: Need just a few 5V Spartan
111671: 06/11/07: Re: Need just a few 5V Spartan
111782: 06/11/09: Re: Need just a few 5V Spartan
111968: 06/11/13: Re: Need just a few 5V Spartan
112071: 06/11/15: Re: 8080 FSGA model in an FPGA
112130: 06/11/16: Re: 8080 FSGA model in an FPGA
112131: 06/11/16: Re: 8080 FSGA model in an FPGA
112340: 06/11/20: Re: 8080 FSGA model in an FPGA
112699: 06/11/27: Re: run a counter without a clock
114051: 07/01/03: Re: Surface mount ic's
114734: 07/01/23: Re: FPGA damage from bad bitstream
114822: 07/01/24: Re: FPGA damage from bad bitstream
114932: 07/01/26: Re: Does xiling cpld's need a power supply bypass cap?
115025: 07/01/29: Re: Minimal design for xilinx?
115510: 07/02/12: Re: Problem with floating inputs on LVDS ports
115691: 07/02/16: Re: Do you like Virtex-5 ?
115693: 07/02/16: Re: Do you like Virtex-5 ?
115695: 07/02/16: Re: Do you like Virtex-5 ?
115756: 07/02/19: Re: Do you like Virtex-5 ?
117539: 07/04/03: Re: FPGA with 5V and PLCC package
117540: 07/04/03: Re: FPGA with 5V and PLCC package
117541: 07/04/03: Re: FPGA with 5V and PLCC package
117542: 07/04/03: Re: FPGA with 5V and PLCC package
117543: 07/04/03: Re: Config PROM for Spartan II
121992: 07/07/17: Xilinx XC9536 current draw ?
122015: 07/07/17: Re: Xilinx XC9536 current draw ?
122018: 07/07/17: Re: Xilinx XC9536 current draw ?
122035: 07/07/17: Re: Xilinx XC9536 current draw ?
122037: 07/07/17: Re: Xilinx XC9536 current draw ?
122044: 07/07/18: Re: Xilinx XC9536 current draw ?
122125: 07/07/19: Re: Can multiple Ferrite Beads be used to connect ...?
122336: 07/07/25: Re: Beginners question
123280: 07/08/22: Re: MCS -> BIT
123363: 07/08/24: Re: xilinx impact 9.2 problem
123829: 07/09/05: Re: Multiple CPLDs on a PCB.
124334: 07/09/18: Re: Altera / Lattice / Xilinx CPLDs ?
124488: 07/09/24: Re: Gated Clock Problems
124489: 07/09/24: Re: Gated Clock Problems
124490: 07/09/24: Re: Gated Clock Problems
124596: 07/09/27: Re: Never buy Altera!!!!
124598: 07/09/27: Re: Never buy Altera!!!!
124636: 07/09/28: Re: Never buy Altera!!!!
124637: 07/09/28: Re: Never buy Altera!!!!
124706: 07/10/01: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124707: 07/10/01: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124708: 07/10/01: Re: FPGA NTSC signal with 2 resistors and PWM
124927: 07/10/10: Re: FPGA tools under VMware or Parallels on a Mac?
125341: 07/10/22: Re: microprocessor on fpga problems
125843: 07/11/06: Re: not totally repulsive
126557: 07/11/27: Re: CPU design uses too many slices
126632: 07/11/28: Re: CPU design uses too many slices
126633: 07/11/28: Re: CPU design uses too many slices
126634: 07/11/28: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
128998: 08/02/12: Re: My first verilog/cpld project
129058: 08/02/13: Re: My first verilog/cpld project
129059: 08/02/13: Re: When are FPGAs the right choice?
129119: 08/02/14: Re: Virtex-4 input pad failures
129263: 08/02/19: Re: FPGA Programming solution
129264: 08/02/19: Re: FPGA Programming solution
129310: 08/02/20: Re: FPGA Programming solution
129402: 08/02/22: Re: FPGA Programming solution
130040: 08/03/13: Re: Danger of having JTAG TAP controller always enabled in Xilinx
130431: 08/03/23: counterfeit Xilinx ?
130441: 08/03/24: Re: counterfeit Xilinx ?
130493: 08/03/25: Re: counterfeit Xilinx ?
130508: 08/03/25: Re: counterfeit Xilinx ?
130509: 08/03/25: Re: counterfeit Xilinx ?
130535: 08/03/26: Re: counterfeit Xilinx ?
130551: 08/03/26: Re: counterfeit Xilinx ?
130582: 08/03/27: Re: counterfeit Xilinx ?
130827: 08/04/02: Re: async clk input, clock glitches
130828: 08/04/02: Re: async clk input, clock glitches
130854: 08/04/03: Re: counterfeit Xilinx ?
130905: 08/04/04: Re: counterfeit Xilinx ?
130973: 08/04/07: Re: counterfeit Xilinx ?
130974: 08/04/07: Re: counterfeit Xilinx ?
131032: 08/04/08: Re: Intel plans to tackle cosmic ray threat (actually they have been
131033: 08/04/08: Re: Intel plans to tackle cosmic ray threat (actually they have been
131035: 08/04/08: Re: Intel plans to tackle cosmic ray threat (actually they have been
131478: 08/04/22: Need a few Xilinx Spartan FPGAs
131664: 08/04/28: Re: Nano transistor breakthrough?
132006: 08/05/09: Re: 5 V oscillator output to GCLK
132122: 08/05/14: Re: Yay! We're done with the quadrature encoder!
132257: 08/05/19: bizarre state machine behavior
132289: 08/05/20: Re: bizarre state machine behavior
132317: 08/05/21: Re: bizarre state machine behavior
132318: 08/05/21: Re: bizarre state machine behavior
132320: 08/05/21: Re: Every newbie's favorite project: the Quadrature Rotary Encoder
132968: 08/06/11: Re: New Home
134205: 08/07/30: Re: Spartan-3A DSP 1800A Dev Board JTAG Cable and Programming Software
134664: 08/08/25: need fast FPGA suggestions
134671: 08/08/25: Re: need fast FPGA suggestions
134672: 08/08/25: Re: need fast FPGA suggestions
134690: 08/08/26: Re: need fast FPGA suggestions
134716: 08/08/27: Re: need fast FPGA suggestions
134717: 08/08/27: Re: need fast FPGA suggestions
134718: 08/08/27: Re: need fast FPGA suggestions
134746: 08/08/28: Re: need fast FPGA suggestions
134747: 08/08/28: Re: need fast FPGA suggestions
135189: 08/09/19: WebPack on CentOS 5 ?
135227: 08/09/22: Re: WebPack on CentOS 5 ?
135228: 08/09/22: Re: Random Mask Generation on FPGAs
135463: 08/10/02: Re: WEBPACK for linux
136180: 08/11/04: Re: Tiny JTAG connector
136777: 08/12/04: Re: Query on Xilinx Nomenclature
136798: 08/12/05: Re: Query on Xilinx Nomenclature
137184: 08/12/30: Re: FPGA > ASIC
139372: 09/03/27: Re: FIFO controlled loop, PLL, FLL or something else?
139631: 09/04/07: Re: Modulo-10 counter
139672: 09/04/08: Re: ANN: Antti-Brain March issue released
140486: 09/05/14: Xilinx 5V FPGA available from distributors again???
140487: 09/05/14: Re: cheapest FPGA?
140517: 09/05/15: Re: Xilinx 5V FPGA available from distributors again???
141535: 09/06/26: Re: Error while downloading prodram on CPLD
141607: 09/06/29: Re: Error while downloading prodram on CPLD
141876: 09/07/14: Re: pullup
141877: 09/07/14: Re: pullup
141977: 09/07/20: Xilinx WebPack 10.1 ISIM under Linux ?
141983: 09/07/20: Re: Xilinx WebPack 10.1 ISIM under Linux ?
142676: 09/08/25: Re: Timing properties of FPGA devices at sub-clock frequencies
142793: 09/09/01: Re: program spartan3 under linux
142794: 09/09/01: Re: program spartan3 under linux
142878: 09/09/04: Re: program spartan3 under linux
144007: 09/11/06: Re: OK Xilinx users, it's time I was let in on the joke...
144135: 09/11/12: Re: max. sinking current of XC95144xl cpld
145844: 10/02/25: Re: using an FPGA to emulate a vintage computer
146204: 10/03/08: Re: Tabula. (FPGA start up)
146288: 10/03/10: Re: Tabula. (FPGA start up)
146289: 10/03/10: Re: Tabula. (FPGA start up)
146720: 10/03/26: Re: PROM for Spartan 6 FPGA
146721: 10/03/26: Re: PROM for Spartan 6 FPGA
147227: 10/04/19: Re: Strange problem about Virtex-5 during working
147496: 10/04/28: Re: xilinx arm finally announced
147662: 10/05/13: Re: New 'standard' compact programming header needed!
148510: 10/07/28: Re: Overheated FPGA? (Spartan-3E)
148593: 10/08/04: Re: A question from a VHDL beginner
149027: 10/09/21: Re: Xilinx XST and a State Machine - A Mystery
149138: 10/10/04: Re: Actel bought by Microsemi
149534: 10/11/02: Re: 0x80000000 Integer not supported??
149568: 10/11/05: Re: PCI Parallel port detection in XILINX
149678: 10/11/16: Re: cool BGA pattern
149804: 10/11/24: Re: Atom 6000C perspective, anyone?
149907: 10/12/01: Re: Atom 6000C perspective, anyone?
149908: 10/12/01: Re: Atom 6000C perspective, anyone?
150275: 11/01/07: Re: OT: Fast Circuits
150276: 11/01/07: Re: spartan 3 xc3s1000 not getting programmed
150445: 11/01/21: Re: Overview for non-technicals.
150482: 11/01/24: Re: Xilinx news
150628: 11/01/28: Re: Simple clock question
150651: 11/01/31: Re: Can't program Spartan3A with JTAG
150796: 11/02/11: Re: Trivia: Where are you on the HDL Map?
150937: 11/02/23: how to keep iSE from grounding unused pins
150938: 11/02/23: How to keep iSE from grounding pins
150939: 11/02/23: Re: How to keep iSE from grounding pins
150978: 11/02/25: Re: How to keep iSE from grounding pins
151056: 11/03/02: Re: Xilinx Parallel cable III 3V3 and current impact version?
151072: 11/03/03: Re: Xilinx Parallel cable III 3V3 and current impact version?
151085: 11/03/04: Re: Xilinx Parallel cable III 3V3 and current impact version?
151480: 11/04/12: Re: Source of Dynamic Power Consumption in FPGAs
151495: 11/04/13: Re: Source of Dynamic Power Consumption in FPGAs
151679: 11/05/05: ise 10.1 (Linux) contraints problem
151689: 11/05/05: Re: ise 10.1 (Linux) contraints problem
151692: 11/05/05: Re: ise 10.1 (Linux) contraints problem
151698: 11/05/06: Re: ise 10.1 (Linux) contraints problem
151707: 11/05/08: Re: ise 10.1 (Linux) constraints problem
151906: 11/06/02: Re: FFT using logic gates only
152115: 11/07/09: VHDL rollover of counter
152119: 11/07/10: Re: VHDL rollover of counter
152121: 11/07/10: Re: VHDL rollover of counter
152357: 11/08/11: Re: Help needed to emulate a microcontroller.
152371: 11/08/12: Re: Help needed to emulate a microcontroller.
152557: 11/09/14: Xilinx Tin Whiskers ?
152560: 11/09/14: Re: Xilinx Tin Whiskers ?
152578: 11/09/15: Re: Xilinx Tin Whiskers ?
152579: 11/09/15: Re: Xilinx Tin Whiskers ?
152582: 11/09/15: Re: Xilinx Tin Whiskers ?
152614: 11/09/18: Re: Xilinx Tin Whiskers ?
152620: 11/09/18: Re: Xilinx Tin Whiskers ?
152640: 11/09/19: Re: Xilinx Tin Whiskers ?
152641: 11/09/19: Re: Xilinx Tin Whiskers ?
152728: 11/10/12: Spartan changes in glitch sensitivity
152733: 11/10/13: Re: Spartan changes in glitch sensitivity
152740: 11/10/15: Re: Spartan changes in glitch sensitivity
152741: 11/10/15: Re: Spartan changes in glitch sensitivity
152742: 11/10/15: Re: Spartan changes in glitch sensitivity
152784: 11/10/21: Re: Peter Alfke has passed away
152787: 11/10/22: Re: Peter Alfke has passed away
152788: 11/10/22: Re: FPGA development
152799: 11/10/24: Re: Spartan changes in glitch sensitivity
152818: 11/10/25: Re: Spartan changes in glitch sensitivity
153063: 11/11/24: Re: XC7V2000T, the perfect Thanksgiving gift
153120: 11/12/07: Re: Horsepower On Tap
153148: 11/12/12: Re: D-Type Flip flop with negated Q in Webise for a schematic capture
153522: 12/03/23: Spartan 3A counter speed ?
153534: 12/03/26: Re: Spartan 3A counter speed ?
153570: 12/03/28: Re: FPGA communication with a PC (Windows)
153574: 12/03/30: Re: Spartan 3A counter speed ?
153575: 12/03/30: Re: Spartan 3A counter speed ?
153660: 12/04/10: strange letter from Xilinx
153667: 12/04/11: Re: strange letter from Xilinx
153671: 12/04/12: Re: strange letter from Xilinx
153809: 12/05/24: Re: Logic Glitches in Spartan-3?
153822: 12/05/29: Re: EDK problems
153840: 12/06/01: Re: PRNG
153845: 12/06/04: Re: Questions about LCMXO2280-B-EVN and LCMXO2-1200ZE-B-EVN ev kits
153903: 12/06/28: Re: Replacement for XC4005E
153917: 12/06/29: Re: Replacement for XC4005E
153977: 12/07/06: XC9500XL keeper ?
153980: 12/07/06: Re: XC9500XL keeper ?
154007: 12/07/10: Re: accumulator (again)
154030: 12/07/13: Re: Completely puzzled: Strange shift register behaviour
154042: 12/07/19: Re: Xilinx UCF: Adding "Virtual Grounds"
154049: 12/07/21: Re: FPGA basic devtool options and prices?
154058: 12/07/23: Re: Interface Xilinx KC705 to BeagleBone?
154059: 12/07/23: Re: Interface Xilinx KC705 to BeagleBone?
154060: 12/07/23: Re: Interface Xilinx KC705 to BeagleBone?
154101: 12/08/07: Re: Burn to an internal prom Spartan-3an
154111: 12/08/09: Spartan 3AN prevent readback ?
154112: 12/08/09: Re: Spartan 3AN prevent readback ?
154115: 12/08/10: Re: Spartan 3AN prevent readback ?
154118: 12/08/10: Re: Spartan 3AN prevent readback ?
154129: 12/08/15: Re: "Decimals" word in binary space
154220: 12/09/10: Re: Looking for an extremely cheap FPGA board (in quantity, academic use)
154227: 12/09/11: Re: New(?) fast binary counter for FPGAs without carry logic (e.g. Actel) -- Request For Comment
154248: 12/09/13: Re: Looking for an extremely cheap FPGA board (in quantity, academic use)
154256: 12/09/17: Re: Looking for an extremely cheap FPGA board (in quantity, academic use)
154303: 12/09/24: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
154388: 12/10/19: production life of Spartan3A ?
154396: 12/10/24: Re: production life of Spartan3A ?
154401: 12/10/25: Re: production life of Spartan3A ?
154404: 12/10/26: Re: production life of Spartan3A ?
154406: 12/10/26: Re: production life of Spartan3A ?
154420: 12/10/27: Re: Altera delivery
154506: 12/11/20: Spartan 3A startup
154507: 12/11/20: Re: Spartan 3A startup
154508: 12/11/21: Re: Spartan 3A startup
154520: 12/11/22: Re: Spartan 3A startup
154521: 12/11/22: Re: Set-up and hold times and metastability
154533: 12/11/24: Re: Set-up and hold times and metastability
154550: 12/11/26: Re: Set-up and hold times and metastability
154669: 12/12/14: Re: MII SFD Detection with Shematics
154726: 12/12/29: Re: Chisel as alternative HDL
154730: 12/12/30: Re: Chisel as alternative HDL
154895: 13/01/31: Re: Combination loops and false paths
154957: 13/03/03: EPROM programmer erase
154978: 13/03/08: Re: EPROM programmer erase
154996: 13/03/23: pullup in Xilinx ISE 10.1
154997: 13/03/24: Re: pullup in Xilinx ISE 10.1
155030: 13/04/01: Re: MISC - Stack Based vs. Register Based
155369: 13/06/24: Re: Chasing Bugs in the Fog
155620: 13/07/30: Re: Lattice Announces EOL for XP and EC/P Product Lines
155623: 13/07/30: Re: Lattice Announces EOL for XP and EC/P Product Lines
155633: 13/07/30: Re: Lattice Announces EOL for XP and EC/P Product Lines
155654: 13/07/31: Re: Lattice Announces EOL for XP and EC/P Product Lines
155744: 13/08/25: Re: Synthesis and mapping of ALU
155945: 13/10/18: Re: Zynq devices, boards and suppliers
156030: 13/11/11: legacy Xilinx software
156033: 13/11/11: Re: legacy Xilinx software
156038: 13/11/12: Re: legacy Xilinx software
156041: 13/11/12: Re: legacy Xilinx software
156049: 13/11/13: Re: legacy Xilinx software
156062: 13/11/21: Re: legacy Xilinx software
156092: 13/11/22: Re: FPGA Cryptosystem
156094: 13/11/22: Re: Granularity of components for FPGA synthesis?
156100: 13/11/22: Re: legacy Xilinx software
156283: 14/02/05: Re: Xilinx Xpower Issues - Help from xilinx team please
156337: 14/03/11: Re: Ball-park price of Xilinx Virtex 7 FPGA?
156506: 14/04/11: Re: ERROR:MapLib:93 - Illegal LOC on IPAD symbol "autman" or BUFGP symbol "autman_BUFGP" (output signal=autman_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site.
156684: 14/06/03: Re: ECG signals Compression/Decompression
156892: 14/07/22: Re: Generating a desired synthesizable binary pulse train on FPGA using VHDL
156893: 14/07/22: Re: Generating a desired synthesizable binary pulse train on FPGA using VHDL
156960: 14/08/07: Re: strange effect with tristate output
156990: 14/08/13: Re: LVDS problem - Black magic anyone?
156995: 14/08/14: Re: LVDS problem - Black magic anyone?
157064: 14/09/19: Re: NetCPU or DotNetCPU DB200 anyone?
157249: 14/11/07: Re: Linux USB JTAG Cable Driver for Xilinx Impact
157380: 14/12/02: Re: Which Altera to buy?
157413: 14/12/03: Re: Which Altera to buy?
157414: 14/12/03: Re: Which Altera to buy?
157737: 15/02/25: Re: Program Xilinx with Altera JTAG Programmer?
157746: 15/02/27: Re: Program Xilinx with Altera JTAG Programmer?
157747: 15/02/27: Re: Program Xilinx with Altera JTAG Programmer?
158209: 15/09/14: Re: low-level vs. high-level
158214: 15/09/15: Re: low-level vs. high-level
158224: 15/09/25: Xilinx Spartan2E options?
158227: 15/09/25: Re: Xilinx Spartan2E options?
158245: 15/09/28: Re: Xilinx Spartan2E options?
158298: 15/10/05: Re: System On Chip From Microsemi
158323: 15/10/21: Re: recovery/removal timing
158338: 15/10/22: Re: recovery/removal timing
158383: 15/10/25: Re: Found: an FPGA with internal tri-states
158387: 15/10/26: Re: Found: an FPGA with internal tri-states
158556: 15/12/23: Re: FPGA for a beginner
158600: 16/01/20: Re: Fully preposterous gate arranger
158616: 16/02/03: Re: watermarking on FPGA
158632: 16/02/11: Re: EPM240T100C5N, LM2596, USB Blaster.
158654: 16/02/27: Re: VQ44 recommended footprint
158685: 16/03/07: Re: How to define a counter whose width is big enough to hold integer 27?
158744: 16/04/06: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158745: 16/04/06: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158747: 16/04/06: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158758: 16/04/07: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158759: 16/04/07: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158760: 16/04/07: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158767: 16/04/07: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158768: 16/04/07: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158774: 16/04/07: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158781: 16/04/08: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158782: 16/04/08: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158783: 16/04/08: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158784: 16/04/08: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158788: 16/04/08: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158789: 16/04/08: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158851: 16/05/11: Re: Watchdog Timers for FPGA Designs
158855: 16/05/11: Re: Watchdog Timers for FPGA Designs
159156: 16/08/26: Re: Low End FPGAs
159160: 16/08/26: Re: Low End FPGAs
159161: 16/08/26: Re: Low End FPGAs
159255: 16/09/08: Re: Low End FPGAs
159467: 16/11/20: Re: Tools on Linux
159551: 16/12/14: Re: Linux OS for FPGA worth
159596: 17/01/15: Re: I/O switching speed of Xilinx spartan 6 or Altera EP4CE10
159618: 17/01/18: Re: I/O switching speed of Xilinx spartan 6 or Altera EP4CE10
159644: 17/01/25: Re: Anyone use 1's compliment or signed magnitude?
159752: 17/02/24: Re: designing a fpga
159755: 17/02/24: Re: designing a fpga
159774: 17/02/27: Re: designing a fpga
159776: 17/03/01: Re: designing a fpga
159785: 17/03/03: Re: designing a fpga
159790: 17/03/03: Re: designing a fpga
160003: 17/05/10: Re: Lattice iCE40 UltraLite DIPSY - what happened?
160136: 17/06/16: Re: Whups. Lattice Diamond says my package does not exist.
160169: 17/07/13: converting from Xilinx 9500 to 9500XL, won't fit
160170: 17/07/13: Re: converting from Xilinx 9500 to 9500XL, won't fit
160269: 17/10/01: Re: Xilinx Platform cable USB and impact on linux without windrvr
160348: 17/12/14: Re: FPGA one-shot
160397: 18/01/11: Re: HDL simple survey - what do you actually use
160398: 18/01/11: Re: HDL simple survey - what do you actually use
160510: 18/03/05: Re: Microsemi now Microchip
160534: 18/03/16: Re: the FPGA one-shot
160568: 18/04/14: Re: FPGA selection recommendation
160600: 18/05/21: Re: Very low pin count FPGA
160608: 18/05/24: Re: Very low pin count FPGA
160610: 18/05/25: Re: Very low pin count FPGA
161406: 19/07/08: Re: Field update
161478: 19/10/25: Re: EDIF as machine language
161619: 20/01/29: Re: Is FPGA code called firmware?
Jon Forrest:
105397: 06/07/21: Re: Hardware book like "Code Complete"?
Jon Francis:
5557: 97/02/24: Internal Staffing at Texas Instruments - FPGA w/VHDL
Jon Goguen:
6930: 97/07/09: Re: fast scopes: how?
Jon Gunnar Solheim:
1723: 95/08/20: List of FPGA Based Computing Machines
Jon Harris:
4254: 96/10/05: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4340: 96/10/17: Re: Xilinx xchecker.exe and Windows NT
4700: 96/12/02: Re: In Search of Xilinx Routing Statistics
36661: 01/11/14: Re: ASRC (asynchronus sample rate conversion)
59315: 03/08/14: Re: FPGA/DSP Expert - business partner for innovative FFT
59324: 03/08/14: Re: Off topic - Re: FPGA/DSP Expert - business partner for innovative FFT
66448: 04/02/19: Re: Dual-stack (Forth) processors
66458: 04/02/19: Re: Dual-stack (Forth) processors
67979: 04/03/23: Re: Bus width between registers in IIR
85846: 05/06/16: Re: Idea exploration - Image stabilization by means of software.
85959: 05/06/19: Re: Idea exploration - Image stabilization by means of software.
85994: 05/06/19: Re: Idea exploration - Image stabilization by means of software.
87559: 05/07/26: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87560: 05/07/26: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87561: 05/07/26: Re: Best Practices to Manage Complexity in Hardward/Software Design?
90741: 05/10/20: Re: MAC Architectures
90829: 05/10/22: Re: MAC Architectures
102681: 06/05/19: Re: Output gain adjuster of digital filters
Jon Harrison:
21984: 00/04/11: Re: Xilinx Foundation 2.1 error
33140: 01/07/18: FPGAs in Safety Involved Applications
33200: 01/07/19: Re: FPGAs in Safety Involved Applications
33443: 01/07/26: Re: prospects for tiny FPGA supercomputer?
35367: 01/10/01: Re: bufgmux in virtex2 not found
Jon Huppenthal:
19843: 00/01/13: FPGA Design Jobs in Colorado
20414: 00/02/09: Reconfigurable Computing Jobs
Jon Jacox:
51273: 03/01/09: NIOS - first attempt
51322: 03/01/10: Re: NIOS - first attempt
52526: 03/02/12: Fractional Divide
Jon Keeble:
29390: 01/02/18: Re: Emacs VHDL Mode 3.31 released
81465: 05/03/24: Re: NIOS II power-on reset
Jon Kirwan:
22394: 00/05/08: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22418: 00/05/08: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22488: 00/05/10: Re: Xilinx Student Edition 1.5 License.dat
22530: 00/05/10: Re: Xilinx Student Edition 1.5 License.dat
22864: 00/05/28: Re: Buying FPGAs in Germany
24590: 00/08/14: Re: what does 0.35 micron mean
24616: 00/08/15: Re: Non-disclosures in job interviews
24618: 00/08/15: Re: Non-disclosures in job interviews
24617: 00/08/15: Re: Non-disclosures in job interviews
24615: 00/08/15: Re: Non-disclosures in job interviews
24639: 00/08/15: Re: Non-disclosures in job interviews
24671: 00/08/16: Re: Non-disclosures in job interviews
24689: 00/08/16: Re: Non-disclosures in job interviews
24709: 00/08/17: Re: Non-disclosures in job interviews, Round One
24757: 00/08/17: Re: Non-disclosures in job interviews
24760: 00/08/17: Re: Non-disclosures in job interviews
24814: 00/08/19: Re: Non-disclosures in job interviews, Round One
24818: 00/08/19: Re: Non-disclosures in job interviews
24849: 00/08/20: Re: Non-disclosures in job interviews, Round One
24892: 00/08/21: Re: Non-disclosures in job interviews, Round One
24950: 00/08/22: Re: Non-disclosures in job interviews, Round One
24970: 00/08/23: Re: Non-disclosures in job interviews, Round One
24971: 00/08/23: Re: Non-disclosures in job interviews, Round Two
24997: 00/08/23: Re: Non-disclosures in job interviews, Round Two
24998: 00/08/23: Re: Non-disclosures in job interviews, Round One
25153: 00/08/28: Re: Non-disclosures in job interviews, Round One
25734: 00/09/18: Re: Non-disclosures in job interviews, Round Two
25669: 00/09/16: Re: hardware compatibility and patent infringement
25670: 00/09/16: Re: hardware compatibility and patent infringement
Jon Masters:
55536: 03/05/12: MMIX Implementation
56620: 03/06/10: Xilinx gdb
56668: 03/06/11: Re: Xilinx gdb
58132: 03/07/15: Virtex II Pro Exceptions
58168: 03/07/16: Re: Virtex II Pro Exceptions
58422: 03/07/23: Insight Reference Board Problems
58429: 03/07/23: Spurious Machine Check Exceptions [WAS: Re: Insight Reference Board
58430: 03/07/23: Re: Spurious Machine Check Exceptions [WAS: Re: Insight Reference
58571: 03/07/27: VHDL Book Recommendations Please
58574: 03/07/27: Re: VHDL Book Recommendations Please
58630: 03/07/29: Re: VHDL Book Recommendations Please
58631: 03/07/29: Handel C
58710: 03/07/31: Re: VHDL Book Recommendations Please
58843: 03/08/02: Re: VHDL Book Recommendations Please
58918: 03/08/04: Xuart Lite Linux driver
58927: 03/08/04: Re: opencores.org - Question on project licensing?
58942: 03/08/05: Re: Xuart Lite Linux driver
58955: 03/08/05: Re: Xuart Lite Linux driver
58956: 03/08/05: Re: Xuart Lite Linux driver
58979: 03/08/05: Re: Xuart Lite Linux driver
58980: 03/08/05: Re: Xuart Lite Linux driver
59005: 03/08/06: Re: Xuart Lite Linux driver
59074: 03/08/07: Re: Xuart Lite Linux driver
59227: 03/08/12: Update on Virtex II Pro Linux
60255: 03/09/09: Virtex II Pro Linux
62211: 03/10/22: VHDL Souce Code Beautifiers
66279: 04/02/16: EDK6.1 vs. EDK3.2 issues
66367: 04/02/18: EDK6.1 vs. EDK3.2 clarification
66388: 04/02/18: Re: EDK6.1 vs. EDK3.2 clarification
66592: 04/02/23: [Fwd: Solution Update [WAS: Re: EDK6.1 vs. EDK3.2 clarification]]
Jon Neerup Lassen:
127072: 07/12/11: Trouble with instantiation of RPM core - RLOCs are not obeyed
127274: 07/12/16: Generating a RPM in Xilinx floorplanner
Jon Nicoll:
45186: 02/07/15: Xilinx (spartan 2) programming 'lore' (CLK timing etc) sought
Jon Parker:
35283: 01/09/27: Re: Opinions on cypress warp 6.1 and devices?
68847: 04/04/20: Trouble with Altera DSP Builder Licensing while trying to use Signal Compiler...
68904: 04/04/21: Re: Trouble with Altera DSP Builder Licensing while trying to use Signal Compiler...
Jon S.:
29438: 01/02/21: Programming Altera CPLD?
29464: 01/02/22: Re: Programming Altera CPLD?
Jon Saul:
1538: 95/07/11: JOB AD (UK): Research at Oxford University in Computing
4705: 96/12/03: CFP: Reed-Muller 97 -- Int. Workshop on Function Representations
5809: 97/03/17: Reminder: Reed-Muller 97 -- Int. Workshop on Function Representations
7277: 97/08/20: Programme: Reed-Muller 97 -- Int. Workshop on Function Representations
Jon Schneider:
28106: 00/12/21: Simple clock and reset on an Ikos VLE-5M box
28224: 01/01/02: Jedec to tms/tdi wiggles
28226: 01/01/02: Re: Jedec to tms/tdi wiggles
28244: 01/01/03: Re: Boston/Senior Software engineer FPGA/ Well Funded Start up/100k+++/Hot Data Storage Market
28788: 01/01/24: Re: UK parts
28791: 01/01/24: Re: Encryption is supported in new Virtex II but.....
28851: 01/01/26: Re: UK parts
29070: 01/02/05: Re: How different is FPGA design from IC design
29303: 01/02/13: What does specman do ?
31616: 01/05/31: Source of old Altera EPX780s
36424: 01/11/08: Testing of EPX780QC132 needed
39658: 02/02/15: Thingy has the property IOB=TRUE
39667: 02/02/15: Re: Thingy has the property IOB=TRUE
39673: 02/02/15: Re: Thingy has the property IOB=TRUE
40486: 02/03/07: Webpack/SpartanII maplib:93 error
40502: 02/03/08: Re: Webpack/SpartanII maplib:93 error
40548: 02/03/09: Instantiating BUFGSR goes tits up
41228: 02/03/22: Re: JTAG under Linux
41350: 02/03/26: Re: Xilinx 4.2i not working on my design
41644: 02/04/04: Can't get off the ground withg an XC2S30
41891: 02/04/10: Webpack XST broken
41936: 02/04/11: Webpack 4.2 checksums
42052: 02/04/14: Odd problem shows on post XST/translate simulation
42102: 02/04/16: Re: JTAG cable and iMPACT
42186: 02/04/18: Re: JTAG cable and iMPACT
42563: 02/04/27: Spartan II OBUF drive strengths
42807: 02/05/03: Re: Spartan II configuration
46946: 02/09/12: Re: Saving results with modelsim
47971: 02/10/08: Re: Booting a FPGA via USB
50828: 02/12/20: Re: Multi cycle Paths..
89296: 05/09/12: SDRAM quality
93974: 06/01/04: Re: Using posedge and negedge causing me grief
Jon Schutz:
1157: 95/05/08: How to choose an FPGA vendor
8540: 98/01/07: AUSTRALIA-ADELAIDE-SYSTEMS ENGINEER
Jon Seddon:
26310: 00/10/11: FPGA PCB design examples
Jon Slaughter:
143421: 09/10/11: Getting started...
143425: 09/10/11: Re: Getting started...
143441: 09/10/12: Microchip Pic pins current limited?
143442: 09/10/12: Re: Microchip Pic pins current limited?
143443: 09/10/12: Re: Getting started...
143459: 09/10/12: Re: Getting started...
143667: 09/10/20: Re: Teammates, interested?
143675: 09/10/20: Re: Teammates, interested?
144060: 09/11/09: Re: Sinewave generation
Jon Sletvold:
15979: 99/04/24: Xilinx Spartan experience?
Jon Terje Haugland:
57458: 03/07/01: Re: memory
Jon Vedum:
8866: 98/02/03: Re: Comments about Xilinx Alliance m1.4 w/Novell and other problems
Jon Young:
27054: 00/11/08: WebPack Problem
<jon@beniston.com>:
76709: 04/12/09: Re: Clock Gating !!!
139020: 09/03/18: Re: Documenting a simple CPU
140146: 09/04/30: Re: ASIC from working FPGA design
140468: 09/05/14: Re: Open source processors
140938: 09/05/30: Re: patent free ARM cores
140943: 09/05/30: Re: patent free ARM cores
140953: 09/05/31: Re: patent free ARM cores
141058: 09/06/04: Re: Xilinx FIR Compiler gives zero only output in hardware
<Jon@nowhe.re>:
Jonah Probell:
18032: 99/09/24: Instanciating Altera LPMs in Leonardo Spectrum
jonah thomas:
67720: 04/03/17: Re: Dual-stack (Forth) processors
Jonah Thomas:
17477: 99/07/30: Re: Semi-deterministic behaviour in FPGA's
Jonas:
27087: 00/11/10: Pull-up
27155: 00/11/13: Re: Pull-up
27180: 00/11/13: Re: Pull-up
jonas:
110665: 06/10/19: Xilinx ISE Problems with combinatorial loops - software bug?
111744: 06/11/09: ISE bugs or newbie error?
112651: 06/11/27: Re: run a counter without a clock
Jonas Floden:
70667: 04/06/23: Problems with a Virtex-II Engineering Sample
70675: 04/06/23: Re: Problems with a Virtex-II Engineering Sample
70706: 04/06/24: Re: Problems with a Virtex-II Engineering Sample
70783: 04/06/28: Re: Division in Xilinx
70999: 04/07/05: Re: Problems with a Virtex-II Engineering Sample
71030: 04/07/06: Re: Problems with a Virtex-II Engineering Sample
71840: 04/08/02: Re: Problems with a Virtex-II Engineering Sample
72105: 04/08/09: Re: EDK tutorial?????
73572: 04/09/24: VxWorks and Xilinx Virtex-II Pro
Jonas Nilsson:
10420: 98/05/18: Re: Cool Clock Enable Synthesis Fix with Synplify 3.0b
53711: 03/03/20: Re: FPGA dev boards
Jonas Otter:
53664: 03/03/19: Re: free downloadable VLSI softwares
Jonas Rangell:
21737: 00/03/30: Re: tristate /driving a bidirectional port
21939: 00/04/07: Re: multiprocessor support of IC design tools
21960: 00/04/10: Re: multiprocessor support of IC design tools
Jonas Thor:
6748: 97/06/23: Help: Two's complement multiplier in ORCA FPGA
8057: 97/11/12: Need info on runtime configurable FPGAs
8088: 97/11/17: Re: I need Help
11174: 98/07/22: FFT in Xilinx FPGA
12168: 98/10/02: Re: Synthesis: Exemplar or Synopsys
12781: 98/10/29: Foundation 1.4 Export to VHDL?
12930: 98/11/05: Re: Q: fifo flags
12997: 98/11/10: Reporting asynchronous loops in Foundation?
13050: 98/11/13: Re: placement&routing problems
13288: 98/11/24: Re: Combining busses Xilinx
13369: 98/11/30: VHDL simulation of exported schematics..?
13419: 98/12/02: Re: VHDL simulation of exported schematics..?
13990: 99/01/06: Gömmer grisöron...
13991: 99/01/06: Re: Gömmer grisöron...
14141: 99/01/15: Re: System reset
14192: 99/01/19: Re: Synthesis tools for Xilinx FPGAs
14262: 99/01/22: Re: CORDIC (was: Best way to digitally synth. stable frequencies?)
14443: 99/01/29: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14849: 99/02/20: Anyone done any GPS designs?
14862: 99/02/21: Re: multiple clock domain problem
14891: 99/02/23: Re: Problem with xilinx M1
14890: 99/02/23: Re: Problem with xilinx M1
15411: 99/03/23: Re: HDL-307 error
15486: 99/03/26: Re: We require your help please
15919: 99/04/21: Re: Virtex based PCI cards
16220: 99/05/10: Re: Divider core
16225: 99/05/11: Synchronizer design?
16644: 99/06/01: Re: Printing to picture files
16661: 99/06/01: Re: Printing to picture files
17503: 99/08/02: Re: Warning! The eclipse approaches... {5.3a}
18416: 99/10/23: Static power consumption
18485: 99/10/27: Re: XILINX: XDL - is this a secret?
19175: 99/12/03: Re: Question to synplicity users and other not Leonardo users,
19412: 99/12/20: Re: Speed grade
19930: 00/01/19: Re: Cores interfaces
20541: 00/02/14: Re: Wildforce Board
21244: 00/03/13: Re: DSP with FPGA
22552: 00/05/11: Re: appropriate ASIC Prototyping Board
23760: 00/07/07: Re: 56 independent PN streams
24016: 00/07/22: 17 clocks in a Virtex
24033: 00/07/24: Re: 17 clocks in a Virtex
24154: 00/07/28: Re: LFSR as a divider
24155: 00/07/28: Re: LFSR as a divider
25098: 00/08/26: Re: help -- of RAMs, FFs, latches, inverted clocks, and other curiosities
25859: 00/09/23: Re: GPS design with xilinx board
26389: 00/10/13: Re: 5V compatible Virtex
26407: 00/10/15: Re: DLL's Spread Spectrum Compatible ??
27533: 00/11/28: Re: Xess - XS40-005XL question
27895: 00/12/14: Re: Is it necessary to synchronize the reset signal in an FPGA ?
28049: 00/12/20: Re: Virtex and metastability
28821: 01/01/25: Re: How does a flip chip differ from a BGA ?
29611: 01/02/28: SRAM vs. FLASH?
30282: 01/03/31: Re: FPGA V CPLD
30825: 01/04/30: High resolution time measurement?
30858: 01/05/01: Re: High resolution time measurement?
30860: 01/05/01: Re: ccd imaging with fpga
30973: 01/05/06: Re: High resolution time measurement?
30975: 01/05/07: Re: ccd imaging with fpga
31916: 01/06/08: Studentlab with Xilinx tools
31919: 01/06/08: Studentlab with Xilinx tools
40628: 02/03/11: Re: floating pins
41650: 02/04/04: Re: pipelined correlation block on Virtex2000?
44694: 02/06/27: Limited sving IO - LVPECL?
Jonas Weiss:
27728: 00/12/05: ALTERA MAX PLUS LPM FIFOs
27749: 00/12/06: Re: ALTERA MAX PLUS LPM FIFOs
27791: 00/12/08: Re: ALTERA MAX PLUS LPM FIFOs
34962: 01/09/17: Re: Virtex-2 availability
35173: 01/09/25: Virtex II current consumption
36746: 01/11/19: Virtex-II Pin-Incompatibility
39646: 02/02/15: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
39934: 02/02/22: Re: Xilinx (ise4.1) is screwed up! SCREAM LOUD!!
40059: 02/02/26: VIRTEX-II DCI Ref Pins
40067: 02/02/26: Re: VIRTEX-II DCI Ref Pins
<jonas@mit.edu>:
111851: 06/11/11: Virtex-5 Webpack?
111858: 06/11/11: Re: Virtex-5 Webpack?
112116: 06/11/16: V-5 power saving ...how?
113147: 06/12/06: Re: How to find an FPGA board
114443: 07/01/16: small, free simple state machine processor suggestions?
114446: 07/01/16: Re: small, free simple state machine processor suggestions?
114449: 07/01/16: Re: small, free simple state machine processor suggestions?
115932: 07/02/26: Re: Xilinx ISE webpack in Ubuntu?
115992: 07/02/27: Re: Xilinx ISE webpack in Ubuntu?
116148: 07/03/02: XST ucf timespec
116923: 07/03/20: Re: Why is Xilinx's WebPACK so inferior?
117078: 07/03/22: Re: Off topic: what is the purpoe of XST?
117267: 07/03/27: Lattice "Open IP" license is GPL-compatible?
117313: 07/03/28: Re: Lattice "Open IP" license is GPL-compatible?
128589: 08/01/31: Xilinx BSCAN primitives proper use
130623: 08/03/28: Webpack 10.1 on 64-bit linux
130624: 08/03/28: Re: Webpack 10.1 on 64-bit linux
130726: 08/03/31: Re: Webpack 10.1 on 64-bit linux
130757: 08/03/31: Re: Webpack 10.1 on 64-bit linux
jonathan:
68680: 04/04/13: Help - DDS Control in Virtex II
Jonathan:
74435: 04/10/11: multiplexing clocks
74449: 04/10/11: Re: multiplexing clocks
74497: 04/10/12: Re: multiplexing clocks
Jonathan AH Hogg:
807: 95/03/04: Re: IST Drying Up In North America
1389: 95/06/13: Re: 80x51 in FPGA anyone ?
1951: 95/09/23: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
1968: 95/09/26: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
1984: 95/09/28: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
2064: 95/10/09: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
Jonathan Babb:
7246: 97/08/18: Announcement: RAW Benchmark Suite Version 1.0 - now available
Jonathan Bromley:
7730: 97/10/08: Re: FPGA multiprocessors => vs. uniprocessors
8192: 97/11/26: Re: what is metastability time of a flip_flop
8178: 97/11/25: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
8206: 97/11/27: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
8392: 97/12/12: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
11706: 98/09/02: Re: Digital PLL
11764: 98/09/08: Re: Digital PLL
12233: 98/10/06: Re: A Johnson counter
11893: 98/09/17: Help a confused teacher
11894: 98/09/17: Re: Help a confused teacher
11919: 98/09/18: Confused teacher's THANKS
11954: 98/09/21: Re: ASIC -> FPGA async issues
12111: 98/09/29: Re: Simple programmable device suggestions please?
12259: 98/10/07: Re: REQ:An FPGA with automation programming tool
12258: 98/10/07: Catching state machine errors (was: A Johnson counter)
12298: 98/10/08: Re: Catching state machine errors (was: A Johnson counter)
12432: 98/10/12: Re: Digital Sine Generator
12505: 98/10/14: Re: Viewsim bashing 101
12536: 98/10/15: Re: Digital Sine Generator
12537: 98/10/15: Re: Schematic entry?
12636: 98/10/21: Re: Schematic entry?
12659: 98/10/22: Re: Schematic entry?
12807: 98/10/30: Re: FPGA Decouple Capacitor values
12996: 98/11/10: Re: FPGA VGA interface
13052: 98/11/13: Re: Affordable boundary scan (JTAG) interconnect testing software any
13358: 98/11/30: Re: serial arbitration
13375: 98/11/30: Re: serial arbitration
13554: 98/12/09: Re: Verilog/FPGA Express Synth Problem
13561: 98/12/09: Re: Verilog/FPGA Express Synth Problem
13580: 98/12/10: Re: Verilog/FPGA Express Synth Problem
13860: 98/12/30: Re: 22V10 Metastability - help please
13960: 99/01/05: Re: 22V10 Metastability - my 2c
14306: 99/01/25: Re: The development of a free FPGA synthesis tool
14360: 99/01/27: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
14426: 99/01/29: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
14434: 99/01/29: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
14483: 99/02/01: Re: Hazard
14489: 99/02/01: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
14504: 99/02/02: Re: Hazard
14505: 99/02/02: Re: Hazard
14510: 99/02/02: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
14523: 99/02/03: Re: Hazard
14544: 99/02/04: Re: Opinions requested : Minc/Synario alternatives
15247: 99/03/16: Re: Inferring IO's
15394: 99/03/22: Re: Frequency synthesis techniques?
15395: 99/03/22: Re: Free Xilinx Vendor Tools ... NOT :-(
16062: 99/04/30: Re: High speed PLL inside FPGA
16289: 99/05/13: Re: Trade-In Offer - ABEL, MINC & Synario Users in Europe
16727: 99/06/04: Actel Desktop installation of Synplify won't work
16732: 99/06/04: Re: Memec 8250 core with Xilinx Spartan device
16733: 99/06/04: Re: Actel Desktop installation of Synplify won't work
16745: 99/06/06: Re: Memec 8250 core with Xilinx Spartan device
16777: 99/06/08: Re: Sensitivity list assumed to be complete
16785: 99/06/08: Re: Actel Desktop installation of Synplify won't work
16800: 99/06/09: Free IP library?????
16854: 99/06/14: Synplify problem - is it just me?
17803: 99/09/06: Re: Newbie question: Reading FPGA programming?
18075: 99/09/27: Re: Obtaining a Synopsys site ID
18117: 99/10/01: Re: Lattice ISP-cable
18233: 99/10/08: Re: UK or Europe Des. Engs for California jobs
19007: 99/11/24: Re: VHDL vs. schematic entry
19068: 99/11/26: Re: Analog
19149: 99/12/02: Re: FPGA vs DSP vs PENTIUM MMX
19158: 99/12/02: CAN testing - Any CANbus cores out there?
19277: 99/12/09: Re: CAN testing - Any CANbus cores out there?
19571: 00/01/01: Re: Design security
19762: 00/01/11: Re: HW resources increased
19806: 00/01/12: Re: Assignment of pins for thousand+ pin packages
20952: 00/02/29: Re: Recommended VHDL titles wanted ...
21184: 00/03/09: Re: SpartanXL route and place
26175: 00/10/06: Re: Non-standard vhdl expressions
30954: 01/05/04: Re: Use of record type in a hierarchical architecture
32450: 01/06/27: Re: Xilinx Spartan - Power Rail Related Timing Problem
32608: 01/07/02: Re: Converting character to integer in VHDL
32631: 01/07/03: Re: Nets with more than one driver
32663: 01/07/04: Re: Nets with more than one driver
33225: 01/07/19: Re: SystemC
34024: 01/08/11: Re: Quicklogic and Actel floorplanning?
34250: 01/08/17: Re: does anyone have a datasheet for a 18P8 PAL
34300: 01/08/20: Re: Internal clock skew when using DLL
35277: 01/09/27: Re: sensitivity list
35308: 01/09/28: Re: sensitivity list
35363: 01/10/01: Re: Forcing a LUT logic function (was Synplicity logic replication)
35496: 01/10/08: Re: ROM based FSMs
35497: 01/10/08: Re: ROM based FSMs
35650: 01/10/12: Re: PWM Signal in VHDL ?
35777: 01/10/17: Re: memory cell
35784: 01/10/17: Re: simple question
36356: 01/11/07: Re: How can I implement such a counter in Verilog?
36459: 01/11/09: Re: Hex numbers in VHDL
36547: 01/11/12: Re: Quadrature Encoder Sampling Time
36862: 01/11/22: Re: How do I.......
37772: 01/12/20: Re: annoying problem and "simple and clever solution"
38175: 02/01/08: Re: FIR Linear Interpolation
38215: 02/01/09: Re: latch vs. register
38231: 02/01/09: Re: FPGA and CCD : any experience?
38261: 02/01/10: Re: FPGA and CCD : any experience?
38510: 02/01/16: Re: Repost: Should clock skew be included for setup time analysis?
38515: 02/01/16: Re: Repost: Should clock skew be included for setup time analysis?
39655: 02/02/15: Re: Modelsim Logo
41290: 02/03/25: Re: Pipelined sorting algorithms...
41600: 02/04/03: Re: Marquis of Queensbury Rules
42370: 02/04/22: Re: Simulating Unisim
42926: 02/05/07: Re: OP-AMP in FPGA
43006: 02/05/09: Re: OP-AMP in FPGA
44340: 02/06/18: Re: How to deal with a slowly rising reset signal?
44397: 02/06/19: Re: beginer's question: what does tran means in verilog
44860: 02/07/03: Re: DC to DC converter at 1.5V
44861: 02/07/03: Re: VHDL Compliation Problem in Synario
44869: 02/07/03: Re: DC to DC converter at 1.5V
44912: 02/07/05: Re: Fixed point arithmetic
44950: 02/07/08: Re: Fixed point arithmetic
45238: 02/07/17: Re: Which is best method for register with settable and clearable bits
45239: 02/07/17: Re: Design Techniques for Memory Mapped Registers.
45249: 02/07/17: Re: LVDS interface cable recommendation sought
45673: 02/07/31: Re: tone detection...
45720: 02/08/02: Re: spiral / waterfall /watersluice : Which are your methods?
46963: 02/09/13: re: 2-D resistor array
46969: 02/09/13: re: 2-D resistor array
46977: 02/09/13: re:2-D resistor array
47514: 02/09/27: re: Timing accuracy with Modelsim
47631: 02/10/01: re: SPDE problems
47687: 02/10/02: re: AMD9513 Timer Chip
47705: 02/10/02: Re: Moving average filter
50716: 02/12/18: Re: Video timing generator on a Flex 20K / Acex 1K.
50727: 02/12/18: Re: A/D converter in FPGA
50733: 02/12/18: Re: Display "real" waves in simulation?
50738: 02/12/18: Re: Async RAM on an FPGA board
50742: 02/12/18: Re: How to asynchronously reset a flip-flop?
50786: 02/12/19: Re: Async RAM on an FPGA board
50824: 02/12/20: Re: Async RAM on an FPGA board
51842: 03/01/23: Re: VHDL or Verilog?
51851: 03/01/23: Re: VHDL or Verilog?
51877: 03/01/24: Re: VHDL or Verilog?
51964: 03/01/27: Re: Somewhat OT - TECO
51978: 03/01/28: Re: GNU C for custom processor
52198: 03/02/04: Re: Difference between : CPLD , FPGA , ASICS
52248: 03/02/05: Re: Clock Enables
52290: 03/02/06: Re: Clock Enables
52292: 03/02/06: Re: Switching synthesis tools
52392: 03/02/07: Re: Switching synthesis tools
52804: 03/02/22: Re: Flop count..
52838: 03/02/24: Re: need help
52890: 03/02/25: Re: Help,please,Verilog
52934: 03/02/26: Re: FPGA arch.
53007: 03/02/28: Re: How to maintain pipeline delays
53169: 03/03/05: Re: Square root implementation
53171: 03/03/05: Re: EP310
53203: 03/03/06: Re: implementing unfinished designs
53297: 03/03/10: Re: Atmel FPGA uk
53387: 03/03/12: Re: Cyclone power up problem
53423: 03/03/13: Re: Cyclone power up problem
53579: 03/03/17: Re: more footprints...
53963: 03/03/28: Re: Quartus Synthesis
54053: 03/04/01: Re: uP interface question
54098: 03/04/02: Re: uP interface question
54135: 03/04/03: Re: uP interface question
54141: 03/04/03: Re: uP interface question
56601: 03/06/10: Re: Shift registers
56617: 03/06/10: Re: Shift registers
57334: 03/06/27: Re: ModelSim and Specman: on the fly generation
57425: 03/06/30: Re: Asynchronous RESET?
57462: 03/07/01: Re: the skew and race condition
57476: 03/07/01: Re: the skew and race condition
57496: 03/07/01: Re: Seriell Decoder possibly in ABEL for Lattice CPLD
57597: 03/07/02: Re: VHDL & OV6620 CMOS camera
57780: 03/07/07: Re: Starter Question and Opinion on VHDL
58615: 03/07/29: Re: VHDL Book Recommendations Please
58652: 03/07/30: Re: VHDL Book Recommendations Please
58657: 03/07/30: Synthesisable fixed-point arithmetic package
58966: 03/08/05: Re: Patent granted for "system on a chip" framework?
59102: 03/08/08: Re: Compilation error
59107: 03/08/08: Re: Compilation error
59208: 03/08/12: Re: PalmChip Patent
59303: 03/08/14: Re: Modelsim : Error code 3601
59385: 03/08/18: Re: VHDL for FPGA VME Slave
59389: 03/08/18: Re: serial communication between pc and altera fpga
59473: 03/08/20: Re: serial communication between pc and altera fpga
59483: 03/08/20: Re: Xilinx XC3000 with Xilinx ISE student edition 4.2i
59535: 03/08/21: Re: Xilinx XC3000 with Xilinx ISE student edition 4.2i
59735: 03/08/27: Re: Max finding
59912: 03/09/01: Re: HDL Designer from Mentor
59913: 03/09/01: Re: serie
59939: 03/09/02: Re: HDL Designer from Mentor
60264: 03/09/09: Re: CMOS camera w/ USB2 -- crazy?
60305: 03/09/10: Re: Crystal Input to FPGA
61540: 03/10/06: Re: How To: 3-input NAND gate using ACTEL ACT 1 logic module
61604: 03/10/07: Re: Xilinx courses
61649: 03/10/08: Re: Implementing a fast cache in Altera Cyclone
61867: 03/10/14: Re: Electronic Dice ( 3 die ) In VHDL
61930: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
62000: 03/10/16: Re: To our future engineers, smart and otherwise...
62256: 03/10/23: Re: The Luddite Needs Reference Books...
62337: 03/10/27: Re: Electronic Dice VHDL Program
62368: 03/10/28: Re: Electronic Dice VHDL Program
62376: 03/10/28: Re: Electronic Dice VHDL Program
62474: 03/10/30: Re: Hit Logic
62487: 03/10/30: Re: simulation stops preliminarily
62718: 03/11/05: Re: Building the 'uber processor'
62915: 03/11/11: Re: Transforming vector position to binary value
62923: 03/11/11: Re: Transforming vector position to binary value
62930: 03/11/11: Re: Transforming vector position to binary value
62944: 03/11/11: Re: Layout examples
63015: 03/11/12: Re: Trying to digitize video with CTT differential input, but webpack wont't cooperate...:-)
63038: 03/11/13: Re: Transforming vector position to binary value
63043: 03/11/13: Re: Reading O value
63216: 03/11/18: Re: Do I need to connect all Vref in a bank together?
63217: 03/11/18: Re: Transforming vector position to binary value
63280: 03/11/19: Re: regarding clock routing
63287: 03/11/19: Re: How do you keep layout info in VHDL?
63296: 03/11/19: Re: State Machines....
63374: 03/11/20: Re: vhdl construct problem
63436: 03/11/21: Re: Xilinx legacy situation
64548: 04/01/07: Re: SDRAM Controller timing problem
64553: 04/01/07: Re: Clock domains
65026: 04/01/19: Re: info on AMD palce22v10
65154: 04/01/21: Re: Synthesis of Loops
66258: 04/02/16: Plea for help - 29PL141
66259: 04/02/16: Re: Dual-stack (Forth) processors
66265: 04/02/16: Re: Manual Partitioning to Multiple FPGAs
66269: 04/02/16: Re: Plea for help - 29PL141
66322: 04/02/17: Re: Plea for help - 29PL141
66643: 04/02/24: Re: Verilog Newbie Question
66646: 04/02/24: Re: Verilog Newbie Question
67097: 04/03/05: Re: use of attributes
68179: 04/03/29: Re: study verilog or vhdl?
68181: 04/03/29: Re: study verilog or vhdl?
68211: 04/03/30: Re: Is there any Sync separator IP(Intellectual property) exists?
68215: 04/03/30: Re: FIFO Depth(Length) Calculation
68217: 04/03/30: Re: Is there any Sync separator IP(Intellectual property) exists?
68223: 04/03/30: Re: Is there any Sync separator IP(Intellectual property) exists?
68257: 04/03/31: Re: Is there any Sync separator IP(Intellectual property) exists?
68258: 04/03/31: Re: Out Of My Depth: VHDL Use Clause warning : Altera DSPBuilder
68259: 04/03/31: Re: FIFO Depth(Length) Calculation
68518: 04/04/07: Re: VHDL: Use of literal '1' on an input port ?
68576: 04/04/08: Re: timing constraints... again
68797: 04/04/19: Re: FPGA techniques for D/A and A/D
68798: 04/04/19: Re: FPGA techniques for D/A and A/D
68811: 04/04/19: Re: FPGA techniques for D/A and A/D
68812: 04/04/19: Re: FPGA techniques for D/A and A/D
69111: 04/04/27: Re: transport applications
69150: 04/04/28: Re: Stupid question
69155: 04/04/28: Re: Comment on my code style
69171: 04/04/29: Re: Comment on my code style
69740: 04/05/19: Re: Video Blob Analysis on FPGAs
69746: 04/05/19: Re: C-code to control FPGA with Leon
69824: 04/05/21: Re: Never right, always room for improvement
71345: 04/07/15: Re: programmable voltage control of a VCCIO Bank
71750: 04/07/29: Re: ramdon noise generation
72599: 04/08/26: Re: X propagation in Timing Simulation
72606: 04/08/26: Re: X propagation in Timing Simulation
75718: 04/11/12: Re: digital analog conversion
75775: 04/11/14: Re: Obsolete processors resurected in FPGAs
77361: 05/01/05: Re: Whither common courtesy ?
77431: 05/01/06: Re: is this memory implementation synthesizeable?
77577: 05/01/11: Re: Beware of Vref pins becoming "unused" (Xilinx)
77609: 05/01/12: Re: Beware of Vref pins becoming "unused" (Xilinx)
78118: 05/01/25: Re: dsp, arithmetic scaling questions, advice
78201: 05/01/26: Re: Creating a pyramid of shift registers
78245: 05/01/27: Re: ADPLL I Think ?
78406: 05/01/31: Re: Asynchronous Inputs Question
78504: 05/02/02: Re: Asynchronous Inputs Question
78565: 05/02/03: Re: Help, i'm geting warnings :-(
80284: 05/03/03: Re: Exporting Modelsim Values?????
81166: 05/03/18: Re: Newbie: Slow FPGAs
81811: 05/04/01: Re: Searching for Vision Concavity Algorithm
81897: 05/04/04: Re: Searching for Vision Concavity Algorithm
81954: 05/04/05: Re: Searching for Vision Concavity Algorithm
81961: 05/04/05: Re: Structural vs Behavioral
81983: 05/04/05: Re: Structural vs Behavioral
82795: 05/04/18: Re: CCD and Graphics - which FPGA?
82796: 05/04/18: Re: Odd Oversampling
82868: 05/04/19: Re: Odd Oversampling
84543: 05/05/20: Re: A Short Pulse Catcher
85044: 05/06/03: Re: A Short Pulse Catcher
85891: 05/06/17: Re: Idea exploration - Image stabilization by means of software.
86681: 05/07/04: Re: ModelSim Timing Simulation Signal Names
87645: 05/07/27: Re: simulatable but not synthesizable (verifiable)
87679: 05/07/28: Re: How to pass parameters to do file in commandline when running vsim?
87946: 05/08/04: Re: Xilinx Best Source for Reset
87949: 05/08/04: Re: Auto generation of memory files
87952: 05/08/04: Re: Auto generation of memory files
87953: 05/08/04: Re: Legality of type conversion on instance ports?
87957: 05/08/04: Re: Auto generation of memory files
88000: 05/08/05: Re: Legality of type conversion on instance ports?
88216: 05/08/12: Re: Delays in verilog
88654: 05/08/24: Re: Delays in verilog
90307: 05/10/10: Re: 16-bit microprocessor dore for Actel
90308: 05/10/10: Re: fixed point dot product with log2(n) pipe stages in vhdl
90316: 05/10/10: Re: 16-bit microprocessor dore for Actel
90372: 05/10/11: Re: converting 12v signal to 3.3v
90413: 05/10/12: Re: converting 12v signal to 3.3v
90574: 05/10/17: Re: ADC implementation on fpga? Information and procudures wanted.
90578: 05/10/17: Re: ADC implementation on fpga? Information and procudures wanted.
90821: 05/10/21: Re: ADC implementation on fpga? Information and procudures wanted.
91193: 05/11/01: Re: hex rep. in VHDL
92186: 05/11/23: Re: Case expression?
92240: 05/11/24: Re: Case expression?
94064: 06/01/05: Re: Xilinx new year Puzzle: binary counter 0,5,2,3,4,1,6,7...
94068: 06/01/05: Re: Xilinx new year Puzzle: binary counter 0,5,2,3,4,1,6,7...
104156: 06/06/20: Re: FSM State Minimization on FPGAs
104705: 06/07/04: Re: Chaos in FF metastability
104787: 06/07/06: Re: Chaos in FF metastability
104880: 06/07/07: Re: Chaos in FF metastability
104986: 06/07/11: Re: Development Boards -Your chance to suggest features
105043: 06/07/12: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105048: 06/07/12: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105055: 06/07/12: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105141: 06/07/14: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105372: 06/07/20: Re: Hardware book like "Code Complete"?
105867: 06/08/02: Re: How do I pass on an integer to a task and compare with an integer in the task?
105875: 06/08/02: Re: How do I pass on an integer to a task and compare with an integer in the task?
106127: 06/08/08: Re: verilog versus vhdl
106143: 06/08/08: Re: verilog versus vhdl
106151: 06/08/08: Re: verilog versus vhdl
106152: 06/08/08: Re: verilog versus vhdl
106153: 06/08/08: Re: verilog versus vhdl
106348: 06/08/12: Re: Embedded clocks
106362: 06/08/12: Re: Embedded clocks
107821: 06/09/01: Re: Higher voltages input, quick check....
107884: 06/09/01: Re: Higher voltages input, quick check....
107987: 06/09/03: Re: Please help me with (insert task here)
107988: 06/09/04: Re: Please help me with (insert task here)
108295: 06/09/07: Re: how can I decrease the time cost when synthesis and implement
108298: 06/09/07: Re: ddr with multiple users
108302: 06/09/07: Re: Altera CPLD 7128S heating up
108697: 06/09/15: Re: Altera CPLD 7128S heating up
110667: 06/10/19: Re: how to implement integrator?
110673: 06/10/19: Re: how to implement integrator?
111373: 06/11/02: Re: Spectre of Metastability Update
111394: 06/11/02: Re: SystemVerilog interface: virtual and ref
111593: 06/11/06: Re: surprised output of Xilinx Virtex-4
111594: 06/11/06: Re: choise of fpga platform
111607: 06/11/06: Re: surprised output of Xilinx Virtex-4
111743: 06/11/09: Re: abel to vhdl converter
111845: 06/11/11: Re: "|->" implicate and sequence in SVA?
113990: 07/01/02: Re: Surface mount ic's
114085: 07/01/04: Re: OT. Re: Surface mount ic's
114088: 07/01/04: Re: newbie needs help
114089: 07/01/04: Re: Surface mount ic's
114092: 07/01/04: Re: [XST 8.2.3] DSP48 inference multiply/add
114096: 07/01/04: Re: [XST 8.2.3] DSP48 inference multiply/add
114197: 07/01/07: Re: Is there a simple complex magnitude algorithm in FPGA implementation?
114302: 07/01/11: Re: VHDL Model of a stepper motor
114304: 07/01/11: Re: Transport Delays in Modelsim
114325: 07/01/11: Re: Transport Delays in Modelsim
114367: 07/01/12: Re: Transport Delays in Modelsim
114394: 07/01/14: Re: Will FPGAs suit my need?
114395: 07/01/14: Re: First Picture of Craignell Modules
115001: 07/01/29: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
115528: 07/02/13: Re: substracting a whole array of values at once
115535: 07/02/13: Re: substracting a whole array of values at once
115554: 07/02/13: Re: Which is your favorite FPGA language?
116503: 07/03/11: Heritage Data books!
116514: 07/03/12: Re: Heritage Data books!
116652: 07/03/14: Re: VHDL and Latch
116653: 07/03/14: Re: VHDL and Latch
116741: 07/03/16: Re: sum of array
117900: 07/04/12: Re: Which are the best books about CORDIC algorithms and applications
117940: 07/04/13: Re: SoC
117941: 07/04/13: Re: Order of the synchronous operations
117942: 07/04/13: Re: Which are the best books about CORDIC algorithms and applications
117963: 07/04/14: Re: Order of the synchronous operations
117964: 07/04/14: Re: Order of the synchronous operations
117976: 07/04/15: Re: Order of the synchronous operations
117979: 07/04/15: Re: Order of the synchronous operations
118072: 07/04/17: Re: vpw/pwm controller
118135: 07/04/18: Re: ModelSim Waveform naming question
118271: 07/04/20: Re: FPGA Newbie
118399: 07/04/25: Re: Modelsim simulation progress in batch/command line mode?
118627: 07/05/01: Re: weird PACE Error, not one google result
118682: 07/05/02: Re: Where can I find the pass transistor's working curve under 1.2V?
118699: 07/05/02: Re: Where can I find the pass transistor's working curve under 1.2V?
118824: 07/05/04: Re: Wait-for / until won't work ? Xilinx Spartan 3
118826: 07/05/04: Re: Tcl slash backslash
119218: 07/05/15: Re: How low DDR2 Clock Frequency can be? To make it work on FPGA.
119222: 07/05/15: Re: Digital gain and offset correction
119246: 07/05/15: Re: How low DDR2 Clock Frequency can be? To make it work on FPGA.
119286: 07/05/16: Re: how to delay a signal in virtex FPGA
119447: 07/05/19: Re: How to insert tab in Write() function in VHDL
119479: 07/05/21: Re: How to insert tab in Write() function in VHDL
119648: 07/05/24: Re: How can i command bit Inputs in an FPGA board?
120216: 07/06/03: Re: Microcontrollers have a better predictable time behaviour than FPGAs
120291: 07/06/05: Re: modelsim
120367: 07/06/05: Re: How to Find false path in a design
120402: 07/06/06: Re: asynchronous circuit design
120434: 07/06/06: Re: How to Find false path in a design
120672: 07/06/13: Re: Newbie questions: Can I do this PLL all digitally in a FPGA? 8Khz clock locked on a 100hz pulse
121048: 07/06/23: Re: Substitute for FORK / JOIN?
121063: 07/06/24: Re: Multidimensional Register in Modul Port List
121076: 07/06/25: Re: Multidimensional Register in Modul Port List
121090: 07/06/25: Re: Multidimensional Register in Modul Port List
121164: 07/06/27: Re: Trace capturing
121168: 07/06/27: Re: Trace capturing
121505: 07/07/06: Re: Doubt in Asynchronus Circuit design
121510: 07/07/06: Re: Doubt in Asynchronus Circuit design
121570: 07/07/08: Re: Doubt in Asynchronus Circuit design
121800: 07/07/13: Re: Counter ?
122482: 07/07/28: Re: dual port ram
122497: 07/07/29: Re: dual port ram
122574: 07/07/31: Re: Xilinx/ModelSim bug ? Clocking headache ...
122658: 07/08/02: Re: Inputs as an Array in Verilog??
123247: 07/08/21: Re: Synthesizing fixed_pkg in ISE 9.2
123275: 07/08/22: Re: Need to force all signals in a design to a known value at start of simulation
123276: 07/08/22: Re: Need to force all signals in a design to a known value at start of simulation
123314: 07/08/23: Re: Need to force all signals in a design to a known value at start of simulation
123324: 07/08/23: Re: Xilinx / ISE multi-cycle path constraint pitfall
123428: 07/08/28: Re: VHDL clocking scheme VS Verilog clocking scheme
123433: 07/08/28: Re: New keyword 'orif' and its implications
123442: 07/08/28: Re: VHDL clocking scheme VS Verilog clocking scheme
123471: 07/08/28: Re: New keyword 'orif' and its implications
123708: 07/09/02: Re: Null statement in VHDL
123729: 07/09/03: Re: Null statement in VHDL
123756: 07/09/04: Re: Null statement in VHDL
124456: 07/09/22: Re: Answer: maximum number of state machines in a current chip: > 500k
124500: 07/09/25: Re: Automotive Electronic Control
124502: 07/09/25: Re: Automotive Electronic Control
124687: 07/09/30: Re: Walking 1's
125271: 07/10/18: Re: VHDL trivia?
125272: 07/10/18: Re: VHDL trivia?
125290: 07/10/19: Re: VHDL trivia?
125369: 07/10/24: Re: Changing refresh rate for DRAM while in operation?
125399: 07/10/24: Re: Changing refresh rate for DRAM while in operation?
125400: 07/10/24: Re: Changing refresh rate for DRAM while in operation?
125495: 07/10/26: Re: FPGA vs ASIC
125499: 07/10/26: Re: FPGA vs ASIC
125519: 07/10/27: Re: How to use an internal signal in a testbench...
125537: 07/10/27: Re: How to use an internal signal in a testbench...
125970: 07/11/10: Re: newbie to 16v8
126208: 07/11/16: Re: FPGA for hobby use
126307: 07/11/19: Re: Low cost FPGA w/serdes
126310: 07/11/19: Re: Low cost FPGA w/serdes
126437: 07/11/22: Re: converter
126440: 07/11/22: Re: React on falling edge in testbench
126482: 07/11/24: Re: vhdl state machine
126486: 07/11/24: Re: using fpga as programmable connection
126757: 07/12/01: Re: Traffic Light with counter
126771: 07/12/01: Re: Traffic Light with counter
127501: 07/12/29: Re: Initialization of arrays
127515: 07/12/31: Re: State machine with stack to implement "subroutines"
127719: 08/01/06: Re: conversion problem
127960: 08/01/11: Re: Is it possible to define an Integer so it could be incremented and return to 0.
127975: 08/01/11: Re: Is it possible to define an Integer so it could be incremented and return to 0.
128242: 08/01/18: Re: Source of accurate frequency
128285: 08/01/20: Re: VHDL Micron memorymodel.
128289: 08/01/20: Re: VHDL Micron memorymodel.
128384: 08/01/23: Re: ieee_ proposed library
128388: 08/01/24: Re: ieee_ proposed library
128426: 08/01/25: Re: Random Number Generation in VHDL
128427: 08/01/25: Re: Random Number Generation in VHDL
128431: 08/01/25: Re: Craignell FPGA DIP Module
128434: 08/01/25: Re: Random Number Generation in VHDL
128507: 08/01/29: Re: Random Number Generation in VHDL
128918: 08/02/10: Re: Strange "Style guide" requirements...
128921: 08/02/10: Re: Strange "Style guide" requirements...
128945: 08/02/11: Re: Unsigned to signed vector.
128947: 08/02/11: Re: Unsigned to signed vector.
128952: 08/02/11: Re: Unsigned to signed vector.
129009: 08/02/12: Re: '1' or '0' when I/O pin is pulled up
129046: 08/02/13: Re: Newbie looking for guidance
129172: 08/02/17: Re: Video Over RF - using bluetooth and Xilinx Video Starter Kit
129179: 08/02/17: Re: Antti needs a job
129441: 08/02/24: Re: canny edge detection
129532: 08/02/27: Re: ModelSim Natural arg value is negative
129535: 08/02/27: Re: How to connect FPGA to a ASIC Board?
129562: 08/02/27: Re: Quicksim/modelsim
129636: 08/02/29: Re: ModelSim Natural arg value is negative
130149: 08/03/17: Re: Designing CPU
130246: 08/03/18: Re: vhdl type conversions
130249: 08/03/18: Re: vhdl type conversions
130340: 08/03/20: Re: Is there a means to conditional synthesis in VHDL?
130361: 08/03/21: Re: verilog question, break while loop to avoid combinational feedback during synthesis
130375: 08/03/21: Re: verilog question, break while loop to avoid combinational feedback during synthesis
130405: 08/03/22: Re: ISE 10.0 finally with multi-threading and SV support ?
130410: 08/03/22: Re: vhdl type conversions
130427: 08/03/23: Re: Modelsim XE III 6.x - huge fonts
130616: 08/03/28: Re: CAM implementation using Dual port ram
131106: 08/04/11: Re: Split register in smaller segments
131110: 08/04/11: Re: Split register in smaller segments
131112: 08/04/11: Re: Split register in smaller segments
132214: 08/05/18: Re: Problem with conversions.vhd
132237: 08/05/19: Re: 2-bit Pseudo Random Number Generator
132323: 08/05/21: Re: RS232 Interface
132345: 08/05/22: Re: timing constraint is impossible to meet
132437: 08/05/27: Re: FIR filter o/p width
132516: 08/05/29: Re: FIR in FPGA
132519: 08/05/29: Re: FIR in FPGA
132557: 08/05/31: Re: cutoff frequency
132613: 08/06/03: Re: Counter implementation with ise problem
132631: 08/06/04: Re: Counter implementation with ise problem
132674: 08/06/05: Re: FPGA clock frequency
132690: 08/06/05: Re: FPGA clock frequency
132702: 08/06/05: Re: FPGA clock frequency
132711: 08/06/05: Your favourite DSP textbooks/websites?
132716: 08/06/05: Re: FPGA clock frequency
132717: 08/06/05: Re: Your favourite DSP textbooks/websites?
132815: 08/06/07: Re: FPGA clock frequency
132816: 08/06/07: Re: Your favourite DSP textbooks/websites?
133033: 08/06/14: Re: Old Mits Dram Datasheet Search
133149: 08/06/19: Re: NVIDIA’s Tesla T10P Blurs Some Lines
133245: 08/06/22: Re: Image Sensor Interface.
133271: 08/06/23: Re: FPGA based database searching
133298: 08/06/24: Re: Image Sensor Interface.
133448: 08/06/30: Re: arithmetic problem
133602: 08/07/05: Re: QPSK SymbolRate generator ...
133610: 08/07/06: Re: QPSK SymbolRate generator ...
133700: 08/07/10: Re: oversampling serializer?
133715: 08/07/11: Re: oversampling serializer?
134108: 08/07/26: Re: Creating new operators
134351: 08/08/07: Re: RTL Schematic as EDIF
134433: 08/08/10: Re: eliminating individual array registers?
134523: 08/08/16: Re: Verilog modules and stimulus in same file: oh and one more thing...
134524: 08/08/16: Re: Verilog modules and stimulus in same file
134529: 08/08/16: Re: Verilog modules and stimulus in same file
134567: 08/08/19: Re: why does inferred RAM cause synthesis times to explode?
134569: 08/08/19: Re: why does inferred RAM cause synthesis times to explode?
134573: 08/08/19: Re: why does inferred RAM cause synthesis times to explode?
134594: 08/08/20: Re: why does inferred RAM cause synthesis times to explode?
134861: 08/09/04: Re: Strange Spartan2 behaviour
135180: 08/09/19: Re: What software do use big organizations for Logic Synthesis from HDL?
135500: 08/10/05: Re: Spartan 3E overmapping problem
135686: 08/10/12: Re: Complex Event Processing on FPGA
136104: 08/10/31: Re: system verilog state machine
136275: 08/11/09: Re: RS-232 Bus controller design in VHDL
136278: 08/11/09: Re: RS-232 Bus controller design in VHDL
136290: 08/11/10: Re: RS-232 Bus controller design in VHDL
136423: 08/11/15: Re: Synplicity/Synplify and Systemverilog support?
136448: 08/11/17: Re: Synplicity/Synplify and Systemverilog support?
136454: 08/11/17: Aligned PLL clocks in RTL simulation
136468: 08/11/18: Re: Aligned PLL clocks in RTL simulation
136554: 08/11/21: Re: Generate sample rate ...
136566: 08/11/22: Re: Small adders in XST?
136567: 08/11/22: Re: Small adders in XST?
136727: 08/12/03: Re: Dynamical alteration of signal path
136732: 08/12/03: Re: Dynamical alteration of signal path
136744: 08/12/03: Re: Relationship between high and low speed clocks
136757: 08/12/04: Re: Query on Xilinx Nomenclature
136813: 08/12/06: Re: Modelsim warning message
136832: 08/12/08: Re: Inverting bus connection order in Verilog
136855: 08/12/09: Re: Inverting bus connection order in Verilog
137080: 08/12/22: Re: Synthesis Problem
137086: 08/12/22: Re: Need comment on the following Verilog always block
137087: 08/12/22: Re: Synthesis Problem
137110: 08/12/23: Re: DFFR using DFF (only, may be extra gates)
137119: 08/12/23: Re: DFFR using DFF (only, may be extra gates)
137161: 08/12/29: Re: DIP PACKAGE ?
137261: 09/01/06: Re: beginner synthesize question - my debounce process won't synthesize.
137266: 09/01/06: Re: beginner synthesize question - my debounce process won't synthesize.
137295: 09/01/07: Re: problems with symbols and how to debug Quartus block diagrams with Modelsim?
137466: 09/01/18: Re: Using memory blocks generated by CoreGen
137468: 09/01/18: Re: VHDL: Process vs concurrent stataments?
137489: 09/01/20: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
137503: 09/01/21: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
137505: 09/01/21: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
137608: 09/01/23: Re: Altera 3000A: Can I make a freq. generator (1 Hz to 2 kHz) ?
137623: 09/01/24: Re: Altera 3000A: Can I make a freq. generator (1 Hz to 2 kHz) ?
137650: 09/01/26: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
137653: 09/01/26: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
137664: 09/01/27: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
137675: 09/01/27: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
137685: 09/01/27: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
137693: 09/01/27: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
137721: 09/01/28: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
137722: 09/01/28: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
137771: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
137777: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
137789: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
137791: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
137824: 09/01/30: Re: UART RS232 "hello world" program trial and terror.
137826: 09/01/30: Re: UART RS232 "hello world" program trial and terror.
137838: 09/01/31: Re: how can we connect the two buses of different width
137863: 09/02/01: Re: Heavily pipelined design
137880: 09/02/01: Re: Heavily pipelined design
137968: 09/02/03: Re: rs232 uart: testbench vs real world, and the missing first letter.
137972: 09/02/03: Re: rs232 uart: testbench vs real world, and the missing first letter.
137973: 09/02/03: Re: rs232 uart: testbench vs real world, and the missing first letter.
137977: 09/02/03: Tabula - new kid on the FPGA block?
137997: 09/02/03: Re: rs232 uart: testbench vs real world, and the missing first letter.
138018: 09/02/04: Re: Tabula - new kid on the FPGA block?
138032: 09/02/04: Re: rs232 uart: testbench vs real world, and the missing first letter.
138033: 09/02/04: Re: rs232 uart: testbench vs real world, and the missing first letter.
138057: 09/02/05: Re: rs232 uart: testbench vs real world, and the missing first letter.
138078: 09/02/05: Re: rs232 uart: testbench vs real world, and the missing first letter.
138092: 09/02/06: Re: rs232 uart: testbench vs real world, and the missing first letter.
138098: 09/02/06: Re: Rotary Encoder - Microblaze and ML505
138105: 09/02/06: Re: rs232 uart: testbench vs real world, and the missing first letter.
138115: 09/02/06: Re: Precedence of signal assignment in a clocked process
138118: 09/02/06: Re: rs232 uart: testbench vs real world, and the missing first letter.
138124: 09/02/06: Re: rs232 uart: testbench vs real world, and the missing first letter.
138140: 09/02/07: Re: [VHDL] Simple syntax error, but why ?
138160: 09/02/08: Is this phase accumulator trick well-known???
138168: 09/02/08: Re: Is this phase accumulator trick well-known???
138169: 09/02/08: Re: Is this phase accumulator trick well-known???
138195: 09/02/09: Re: Is this phase accumulator trick well-known???
138198: 09/02/09: Re: Is this phase accumulator trick well-known???
138214: 09/02/09: Re: Is this phase accumulator trick well-known???
138231: 09/02/10: Re: Is this phase accumulator trick well-known???
138233: 09/02/10: Re: Is this phase accumulator trick well-known???
138241: 09/02/10: Re: rs232 uart: testbench vs real world, and the missing first letter.
138259: 09/02/11: Re: rs232 uart: testbench vs real world, and the missing first letter.
138260: 09/02/11: Re: rs232 uart: testbench vs real world, and the missing first letter.
138263: 09/02/11: Re: Is this phase accumulator trick well-known???
138293: 09/02/13: Re: Logic Analyzer
138304: 09/02/14: Re: Capture parallel data ...
138306: 09/02/14: Re: Capture parallel data ...
138314: 09/02/15: Re: Capture parallel data ...
138315: 09/02/15: Re: UART RS232 "hello world" really taking shape now.
138329: 09/02/16: Re: UART RS232 "hello world" really taking shape now.
138336: 09/02/16: Re: UART RS232 "hello world" really taking shape now.
138342: 09/02/16: Re: "Type of xxx is incompatible with type of yyy." typecasting error.
138357: 09/02/17: Re: "Type of xxx is incompatible with type of yyy." typecasting error.
138364: 09/02/17: Re: "Type of xxx is incompatible with type of yyy." typecasting error.
138725: 09/03/06: Re: New person to CPLD programming
138741: 09/03/06: Re: New person to CPLD programming
138808: 09/03/11: Re: Best way to write to LUT based CPLD from slow CPU?
138891: 09/03/13: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138926: 09/03/14: Re: Digital division scale
138943: 09/03/16: Re: Well Known? Phase Accumulator Trick
138962: 09/03/17: Re: Zero operand CPUs
138964: 09/03/17: Re: Zero operand CPUs
138975: 09/03/17: Re: Zero operand CPUs
138995: 09/03/18: Re: Zero operand CPUs
139006: 09/03/18: Documenting a simple CPU
139047: 09/03/19: Re: Documenting a simple CPU
139048: 09/03/19: Re: Documenting a simple CPU
139050: 09/03/19: Re: Documenting a simple CPU
139066: 09/03/19: Re: Documenting a simple CPU
139100: 09/03/20: Re: How big is my vhdl and am I approaching some size limitation on the chip.
139112: 09/03/21: Re: How big is my vhdl and am I approaching some size limitation on the chip.
139186: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on ?the chip.
139187: 09/03/22: Re: Cross talk in Altera
139582: 09/04/05: Re: Modulo-10 counter
139589: 09/04/06: Re: Modulo-10 counter
139597: 09/04/06: Re: Modulo-10 counter
139609: 09/04/07: Re: Modulo-10 counter
139712: 09/04/10: Re: Noise in Stratix3?
139713: 09/04/10: Re: NCO'S
139769: 09/04/13: Stupid question about COE files
139823: 09/04/15: Re: S3A starterkit weird behaviou (mini quiz)
140028: 09/04/24: Re: Modelsim GTP_DUAL not recognized
140031: 09/04/24: Re: Modelsim GTP_DUAL not recognized
140047: 09/04/25: Re: Error in Verilog Code
140167: 09/05/01: Re: Representation of Read processor convention
140254: 09/05/06: Re: Code blocks to realize this in VHDL
140256: 09/05/06: Re: ISE & VHDL : how to include time/date
140286: 09/05/07: Re: Dual Port RAM Inference
140291: 09/05/07: Re: Dual Port RAM Inference
140306: 09/05/08: Re: Dual Port RAM Inference
140329: 09/05/09: Re: Dual Port RAM Inference
140340: 09/05/09: Re: Which alternative prog to use for hdl handling ?
140353: 09/05/10: Re: Dual Port RAM Inference
140442: 09/05/13: Re: Achronix' asynchronous FPGAs
140566: 09/05/18: Re: Doubts in using memory of verilog
140571: 09/05/18: Re: Survey: What's a good FPGA-related conference?
140617: 09/05/20: Re: Port assignment question
140648: 09/05/21: Re: Are all these claims in VHDL correct?
140653: 09/05/21: Re: Are all these claims in VHDL correct?
140662: 09/05/21: Re: Are all these claims in VHDL correct?
140682: 09/05/21: Re: Are all these claims in VHDL correct?
140704: 09/05/22: Re: Are all these claims in VHDL correct?
140707: 09/05/22: Re: Are all these claims in VHDL correct?
140936: 09/05/30: Re: VHDL synthesis difference bwetween tools
141009: 09/06/02: Re: the reach of VHDL
141162: 09/06/09: Re: Xilinx Block RAM Sim
141181: 09/06/10: Re: Xilinx Block RAM Sim
141245: 09/06/12: Re: Verilog "for loop" - exit by setting i to exit value?
141247: 09/06/12: Re: Verilog "for loop" - exit by setting i to exit value?
141252: 09/06/12: Re: Verilog "for loop" - exit by setting i to exit value?
141263: 09/06/13: Re: Correlation Algorithm: converting user type integer array into std_logic_vector
141265: 09/06/14: Re: Correlation Algorithm: converting user type integer array into std_logic_vector
141386: 09/06/22: Re: Question on FPGA driver
141389: 09/06/22: Re: Subtleties of Booth's Algorithm Implementation
141411: 09/06/23: Re: index in arrays doesn't work
141413: 09/06/23: Re: index in arrays doesn't work
141424: 09/06/24: True dual-port RAM in VHDL: XST question
141426: 09/06/24: Re: True dual-port RAM in VHDL: XST question
141428: 09/06/24: Re: True dual-port RAM in VHDL: XST question
141433: 09/06/24: Re: True dual-port RAM in VHDL: XST question
141442: 09/06/24: Re: True dual-port RAM in VHDL: XST question
141443: 09/06/24: Re: True dual-port RAM in VHDL: XST question
141495: 09/06/25: Re: True dual-port RAM in VHDL: XST question
141511: 09/06/26: Re: True dual-port RAM in VHDL: XST question
141590: 09/06/29: Re: True dual-port RAM in VHDL: XST question
141592: 09/06/29: Re: STA Problem on Asynchronous FIFO
141655: 09/07/02: Re: Verilog module parameter generating ports in module declaration?
141744: 09/07/06: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
141868: 09/07/14: Re: Minimal size 1-bit adder....
141880: 09/07/15: Re: Minimal size 1-bit adder....
141889: 09/07/15: Re: parallel processing
141905: 09/07/16: Re: Minimal size 1-bit adder....
141992: 09/07/21: Re: Strange FPGA behavior
142289: 09/08/02: Re: [newbie] Verilog test bench with automatic verification
142290: 09/08/02: Re: [newbie] Verilog test bench with automatic verification
142292: 09/08/02: Re: [newbie] Verilog test bench with automatic verification
142387: 09/08/08: Re: can't write to a bram module (verilog)
142389: 09/08/08: Re: Peter Alfke
142398: 09/08/09: Re: EVERAGE ?
142738: 09/08/29: Re: Does ModelSim or any simulator software have a function similar to the standard function any logic analizer has?
142753: 09/08/30: Re: Does ModelSim or any simulator software have a function similar to the standard function any logic analizer has?
142779: 09/09/01: Re: Polynomial Function ...
142782: 09/09/01: Re: Polynomial Function ...
142812: 09/09/02: Re: Polynomial Function ...
142860: 09/09/04: Re: Choice of Language for FPGA programming
142877: 09/09/04: Re: Choice of Language for FPGA programming
142883: 09/09/05: Re: Interfacing variable-speed functional units
142884: 09/09/05: Re: Choice of Language for FPGA programming
142899: 09/09/07: Re: Choice of Language for FPGA programming
142905: 09/09/07: Re: Choice of Language for FPGA programming
142936: 09/09/09: ANN: Coding style guidance for FPGA memory
142986: 09/09/13: Re: ANN: Coding style guidance for FPGA memory
143038: 09/09/15: Re: ANN: Coding style guidance for FPGA memory
143099: 09/09/20: Re: Everything in single clock cycle.
143113: 09/09/21: Re: timing simulation performance
143153: 09/09/23: Re: Shift left arithmetic?
143213: 09/09/25: Re: Shift left arithmetic?
143873: 09/10/30: Re: Best way to model a large external ROM in a simulation? (XST simulator)
143879: 09/10/31: Re: Almost Full signal a clk before Wfull signal
144026: 09/11/08: Re: Sinewave generation
144036: 09/11/08: Re: free software/open source projects and FPGA?
144281: 09/11/24: Re: Help needed with Quicklogic QL8X12B-1PL68M tools and programmer
144284: 09/11/24: Re: Help needed with Quicklogic QL8X12B-1PL68M tools and programmer
144294: 09/11/25: Re: Help needed with Quicklogic QL8X12B-1PL68M tools and programmer
144348: 09/11/29: Re: Help needed with Quicklogic QL8X12B-1PL68M tools and programmer
144514: 09/12/12: Re: Does a 1-bit mux glitch if only one input is known to change at one time?
144521: 09/12/12: Re: Does a 1-bit mux glitch if only one input is known to change at one time?
144546: 09/12/14: Re: Does a 1-bit mux glitch if only one input is known to change at one time?
144710: 09/12/27: Info on heritage Nallatech board?
144756: 09/12/30: Re: ADC problem on spartan3E
144818: 10/01/06: Re: Databus crossing clock domains with data freeze
144828: 10/01/07: Re: Databus crossing clock domains with data freeze
144829: 10/01/07: Re: Databus crossing clock domains with data freeze
144918: 10/01/15: Re: SystemVerilog Verification Example using Quartus and ModelSim
144925: 10/01/15: Re: SystemVerilog Verification Example using Quartus and ModelSim
144982: 10/01/18: Re: bit vs std_logic (was Re: Simulation of VHDL code for a vending machine)
144994: 10/01/19: Re: XST is driving me mad.
145001: 10/01/19: Re: compiler output to fpga.
145021: 10/01/20: Re: compiler output to fpga.
145034: 10/01/21: Re: bit vs std_logic (was Re: Simulation of VHDL code for a vending machine)
145089: 10/01/26: Re: timing properties of fpga devices at sub-clock frequencies
145094: 10/01/27: Re: timing properties of fpga devices at sub-clock frequencies
145096: 10/01/27: Re: Achronix FPGA
145100: 10/01/27: Re: Achronix FPGA
145133: 10/01/29: Re: timing properties of fpga devices at sub-clock frequencies
145307: 10/02/05: Re: How good are Actel tools
145358: 10/02/06: Re: using an FPGA to emulate a vintage computer
145376: 10/02/07: Re: Databus crossing clock domains with data freeze
145508: 10/02/12: Re: Why is following Verilog code snipper considered a Latch
145510: 10/02/12: Re: Why is following Verilog code snipper considered a Latch
145523: 10/02/13: Re: VHDL vs Verilog
145525: 10/02/13: Re: VHDL vs Verilog
145526: 10/02/13: Re: VHDL vs Verilog
145551: 10/02/14: Re: VHDL vs Verilog
145552: 10/02/14: Re: VHDL vs Verilog
145553: 10/02/14: Re: 28nm FPGAs are coming...
145555: 10/02/14: Re: VHDL vs Verilog
145586: 10/02/15: Re: optimal no of inputs to be given in a test bench
145964: 10/03/02: Re: LVDS i/o in a SystemVerilog Interface block
145970: 10/03/02: Re: Tabula. (FPGA start up)
145993: 10/03/02: Re: Tabula. (FPGA start up)
146078: 10/03/05: Re: Is an inout reg allowed
146079: 10/03/05: Re: Tabula. (FPGA start up)
146109: 10/03/05: Re: Is an inout reg allowed
146166: 10/03/07: Re: Question in verilog testbench
146255: 10/03/10: Re: Some Active-HDL questions
146258: 10/03/10: Re: Some Active-HDL questions
146482: 10/03/19: Re: Why doesn't this situation generate a latch?
146521: 10/03/21: Re: Changing Generics in Simulation
146554: 10/03/22: Re: Finally, selling my old Xilinx/Viewlogic software package
146723: 10/03/26: Re: EMC discussion
146827: 10/03/29: Re: Which is the most beautiful and memorable hardware structure in a CPU?
146853: 10/03/30: Re: Which is the most beautiful and memorable hardware structure in a
146936: 10/04/02: Re: Using Verilog Macros with Arguments
146941: 10/04/03: Re: Using Verilog Macros with Arguments
146959: 10/04/05: Re: How to convert Verilog in to VHDL code
146981: 10/04/07: Re: Case with HEX value ...
147026: 10/04/09: Re: I'd rather switch than fight!
147154: 10/04/15: Re: I'd rather switch than fight!
147158: 10/04/16: Re: I'd rather switch than fight!
147280: 10/04/21: Re: Tutorial for C based bit-accurate hardware modeling ?
147352: 10/04/23: Re: I'd rather switch than fight!
147454: 10/04/27: Re: Inferring mutipliers
147577: 10/05/04: Re: FIFO Depth Calculation
147947: 10/06/03: Re: ISE Design Suite 11 will not evaluate 2's comp
148061: 10/06/17: Re: Why is Google so F****** dense about SPAM?
148073: 10/06/18: Re: Why is Google so F****** dense about SPAM?
148152: 10/06/23: Re: Xilinx Timing Constraings
148360: 10/07/15: Re: Verilog in Quartus and assignments in blocks
148366: 10/07/15: Re: Verilog in Quartus and assignments in blocks
148367: 10/07/15: Re: Verilog in Quartus and assignments in blocks
148393: 10/07/17: Re: Dumb VHDL Question -- Type Conversion
148475: 10/07/26: Re: temporal logic folding
148561: 10/08/01: Re: Differences between Verilog versions
148670: 10/08/17: Re: VDHL initializing
148674: 10/08/17: Re: I have problem in writing testbench
148685: 10/08/17: Re: Getting started with FPGA
148686: 10/08/17: Re: VDHL initializing
148788: 10/08/24: Looking to buy some obsolete FPGAs
148845: 10/09/02: Re: parsing script arguments in QuestaSim/ModelSim
148846: 10/09/02: Re: parsing script arguments in QuestaSim/ModelSim
149540: 10/11/03: Re: Good Dev Board
149805: 10/11/24: Re: Verilog preprocessor macro syntax
149806: 10/11/24: Re: Brain Cramps...
149967: 10/12/03: Re: [HUMOR]: The Danger of When Programmable Logic Meets the Consumer Market -- The Informercial
149984: 10/12/05: Re: : The Danger of When Programmable Logic Meets the Consumer Market -- The Informercial
150054: 10/12/08: Re: Concurrent Logic Timing
150202: 10/12/31: Re: I Give Up!
150381: 11/01/14: Re: Verilog Book for VHDL Users
150387: 11/01/15: Re: Verilog Book for VHDL Users
150415: 11/01/18: Re: Verilog Book for VHDL Users
150609: 11/01/27: Re: Wow! No TestbenchWow!
150679: 11/02/02: Re: Trivia: Where are you on the HDL Map?
150842: 11/02/16: Re: Regarding passing a control signal from fast to slow cloak domain
150898: 11/02/20: Re: Regarding passing a control signal from fast to slow cloak domain
151217: 11/03/15: Re: Regfile access
151347: 11/03/26: Re: Measuring the delay between two rising edges in modelsim simulation through command/tcl script and writing them to a file.
151354: 11/03/27: Re: fpga express 3.6
151367: 11/03/28: Re: fpga express 3.6
151581: 11/04/21: Re: more precise info
151801: 11/05/18: Re: Modelsim
151842: 11/05/23: Re: comparator fast implementation
152047: 11/06/27: XST 13.1 explodes with generic of enum type with only one member
152054: 11/06/28: Re: XST 13.1 explodes with generic of enum type with only one member
152055: 11/06/28: Re: XST 13.1 explodes with generic of enum type with only one member
152057: 11/06/29: Re: XST 13.1 explodes with generic of enum type with only one member
152058: 11/06/29: Re: XST 13.1 explodes with generic of enum type with only one member
152066: 11/06/29: Re: XST 13.1 explodes with generic of enum type with only one member
152414: 11/08/20: Re: VHDL Basic Question
152417: 11/08/20: Re: VHDL Basic Question
152420: 11/08/21: Re: VHDL Basic Question
152424: 11/08/21: Re: VHDL Basic Question
152426: 11/08/21: Re: VHDL Basic Question
152446: 11/08/23: Re: vhdl:passing generic sized arrays to functions?
152450: 11/08/23: Re: extracting D from 1 / D*D
152782: 11/10/21: Re: Peter Alfke has passed away
152792: 11/10/23: Re: Doulos training courses at Xilinx
Jonathan Buller:
4540: 96/11/11: Re: Info on FPGA Internal Architecture/ Programming
Jonathan Cutting:
17614: 99/08/14: Free UART
Jonathan Debrouwere:
68043: 04/03/25: opb arbitrer
68078: 04/03/26: Re: opb arbitrer
68563: 04/04/08: XAPP662 readframe and writeframe functions.
Jonathan Dumaresq:
79097: 05/02/14: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
79111: 05/02/14: opencore under edk 6.3i
79120: 05/02/14: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
79124: 05/02/14: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
79125: 05/02/14: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
79127: 05/02/14: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
79162: 05/02/15: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
79168: 05/02/15: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
79211: 05/02/15: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
79225: 05/02/15: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
79343: 05/02/17: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
79344: 05/02/17: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
79350: 05/02/17: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
79404: 05/02/18: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
79627: 05/02/22: Re: USB 1.1 core
79628: 05/02/22: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
79809: 05/02/24: edk, chipscope_icon and chipscope_ila
79825: 05/02/24: Re: edk, chipscope_icon and chipscope_ila
Jonathan Feifarek:
16221: 99/05/10: Re: Spartan Metastability parameters
16268: 99/05/12: Re: Virtex development boards
16414: 99/05/20: Re: High Speed Reconfigurability
16468: 99/05/24: Re: High Speed Reconfigurability
16469: 99/05/24: Re: High Speed Reconfigurability
16470: 99/05/24: Re: High Speed Reconfigurability
16483: 99/05/25: Re: High Speed Reconfigurability
16490: 99/05/25: Re: High Speed Reconfigurability
16534: 99/05/26: Re: High Speed Reconfigurability
16585: 99/05/28: Re: Dynamically reconfigurable devices
16586: 99/05/28: Evolutionary computation
16666: 99/06/01: Re: Evolutionary computation
16686: 99/06/02: Re: Evolutionary computation
16687: 99/06/02: Re: FPGA Introduction is needed, right?
16764: 99/06/07: Re: [Q] low cost asic
16978: 99/06/21: Re: FPGA in Wireless Designs
17026: 99/06/25: Re: 100 Billion operations per sec.!
17715: 99/08/26: Re: looking for image processing hardware
21727: 00/03/29: Re: FPGA & single point failure
Jonathan Greenlaw:
182: 94/09/14: Re: Xilinx and 8.4 -- not!
Jonathan Griffitts:
1331: 95/06/02: Re: Latch up in Xilinx 3000 Series FPGA's. Part smokes & smells bad.
1918: 95/09/19: Re: Fast FPGA's?
2451: 95/12/06: Re: Xilinx 5200 vs. 3000, & Xilinx-ABEL?
3579: 96/06/30: Re: sanity check for 100k gate DSP FPGA project (long)
Jonathan Jenkins:
3079: 96/03/27: Re: MTI VHDL simulation w/ Xilinx
Jonathan Kirwan:
40634: 02/03/12: Re: Mystery two wire interface, or am I being dense?
40825: 02/03/16: Re: High speed clock routing
55118: 03/04/28: Re: Low pin count SOC
55141: 03/04/28: Re: Low pin count SOC
72889: 04/09/07: Re: VHDL code for 16-32 bit counter for quadrature encoder signals (A-B)
72932: 04/09/08: Re: VHDL code for 16-32 bit counter for quadrature encoder signals (A-B)
94129: 06/01/06: Re: RTL for Z8000 series CPU?
95273: 06/01/22: Re: OT:Shooting Ourselves in the Foot
124023: 07/09/11: Re: Uses of Gray code in digital design
124031: 07/09/11: Re: Uses of Gray code in digital design
124033: 07/09/11: Re: Uses of Gray code in digital design
124035: 07/09/11: Re: Uses of Gray code in digital design
124043: 07/09/11: Re: Uses of Gray code in digital design
124077: 07/09/11: Re: Uses of Gray code in digital design
124097: 07/09/12: Re: Uses of Gray code in digital design
Jonathan M Hill:
17391: 99/07/23: Re: Hardware FFT Design?
Jonathan Montag:
5558: 97/02/24: Does anybody know how defaults work in a State Machine in AHDL ?
Jonathan N. Wolfe:
774: 95/02/27: Re: Real-time fractal gen in h/w
Jonathan O'Brien:
46162: 02/08/20: Re: Fun FPGA system
Jonathan Rose:
14: 94/07/28: FPGA '95 Symposium Call for Papers
175: 94/09/09: FPGA `95 Symposium Second Call for Papers
488: 94/12/02: FPGA '95 Symposium Advance Program
153395: 12/02/15: Major New Release of Public-Domain FPGA Architecture and CAD Research
Jonathan Ross:
149974: 10/12/04: Re: FPGA project structure definition
149980: 10/12/04: Re: Concurrent Logic Timing
Jonathan Schneider:
91767: 05/11/12: Kingston ValueRAM double deckers
96519: 06/02/06: Tefzel or Kynar for PCB mods ?
104158: 06/06/20: Google FPGA Designer beta release
Jonathan Swift:
41944: 02/04/11: Re: Attributes *and* generics!?
41945: 02/04/11: Re: Destroying Xilinx xc4000 etc
42075: 02/04/15: Re: Using SRL16E Xilinx primitive.
42076: 02/04/15: Re: Configuring XIlinx XL Fpga with no XL PROM.
80175: 05/03/02: Re: RocketIO minimum bitrate and other questions
Jonathan Thornburg:
28334: 01/01/08: Re: Nondeterministic FSMs in hardware?
Jonathan Wilson:
31712: 01/06/03: does anyone have a disassembler for a 18P8 PAL?
34143: 01/08/15: I need help disassembling a JEDEC .jed file from a PLHS18P8A
34235: 01/08/16: does anyone have a datasheet for a 18P8 PAL
34276: 01/08/17: Re: does anyone have a datasheet for a 18P8 PAL
Jonathan Zingman:
23035: 00/06/09: Too many unbeffered connections in Foundation
<jonathan.bromley@doulos.com>:
65223: 04/01/22: Re: Synthesis of Loops
<jonathan@dcs.gla.ac.uk>:
3723: 96/07/22: Re: What about the XC6200 ?
<JonathanScottRose@gmail.com>:
129909: 08/03/09: New Release of VPR, Version 5.0 Beta
134041: 08/07/22: New Release of VPR Version 5.0 (non-Beta)
Jonathon Hill:
18911: 99/11/21: Brand New MUSIC
Jonathon Ralston:
2351: 95/11/22: ISSPA 96 Final Call for Papers
Jone_yang:
154116: 12/08/10: RE: Problem in Xilkernel
<jonesandy@comcast.net>:
154125: 12/08/15: Re: "Decimals" word in binary space
154143: 12/08/21: Re: "Decimals" word in binary space
154267: 12/09/19: Re: Global Reset using Global Buffer
154277: 12/09/20: Re: Global Reset using Global Buffer (long!)
154309: 12/09/25: Re: Getting in to the industry
154339: 12/10/04: Re: FPGA-Board for Ethernet
154362: 12/10/15: Re: My First CPU but.. one problem
154364: 12/10/15: Re: My First CPU but.. one problem
154370: 12/10/16: Re: My First CPU but.. one problem
154394: 12/10/24: Re: Serial LVDS ADC to spartan6
154395: 12/10/24: Re: tell QuartusII to use registers and not RAM
154439: 12/11/02: Re: Altera FPGA: EP4CE10 as drop-in replacement for EP4CE15 (F17)
154457: 12/11/05: Re: Xilinx XC3S400 reproducibility madness
154599: 12/11/30: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
154624: 12/12/03: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
154635: 12/12/04: Re: How to transfer multiple bit data between phase shifted clock?
154663: 12/12/13: Re: MII SFD Detection with Shematics
154693: 12/12/18: Re: MII SFD Detection with Shematics
154779: 13/01/07: Re: Which to learn: Verilog vs. VHDL?
154806: 13/01/14: Re: Chisel as alternative HDL
154808: 13/01/14: Re: is this multicycle?
154810: 13/01/14: Re: is this multicycle?
154815: 13/01/15: Re: is this multicycle?
154892: 13/01/29: Re: Ray Andraka's Book?
154916: 13/02/13: Re: Chisel as alternative HDL
154919: 13/02/13: Re: Chisel as alternative HDL
154921: 13/02/14: Re: Chisel as alternative HDL
154966: 13/03/04: Re: Xilinx XST and initializing block RAMs
154968: 13/03/04: Re: about the always block in verilog
154970: 13/03/05: Re: about the always block in verilog
154975: 13/03/06: Re: about the always block in verilog
155088: 13/04/08: Re: FPGA for large HDMI switch
155089: 13/04/08: Re: RS232 VHDL-core
155112: 13/04/22: Re: FPGA for large HDMI switch
155114: 13/04/22: Re: FPGA for large HDMI switch
155116: 13/04/23: Re: FPGA for large HDMI switch
155158: 13/05/13: Re: Inferring Xilinx BlockRAM FIFO
155165: 13/05/16: Re: Linting tool setup
155176: 13/05/22: Re: Die size of BRAM/DSP48 in CLBs
155259: 13/06/19: Re: Ask about finding maximum and second's maximum number in array is given.
155372: 13/06/24: Re: Ask about finding maximum and second's maximum number in array is given.
155374: 13/06/24: Re: Ask about finding maximum and second's maximum number in array is given.
155423: 13/06/26: Re: FPGA Exchange
155560: 13/07/18: Re: Metastability mitigation and I/O registers
155574: 13/07/23: Re: Verilog:
155642: 13/07/31: Re: seperate high speed rules for HDL?
155661: 13/08/01: Re: seperate high speed rules for HDL?
155690: 13/08/05: Re: seperate high speed rules for HDL?
155719: 13/08/21: Re: Cascaded floating-point reduction?
155722: 13/08/22: Re: Cascaded floating-point reduction?
155723: 13/08/22: Re: Lattice Announces EOL for XP and EC/P Product Lines
155727: 13/08/23: Re: Cascaded floating-point reduction?
155745: 13/08/26: Re: Cascaded floating-point reduction?
155746: 13/08/26: Re: Lattice Announces EOL for XP and EC/P Product Lines
155774: 13/08/29: Re: FPGA temperature measurement
155796: 13/09/06: Re: Lattice Announces EOL for XP and EC/P Product Lines
155823: 13/09/20: Re: timing closure
155988: 13/11/04: Re: Simulation of VHDL code for a vending machine
156157: 13/12/26: Re: Use of latches in FSMs
156166: 14/01/05: Re: Use of latches in FSMs
156177: 14/01/09: Re: addsubs on FPGA
156181: 14/01/10: Re: addsubs on FPGA
156182: 14/01/10: Re: addsubs on FPGA
156185: 14/01/10: Re: addsubs on FPGA
156248: 14/01/21: Re: embedded RAM vs. registers
156262: 14/01/27: Re: embedded RAM vs. registers
156282: 14/02/05: Re: Verilog (Xilinx): Virtual tristate or muxes?
156771: 14/06/24: Re: A new domain for FPGAs ? Function approximation
156776: 14/06/24: Re: A new domain for FPGAs ? Function approximation
156852: 14/07/09: Re: Using FPGA as dual ported ram
156986: 14/08/11: Re: Basic question: sequence of execution within FPGAs
157003: 14/08/21: Re: calculations of logic vectors and constant
157653: 15/01/20: Re: Altera Cyclone II
157854: 15/04/20: Re: Choosing the right FPGA board
158027: 15/07/10: Re: Dynamic Array in VHDL
158618: 16/02/03: Re: Fully preposterous gate arranger
jong moo kim:
4246: 96/10/04: I want best synthesis tool for fpga/cpld.
4245: 96/10/04: I want best synthesis tool for fpga/cpld.
Jong-Heon Lee:
9234: 98/03/04: Re: Questions about creating personal package
Joni Dambre:
11577: 98/08/25: ZSA
18398: 99/10/22: pin limitation
18468: 99/10/26: Re: XILINX: XDL - is this a secret?
jonno:
53680: 03/03/19: Re: Quartus2 : assigning I/O pins
Jonny:
43364: 02/05/20: Request: PCI to ISA Firewire and USB2.0 Advice Please
Jonny Cochrane:
4404: 96/10/24: win95 env variables
jonpry:
150060: 10/12/08: LPDDR on spartan-3e
150064: 10/12/09: Re: LPDDR on spartan-3e
150070: 10/12/09: Re: LPDDR on spartan-3e
150072: 10/12/09: Re: LPDDR on spartan-3e
150085: 10/12/10: Re: LPDDR on spartan-3e
150089: 10/12/10: Re: LPDDR on spartan-3e
150090: 10/12/10: Re: LPDDR on spartan-3e
153760: 12/05/15: Spartan-6 66mhz pci
153770: 12/05/16: Re: Spartan-6 66mhz pci
153823: 12/05/30: ISERDES2 divide factor
<jonpry@gmail.com>:
119939: 07/05/29: spartan-iie
119978: 07/05/30: Re: spartan-iie
121900: 07/07/14: spartan-3e idcode
121935: 07/07/15: Re: spartan-3e idcode
121937: 07/07/15: Re: spartan-3e idcode
121974: 07/07/16: Re: spartan-3e idcode
122472: 07/07/27: spartan-3e spi problems
122491: 07/07/29: Re: spartan-3e spi problems
123959: 07/09/07: Re: VCCAUX too high on a Spartan 3 design
127611: 08/01/03: Differential output drive-strength in spartan-3
127614: 08/01/03: Re: Differential output drive-strength in spartan-3
127616: 08/01/03: Re: Differential output drive-strength in spartan-3
137875: 09/02/01: Re: Selecting a starter FPGA board
137876: 09/02/01: Re: What software do you use for PCB with FPGA ?
153905: 12/06/28: Re: ISERDES2 divide factor
<jonyt@eng.tau.ac.il>:
120797: 07/06/17: anyone know a FPGA designer?
jools:
53288: 03/03/10: Atmel FPGA uk
53721: 03/03/20: FPGA choice (UK)
Joon Lee:
15622: 99/04/03: Re: Schematic Capture & FPGA synthesis
15624: 99/04/03: Re: IP cores and software industry
15623: 99/04/03: Re: How to implement Matched Filter in FPGA?
Joona I Palaste:
77194: 04/12/29: Re: Primers for Handel-C; Handel-C efficiency
Joona R:
54842: 03/04/20: bidirectional differential pairs, possible?
54911: 03/04/21: Re: bidirectional differential pairs, possible?
54912: 03/04/21: Re: bidirectional differential pairs, possible?
54956: 03/04/22: Re: bidirectional differential pairs, possible?
54957: 03/04/22: Re: bidirectional differential pairs, possible?
55106: 03/04/26: Using Cyclone's PLL
55347: 03/05/05: Ibis for Cyclone?
55372: 03/05/06: Re: Ibis for Cyclone?
55373: 03/05/06: Re: Ibis for Cyclone?
59192: 03/08/11: Cyclone's LVDS and Quartus II
Joonas Timo Taavetti Kekoni:
64413: 04/01/02: Re: Reverse engineering an EDIF file?
jorbedo:
145247: 10/02/03: Unknown LVDS pinout order
<jorchi@gmail.com>:
81366: 05/03/22: Problem writing Pinouts on Webpack
Jordan Fix:
153579: 12/03/31: Low latency FPGA options
153639: 12/04/08: Best FPGA for algorithmic acceleration
Jordan Swartz:
10997: 98/07/09: high-speed place and route
11049: 98/07/15: Re: high-speed place and route
11051: 98/07/15: Re: high-speed place and route
11052: 98/07/15: Re: high-speed place and route
Jordi:
91751: 05/11/11: FPGA KIT recommendation
91770: 05/11/12: Re: FPGA KIT recommendation
97226: 06/02/19: help with VGA timings
97302: 06/02/20: Re: help with VGA timings
133922: 08/07/19: Xilinx EDK OPB bus compatibility
jorge:
4616: 96/11/21: Which Mentor Graphics synthesis tool?
Jorge:
84877: 05/05/31: Re: FPGA Boards
84880: 05/05/31: JTAG Programming Problem
99364: 06/03/23: Changes on xapp765 for ISE/EDK7.1 and 8.1?
120583: 07/06/11: EDK 9.1 + Virtex 5 Hard MAC
Jorge Guajardo:
17102: 99/06/30: Accepted Papers at CHES
17204: 99/07/08: CHES Conference Preliminary Program
Jorge Ivonnet:
8914: 98/02/06: Altera Timing Requirements
Jorge Jure Zaninovich:
11161: 98/07/21: Re: Shift Invarient Bit Transform
Jorge Neves:
29160: 01/02/08: Xilinx 4010E development kit
29450: 01/02/21: How to get Xilinx FPGA demo board?
Jorge P. Seidel:
4272: 96/10/08: Re: Reversible LFSR?
4274: 96/10/08: Re: Reversible LFSR?
jorge quintino:
22840: 00/05/26: help
Jorge Seidel:
2132: 95/10/18: Re: LPM Information
<jorgen.gade@gmail.com>:
108364: 06/09/09: Anyone who have succeeded with BPI configuration on the Spartan-3E Starter Kit
Jos De Laender:
5582: 97/02/26: Re: Rising_Edge/Falling_Edge Functions
5708: 97/03/10: Re: Rising_Edge/Falling_Edge Functions
7658: 97/10/01: Re: book
15684: 99/04/08: Re: Data Types and Synthesis
17542: 99/08/09: Re: comparison with xxxx
36796: 01/11/20: Re: Log2(x) for vhdl?
64161: 03/12/18: Re: VHDL comments in Vim?
72939: 04/09/08: Re: why systemc?
72958: 04/09/09: Re: why systemc?
jos de laender sh144 7461:
1882: 95/09/15: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
1958: 95/09/25: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
1959: 95/09/25: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
Jos Dreesen:
141953: 09/07/19: How to integerate Firmware into an FPGA
Jos? Luiz Martins:
81616: 05/03/28: Quartus II 4.1 Problem
81644: 05/03/29: Re: Quartus II 4.1 Problem
JoSa:
148502: 10/07/28: Overheated FPGA? (Spartan-3E)
Josan:
62517: 03/10/31: Microblaze & ucLinux for XSV800
Josan Moreno:
17522: 99/08/05: Support of XS40 in Jbits new version
17698: 99/08/25: Jbits for XS40?
38724: 02/01/23: Post-synthesis simulation with Modelsim from Leonardo Netlist
39379: 02/02/07: Design with Triscend E5
44366: 02/06/18: XC6200 Synopsys synthesis libraries
44874: 02/07/03: Modelsim 5.6a for Linux execution problem
Jose:
20373: 00/02/08: EDIF info
20425: 00/02/10: RE: EDIF info
jose:
61137: 03/09/29: Spartan 2e implementation
Jose Antonio:
70899: 04/07/01: Re: Newbie Q
Jose Antonio Moreno Zamora:
17850: 99/09/13: JERC6k
Jose Carlos Alves:
141: 94/08/30: Incremental reconfiguration ?
1219: 95/05/17: Can the X4010 replace a X4003 ?
Jose Commins:
41571: 02/04/02: Re: Data Compression in FPGAs
41611: 02/04/03: Re: Data Compression in FPGAs
Jose De Castro:
552: 94/12/30: LPM Docs & Resources
1648: 95/08/10: EDA Newsgroup Archive Via WWWeb
Jose I Quinones:
37257: 01/12/05: For Sale: Huge Xilinx FPGA lots
JOSE MANUEL DIAZ RIVERA:
7391: 97/09/06: arte
Jose Paredes:
5119: 97/01/24: Re: FPGA & division
5148: 97/01/27: Re: FPGA & division
7263: 97/08/19: Re: Xilinx & Altera using same configuration lines?
Jose T. de Sousa:
68325: 04/04/01: How to advertise in www.fpga-faq.com/FPGA_Boards.shtml
Jose'Pedro Abreu:
2477: 95/12/14: Looking for OpenABEL
Josef Däubler:
25787: 00/09/20: Placement and routing of Xilinx physical macro can't be locked
Josef Fleischmann:
18628: 99/11/04: Simulation of FPGA design. Please Help!
Josef Moellers:
161642: 20/02/13: Code block in icestudio
161643: 20/02/13: Re: Code block in icestudio
161645: 20/02/13: Re: Code block in icestudio
161651: 20/02/14: Re: Code block in icestudio
161654: 20/02/14: Re: Code block in icestudio
161661: 20/02/17: Re: Code block in icestudio
161666: 20/02/20: Re: Code block in icestudio
Josep Duran:
43292: 02/05/18: Re: PCI Board Project
59117: 03/08/08: Re: Upgrading OS or WebPack
64182: 03/12/19: Re: www.fpga-faq.com
65181: 04/01/21: Soft failures (?) 9536XL
65208: 04/01/22: Re: Soft failures (?) 9536XL
109131: 06/09/21: Re: MicroFpga = program an FPGA as it would be a MCU !
111891: 06/11/12: Re: Area Constraints in Xilinx
111892: 06/11/12: Re: Pad to Setup, Clock to Pad
111919: 06/11/13: Re: Pad to Setup, Clock to Pad
113859: 06/12/26: Re: Help with xilinx simulation?
114630: 07/01/21: Re: project help
115942: 07/02/26: Re: XC3S400 and XC3S500E in PQ208
116075: 07/02/28: Re: XC3S400 and XC3S500E in PQ208
133941: 08/07/20: Re: The littlest CPU
Josep Durán:
75586: 04/11/10: Re: Where to find very basic FPGAs
77364: 05/01/05: Re: Whither common courtesy ?
97951: 06/03/02: Re: How do I make dual-port RAM from single port RAM?
98142: 06/03/06: Re: How do I make dual-port RAM from single port RAM?
101505: 06/05/02: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
105338: 06/07/20: Re: xess board problem (error downloading into ram)
joseph:
92692: 05/12/05: Re: Xilinx V4 ISERDES problem
Joseph:
81455: 05/03/23: Xilkernel: configure to use 2 PPCs
81743: 05/03/30: Re: Xilkernel: configure to use 2 PPCs
81936: 05/04/04: Re: Xilkernel: configure to use 2 PPCs
83023: 05/04/21: PPCs sharing an OCM BRAM
83037: 05/04/21: Re: PPCs sharing an OCM BRAM
83040: 05/04/21: Re: PPCs sharing an OCM BRAM
83589: 05/05/03: Simulating custom peripherals
83722: 05/05/05: Re: Simulating custom peripherals
83813: 05/05/06: Re: Simulating custom peripherals
83815: 05/05/06: Re: how can i join the comp.arch.fpga group
83899: 05/05/09: Re: Simulating custom peripherals
83904: 05/05/09: Re: Simulating custom peripherals
84583: 05/05/21: Custom IP and BFM simulation help
86911: 05/07/08: Ethernet reference design for ML310?
86915: 05/07/08: Re: Ethernet reference design for ML310?
86977: 05/07/11: Re: Ethernet reference design for ML310?
89399: 05/09/14: Re: ARM IP Core implementation in FPGA
89602: 05/09/20: Re: SoC embedded FPGA
90109: 05/10/04: XMD and xilmfs help
90669: 05/10/18: Re: XMD and xilmfs help
94702: 06/01/16: BRAM/XMD strangeness?
94710: 06/01/16: Re: BRAM/XMD strangeness?
94711: 06/01/16: Re: BRAM/XMD strangeness?
94777: 06/01/17: Re: BRAM/XMD strangeness?
94857: 06/01/18: Re: xilmfs on flash
94898: 06/01/18: Re: xilmfs on flash
94976: 06/01/19: Re: xilmfs on flash
96395: 06/02/02: Re: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
97995: 06/03/02: Re: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
98690: 06/03/14: Using XMD to upload from board
99501: 06/03/25: Re: Ace file for design with dual ppc405
99990: 06/03/31: Re: Ace file for design with dual ppc405
100163: 06/04/04: Re: Sharing BRAM between Xilinx PowerPC's (on data-OCM ports)
100418: 06/04/08: Re: shared BRAM between PPC and FPGA fabric
101454: 06/05/01: Re: fpga programming
101949: 06/05/08: Re: Anyone use Xilinx ppc405 profiling tools?
102936: 06/05/23: Re: Anyone use Xilinx ppc405 profiling tools?
103157: 06/05/26: Xilinx IP wizard help
103160: 06/05/26: Re: Xilinx IP wizard help
103312: 06/05/30: PLB transfers: PPC to IP
103936: 06/06/15: Re: ARM cores in FPGA ?
104252: 06/06/21: Re: Linking/mapping code sections with Xilinx EDK
104358: 06/06/25: Re: no ram core simulation with free Ise ?
106888: 06/08/22: Re: Modelsim SE Simulation
106907: 06/08/22: Re: Modelsim SE Simulation
108569: 06/09/13: Re: use of Barrel shifter IN ARM TDMI 9
112795: 06/11/29: FPGA workstation - should I wait for Window Vista?
112808: 06/11/29: Re: FPGA workstation - should I wait for Window Vista?
112872: 06/11/30: Re: FPGA workstation - should I wait for Window Vista?
114521: 07/01/18: Re: ARM AHBA 1Kbyte boundary issue
114531: 07/01/18: Re: ARM AHBA 1Kbyte boundary issue
124398: 07/09/20: Comparing Adder synthesis techniques
127073: 07/12/11: Xilinx : Incorrect PACE file generation from schematic
130402: 08/03/22: Viewing internal signals with ModelSim
130923: 08/04/05: PLA datasheet - PLS161
Joseph Tan:
84859: 05/05/31: Nios II - Booting software from Flash
84908: 05/05/31: Re: Nios II - Booting software from Flash
85685: 05/06/13: Re: Nios II - Booting software from Flash
Joseph A. Legris:
17918: 99/09/17: Re: Question for Circuit Designers of Large High-Speed Boards: Best Means to
Joseph C. Su:
18971: 99/11/23: Re: implementing TCP/IP on PLD
Joseph Camp:
68983: 04/04/23: LMB BRAM IF Controller
Joseph Goldburg:
68774: 04/04/18: dumb question CPLD or FPGA
Joseph Gottlieb:
2683: 96/01/24: Multipliers? How many different arch?
Joseph H Allen:
500: 94/12/09: Re: driving PCI
544: 94/12/28: Re: Which FPGA should I be looking at
1018: 95/04/14: Re: $40 Million For NeoCAD & A New FPGA Synthesis Tool
1031: 95/04/18: Re: Free Hardware
1665: 95/08/12: Re: Clocking methods - which is prefered?
1781: 95/08/31: program for xilinx parts
3257: 96/05/04: Re: Simple Xilinx board (and cool application)
4466: 96/11/01: Re: What is the fastest fpga for ...
5280: 97/02/03: Xilinx keys break on fast machines
6405: 97/05/21: Re: VHDL PCI FPGA Implementation
6578: 97/06/03: Re: Altera Versus Xilinx
6687: 97/06/13: 100MHz SDRAMs with Xilinx?
6769: 97/06/26: Re: FPGA prototype board
6803: 97/06/29: fast scopes: how?
6866: 97/07/03: Re: fast scopes: how?
6874: 97/07/04: Re: Fast sampling techniques. Was: Fast scopes, How?
6902: 97/07/07: Re: fast scopes: how?
6909: 97/07/08: xilinx pci question...
6995: 97/07/21: PCI burst transfers
7002: 97/07/22: Re: PCI burst transfers
7129: 97/08/04: Re: PCI burst transfers
7330: 97/08/27: Re: Xilinx PCI simulation problem...
7353: 97/08/29: PCI bus abuse
7354: 97/08/29: fpga configuration over PCI
7357: 97/08/31: Re: fpga configuration over PCI
7360: 97/09/01: Re: fpga configuration over PCI
7367: 97/09/02: Re: fpga configuration over PCI
7396: 97/09/06: Re: export pins from MAX+ to orcad schem symbol
7399: 97/09/06: Re: Which FPGA ?
7400: 97/09/07: Xilinx XACT for sale
7404: 97/09/07: Re: Joseph Allen's Ubiquitous tagline (was, in this case Re: Which FPGA ?)
7429: 97/09/09: Re: HELP: FIFO's on an FPGA
7437: 97/09/10: Re: HELP: FIFO's on an FPGA
7549: 97/09/21: Re: Hacking bitstream formats
7573: 97/09/23: Re: Hacking bitstream formats
7605: 97/09/26: Still for sale OrCAD SDT & Xilinx XACT
7616: 97/09/28: Re: Still for sale OrCAD SDT & Xilinx XACT
7642: 97/09/30: Re: Problem using FAST config mode with X4kE part?
7647: 97/09/30: Xilinx license idiocy
7651: 97/09/30: Re: Xilinx license idiocy
7649: 97/09/30: Re: Xilinx license idiocy
7662: 97/10/01: Re: Xilinx licensie idiocy
7688: 97/10/02: Re: High Speed FPGAs
7697: 97/10/03: Re: FPGA multiprocessors
7699: 97/10/04: Re: bidirectional bus problem
7711: 97/10/06: Re: bidirectional bus problem
7727: 97/10/07: Re: FPGA multiprocessors
8232: 97/12/02: Re: what is metastability time of a flip_flop
8301: 97/12/06: Re: Xilinx P&R - how does M1 compare to XACT6?
8387: 97/12/12: Re: what is metastability time of a flip_flop
8471: 97/12/18: xc4000e tms/tck/tdi/tdo pins
8694: 98/01/20: Re: PCI question
8695: 98/01/20: Re: SDRAM Interface from an FPGA
8794: 98/01/27: Re: SDRAM Interface from an FPGA
9494: 98/03/18: Re: Strange Xilinx question?
9683: 98/03/30: Re: XactStep6 - The cure for a dongle
9684: 98/03/30: Re: XactStep6 - The cure for a dongle
9810: 98/04/07: Re: Effects of IC production
10094: 98/04/27: Re: Make a delay in Xilinx FPGAs (more Details)?
10257: 98/05/08: Re: Low power FPGA design
10337: 98/05/13: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
10369: 98/05/15: Re: Minimal ALU instruction set.
10383: 98/05/15: Re: Minimal ALU instruction set.
10415: 98/05/18: Re: Minimal ALU instruction set.
10416: 98/05/18: Re: Minimal ALU instruction set.
10436: 98/05/19: Re: Minimal ALU instruction set.
10481: 98/05/22: Re: Minimal ALU instruction set.
11602: 98/08/26: Re: How to design a PLL
11874: 98/09/15: Re: ASIC -> FPGA async issues
11930: 98/09/19: Re: ASIC -> FPGA async issues
12736: 98/10/27: New free FPGA CPU
12768: 98/10/28: Re: New free FPGA CPU
12826: 98/10/31: Re: New free FPGA CPU
12830: 98/10/31: Re: New free FPGA CPU
12841: 98/11/01: Re: New free FPGA CPU
12857: 98/11/02: Re: New free FPGA CPU
12877: 98/11/03: Re: New free FPGA CPU
12921: 98/11/05: Re: New free FPGA CPU
12950: 98/11/06: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
13417: 98/12/02: Re: XILINX FPGA reaches GHz speeds
13442: 98/12/03: Re: XILINX FPGA reaches GHz speeds
15560: 99/03/30: Re: FPGAs with ECL-compatible I/Os
17087: 99/06/30: Re: FGPA Servo Motor Controller
17136: 99/07/02: Re: FGPA Servo Motor Controller
17131: 99/07/01: neuron logic
17789: 99/09/03: Re: FreeDES and Free6502 Comments
17791: 99/09/04: Re: FreeDES and Free6502 Comments
18098: 99/09/29: GSR
18111: 99/09/30: reset in xilinx
18129: 99/10/02: Re: reset in xilinx
18170: 99/10/05: Re: reset in xilinx
18132: 99/10/02: Re: reset in xilinx
18784: 99/11/15: Re: Need advice on interfacing SDRAM modules
18912: 99/11/21: Re: Need advice on interfacing SDRAM modules
18943: 99/11/22: Re: PADS Experience?
18945: 99/11/22: Re: Filter Coefficient and Output Quantisation
18946: 99/11/22: Re: Why not Lucent ORCA FGPAs?
19256: 99/12/09: Re: JTAG on PCI slot
19268: 99/12/09: Re: JTAG on PCI slot
19511: 99/12/28: Re: VGA controller in FPGA
19512: 99/12/28: Re: VGA controller in FPGA
19821: 00/01/13: Re: PCI Bus Problems with Burst Transfers
20033: 00/01/24: Re: Virtex Fine Pitch BGA pcb layout
20034: 00/01/24: Re: Virtex Fine Pitch BGA pcb layout
20091: 00/01/27: Re: Virtex Fine Pitch BGA pcb layout
20641: 00/02/16: Xilinx hold time problems...
20643: 00/02/16: Re: Xilinx hold time problems...
20674: 00/02/17: Re: Xilinx hold time problems...
20675: 00/02/17: Re: Xilinx hold time problems...
21085: 00/03/06: Re: Comment on Atmel AT40K ?
21093: 00/03/06: Re: Comment on Atmel AT40K ?
21192: 00/03/09: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86,
24063: 00/07/25: Re: Silicon Valley Housing Nightmare?
25304: 00/09/05: Re: Mealy vs Moore FSM model
25323: 00/09/06: Re: Mealy vs Moore FSM model
40461: 02/03/07: Need XC2V4000/6000-4FF1152CES
48825: 02/10/25: Re: Pin locking Virtex 2 FPGA
48828: 02/10/25: Re: Pin locking Virtex 2 FPGA
48878: 02/10/25: Re: PCI burst reads w/ Spartan
49166: 02/11/04: Re: 16-bit FGPA CPU core (commercial)
59083: 03/08/08: Re: Offshore engineering
59564: 03/08/21: Re: Old Xilinx FPGAs
59565: 03/08/21: Re: Old Xilinx FPGAs
70904: 04/07/01: Re: *RANT* Ridiculous EDA software "user license agreements"?
71048: 04/07/06: Re: new Lattice FPGAs vs Cyclone and SpartanIII
71220: 04/07/12: Re: Info on FPGA routing algorithms?
71235: 04/07/12: Re: NIOS 2 HAL, libraries, ...
71658: 04/07/27: Re: www.opencores.org?
71728: 04/07/28: Re: XILINX RocketIO / MGT signal quality problems
72001: 04/08/05: Microblaze / XMD question
72238: 04/08/12: Re: How important are software tools while choosing FPGA
76584: 04/12/06: Re: internal tristates and busses
81018: 05/03/16: Re: Which HDL?
84117: 05/05/12: V4 vs. Stratix-II...
84187: 05/05/13: Re: V4 vs. Stratix-II...
85217: 05/06/06: board-level simulation?
85509: 05/06/10: set seed in 6.2i or 6.3i -timing?
85673: 05/06/13: Re: Synplify vs XST...
86344: 05/06/26: Re: ISE 7.1 Service Pack 2 - Ready yet?
86382: 05/06/27: Re: Two Verilog FSM style compare
86408: 05/06/27: Re: Two Verilog FSM style compare
86478: 05/06/28: Re: Two Verilog FSM style compare
87210: 05/07/19: Re: "Tbufs don't exist"
98368: 06/03/09: Re: for all those who believe in ASICs....
99169: 06/03/21: Re: microprocessor design: where to go from here?
99726: 06/03/28: Re: OpenSPARC released
99733: 06/03/28: Re: OpenSPARC released
99744: 06/03/28: Re: OpenSPARC released
99860: 06/03/30: Re: OpenSPARC released
99867: 06/03/30: Re: OpenSPARC released
106925: 06/08/22: PCIe latency
118354: 07/04/24: Altera DPA compatible with Xilinx IOSERDES?
118511: 07/04/28: fast arbiters (was Re: How to design an abitration cicuit...)
118709: 07/05/02: Re: fast arbiters (was Re: How to design an abitration cicuit...)
118794: 07/05/03: Re: fast arbiters (was Re: How to design an abitration cicuit...)
125974: 07/11/10: Re: Embedded Linux & Code Security
126129: 07/11/15: Re: Xilinx Virtex-II Newbie
126130: 07/11/15: Re: FPGA for hobby use
126215: 07/11/17: Re: FPGA for hobby use
126254: 07/11/18: Re: Lattice Semi
126300: 07/11/19: Re: Low cost FPGA w/serdes
132195: 08/05/16: Re: Cyclone 3 margins: none at all at 3.3v
132262: 08/05/20: Re: Stratix IV Announced
132963: 08/06/11: Re: New Home
133087: 08/06/18: Re: Cadence offers to buy Mentor Graphics for $1.45B
133172: 08/06/19: Re: which commercial HDL-Simulator for FPGA?
133177: 08/06/19: Re: which commercial HDL-Simulator for FPGA?
133211: 08/06/20: Re: which commercial HDL-Simulator for FPGA?
133212: 08/06/20: Re: which commercial HDL-Simulator for FPGA?
133476: 08/07/01: Re: Quartus-II 8.0 resource-sharing? (why inferred addsub takes 2x LUTs?)
134777: 08/08/29: Re: need fast FPGA suggestions
135215: 08/09/21: Re: 50 Ohm Analog Output of FPGA
135335: 08/09/26: Re: Clocking Sync Burst SRAM
135942: 08/10/22: Re: How to synthesize a delay of around 10 ns in FPGA?
136134: 08/11/03: Re: Altera simulation models performance
137964: 09/02/03: Re: Why the second flip-flop in Virtex-6?
137969: 09/02/03: Re: Why the second flip-flop in Virtex-6?
138059: 09/02/05: Re: Why the second flip-flop in Virtex-6?
138183: 09/02/09: Re: Is this phase accumulator trick well-known???
141007: 09/06/02: Tektronix vs. Agilent, probes
141017: 09/06/02: Re: Tektronix vs. Agilent, probes
155590: 13/07/25: New Relay Computer
155838: 13/09/29: Lattice diamond / MachXO2
155843: 13/09/30: Re: Lattice diamond / MachXO2
155844: 13/09/30: Re: Lattice diamond / MachXO2
155848: 13/09/30: Re: Lattice diamond / MachXO2
155860: 13/10/04: Re: Lattice Diamond & tristate
155862: 13/10/05: Re: Lattice Diamond & tristate
155885: 13/10/11: Re: reset strategy FPGA Igloo
155886: 13/10/11: extra reset pin should not be needed..
155895: 13/10/14: Re: extra reset pin should not be needed..
155899: 13/10/14: Re: extra reset pin should not be needed..
155907: 13/10/15: Re: Xilinx tools for XC3020???
155925: 13/10/16: Re: reset strategy FPGA Igloo
155927: 13/10/16: Re: reset strategy FPGA Igloo
155950: 13/10/20: Re: draw lines, circles, squares on FPGA by mouse and display on VGA ( not use NIOS)
156071: 13/11/22: Mill: FPGA version?
156099: 13/11/22: Re: Mill: FPGA version?
156105: 13/11/23: Re: Mill: FPGA version?
Joseph Hlebasko:
19193: 99/12/04: Re: CAN testing - Any CANbus cores out there?
Joseph J. Kubicky:
911: 95/03/29: Excuse me while I vent about Data I/O & Abel...
1501: 95/07/03: Who makes low-power 22v10-type PLDs?
1529: 95/07/09: Alternative to low-power 22v10...
Joseph Legris:
11655: 98/08/29: Re: FACTS: Evolutionary Electronics Book
Joseph LoCicero IV:
3603: 96/07/02: Re: INDUSTRY GADFLY "Why I Hate Wally"
Joseph Mak:
30687: 01/04/24: System Spec
Joseph Navarro Hong -FT-:
1890: 95/09/15: Re: Fast FPGA's?
Joseph Oravec:
34319: 01/08/21: Re: Slowing PCI for FPGA
Joseph S. Gottlieb:
1491: 95/06/28: Verilog Vs. VHDL
Joseph Samson:
89900: 05/09/29: Re: IPIF interface not fast enough
90971: 05/10/26: Re: Xilinx ISERDES
91001: 05/10/27: Re: Xilinx ISERDES
91666: 05/11/10: Re: Can't pack into OLOGIC
92063: 05/11/21: Re: XST options in XPS
92359: 05/11/28: Re: instruction counts and cache hits/misses on FPGA
92542: 05/12/01: Re: Which Phy transceiver for 10/100 ethernet?
92823: 05/12/07: Re: FPGA development board with digital image camera
93786: 05/12/30: Re: Xilinx ML402 DRAM control
94268: 06/01/09: Re: concurrent auto precharge - memory controller
94318: 06/01/09: Re: concurrent auto precharge - memory controller
94407: 06/01/11: Re: SDRAM Clock Skew
95955: 06/01/27: Re: SDRAM Controller
97101: 06/02/16: Re: VHDL or verilog
97125: 06/02/17: Re: Xilinx EDK GPIO: Can I drive internal logic with it?
97325: 06/02/20: Re: Is FPGA code called firmware?
97366: 06/02/21: Re: Is FPGA code called firmware?
98073: 06/03/04: Re: EDK: choices for simple internal control
100609: 06/04/13: Re: PCB Stack
100623: 06/04/13: Re: RGMII mode on V4 Hard Tri-EMAC core
100627: 06/04/13: Re: RGMII mode on V4 Hard Tri-EMAC core
100853: 06/04/19: Re: RGMII mode on V4 Hard Tri-EMAC core
102074: 06/05/10: Re: Xilinx ISE 8.1 Makefile
102233: 06/05/12: Re: How to check IOB register packing?
102252: 06/05/12: Re: How to check IOB register packing?
103102: 06/05/25: Re: setting max fanout with xps flow
103523: 06/06/05: Re: Help on DDR SDRAM contoller generated by MIG1.5
103578: 06/06/06: Re: Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5
103579: 06/06/06: Re: Help on DDR SDRAM contoller generated by MIG1.5
103782: 06/06/11: Re: initialization sequence and auto refresh for sdr-sdram
103784: 06/06/11: Re: initialization sequence and auto refresh for sdr-sdram
103793: 06/06/12: Re: initialization sequence and auto refresh for sdr-sdram
103794: 06/06/12: Re: initialization sequence and auto refresh for sdr-sdram
103893: 06/06/14: Re: How do I use the DDS core in a verilog flow?
104005: 06/06/16: Re: How do I use the DDS core in a verilog flow?
104008: 06/06/16: Re: Doubts on IBUFGDP
104303: 06/06/23: Re: Newbie in Chipscope-changes need to route bidirectional data
104333: 06/06/24: Re: Achieving timing in Xilinx EDK designs
104348: 06/06/25: Re: Achieving timing in Xilinx EDK designs
104365: 06/06/26: Re: Newbie in Chipscope-changes need to route bidirectional data
104728: 06/07/05: Re: PPC and Chipscope?
104736: 06/07/05: Re: PPC and Chipscope?
105081: 06/07/13: Re: Can't get my Verilog Peripheral to import into XPS! Any tricks?
105092: 06/07/13: Re: Can't get my Verilog Peripheral to import into XPS! Any tricks?
105102: 06/07/13: Re: Can't get my Verilog Peripheral to import into XPS! Any tricks?
105138: 06/07/14: Re: Using Samsung DDR2 memory with Xilinx Memory Interface Generator
105362: 06/07/20: Re: MIG DDR2 controller does not work (reset problems?)
105387: 06/07/21: Re: MIG DDR2 controller does not work (reset problems?)
105398: 06/07/21: Re: MIG DDR2 controller does not work (reset problems?)
105430: 06/07/22: Re: MIG DDR2 controller does not work (reset problems?)
105615: 06/07/27: Re: ISE 8.2i and EDK8.1i
105794: 06/08/01: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
105811: 06/08/01: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
106029: 06/08/05: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
106239: 06/08/09: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
106289: 06/08/10: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
106801: 06/08/19: Re: xc2vp30-6ff1152
109426: 06/09/26: Re: Newbee question - how to upgrade to Xilinx ISE/EDK 8.2 from 8.1
109528: 06/09/28: Re: ddr2 sodimm controller
110494: 06/10/16: ISE On Intel Mac
110687: 06/10/19: Re: Fixing Down Parts of Logic in ISE (8.2)
110842: 06/10/24: Re: Xilinx Virtex4 DDR clock output
111078: 06/10/28: Re: Xilinx Virtex4 Outputs for Camera Link
111079: 06/10/28: Re: Chipscope and debugger through the same JTAG port
111159: 06/10/30: Re: Chipscope and debugger through the same JTAG port
111520: 06/11/04: Re: Cleaning generated files in Xilinx 8.2 EDK and ISE
111980: 06/11/14: Re: Fastest ISE Compile PC?
113059: 06/12/05: Re: Usage of BUFIO in Virtex 4?
113365: 06/12/12: Re: DDR2 DIMM memory termination resistors?
113711: 06/12/19: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV
113844: 06/12/24: Re: Signal <foo> is assigned but never used. XST Warning help
113934: 06/12/29: Re: FPGA workstation - should I wait for Window Vista?
114825: 07/01/24: Re: FPGA workstation - should I wait for Window Vista?
114989: 07/01/29: Re: Problem with verilog program
114990: 07/01/29: Re: Problem with pin assign using CASE
115214: 07/02/02: Re: ISE 9.1 SAY YOURS OPINION
115231: 07/02/04: Re: ISE 9.1 SAY YOURS OPINION
115272: 07/02/05: Re: ISE 9.1 SAY YOURS OPINION
115284: 07/02/06: Re: DDR FPGA Design
115296: 07/02/06: Re: ISE 9.1 SAY YOURS OPINION
115367: 07/02/08: Re: question abt DPRAM
115410: 07/02/09: Re: Need advice to help improve timing on V4 FX
115420: 07/02/09: Re: uestion about "clock signal" in Xilinx EDK design. (XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING
115592: 07/02/14: Re: regarding VREF and VCCO and GCLK in virtex 2 pro fpga
115773: 07/02/20: Re: Xilinx MIG DDR2 Documentation
115997: 07/02/27: Re: ISE:Simulation
116811: 07/03/19: Re: IOSTANDARD default value in Xilinx UCF-Files?
116828: 07/03/19: Re: IOSTANDARD default value in Xilinx UCF-Files?
117114: 07/03/23: Re: problem while using if or case statements
117255: 07/03/27: Re: PCI-Express drivers with Xilinx FPGA?
118477: 07/04/27: Re: VHDL editing with UltraEdit
118907: 07/05/07: Re: About DDR SDRAM
119457: 07/05/20: Re: EDK 8.1i to EDK 9.1i UCF file errors
120042: 07/05/31: Re: Ise Flow with PowerPC
123408: 07/08/27: Re: Newbie with ISE 9_2_02i_lin gets error : Process "Translate"
123863: 07/09/06: Re: clock skew problems
124516: 07/09/25: Re: DRAM modules - RIMM, SODIMM,UDIMM..etc
124547: 07/09/26: Re: XST corrupts my state machine. Only disabling FSM encoding helps
125442: 07/10/25: Re: builing a SPI interface in vhdl
126356: 07/11/20: Re: 33+ Regs in PLB IPIF
126404: 07/11/21: Re: An error occured while using Dual Port Block Memory
126446: 07/11/22: Re: DDR2 dqs pin // virtex4
126454: 07/11/23: Re: DDR2 dqs pin // virtex4
126623: 07/11/28: Re: CPU design uses too many slices
126813: 07/12/03: Re: Xilinx ISE Bugs
127122: 07/12/12: Re: Initializing Micron DDR2 Memory
127848: 08/01/09: Re: MPMC3, DDR 32Mx16, S3E1200, single bank, impossible?
127886: 08/01/09: Re: MPMC3, DDR 32Mx16, S3E1200, single bank, impossible?
129163: 08/02/16: Re: Ballpark PLB frequency
130240: 08/03/18: Re: Help on Virtex-II Pro global clocks.
132035: 08/05/10: Re: how to set trigger in ChipScopePro for this
132817: 08/06/07: Re: HDL tricks for better timing closure in FPGAs
132818: 08/06/07: Re: HDL tricks for better timing closure in FPGAs
133312: 08/06/24: Re: Migrating to 9.2i from 8.2i
134334: 08/08/06: Re: Downsizing Verilog synthesization.
Joseph Su:
18797: 99/11/16: Q: implementing TCP/IP on PLD
18818: 99/11/17: Re: implementing TCP/IP on PLD
18819: 99/11/17: Re: implementing TCP/IP on PLD
Joseph Van der ree:
11868: 98/09/15: Re: A Linear Feedback Shiftregister
Joseph Yiu:
143387: 09/10/08: Re: Implement ARM cores on a FPGA chip?
143397: 09/10/09: Re: Implement ARM cores on a FPGA chip?
143454: 09/10/12: Re: Implement ARM cores on a FPGA chip?
Joseph2k:
95631: 06/01/25: Re: OT:Shooting Ourselves in the Foot
95632: 06/01/25: Re: OT:Shooting Ourselves in the Foot
95634: 06/01/25: Re: OT:Shooting Ourselves in the Foot
95635: 06/01/25: Re: OT:Shooting Ourselves in the Foot
95636: 06/01/25: Re: OT:Shooting Ourselves in the Foot
95637: 06/01/25: Re: OT:Shooting Ourselves in the Foot
95639: 06/01/25: Re: OT:Shooting Ourselves in the Foot
95642: 06/01/25: Re: OT:Shooting Ourselves in the Foot
95769: 06/01/26: Re: OT:Shooting Ourselves in the Foot
95777: 06/01/26: Re: OT:Shooting Ourselves in the Foot
95800: 06/01/26: Re: OT:Shooting Ourselves in the Foot
97487: 06/02/23: Re: Input stage for VHF frequency counter in an FPGA?
joseph2k:
104033: 06/06/17: Re: Xilinx ISE S/W Install kernel version "mismatch"
105109: 06/07/14: Re: Any *really old* Viewlogic / Xilinx users around here? :)
106879: 06/08/22: Re: generating sine-like waveforms
107568: 06/08/30: Re: FPGA -> SATA?
107991: 06/09/03: Re: Spartan 3 and 5V input
108145: 06/09/06: Re: Undergrad project-8051 specifications??
108760: 06/09/16: Re: Performance Appraisals
108762: 06/09/16: Re: Performance Appraisals
108763: 06/09/16: Re: Performance Appraisals
108766: 06/09/16: Re: Performance Appraisals
108784: 06/09/16: Re: Impossible to download WebPACK?
110570: 06/10/18: Re: Looking for internship near Toronto
112348: 06/11/21: Re: board - T562.jpg
112349: 06/11/21: Re: board - T562.jpg
112542: 06/11/24: Re: board - T562.jpg
113972: 06/12/31: Re: (Improve Verilog skill) Recommend CPU core with good document and coding?
119440: 07/05/18: Re: Visio logic symbols
josephbarrymore:
157440: 14/12/10: Re: Problems with Xilinx SDK and LwIP
157441: 14/12/10: Re: Problems with Xilinx SDK and LwIP
JosephKK:
131545: 08/04/24: Re: Survey: FPGA PCB layout
131550: 08/04/24: Re: Survey: FPGA PCB layout
131551: 08/04/24: Re: Survey: FPGA PCB layout
131552: 08/04/25: Re: Survey: FPGA PCB layout
131553: 08/04/24: Re: Survey: FPGA PCB layout
131555: 08/04/24: Re: Survey: FPGA PCB layout
131556: 08/04/24: Re: Survey: FPGA PCB layout
131632: 08/04/27: Re: Survey: FPGA PCB layout
131633: 08/04/27: Re: Survey: FPGA PCB layout
131634: 08/04/27: Re: Survey: FPGA PCB layout
131635: 08/04/27: Re: Survey: FPGA PCB layout
141065: 09/06/04: Re: Tektronix vs. Agilent, probes
142240: 09/07/29: Re: cool chart
142285: 09/08/01: Re: cool chart
josephkk:
156230: 14/01/19: Re: my first microZed board
156231: 14/01/19: Re: my first microZed board
Josh:
134283: 08/08/04: AC coupling on GTX RocketIO clocks
josh forgione:
48262: 02/10/15: AHDL Command Reference?
Josh Fryman:
35797: 01/10/17: Re: High level synthesis will never work well :)
Josh Graham:
68169: 04/03/28: A timing related Question
68353: 04/04/01: Mapping Logic to Virtex II Block RAM
69022: 04/04/25: Inferring Dynamic shift registers in XST
69081: 04/04/26: Re: Inferring Dynamic shift registers in XST
69244: 04/05/02: Behavioural Simulation of a RPM using ModelSim XE
Josh Kramer:
58076: 03/07/14: Aurora Reference Design help
Josh Model:
46059: 02/08/15: Re: Problem with Xilinx mapper
46060: 02/08/15: oops
46112: 02/08/19: Actel Proto Boards
46413: 02/08/28: WebPack FSM woes...
50592: 02/12/13: Re: Single event Upset effect in One Time PROM used for configuration in Xilix FPGA
55380: 03/05/06: Re: Xilinx VirtexII Pro Rocket-IO--Power
55914: 03/05/23: Re: Nois generator - project
55932: 03/05/23: Re: Nois generator - project
56563: 03/06/09: PC-104 dev Boards
56602: 03/06/10: Re: PC-104 dev Boards
59732: 03/08/27: Max finding
59738: 03/08/27: Re: Max finding
59798: 03/08/28: Re: Moving Sum
59799: 03/08/28: Re: Moving Sum
67062: 04/03/04: Re: Jitter in DLLs vs PLLs
68047: 04/03/25: RocketIO 8/10b bypass
71940: 04/08/04: Re: clock synthesis with RocketIO
73480: 04/09/22: Re: How To Synchronize FPGAs
73579: 04/09/24: Re: How To Synchronize FPGAs
75594: 04/11/10: Re: VirtexII-Pro MGT: 8/10 coding bypass problems
76893: 04/12/15: Re: Cyclone device misteriously overheats
107020: 06/08/23: Re: fastest FPGA
141492: 09/06/25: Re: 720 Mhz IF Processing
146273: 10/03/10: Re: Tier Logic introduces the world's first 3D FPGA
Josh Pfrimmer:
37767: 01/12/19: Re: Hardware FPGA questions
38860: 02/01/26: tri-state vs. Mux
38873: 02/01/26: Re: tri-state vs. Mux
40737: 02/03/14: where to start with constraining..
40768: 02/03/14: Re: where to start with constraining..
41183: 02/03/22: Re: another from newbie
52568: 03/02/13: Re: which microprocessor core?
53483: 03/03/13: IFDs in Xilinx Foundation 4.1i
53519: 03/03/14: Re: IFDs in Xilinx Foundation 4.1i
53525: 03/03/14: Re: IFDs in Xilinx Foundation 4.1i
53534: 03/03/14: Re: IFDs in Xilinx Foundation 4.1i
53545: 03/03/15: Re: IFDs in Xilinx Foundation 4.1i
53598: 03/03/17: Re: IFDs in Xilinx Foundation 4.1i
53614: 03/03/17: Re: IFDs in Xilinx Foundation 4.1i
53615: 03/03/17: Re: IFDs in Xilinx Foundation 4.1i
63205: 03/11/17: Memory Initialization: mif, coe, hex, etc,
63244: 03/11/18: Re: Memory Initialization: mif, coe, hex, etc,
63394: 03/11/20: Re: Memory Initialization: mif, coe, hex, etc,
Josh Rosen:
96683: 06/02/08: Re: Which workstation or server should I take to build a state-of-the-art FPGA CAE tool workstation?
97106: 06/02/16: Re: VHDL or verilog
97658: 06/02/25: Re: Combinatorial Division?
97665: 06/02/25: Re: Combinatorial Division?
97671: 06/02/25: Re: Combinatorial Division?
98636: 06/03/13: Re: Why does Xilinx hate version control?
98743: 06/03/15: Re: Why does Xilinx hate version control?
98979: 06/03/18: Re: Support software for XC3042
98984: 06/03/18: Re: ISE 8.1 linux 64bit license key
99308: 06/03/22: Re: Are Quad-processors advantageous?
100156: 06/04/04: Re: ISE under 64-bit Linux?
101173: 06/04/26: Re: Async FPGA ~2GHz
101394: 06/04/30: Re: Book Software for XC3190A?
102347: 06/05/15: Re: Virtex 5 announced
102348: 06/05/15: Re: Xilinx XC4000 series
102403: 06/05/15: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
103301: 06/05/30: Running Xilinx and Altera Tools on Fedora Core 5
103303: 06/05/30: Re: Running Xilinx and Altera Tools on Fedora Core 5
103464: 06/06/02: Re: WebPack on Linux
103494: 06/06/04: Re: WebPack on Linux
103691: 06/06/08: Re: Block Ram vs Distributed Ram
103733: 06/06/09: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
105706: 06/07/28: Re: Verilog case statements
105717: 06/07/29: Re: Verilog case statements
105973: 06/08/03: Re: RocketIO simulation in VCS
106043: 06/08/06: Changing SerDes speed on the V4FX RocketIO
106064: 06/08/07: Re: verilog versus vhdl
106138: 06/08/08: Switching speeds on V4FX RocketIO
106943: 06/08/22: New release of HDLmaker
107848: 06/09/01: Re: easics - crc equations
110499: 06/10/16: Re: WebPack on Linux
110554: 06/10/17: Re: WebPack on Linux
110597: 06/10/18: Re: WebPack on Linux
110663: 06/10/19: Re: WebPack on Linux
110674: 06/10/19: Re: WebPack on Linux
110681: 06/10/19: Re: WebPack on Linux
<Josh.OuterSpace@gmail.com>:
127154: 07/12/12: spartan 3e VQ100 serious question
127155: 07/12/12: Re: spartan 3e VQ100 serious question
127166: 07/12/12: Re: spartan 3e VQ100 serious question
127169: 07/12/12: Re: spartan 3e VQ100 serious question
<josh_eckstein@my-deja.com>:
24496: 00/08/11: Getting into FPGAs
JoshforRefugee:
114312: 07/01/11: Re: Interlock and stall in CPU design?
Joshi:
144569: 09/12/15: what is Timing generating before interfacing?
144570: 09/12/15: Re: what is Timing generating before interfacing?
144577: 09/12/16: Re: Please Help me
Joshi & Joshi:
144487: 09/12/10: Please Help me
144499: 09/12/11: Re: Please Help me
144565: 09/12/14: what is Timing generating before interfacing?
<joshrsmith@gmail.com>:
154884: 13/01/28: Re: Sometimes I Just Don't Get the Tools
Joshua B. Halpern:
2099: 95/10/14: Re: Good materials schools?
joshua j potts:
8249: 97/12/03: Xilinx pullup / pulldown resistors
Joshua Lamorie:
16929: 99/06/17: Logic factoring program
17661: 99/08/20: Smallest Configurator for Xilinx
17679: 99/08/23: JTAG 1149 Info
17723: 99/08/27: FPGA Express: Not enough storage...(etc.)
17728: 99/08/27: Re: microcontroller vs FPGA
17688: 99/08/24: Re: Smallest Configurator for Xilinx
20552: 00/02/14: FPGA Network stack
22650: 00/05/16: Re: Bidirectional BUS!!!
22984: 00/06/07: Re: VHDL code works in foundation 1.5, dosen't work in 2.1?
Joshua Rosen:
1060: 95/04/22: SIS (where do I find it)
Joshua Roy:
161473: 19/09/29: Student seeking for Internship in Digital Design
Joshua Schwartz:
9711: 98/04/01: One time programmables
10704: 98/06/11: floorplanning in xilinx
17700: 99/08/25: Re: microcontroller vs FPGA
Joshua Yin:
54958: 03/04/23: Re: Some suggestions on system design on PCB
54960: 03/04/23: Re: Very low pin count FPGA
54963: 03/04/23: Re: Initial values for internal RAM
55003: 03/04/24: Re: Challenge: (n mod 3) in hardware???
Josip:
136724: 08/12/03: Dynamical alteration of signal path
136728: 08/12/03: Re: Dynamical alteration of signal path
136730: 08/12/03: Re: Dynamical alteration of signal path
136731: 08/12/03: Re: Dynamical alteration of signal path
136788: 08/12/05: Re: Dynamical alteration of signal path
Josselin Lebahar:
29072: 01/02/05: !!!!!!!!!!!!!! Offre d'emploi !!!!!!!!!!!!!!!!!!! URGENT
Jostein Rolstad:
60544: 03/09/16: Reporting in ISE5.1 timing analyzer
Josue P. J. de Freitas:
128637: 08/02/01: Gemac on ML402
José da Rocha:
69432: 04/05/11: FPGA vs Microprocessor: newbie question
José F. da Rocha:
61843: 03/10/14: FPGA/CPLD With Analog Functions?
José Luis Ayala:
17823: 99/09/08: PROBLEMS WITH ORCA
<jothi@singnet.com.sg>:
1590: 95/07/22: Re: Xilinx EPLD's
1666: 95/08/12: Re: Xilinx PROMs
1852: 95/09/09: Re: Lattice ispLSI problem
1905: 95/09/18: Re: Is there a reprogramable XC17256D available?
1946: 95/09/22: Re: Is there a reprogramable XC17256D available?
Jouni Siirtola:
1559: 95/07/14: Has anyone programmed the Lattice in-system-programmable ispLSI2032?
jozamm:
144762: 09/12/30: RTL View of synthezied code
145696: 10/02/19: System design in FPGA
145708: 10/02/20: Re: System design in FPGA
151389: 11/04/01: Re: Ideal FPGA Development Kit
153293: 12/01/26: OT : No daily abridged emails
Joze Dedic:
43197: 02/05/16: Re: PCMCIA interface Logic Between PCMCIA LAN Card and ARM CPU....
43199: 02/05/16: SPARTAN II - Master serial mode configuration problem
43212: 02/05/16: Re: Bidirectional DONE?
52754: 03/02/20: spartan2: combinatorial logic -> clock buffer = problem
52835: 03/02/24: Spartan2 internal bus state?
53955: 03/03/28: Pin failure detection
53964: 03/03/28: Re: Pin failure detection
Jozsef:
106212: 06/08/09: ISE software bug???
106223: 06/08/09: Re: ISE software bug???
106224: 06/08/09: Re: ISE software bug???
106227: 06/08/09: Re: ISE software bug???
106238: 06/08/09: Re: ISE software bug???
106244: 06/08/09: Re: ISE software bug???
106247: 06/08/09: Re: ISE software bug???
106262: 06/08/10: Re: ISE software bug???
106292: 06/08/10: Re: ISE software bug???
108170: 06/09/06: Re: Global constants definition problem
108327: 06/09/08: Re: NON-CLK pins failed to route using a CLK template
112418: 06/11/21: ISE 8.2 & XC9500XL family
112464: 06/11/22: Re: ISE 8.2 & XC9500XL family
Jozsef Ludvig:
1589: 95/07/22: Are the Mach210/230 programming algoritms?
1626: 95/08/06: Re: Double side SMT
JP:
69051: 04/04/26: Re: Newbie question: which choice is right for my engineering project?
69146: 04/04/28: Re: Newbie question: which choice is right for my engineering project?
JP Nicholls:
44913: 02/07/05: Xilinx Spartan-E LVDS at 622Mbps?
45246: 02/07/17: Re: LVDS interface cable recommendation sought
45517: 02/07/25: Re: LVDS interface cable recommendation sought
45522: 02/07/25: Re: LVDS interface cable recommendation sought
48416: 02/10/17: Xilinx FPGA Tools cause Java problems in Internet Explorer
49498: 02/11/13: Problem with Xilinx Application 134 "Synthesizable High-Performance SDRAM Controllers"
55469: 03/05/09: Encrypted bitstream - battery lifetime problem
<JP@noemail.com>:
69011: 04/04/25: Newbie question: which choice is right for my engineering project?
JPC:
20113: 00/01/27: displaying an internal node with Quartus simulation
21336: 00/03/17: Re: Altera literature misleading
22166: 00/04/28: Re: Verilog Compiler ?
26164: 00/10/06: Re: Altera Internal Error
<jpdullius@gmail.com>:
94927: 06/01/19: Re: How to NON_CLK pin that messes my clock
94868: 06/01/18: Re: How to NON_CLK pin that messes my clock
95868: 06/01/26: Re: Current to sink PROG_B low?
jpendlum:
153224: 12/01/12: Re: Trying to select a development board, can somebody help me make an informed choice?
JPIQ:
12776: 98/10/29: Musical Chairs
<JPiqueras.M@gmail.com>:
132163: 08/05/16: Re: Camera link interface
<jpopelish@rica.net>:
118591: 07/04/30: Re: debounce state diagram FSM
JPR:
74668: 04/10/16: BCD to bin convertor
74685: 04/10/16: Re: BCD to bin convertor
74686: 04/10/16: Re: BCD to bin convertor
<jprovidenza@yahoo.com>:
130593: 08/03/27: Re: Xilinx ISE 9.2i out of memory
131841: 08/05/03: Re: Using SRL16
133163: 08/06/19: Re: which commercial HDL-Simulator for FPGA?
133246: 08/06/22: Re: Newbie Verilog Question / ModelSim
135205: 08/09/19: Re: Peter says Good Bye
137287: 09/01/07: Re: DFFR using DFF (only, may be extra gates)
138359: 09/02/17: Re: Troubleshooting fpga design
138452: 09/02/23: Re: Very fast counter in VirtexII
138677: 09/03/04: Re: writing current date to a register
138765: 09/03/09: Re: Timing requirements for generating off-chip clock with DDR
139093: 09/03/20: Re: FPGA users, Please take a few seconds to report SPAM
139546: 09/04/02: Re: clock multipliers, dividers, and more clocks...
139566: 09/04/03: Xilinx Mig bus functional model?
139600: 09/04/06: Re: Modulo-10 counter
139715: 09/04/10: Re: Noise in Stratix3?
139991: 09/04/22: MIG DDR2 controller functional model available
139993: 09/04/22: Re: MIG DDR2 controller functional model available
140017: 09/04/23: Re: MIG DDR2 controller functional model available
140151: 09/04/30: Re: FPGA simulator for face recognition
JPS Nagi:
109529: 06/09/27: EBR Based FIFO ...
139041: 09/03/19: Groundhog 2009 ...
JPSNagi:
138670: 09/03/03: Re: Lattice announces ECP3
jpvarkey@gmail.com:
103213: 06/05/28: PCI related documents
103233: 06/05/29: PCI related doubts !!!!!!
103267: 06/05/30: PCI Header types !!!
103268: 06/05/30: Power Up delay in FPGA !!!!!
103271: 06/05/30: Re: PCI Header types !!!
103325: 06/05/30: Cardbus Power On Reset !!!!!!!!
103327: 06/05/31: Re: Cardbus Power On Reset !!!!!!!!
103334: 06/05/31: Re: Cardbus Power On Reset !!!!!!!!
103510: 06/06/04: Re: Cardbus Power On Reset !!!!!!!!
jr:
108270: 06/09/07: Re: Global constants definition problem
<jrabbani@gmail.com>:
116383: 07/03/07: Avnet Virtex-4 FX12 mini module
116413: 07/03/08: Re: Avnet Virtex-4 FX12 mini module
119319: 07/05/16: Avnet Virtex-4 LX Evaluation Kit USB FX2 Issue
119320: 07/05/16: Avnet Virtex-4 LX25 Evaluation Kit
<jraj.thakkar@gmail.com>:
131893: 08/05/06: Getting started with VHDL and Verilog
131898: 08/05/06: Re: Getting started with VHDL and Verilog
131899: 08/05/06: Re: Getting started with VHDL and Verilog
jralston:
77813: 05/01/17: Passing OPB signals through submodule
77944: 05/01/20: Re: Passing OPB signals through submodule
jrbattin@gmail.com:
110766: 06/10/21: Potential problem w/EDK's Microblaze and the Spartan-3E Starter Kit?
jrc:
39382: 02/02/07: Re: Pseudorandom Bitstream
JRei7227:
20918: 00/02/28: Xilinx Abel Problems
<jrf0@my-dejanews.com>:
15720: 99/04/10: Re: Best FPGA for High Speed DSP Logic?
<jrgodara@gmail.com>:
108621: 06/09/13: downloading bitstream on FPGA
jrh:
66254: 04/02/16: Re: Dual-stack (Forth) processors
67668: 04/03/17: Re: Dual-stack (Forth) processors
67737: 04/03/18: Re: Dual-stack (Forth) processors
120738: 07/06/15: Re: another Forth CPU design
Jrrvvf:
33298: 01/07/22: Re: Silo-3 Demo Program Crashes onDell 4100
jrschenk:
37929: 01/12/25: Re: Where could I get a signal waveform editor?
<jrwalliker@gmail.com>:
109309: 06/09/23: EPIA M10000 single board computer
js:
118343: 07/04/24: Is anyone has experience to share OPB for 2 PowerPC in MPMC2 core
JSalk:
111630: 06/11/07: Re: PCIe latency
112954: 06/12/02: Digitally Controlled Impedance with Lattice ECP2M FPGA's
<jsavard@ecn.ab.ca>:
82067: 05/04/06: Re: ISA vs. patent/trademark
82068: 05/04/06: Re: ISA vs. patent/trademark
82204: 05/04/08: Re: ISA vs. patent/trademark
82255: 05/04/09: Re: ISA vs. patent/trademark
82720: 05/04/16: The DLP from Texas Instruments...
<jschneider@cix.ceeowe.ewekay>:
32843: 01/07/10: Re: FPGA on flex?
<jschneider@cix.CEEOWE.EWEKAY>:
29704: 01/03/05: Suggestions for I/O card
29714: 01/03/06: Re: Suggestions for I/O card
29804: 01/03/11: Configuration devices
jsd:
139614: 09/04/07: Virtex6 software
<jshrini.vasu@gmail.com>:
129915: 08/03/10: its regarding to the Max Frequency in xilinx FPGA
129935: 08/03/11: vhdl code realization
JSingh:
53713: 03/03/20: PrimeTime
53718: 03/03/20: Re: PrimeTime
jsmith:
52789: 03/02/21: spartan III what is it?
<jsmith@red-branch.MIT.EDU>:
98: 94/08/15: Re: FPGA Hobbyist and their software/programmer/hardware
1431: 95/06/22: Re: Low cost ISA board
<jspeter@twinkle.roanoke.infi.net>:
14224: 99/01/20: Re: The development of a free FPGA synthesis tool
JSreeniv:
138755: 09/03/08: Regarding to the "change in duty Cycle"
139770: 09/04/13: Processor returns-Explanation
139829: 09/04/15: sync timer register
140138: 09/04/29: Representation of Read processor convention
144507: 09/12/12: post route simulation
<jsreenivas.naidu@gmail.com>:
133511: 08/07/01: VHDL code for RCOM message
<jstephenson.public@gmail.com>:
109893: 06/10/06: Re: Instantiating Altera M4K block without MegaWizard
jswestra77:
88864: 05/08/30: UDP problems with Xilinx EDK 7.1
88873: 05/08/30: Re: UDP problems with Xilinx EDK 7.1
JT:
78467: 05/02/01: Model Sim: Color Printing
86183: 05/06/22: Serial I/O - Delay Output
jt_eaton:
144529: 09/12/13: Re: Does a 1-bit mux glitch if only one input is known to change at one time?
144537: 09/12/13: Re: Does a 1-bit mux glitch if only one input is known to change at one time?
144713: 09/12/27: Re: JTAG-USB CABLE NOT DETECTED
144765: 09/12/31: Re: RTL View of synthezied code
144890: 10/01/12: Re: Timing errors in Post route simulation in modelsim
144900: 10/01/13: Re: Timing errors in Post route simulation in modelsim
145128: 10/01/28: Re: DPA vs FPGA Security?
145281: 10/02/04: Re: Prog3 - USB Programming Solution for Xilinx
146435: 10/03/17: Digilent Nexys2 board
146496: 10/03/20: Re: wishbone
146804: 10/03/29: Re: upgrading to ISE 11.x
147038: 10/04/10: Re: I'd rather switch than fight!
147206: 10/04/18: Re: Xilinx Virtex-4 Block RAM Initialisation missing
147570: 10/05/04: Re: Unecessary simulation paths
147672: 10/05/13: Re: problem in clock input in virtexpro/spartan3a/spartan3 kit
147931: 10/06/02: Re: Programming Digilent Nexys 2 from Linux
148006: 10/06/11: Re: Is it possible to get consistent implementation results?
148158: 10/06/23: Re: Help with VGA controller in Verilog
148166: 10/06/24: Re: Help with VGA controller in Verilog
148807: 10/08/27: Re: about (low-level) jtag
148989: 10/09/19: Re: Stack Exchange site for programmable logic and FPGA design
148991: 10/09/19: Re: Stack Exchange site for programmable logic and FPGA design
148992: 10/09/19: Re: Stack Exchange site for programmable logic and FPGA design
149049: 10/09/25: Re: Stack Exchange site for programmable logic and FPGA design
149174: 10/10/06: Re: Starting a career with FPGAs
149756: 10/11/22: Re: Multiple Reset Inputs
150168: 10/12/23: Re: Xilinx support makes me want to scream
150357: 11/01/11: Re: FPGA to PHY/MAC chip
150629: 11/01/28: Re: Simple clock question
151945: 11/06/12: Re: Area Optimization
151948: 11/06/13: Re: Area Optimization
151951: 11/06/14: Re: Area Optimization
151971: 11/06/15: Re: Area Optimization
151973: 11/06/15: Re: Area Optimization
152112: 11/07/08: Re: Spartan3DSP TphDCM spec question
152227: 11/07/24: Re: Post-map simulation: timing violation and delays
153000: 11/11/10: Re: ASIC design job vs FPGA design job
153009: 11/11/11: Re: ASIC design job vs FPGA design job
153077: 11/11/27: Re: Compatible Xilinx USB Cables: worth to bother?
153085: 11/11/28: Re: Compatible Xilinx USB Cables: worth to bother?
153133: 11/12/08: Re: Horsepower On Tap
153982: 12/07/08: Re: XC9500XL keeper ?
153985: 12/07/08: Re: XC9500XL keeper ?
154260: 12/09/18: Re: Global Reset using Global Buffer
154268: 12/09/19: Re: Global Reset using Global Buffer
154271: 12/09/19: Re: Global Reset using Global Buffer
155163: 13/05/15: Re: Linting tool setup
155223: 13/06/13: Re: New soft processor core paper publisher?
155248: 13/06/18: Re: Chasing Bugs in the Fog
155502: 13/07/08: Re: VHDL syntheses timestamp
156542: 14/04/18: Re: ERROR:HDLCompilers:27 -
156835: 14/07/07: Re: wishbone bus between two fpgas
156856: 14/07/10: Re: wishbone bus between two fpgas
157053: 14/09/17: Re: Comparision of Advantages/Disadvantges of Verilog or VHDL in Hardware verification
157068: 14/09/21: opencores.org
157162: 14/10/22: Re: [cross-post] verification vs design
157714: 15/02/12: Re: Open Source GPGPU core
157717: 15/02/13: Re: Open Source GPGPU core
157718: 15/02/13: Re: Open Source GPGPU core
157729: 15/02/23: Re: FPGA Project -
157876: 15/05/04: Re: Spartan-3 starter kit
158318: 15/10/20: Re: recovery/removal timing
158353: 15/10/23: Re: recovery/removal timing
158354: 15/10/23: Re: recovery/removal timing
158367: 15/10/24: Re: recovery/removal timing
158393: 15/10/29: Re: recovery/removal timing
158412: 15/10/30: Re: recovery/removal timing
158413: 15/10/30: Re: recovery/removal timing
158443: 15/11/30: Re: Simulation vs Synthesis
158493: 15/12/03: Re: Simulation vs Synthesis
<jtang@magma.ca>:
125331: 07/10/22: Alter RBF Compression
125334: 07/10/22: Re: Alter RBF Compression
125340: 07/10/22: Re: Alter RBF Compression
125344: 07/10/22: Re: Alter RBF Compression
JTB WORLD:
<jtconnor@trog.dra.hmg.gb>:
3364: 96/05/21: Re: *** The Great ESDA Shootout ***
<jthioude@my-deja.com>:
22920: 00/06/02: to make few modifications on a design
<jtindle@gmail.com>:
125795: 07/11/05: FPGA I/O Selection in UCF
125800: 07/11/05: Re: FPGA I/O Selection in UCF
125801: 07/11/05: Re: FPGA I/O Selection in UCF
<JTrendoa2@msn.com>:
jtw:
65273: 04/01/23: Xilinx CoreGen - java - Windows 2000 error
66418: 04/02/19: Re: Unix workstation runs ISE 6.1 slower than a PC?
68355: 04/04/02: Re: Help with Xilinx Ram16X1S example VHDL code
68438: 04/04/05: Re: signal names in modelsim
68964: 04/04/23: Re: VCD file generation
68965: 04/04/23: Re: reading files in vhdl
69422: 04/05/11: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
69423: 04/05/11: Re: is it possible to design usb only with fpga?
70507: 04/06/18: Re: >Math Skills = >Engineer ?
70622: 04/06/22: Re: Unused signals in Modelsim
70748: 04/06/26: Re: Xilinx's interp on EDIF properties
73002: 04/09/10: Re: why systemc?
74384: 04/10/10: Re: Daft RapidIO question
78788: 05/02/08: Re: Max. Operating Frequency - Timing report
79055: 05/02/12: Re: FPGA design problem
79446: 05/02/19: Re: Make program stop
80829: 05/03/12: Re: Over-Sampling
82723: 05/04/16: Re: salary ballpark please guys
84366: 05/05/18: Re: "Mine is bigger than yours..."
84410: 05/05/18: Re: floorplanning
84430: 05/05/19: Re: Which Simulators
85404: 05/06/09: Re: Xilinx -- iMPACT -- Parallel Port [JTAG Cable] Cable connect
85681: 05/06/14: Re: ISE7.1 PAR Warinng: excessive skew because 1 NON-CLK pins...
85917: 05/06/18: Re: Good FPGA introduction book ?
86304: 05/06/24: Re: How do I convert a polynomial into a parallel scrambler formula?
87128: 05/07/16: Re: Compilation error with Synplify attribute
89434: 05/09/15: Re: FIFO design using Virtex-II block ram..
91303: 05/11/03: Re: Reed Solomon generation / verification
98370: 06/03/09: Inferring RAM from array of records
102207: 06/05/12: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
106197: 06/08/09: Re: WHAT SITUATION I NEED A BUFFER
110698: 06/10/20: Re: Fixing Down Parts of Logic in ISE (8.2)
110699: 06/10/20: Re: Meeting Timing Constraint
113565: 06/12/17: Re: Xilins ISE Re-Creating Projects
116169: 07/03/03: Re: How to get the area/time results without IO mapping
116498: 07/03/11: Re: How best do I implement routing boxes in RTL?
119271: 07/05/15: Re: clock wide pulse transfer b/w clock domains
119272: 07/05/15: Re: clock wide pulse transfer b/w clock domains
120504: 07/06/08: Re: Arbiter
121170: 07/06/27: Re: Xilinx FPGA: "after 10ns" constraint
124373: 07/09/19: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
128078: 08/01/15: Re: Resource utilization broken down by hierarchy?
128911: 08/02/09: Re: Strange "Style guide" requirements...
128968: 08/02/12: Re: Reed solomon IP core
129419: 08/02/22: Re: Interview questions
129758: 08/03/05: Re: Blast from the past
130113: 08/03/14: Re: Help on Virtex-II Pro global clocks.
130114: 08/03/14: Re: Design complexity in Logic cells - Virtex-5 FPGA
130417: 08/03/22: Re: timing and timing reports (again)
130858: 08/04/03: Re: coregenerator bram in synplify pro error
130869: 08/04/04: Re: coregenerator bram in synplify pro error
131544: 08/04/25: Re: FPGA comeback
132553: 08/05/30: Re: Can I make ISE 9.2 ngdbuild stop generating new PERIOD specs on PLL outputs?
132747: 08/06/05: Re: HDL tricks for better timing closure in FPGAs
132811: 08/06/06: Re: HDL tricks for better timing closure in FPGAs
132830: 08/06/07: Re: HDL tricks for better timing closure in FPGAs
133787: 08/07/14: Re: xilinx core generator
133788: 08/07/14: Re: How to prevent mapper stripping when synthesizing without IO buffers?
134265: 08/08/02: Re: question about fifo
134995: 08/09/09: Re: What version of ISE is availabe for Virtex5?
136091: 08/10/30: Re: Xilinx RapidIO 5.1
136112: 08/11/01: Re: ISE 9.2.03i problem
137248: 09/01/05: Re: beginner synthesize question - my debounce process won't synthesize.
JTW:
77067: 04/12/21: Memory Controller
88970: 05/09/01: MicroBlaze: PLX PCI 9056 IP
89420: 05/09/14: VHDL: Address Decoder
jtwhite@hal-pc.org:
8460: 97/12/17: FPGA Prototyping on the ISA Bus
Ju, Jian:
107761: 06/09/01: spartan 3e starter kit usb cable
107768: 06/09/01: Re: spartan 3e starter kit usb cable
107770: 06/09/01: Re: spartan 3e starter kit usb cable
110459: 06/10/16: ADC (LTC1407a) on Xilinx Spartan 3E starter kit
110501: 06/10/17: Re: ADC (LTC1407a) on Xilinx Spartan 3E starter kit
111197: 06/10/31: Re: FPGA's for Ethernet?
124898: 07/10/10: Unrouted nets (Xilinx FPGA Editor)
125929: 07/11/09: MANIK LwIP port
Juan:
72304: 04/08/13: FIFO on Spartan 2E question....
72323: 04/08/15: Spartan 2E problem
94066: 06/01/05: Simulating EDIF from DK with Xilinx ISE waveform analyzer
Juan Antonio =?iso-8859-1?Q?G=F3mez?= Pulido:
16843: 99/06/14: Float.p. with Xilinx Express VHDL
21177: 00/03/09: I need parallel processor SIMULATOR
28482: 01/01/15: Looking for prototyping board
juan echeverri:
Juan M. Rivas:
28594: 01/01/17: About programming cables
28647: 01/01/19: About JTAG
28751: 01/01/23: Can Virtex-II be programmed with MultiLINX?
29622: 01/03/01: What about speed-grade?
29733: 01/03/06: Is there any Virtex-II Evaluation Board?
Juan Toledo Cota:
462: 94/11/24: Should I jump to Actel when using Synopsys/Altera?
Juan-Luis Lopez:
11019: 98/07/11: Howto: CRC's and PRBS in Parallel
15354: 99/03/20: Re: Bit Error Rate Test
23297: 00/06/21: RE: Xilinx config over parallel port ?
23360: 00/06/23: RE: Xilinx config over parallel port ?
23539: 00/06/29: RE: PSN Generator
23540: 00/06/29: RE: PSN Generator
23755: 00/07/07: RE: 56 independent PN streams
31802: 01/06/06: RE: Xilinx Configuration Bitstream
38431: 02/01/14: RE: PDH MUX (E2,E3) VHLD cores
Juan-Luis L˘pez Rodrˇguez:
23531: 00/06/28: Re: PSN Generator
23551: 00/06/29: [REPOST] Bit error rate
Juan-Luis López Rodríguez:
25352: 00/09/07: Re: XC3000A Configuration data
JuanC:
113393: 06/12/12: Re: Virtex4 : cleaner signals?
113434: 06/12/13: Re: FPGA : Async FIFO, Programmable full
128845: 08/02/07: Re: Marking Flase paths for Timing Ignore + Virtex 2 Pro support
139594: 09/04/06: Re: Chipscope problem
139612: 09/04/07: Re: Chipscope problem
139721: 09/04/10: Re: How to insert Chipscope blocks directly in Xilinx Project
141100: 09/06/05: Re: Help with Remote debugging ideas.
juanjo:
32144: 01/06/15: Fpga tutorial
Jude Wu:
94261: 06/01/09: Does Xilinx's step1 chips is the ES?
97090: 06/02/16: Re: What is back_annotate?
Judi:
Judy35LUNA:
150153: 10/12/21: Re: Virtex 4 FX12 minimodule
<juendme@yahoo.com>:
92447: 05/11/29: Xilinx Coregen IP Customizer Causes Exception During Customization
92557: 05/12/01: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92558: 05/12/01: Re: Download old Quartus versions (4.0, 4.1)
92572: 05/12/01: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92685: 05/12/04: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92689: 05/12/04: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92690: 05/12/04: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92709: 05/12/05: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92723: 05/12/05: Re: What's wrong with the document?
92725: 05/12/05: Re: What's wrong with the document?
92733: 05/12/05: Re: What's wrong with the document?
92734: 05/12/05: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92979: 05/12/10: Re: Post PAR Simulation and Actual FPGA results differ
92980: 05/12/10: Re: Adding "super-LUTs" to FPGA, good idea ?
Juerg Haefliger:
5384: 97/02/12: bonding of XC4025
5385: 97/02/12: Re: bonding of XC4025
6924: 97/07/09: FIFO in XC4000
Juergen:
59835: 03/08/29: Re: Moving Sum
Juergen Baumgartner:
12870: 98/11/03: Altera MAX+plus II fitting problem
Juergen Buehler:
18486: 99/10/27: Altera UNIX licence
38580: 02/01/18: DDR-Interface
38588: 02/01/18: Re: DDR-Interface
Juergen Fuhrmann:
73167: 04/09/15: Re: Virtex 4 released today
Juergen Jaeger:
54360: 03/04/08: Re: Altera not supplying Leonardo any more
Juergen Kahrs:
12799: 98/10/30: Re: Digital Sine Generator
14263: 99/01/22: Re: The development of a free FPGA synthesis tool
14301: 99/01/24: Re: The development of a free FPGA synthesis tool
Juergen Marquardt:
19847: 00/01/14: 8259 interrupt controller functionality
Juergen Otterbach:
12039: 98/09/25: FIR Filter Design
16192: 99/05/08: Re: PCI slave in FPGA?
16836: 99/06/12: EPC2 and JTAG
16870: 99/06/15: Re: EPC2 and JTAG
26510: 00/10/18: XILINX Download cable with USB
26643: 00/10/23: Re: XILINX Download cable with USB
35652: 01/10/12: Reassemble a BGA560 device
36495: 01/11/09: Re: How to convert unsigned integer into std_logic_vector in VHDL
45925: 02/08/11: Re: EDIF netlist from XST
juergen sauermann:
63538: 03/11/25: Re: Slightly unmatched UART frequencies
juergen Sauermann:
63552: 03/11/25: Re: Slightly unmatched UART frequencies
Juha Kuusama:
7: 94/07/28: Tee minulle Xilinx-suunnittelu (korvausta vastaan, tietty)
Juha Pajunen:
45333: 02/07/19: Making my own software
Juha Turunen:
79027: 05/02/11: Re: Xilinx makes dreams true :)
79092: 05/02/14: Re: Xilinx Spartan 3 kit - displaying unique numbers
Jui Tan:
39383: 02/02/07: Xilinx ISE 3.3 upgrade to 4.1
juice28:
57618: 03/07/03: xilinx and web pack questions newbe
57657: 03/07/03: Re: xilinx and web pack questions newbe
57699: 03/07/04: okay what am I missing??? Please
57935: 03/07/10: Re: okay what am I missing??? Please
57939: 03/07/10: Re: okay what am I missing??? Please
60338: 03/09/10: Newbee question? Schematic entry
60350: 03/09/11: Re: Newbee question? Schematic entry
Juinn-Dar Huang:
636: 95/01/25: About XC5000 Series
Jukka Marin:
135872: 08/10/19: Cyclone III, DP RAM, and Verilog
135883: 08/10/20: Re: Cyclone III, DP RAM, and Verilog
140285: 09/05/07: OpenCores CAN/Ethernet cores
140421: 09/05/13: Re: OpenCores CAN/Ethernet cores
154988: 13/03/21: Using Quartus II without GUI
Jukka Pöppönen:
22978: 00/06/07: Xilinx Spartan; CLB's run out
Jul:
91523: 05/11/08: Re: ML402 DDR SDRAM
Jules:
115807: 07/02/21: Cyclone II "altsyncram" timing constraints?
115808: 07/02/21: Re: RTOS?
115809: 07/02/21: Re: Theora vs. M-JPEG2000
115811: 07/02/21: Re: wintel CPU reads across the PCI Express bus
Jules P:
76892: 04/12/15: Re: Xilinx speed grading
julia:
31324: 01/05/18: Tutorial
31405: 01/05/22: FPGA
Julian:
74715: 04/10/17: how to transfer Xilinx .vhd back to .vhw/.tbw?
74721: 04/10/17: How to transfer Xilinx .vhd back to .vhw/.tbw?
Julian Cox:
3874: 96/08/13: Re: ACTEL Prices
3875: 96/08/13: Re: ACTEL Security Fuse
4281: 96/10/09: Re: Atmel Serial Configuration EEPROM - AT17C128
4282: 96/10/09: Re: 16x16 multiplier needer (Altera or VHDL)
4426: 96/10/28: Re: Altera Configuration EPROM Equivalents
4569: 96/11/15: Re: Fast FPGA
4773: 96/12/13: Re: Configuration EEPROMS for Altera Flex10K & Flex8K
5066: 97/01/20: Re: ASICs Vs. FPGA in Safety Critical Apps.
5067: 97/01/20: Re: advice request
5112: 97/01/24: Re: FPGA Lab.
5196: 97/01/30: Re: Altera support better than Xilinx
5476: 97/02/19: Re: Xilinx or Altera?
5546: 97/02/24: Re: Xilinx or Altera?
5572: 97/02/25: Re: Xilinx or Altera?
6035: 97/04/07: Re: Pentium Pro Worth it for Altera Max Plus?
6324: 97/05/15: Re: Anyone using Actel software?
6369: 97/05/19: Re: Cheap way to develop for FPGAs?
6952: 97/07/15: Re: Altera FLEX10K initialization
7151: 97/08/07: Re: digitizer design, high speed
7218: 97/08/15: Re: Price of Serial EEPROM is Outrageous
7533: 97/09/19: Re: Atmel 17256 serial config EEPROMs
27002: 00/11/07: Re: ViewLogic ViewDraw questions
39501: 02/02/12: Re: Making Altera development quicker
Julian Gardner:
157327: 14/11/22: What would you say is the best board to buy
157728: 15/02/22: FPGA Project -
157731: 15/02/24: Re: FPGA Project
158180: 15/09/11: Re: Why is this group so quiet?
Julian Hu:
63990: 03/12/10: Re: Video Scan Conversion Rate - Camera Input to DVI Display Output
Julian Kain:
89690: 05/09/22: Xilinx PAR -- WARNING:Route - CLK Net may have excessive skew...
93814: 05/12/31: Re: Timing problem in ModelSim, Post-Route Simulation.
93861: 06/01/02: Re: Start up condition of flip flops in FPGA?
97300: 06/02/20: Re: Is FPGA code called firmware?
114550: 07/01/18: Re: ISE 9.1i and partial reconfiguration
Julian Kemmerer:
160642: 18/08/02: PipelineC
161440: 19/09/07: PipelineC (again), dct example, looking for help/interest
161441: 19/09/07: PipelineC (again), dct example, looking for help/interest
161673: 20/03/21: PipelineC - C-like almost hardware description language - AWS F1 Example
161675: 20/03/23: Re: PipelineC - C-like almost hardware description language - AWS F1 Example
Julian V. Noble:
66260: 04/02/16: Re: Dual-stack (Forth) processors
Julien:
76698: 04/12/09: 100MHz Microblaze and 50 MHz OPB
Julien Chevalier:
70178: 04/06/08: SOPC BUILDER - SOFTWARE GENERATION
70249: 04/06/10: can't trap custom ITon NIOS
Julien Eyries:
60793: 03/09/22: LUT and Registers in Xilinx Virtex 2
60928: 03/09/25: Re: LUT and Registers in Xilinx Virtex 2
Julien Lochen:
100210: 06/04/05: I2C bus controller Implementation
111739: 06/11/09: drive LVDS clocks with a spartan3
111758: 06/11/09: tri0 GSR = glbl.GSR;
129196: 08/02/18: Define the primary clock with XST in VHDL
Julien Sobrier:
61620: 03/10/07: ASIC/FPGA programming
julio:
147078: 10/04/13: Nios Memory Protection Unit
Julio Cezar David de Melo:
5227: 97/01/31: Re: Altera PCI experience anyone?
Julio Di Egidio:
160375: 18/01/01: Qs on HDL library code and pipelining
160377: 18/01/03: Re: Qs on HDL library code and pipelining
160383: 18/01/05: Re: Qs on HDL library code and pipelining
160556: 18/04/14: Re: FPGA selection recommendation
160558: 18/04/14: Re: FPGA selection recommendation
160826: 18/12/02: Re: Periodically delayed clock
160827: 18/12/02: Re: Periodically delayed clock
161349: 19/04/18: Re: Field update
161677: 20/03/24: Re: Use example of Intel University program in Intel Quartus -
Julio Espada:
131543: 08/04/25: ATF750 for Proteus
131672: 08/04/29: Re: ATF750 for Proteus
<Julio>:
7201: 97/08/14: Re: FPGA power consumption
Julius:
152223: 11/07/22: Re: Issues with Soft-Cores
153050: 11/11/23: Re: RTOS with support for TCP/IP sockets on Spartan 3E
julius:
116796: 07/03/18: Re: how to transform Arun's LDPC code to max-product (Min-sum)?
julius kusuma:
15790: 99/04/14: Re: SUBSCRIBE
Juliusz:
20752: 00/02/20: Re: Divider
Julián Calderón Almendros:
31909: 01/06/08: On the prices of the FPGA and how to buy it
32172: 01/06/18: Re: On the prices of the FPGA and how to buy it
<jum>:
34666: 01/09/02: Re: FPGA : USB in an FPGA, has anyone done it before?
Jun:
30644: 01/04/20: what does it mean in fe.log?
57456: 03/07/01: fpga video evaluation board
57499: 03/07/01: Re: fpga video evaluation board
57667: 03/07/03: Re: memory
57952: 03/07/10: Re: memory
58074: 03/07/14: Re: memory
Jun Jiang:
41126: 02/03/21: Re: Fixed Point Library
Jun Xu:
49126: 02/11/01: Q on extracting the state bits of registers from readback bitstream
Jun Yang:
20703: 00/02/18: Does testability measurement play an inportant role in DFT?
junaid:
86725: 05/07/05: VPR fundaes
87158: 05/07/18: Re: VPR fundaes
87373: 05/07/22: verilog to blif(lut)
87771: 05/08/01: Re: verilog to blif(lut)
junaidabidi:
105342: 06/07/20: Using DCM-Virtex-II Pro
Jung Ko:
74550: 04/10/13: Re: EP1C12 or XC3S400?
<junk.account.of.mine@gmail.com>:
99177: 06/03/21: ATTENTION THE PEOPLE OF INDIA ( was Urgent Help Needed)
<junk.dontsend@gmail.com>:
103367: 06/05/31: How many of the old reference sites are still around?
<junkmail@fastertechnology.com>:
78533: 05/02/02: Re: 100Mbps ethernet core
78654: 05/02/04: Re: memory size of C code
80393: 05/03/04: Re: 100Mbps ethernet core
80401: 05/03/04: Re: 100Mbps ethernet core
81814: 05/04/01: Re: Xilkernel: configure to use 2 PPCs
82196: 05/04/08: Heatsinks with fan for Xilinx FF1152 on PCI card
82504: 05/04/13: Re: virtex4 reconfiguration time
83010: 05/04/21: Re: Heatsinks with fan for Xilinx FF1152 on PCI card
JuNNi:
145747: 10/02/22: FPGA platform??
<junnuthula@yahoo.com>:
89327: 05/09/12: Please Help:Modelsim-Altera License "Verilog Computer Based training course"
<junsc@sysic.hei.co.kr>:
12530: 98/10/15: Fixed-point arithmetic coding
Jura:
86376: 05/06/27: Rising to falling edge constraints on Actel ProAsic
Jure Oblak:
32777: 01/07/08: Simulation problems with BlockRAM's INIT values !
Jurgen Defurne:
143415: 09/10/10: Development boards for CPU development ?
143431: 09/10/11: Re: Development boards for CPU development ?
Jurgen Maus:
6182: 97/04/23: Download Xilinx Fpga (XC4***)
Juri Kanevski:
29987: 01/03/20: Re: TOA measurement
29988: 01/03/20: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
Jurjen Boss:
27448: 00/11/22: Power consumption FPGA...
Jussi =?ISO-8859-1?Q?L=E4hteenm=E4ki?=:
49421: 02/11/12: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
49433: 02/11/12: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
52243: 03/02/05: Re: Clock Enables
52646: 03/02/18: Re: SoC pheripheral Design Resouraces
55005: 03/04/24: Re: hardware implementation of viterbi decoder
55119: 03/04/28: Re: hardware implementation of viterbi decoder
55700: 03/05/16: Re: Moore Vs Mealy machine ..
JussiJ:
118948: 07/05/07: Re: VHDL editing with UltraEdit
<jussij@zeusedit.com>:
91567: 05/11/08: Re: Verilog Editor.
91803: 05/11/13: Re: Verilog Editor.
91829: 05/11/14: Re: Verilog Editor.
91922: 05/11/16: Re: Verilog Editor.
92039: 05/11/20: Re: Verilog Editor.
92068: 05/11/21: Re: Verilog Editor.
Just an Illusion:
70891: 04/07/01: Re: *RANT* Ridiculous EDA software "user license agreements"?
71534: 04/07/21: Re: FSM in illegal state (conclusion)
Just Me:
54257: 03/04/06: Should I bother with Xilinx Foundation 1.5 vs 2.1?
54327: 03/04/08: Re: price of fpga chips
Just Some Guy:
54335: 03/04/08: OK, where does an FPGA newbie start?
54347: 03/04/08: Re: OK, where does an FPGA newbie start?
54387: 03/04/09: Re: OK, where does an FPGA newbie start?
54447: 03/04/10: Re: OK, where does an FPGA newbie start?
54514: 03/04/12: Re: Webpack 5.2i download
Justen:
11597: 98/08/26: How to design a PLL
justen:
12271: 98/10/07: Need 100MHz Counter with 3 Comparators
<justforpretend@gmail.com>:
138704: 09/03/05: Want to buy: FPGA T-Shirt $$
Justin:
70399: 04/06/15: Using Altera libraries for Nios Dev Board
105469: 06/07/24: Re: Xilinx Virtex-4 APU Controller Questions
Justin Slavin:
Justin A. Kolodziej:
49399: 02/11/11: The "Do"s and "Don't"s of Synthesizing VHDL?
Justin Cowling:
49040: 02/10/30: Re: FPGA board recommendation
52096: 03/01/31: Re: Simulink to vhdl tools
Justin Cui:
35539: 01/10/10: Who knows the news server of synplicity?
Justin Erickson:
101056: 06/04/24: Smallest uClinux configuration
Justin Morgan:
5925: 97/03/26: Software602, Inc.
Justin Oo:
34345: 01/08/21: JTAG issue again ...
34376: 01/08/22: Re: JTAG issue again ...
JustJohn:
87339: 05/07/21: Re: Ones Count 64 bit on Xilinx in VHDL
92004: 05/11/19: Oh no! Resets Again? Yes, but it could be important.
92010: 05/11/19: Re: Oh no! Resets Again? Yes, but it could be important.
92014: 05/11/19: Re: Oh no! Resets Again? Yes, but it could be important.
92015: 05/11/19: Re: Oh no! Resets Again? Yes, but it could be important.
92023: 05/11/19: Re: Oh no! Resets Again? Yes, but it could be important.
92033: 05/11/20: Re: CLK input DOES NOT use clk pin ( Altera Stratix II)
92067: 05/11/21: Re: Oh no! Resets Again? Yes, but it could be important.
92070: 05/11/21: Re: Oh no! Resets Again? Yes, but it could be important.
92113: 05/11/22: Re: Xst optimizes almost everything away
92126: 05/11/22: Re: Disabling Xilinx clock enable usage...
92201: 05/11/23: Re: Xst optimizes almost everything away
92207: 05/11/23: Re: XST vs Synplify
92208: 05/11/23: Re: Xst optimizes almost everything away
93110: 05/12/13: Re: Mean value filter
93136: 05/12/14: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93162: 05/12/14: Re: Mean value filter
93163: 05/12/14: Re: consensus theorem and power
93207: 05/12/15: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93209: 05/12/15: Re: Mean value filter
93297: 05/12/19: Re: Mean value filter
93305: 05/12/19: Re: Mean value filter
93313: 05/12/19: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93369: 05/12/20: Re: Patents and (possible) Plagiarism, an open apology
96223: 06/01/31: Re: Constraining a 50 MSPS DAC Interface
97210: 06/02/18: Re: Xilinx Tight packing : Map error, the tools don't get it ...
99013: 06/03/18: Re: question regarding LUT and MAP
99420: 06/03/23: TNM propagation: I seem to be having trouble
99483: 06/03/24: Re: XST takes unusually long
99514: 06/03/25: BlockROM inference in XST - This is just plain silly
99555: 06/03/26: Re: BlockROM inference in XST - I'm just plain silly
99557: 06/03/26: Re: BlockROM inference in XST - A matter of Quantity
99558: 06/03/26: Re: BlockROM inference in XST - This Finally Works
99562: 06/03/26: Re: BlockROM inference in XST - This Finally Works - Arrgh, no it doesn't...
99566: 06/03/26: Re: Clock multiplication without using the Xilinx DCM's
99734: 06/03/28: Keystroke saving w/ IEEE.Numeric_Std
99805: 06/03/29: Re: Keystroke saving w/ IEEE.Numeric_Std
99995: 06/03/31: Re: FIFO Vs Shift Register
100599: 06/04/12: Re: timing constraints ?
100714: 06/04/16: Re: XST not inferring distributed RAM
100836: 06/04/19: Re: Counting bits
100873: 06/04/19: Re: clock mux in spartan2e fpga
100874: 06/04/19: Front Side Bus, was Re: Counting bits
100903: 06/04/20: Re: clock mux in spartan2e fpga
103877: 06/06/13: Re: FSM state minimization with ISE?
103879: 06/06/13: Re: FSM state minimization with ISE?
103958: 06/06/15: Re: FSM state minimization with ISE?
104180: 06/06/20: Re: FSM State Minimization on FPGAs
104185: 06/06/20: Re: FSM State Minimization on FPGAs
104232: 06/06/21: Re: FSM State Minimization on FPGAs
104713: 06/07/04: Re: single pad to pad timing in ISE
106457: 06/08/13: Re: Embedded clocks
106475: 06/08/13: Re: Embedded clocks
107289: 06/08/26: Re: fastest FPGA
108750: 06/09/15: Re: Parallel P&R
109805: 06/10/05: Re: unexpected Xilinx TNM constraint behaviour
110157: 06/10/11: Re: TIG Being Ignored?
110497: 06/10/16: Re: TIG Being Ignored?
110693: 06/10/19: Re: 64 bit division compensate NCO
111354: 06/11/01: Dual-port BlockRAM "write first" puzzler...
111367: 06/11/01: Re: Dual-port BlockRAM "write first" puzzler...
112169: 06/11/17: Re: combinatorical divide by 2 in FPGA
112219: 06/11/17: Re: combinatorical divide by 2 in FPGA
112275: 06/11/19: Re: combinatorical divide by 2 in FPGA
112857: 06/11/29: Re: Old XCell journals gone?
114602: 07/01/20: Re: Phasse Detector
114756: 07/01/23: Re: "Divide" a video line in two stripe
114762: 07/01/23: Re: "Divide" a video line in two stripe
114907: 07/01/25: Re: video buffering scheme, nonsequential access (no spatial locality)
114924: 07/01/26: Re: Forcing a LUT to not be optimized
114925: 07/01/26: Re: Datapath design problem?
116794: 07/03/18: Re: XILINX ISE: How to define a Internal clock and use it in OFFSET command?
125019: 07/10/15: Re: FPGA quiz: what can be wrong
148386: 10/07/16: Re: Dumb VHDL Question -- Type Conversion
148396: 10/07/17: Re: Dumb VHDL Question -- Type Conversion
151084: 11/03/04: Re: Count bits in VHDL, with loop and unrolled loop produces
151107: 11/03/06: Re: Count bits in VHDL, with loop and unrolled loop produces
151121: 11/03/08: Re: Count bits in VHDL, with loop and unrolled loop produces
jv:
18382: 99/10/21: Xilinx Orientation Question
jvdh:
88535: 05/08/22: Spartan slave-parallel development board
91631: 05/11/10: Coolrunner output pins stuck at 0V
91660: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91737: 05/11/11: Re: Coolrunner output pins stuck at 0V
91866: 05/11/15: Re: Coolrunner output pins stuck at 0V
91974: 05/11/18: Re: Coolrunner output pins stuck at 0V
102646: 06/05/18: Spartan 3 Readback
102699: 06/05/19: Re: Spartan 3 Readback
102704: 06/05/19: Re: Spartan 3 Readback
102740: 06/05/19: Re: Spartan 3 Readback
105759: 06/07/31: 100m JTAG cable
105766: 06/07/31: Re: 100m JTAG cable
105802: 06/08/01: Re: 100m JTAG cable
105840: 06/08/01: Re: 100m JTAG cable
105842: 06/08/01: Re: 100m JTAG cable
JW:
85270: 05/06/07: Placing variables at a specific location (address) using microblaze GCC
85308: 05/06/07: Re: Placing variables at a specific location (address) using microblaze GCC
85309: 05/06/07: Anonymous structs in Microblaze C compiler
jwbrooks:
6317: 97/05/14: Re: FPGA gate counting: No truth in advertising
jweissberg:
92891: 05/12/08: Experiences with Actel ProAsic3E and toolchain?
jwes on BIX:
751: 95/02/22: Re: Newsgroup for Micro Controllers
JWKIM:
22104: 00/04/24: Re: CLKDLL
22288: 00/05/04: Re: [Q] Virtex FPGA : compile time error message
jwwebb:
152528: 11/09/05: Re: Virtex-6 XC6VHX380T Master SPI Configuration Problems....
JX:
22642: 00/05/16: Where can I find resource for USB?
Jye Mei Ng:
6500: 97/05/29: Altera Versus Xilinx
jyhur:
77663: 05/01/13: Re: MHS modify and then ...?
Jyke:
33352: 01/07/24: Re: Register Chain
49528: 02/11/14: Re: how to name the IOBUF attribute in UCF
Jym:
48382: 02/10/16: unconnected nets in schematic editor of ISE 5.1
jyoti:
137452: 09/01/17: problems in PR;planahead
Jyoti Wagholikar:
49671: 02/11/18: Newbie Question: Instantiating Muliplier18X18
jypa09:
149599: 10/11/10: Device 0 Unit 0:waiting for core to be armed, slow or stopped clock.
<jzakiya@mail.com>:
29093: 01/02/06: Re: Rijndael
<jzakiya@my-deja.com>:
29088: 01/02/05: Re: Rijndael
Jérémie WEBER:
47343: 02/09/24: FPGA fail when Electrostatic discharge Occurs
54530: 03/04/13: tristates using synplify
Jörg Rockstroh:
90367: 05/10/11: ModelSim XE: Can't import vital 2000 library
90404: 05/10/12: Re: ModelSim XE: Can't import vital 2000 library
Jörgen Bĺth:
5678: 97/03/06: Re: JTAG config on ALTERA FLEX10K10: How?
Jörgen Gade:
1694: 95/08/17: Re: Email Address of Xilinx
1933: 95/09/21: Re: Editors that understand VHDL under UNIX
Jürgen Marquardt:
20934: 00/02/29: Philips LA PM3585 disassembler software wanted
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