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On Jun 11, 7:14=A0am, rana <rande...@gmail.com> wrote: > hi all, > > i have a ddr2 controller that works on 4 burst mode. ddr2 dq width is > 16. i must provide 2, 32 bit data to the controller before writing it > to memory. As well as when reading from a memory location it gives out > 2, 32 bit data out. > my processor is a master AHB, has a 32 bit address and 32 bit data > bus. > How can i connect these 2 together? > problem is ahb sends out 32 bit data but i have to write to 64 bit > data to memory. > also the burst is 4, so it will write to 2, 32 bit memory locations, > so there would be a 32 bit memory location that would be written with > redundant data(if i write 64 bit data to memory). > > thank you, > randeel. Well now ... if your memory controller doesn't support writes that are less than 64 bits, you're screwed trying to connect to a 32 bit AHB system. I would be surprised if that is the case .. a controller should support byte writes for that matter. Well anyway ... if you have this simple controller that must work in chunks of 64 bits then you will have to store the first 32 AHB write and when the second 32 AHB write occurs then you can send the 64 bits to the memory controller. Similarily for the read, you will have to store the 64 bit read data and provide it as 2 32 bit chunks when the AHB requests it. If the next AHB read is not to the subsequent address, throw the unused 32 bits away and start another read transaction. MikeArticle: 148001
On Jun 11, 8:13=A0pm, mike <gosenator...@hotmail.com> wrote: > On Jun 11, 7:14=A0am, rana <rande...@gmail.com> wrote: > > > > > > > hi all, > > > i have a ddr2 controller that works on 4 burst mode. ddr2 dq width is > > 16. i must provide 2, 32 bit data to the controller before writing it > > to memory. As well as when reading from a memory location it gives out > > 2, 32 bit data out. > > my processor is a master AHB, has a 32 bit address and 32 bit data > > bus. > > How can i connect these 2 together? > > problem is ahb sends out 32 bit data but i have to write to 64 bit > > data to memory. > > also the burst is 4, so it will write to 2, 32 bit memory locations, > > so there would be a 32 bit memory location that would be written with > > redundant data(if i write 64 bit data to memory). > > > thank you, > > randeel. > > Well now ... if your memory controller doesn't support writes that are > less than 64 bits, you're screwed trying to connect to a 32 bit AHB > system. > I would be surprised if that is the case .. a controller should > support byte writes for that matter. > > Well anyway ... if you have this simple controller that must work in > chunks of 64 bits then you will have to store the first 32 AHB write > and when the second 32 AHB write > occurs then you can send the 64 bits to the memory controller. > Similarily for the read, you will have to store the 64 bit read data > and provide it as 2 32 bit chunks when the > AHB requests it. If the next AHB read is not to the subsequent > address, throw the unused 32 bits away and start another read > transaction. > > Mike hi mike, the problem is when u write 2 writes consecutively, to totally unrelated memory addresses the above write procedure will not work. thank you, randeel.Article: 148002
On Jun 11, 8:10=A0pm, "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > You dont have to write all of the data into memory, you can use the data > masks. > > Jon =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com what u mean is controlling the DM signal in ddr2 memory writes. thank you, randeel.Article: 148003
Thanks for the replies. As for the design, it is a superscalar processor not designed with FPGA in mind. Currently, I'm just trying to get it running on a Virtex-5 and I don't care how slow it is. So yes, I am slowing the clock down as well. Actually, how I was changing the constraints was by changing the frequency of the clock from the DCM and letting Xilinx detect the constraint for the clock. The clock into the FPGA and constraints for it have remained the same. I'll work on speeding it up later. Without changing the design except the clock period and having nearly all optimizations on and timing performance design strategy along with normal extra effort on map and par, I still couldn't meet a cycle time of 40 ns. Then I only changed the extra effort on map and par from normal to the next highest - continue on impossible - and it met a 30 ns cycle time. Xilinx even mentions in the report that "continue on impossible" should not be needed in normal cases. I would really like to not have to use "continue on impossible" as it takes nearly 3 hours just for par. I'm using Xilinx 10.1 so no multi-threading. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148004
You are doing something seriously wrong if it takes 3 hours to p&r. You need to specify the clock that you want to run the design and then after synthesis examine the report to see if it has been met. If it hasnt then you need to investigate the paths that are failing and then modify the design to make it pass. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148005
I've specified the constraint on the clock to the FPGA. That clock goes to a DCM and Xilinx generates a constraint for the output clock of the DCM. Synthesis runs fine, I get around a 3 ns cycle time. I don't get an error about failing timing constraints until after place and route has completed. I guess I just need to experiment to find out what works. >You are doing something seriously wrong if it takes 3 hours to p&r. You >need to specify the clock that you want to run the design and then after >synthesis examine the report to see if it has been met. If it hasnt then >you need to investigate the paths that are failing and then modify the >design to make it pass. > >Jon > >--------------------------------------- >Posted through http://www.FPGARelated.com > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148006
>Hi, > >I'm working with Xilinx ISE 10.1 and I am having troubles with timing >constraints. > > >--------------------------------------- > What is your % of utilization? Is this chip packed to the max? Have you tried sacrificing a chicken on top of your workstation? John --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148007
On 6/11/2010 4:52 PM, BrandonD wrote: > Thanks for the replies. > > As for the design, it is a superscalar processor not designed with FPGA in > mind. Hi Brandon, Wow, you are designing a "superscalar processor" and yet you can't meet FPGA timing? Good luck with that! Syms.Article: 148008
Just because synthesis passes your timing constraint it doesnt mean it will pass after p&r. For instance there could be two pieces of logic at opposite sides of the fpga connected by a long delay. So you need to look at the static timing report to see what paths are failing. Just randomly changing things until it works isnt the way to go. Jon >I've specified the constraint on the clock to the FPGA. That clock goes to >a DCM and Xilinx generates a constraint for the output clock of the DCM. > >Synthesis runs fine, I get around a 3 ns cycle time. > >I don't get an error about failing timing constraints until after place and >route has completed. I guess I just need to experiment to find out what >works. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148009
In prep for the release of more Altera development board additions to our range we have a new programming cable Prog4. We will be selling this 2 ways. The first is as a programming cable and that will be in a case similar to our Xilinx cable Prog3.. The second use is as a simple FT245 USB based development board where in addition to the programming interfaces there are 36 I/O arranged in our normal DIL Header configuration. That header can take things like our 16 channel A/D modules or stripboard add ons. The board is based on a XC3S50AN FPGA and will sell for GBP 50 approximately USD 75. Picture and more details will appear on website over the next 24 hours. John Adair Enterpoint Ltd.Article: 148010
Help !!! The megawizard in Quartus 2 does not seem to support generating small roms & rams using the LUT tables, only using the M9K memory blocks. Any way to generate small roms & rams using the logic cells ? I'm looking for something similar to Xilinx distributed memory generator. TIA. JimArticle: 148011
newzhnd <nobody@home.com> wrote: > Help !!! The megawizard in Quartus 2 does not seem to support generating > small roms & rams using the LUT > tables, only using the M9K memory blocks. Any way to generate small roms & > rams using the logic cells ? > I'm looking for something similar to Xilinx distributed memory generator. > TIA. Can't you just generate them in ordinary verilog or VHDL? For Xilinx, the RAM arrays are synchronous, so it has to generate LUT RAM (or ROM) if it is used asynchronously. -- glenArticle: 148012
I'd rather not write verilog & specify each rom or ram word individually. Cyclone 2 supports logic cell usage for rom or ram. I'm surprised cyclone 3 doesn't. Xilinx allows either LUT or block memory for ram or rom. Nothing to do with sync or async. "glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:hv3rmb$ul3$1@speranza.aioe.org... > newzhnd <nobody@home.com> wrote: > >> Help !!! The megawizard in Quartus 2 does not seem to support >> generating >> small roms & rams using the LUT >> tables, only using the M9K memory blocks. Any way to generate small roms >> & >> rams using the logic cells ? >> I'm looking for something similar to Xilinx distributed memory generator. >> TIA. > > Can't you just generate them in ordinary verilog or VHDL? > > For Xilinx, the RAM arrays are synchronous, so it has to generate > LUT RAM (or ROM) if it is used asynchronously. > > -- glenArticle: 148013
hi I am implementing BMD design as explained in xapp1052(v2.5). Have implemented the design on Avnet V5LXT/SXT PCIe Development Board using the PCIe. Have generated the Endpoint Block plus for PCIe 1.9 using ISE 10.1. I have been successful in running the BMD design. I want to switch off the power management at the system start up. in my understanding there can be two ways to do it. firstly through the bios setting and other at the time of core generation. i am working on the bios part but i want to know about the power management option present at the time of core generation. What would be the result if i use that option. will that option help me in switching off the power management. Secondly is there any option in the RTL of XAPP1052 which could be hard coded to stop the power management negotiation at the system startup? Can i set any options at the time time of bit stream generation that would help me in switching off the power management. Regards UsamaArticle: 148014
"newzhnd" <nobody@home.com> wrote in message news:XaeRn.26714$%u7.16071@newsfe14.iad... > Help !!! The megawizard in Quartus 2 does not seem to support generating small roms & rams using > the LUT > tables, only using the M9K memory blocks. Any way to generate small roms & rams using the logic > cells ? > I'm looking for something similar to Xilinx distributed memory generator. Altera devices can't implement LUT based distributed memory, this is one of Xilinx's heavily patented uniqe selling points! You just have to use device logic or M9Ks. Nial.Article: 148015
On Jun 14, 8:06=A0am, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > "newzhnd" <nob...@home.com> wrote in messagenews:XaeRn.26714$%u7.16071@ne= wsfe14.iad... > > Help !!! =A0 The megawizard in Quartus 2 does not seem to support gener= ating small roms & rams using > > the LUT > > tables, only using the M9K memory blocks. =A0Any way to generate small = roms & rams using the logic > > cells ? > > I'm looking for something similar to Xilinx distributed memory generato= r. > > Altera devices can't implement LUT based distributed memory, this is one = of > Xilinx's heavily patented uniqe selling points! > > You just have to use device logic or M9Ks. > > Nial. If it's so heavily patented, why do Lattice devices support distributed RAM? There must be some work-arounds to the existing patents.Article: 148016
Hi, In a design I'm working on I have a machine that produces 128 bit of data. This data is destined to a 16 bit DAC running 8x faster. Knowing that I can produce the 128bit up to a 120MHz rate I wanted to generate the 8x 16bit stream as fast as I can (and I'm using a 500MHz DAC) The 128 to 16bit It's all done in a component I called front8x that selects counts and selects the 16bit slice out of the 128bit data as below (being the clock output the one used to run the rest of the circuit). In practice I found it to run up to 300MHz. Should I expect that this would be the right up limit I could do it ? Is there any clever design of this frontend to allow higher speed ? ( note: the phase of the clock out to the DAC is set on another PLL so I'm surely well by setting the DAC to sample at the middle of the eye pattern. So no issues here ) I would like very much to read some comments, please. Thanks. Luis C. (device CycloneIII-FBGA fastest grade, all outs using LVDS) -- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; ENTITY front8x IS PORT ( clkin: IN STD_LOGIC; -- master frontend clock sync: IN STD_LOGIC; -- Sync frontend clkout: OUT STD_LOGIC; -- 1/8 main clock out datain: IN STD_LOGIC_VECTOR (127 downto 0);-- system data bus dacout: OUT STD_LOGIC_VECTOR (15 downto 0)-- DAC data bus ); END front8x; ARCHITECTURE regmux8 OF front8x IS SIGNAL dacreg: STD_LOGIC_VECTOR ( 15 DOWNTO 0 ); SIGNAL datareg:STD_LOGIC_VECTOR ( 127 DOWNTO 0 ); SIGNAL cntr: INTEGER RANGE 0 TO 7; BEGIN dacout <= dacreg; -------------------------- -- Main 8:1 cycle -- clockout rise at count=4 -- bigdata is fetch at cont = last = 7 main: PROCESS(clkin,sync) BEGIN IF (clkin='1' AND clkin'EVENT) THEN IF (sync='0') THEN cntr <= 0; ELSE cntr <= cntr + 1; END IF; case cntr is when 0 => dacreg <= datareg(127 downto 112); when 1 => dacreg <= datareg(111 downto 96); when 2 => dacreg <= datareg(95 downto 80); when 3 => dacreg <= datareg(79 downto 64); when 4 => dacreg <= datareg(63 downto 48); when 5 => dacreg <= datareg(47 downto 32); when 6 => dacreg <= datareg(31 downto 16); when others => dacreg <= datareg(15 downto 0); datareg <= datain; END CASE; IF (cntr > 4) THEN clkout <= '1'; ELSE clkout <= '0'; END IF; END IF; END PROCESS main; END regmux8;Article: 148017
> > Altera devices can't implement LUT based distributed memory, this is one of > > Xilinx's heavily patented uniqe selling points! > If it's so heavily patented, why do Lattice devices support > distributed RAM? There must be some work-arounds to the > existing patents. Licensing? It's a useful feature so I presumed (and have read here I think) the thing stopping the other vendors implementing it is patents. Nial.Article: 148018
On Mon, 14 Jun 2010 13:06:44 +0100, Nial Stewart wrote: > "newzhnd" <nobody@home.com> wrote in message > news:XaeRn.26714$%u7.16071@newsfe14.iad... >> Help !!! The megawizard in Quartus 2 does not seem to support >> generating small roms & rams using the LUT >> tables, only using the M9K memory blocks. Any way to generate small >> roms & rams using the logic cells ? >> I'm looking for something similar to Xilinx distributed memory >> generator. > > > Altera devices can't implement LUT based distributed memory, this is one > of Xilinx's heavily patented uniqe selling points! > > You just have to use device logic or M9Ks. > > > Nial. They can implement ROMs with LUTs, all logic in a LUT based FPGA is a ROM. The LUT RAM patent was filed in 1989 and granted in 1994 so it should expire next year, the patent term was 17 years from the date of grant in the early 90s.Article: 148019
> Is there any clever design of this frontend to allow higher speed ? As you're stepping through the 128 bits to extract the 16 bit output I would have implemented it as a big shift register and take off the top/bottom bits. Then all the tools have to worry about is a single register to register delay rather than big mux required to 'select' the correct 16 bits. Nial.Article: 148020
Can't wait to use this thing! http://ppclone.blogspot.com/2010/06/mystery-devboard.htmlArticle: 148021
On Jun 14, 3:25=A0pm, Gabor <ga...@alacron.com> wrote: > On Jun 14, 8:06=A0am, "Nial Stewart" > > <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > "newzhnd" <nob...@home.com> wrote in messagenews:XaeRn.26714$%u7.16071@= newsfe14.iad... > > > Help !!! =A0 The megawizard in Quartus 2 does not seem to support gen= erating small roms & rams using > > > the LUT > > > tables, only using the M9K memory blocks. =A0Any way to generate smal= l roms & rams using the logic > > > cells ? > > > I'm looking for something similar to Xilinx distributed memory genera= tor. > > > Altera devices can't implement LUT based distributed memory, this is on= e of > > Xilinx's heavily patented uniqe selling points! > > > You just have to use device logic or M9Ks. > > > Nial. > > If it's so heavily patented, why do Lattice devices support > distributed RAM? =A0There must be some work-arounds to the > existing patents. very simple: Lattice has the license! because AT&T used to to manufacture Xilinx compatible FPGA's and Lattice is the current license holder of those old technologies hence Lattice inherited the rights to use LUT as distributed RAM. Other FPGA vendors like Altera can not do it without legal issues AnttiArticle: 148022
"newzhnd" <nobody@home.com> wrote in message news:JxeRn.38054$rU6.33631@newsfe10.iad... > I'd rather not write verilog & specify each rom or ram word individually. > Cyclone 2 supports logic cell usage > for rom or ram. I'm surprised cyclone 3 doesn't. Xilinx allows either LUT > or block memory for ram or rom. > Nothing to do with sync or async. > > "glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message > news:hv3rmb$ul3$1@speranza.aioe.org... >> newzhnd <nobody@home.com> wrote: >> >>> Help !!! The megawizard in Quartus 2 does not seem to support >>> generating >>> small roms & rams using the LUT >>> tables, only using the M9K memory blocks. Any way to generate small >>> roms & >>> rams using the logic cells ? >>> I'm looking for something similar to Xilinx distributed memory >>> generator. >>> TIA. >> >> Can't you just generate them in ordinary verilog or VHDL? >> >> For Xilinx, the RAM arrays are synchronous, so it has to generate >> LUT RAM (or ROM) if it is used asynchronously. >> >> -- glen > > Just use the LPM_CONSTANT primitive and specify the bit width and value. I am sure you can take it from there ....Article: 148023
Dear Friends,
i am using Altium Designer for fpga and embedded project on digilent
spartan3E-500 board.
I have created an FPGA project in Altium using open bus document
containing three device:
1. TSK3000A
2. WB_PRTIO_1 (for leds)
3. WB_UART_V2_1
Added a top level schematic sheet. Added constraint file to the
project containing correct fpga pin designators. Configured the
TSK3000 memory size as 16K. The fpga project gets synthesized and bit
stream is generated without any problem.
Next i created an embedded project and made it child of the TSK3000
cpu.
Configured Aplication Memory as 0-8K as ROM and 8k-16K as ram.
Adjusted the Stack size to 512. Heap size " " (nothing not even 0).
Created main.c and software platform document. My software platform
document contains:
hardware rappers:
1. WB_PRTIO_1
2. WB_UART_V2_1
and driver files:
1. DRV_PRTIO_1
2. DRV_UART_V2_1
following is my main.c:
-------------------------------------------------
#include <stdio.h>
#include <stdint.h>
#include <drv_uart8.h>
#include <drv_ioport.h>
#include "hardware.h"
#include "devices.h"
uart8_t* uart;
ioport_t* ioport;
void main(void)
{
int value=0;
uart = uart8_open(DRV_UART8_1); //uart8_t* uart8_open(int id);
uart8_set_baudrate(uart,19200);
ioport = ioport_open(DRV_IOPORT_1); //ioport_t* ioport_open(const int
id);
value = uart8_write(uart,"helloworld\n", 20);
ioport_set_value(ioport, WB_PRTIO_1, 0xaa);
ioport_set_value(ioport, WB_PRTIO_1, 0x55);
while (1)
{
//int uart8_putchar(uart8_t *restrict drv, int val);
//uart8_putchar(uart, uart8_getchar(uart)); //int
uart8_getchar(uart8_t *restrict drv);
uart8_putchar(uart, 'U');
}
}
---------------------------------
I have attached pc com port with my boards serial port and running
hyper terminal on the other end of the serial cable.
Now the problem is:
I can write to leds without any problem but i never see prints from
uart8_write(); function.
I have following questions which I hope someone will come up with
answers:
1. How to compute value of stack requirement?
2. How to compute value for heap?
3. What might be wrong with my design that i dont see message on the
serial port?
4. How can i configure my embedded design to re-direct printf output
to UART?
Regards.
Article: 148024On 6/14/2010 1:45 PM, LC wrote: > > Should I expect that this would be the right up limit I could do it ? > Is there any clever design of this frontend to allow higher speed ? > Does XAPP265 give you any architectural hints that you can use in your Altera part? HTH., Syms.
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