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Authors (E)
e:
82261: 05/04/09: Neural Networks in FPGA
82302: 05/04/10: Re: Neural Networks in FPGA
e kartheeka:
153697: 12/04/25: FPGA circuit simulator
153698: 12/04/25: FPGA circuit simulator
E Srikanth:
152373: 11/08/15: Re: VHDL horror in Xcell 76
E. Backhus:
49970: 02/11/26: Re: question about PCB traces for FPGA board... ?
58468: 03/07/24: XST fails to recognize FSM with registered outputs
71375: 04/07/16: Re: FPGA with fully asynchronous RAM
71453: 04/07/19: Re: FPGA with fully asynchronous RAM
71493: 04/07/20: Re: FPGA with fully asynchronous RAM
E. Kappos:
11593: 98/08/26: test - ignore
14243: 99/01/21: Re: CORDIC (was: Best way to digitally synth. stable frequencies?)
E. Napoli:
46451: 02/08/30: XNF vs. EDIF
50147: 02/12/03: free software for XC4000
E. R. Beers Jr.:
5614: 97/02/28: Re: Cypress says good-bye to Anti-Fuse
E. Robert Tisdale:
20802: 00/02/23: Bit Serial Arithmetic De-mystified
20828: 00/02/23: Re: Bit Serial Arithmetic De-mystified
20871: 00/02/24: Re: Bit Serial Arithmetic De-mystified
24595: 00/08/15: Re: Non-disclosures in job interviews
24598: 00/08/15: Re: Non-disclosures in job interviews
E. van Putten:
80699: 05/03/10: Altera Stratix kit PCI to DDR reference design
80702: 05/03/10: Altera Stratix kit PCI to DDR reference design
e.i.chester:
40738: 02/03/14: Re: How would I know somebody has copied my files in Unix?
E.M. Shattock:
8105: 97/11/17: M1 router crash
8113: 97/11/18: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
8186: 97/11/25: Xilinx tech support
8320: 97/12/08: Re: Xilinx M1 ABEL-EDIF problem
8481: 97/12/20: Simulating Bidi pins/Foundation
9138: 98/02/24: Re: AZ - JOB => Digital FPGA Design Engineers needed...........
9225: 98/03/03: Re: The case for Linux and EDA
E.S.:
69555: 04/05/13: Re: unused IO on SPARTAN-IIE
69714: 04/05/18: Re: How to select an FPGA size (beginner)
69774: 04/05/19: Re: program flash memory through JTAG on FPGA
69802: 04/05/20: Re: S3 cheap shot
69803: 04/05/20: Re: program flash memory through JTAG on FPGA
69861: 04/05/22: Transputer on FPGA, was: Re: Never right, always room for improvement
69954: 04/05/25: Re: Nios II = Microblaze
69960: 04/05/25: Re: Nios II = Microblaze
69997: 04/05/26: Re: Nios II = Microblaze
69998: 04/05/26: Economics of CPU softcores, was : Re: Nios II = Microblaze
72802: 04/09/02: Re: EDK core wrapping and include files
73772: 04/09/29: Re: MicroBlaze is now available as Open-Source!! (from independant
74022: 04/10/02: Re: JOP on Spartan-3 Starter Kit
74031: 04/10/02: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
73580: 04/09/24: Re: Webpack 6.3 and Spartan3-1000/1500?
73623: 04/09/26: Re: XILINX FIX UP THE WEBPACK 6.3 DOWNLOAD !!!
73650: 04/09/27: Re: embedded linux on FPGA?
75197: 04/10/28: xilinx edk 6.3
75286: 04/11/01: Re: information about Nuhorizon Spartan-3 Development Board ?
74583: 04/10/14: Re: Xilinx to Make Image Processing FPGA
74628: 04/10/15: Re: Question on Xilinx VirtexPro II FPGA chip... please
74929: 04/10/21: Re: Anyone routing signals between balls in FBGA?
75515: 04/11/08: xilinx software licenses and updates
75564: 04/11/09: Re: C Compiler for Picoblaze !!!!!
77169: 04/12/27: MicroBlaze with MMU
77883: 05/01/19: Re: Comparison of LEON2, Microblaze and Openrisc processors
<e2point@yahoo.com>:
121529: 07/07/06: or1200 uses more than 100% of resources. how to reduce?
121545: 07/07/07: or1k binutil source checkout problem
122446: 07/07/27: Re: or1200 uses more than 100% of resources. how to reduce?
124975: 07/10/13: where to download latest systemc libararies?
<e8johan@gmail.com>:
111748: 06/11/09: Microblaze + uClinux issues
111796: 06/11/10: Re: Microblaze + uClinux issues
<e97bjli@thn.htu.se>:
21426: 00/03/22: constant error in VHDL code
21853: 00/04/04: No net is connected....... ( xilinx)
22297: 00/05/04: How to connect JTAG to XCS10pc84 FPGA device
22496: 00/05/10: Spartan XCS10
26429: 00/10/16: Low power cpld?
<eacosta@media.mit.edu>:
816: 95/03/06: Re: Comp.Arch.FPGA Reflector V1 #152
Eagle_mk4:
147709: 10/05/18: MIG v3.0 inputs signal
147800: 10/05/25: Re: MIG v3.0 inputs signal
147801: 10/05/25: Re: MIG v3.0 inputs signal
147858: 10/05/27: Re: MIG v3.0 inputs signal
147893: 10/05/31: Re: MIG v3.0 inputs signal
Eaglet_bff:
82071: 05/04/06: How to use the library in VHDL (ISE)?
<eapen.abraham@gmail.com>:
118503: 07/04/28: TigerSHARC TS201 to PLX 9656
118524: 07/04/29: Re: TigerSHARC TS201 to PLX 9656
118561: 07/04/30: Serial FPDP
118613: 07/05/01: Re: synthesis tools
118614: 07/05/01: Re: TigerSHARC TS201 to PLX 9656
Earthlink News:
17293: 99/07/19: Re: Frequency multiplier in XC4000
17310: 99/07/20: Re: Frequency multiplier in XC4000
eas:
35545: 01/10/10: qpsk clock recovery
35591: 01/10/11: Re: qpsk clock recovery
35783: 01/10/17: Digital mixers,complex multipliers
<eascheiber@yahoo.com>:
103580: 06/06/06: ppc instruction count
103724: 06/06/09: Re: ppc instruction count
104208: 06/06/21: cache aware programming
104306: 06/06/23: Re: cache aware programming
104307: 06/06/23: Re: cache aware programming
110520: 06/10/17: xilinx power pc & microblaze
113369: 06/12/11: booting from isocm
113600: 06/12/17: ppc elf data and vectors sections
116145: 07/03/02: OPB-to-PLB bridge
116734: 07/03/16: dual PowerPC booting
117875: 07/04/12: EDK + XMD
<easymake@hotmail.com>:
8235: 97/12/02: FREE INCOME OPPORTUNITY
easystep2:
88393: 05/08/17: FPGA-Based system design project
<eawckyegcy@yahoo.com>:
57199: 03/06/25: Xilinx XC3430A
ebi:
90377: 05/10/11: stratix fpga pll
Eboy:
90682: 05/10/18: Webpack install yields "299" error
ec:
79528: 05/02/20: BACK to FPGA
79558: 05/02/21: Re: BACK to FPGA
<ece00380@myport.ac.uk>:
155168: 13/05/22: Re: EPC2 and JTAG
<ecebharath@gmail.com>:
158188: 15/09/11: I am getting errors when i run a systemC Code in edaplayground
158195: 15/09/12: Re: I am getting errors when i run a systemC Code in edaplayground
<ecffung@ntu.edu.sg>:
7785: 97/10/15: Help on coding numerical algorithms using VHDL
echo:
122816: 07/08/07: EDK 8.1
122823: 07/08/07: Re: EDK 8.1
122853: 07/08/08: Re: EDK 8.1
echoisme:
88629: 05/08/24: what is the difference between "configuring" and "programming"?
88670: 05/08/24: Re: what is the difference between "configuring" and "programming"?
88720: 05/08/25: Re: what is the difference between "configuring" and "programming"?
88722: 05/08/25: SystemACE CF and partial reconfiguration
Eci User:
15154: 99/03/10: need info
Eckhard Hammer:
27451: 00/11/22: Re: Using FPGA as PCI target
<ecla@world.std.com>:
17231: 99/07/12: Boston, MA: Senior ASIC Designer
ECM Selection Ltd:
7967: 97/11/04: The Top UK Opportunities in ASIC, Systems & Hardware R&D, ECM
8118: 97/11/19: The Top UK Opportunities in ASIC, Systems & Hardware R&D, ECM
10547: 98/05/29: VHDL, Processor Design, 3D Graphics, to 35k, Cambridge, UK - ECM
10548: 98/05/29: VHDL, 3D Graphics, Embedded Systems, to 35k, Cambridge, UK - ECM
10577: 98/06/02: VHDL, Processor Design, 3D Graphics, to 35k, Cambridge, UK - ECM
10578: 98/06/02: VHDL, 3D Graphics, Embedded Systems, to 35k, Cambridge, UK - ECM
ecp:
9235: 98/03/04: Re: Debugging question.
<ecpark@gmail.com>:
84291: 05/05/16: Re: "Mine is bigger than yours..."
ECruz68007:
22075: 00/04/18: Modification on Pioneer DV-525 dvd player inquiery
ECS.MSc.SOC:
152233: 11/07/25: synthesizing
152311: 11/08/07: FPGA
152313: 11/08/07: RS232
ed:
28952: 01/01/31: Re: FPGA to ASIC conversion
50810: 02/12/19: stupid rookie timing question
50835: 02/12/20: Re: stupid rookie timing question
53010: 03/02/28: guided par question
53097: 03/03/03: Re: guided par question
57424: 03/06/30: Re: Xilinx par at max effort
64358: 03/12/30: virtex-II problems
128403: 08/01/24: Re: Random Number Generation in VHDL
143927: 09/11/03: initialization issues on Spartan-3E after startup
143948: 09/11/04: Re: initialization issues on Spartan-3E after startup
143950: 09/11/04: Re: initialization issues on Spartan-3E after startup
Ed:
31513: 01/05/29: Re: Want to buy: Old copy of ABEL, Synario or ViewPLD
50676: 02/12/16: Re: Virtex2Pro question
51668: 03/01/18: Re: quality of software tools in general
61852: 03/10/14: Picojava FPGA and Development board
71520: 04/07/20: Altera FPGA's
71522: 04/07/20: Re: 32-channel PC-based logic analyzers
71557: 04/07/21: Cheap FPGA's
103293: 06/05/30: reverse from jedec to abel
115427: 07/02/09: Disabling Interrupts/Context switching in Xilkernel
118265: 07/04/20: Ouputs during startup and Programming
Ed Anuff:
64053: 03/12/14: Help w/ WARNING:Xst:1868
65853: 04/02/08: New open source utility for using Xilinx Block RAM
69619: 04/05/15: FPGA Timing question
70101: 04/06/02: Re: How to generate a 320x200 VGA signal?
Ed Arthur:
148: 94/09/01: PLDshell/Intel ftp site
Ed Barrett:
4153: 96/09/19: Re: Good starting point to learn FPGA for hobbyist?
4624: 96/11/21: Re: Lattice ISP Question
5291: 97/02/04: Re: Altera BitBlaster
5461: 97/02/17: Re: Xilinx or Altera?
5568: 97/02/24: Re: Antifuse Comparisons?
5580: 97/02/25: Re: Xilinx or Altera?
5672: 97/03/05: Re: Antifuse Comparisons?
6145: 97/04/17: Re: Seeking PALASM/ABEL/CUPL/?
6215: 97/04/28: Re: ISP CPLD from AMD or Cypress???
6247: 97/05/02: Re: ISP CPLD from AMD or Cypress???
6259: 97/05/05: Re: ISP CPLD from AMD or Cypress???
7205: 97/08/14: Re: FPGA power consumption
7288: 97/08/21: Re: ISP Stories
9640: 98/03/27: Re: Dual port
Ed Beers:
2525: 95/12/27: Re: [q][Reverse Engineering Protection]
Ed Browne, Precision Electronic Solutions:
37068: 01/11/29: Re: Modelsim
48133: 02/10/11: Active HDL
Ed Caceres:
3983: 96/08/28: DES in Xilinx
Ed Casas:
3944: 96/08/23: Re: CHEAP XILINX FPGA ROUTING SOFTWARE ?
Ed Coombs:
108672: 06/09/15: Re: xilinx bram instantation template in vhdl?
Ed Diego:
57767: 03/07/06: Spartan2E + PCI
Ed Hemphill:
61601: 03/10/07: Re: AWGN in VHDL
Ed Henciak:
57877: 03/07/09: Re: Cyclone vs Spartan-3
Ed Hutchinson:
12126: 98/10/01: Re: NFX780, where to get?
Ed J:
62524: 03/10/31: Floating Point support
62534: 03/10/31: Re: Floating Point support
Ed Jubenville:
53188: 03/03/05: Virtex II Pro : Memec V2PRO board
Ed McCauley:
9222: 98/03/03: Re: Xilinx Info.
8877: 98/02/04: Re: FPGA/ASIC - same difference?
8887: 98/02/05: Re: Can XACT6 run in a NT4 DOS box?
8893: 98/02/05: Re: Can XACT6 run in a NT4 DOS box?
9006: 98/02/13: Re: Altera Classic Devices 1810, 910, 5128 Problems
9443: 98/03/13: Re: Strange Xilinx question?
9449: 98/03/14: Re: Strange Xilinx question?
9459: 98/03/15: Re: Strange Xilinx question?
9481: 98/03/16: Re: Strange Xilinx question?
9537: 98/03/21: Re: Dual port
9816: 98/04/07: Re: Effects of IC production
9954: 98/04/16: Re: Xilinx Timing Constraints
10327: 98/05/12: Re: How to use LogiBlox Components in FPGA Express?
10328: 98/05/12: Re: Xilinx Routing Delay
10329: 98/05/12: Re: Xilinx Routing Delay
10357: 98/05/14: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
10444: 98/05/19: Re: Building signal delays inside an FPGA
10566: 98/05/30: Re: PGCK pin and external clock assignment problem on XC4000A
10581: 98/06/02: Re: More Xilinx timing constraints
10698: 98/06/11: Re: Xilinx 4000/Spartan: Maximum pin pullup
10842: 98/06/24: Re: 62.5MHz 128x17Bit Dualport-Fifo in Xilinx
10859: 98/06/25: Re: Xilinx Foundation simulator problem?
10948: 98/07/06: Re: Configure with BIT file
10957: 98/07/07: Re: CRC's and PRBS in Paralell
10990: 98/07/08: Re: Configure with BIT file
11004: 98/07/09: Re: question on combinational logic synthesis for FPGA
11007: 98/07/09: Re: Xilinx Foundation Frustartions
11014: 98/07/10: Re: Xilinx Foundation Frustartions
11237: 98/07/29: Re: TRISTATE in FPGA
11441: 98/08/13: Re: ADPCM G.726 encoder/decoder
11479: 98/08/18: Re: Help on Xilinx !
11630: 98/08/27: Re: Help on Xilinx !
11821: 98/09/11: Re: Xilinx Spartan vs. 4K series
11850: 98/09/14: Re: ASIC -> FPGA async issues
11861: 98/09/15: Re: ASIC -> FPGA async issues
11862: 98/09/15: Re: ASIC -> FPGA async issues
11863: 98/09/15: Re: ASIC -> FPGA async issues
11878: 98/09/15: Re: ASIC -> FPGA async issues
11885: 98/09/16: Re: Xilinx Spartan and 4K speed grades
11902: 98/09/17: Re: Help a confused teacher
12368: 98/10/10: Re: Need 100MHz Counter with 3 Comparators
12369: 98/10/10: Re: Spartan: strange problem
12370: 98/10/10: Re: Xilinx may not support schematics for Virtex?????
13808: 98/12/28: Re: 22V10 Metastability - help please
15307: 99/03/18: Re: Clock multiplier
15308: 99/03/18: Re: Possible problem with die shrink of xc4010
21368: 00/03/20: Re: How to eliminate high fan-out in Xilinx FPGA's?
22198: 00/05/01: Re: Xilinx "length count" question
Ed Mcgettigan:
16020: 99/04/28: Re: High speed PLL inside FPGA
16027: 99/04/28: Re: High speed PLL inside FPGA
16078: 99/04/30: Re: Double Port ram for Altera EPF10K20
16098: 99/05/03: Re: 10KE dual port RAM help ?
16151: 99/05/06: Re: Bugs in place and route s/w....XLINX???
17421: 99/07/26: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
17461: 99/07/29: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
17533: 99/08/06: Re: carry logic for implementing wide logic functions
17584: 99/08/11: Re: Xilinx: Verilog only???
19653: 00/01/06: Re: Virtex 5V io
19677: 00/01/07: Re: Design security
20204: 00/01/31: Re: Virtex DLL inoperability
21026: 00/03/03: Re: restrictions due to signal types of Global Clock inputs for Virtex
22062: 00/04/17: Re: CLKDLL stabilty state
22064: 00/04/17: Re: OE in hierachial ABEL design
Ed McGettigan:
94: 94/08/13: FPGA Hobbyist and their software/programmer/hardware
3168: 96/04/17: Re: ACTEL design with Synopsys
14223: 99/01/20: Re: Secondary clock nets in Xilinx Virtex
15087: 99/03/05: Re: I/O standards revisited
15125: 99/03/08: Re: Clock divider: 100MHz->40MHz
15298: 99/03/17: Re: Allowed logic functions in Virtex LE
15329: 99/03/18: Re: Allowed logic functions in Virtex LE
15408: 99/03/22: Re: Free Xilinx Vendor Tools ... NOT :-(
15575: 99/03/31: Re: virtex partial reconfiguration
15590: 99/04/01: Re: virtex partial reconfiguration
15610: 99/04/02: Re: virtex partial reconfiguration
15611: 99/04/02: Re: virtex partial reconfiguration
15689: 99/04/08: Re: ZBT to Virtex Interface at +100M
15928: 99/04/21: Re: Virtex, VREF, and serial configuration
15942: 99/04/22: Re: High speed reconfigurability
80715: 05/03/10: Re: ML310 + Linux (elf file ) + bit file
80722: 05/03/10: Re: RocketIO and Gigabit Ethernet
81194: 05/03/18: Re: rocketio
81370: 05/03/22: Re: rocketio
81372: 05/03/22: Re: PowerPC soft-core?
82227: 05/04/08: Re: Getting started with Virtex-II Pro LC Dev Board
82343: 05/04/11: Re: Problem with appnote XAPP622 (SDR LVDS)
82350: 05/04/11: Re: xilinx virtex 4 download cable
82582: 05/04/14: Re: Connecting Virtex2pro to Virtex4 via RocketIO MGT's
82593: 05/04/14: Re: Connecting Virtex2pro to Virtex4 via RocketIO MGT's
82597: 05/04/14: Re: Xilinx VIIPro power supplies
82600: 05/04/14: Re: Connecting Virtex2pro to Virtex4 via RocketIO MGT's
82814: 05/04/18: Re: rocketio decoupling
82832: 05/04/18: Re: rocketio decoupling
83165: 05/04/25: Re: New FPGA Development Board
83361: 05/04/28: Re: RocketIO decoupling
83702: 05/05/05: Re: Xilinx V4 Power Calculations
83709: 05/05/05: Re: VIIPro on-chip LVDS termination
83720: 05/05/05: Re: VIIPro on-chip LVDS termination
84017: 05/05/11: Re: Test the code on FPGA Board...
84096: 05/05/12: Re: 8051 IP core
84632: 05/05/23: Re: Same problem
84683: 05/05/24: Re: using a SDRAM FIFO
84729: 05/05/25: Re: xilinx virtex 4 download cable
84881: 05/05/31: Re: generate systemACE file in EDK
84936: 05/06/01: Re: how to generate system ACE file in EDK
85042: 05/06/03: Re: xilinx virtex 4 download cable
86586: 05/06/30: Re: ip core supply
86843: 05/07/07: Re: Actel vs. Xilinx and Altera
88411: 05/08/17: Re: Chipscope pro : timing constraint?
88419: 05/08/17: Re: Chipscope pro : timing constraint?
88452: 05/08/18: Re: Chipscope pro : timing constraint?
88484: 05/08/19: Re: Chipscope pro : timing constraint?
88858: 05/08/30: Re: Embedded Processors/Serdes
88884: 05/08/30: Re: Embedded Processors/Serdes
88891: 05/08/30: Re: Embedded Processors/Serdes
88921: 05/08/31: Re: chipscope commands?
89020: 05/09/02: Re: Embedded Processors/Serdes
89457: 05/09/15: Re: Xilinx V2Pro & SATA hard disk
89501: 05/09/16: Re: fan out capability of FPGA
89505: 05/09/16: Re: Xilinx ML403
89516: 05/09/16: Re: Xilinx ML403
89565: 05/09/19: Re: Xilinx ML403
89655: 05/09/21: Re: data logging via JTAG?
89859: 05/09/28: Re: chipscope pro
90047: 05/10/03: Re: Xilinx dev board with high quality video?
90071: 05/10/04: Re: Xilinx dev board with high quality video?
90073: 05/10/04: Re: Xilinx dev board with high quality video?
90083: 05/10/04: Re: Xilinx IMPACT Problem... detects 101 unknown devices
90342: 05/10/10: Re: Xilinx Chipscope VIO Core Utilization
90657: 05/10/18: Re: Newbie question: XC3S400 Gate Count
90680: 05/10/18: Re: Newbie question: XC3S400 Gate Count
90685: 05/10/18: Re: Newbie question: XC3S400 Gate Count
91162: 05/10/31: Re: SystemACE parts wanted
93295: 05/12/19: Re: Powering unused MGTs in XC4VFX20CES2
93296: 05/12/19: Re: Powering unused MGTs in XC4VFX20CES2
93465: 05/12/22: Re: Going insane - Xilinx VGA controller...
94025: 06/01/04: Re: Using posedge and negedge causing me grief
95753: 06/01/25: Re: porting linux on ml403
95755: 06/01/25: Re: So what happened to JHDLBits?
95845: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source
95915: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source
95909: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source
96116: 06/01/30: Re: Xilinx Legal
96189: 06/01/31: Re: Xilinx Legal
96192: 06/01/31: Re: Xilinx Legal
97108: 06/02/16: Re: WebPACK license (and Quartus Web Edition too).
100589: 06/04/12: Re: vertex II and powerpc core
101140: 06/04/26: Re: How to avoid lossing channel bonding when using Rocket IO?
101284: 06/04/28: Re: How to avoid lossing channel bonding when using Rocket IO?
101288: 06/04/28: Re: Xilinx SystemACE on multi-FPGA board
101320: 06/04/28: Re: Xilinx SystemACE on multi-FPGA board
101596: 06/05/03: Re: ML405 board
101769: 06/05/05: Re: ML405 board
102371: 06/05/15: Re: Virtex 5 announced
102374: 06/05/15: Re: Virtex 5 announced and sampling
102489: 06/05/16: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
102495: 06/05/16: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
102542: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
102543: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
102603: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
102615: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
102616: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source
102876: 06/05/22: Re: xilinx pricing discrepancy
102949: 06/05/23: Re: Verilog vs VHDL
103302: 06/05/30: Re: Aurora sample design: Testing/Eye Diagrams
103413: 06/06/01: Re: RocketIO signal polarity swap
103749: 06/06/09: Re: Anyone with Xilinx SP305-board ?
103897: 06/06/14: Re: boot mode pins on Spartan3
103919: 06/06/14: Re: boot mode pins on Spartan3
103928: 06/06/15: Re: Virtex-4 with Rocket IO capability??
103938: 06/06/15: Re: Virtex-4 with Rocket IO capability??
103943: 06/06/15: Re: ARM cores in FPGA ?
103986: 06/06/16: Re: ARM cores in FPGA ?
104029: 06/06/16: Re: Floppy to FPGA?
104241: 06/06/21: Re: Detachable Virtex-II Pro/Virtex-4 FX module with Rocket I/O
104498: 06/06/28: Re: Virtex5 Availability
104506: 06/06/28: Re: Virtex5 Availability
104533: 06/06/29: Re: Problem to extend Xilinx GSRD Design
104554: 06/06/29: Re: Problem to extend Xilinx GSRD Design
104567: 06/06/29: Re: Problem to extend Xilinx GSRD Design
104591: 06/06/30: Re: Problem to extend Xilinx GSRD Design
105286: 06/07/19: Re: Virtex 4 ACE Compact Flash configuration problem
105308: 06/07/19: Re: Virtex 4 ACE Compact Flash configuration problem
105356: 06/07/20: Re: Virtex 4 ACE Compact Flash configuration problem
105395: 06/07/21: Re: Virtex 4 ACE Compact Flash configuration problem
105470: 06/07/24: Re: Virtex 4 ACE Compact Flash configuration problem
105495: 06/07/24: Re: Virtex 4 ACE Compact Flash configuration problem
105555: 06/07/25: Re: Virtex 4 ACE Compact Flash configuration problem
105585: 06/07/26: Re: Virtex 4 ACE Compact Flash configuration problem
107021: 06/08/23: Re: Xilinx ML501 availability
107144: 06/08/24: Re: RocketIO over cable
107267: 06/08/25: Re: RocketIO over cable
109525: 06/09/27: Re: ML501 where to order
109726: 06/10/04: Re: Xilinx PowerPC & MicroBlaze Development Kit
109825: 06/10/05: Re: System ACE woes
110343: 06/10/13: Re: ML501 finally released
111506: 06/11/03: Re: maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
114362: 07/01/12: Re: RocketIO, MGT documentation. Does MGT clcok have to be 50% duty
114536: 07/01/18: Re: Behavior of REV input in Virtex2 flops?
114675: 07/01/22: Re: edif format
114876: 07/01/25: Re: Xilinx USB download cable
115969: 07/02/26: Re: ML501 Platform Flash Configuration
116043: 07/02/28: Re: Virtex 4 FX Sonet Alignment
117752: 07/04/09: Re: MGT Clocking
117784: 07/04/10: Re: Why I cannot use the XAUI core(generated by xilinx)
118441: 07/04/26: Re: V5 GTP question
120140: 07/06/01: Re: ML402 development board
120524: 07/06/08: Re: FPGA with ARM+CAN+USB+ethernet+ADC
122825: 07/08/07: Re: EDK 8.1
123956: 07/09/07: Re: Rocket IO clock
124271: 07/09/17: Re: global clock on virtex5 question
124315: 07/09/18: Re: global clock on virtex5 question
125574: 07/10/29: Re: Bitfile checking
125588: 07/10/29: Re: Bitfile checking
126573: 07/11/27: Re: Global Reset using Global Buffer
126981: 07/12/07: Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
127054: 07/12/10: Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
127055: 07/12/10: Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
127142: 07/12/12: Re: Chipscope 7.1 and JTAG TAP
127153: 07/12/12: Re: Xilinx RocketIO problems
127191: 07/12/13: Re: ML505 board Compact Flash
127226: 07/12/14: Re: xilinx v5 configeration problem
127227: 07/12/14: Re: serial ATA question
127370: 07/12/19: Re: BGA reflow soldering using vapor phase
128190: 08/01/17: Re: Chipscope compatible with Synopsis or Cadence sythesise tools?
128195: 08/01/17: Re: Chipscope compatible with Synopsis or Cadence sythesise tools?
128612: 08/01/31: Re: Design security for pre-Virtex2 parts ?
128698: 08/02/04: Re: Loading from Compact Flash on ML310...
128707: 08/02/04: Re: 4-bit table look-up
129604: 08/02/28: Re: Loading from Compact Flash on ML310...
130900: 08/04/04: Re: EDK 10.1 first impressions
130989: 08/04/07: Re: Virtex-5 FXT coming soon?
130990: 08/04/07: Re: FPGA configuration mode on ML310
131479: 08/04/22: Re: How to independently program the embedded PowerPC in a Virtex?
131661: 08/04/28: Re: Timing closure problem --- how to make the QII fitter smarter
132621: 08/06/03: Re: xilinx and jtag
132940: 08/06/10: Re: Trouble programming V4FX40
132955: 08/06/11: Re: Trouble programming V4FX40
133059: 08/06/16: Re: XAUI v7.2 - timing issue - *channel bonding attributes*
133061: 08/06/16: Re: XAUI v7.2 - timing issue - *channel bonding attributes*
133392: 08/06/26: Re: synthesis error
134307: 08/08/05: Re: Altera sues Zilog - signs of desperation from Programmable Vendor
134602: 08/08/20: Re: Xilinx extends Spartan 3A series
134627: 08/08/21: Re: Xilinx extends Spartan 3A series
134658: 08/08/25: Re: Xilinx extends Spartan 3A series
134714: 08/08/27: Re: Virtex 5 bitstream encryption
134756: 08/08/28: Re: Virtex 5 bitstream encryption
135093: 08/09/15: Re: need fast FPGA suggestions
135221: 08/09/22: Re: Virtex-II Pro to Stratix GX
135264: 08/09/23: Re: Is it possible to get an RTL netlist from Xilinx tools?
135292: 08/09/24: Re: Weird DCM problem with external deskew
135309: 08/09/25: Re: Weird DCM problem with external deskew
135419: 08/10/01: Re: Asynchronous delay report shows delays longer that clock period
135431: 08/10/01: Re: Xilinx device not listed
135607: 08/10/09: Re: Virtex-5 clocking
135643: 08/10/10: Re: Virtex-5 clocking
135692: 08/10/12: Re: DDR FLOP?
138416: 09/02/20: Re: Xilinx ISE complete device IBIS file generation?
138843: 09/03/12: Re: Want to buy: FPGA T-Shirt $$
140183: 09/05/01: Re: ISE/EDK/SDK 11.1 licensing
140919: 09/05/29: Re: Urgent help with a Simple AND simulation
141322: 09/06/17: Re: Do you know how aggressive the patent fighting between Xilinx
141352: 09/06/19: Re: Virtex 2 Pro IO Banks Vcco
141359: 09/06/19: Re: FDRSE Spartan 3A - Active high/low set/reset
141435: 09/06/24: Re: True dual-port RAM in VHDL: XST question
141445: 09/06/24: Re: Virtex-6 shipping?
141503: 09/06/25: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
141539: 09/06/26: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
141556: 09/06/27: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
141557: 09/06/27: Re: 6/6 infos
141558: 09/06/27: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::) yippii
141629: 09/07/01: Re: pinout
141701: 09/07/03: Re: XILINX: verilog is not supported as a language, using usenglish
142475: 09/08/12: Re: Spartan-6 Boards - Your Wish List
142511: 09/08/13: Re: V5 GTX and V4 MGT interoperability
142526: 09/08/14: Re: Spartan-6 Boards - Your Wish List
142827: 09/09/02: Re: Virtex-5 clock input is excessively loading SERDES recovered
142844: 09/09/03: Re: Virtex-5 clock input is excessively loading SERDES recovered
142852: 09/09/03: Re: Where to find source code for Xilinx ML507 board demos?
142853: 09/09/03: Re: Spartan-6 boards now REALLY in online shops
142854: 09/09/03: Re: Wants an update on FPGA development IDE/toolchains
142869: 09/09/04: Re: Spartan-6 boards now REALLY in online shops
142875: 09/09/04: Re: Spartan-6 boards now REALLY in online shops
142876: 09/09/04: Re: Virtex-5 clock input is excessively loading SERDES recovered
142912: 09/09/07: Re: Virtex5 DDR2 ref design failed at JTAG programming with CRC error
142926: 09/09/08: Re: Traversing hierarchy in UCF works for OBUF, but not IOBUF, please
142943: 09/09/09: Re: Traversing hierarchy in UCF works for OBUF, but not IOBUF, please
142955: 09/09/09: Re: Traversing hierarchy in UCF works for OBUF, but not IOBUF, please
143062: 09/09/17: Re: Looking for Virtex-6 PCIe development board
143063: 09/09/17: Re: Looking for Virtex-6 PCIe development board
143291: 09/09/29: Re: SP601 HDL source files available?
143406: 09/10/09: Re: foundation 2.1 - 3.1 sharing...
143506: 09/10/13: Re: difference between virtex 5 and old versin(virtex3,2)
143837: 09/10/28: Re: ML605 Evaluation Kit and FPGA Mezzanine Connectors (FMC) ?
143839: 09/10/28: Re: ML605 Evaluation Kit and FPGA Mezzanine Connectors (FMC) ?
143874: 09/10/30: Re: Chipscope with Verilog
144208: 09/11/19: Re: ML605 Evaluation Kit and FPGA Mezzanine Connectors (FMC) ?
144218: 09/11/20: Re: ML605 Evaluation Kit and FPGA Mezzanine Connectors (FMC) ?
144219: 09/11/20: Re: ML605 Evaluation Kit and FPGA Mezzanine Connectors (FMC) ?
144486: 09/12/09: Re: Data2MEM - finding the blockrams after PAR?
144563: 09/12/14: Re: Xilinx's version of Quartus' Signaltap?
144635: 09/12/21: Re: Please help, Xilinx FIFO problem!
144657: 09/12/21: Re: Please help, Xilinx FIFO problem!
144766: 09/12/31: Re: How to protect my Virtex5 design without battery?
144871: 10/01/10: Re: Solved! Why my pins were being optimized out. How do I get the
145058: 10/01/22: Re: Networking Board Recommendation
145156: 10/01/29: Re: synthesizing a completely empty design for an FPGA to measure
145163: 10/01/29: Re: synthesizing a completely empty design for an FPGA to measure
145254: 10/02/03: Re: Help Please - Xilinx message
145626: 10/02/16: Re: EDK 11,1 on Windows 7, 32 Bit
145627: 10/02/16: Re: rocketio TX delay between sata0 and sata1
145642: 10/02/16: Re: EDK 11,1 on Windows 7, 32 Bit
145735: 10/02/21: Re: rocketio TX delay between sata0 and sata1
145764: 10/02/22: Re: rocketio TX delay between sata0 and sata1
145768: 10/02/22: Re: rocketio TX delay between sata0 and sata1
146014: 10/03/03: Re: Xilinx IOBUF - operation Q (virtex4 chip)
146217: 10/03/08: Re: Why doesn't this situation generate a latch?
146226: 10/03/09: Re: Why doesn't this situation generate a latch?
146269: 10/03/10: Re: Why doesn't this situation generate a latch?
146285: 10/03/10: Re: Spartan3AN DDR2 - bad writing zeros
146292: 10/03/10: Re: Why doesn't this situation generate a latch?
146294: 10/03/10: Re: Why doesn't this situation generate a latch?
146560: 10/03/22: Re: Standard cell library help
146601: 10/03/23: Re: Standard cell library help
146732: 10/03/26: Re: Version of Xilinx ISE for Spartan 6 FPGAs
146806: 10/03/29: Re: Xilinx Webpack v11.4 availability
146808: 10/03/29: Re: PCB routing issues for sync SRAM
146817: 10/03/29: Re: XST optimization
146860: 10/03/30: Re: Xilinx Webpack v11.4 availability
146870: 10/03/30: Re: Xilinx Webpack v11.4 availability
146891: 10/03/31: Re: Migrating project from Xilinx ISE v7.1 to v11.1
146892: 10/03/31: Re: FMC Boards ?
146913: 10/04/01: Re: Predefined MACRO's in XST v11.5
146915: 10/04/01: Re: Predefined MACRO's in XST v11.5
147001: 10/04/09: Re: FMC Boards ?
147002: 10/04/09: Re: Debug multiple FPGAs using ChipScope via single JTAG chain
147034: 10/04/10: Re: Module wise FPGA resource utilization report
147222: 10/04/19: Re: clock routing to generic IO pins?
147266: 10/04/21: Re: Virtex 7?
147267: 10/04/21: Re: Xilinx no longer ships with Modelsim MXE?
147669: 10/05/13: Re: problem in clock input in virtexpro/spartan3a/spartan3 kit
147698: 10/05/17: Re: New 'standard' compact programming header needed!
147701: 10/05/17: Re: New 'standard' compact programming header needed!
147710: 10/05/18: Re: New 'standard' compact programming header needed!
147715: 10/05/18: Re: New 'standard' compact programming header needed!
147749: 10/05/21: Re: speed grade and temperature grade aren't marked??
147778: 10/05/23: Re: Xilinx Xact software for XC2018 Logic Cell Array
147903: 10/06/01: Re: Block RAM unusually long setup time ?
147967: 10/06/07: Re: Calling different modules of a project from another main file
148059: 10/06/17: Re: Why is Google so F****** dense about SPAM?
148102: 10/06/21: Re: Xilinx BULLSHITIX-8, when?
148105: 10/06/21: Re: Xilinx BULLSHITIX-8, when?
148112: 10/06/21: Re: Why is Google so F****** dense about SPAM?
148401: 10/07/18: Re: I2C Master Start stop generation
148409: 10/07/19: Re: I2C Master Start stop generation
148410: 10/07/19: Re: I2C Master Start stop generation
148625: 10/08/09: Re: Signal value clears for no reason [VHDL, ISE 10.1]
148654: 10/08/12: Re: XC5VTX240T-2FF1759I4177
148661: 10/08/14: Re: How to use VIO and core inserter at the same time.
148663: 10/08/15: Re: How to use VIO and core inserter at the same time.
148866: 10/09/05: Re: MPMC without MCB on Spartan-6
148886: 10/09/08: Re: We need an administrator for the group to fight spam
148891: 10/09/08: Re: Divide clock by 4/5 in Spartan 3A?
148960: 10/09/15: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
149006: 10/09/20: Re: Stack Exchange site for programmable logic and FPGA design
149039: 10/09/23: Re: Virtex5 MGT signals as standard diff ports
149065: 10/09/27: Re: FPGA For Image Processing[Economical]
149170: 10/10/05: Re: Xilinx Artix 7 - When?
149172: 10/10/05: Re: Xilinx Artix 7 - When?
149217: 10/10/08: Re: Xilinx Artix 7 - When?
149265: 10/10/12: Re: JTAG stops working!
149372: 10/10/19: Re: Old LOC constraint stuck somewhere
149388: 10/10/20: Re: Old LOC constraint stuck somewhere
149459: 10/10/26: Re: using FPGA editor to set IOSTANDARD
149484: 10/10/29: Re: Xilinx ISE ERRORS HDLCompilers:108
149492: 10/10/29: Re: Can't migrate from 11.5 to 12.3
149497: 10/10/29: Re: Can't migrate from 11.5 to 12.3
149506: 10/11/01: Re: Timing error for EDK project using a DCM?
149515: 10/11/01: Re: Timing error for EDK project using a DCM?
149518: 10/11/01: Re: Xilinx ConstraintSystem:59
149545: 10/11/03: Re: Chance to win a SP601 board in Xcell Journal Caption Contest
149548: 10/11/04: Re: Achronix
149691: 10/11/17: Re: Signal is connected to multiple drivers
150639: 11/01/30: Re: Can't program Spartan3A with JTAG
150645: 11/01/31: Re: Can't program Spartan3A with JTAG
150646: 11/01/31: Re: Xilinx tool options
150650: 11/01/31: Re: Can't program Spartan3A with JTAG
150655: 11/01/31: Re: Can't program Spartan3A with JTAG
150685: 11/02/03: Re: Dynamic Voltage switching for FPGA IO
150703: 11/02/04: Re: FPGA pin re-configuration
150880: 11/02/19: Re: Mathematical definition of an FPGA
150885: 11/02/19: Re: Mathematical definition of an FPGA
150893: 11/02/19: Re: Mathematical definition of an FPGA
151028: 11/03/01: Re: xilinx spartan 6
151029: 11/03/01: Re: PLL Cyclone III vs PLL(DLL) Spartan-3AN
151145: 11/03/10: Re: pcb&bitstream
151153: 11/03/11: Re: pcb&bitstream
151163: 11/03/12: Re: pcb&bitstream
151184: 11/03/14: Re: pcb&bitstream
151193: 11/03/14: Re: pcb&bitstream
151194: 11/03/14: Re: pcb&bitstream
151197: 11/03/14: Re: pcb&bitstream
151213: 11/03/15: Re: Regfile access
151218: 11/03/15: Re: Regfile access
151230: 11/03/16: Re: pcb&bitstream
151235: 11/03/16: Re: Regfile access
151243: 11/03/17: Re: Regfile access
151274: 11/03/19: Re: pcb&bitstream
151280: 11/03/19: Re: pcb&bitstream
151286: 11/03/20: Re: pcb&bitstream
151344: 11/03/25: Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors
151349: 11/03/26: Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors
151350: 11/03/26: Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors
151353: 11/03/27: Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors
151357: 11/03/27: Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors
151360: 11/03/27: Re: fpga express 3.6
151361: 11/03/27: Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors
151365: 11/03/28: Re: Spartan IOB Input Switching Characteristic
151424: 11/04/06: Re: Help with SDC (specifically edge_shift)
151427: 11/04/06: Re: Help with SDC (specifically edge_shift)
151466: 11/04/11: Re: Altium Limited closing up shop - Altium Designer discontinued
151518: 11/04/16: Re: XST - timing constraints of the combinatorial logic
151526: 11/04/17: Re: same RTL on two same boards giving different behaviour
151598: 11/04/25: Re: Xilinx ML605 Demo Qusstion
151600: 11/04/25: Re: Xilinx ML605 Demo Qusstion
151606: 11/04/25: Re: Xilinx ML605 Demo Qusstion
151608: 11/04/25: Re: same RTL on two same boards giving different behaviour
151634: 11/04/27: Re: same RTL on two same boards giving different behaviour
151639: 11/04/28: Re: Xilinx ML605 Demo Qusstion
151653: 11/05/02: Re: help with a power pc processor based software
151696: 11/05/05: Re: Logic Accessible Clock
151704: 11/05/07: Re: Soft Processors and Licensing
151709: 11/05/08: Re: Soft Processors and Licensing
151802: 11/05/18: Re: How to use the EXT_CLK_P and EXT_CLK_N pins of Virtex II Pro
151809: 11/05/19: Re: How to use the EXT_CLK_P and EXT_CLK_N pins of Virtex II Pro
151858: 11/05/25: Re: Fall Times and Pullup
151920: 11/06/03: Re: Looking for bitgen Virtex7 and Kintex7 support
151982: 11/06/17: Re: Xilinx or Altera
152006: 11/06/21: Re: ucf file for 32 bit counter spartan 3e S500E -4
152033: 11/06/23: Re: Depth of logical Circuit
152090: 11/07/05: Re: How do they handle shorts during the dynamic reconfiguration?
152092: 11/07/05: Re: How do they handle shorts during the dynamic reconfiguration?
152193: 11/07/18: Re: FPGA not getting programmed
152196: 11/07/18: Re: FPGA not getting programmed
152200: 11/07/19: Re: FPGA not getting programmed
152296: 11/08/04: Re: DVI-decoder clock question
152298: 11/08/04: Re: die's in different packages
152300: 11/08/04: Re: die's in different packages
152416: 11/08/20: Re: What is the advantage of source-syncronization (in SDRAMs)?
152456: 11/08/25: Re: What is the advantage of source-syncronization (in SDRAMs)?
152500: 11/08/29: Re: Boundary scan
152518: 11/08/30: Re: Problem in using the A23 HS_IO pin of bank J37 with SSTL2_II IO
152522: 11/08/31: Re: Problem in using the A23 HS_IO pin of bank J37 with SSTL2_II IO
152605: 11/09/17: Re: Registers at I/O
152639: 11/09/19: Re: Virtex 6 dev. board suppliers?
152655: 11/09/23: Re: comparing Xilinx XC3S500E-4CPG132C vs Altera Cyclone IV FPGA
152770: 11/10/20: Re: Peter Alfke has passed away
153118: 11/12/07: Re: Xilinx 7 series PCIe core models vs. Icarus Verilog
153128: 11/12/08: Re: Xilinx 7 series PCIe core models vs. Icarus Verilog
153131: 11/12/08: Re: Xilinx 7 series PCIe core models vs. Icarus Verilog
153144: 11/12/12: Re: D-Type Flip flop with negated Q in Webise for a schematic capture
153150: 11/12/12: Re: D-Type Flip flop with negated Q in Webise for a schematic capture
153152: 11/12/13: Re: D-Type Flip flop with negated Q in Webise for a schematic capture
153155: 11/12/13: Re: D-Type Flip flop with negated Q in Webise for a schematic capture
153157: 11/12/16: Re: Clock distribution for ADC and jitter
153518: 12/03/21: Re: Spartan 3 DiffPairs restricted to Banks 0 and 2?
153586: 12/04/02: Re: Ball-park price of Xilinx Virtex 7 FPGA?
153609: 12/04/04: Re: Very poor Xilinx experience
153694: 12/04/24: Re: Data Transfer from PC to FPGA through USB
153769: 12/05/16: Re: Synthesis Problem
153782: 12/05/17: Re: Xilinx ISE Multiple Drivers Error
153786: 12/05/19: Re: Xilinx ISE Multiple Drivers Error
153787: 12/05/19: Re: Xilinx ISE Multiple Drivers Error
153795: 12/05/23: Re: Xilinx ISE Multiple Drivers Error
153953: 12/07/02: Re: accumulator (again)
153961: 12/07/03: Re: accumulator (again)
153969: 12/07/05: Re: accumulator (again)
153971: 12/07/05: Re: accumulator (again)
155167: 13/05/21: Re: FPGA Development Board with hard PowerPC
155800: 13/09/11: Re: FPGA temperature measurement
155802: 13/09/12: Re: FPGA temperature measurement
156970: 14/08/08: Re: What is the content of "High-speed SERDES interfacing such as
157691: 15/01/29: Re: Where in ISE/Vivado are the chip specific resources listed?
Ed Musall:
1544: 95/07/12: Flex 8000: Locking down pins
Ed Ngai:
28386: 01/01/11: Need some help on beginning
29053: 01/02/04: Re: Help for a novice. Where to begin?
29365: 01/02/16: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29523: 01/02/25: Re: Soldering and Unsoldering PQFP by hand ...
37891: 01/12/23: Re: Kindergarten Stuff
37897: 01/12/23: Re: Kindergarten Stuff
37915: 01/12/24: Re: Kindergarten Stuff
ed ngai:
8719: 98/01/21: Re: Opinions of My FPGA - Like Chip Design Wanted
Ed Paolo:
6638: 97/06/08: Re: Need Address/Phone/Fax List of Semiconductor Companies
Ed Perez:
11186: 98/07/23: IT Professionals - Join the NetVital Survey and make a difference
Ed Peterson:
11265: 98/07/31: Re: Symbols, design changes, pin changes
11266: 98/07/31: Re: Symbols, design changes, pin changes
11267: 98/07/31: Re: Symbols, design changes, pin changes
Ed Prochak:
125492: 07/10/26: Re: Changing refresh rate for DRAM while in operation?
136656: 08/11/28: Re: Gizmo invent Gizmo. The State of the Art in 1999, today and the
Ed Stevens:
56031: 03/05/27: 2 Questions about VHDL
56033: 03/05/27: Re: High-Speed Clock & Data Recovery
56043: 03/05/27: Re: 2 Questions about VHDL
56094: 03/05/28: Re: 2 Questions about VHDL
56312: 03/06/02: Level Converters
56762: 03/06/13: XILINX Error Message
57015: 03/06/20: Please help with clock signal
57030: 03/06/20: Re: Please help with clock signal
57043: 03/06/21: Re: Please help with clock signal
57201: 03/06/25: Interfacing IDE
57213: 03/06/25: Re: Interfacing IDE
Ed Taub:
1741: 95/08/22: Re: Any one using synthesizable HDL megacells ?
Ed Vogel:
5201: 97/01/30: Reconfigurable Logic Query
5274: 97/02/03: Re: Reconfigurable Logic Query
5719: 97/03/10: Re: DEVICE SELECTION
<ed.agunos@gmail.com>:
103371: 06/05/31: controlling synthesis and implemention with tcl/tk scripts
122918: 07/08/10: embedded tips
139215: 09/03/23: low-power, high capacity data queue design ideas
ed.mccauley:
28377: 01/01/10: Xilinx XPERT Partner seeking Senior FPGA/ASIC & HDL Engineers
<ed.moore@snellwilcox.com>:
25325: 00/09/06: pcilogic celss
26117: 00/10/04: Re: multi-input adders in virtex ?
<ed@earth.wustl.edu>:
22229: 00/05/02: Start Up Reset after config on Virtex design
ed_h:
113051: 06/12/05: Xilinx MPMC2 "External Ports" question
113057: 06/12/05: Re: Xilinx MPMC2 "External Ports" question
113102: 06/12/06: Re: Xilinx MPMC2 "External Ports" question
113103: 06/12/06: Re: Xilinx MPMC2 "External Ports" question
113104: 06/12/06: Re: Xilinx MPMC2 "External Ports" question
113248: 06/12/08: Re: Xilinx MPMC2 "External Ports" question
113296: 06/12/10: Re: Xilinx MPMC2 "External Ports" question
<Ed_Peschko@csgsystems.com>:
10600: 98/06/05: minimalist FPGA - C API for FPGA
10614: 98/06/05: Re: minimalist FPGA - C API for FPGA
10615: 98/06/06: Re: minimalist FPGA - C API for FPGA
10771: 98/06/17: Paging VCC..
EdA:
80319: 05/03/03: Re: FPGA tool benchmarks on Linux systems
110462: 06/10/16: Re: Synopsys's VMM and Mentor's AVM
120387: 07/06/06: Re: Portable TCP/IP socket library
EDA Research:
3468: 96/06/04: "State-of-the-Art" in ASIC design today
EDA Vendor:
EDA wannabe:
76931: 04/12/15: Exportability of EDA industry from North America?
76954: 04/12/16: Re: Exportability of EDA industry from North America?
<eda1000@my-deja.com>:
20114: 00/01/27: licenses
eda_dude:
48708: 02/10/23: Verilog simulation performance on dual-CPU Linux?
48748: 02/10/23: Re: ISE vs. Foundation
<edad3000@yahoo.co.uk>:
77527: 05/01/09: Configuration devices
edaudio2000@yahoo.co.uk:
107204: 06/08/25: Installing Quartus 6 "web edition full"
127673: 08/01/05: Cyclone II short-circuit failure mode
127718: 08/01/06: Re: Cyclone II short-circuit failure mode
<eddds@dds.nl>:
32483: 01/06/27: Spartan2 spares!
Eddie Amara:
2015: 95/10/02: To John Cooley and other members of the FPGA industry:
eddie amara:
1728: 95/08/21: Need Help-FPGA Dev/Des.Eng.
1729: 95/08/21: Help Needed-FPGA Apps Eng.-Allentown,PA.-Recruiter
1730: 95/08/21: Help Needed-Technical Marketing Eng.FPGA-Allantown,Pa.-Recruiter
1731: 95/08/21: Help Needed-FPGA Technical Engineer-Allentown,Pa.-Recruiter
1732: 95/08/21: Help Needed-FPGA Product Engineer-Allentown,Pa.-Recruiter
1758: 95/08/28: Help Needed-Technical Marketing Eng.FPGA-Allantown,Pa.-Recruiter
1759: 95/08/28: Help Needed-FPGA Product Engineer-Allentown,Pa.-Recruiter
1760: 95/08/28: Help Needed-FPGA Apps Eng.-Allentown,PA.-Recruiter
1761: 95/08/28: Need Help-FPGA Dev/Des.Eng.
1762: 95/08/28: Help Needed-Technical Marketing Eng.FPGA-Allantown,Pa.-Recruiter
1798: 95/09/04: Re: Help Needed-FPGA Apps Eng.-Allentown,PA.-Recruiter
1806: 95/09/05: Re: Help Needed-FPGA Apps Eng.-Allentown,PA.-Recruiter
Eddie H:
121279: 07/06/29: Virtex5 LXT Clock Distribution
121292: 07/06/30: Why PLL and not DCM for V5?
121331: 07/07/02: Can I use chipscoe to look at V5 GTPoutputs
121760: 07/07/12: CML output swing for V5
121778: 07/07/12: Re: CML output swing for V5
121779: 07/07/12: Re: CML output swing for V5
121801: 07/07/13: Re: CML output swing for V5
121830: 07/07/13: Re: CML output swing for V5
121840: 07/07/13: Re: CML output swing for V5
121866: 07/07/13: Re: CML output swing for V5
122154: 07/07/20: Running Virtex5 GTP at lower data rate
122156: 07/07/20: Re: Running Virtex5 GTP at lower data rate
122295: 07/07/25: Re: Running Virtex5 GTP at lower data rate
122342: 07/07/25: Timing simulation
122348: 07/07/25: Re: Timing simulation
122358: 07/07/25: Re: Timing simulation
122429: 07/07/27: Re: Timing simulation
122741: 07/08/05: Single Ended signal in sync with V5 GTP
122744: 07/08/05: Re: Single Ended signal in sync with V5 GTP
122768: 07/08/06: Re: Single Ended signal in sync with V5 GTP
122798: 07/08/07: Re: Single Ended signal in sync with V5 GTP
123215: 07/08/20: Voltage translation question
123219: 07/08/20: Re: Voltage translation question
123236: 07/08/20: Re: Voltage translation question
123249: 07/08/21: Re: Voltage translation question
123316: 07/08/23: Re: Voltage translation question
Eddie Ng:
11209: 98/07/26: Delay Element for async design.
11214: 98/07/26: Re: Delay Element for async design.
Eddy:
22425: 00/05/09: Timing Analyzer drains System recources
41463: 02/03/29: Re: Clock termination affecting JTAG interface
Eddy Sambuaga:
29182: 01/02/08: Need help using bitgen
<eddy_bobby@my-deja.com>:
25448: 00/09/12: Re: Numerically-Controlled Crystal Oscillator (NCXO) or Digitally-Controlled Crystal Oscillator (DCXO) Designs
25449: 00/09/12: Re: Numerically-Controlled Crystal Oscillator (NCXO) or Digitally-Controlled Crystal Oscillator (DCXO) Designs
25860: 00/09/23: Re: Announce: Free HC11 CPU Core
<eddy_reply@xs4all.nl>:
67705: 04/03/17: Cyclone refuses quartusII bitfiles
edgar:
33599: 01/07/31: computer science Vs Computer Enginnering
Edgar Conzen:
16165: 99/05/07: Re: BGA Prototyping ?
Edi:
29643: 01/03/03: Virtex-E Equivalent Power/Ground Pairs
Edi Hiltebrand:
140: 94/08/30: Xilinx slow on distribution of r5.0
261: 94/10/06: Re: CLI
319: 94/10/19: Xilinx v5.0 unified libraries are wasting CLBs
329: 94/10/21: Re: Xilinx v5.0 unified libraries are wasting CLBs
EdiBen612:
74154: 04/10/05: I need help for Xilinx Demo Board (XC40xx-PC84
<edick@hotmail.com>:
85567: 05/06/10: FPGAFLASH
85657: 05/06/13: Re: FPGAFLASH
<edick@idcomm.com>:
119458: 07/05/20: Signal Assignment bugs in Quartus-II ... AGAIN!
119459: 07/05/20: Signal Assignment bugs in Quartus-II ... AGAIN!
<editor@mail.booksonline.com>:
21251: 00/03/14: Survey on computer/electrical engineering – free book
Ediz Cetin:
51721: 03/01/20: Virtex 2 FPGA Board ...
EdJ:
110762: 06/10/21: Can ISE text editor generate CRLF line endings?
EDK Simulation:
89568: 05/09/19: Simulation : EDK
EDM:
21473: 00/03/23: FPGA & single point failure
21631: 00/03/27: Re: FPGA & single point failure
Edmond Tam:
7728: 97/10/07: Design verification jobs
edmoore:
155689: 13/08/05: Re: serial protocol specs and verification
155856: 13/10/03: Re: VHDL syntheses timestamp
160144: 17/06/21: Re: sync or async SRAM?
Edoardo:
40267: 02/03/04: Re: negative offset warning message
47794: 02/10/04: Re: modelsim XE starter
47795: 02/10/04: Re: VHDL primitives: what am I doing that's stupid?
edoardo:
144389: 09/12/03: Xilkernel interrupt test failure.
Edoardo Causarano:
115304: 07/02/06: Re: 9.1i in Red Hat Enterprise Linux AS 64-bit
EDPHWSW:
139703: 09/04/09: xilinx ram dual-edge?
Edson:
118856: 07/05/04: ISE Simulator :Does nothing when double click
Eduard Kriegler:
50011: 02/11/28: Leon Softcore and Altera
51776: 03/01/21: Re: A Request: VHDL Source of a 32bit Floating Point ALU
Eduard Nikke:
60321: 03/09/10: LVDS in cyclone
Eduardo Augusto Bezerra:
14064: 99/01/11: Non-standard use of I/O blocks
14597: 99/02/05: VHDL synthesis
14625: 99/02/07: Re: VHDL synthesis
14633: 99/02/07: Re: VHDL synthesis
14732: 99/02/13: Synplify resource usage report for Virtex devices
14766: 99/02/16: Re: Synplify resource usage report for Virtex devices
14767: 99/02/16: Re: Synplify resource usage report for Virtex devices
14790: 99/02/17: Re: Synplify resource usage report for Virtex devices
14996: 99/03/02: Problems inferring RAM memory
15108: 99/03/07: Re: Problems inferring RAM memory
15224: 99/03/15: Seeking for data in an FPGA RAM
15671: 99/04/07: 8051 gate counting
15753: 99/04/12: Re: Does any one want to talk about Dynamic Configuration?
16369: 99/05/19: Re: Dual Port mem
16512: 99/05/26: Re: C to VHDL translator?
17353: 99/07/22: Looking for proceedings
17576: 99/08/11: Re: Java and XS40 board
18089: 99/09/29: Re: Performance of reprogrammable =?iso-8859-9?Q?FPGA=B4s=3F?=
18189: 99/10/06: 1ST IEEE LATIN-AMERICAN TEST WORKSHOP
18245: 99/10/09: Re: RAM in xilinx FPGAs.
19322: 99/12/14: CORE-2000 - Reconfigurable Computing Workshop
24281: 00/08/02: 8251A USART
24283: 00/08/02: Re: 8251A USART
24307: 00/08/03: Re: 8251A USART
24619: 00/08/15: Re: 8251 USART
24629: 00/08/15: Re: 8251 USART
24645: 00/08/16: Re: 8251 USART
24670: 00/08/16: Re: 8251 USART
27151: 00/11/13: Re: manchester decoder
27912: 00/12/14: Re: Verilog or VHDL
36577: 01/11/12: Jpeg 2000
Eduardo Sanchez:
1158: 95/05/08: workshop on evolvable hardware
Eduardo Wenzel Brião:
51801: 03/01/22: Partial Reconfiguration : Xapp290 Example
51949: 03/01/27: Re: Partial Reconfiguration : Xapp290 Example
53190: 03/03/05: Partial Reconfiguration : Modular Design Help
53287: 03/03/10: Partial Reconfigration:Active Module of MD
53390: 03/03/12: Modular Design: Dangerous warnings..
53582: 03/03/17: Modular Design:Fatal error issued by PAR
53643: 03/03/18: Modular Design: FATAL_ERROR
53656: 03/03/19: NGDBuild: LUT1 Error
53712: 03/03/20: Partial Reconfiguration: The use of BUS MACRO
53764: 03/03/21: Leonardo Spectrum: Synthesis without optimization
53917: 03/03/27: Modular Design: level of module hierarchy
53920: 03/03/27: Modular Design: level of module hierarchy
54195: 03/04/04: Modular Design: PAR error in sequential circuit
54381: 03/04/09: Bus Macros: Power supply
54382: 03/04/09: Modular Design: XAPP404
54422: 03/04/10: ngdbuild error: drivers and ilegal connections
54448: 03/04/10: Modular Design: last step to finish
59578: 03/08/22: Re: Partial Reconfiguration on Xilinx FPGA
EdV:
128163: 08/01/17: Re: effect of xray on fpga electronic circuits
142388: 09/08/08: Re: Peter Alfke
<edvenson@gmail.com>:
88116: 05/08/09: Re: Fast Recompilation of an XPS project
98422: 06/03/09: Re: EDK remote TCP debug
101549: 06/05/02: Re: EDK and SYSGEN
101610: 06/05/03: Re: EDK and SYSGEN
Edward:
21400: 00/03/22: How to solder FPGA in BGA package ?
30376: 01/04/04: QPSK phase rotator implementation in FPGA ?
30681: 01/04/23: Any good sources for digital rf processing ?
30699: 01/04/24: Re: Any good sources for digital rf processing ?
32094: 01/06/13: DQPSK encoding table.
32439: 01/06/26: QPSK signal processing.
33364: 01/07/24: Re: Soldering Ceramic BGA's
68484: 04/04/06: XPower: -tb switch
68486: 04/04/06: XPower: Post-Place and Route Simulation model
70286: 04/06/11: Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5
70325: 04/06/12: Megawizard Plugin and SDRAM controller
70338: 04/06/13: Re: Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5
Edward Buckley:
64805: 04/01/14: Microblaze simulation
Edward C. Schram:
2358: 95/11/22: Re: Device Programmer Selection
Edward Craig:
31905: 01/06/08: Re: looking for work
Edward K. Acosta:
1340: 95/06/02: Survey of FPGA
1342: 95/06/02: Re: ATMEL 6000 question
Edward L. Hepler:
16161: 99/05/06: Re: Fpga gates, PLD gates ASIC gates: Help us please.
17321: 99/07/20: Re: Solaris vs. NT
22722: 00/05/19: Re: 68k - core
26278: 00/10/10: Re: 68000 vhdl model
28895: 01/01/27: Leonardo -> Xilinx Alliance 3.1i
28896: 01/01/27: Re: Leonardo -> Xilinx Alliance 3.1i
Edward Lee:
8973: 98/02/10: Re: Free FPGA tools???
20988: 00/03/02: Re: JTAG Programmer & Windows 2000
20997: 00/03/02: Re: Bit Serial Arithmetic De-mystified : On-Line Arithmetic
21062: 00/03/05: Re: JTAG Programmer & Windows 2000
Edward Leventhal:
609: 95/01/18: Multiple FPGAs
655: 95/01/30: Inefficiency(?)
1135: 95/05/03: IOLOC or Other Xilinx Tools
2867: 96/02/20: Xilinx 8100 Series
2970: 96/03/07: Multiple FPGA Partitioning
3761: 96/07/26: Fault Tolerance With Programmable Logic
Edward Moore:
11926: 98/09/19: Re: sync or async SRAM?
11938: 98/09/20: Re: Xilinx Spartan vs. 4K series
12287: 98/10/08: Re: Degradation of results from Xilinx F1.3 -> F1.4 -> F1.5 (MORE INFO)
12454: 98/10/12: Re: Xilinx F1.5/FPGA Express wackiness
12456: 98/10/12: Re: Digital Sine Generator
12457: 98/10/12: Re: FPGA info..
12836: 98/11/01: Re: Schematic entry?
13006: 98/11/10: Re: placement&routing problems
13007: 98/11/10: Re: How to determine macro size in Xilinx Foundation?
13068: 98/11/14: Re: placement&routing problems
13071: 98/11/14: Re: placement&routing problems
13072: 98/11/14: Re: placement&routing problems
13711: 98/12/19: Re: Async Fifo Core or Macro for Xilinx FPGA
13716: 98/12/20: Re: Async Fifo Core or Macro for Xilinx FPGA
13998: 99/01/06: Re: Gamma correction in YUV space
14599: 99/02/06: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14619: 99/02/06: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14616: 99/02/06: Re: Synplify/Xilinx4085XLA question
16447: 99/05/22: IOB tristate register in Xilinx XLA devices
17036: 99/06/26: Major Exemplar Bug
17948: 99/09/18: Loadable arithmetic in Virtex
17951: 99/09/18: Virtex global set/reset
17955: 99/09/19: Re: Virtex global set/reset
17956: 99/09/19: Re: Loadable arithmetic in Virtex
17964: 99/09/19: Re: Loadable arithmetic in Virtex
18408: 99/10/23: Re: External Cloking of Altera MAX 7000S
35114: 01/09/21: Re: Virtex Clock Enable and Synplify
38663: 02/01/21: Re: DDR-Interface
45463: 02/07/24: Re: Clock-gating in Virtex-E parts
45684: 02/08/01: Re: Pipelined Multiplier Implemented in Slices in Virtex II
160201: 17/08/05: additional fpga forums
160204: 17/08/05: additional fpga forums
161411: 19/07/25: Re: New uses of FPGAs
161417: 19/07/29: Re: New uses of FPGAs
Edward Pickering:
11118: 98/07/20: Old Contace Information
11119: 98/07/20: Old Contace Information
11120: 98/07/20: Old Contace Information
Edward Wallington:
13003: 98/11/10: Affordable boundary scan (JTAG) interconnect testing software any
18985: 99/11/23: Anybody using Lucent OR3TP12?
19046: 99/11/25: Lucent: OR3TP12, Some work arounds that we have found.
Edward Watts:
95376: 06/01/22: Re: Virtual Pin in Xilinx ISE
Edwin:
26519: 00/10/18: Off Subject- FPGA Jobs Available
26545: 00/10/19: Very Lucrative FPGA Jobs
26547: 00/10/19: FPGA Designers Wanted!!!!!
Edwin Bland:
39580: 02/02/13: Re: Xilinx synthesis tools
40846: 02/03/16: Re: Block Ram
71011: 04/07/05: Re: Linux.
Edwin Grigorian:
9076: 98/02/18: Re: Walace tree???
12225: 98/10/05: RAM Implementation in Altera Flex10K100A
14825: 99/02/18: Re: P&R times for Altera10K200E and Virtex
14826: 99/02/18: Re: P&R times for Altera10K200E and Virtex
16302: 99/05/14: Re: Need Altera 10k Prototype bd
18874: 99/11/19: Re: Altera Files vho and sdo too big
19136: 99/12/01: Re: ALTERA EPC2 Configuration Help needed!
19143: 99/12/01: Re: ALTERA EPC2 Configuration Help needed!
Edwin Naroska:
7675: 97/10/02: Re: Wanted: cheap way to learn VHDL
9691: 98/03/31: Re: Verilog 2 VHDL
12438: 98/10/12: Re: Software tool
12506: 98/10/14: Re: VHDL Editor
12684: 98/10/23: Re: Need VHDL tools for Win NT/ Win 95
13767: 98/12/23: Re: VHDL books (seeking)
13768: 98/12/23: Re: [Question] How to make Random in VHDL
15160: 99/03/10: Re: VLSI Design on random number genrator
15940: 99/04/22: Re: VHDL compiler and simulator?
17512: 99/08/04: Re: looking for software
17575: 99/08/11: Re: PCI core
17585: 99/08/11: Re: UART
18001: 99/09/22: Re: No Subject
18121: 99/10/01: Re: Implementing a LFSH in Xilinx XC9500 series
18163: 99/10/04: Re: SDRAM&PCI controller
19506: 99/12/28: Re: HDL to graphic conversion
20106: 00/01/27: Re: microcontroller in vhdl
20432: 00/02/10: Re: Viterbi Dec. in VHDL (on Xilinx XC4000)
20958: 00/03/01: Re: Book recommendations?
21386: 00/03/21: Re: Beginner's Guide
21931: 00/04/07: Re: Any free design of 8051 in the net?
27233: 00/11/16: Re: Schematics & VHDL
32603: 01/07/02: Re: Converting character to integer in VHDL
32659: 01/07/04: Re: uart rs232? (for free)
33241: 01/07/20: Re: xilinx web pack problem
33434: 01/07/26: Re: Free VHDL cores - where?
34544: 01/08/29: Re: SmartMedia
35883: 01/10/22: Re: Verilog vs. VHDL
36350: 01/11/07: Re: Fifo books
36552: 01/11/12: Re: Interleaver and Reed Solomon Encoder example
36575: 01/11/12: Re: Hex numbers in VHDL
36797: 01/11/20: Re: Synthesis in Active-VHDL
48417: 02/10/17: Re: Xilinx microblaze vs. picoblaze
Edwin Pijpers:
34841: 01/09/11: Spartan configuration
Edwin Tsang:
789: 95/03/02: Re: Can I implement a digital PLL in an FPGA??
2661: 96/01/21: how to write place and route software
2670: 96/01/22: Re: Chosing VHDL or Verilog Does Have An Impact For U.S. Engineers
2749: 96/02/01: Re: Chosing VHDL or Verilog Does Have An Impact For U.S. Engineers
<edwin.gobain@gmail.com>:
135070: 08/09/12: ASIC Prototyping
<edwinpark@my-dejanews.com>:
14793: 99/02/17: Re: Anyone experience with Aptix?
14796: 99/02/17: P&R times for Altera10K200E and Virtex
15878: 99/04/18: Any good book suggestions
16004: 99/04/27: Re: FPGA and Virtex die size
EDYNet Web Design & More:
16821: 99/06/11: www.edy.net/jnonia
Edzel:
43002: 02/05/08: Eliminating Hierarchy in Xilinx XST
43072: 02/05/12: Re: Eliminating Hierarchy in Xilinx XST
43075: 02/05/13: Re: Eliminating Hierarchy in Xilinx XST
EE EE:
145153: 10/01/29: synthesizing a completely empty design for an FPGA to measure
ee_ether:
113013: 06/12/05: Spartan3 IBIS / Simulation questions
127066: 07/12/10: PCI Parallel port card for JTAG / programming?
131497: 08/04/23: Verilog state machines, latches, syntax and a bet!
140202: 09/05/03: High-speed signals crossing a split-ground
eeh:
88768: 05/08/27: Feedback signal cancellation algorithm
89982: 05/09/30: VHDL 2 dimension array
89990: 05/10/01: Re: VHDL 2 dimension array
eehinjor:
93717: 05/12/28: PCI interface on CYCLONE(ep1c6)
96537: 06/02/06: realize pci in fpga
96659: 06/02/08: Re: realize pci in fpga
96712: 06/02/09: Re: realize pci in fpga
96714: 06/02/09: Re: realize pci in fpga
eejsy:
109108: 06/09/20: Re: DDR2 Memory Controller : IOSTANDARD
109116: 06/09/20: Re: DDR2 Memory Controller : IOSTANDARD
eejw:
105454: 06/07/23: Microblaze: how to determine remainder after integer division
105532: 06/07/25: Re: Microblaze: how to determine remainder after integer division
117788: 07/04/10: System Generator pcore I/O performance results
117789: 07/04/10: Re: System Generator pcore I/O performance results
117840: 07/04/11: Re: System Generator pcore I/O performance results
117842: 07/04/11: Re: System Generator pcore I/O performance results
<eem3kc@gmail.com>:
104580: 06/06/30: Nu Horizon Xilinx 1500 fpga board
EEngineer:
105353: 06/07/20: Re: Virtex 4 ACE Compact Flash configuration problem
105355: 06/07/20: Re: Virtex 4 ACE Compact Flash configuration problem
105357: 06/07/20: Re: Virtex 4 ACE Compact Flash configuration problem
105358: 06/07/20: Re: Virtex 4 ACE Compact Flash configuration problem
105401: 06/07/21: Re: Virtex 4 ACE Compact Flash configuration problem
105475: 06/07/24: Re: Virtex 4 ACE Compact Flash configuration problem
105476: 06/07/24: Re: Virtex 4 ACE Compact Flash configuration problem
105477: 06/07/24: Re: Virtex 4 ACE Compact Flash configuration problem
105552: 06/07/25: Re: Virtex 4 ACE Compact Flash configuration problem
105576: 06/07/26: Re: Virtex 4 ACE Compact Flash configuration problem
105578: 06/07/26: Re: Virtex 4 ACE Compact Flash configuration problem
107466: 06/08/28: How to load the data off the FPGA to the PC?
107544: 06/08/29: Re: How to load the data off the FPGA to the PC?
115299: 07/02/06: generating VHDL code from Matlab code for DSP - wavelet image compression
115343: 07/02/07: Re: generating VHDL code from Matlab code for DSP - wavelet image compression
115436: 07/02/10: Re: generating VHDL code from Matlab code for DSP - wavelet image compression
121094: 07/06/25: Xilinx FPGA: "after 10ns" constraint
121097: 07/06/25: Re: Xilinx FPGA: "after 10ns" constraint
121099: 07/06/25: Re: Xilinx FPGA: "after 10ns" constraint
121104: 07/06/25: Re: Xilinx FPGA: "after 10ns" constraint
122675: 07/08/02: Download the contents of the FPGA's RAM block
122742: 07/08/06: Re: Download the contents of the FPGA's RAM block
122766: 07/08/06: Re: Download the contents of the FPGA's RAM block
122770: 07/08/06: Re: bidirectional pin
122777: 07/08/06: FPGA board connected to CMOS chip: ESD hazards?
122803: 07/08/07: Re: FPGA board connected to CMOS chip: ESD hazards?
123535: 07/08/29: Output signals not synchronized
123538: 07/08/29: Re: Output signals not synchronized
123572: 07/08/30: Re: Output signals not synchronized
123592: 07/08/30: Re: Output signals not synchronized
123613: 07/08/31: Re: Output signals not synchronized
126054: 07/11/13: Re: implementing MAC protocols on fpga
126113: 07/11/14: Re: Xilinx Virtex-II Newbie
126122: 07/11/14: Re: Xilinx Virtex-II Newbie
126123: 07/11/14: Re: Xilinx Virtex-II Newbie
126144: 07/11/15: Re: Xilinx Virtex-II Newbie
126524: 07/11/26: Re: ISE and Itanium
ees3dc:
153863: 12/06/14: Virtex 4 Cameralink DCM Limitation
158633: 16/02/15: Synplify Identify with Microsemi FPGAs
efim:
87610: 05/07/27: WEB Pack 7.1 and registry access
EFR:
136024: 08/10/28: XUPV2P & xps_tft controller
Eftychios Eftychiou:
37248: 01/12/04: Xilinx ISE 4.1 md0 md2 and ipad symbols not found for xc4005xl
egadget1:
131901: 08/05/06: Call VHDL module from Verilog
131903: 08/05/06: Re: Call VHDL module from Verilog
Egads:
54280: 03/04/07: Re: 2.5V switching regulator for Spartan 2
55444: 03/05/08: Re: Xilinx configuration flash/proms
58529: 03/07/25: XAPP058 SVF2XSVF converter problems
64718: 04/01/12: Re: iMPACT error : Done did not go high.
64852: 04/01/15: Re: 1.8v SpartanIIE
Egbert Molenkamp:
22126: 00/04/26: Re: xilinx --> altera vhdl
35260: 01/09/27: Re: Maxplus waveform simulations
54238: 03/04/05: Re: anyone has doc on Viewsim commands? Thanks!
57000: 03/06/20: Re: Quartus bug or wrong VHDL?
59258: 03/08/13: Re: Error please Help
65490: 04/01/30: Re: asynchronous counter an Xilinx FPGA for a newbie
82881: 05/04/19: Re: Strange FPGA problem
Egon Bild:
7791: 97/10/15: Download Cable for In-System programming of LATTICE ispLSI, ....
7800: 97/10/16: Re: Download Cable for In-System programming of LATTICE ispLSI, ....
EH-2004:
63251: 03/11/18: CFP: EH-2004 Second Call for Abstracts
65367: 04/01/26: CFP: Evolvable Hardware 2004
68765: 04/04/16: EH-2004 Registration
<ehiebert@my-deja.com>:
17143: 99/07/02: Re: Synplify problem - is it just me?
<ehliar@isy.liu.se>:
142972: 09/09/11: Re: Does ModelSim or any simulator software have a function similar
ehml:
45729: 02/08/02: Re: spiral / waterfall /watersluice : Which are your methods?
<eholbrook@austin.rr.com>:
57551: 03/07/02: Looking for DIMM format FPGA board
Ehsan:
137365: 09/01/11: ISE Simulator and State Machines
137456: 09/01/17: Using memory blocks generated by CoreGen
137469: 09/01/18: Re: Using memory blocks generated by CoreGen
137851: 09/01/31: Heavily pipelined design
137861: 09/02/01: Re: Heavily pipelined design
137862: 09/02/01: Re: Heavily pipelined design
138358: 09/02/17: Troubleshooting fpga design
138411: 09/02/20: Re: Troubleshooting fpga design
138419: 09/02/20: Re: Troubleshooting fpga design
139571: 09/04/03: Chipscope problem
139577: 09/04/04: Re: Chipscope problem
139585: 09/04/05: Re: Chipscope problem
139587: 09/04/05: Re: Chipscope problem
139635: 09/04/07: Re: Chipscope problem
139680: 09/04/08: Re: Chipscope debug in EDK
147515: 10/04/29: Large Fanout
148483: 10/07/27: All Digital PLL
148490: 10/07/27: Re: All Digital PLL
156153: 13/12/23: Use of latches in FSMs
ehsjr:
131952: 08/05/08: Re: ANNC: FPGA Design Software Webcast
Ehud Reshef:
3578: 96/06/30: Using XC4000 Primary Clocks from Verilog
8865: 98/02/03: CardBus Core
EiblmayrA:
3174: 96/04/18: PLD-Forum der Design & Elektronik
Eileen Haldeman:
19334: 99/12/14: System Engineering positions
19622: 00/01/04: synthesis opportunities
eiliot schei:
73965: 04/10/01: Re: System Generator.
Eion Magen:
18488: 99/10/27: Re: Pc system requirment for Foundation Series
Eircom:
22696: 00/05/18: Help with macrocell , explain it to me
Eirik Esp:
17425: 99/07/27: NRZ Deserializing in Virtex
22923: 00/06/02: Virtex Block Select RAM Timing Problem
22924: 00/06/02: Re: Virtex Block Select RAM Timing Problem
23274: 00/06/20: Powerup problem to 9500XL part @ -40 deg
39534: 02/02/12: Re: chipscope "disable JTAG clock BUFG insertion"
Eirik Seljelid:
72070: 04/08/07: ABEL support for legacy chips
72085: 04/08/08: Re: ABEL support for legacy chips
72139: 04/08/10: Re: ABEL support for legacy chips
72141: 04/08/10: Re: ABEL support for legacy chips
72185: 04/08/11: Re: ABEL support for legacy chips
72418: 04/08/18: Re: ABEL support for legacy chips
ejob:
11736: 98/09/04: Architect Postions @ Lucent Technologies
11809: 98/09/10: jobs @ lucent technologies
11968: 98/09/21: vlsi / fpga jobs @ lucent
12134: 98/09/30: jobs @ lucent
12756: 98/10/28: jobs @ Lucent
12971: 98/11/08: employment @ lucent <nj>
13551: 98/12/09: PhDs Needed @ Lucent <NJ>
13864: 98/12/29: Arch Jobs @ Lucent <NJ>
14207: 99/01/19: VLSI Jobs @ Lucent <NJ>
Eka:
132458: 08/05/27: Need comparison table about Xilinx ISE WebPack 10.1i vs ISE
Eka From Indonesia:
101072: 06/04/25: SPARTAN3E SK LCD
102956: 06/05/23: Reading from and Writing to J3 Intel StrataFlash NOR FlashPROM on Spartan3E SK
103175: 06/05/26: Re: Reading from and Writing to J3 Intel StrataFlash NOR FlashPROM on Spartan3E SK
Ekalavya Nishada:
61054: 03/09/26: FPGA implementation of a lexer and parser - feasible?
61084: 03/09/27: Re: FPGA implementation of a lexer and parser - feasible?
61085: 03/09/27: Re: FPGA implementation of a lexer and parser - feasible?
ekavirsrikanth@gmail.com:
111132: 06/10/30: prob regarding Bitgen failed while gen prog file xilinx ise 7.1i
111434: 06/11/02: regardign signal assinment statement............................
111917: 06/11/13: regarding changing serial data out to LVDS form
113153: 06/12/06: regarding -ve slack while doing post PAR timing analysis
113240: 06/12/08: regarding -ve slack while doing post PAR timing analysis
115578: 07/02/13: regarding VREF and VCCO and GCLK in virtex 2 pro fpga
115766: 07/02/19: configuring in slave serial mode with serial platform PROM
121589: 07/07/09: regarding post place and route timing simulation steps........
121649: 07/07/10: Re: regarding post place and route timing simulation steps........
121879: 07/07/13: DCM CLK driving load problem
122086: 07/07/18: regarding specifying clock as internal signal in chipscope
122966: 07/08/12: regarding the clock issues in the fpga...
123001: 07/08/13: Re: regarding the clock issues in the fpga...
133714: 08/07/10: multicyle and false path in FPGA Design
133979: 08/07/21: why holdtime is not considerd for Tclkmax calculation
135149: 08/09/17: interview questions ........
135390: 08/09/29: if data moves faster faster than the Clock....
EKC:
13416: 98/12/01: XILINX FPGA reaches GHz speeds
13612: 98/12/12: FPGA Data compression
14273: 99/01/22: Foundation V3.1 VHDL synthesis
14799: 99/02/17: Xilinx Foundation V1.5
16959: 99/06/19: Vendor Market Share
17065: 99/06/28: FGPA Servo Motor Controller
17342: 99/07/21: Re: Dongle problems.
22693: 00/05/18: Re: Do you know xilinx FPGAs well?
23301: 00/06/21: 500 million transistor FPGA's
23304: 00/06/22: FPGAs for Bioinformatics accelerators
23626: 00/07/03: Altera Ships Largest PLD
23966: 00/07/18: FPGA Conferences
26337: 00/10/12: Re: Xilinx, Altera stocks take dumps!
28893: 01/01/27: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip multiprocessor!
29052: 01/02/04: FPGA Conferences
29222: 01/02/10: VHDL PID
eKo1:
109417: 06/09/26: Re: An algorithm with Minimum vertex cover without considering its performance
eko_mies:
44812: 02/07/02: VHDL (IP) to PC/LPT ?
<ekrads@gmail.com>:
104119: 06/06/19: Re: Newbie to FPGA
104332: 06/06/23: Re: stimulus for FPGA
Ekrem Aras:
33154: 01/07/18: Re: Xilinx WebPACK - ROM
<ekuria01@kepler.poly.edu>:
13742: 98/12/21: Starting with FPGAs
13911: 99/01/02: Re: program flow chart to state machine ?
13984: 99/01/06: which FPGA to choose ?
15813: 99/04/15: Some FPGA questions
15828: 99/04/16: Intelliflow question: ORD files?
15871: 99/04/17: Re: Some FPGA questions
el cintura partida:
55645: 03/05/14: Error in the Simulation with Xilinx ISE 4.1.
El-Mehdi Taileb:
114417: 07/01/15: ISE 9.1i and partial reconfiguration
114552: 07/01/19: Re: Xilinx website login problems
114554: 07/01/19: Re: ISE Simulator Error 222: SuSE 10.1 Linux
114626: 07/01/21: Re: ISE 9.1i and partial reconfiguration
115760: 07/02/20: MIG 1.6 on ISE-9.1i-SP1
115908: 07/02/24: MIG 1.6 on ISE9.1i
el231bat:
83117: 05/04/23: Re: Time Borrowing
83336: 05/04/27: LM4550 AC97 Codec on the XUP board
83566: 05/05/03: Re: LM4550 Audio Codec
87298: 05/07/20: Re: setting XUP new board
el_boricua:
88083: 05/08/08: Incorporating Cores to the Virtex2Pro PLB
88113: 05/08/09: Re: Incorporating Cores to the Virtex2Pro PLB
88163: 05/08/10: EDK and ISE questions
88257: 05/08/13: EDK IPIF + User Core
88671: 05/08/24: Single PPC with DES on V2P
88687: 05/08/25: Re: Single PPC with DES on V2P
88705: 05/08/25: Re: Single PPC with DES on V2P
88707: 05/08/25: DMA issues with IPIF on V2P
elcielo:
86921: 05/07/09: re:Spartan-3E, ISE 7.1 some issues - solved (BUFG insertion pro
Elder:
154438: 12/11/01: Altera FPGA: EP4CE10 as drop-in replacement for EP4CE15 (F17)
Elder Costa:
75725: 04/11/13: Re: Spartan3 Block RAM from WebPACK
75836: 04/11/16: Re: Spartan3 Block RAM from WebPACK
75976: 04/11/21: Re: 18x18 Multipliers - Spartan III
76755: 04/12/10: Lookup table simulation problems
76771: 04/12/10: Re: Lookup table simulation problems
76772: 04/12/10: Re: Lookup table simulation problems
76776: 04/12/10: Inferring dual port RAMs with different bus widths.
76824: 04/12/13: Re: Inferring dual port RAMs with different bus widths.
77141: 04/12/25: Re: Clock Synchronization
78040: 05/01/23: Re: ModelSim & Constant
79009: 05/02/11: ISE versus Modelsim inconsistency and attribute definition
79016: 05/02/11: Re: ISE versus Modelsim inconsistency and attribute definition
79049: 05/02/11: Re: ISE versus Modelsim inconsistency and attribute definition
79223: 05/02/15: Re: ISE versus Modelsim inconsistency and attribute definition
86970: 05/07/11: Connecting TigerSharc TS201 EzKIT to PCI with Spartan 3
148548: 10/07/31: Spartan 3E: SPI programming through JTAG
148549: 10/07/31: Re: Spartan 3E: SPI programming through JTAG
Elder V Costa:
12121: 98/09/30: Xilinx XC95xx JTAG program for DOS
13383: 98/11/30: Archiving Xilinx Foundation Projects
16358: 99/05/18: Re: Glue logic
16384: 99/05/19: Xilinx Foundation Archiving
16528: 99/05/26: Re: Synthesis problem
16577: 99/05/28: Re: Synthesis problem
electrin:
157939: 15/05/18: Clock triggered FSM
electro:
92114: 05/11/22: Re: Verilog Editor.
101346: 06/04/29: Re: Picoblaze C Compiler
electrocoder:
151352: 11/03/27: fpga express 3.6
151358: 11/03/27: Re: fpga express 3.6
Electron:
55738: 03/05/18: Interfacing cpld with eeprom, energy metering ic, real time clock
electron man:
69884: 04/05/23: Re: OT: Electronics learner kit?
69885: 04/05/23: is RAMbus going to resurect itself as another DDR2 format?
electron-man:
36114: 01/10/30: Re: Firewire chipset
ElectronicDesignNet:
110251: 06/10/12: Re: New Electronic Design Web site
110302: 06/10/13: Re: New Electronic Design Web site
<electronics_designer@hotmail.com>:
92385: 05/11/29: Re: Looking for manual for logic analyzer module 16750A.
92387: 05/11/29: Merging the ML403 refence design and the GSRD design
Elektro:
78009: 05/01/22: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
78075: 05/01/24: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
78145: 05/01/25: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
78159: 05/01/25: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
78451: 05/02/01: Input logic level on Spartan 3?
80761: 05/03/11: Re: low speed FIR filter in FPGA
81986: 05/04/05: Book?
81990: 05/04/05: Re: Book?
82205: 05/04/08: PicoBlaze JTAG Program Loader problems
82224: 05/04/08: Re: PicoBlaze JTAG Program Loader problems
82247: 05/04/09: Re: PicoBlaze JTAG Program Loader problems
82344: 05/04/11: Re: lcd controller - how to realize it?
82346: 05/04/11: Re: lcd controller - how to realize it?
86848: 05/07/07: Bit serial, book, other info???
86904: 05/07/08: Re: Bit serial, book, other info???
<elen>:
151010: 11/02/28: Re: How to change the font size in text editor of modelsim
elena:
105883: 06/08/02: USB application on ML40X boards
elenappli:
156646: 14/05/22: Signal Integrity Failure on Custom FPGA board
Eleonore Bereau:
53919: 03/03/27: constant on Maxplus2
elesser:
103789: 06/06/11: from VHDL to FPGA
103798: 06/06/12: Re: from VHDL to FPGA
103814: 06/06/12: Re: from VHDL to FPGA
<elf_ster@hotmail.com>:
96933: 06/02/13: Re: spartan-3e starter kit
112774: 06/11/28: Re: Xilinx XST Incremental Design Change
112875: 06/11/30: Re: Hardware in the loop simulation for Altera design
Elftmann:
23039: 00/06/09: Re: Readout of an FPGA?
23040: 00/06/09: Re: TTL device Libraries
23242: 00/06/18: Re: Hand soldering a PQ208 - It looks tough to do.
23424: 00/06/24: Re: Powerup problem to 9500XL part @ -40 deg
24819: 00/08/19: Re: Permanently programming FPGAs
24823: 00/08/19: Re: Permanently programming FPGAs
24825: 00/08/19: Re: Permanently programming FPGAs
24845: 00/08/20: Re: Metastability and antifuze
24854: 00/08/20: Re: Metastability and antifuze
25122: 00/08/26: Re: Metastability and antifuze
25128: 00/08/26: Re: Metastability and antifuze
25130: 00/08/26: Re: Why Aren't Anti-Fuse FPGAs The Biggest FPGAs In The World?
25277: 00/09/04: Re: Balls!
Eli:
147414: 10/04/26: ISE tools not detecting IOSTANDARD conflicts within bank
147529: 10/04/30: Re: ISE tools not detecting IOSTANDARD conflicts within bank
Eli Bendersky:
107051: 06/08/23: Style of coding complex logic (particularly state machines)
107071: 06/08/24: Re: Style of coding complex logic (particularly state machines)
107166: 06/08/24: Re: Style of coding complex logic (particularly state machines)
107392: 06/08/27: Re: Style of coding complex logic (particularly state machines)
107475: 06/08/28: Re: Style of coding complex logic (particularly state machines)
109752: 06/10/05: An implementation of a clean reset signal
109834: 06/10/05: Re: An implementation of a clean reset signal
110273: 06/10/13: Re: An implementation of a clean reset signal
110685: 06/10/19: Re: An implementation of a clean reset signal
111872: 06/11/12: Re: SPI module in FPGA
117557: 07/04/03: Re: RFC: VHDL testbench enhancements
119472: 07/05/21: Filtering the FPGA reset signal
119487: 07/05/21: Re: Filtering the FPGA reset signal
124091: 07/09/12: Re: Good VHDL reference?
124900: 07/10/10: Re: Basic VHDL Development kit
126514: 07/11/26: Re: Hook open drain "power good" to nSTATUS or nCONFIG?
127793: 08/01/08: Real examples of metastability causing bugs
127805: 08/01/08: Re: Real examples of metastability causing bugs
127829: 08/01/08: Re: Real examples of metastability causing bugs
127830: 08/01/08: Re: Real examples of metastability causing bugs
127831: 08/01/08: Re: Real examples of metastability causing bugs
128222: 08/01/18: Re: How is FIFO implemented in FPGA and ASIC?
Eli Billauer:
100595: 06/04/12: Published Verilog code: Timing improvement and FWFT FIFOs
122713: 07/08/04: SDR SDRAM controller for Xilinx Spartan-3E
122715: 07/08/04: Re: SDR SDRAM controller for Xilinx Spartan-3E
122790: 07/08/07: Re: SDR SDRAM controller for Xilinx Spartan-3E
Eli Hughes:
90213: 05/10/06: Xilinx PLB IPIF Master
90260: 05/10/07: Re: Xilinx PLB IPIF Master
90273: 05/10/07: PowerPC interrupt latency
90329: 05/10/10: Xilinx IPIF PLB Master Update
90386: 05/10/11: Re: Question regarding FPGA startup ROMs
90446: 05/10/13: Re: Simulink to hdl conversion
90489: 05/10/14: Re: Help me
90749: 05/10/20: Re: to write the driver for my own ip core
91146: 05/10/31: Re: SystemACE parts wanted
91161: 05/10/31: Re: Spartan-3E starter kit
91167: 05/10/31: Re: SystemACE parts wanted
91171: 05/10/31: Re: Spartan-3E starter kit
91200: 05/11/01: Thank-you Xilinx!
91245: 05/11/02: Re: differential clock in EDK
91370: 05/11/04: Re: ChipScope and Spartan-3 Starter Kit (DO-SPAR3-DK)
91377: 05/11/04: Re: icarus verilog
91379: 05/11/04: Re: Actel SoftARM IP core generator tools finally available !!!
91381: 05/11/04: Re: ChipScope and Spartan-3 Starter Kit (DO-SPAR3-DK)
91457: 05/11/07: Re: Spartan-3E starter kit
91458: 05/11/07: Xilinx Package/Logic Options
91481: 05/11/07: Verilog Editor.
91483: 05/11/07: Re: Verilog Editor.
91646: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
91663: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
91761: 05/11/11: Re: FPGA KIT recommendation
92543: 05/12/01: Re: Any fpga tutorials online?
92708: 05/12/05: Re: Tip: Spotlight (OS X) indexing of VHDL files
93287: 05/12/19: Re: where can i get a release copy of ISE 8i?
95070: 06/01/20: Actel Fusion
94161: 06/01/06: FPGA -> ASIC`
94271: 06/01/09: Re: Programming Xilinx PowerPC
94845: 06/01/18: EDK 8.1
95071: 06/01/20: First Impressions of Actel Fusion?
95408: 06/01/23: Re: Reconfigurable Array of Array
95581: 06/01/24: Re: help:dual-edge flip-flop possible using Verilog?
95698: 06/01/25: Re: open source fpga programmer programs
95718: 06/01/25: Re: open source fpga programmer programs
95826: 06/01/26: Re: open source fpga programmer programs
95696: 06/01/25: Re: Spartan-3 Starter Board
98588: 06/03/13: Re: Soldering SMT/BGA
98687: 06/03/14: Re: Soldering SMT/BGA
98688: 06/03/14: Re: Soldering SMT/BGA
98863: 06/03/17: Re: EDK : PPC405 Interrupt question
98869: 06/03/17: Re: EDK : PPC405 Interrupt question
99889: 06/03/30: Xilinx Schematic Entry
100088: 06/04/03: Spartan 3E SPI Programming
100092: 06/04/03: Re: Spartan 3E SPI Programming
100146: 06/04/04: System Ace
100313: 06/04/06: Re: XUPv"P DDR failure log
100376: 06/04/07: Re: Accessing compact flash?????????
100661: 06/04/14: Re: C# and Spartan 3 Starter Kit
100792: 06/04/18: FPGA + FTDI
100793: 06/04/18: Re: FPGA + MAC board?
101016: 06/04/24: ISE 8.1 Sub module Synthesis
101450: 06/05/01: ISE 8.1 Comment Bug, Very hideous
101452: 06/05/01: Re: ISE 8.1 Comment Bug, Very hideous
101466: 06/05/01: Re: ISE 8.1 Comment Bug, Very hideous
101609: 06/05/03: Re: Interfacing Spartan 3 board to PC parallel port??
101682: 06/05/04: Re: New To FPGA, Program question
102075: 06/05/10: CoolRunner XPLA3 getting axed?
102077: 06/05/10: Altera Equiv.
102082: 06/05/10: Re: CoolRunner XPLA3 getting axed?
102099: 06/05/10: Re: CoolRunner XPLA3 getting axed?
102105: 06/05/10: Re: CoolRunner XPLA3 getting axed?
102236: 06/05/12: Re: JTAG tutorial
102533: 06/05/17: CoolRunner Pins during Programming
102638: 06/05/18: FPGA Configuration Question
104444: 06/06/27: Re: XilFatFS and CF...
104764: 06/07/05: Re: PLB master without xilinx ipif
104975: 06/07/11: Re: Development Boards -Your chance to suggest features
105006: 06/07/11: Re: Development Boards -Your chance to suggest features
105095: 06/07/13: Re: Can't get my Verilog Peripheral to import into XPS! Any tricks?
105127: 06/07/14: Re: OPB or FSL?
105183: 06/07/17: Re: Where are you heading?
105571: 06/07/26: Re: uClinux on Virtex-4 Mini-Module
107605: 06/08/30: Xilinx Spartan-3A
108694: 06/09/15: Fusion
108711: 06/09/15: Re: Fusion
108916: 06/09/19: Re: XPLA3 going obsolete?
109772: 06/10/05: This is great news
110232: 06/10/12: VirTex 4 mini Module
114365: 07/01/12: Re: xc3sprog
115962: 07/02/26: Re: Spartan-3AN
117663: 07/04/06: Icarus Verilog
118041: 07/04/16: Re: PLB Master
118078: 07/04/17: Re: PLB Master
118085: 07/04/17: Re: PLB Master
118090: 07/04/17: 80000 Bit Shift Register
118092: 07/04/17: 80000 Bit Shift Register - The Code
118111: 07/04/17: Re: 80000 Bit Shift Register
118140: 07/04/18: Re: 80000 Bit Shift Register
118142: 07/04/18: Re: Seeking the solutions of high speed interconnection for the long
118293: 07/04/23: Re: Summer with fpgas
118306: 07/04/23: Re: Summer with fpgas
118346: 07/04/24: Re: 80000 Bit Shift Register
118347: 07/04/24: Re: DARNAW! - PGA Style FPGA Module
120246: 07/06/04: Re: any experiences concerning xup and digilent inc.?
125824: 07/11/06: Re: not totally repulsive
Eli Keren:
13788: 98/12/28: Re: 22V10 Metastability - help please
13889: 98/12/31: Re: program flow chart to state machine ?
14336: 99/01/26: Re: FPGA architecture
15106: 99/03/07: Re: ALTERA pin assignment
15243: 99/03/16: Re: Clock multiplier
15789: 99/04/14: Re: FIFO
16037: 99/04/29: Re: High speed PLL inside FPGA
16038: 99/04/29: Re: High speed PLL inside FPGA
16039: 99/04/29: Re: Double Port ram for Altera EPF10K20
16093: 99/05/02: Re: 10KE dual port RAM help ?
16656: 99/06/01: CONTROLLED IMPEDANCE SOFTWARE
<eli.billauer@gmail.com>:
118984: 07/05/08: SelectMap or serial: How does the PROM know?
118996: 07/05/09: Re: SelectMap or serial: How does the PROM know?
123186: 07/08/19: Xilinx / ISE multi-cycle path constraint pitfall
123195: 07/08/19: Re: Xilinx / ISE multi-cycle path constraint pitfall
123322: 07/08/23: Re: Synthesizing fixed_pkg in ISE 9.2
123435: 07/08/28: Re: Xilinx / ISE multi-cycle path constraint pitfall
123505: 07/08/29: Re: Xilinx / ISE multi-cycle path constraint pitfall
123554: 07/08/30: Re: Xilinx / ISE multi-cycle path constraint pitfall
123584: 07/08/30: Re: Xilinx / ISE multi-cycle path constraint pitfall
123657: 07/08/31: Re: Xilinx / ISE multi-cycle path constraint pitfall
128696: 08/02/04: A video tutorial: The Xilinx FPGA Editor
128736: 08/02/05: Re: A video tutorial: The Xilinx FPGA Editor
eliben:
123818: 07/09/05: high bandwitch ethernet communication
123852: 07/09/06: Re: high bandwitch ethernet communication
123853: 07/09/06: Re: high bandwitch ethernet communication
123866: 07/09/06: Re: high bandwitch ethernet communication
123892: 07/09/06: Re: high bandwitch ethernet communication
123925: 07/09/07: Re: high bandwitch ethernet communication
123948: 07/09/07: Re: high bandwitch ethernet communication
123964: 07/09/08: Re: high bandwitch ethernet communication
<eliben@gmail.com>:
75025: 04/10/25: initializing custom memory with .mif (or .hex) in Quartus 3
75085: 04/10/26: inefficient mux synthesis in quartus
75119: 04/10/26: Re: inefficient mux synthesis in quartus
75120: 04/10/26: Re: inefficient mux synthesis in quartus
77011: 04/12/19: Using low-core-voltage devices in industrial applications
<eliintertel@gmail.com>:
159258: 16/09/12: Re: Ob Screen Display from video coming from OV7670
Elinore:
79057: 05/02/12: 2 microblaze access same BRAM ?
79099: 05/02/14: Re: 2 microblaze access same BRAM ?
79235: 05/02/15: Re: 2 microblaze access same BRAM ?
79281: 05/02/16: Re: 2 microblaze access same BRAM ?
79312: 05/02/17: Re: 2 microblaze access same BRAM ?
79332: 05/02/17: Re: thread programming support in EDK?
<elinore2005@yahoo.fr>:
87164: 05/07/18: setting XUP new board
87202: 05/07/19: Re: setting XUP new board
Eliot Blennerhassett:
2397: 95/11/28: Re: NeoCAD and AT&T vs. Xilinx
3081: 96/03/28: Re: sigma delta analog to digital conversion
Eliot Friedman:
23499: 00/06/27: Porting C to FPGA
Elizabeth D Rather:
137063: 08/12/21: Re: Bit width in CPU cores
137076: 08/12/21: Re: Bit width in CPU cores
138983: 09/03/17: Re: Zero operand CPUs
139171: 09/03/22: Re: Re Zero operand CPUs
151797: 11/05/18: Re: J1 forth processor in FPGA - possibility of interactive work?
Elizabeth D. Rather:
39046: 02/01/30: Re: MSP430 + Xilinx via JTAG
39282: 02/02/05: Re: MSP430 + Xilinx via JTAG
155056: 13/04/04: Re: MISC - Stack Based vs. Register Based
155273: 13/06/20: Re: New soft processor core paper publisher?
Ellen Sentovich:
1045: 95/04/20: Freeware Was: $40 Million For NeoCAD & A New FPGA Synthesis Tool
Elling Diesen:
90021: 05/10/03: RLDRAM-II controller - Read problem
94183: 06/01/07: Re: Xilinx DCM
Elliot Mackenzie:
45719: 02/08/02: Xilinx2.1i/Celoxica DK1.1 implementation error
45767: 02/08/05: Re: Xilinx2.1i/Celoxica DK1.1 implementation error
Elliot Schei:
70298: 04/06/11: Re: example designs for Xilinx System Generator ?
71956: 04/08/04: Re: Best tool(s) for filter float->fixed->VHDL flow?
71959: 04/08/04: Re: Matlab/Simulink - System Generator HDL Co-Simulation
Elliot Waingold:
5292: 97/02/04: HELP: Signed Arithmetic in Behavioral Verilog
Ellis Easley:
13359: 98/11/30: Logical Devices ALLPRO diagnostics
Elmar Dukek:
37641: 01/12/18: Atmel IDS 7.5 and also older Versions do not work with Windows XP
Elmar Haneke:
26786: 00/10/29: Re: Fpga vs. ASIC
Elmar Weber:
112285: 06/11/19: Virtex-4 DDR RAM Usage (with VHDL)
Elmo:
75996: 04/11/22: DDR SDRAM with Xilinx Virtex 2 on self designed PCB
75999: 04/11/22: Re: DDR SDRAM with Xilinx Virtex 2 on self designed PCB
Elmo Fuchs:
111016: 06/10/27: Xilinx Virtex-4 Clock Multiplexer Inputs
111136: 06/10/30: clock multiplexor device
<elmo1@rocketmail.com>:
6488: 97/05/28: World Weather Database
<elmoties@hotmail.com>:
28558: 01/01/17: FSM encoding
<elmousa@my-dejanews.com>:
12243: 98/10/06: REQ:An FPGA with automation programming tool
12261: 98/10/07: Re: REQ:An FPGA with automation programming tool
12262: 98/10/07: Re: REQ:An FPGA with automation programming tool
elr:
116780: 07/03/17: Eval board advice
elraymonds:
157957: 15/06/04: Re: Free timing diagram drawing software
Elron Osafat:
13084: 98/11/15: Modifying Disk serial number in boot sector....anyone have any problems with it?
<elshoukry@gmail.com>:
117898: 07/04/12: Back annotating to RTL
ElVale:
143659: 09/10/20: Dealing with SPI ADC timings
143660: 09/10/20: Re: Dealing with SPI ADC timings
143673: 09/10/20: Re: Handwritten recognition using FPGA
143674: 09/10/20: Re: Teammates, interested?
"elvira catherina":
30728: 01/04/26: <no subject>
31367: 01/05/21: <no subject>
<elvis@dcs.rhbnc.ac.uk>:
6587: 97/06/04: Ripp10 Board
Elya Kapelyan:
15340: 99/03/19: Re: FPGA Express FSM Synthesis Concern
<elynum@my-deja.com>:
19425: 99/12/21: fpga cost
19456: 99/12/22: XC4000E
19537: 99/12/29: xess board
19625: 00/01/05: timing diagrams
19763: 00/01/11: Re: Lucent Orca designs
19802: 00/01/12: Lattice
19827: 00/01/13: fpga board
19835: 00/01/13: Re: Lattice
19864: 00/01/14: Re: Lattice
20318: 00/02/04: Re: Which is the best HDL book ?
20486: 00/02/11: xilinx
20492: 00/02/11: fpga
20493: 00/02/11: Re: xilinx
20604: 00/02/16: Re: xilinx
21838: 00/04/03: Re: Xilinx student edition, version 1.5
21847: 00/04/04: Re: Xilinx student edition, version 1.5
22551: 00/05/11: Re: Xilinx fpga board schematics?
25041: 00/08/24: fpga programmed by microcontroller
ELYUMA:
17414: 99/07/26: Interesting Links
EM:
135336: 08/09/26: Does XST support global signals?
135549: 08/10/07: Re: Does XST support global signals?
<email.crj@gmail.com>:
158823: 16/04/21: VHDL Obfuscators, the Good, the Bad, and the Ugly
<email@inter.net>:
18892: 99/11/19: Re: implementing TCP/IP on PLD
<email_address@message.end>:
51875: 03/01/24: Expansion for Cypress Demo Board
56256: 03/06/01: Need help with Xilinx ISE
56259: 03/06/01: Re: Need help with Xilinx ISE
56316: 03/06/03: Re: Need help with Xilinx ISE
56318: 03/06/03: Re: Need help with Xilinx ISE
58159: 03/07/16: Xilinx XST - how to create an EDIF?
58606: 03/07/28: Re: xilinx programing interface
58607: 03/07/28: Re: xilinx programing interface
<emailbogsuv@gmail.com>:
158630: 16/02/10: EPM240T100C5N, LM2596, USB Blaster.
Eman:
63084: 03/11/13: getting started in FPGA
Emanuel:
Emanuel Fontes:
1693: 95/08/16: Email Address of Xilinx
Emanuel Machado:
30217: 01/03/28: JTAG Chain problem and Altera -- has anyone seen this before?
97509: 06/02/23: project validation: best procedures?
emanuel stiebler:
15315: 99/03/18: Re: How can I improve an adder?
15382: 99/03/21: Re: From VHDL to FPGA?
15396: 99/03/22: Re: From VHDL to FPGA?
25281: 00/09/04: Re: Balls!
27934: 00/12/15: Re: FPGA starter kit
32908: 01/07/11: Re: 8031 microcontroller on FPGA development board :-)
32993: 01/07/14: Re: Design entry
33662: 01/08/01: spartan & atmel eeproms
35010: 01/09/17: Re: Virtex-2 availability
35235: 01/09/26: Re: Spartan-IIE?
39116: 02/01/31: Re: Intel vs. AMD
40072: 02/02/26: microblaze
40103: 02/02/27: scsi, ip, spartanII, vhdl
40113: 02/02/27: Re: microblaze
40193: 02/03/01: Re: microblaze
40324: 02/03/05: Re: exceeding 2GB limits in xilinx
40842: 02/03/16: Re: FPGA tools and Win2000 - problems
40881: 02/03/17: Re: FPGA tools and Win2000 - problems
41058: 02/03/20: spartan 2e, 5V i/o
41106: 02/03/20: Re: spartan 2e, 5V i/o
41311: 02/03/25: Re: Xilinx 4.2i not working on my design
42588: 02/04/28: Re: SpartanII design considerations...
42718: 02/05/01: usb 2.0 on FPGAs
42778: 02/05/02: Re: Availability of XC2S150E-6FG456I
42841: 02/05/04: Re: Xilinx MicroBlaze, Opinion?
43101: 02/05/13: 50 mA sink
44470: 02/06/20: Re: 5V tolerance
44999: 02/07/09: Re: Routing Virtex-II 256 pin BGA on 4 layers
45247: 02/07/17: Re: I would like to know how to develop a MCU.
45615: 02/07/29: xilinx ISE 4.2, xst, cpld 95144xl, tristate
45677: 02/07/31: Re: xilinx ISE 4.2, xst, cpld 95144xl, tristate
46242: 02/08/22: Re: onboard reconfiguration of Xilinx FPGA
47067: 02/09/16: Re: Virtex II packaging, why no QFP?
47224: 02/09/20: Re: Xilinx ISE5.1 and Windows NT
47225: 02/09/20: Re: Xilinx ISE5.1 and Windows NT
48020: 02/10/09: Re: USB2 in FPGA?
48250: 02/10/14: Xilinx microblaze vs. picoblaze
48278: 02/10/15: Re: Xilinx microblaze vs. picoblaze
48279: 02/10/15: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48290: 02/10/15: Re: Xilinx microblaze vs. picoblaze
49282: 02/11/07: Re: Instruction sets to implement instruction sets
50189: 02/12/04: Re: ISA bus VGA
51579: 03/01/16: Re: 200K gates FPGA for GPU
51580: 03/01/16: Re: 200K gates FPGA for GPU
55204: 03/04/30: Re: Any experience (good or bad) with Northwest Logic PCI core?
55394: 03/05/06: Re: use of DRAM as massive FIFO
56002: 03/05/26: xilinix edk 3.2 and webpack
56235: 03/05/31: DES-encrypt, Spartan3, was Re: FPGA's an Flash
56246: 03/06/01: Re: DES-encrypt, Spartan3, was Re: FPGA's an Flash
57367: 03/06/28: Schematics, was : Re: Xilinx Webpack bugs bugs bugs
Emanuele C:
150755: 11/02/09: Re: FPGA changes behaviour when the resource's usage percentage changes
150771: 11/02/10: Re: FPGA changes behaviour when the resource's usage percentage changes
150909: 11/02/21: Re: FPGA changes behaviour when the resource's usage percentage changes
Emanuele Carraro:
150670: 11/02/02: Re: FPGA changes behaviour when the resource's usage percentage changes
Emanuele Russo:
26622: 00/10/23: implementing a memory
Emanuele83:
150503: 11/01/25: FPGA changes behaviour when the resource's usage percentage changes
150506: 11/01/25: Re: FPGA changes behaviour when the resource's usage percentage changes
150510: 11/01/25: Re: FPGA changes behaviour when the resource's usage percentage changes
150519: 11/01/25: Re: FPGA changes behaviour when the resource's usage percentage changes
150522: 11/01/25: Re: newbie looking for Xilinx help
150536: 11/01/25: Re: FPGA changes behaviour when the resource's usage percentage changes
150538: 11/01/25: Re: FPGA changes behaviour when the resource's usage percentage changes
150550: 11/01/26: Re: FPGA changes behaviour when the resource's usage percentage changes
150553: 11/01/26: Re: FPGA changes behaviour when the resource's usage percentage changes
150555: 11/01/26: Re: FPGA changes behaviour when the resource's usage percentage changes
150580: 11/01/27: Re: FPGA changes behaviour when the resource's usage percentage changes
150582: 11/01/27: Re: Interfacing with a 5v micro controller
150585: 11/01/27: Re: FPGA changes behaviour when the resource's usage percentage changes
150618: 11/01/28: Re: FPGA changes behaviour when the resource's usage percentage changes
embargo:
22585: 00/05/13: Help-help
embedded:
148573: 10/08/03: PIT interrupt in Xilinx
Embedded Head:
29648: 01/03/03: Full Time - No contractors
29708: 01/03/06: Re: Full Time - No contractors
<embeddedexpert2007@gmail.com>:
124246: 07/09/16: FPGA power optimize! Help
embyembu:
97442: 06/02/22: state machine and i2c
emeb:
124828: 07/10/05: Re: XUPV2P from digilentinc
126741: 07/11/30: Re: What tools do you use ? Why ?
127013: 07/12/08: Re: What to look for when synthesising verilog code originally
127015: 07/12/08: Re: DDS generator with interpolated samples for Spartan3E development
127661: 08/01/04: Re: Where are the LCD or OLED bitmapped displays?
128646: 08/02/01: Re: Xilinx BSCAN primitives proper use
128955: 08/02/11: Re: FYI. Free Verilog cores from MIT.
129296: 08/02/20: Re: FPGA Programming solution
129298: 08/02/20: Re: FPGA Programming solution
130347: 08/03/20: Re: Configuring a Spartan 3A1800 ExtremeDSP from Spartan3 cable?
130614: 08/03/28: ISE 10.1 XST runs in background?
130615: 08/03/28: Re: ISE 10.1 XST runs in background?
130649: 08/03/29: ISE 10.1 - Initial experience
130751: 08/03/31: Re: ISE 10.1 - Initial experience
130778: 08/04/01: Re: ISE 10.1 - Initial experience
134263: 08/08/02: Re: What's the deal with PSoC programmers?
134268: 08/08/03: Re: What's the deal with PSoC programmers?
135293: 08/09/24: Re: Xilinx Mode Select Pins
135307: 08/09/25: Re: Xilinx Mode Select Pins
138150: 09/02/07: Re: Recommended Xilinx USB JTAG cable?
138218: 09/02/09: Re: Recommended Xilinx USB JTAG cable?
138223: 09/02/09: Re: Recommended Xilinx USB JTAG cable?
138428: 09/02/22: Spartan 3E Slave Serial problems
138440: 09/02/23: Re: Spartan 3E Slave Serial problems
138441: 09/02/23: Re: Spartan 3E Slave Serial problems
138445: 09/02/23: Re: Spartan 3E Slave Serial problems
138447: 09/02/23: Re: Spartan 3E Slave Serial problems
138456: 09/02/23: Re: Spartan 3E Slave Serial problems
138460: 09/02/23: Re: Spartan 3E Slave Serial problems
138489: 09/02/24: Re: XST hangs on HDL Analysis
139485: 09/03/31: Re: Programming Digilent Nexys 2 from Linux
139515: 09/04/01: Re: Programming Digilent Nexys 2 from Linux
139547: 09/04/02: Re: Programming Digilent Nexys 2 from Linux
143261: 09/09/28: Re: USB programmable Open Source Hardware
143279: 09/09/29: Re: USB programmable Open Source Hardware
143283: 09/09/29: Re: USB programmable Open Source Hardware
143287: 09/09/29: Re: USB programmable Open Source Hardware
143310: 09/10/01: Re: Antti-Brain one year anniversary
143312: 09/10/01: Re: Antti-Brain one year anniversary
144365: 09/12/01: Re: Goal to make $30-40 Open Source Logic Analyzer with Spartan 3E.
144424: 09/12/05: Help with Xilinx Eval Board Schematic
144425: 09/12/05: Re: Help with Xilinx Eval Board Schematic
144607: 09/12/20: Re: Trouble with Xilinx DCM - Spartan3
144848: 10/01/07: Re: new PC specs for Xilinx tools
145053: 10/01/22: Re: ChipScope scripting for batch data collection?
145125: 10/01/28: DPA vs FPGA Security?
145158: 10/01/29: Re: DPA vs FPGA Security?
145165: 10/01/29: Re: DPA vs FPGA Security?
145285: 10/02/04: Audio FPGA project
146008: 10/03/03: Re: Laptop for FPGA design?
146031: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
146039: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
148586: 10/08/03: Re: Xilinx ISE Webpack and Pipeline Optimization
149407: 10/10/22: Re: Combined Microprocessor and FPGA
Emeka MOSANYA:
14238: 99/01/21: Re: The development of a free FPGA synthesis tool
Emel:
94218: 06/01/08: Help! FIR Filter - MATLAB fdatool - VHDL
<ememka@my-dejanews.com>:
12621: 98/10/20: isp download cable ?
12620: 98/10/20: isp downnload cable
EMF:
26659: 00/10/24: New PACT 50 GOP Reconfigurable Processor
Emil Blaschek:
15051: 99/03/04: Re: Clock divider: 100MHz->40MHz
16142: 99/05/06: Re: [Q]Do you recommend Altera MAXPLUS II9.01 as a VHDL compiler for Altera FPGA?
18106: 99/09/30: Re: Performance of reprogrammable =?iso-8859-1?Q?FPGA=B4s=3F?=
22485: 00/05/10: Re: pipeline shiftreg in virtex
22487: 00/05/10: Re: virtex e lvds clock recovery
22528: 00/05/11: alexander decoder
23538: 00/06/29: Re: 500 million transistor FPGA's
24474: 00/08/10: Re: 17 clocks in a Virtex
36450: 01/11/09: reply
36544: 01/11/12: Re: Probing BGA Designs
46960: 02/09/13: Re: tristate bus
49172: 02/11/04: Re: High Performance FPGA's - Xilinx and ??????
53160: 03/03/05: Re: Mac Os X for FPGA design
53290: 03/03/10: Re: Partial Reconfigration:Active Module of MD
Emil Imrith:
154460: 12/11/05: Real Time Protocol - RTP using FPGA
154461: 12/11/05: Re: Real Time Protocol - RTP using FPGA
Emil Isaakian:
54413: 03/04/10: Re: Really long vectors in VHDL
Emil Wennman:
51358: 03/01/11: MPEG ASIC
Emile:
48073: 02/10/10: XC2S150-5FG456C or XC2S150-5FG256C
54498: 03/04/11: Re: Buying FPGAs from parts brokers
58703: 03/07/31: Re: Pricing question....
61586: 03/10/07: BF957C Application
65424: 04/01/28: Flip-Chip Package Substrate Solder Issue
65561: 04/02/02: Re: Flip-Chip Package Substrate Solder Issue
emilia:
58708: 03/07/31: Problem in Xilinx (Freq Counter) design
58757: 03/07/31: Re: Problem in Xilinx (Freq Counter) design
Emilian Miron:
158566: 15/12/27: Re: FPGA for a beginner
158631: 16/02/11: Re: EPM240T100C5N, LM2596, USB Blaster.
159064: 16/07/23: Re: Mod-24: The State of High-Level Synthesis in 2016
159158: 16/08/26: Re: Low End FPGAs
159259: 16/09/13: Re: Ob Screen Display from video coming from OV7670
159932: 17/04/30: Re: RISC-V Support in FPGA
160373: 17/12/31: Re: FPGA motherboard for 80386 CPU
160517: 18/03/13: Re: How to handle a data packet while calculating CRC.
160866: 18/12/10: Re: Help with Pmod VGA on Altera
emilymr:
139550: 09/04/02: summer internship DSP + FPGA + Image processing
EML:
153455: 12/03/02: JTAG to obsolete Lattice MACH131?
<eml@riverside-machines.com.NOSPAM>:
18173: 99/10/05: Re: What are the Virtex REV connections?
18123: 99/10/01: Re: Slice (or CLB) count
18252: 99/10/10: Re: DLL and programmable delay in Xilinx FPGA
18369: 99/10/20: Re: Interconnecting LUTs on a Virtex
18372: 99/10/20: Re: Interconnecting LUTs on a Virtex
18517: 99/10/28: Re: Xilinx Orientation Question
18559: 99/10/31: Re: Comparison between Altera and Xilinx
18750: 99/11/11: Re: Simulation of FPGA design. Please Help!
18860: 99/11/19: Re: How to use multiple resets?
18861: 99/11/19: Re: How to use GSR-net in Virtex?
19086: 99/11/28: Re: Programming Virtex device via JTAG
19087: 99/11/28: Re: PADS Experience?
19088: 99/11/28: Re: VHDL vs. schematic entry
19089: 99/11/28: Re: Leonardo Spectrum Printing Problem
19090: 99/11/28: Re: async latch implementation in Leonardo
19245: 99/12/08: Re: Xilinx FPGA Map report question
19451: 99/12/22: Re: State machine ok with binary encoding but unstable with one hot encoding
19452: 99/12/22: Re: M1 timings
19509: 99/12/28: Re: How can I preset /prereset some Latches
19592: 00/01/03: Re: Design security
19679: 00/01/07: Re: Disable clockbuffer for only a single flip-flop
19694: 00/01/08: Re: Disable clockbuffer for only a single flip-flop
19695: 00/01/08: Re: Disable clockbuffer for only a single flip-flop
19856: 00/01/14: Re: Design security
19990: 00/01/21: Re: help: signal stuck at 'U' inside generate statement
20055: 00/01/25: Re: Virtex Fine Pitch BGA pcb layout
20056: 00/01/25: Anyone changed an NT disk serial number?
20069: 00/01/26: Re: Virtex Fine Pitch BGA pcb layout
20070: 00/01/26: Re: Xilinx programming from a Linux PC
20103: 00/01/27: Re: Anyone changed an NT disk serial number?
20104: 00/01/27: Re: GSR in HDL on instantiated flip-flop primitives
20240: 00/02/02: Re: Announcement: Xilinx on Linux HowTo
20272: 00/02/03: Renoir problem: several engineers sharing a common setup?
20283: 00/02/03: Re: Renoir problem: several engineers sharing a common setup?
20299: 00/02/04: Re: Renoir problem: several engineers sharing a common setup?
20310: 00/02/04: Re: Conditional compilation in VHDL?
21161: 00/03/08: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
21176: 00/03/09: Re: antifuse fpga's replacing xilinx
21207: 00/03/10: Re: SpartanXL route and place
21209: 00/03/10: Re: antifuse fpga's replacing xilinx
21210: 00/03/10: Re: SpartanXL route and place
21282: 00/03/15: Re: Virtex IOB T register
21283: 00/03/15: Re: Is there a chance to synthesize that?
21284: 00/03/15: Re: Difference between FPGA, PLD, CPLD ?
21476: 00/03/23: Re: FPGA openness
21518: 00/03/24: Re: No- FPGA openness
21520: 00/03/24: Re: FPGA openness
21556: 00/03/24: Re: FPGA openness
21569: 00/03/25: Re: FPGA openness
21570: 00/03/25: Re: Altering Xilinx FPGA version/ID after PAR
22312: 00/05/04: Re: Wait until statement problem in synthesis
22573: 00/05/12: Re: [BitGen] - pb option UserClk
22593: 00/05/12: Re: Do you know xilinx FPGAs well?
24011: 00/07/21: Re: Foundation 3.1i in Germany
24170: 00/07/28: Re: Which one is good coding style?
24171: 00/07/28: Re: Pad trireg in XLA FPGA
24172: 00/07/28: Re: Pad trireg in XLA FPGA (beating a horse to death)
24306: 00/08/03: Re: tbuf
24304: 00/08/03: Re: 8251A USART
24305: 00/08/03: Re: Well, it finally happenned
24343: 00/08/04: Re: Who needs all those printed ac parameters?
24344: 00/08/04: Re: XST?
24452: 00/08/09: Re: Who needs all those printed ac parameters?
24453: 00/08/09: Re: XST?
24454: 00/08/09: Re: Xilinx Foundation 3.1i
24518: 00/08/11: Re: Xilinx of Linux Howto Updated
24519: 00/08/11: Re: Deterministic FPGA routing?
24713: 00/08/17: Re: error during synthesis
24714: 00/08/17: Re: Xilinx design flow with Mentor
24715: 00/08/17: Re: When will SpartanII be in ditribution
24778: 00/08/18: Re: state encoding in Synplify!!!
24807: 00/08/19: Re: Xilinx design flow with Mentor
24808: 00/08/19: Re: Fully contrained designs...
24990: 00/08/23: Re: timing simulation vs functional one
24991: 00/08/23: Re: xdl documentation
25226: 00/08/31: Re: make for design flow (was: Deterministic FPGA routing?)
25227: 00/08/31: Re: "generate" and instance name indexes in Synopsys
25233: 00/08/31: Re: "generate" and instance name indexes in Synopsys
25313: 00/09/06: Re: Mealy vs Moore FSM model
25394: 00/09/09: Re: 3.3/2.5 voltage regulators
25395: 00/09/09: Re: IEEE 754 Floating point VHDL functions / MATH package
25525: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
25546: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
25548: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
25577: 00/09/14: Re: Ethernet MII + bit ordering
25609: 00/09/15: Re: FPGA Express Strikes Again!
25783: 00/09/20: Re: Simon , decoupling caps
25784: 00/09/20: Re: Virtex clock fanout
25785: 00/09/20: Re: Freelance Designer Needed: Protel & FPGA
25786: 00/09/20: Synthesiser comparisons (was: FPGA Express strikes again)
25828: 00/09/22: Re: Category : Why CRs are cleared?
25829: 00/09/22: Re: Simon , decoupling caps
25833: 00/09/22: Re: Announce: Free HC11 CPU Core
25951: 00/09/27: Re: Simon , decoupling caps
25968: 00/09/28: Re: ABEL truth table for 8-1 Mux
26135: 00/10/05: Re: 3DES VHDL
26136: 00/10/05: Re: DLL unlocking
26168: 00/10/06: Re: Non-standard vhdl expressions
26238: 00/10/09: Re: Non-standard vhdl expressions
26284: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26339: 00/10/12: Re: LUT to CLB assignment
26340: 00/10/12: Re: Category : Subject:Floorplanning
26375: 00/10/13: Re: CRC calculation
26492: 00/10/18: Re: const coeff multiplier w/ LUTs
26493: 00/10/18: Re: 5V compatible Virtex
26687: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
26691: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
26709: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
26710: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
26722: 00/10/26: Re: How safe is the algorithm implemented with FPGA?
26723: 00/10/26: Re: How safe is the algorithm implemented with FPGA?
26724: 00/10/26: Re: Design theft story in EDN. New security ?
26874: 00/11/02: Re: Alliance under Linux?
26951: 00/11/04: Re: Alliance under Linux?
26873: 00/11/02: Re: Spartan II ?
26895: 00/11/02: Re: OT: Xilinx T-Shirt
26910: 00/11/03: Re: OT: Xilinx T-Shirt
26921: 00/11/03: Re: High Slice Usage in Virtex-E
27443: 00/11/22: Re: Using FPGA as PCI target
27444: 00/11/22: Re: Resetting Flip-Flops in Virtex
27445: 00/11/22: Re: Resetting Flip-Flops in Virtex
27459: 00/11/22: Re: Using FPGA as PCI target
27460: 00/11/22: Re: Clock Skew : Does Xilinx know what they're doing?
27475: 00/11/23: Re: Clock Skew : Does Xilinx know what they're doing?
27588: 00/11/29: Re: NGDBUILD/UCF Problem
27654: 00/12/01: Re: Synplify Benchmarks
27751: 00/12/06: Re: Gate Level Simulation Questions
27872: 00/12/13: Re: Synplify PRO 6.1 + Foundation 3.1i
27931: 00/12/15: Re: Setup violation
27932: 00/12/15: Re: Exemplar: max_load=1 gives me fanout=75
27933: 00/12/15: Re: Verilog or VHDL
28093: 00/12/20: Re: Is it necessary to synchronize the reset signal in an FPGA ?
28094: 00/12/20: Re: Verilog or VHDL
28096: 00/12/20: Re: Help with encoder/decoder
28110: 00/12/21: Re: really fast counter in SpartanXL?
28111: 00/12/21: Re: Is it necessary to synchronize the reset signal in an FPGA ?
28112: 00/12/21: Re: Help with encoder/decoder
28124: 00/12/21: Re: Help with encoder/decoder
28196: 00/12/27: Re: Methodology
28234: 01/01/03: Re: Newbie question on clock timing generation
28235: 01/01/03: Re: Newbie question on clock timing generation
28399: 01/01/11: Re: Alliance for Linux
28433: 01/01/12: Re: CRC - from long division to XOR, how?
28448: 01/01/12: Re: CRC - from long division to XOR, how?
28570: 01/01/17: Re: revision control tools ??
28571: 01/01/17: Re: CRC - from long division to XOR, how?
28615: 01/01/18: Re: revision control tools ??
28633: 01/01/18: Re: revision control tools ??
29132: 01/02/07: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29133: 01/02/07: Re: interior timing constraints - Xilinx F1.5
29141: 01/02/07: JTAG debugging?
29170: 01/02/08: Re: Wired-or on Virtex FPGAs
29254: 01/02/11: Re: Mentor Advice
29344: 01/02/15: FAQ submission (was: Re: JTAG debugging?)
29345: 01/02/15: Re: Wired-or on Virtex FPGAs
29362: 01/02/16: Re: Xilinx GSR in Verilog simulations
Emma Mowat:
162: 94/09/05: XC3130 Electrical Overstress Problem
861: 95/03/16: Tie option in makebits
Emmanuel JOLLY:
14392: 99/01/28: Re: HEX file format
14393: 99/01/28: ALTERA: Configuration problem of 10K50VRC240-3 + EPC1PC8
16676: 99/06/02: Re: Printing to picture files
Emmanuel Jolly:
7563: 97/09/22: I2C bus in an ALTERA FPGA (FLEX 10K50)
emmanuel jolly:
8677: 98/01/19: Re: ByteBlaster
9435: 98/03/13: Re: Altera Flex10K register initialization confusion
12317: 98/10/08: Re: LCELL delay of Altera 10K's
12318: 98/10/08: Re: Altera MAXPLUS2 V9 slow.
Emmanuel Lecomte:
22497: 00/05/10: Re: ? economical SPROM programmer for Xilinx
Emmanuel Monnerie:
8339: 97/12/09: Need a fast ADC
8395: 97/12/12: Re: PCs vs. workstations
8442: 97/12/15: Re: bus design in Altera 10K, how to increase speed
Emmanuel Said:
49754: 02/11/20: Re: Cpld beginner
Emmanuel SAID:
24784: 00/08/18: MP3 in FPGA ?
Emmanuel SIMLER:
7596: 97/09/25: PCMCIA library
<emotuk@gmail.com>:
119243: 07/05/15: Using dynamic reconfiguration ports of DCMs on Virtex 4
Emp:
106477: 06/08/14: Microblaze : Timingproblems
106962: 06/08/23: Microblaze : xil_malloc malloc
<employment@beer.com>:
emrah:
76037: 04/11/23: Quartus II: trace
76052: 04/11/23: Re: Quartus II: trace
76115: 04/11/25: Re: Quartus II: trace
Emrah:
94069: 06/01/05: Costas Loop Carrier Recovery
<emrith@gmail.com>:
124594: 07/09/27: Xilinx upgrade
ems:
9448: 98/03/14: Re: Strange Xilinx question?
9470: 98/03/16: Re: Strange Xilinx question?
9469: 98/03/16: Re: Strange Xilinx question?
9568: 98/03/24: Re: Orca Floorplanning tools
9627: 98/03/27: Re: VHDL shareware editor?
9671: 98/03/30: Re: XactStep6 - The cure for a dongle
9953: 98/04/16: Re: Xilinx Timing Constraints
10008: 98/04/22: Re: Xilinx Timing Constraints
10323: 98/05/12: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
10354: 98/05/14: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
10355: 98/05/14: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
10424: 98/05/18: Re: XABEL problem
10580: 98/06/02: More Xilinx timing constraints
10680: 98/06/10: Re: How about Lattice ispLSI?
10858: 98/06/25: Xilinx Foundation simulator problem?
10864: 98/06/26: Re: Xilinx Foundation simulator problem?
10869: 98/06/26: Re: Xilinx Foundation simulator problem?
10871: 98/06/26: Re: Xilinx Foundation simulator problem?
10874: 98/06/26: Re: Xilinx Foundation simulator problem?
10886: 98/06/28: Re: Xilinx Foundation simulator problem?
10887: 98/06/28: Re: Xilinx Foundation simulator problem?
10888: 98/06/28: Re: Xilinx Foundation simulator problem?
10921: 98/07/01: Re: Xilinx Foundation simulator problem?
10922: 98/07/01: Re: Xilinx Foundation simulator problem?
10999: 98/07/09: Re: Simulation at powerup
11011: 98/07/10: Re: Xilinx Foundation Frustartions
11101: 98/07/19: Re: Too much advertising in this news group?
11102: 98/07/19: Re: Floorplanning Intro?
11115: 98/07/20: Re: CRC Implementation
11132: 98/07/20: Re: How to write a VHDL counter of up & down
11142: 98/07/21: Re: Any VHDL counter with up & down functions
11143: 98/07/21: Re: problems in SDF files from foundation 1.4?
11227: 98/07/28: Async design/minimum prop delays
11252: 98/07/30: Re: How to connect my reset with GSR at Xilinx-FPGAs - response and Additional questions!
11333: 98/08/05: Re: Delay Element for async design.
11358: 98/08/06: Re: PCI Core In FPGA
11370: 98/08/07: Re: Delay Element for async design.
11371: 98/08/07: Re: PCI Core In FPGA
11395: 98/08/10: Re: PCI Core In FPGA
11396: 98/08/10: Re: PCI Core In FPGA
11332: 98/08/05: Re: VHDL std_logic_vector to integer
11423: 98/08/12: Re: Security
11434: 98/08/13: Re: FFT-Speed
11460: 98/08/17: Re: FFT-Speed
11491: 98/08/19: Re: Where are the multiple drivers?
<ems@nospam.riverside-machines.com>:
11649: 98/08/28: Re: New Evolutionary Electronics Book
11715: 98/09/03: Re: Digital PLL
11704: 98/09/02: Re: Wait statements and while loops
11851: 98/09/14: Re: Xilinx Spartan vs. 4K series
11852: 98/09/14: Re: ASIC -> FPGA async issues
11870: 98/09/15: Re: ASIC -> FPGA async issues
11924: 98/09/19: Re: Problems with the Floorplanner in Xilinx Alliance 1.5
11925: 98/09/19: Re: Confused teacher's THANKS
11941: 98/09/20: Re: Xilinx Configuration Info
11952: 98/09/21: Re: Dynamic pattern matching in Xilinx FPGAs
11969: 98/09/22: Re: Confused teacher's THANKS
12232: 98/10/06: Re: Synthesis: Exemplar or Synopsys
12299: 98/10/08: Re: Synthesis: Exemplar or Synopsys
12300: 98/10/08: Re: Synthesis: Exemplar or Synopsys
12301: 98/10/08: Re: USAGE of XILINX "FROM:TO" for VHDL and IMPLEMENTATION
12302: 98/10/08: Re: Degradation of results from Xilinx F1.3 -> F1.4 -> F1.5
12461: 98/10/12: Re: FOCUS FOCUS FOCUS
12462: 98/10/12: Re: FOCUS FOCUS FOCUS
12495: 98/10/13: Re: FOCUS FOCUS FOCUS
12521: 98/10/14: Re: Viewsim bashing 101
12522: 98/10/14: Re: FOCUS FOCUS FOCUS
12523: 98/10/14: Re: Schematic entry?
<ems@riverside-machines.com.NOSPAM>:
12656: 98/10/22: Re: State machines in VHDL/Verilog
12663: 98/10/22: Re: State machines in VHDL/Verilog
12742: 98/10/27: Re: FPGA Decouple Capacitor values
12777: 98/10/29: Re: FPGA Decouple Capacitor values
12801: 98/10/30: Re: FPGA Decouple Capacitor values
12802: 98/10/30: Re: 8051 VHDL Model
12803: 98/10/30: Re: FPGA Decouple Capacitor values
12804: 98/10/30: Re: FPGA Decouple Capacitor values
12833: 98/10/31: Re: Schematic entry?
12926: 98/11/05: Re: Schematic entry?
12905: 98/11/04: Re: Q: fifo flags
12962: 98/11/08: Re: Clock Doubler
13076: 98/11/14: Re: placement&routing problems
13083: 98/11/15: Re: placement&routing problems
13154: 98/11/17: Re: placement&routing problems
13658: 98/12/16: Re: HELP, Tool selection
13659: 98/12/16: Re: 4000 series EDIF routing property
13743: 98/12/21: Xilinx, RPMs, and VHDL
13835: 98/12/29: Re: 22V10 Metastability - help please
13865: 98/12/30: Re: 22V10 Metastability - help please
13867: 98/12/30: Re: about using Mentor and Foudation together
13886: 98/12/31: Re: 22V10 Metastability - help please
13900: 99/01/01: Re: Can a cross coupled latch "oscillate"? was Re: ..........
14151: 99/01/15: Re: Problems with processes
14152: 99/01/15: Re: Problem with reducing bus width / Foundation Series v1.5
14153: 99/01/15: Re: Hard porting to FPGA Express
14176: 99/01/17: Re: Xilinx Bitstream
14212: 99/01/20: Re: Xilinx Bitstream
14231: 99/01/21: Re: Can we get back to DSP again? Was Re: Who cares what DSP programmers think?
14364: 99/01/27: Re: The development of a free FPGA synthesis tool
14363: 99/01/27: Re: Hysteresis on PLD Clock Inputs
14365: 99/01/27: Re: FPGA express warning
14366: 99/01/27: Re: Ratings for Synplicity Synplify
14370: 99/01/27: Re: Ratings for Synplicity Synplify
14416: 99/01/29: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
14417: 99/01/29: Re: Hold Time Violation
14537: 99/02/03: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14539: 99/02/03: Re: Ratings for Synplicity Synplify
14613: 99/02/06: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14614: 99/02/06: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14538: 99/02/03: Re: Need Help! clock multiplier!
14615: 99/02/06: Re: VHDL synthesis
14749: 99/02/14: Re: Derived Clocks and Clock enables in XILINX parts
14750: 99/02/14: Re: Problems with Xilinx F1.5 & latchs
14852: 99/02/20: Re: multiple clock domain problem
14853: 99/02/20: Re: multiple clock domain problem
14856: 99/02/20: Re: multiple clock domain problem
14894: 99/02/23: Re: Inferring IOFFs with FPGA Express 3.x and Foundation 1.5i
14929: 99/02/25: Re: Xilinx ABEL?
15098: 99/03/06: Re: Problems inferring RAM memory
15290: 99/03/17: Re: Power Estimiation
15601: 99/04/02: Re: Schematic Capture & FPGA synthesis
15642: 99/04/05: Re: Schematic Capture & FPGA synthesis
15602: 99/04/02: Re: How to implement Matched Filter in FPGA?
15643: 99/04/05: Re: How to implement Matched Filter in FPGA?
15758: 99/04/12: Re: Illegal States in 1 Hot State Machines
15825: 99/04/15: Re: Illegal States in 1 Hot State Machines
15868: 99/04/17: Re: Some FPGA questions
15925: 99/04/21: Virtex, VREF, and serial configuration
15927: 99/04/21: Re: Xilinx Virtex GCLKs
15936: 99/04/22: Re: Virtex, VREF, and serial configuration
15966: 99/04/23: Re: Timing Constraint
15993: 99/04/26: Re: Job Advert Netiquette?
15994: 99/04/26: Re: Timing Constraint
16024: 99/04/28: Re: Timing Constraint
16025: 99/04/28: Re: High speed PLL inside FPGA
16219: 99/05/10: Re: Looking for Altera APEX board
16413: 99/05/20: Re: How synthesize tools concern with size of the design?
16464: 99/05/24: Re: How synthesize tools concern with size of the design?
16588: 99/05/28: Re: FPGA express + VHDL: strange SR implementation?
16597: 99/05/29: Re: FPGA express + VHDL: strange SR implementation?
16598: 99/05/29: Re: Generating GSR From Within Chip
16662: 99/06/01: Re: Generating GSR From Within Chip
16663: 99/06/01: Re: FPGA express + VHDL: strange SR implementation?
16955: 99/06/19: Re: Read/Writes to memories/register files for PIC core
17004: 99/06/23: Re: Read/Writes to memories/register files for PIC core
17032: 99/06/26: Re: Synopsys FPGA Express vs. Compiler II
17033: 99/06/26: Re: Virtex data sheet is incomplete
Emtech:
90865: 05/10/24: 24 to 32 8-bit PWM outputs
91019: 05/10/27: Re: 24 to 32 8-bit PWM outputs
emu:
106814: 06/08/20: Re: Xilinx ML501 availability
117892: 07/04/12: spartan 3e availability
117901: 07/04/12: Re: spartan 3e availability
119863: 07/05/28: Re: 6502 FPGA core
120270: 07/06/04: Re: Nexys by Digilen xbd file
120326: 07/06/05: Re: Nexys by Digilen xbd file
120630: 07/06/12: xilinx spartan3e kit ddr sdram
120843: 07/06/18: Re: Recommendation for creating a DDR Sdram core for custom board and integrate in XPS
123573: 07/08/30: Re: Spartan 3E starter kit (Rev.D) modification : 3E500 -> 3E1200
124667: 07/09/29: Re: XUPV2P from digilentinc
124669: 07/09/29: Re: Own soft-processor
en:
46700: 02/09/06: Re: Lattice GAL22V10 and everything it entails . . . !
ENapoli:
32381: 01/06/25: Xilinx unified library
<enavacchia@virgilio.it>:
110720: 06/10/20: i486 FPGA replacement
110822: 06/10/24: Re: i486 FPGA replacement
Encore Electronics:
5054: 97/01/17: Able to reverse a .JED back to logic?
Endric Schubert:
14602: 99/02/05: Re: Worst service in India by Xilinx
14691: 99/02/11: Re: AHDL VS. VHDL
14603: 99/02/05: routability of FPGA - is this an issue?
14645: 99/02/08: Re: routability of FPGA - is this an issue?
43466: 02/05/21: Re: extend jtag downloadcable
44514: 02/06/22: Re: Quartus v/s Leonardo
44515: 02/06/22: Bad Virtex2 devices - any similar experiences
Enes ERDIN:
127930: 08/01/10: Connecting different FPGAs using LVDS
127948: 08/01/10: Re: Connecting different FPGAs using LVDS
127949: 08/01/10: Re: Connecting different FPGAs using LVDS
127955: 08/01/11: VirtexE LVDS driver
128141: 08/01/16: Re: gaussian filter in Altera FPGA
Enes Erdin:
132136: 08/05/15: Re: Camera link interface
132138: 08/05/15: Re: Camera link interface
132162: 08/05/16: Length between blocks in FPGA
132171: 08/05/16: Re: Incorporating FPGAs on PCBs
132177: 08/05/16: Re: Incorporating FPGAs on PCBs
132179: 08/05/16: Re: Incorporating FPGAs on PCBs
132188: 08/05/16: Re: Incorporating FPGAs on PCBs
132204: 08/05/17: Re: Incorporating FPGAs on PCBs
132206: 08/05/17: Re: FPGA art
132412: 08/05/26: Re: Downloading external data file to FPGA
132416: 08/05/26: Re: Downloading external data file to FPGA
132537: 08/05/30: dual port ramb16 problem
135031: 08/09/11: Re: How to install Xilinx ISE simulator?
136016: 08/10/28: FPGA RAM clock connection
136496: 08/11/19: Re: how to implement an application with external memory in ISE?
136522: 08/11/20: Re: how to implement an application with external memory in ISE?
136787: 08/12/05: Re: Xilinx-ISE nets names after placement & routing
137889: 09/02/01: Re: Dangling blockram output - how to remove warning?
138029: 09/02/04: dual processor PC for PPR - are they worth the extra cost?
138030: 09/02/04: Re: dual processor PC for PPR - are they worth the extra cost?
138068: 09/02/05: Re: dual processor PC for PPR - are they worth the extra cost?
138101: 09/02/06: Re: Precedence of signal assignment in a clocked process
141680: 09/07/03: Re: how to use ram or memory
145198: 10/02/01: Re: Single Port Rom created by Core Generator configurable by generic
145200: 10/02/01: Re: Single Port Rom created by Core Generator configurable by generic
153687: 12/04/22: Re: VHDL syntheses timestamp
154800: 13/01/12: Do you have any BROKEN Xilinx Platform Cable Usb or II
eng:
23230: 00/06/18: Re: Problem copying text from the Spartan II data sheet
23249: 00/06/19: Re: Hand soldering a PQ208 - It looks tough to do.
26654: 00/10/24: Re: Atmel FPGA tools (was Re: Cheapy FPGA sw)
26935: 00/11/04: Crosspoint switch in CPLD/FPGA ??
Eng Gan:
69696: 04/05/18: clock buffer in Leonardo Spectrum
Eng.Emad Samuel:
130133: 08/03/16: Need help in SDR
Engine:
93641: 05/12/28: Xilinx Stepping Methodology
93669: 05/12/28: Re: Xilinx Stepping Methodology
93677: 05/12/28: Re: Xilinx Stepping Methodology
Engineer:
48131: 02/10/11: Quartus design question
EngineerEDGE:
129456: 08/02/25: Online Engineering Calculator Tool for Electronic Engineers - FREE to
Engineering Guy:
82499: 05/04/13: Re: Reading old F2.1i schematics
82500: 05/04/13: Re: Reading old F2.1i schematics
82503: 05/04/13: Re: Simualtion of Rocket I/O MGT in ModelSim XE
82506: 05/04/13: Re: Importing waveforms from ASCII files
82569: 05/04/14: Re: Reading old F2.1i schematics
82570: 05/04/14: Re: Flowcharts and diagrams
82634: 05/04/15: Re: Reading old F2.1i schematics
82635: 05/04/15: Re: Flowcharts and diagrams
82641: 05/04/15: Re: different I/O buffers available inXilinx FPGA
82794: 05/04/18: Re: combining two EDF netlist in ISE
engr:
41162: 02/03/21: Re: Xilinx JTAG Cables
41509: 02/03/31: Re: Orcad Sch f/Xilinx Spartan II
43377: 02/05/20: Re: Spartan II Proto. Board
Enno Luebbers:
97051: 06/02/15: Re: EDK - PLB/OPB Bus questions.
101201: 06/04/27: Re: hwicap can be used in the virtex4
101737: 06/05/05: Re: New To FPGA, Program question
enny:
36911: 01/11/24: DDS by LogiCore & how to overcome net delay
37279: 01/12/06: $EXPORT=NO(exp_EDIF) for CoreGen Component, schematic entry
37558: 01/12/14: Direct Digital Synthesizer, CoreGen
37633: 01/12/18: Disadvantages of core creating_rpm and pipeline ?
eNo:
65581: 04/02/02: Xilinx Virtex II Pro: LVDS_25 vs. BLVDS_25
enq_semi:
60362: 03/09/11: Altera's Quartus II "smart compilation" feature killed my design?
60419: 03/09/12: Re: Altera's Quartus II "smart compilation" feature killed my design?
60541: 03/09/16: Re: Altera's Quartus II "smart compilation" feature killed my design?
60542: 03/09/16: Re: Altera's Quartus II "smart compilation" feature killed my design?
60543: 03/09/16: Re: Altera's Quartus II "smart compilation" feature killed my design?
60547: 03/09/16: Re: Altera's Quartus II "smart compilation" feature killed my design?
60700: 03/09/19: Re: Altera's Quartus II "smart compilation" feature killed my design?
63050: 03/11/13: How to bring PLL's output to Pin_F1
63504: 03/11/24: How many dedicated clock pins EP20K1500EBC652 device?
63551: 03/11/25: Re: How many dedicated clock pins EP20K1500EBC652 device?
63607: 03/11/26: Re: How many dedicated clock pins EP20K1500EBC652 device?
Enrica Abbate:
1351: 95/06/05: Participate in Biennale Symposium via the Internet
Enrico Migliore:
16086: 99/05/01: IrDA controller macro: is it easy to design?
16507: 99/05/26: C to VHDL translator?
21230: 00/03/11: Xilinx Foundation Series and FSM designs
<enrique.laserna@web.de>:
57640: 03/07/03: Re: Excel and FPGA's
Ensign Jimmy:
38797: 02/01/25: Re: Intel vs. AMD
Ensoul Chee:
47598: 02/09/30: system item in synplify report
<entanglebit@gmail.com>:
111098: 06/10/28: Hardware mapping of algorithms
enterpoint:
44892: 02/07/04: Re: Maximum frequency in Virtex and Virtex-E Devices
Entwicklung:
33910: 01/08/08: PCI Postcode Display
Enver:
90385: 05/10/11: how to implement 8x8 circular shifter on FPGA
Envjoe:
1260: 95/05/23: Re: Is anybody using FPGA's to do PCI interfaces?
Enzo B.:
77696: 05/01/14: Questions from a beginner...
77721: 05/01/15: Re: Questions from a beginner...
77722: 05/01/15: Re: Questions from a beginner...
82057: 05/04/06: A "simple" problem...
82080: 05/04/06: Re: A "simple" problem...
82132: 05/04/07: Re: A "simple" problem...
82139: 05/04/07: Re: A "simple" problem...
129887: 08/03/08: Datasheet on Micron's secure products
129897: 08/03/08: Re: Datasheet on Micron's secure products
Enzo Guerra:
88033: 05/08/07: Xilinx V4 & DDR2 Memory Interface
92314: 05/11/27: Virtex 4 Configuration
Enzo Liguori:
317: 94/10/18: Re: Multipliers in FPGA's
<eongur@wank.com>:
<eonxvt@faqlist.net>:
14595: 99/02/05: _____FAQ update for this newsgroup_____ 3732
eou4:
82381: 05/04/11: Xilinx VirtexII master serial mode problem(cclk)
82386: 05/04/11: Re: Xilinx VirtexII master serial mode problem(cclk)
82387: 05/04/11: Re: Xilinx VirtexII master serial mode problem(cclk)
82400: 05/04/12: Re: Xilinx VirtexII master serial mode problem(cclk)
82402: 05/04/12: Re: Xilinx 7.1 ISE patch - for XC9500/XL/XV and CoolRunnerXPLA3
82407: 05/04/12: Re: 2 bit multiplier
93659: 05/12/27: Re: Can Altera Cyclone device's clock input directly used as CLK with PLL?
93660: 05/12/27: disappear silicore
epson:
48126: 02/10/11: Simple PCI target core in XILINX Spartan2
48128: 02/10/11: Re: Simple PCI target core in XILINX Spartan2
48179: 02/10/13: Re: Simple PCI target core in XILINX Spartan2
EPV:
2906: 96/02/27: Re: Languages for reconfigurable computing.
3056: 96/03/22: sigma delta analog to digital conversion
Equinox:
135685: 08/10/12: Complex Event Processing on FPGA
135694: 08/10/12: Re: Complex Event Processing on FPGA
135695: 08/10/12: Re: Complex Event Processing on FPGA
135781: 08/10/15: Re: Complex Event Processing on FPGA
Erasmo Brenes:
1754: 95/08/25: Re: Synario/OrCad/Viewlogic
4392: 96/10/23: Re: VHDL for Xilinx designs?
4508: 96/11/06: Re: VHDL for Xilinx designs?
eraterg:
Erdinc Ozturk:
56358: 03/06/03: Celoxica RC200
ereader:
127100: 07/12/11: Poor quality Xilinx boards ? Your experience ?
127112: 07/12/11: Re: Poor quality Xilinx boards ? Your experience ?
127126: 07/12/12: Re: Poor quality Xilinx boards ? Your experience ?
127132: 07/12/12: Re: Poor quality Xilinx boards ? Your experience ?
127137: 07/12/12: Re: Poor quality Xilinx boards ? Your experience ?
127139: 07/12/12: Re: Poor quality Xilinx boards ? Your experience ?
127144: 07/12/12: Re: Poor quality Xilinx boards ? Your experience ?
127183: 07/12/13: Re: Poor quality Xilinx boards ? Your experience ?
127195: 07/12/13: Re: Poor quality Xilinx boards ? Your experience ?
127202: 07/12/13: Re: Poor quality Xilinx boards ? Your experience ?
127203: 07/12/13: Spartan 3E starter kit expansion boards - Gb ethernet & video
127257: 07/12/15: Re: Getting started guide for Digilent Spartan 3E Starter Board?
127258: 07/12/15: Re: serial ATA question
127296: 07/12/17: Re: Ethernet data rates using Spartan-3 FPGA
Erez Birenzwig:
62888: 03/11/11: Implementing a very fast counterin VirtexII
62893: 03/11/11: Re: How to create a look up table for a RAM application
62896: 03/11/11: Re: FPGAs and DRAM bandwidth
62898: 03/11/11: Re: Implementing a very fast counterin VirtexII
62904: 03/11/11: Re: Implementing a very fast counterin VirtexII
62953: 03/11/12: Re: Are modules that are not floorplanned still functional?
62957: 03/11/12: Re: Implementing a very fast counterin VirtexII
62958: 03/11/12: Re: Home grown CPU core legal?
62963: 03/11/12: Re: Implementing a very fast counterin VirtexII
63144: 03/11/17: Re: ISE 6.1 with synplify : pin assignments
63695: 03/12/01: Re: how to create timing report for all nets?
Erez Mozes:
21049: 00/03/04: I need an advice here pls!
Eric:
22239: 00/05/02: Re: new2fpga
22759: 00/05/23: Re: Xilinx tools becoming "RentWare"
22785: 00/05/24: Re: V23 and DTMF core?
23209: 00/06/17: Battery backup for 5V Xilinx Spartan devices
30020: 01/03/20: XESS Prototyping boards - Is there a difference between...
30585: 01/04/18: Re: Download Cable Mystery Solved
31103: 01/05/11: Re: Spartan Annoyances
31188: 01/05/14: Re: Quad Decoder
31191: 01/05/14: Re: Quad Decoder
31195: 01/05/14: Re: Quad Decoder
31196: 01/05/14: Re: Quad Decoder
31337: 01/05/19: Re: FPGA consultant needed
31359: 01/05/21: Re: FPGA consultant needed
31360: 01/05/21: Re: FPGA consultant needed
31626: 01/05/31: Re: Help in FIFO design
31862: 01/06/06: Re: Pentium 4 or AMD ?
31718: 01/06/04: Re: Pentium 4 or AMD ?
31893: 01/06/07: Re: Pentium 4 or AMD ?
32466: 01/06/27: Re: Can 3" CDROMs Damage 5" CDROM Drives?
33847: 01/08/06: Re: Slightly off topic - PCs for running FPGA tools
35351: 01/09/30: future Xilinx products wish list ...
35377: 01/10/01: Re: future Xilinx products wish list ...
35378: 01/10/02: Re: future Xilinx products wish list ...
35499: 01/10/08: Re: future Xilinx products wish list ...
35697: 01/10/14: Re: future Xilinx products wish list ...
35722: 01/10/15: Re: future Xilinx products wish list ...
36696: 01/11/15: Re: High Speed PWM?
36931: 01/11/26: Re: fpga programming using microcontroller
36933: 01/11/26: Re: fpga programming using microcontroller
36934: 01/11/26: Re: fpga programming using microcontroller
37065: 01/11/29: Re: palette LUT design(finding Virtex / Spartan II)
53901: 03/03/26: xilinx/modelsim simulate a subsystem ?
54825: 03/04/19: Spartan-3 questions?
58679: 03/07/30: tri-State buffer troubles ...
58754: 03/07/31: Re: tri-State buffer troubles ...
59057: 03/08/07: Spartan-IIE LVDS?
59094: 03/08/07: Re: Spartan-IIE LVDS?
59650: 03/08/25: Two near-identicial clocks?
75323: 04/11/02: XST - Memory Problems
74812: 04/10/19: Virtex-4 Slower than V2Pro?
75362: 04/11/03: Re: XST - Memory Problems
75379: 04/11/03: SRL16E_1 primitive instantiation in VHDL
75423: 04/11/05: Re: SRL16E_1 primitive instantiation in VHDL
75455: 04/11/06: Re: SRL16E_1 primitive instantiation in VHDL
77294: 05/01/03: Re: Skew between signals
77596: 05/01/11: Vht to Vwf
81310: 05/03/21: Re: question about salary
81542: 05/03/26: Multi-FPGA PCB data aggregation?
81544: 05/03/26: Re: Multi-FPGA PCB data aggregation?
81559: 05/03/27: Re: Multi-FPGA PCB data aggregation?
81586: 05/03/28: Re: Multi-FPGA PCB data aggregation?
81608: 05/03/28: Re: Multi-FPGA PCB data aggregation?
81730: 05/03/30: Xilinx ISE 7.1
82514: 05/04/13: Re: help neeeded for byteblaster of altera
82648: 05/04/15: Re: Soft CPU vs Hard CPU's
82649: 05/04/15: Re: Soft CPU vs Hard CPU's
82858: 05/04/18: Re: Declining a job offer
83018: 05/04/21: Re: HDL in safety critical applications
83019: 05/04/21: Re: HDL in safety critical applications
83272: 05/04/26: Re: dynamic size of ports
83785: 05/05/06: Re: newbie question
84058: 05/05/11: Re: FPGA/Embedded Design Training
85049: 05/06/03: Re: XP for NIOS2
85199: 05/06/06: Sch & Layout Free Program
85205: 05/06/06: Re: Sch & Layout Free Program
85291: 05/06/07: Re: Sch & Layout Free Program
86307: 05/06/24: Re: FPGA vs. ASIC vs. Processor
87972: 05/08/04: Re: Where can i find GeneticFPGA toolkit
88023: 05/08/05: Re: Where can i find GeneticFPGA toolkit
88065: 05/08/08: Re: Where can i find GeneticFPGA toolkit
88073: 05/08/08: Re: Where can i find GeneticFPGA toolkit
88136: 05/08/10: Re: Where can i find GeneticFPGA toolkit
88137: 05/08/10: Re: Where can i find GeneticFPGA toolkit
88232: 05/08/12: Re: Where can i find GeneticFPGA toolkit
88401: 05/08/17: Re: Evolutionary VHDL code example
88402: 05/08/17: Re: Evolutionary VHDL code example
88407: 05/08/17: Re: FPGA-Based system design project
88731: 05/08/26: Re: Writing to Spartan 3 SRAM
88856: 05/08/30: Re: Embedded Processors/Serdes
88913: 05/08/31: Re: Hi-Z input
88933: 05/08/31: Re: Hi-Z input
89153: 05/09/06: Linux on Viretex-II pro
89417: 05/09/14: USB tranciever + controller in FPGA
89459: 05/09/15: Re: FFT implementation in Xilinx Spartan 3 started kit
90606: 05/10/17: Program FPGA from PowerPC in V2P
90644: 05/10/18: Re: Program FPGA from PowerPC in V2P
90860: 05/10/23: RS232 Uart for Virtex-II Pro
90939: 05/10/25: EDK custom IP read/write
90942: 05/10/25: Re: EDK custom IP read/write
91346: 05/11/03: use ppc405 on virtex-II pro
91738: 05/11/11: Factory Mutual Approvable Sealed Lead Acid Battery
93317: 05/12/19: software application on the virtex-ii pro
94121: 06/01/05: Re: XC3S100/250/500E Availability?
94370: 06/01/10: application running on the top of Linux on virtex-ii pro
94453: 06/01/11: virtex-ii pro linux partition check hangs
94852: 06/01/18: Re: Selling Microblaze based Machines
95644: 06/01/24: custom ip using EDK
95712: 06/01/25: Re: custom ip using EDK
96783: 06/02/10: Spartan-3 Serial LVDS max speed?
96808: 06/02/10: SMP on virtex-ii pro
97999: 06/03/02: Using time.h in EDK
98172: 06/03/06: ac97 codec on xupv2p
98346: 06/03/08: EDK remote TCP debug
98471: 06/03/10: AC97 Codec
98699: 06/03/14: reading data off a virtex-ii pro board
99909: 06/03/30: question about Virtex-II Pro program execution time
100269: 06/04/05: audio codec on the virtex-ii pro board
103804: 06/06/12: xc3sprog -- any updates?
103808: 06/06/12: Re: xc3sprog -- any updates?
103847: 06/06/13: Re: xc3sprog -- any updates?
104245: 06/06/21: Re: xc3sprog -- any updates?
104310: 06/06/23: Re: xc3sprog -- any updates?
104339: 06/06/24: Re: xc3sprog -- any updates?
105363: 06/07/20: Re: Hardware book like "Code Complete"?
108095: 06/09/05: Microblaze Programmers Reference Guide?
108099: 06/09/05: Re: Microblaze Programmers Reference Guide?
110606: 06/10/18: Re: ANNC: Open Source, Free 32-bit soft processor webcast
116961: 07/03/21: Re: softcore CPU tools
124965: 07/10/13: Cyclone II on Altera DE2 Board - DRAM Timing on 18 inches?
124967: 07/10/13: Quartus II Web Edition License - SOPC Builder generation?
125050: 07/10/16: Re: Quartus II Web Edition License - SOPC Builder generation?
125135: 07/10/16: Re: Quartus II Web Edition License - SOPC Builder generation?
135497: 08/10/05: ISE Question - FPGA Program.jpg (0/1)
136028: 08/10/28: classic Spartan-3 DDR2 and IOBs
136096: 08/10/31: Re: classic Spartan-3 DDR2 and IOBs
136166: 08/11/04: Tiny JTAG connector
136541: 08/11/21: Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell
137238: 09/01/05: Intel QPI accelerators
138119: 09/02/06: Recommended Xilinx USB JTAG cable?
147241: 10/04/20: Efficient Multi-Ported Memories for FPGAs
147304: 10/04/22: Re: Efficient Multi-Ported Memories for FPGAs
147311: 10/04/22: Re: Efficient Multi-Ported Memories for FPGAs
147404: 10/04/26: Re: Efficient Multi-Ported Memories for FPGAs
147405: 10/04/26: Re: Efficient Multi-Ported Memories for FPGAs
147431: 10/04/27: Re: Efficient Multi-Ported Memories for FPGAs
147599: 10/05/05: FPGA Compilation Time Windows vs Linux
eric:
1955: 95/09/25: Re: UART for Actel FPGA needed
2264: 95/11/15: Can Actel A12XX probe itself? (was: Can X30xx Reset itself?)
46850: 02/09/09: How to make Altera UPX board self bootable?
57161: 03/06/24: Xilinx EDK examples from Website
57371: 03/06/28: Re: Xilinx EDK examples from Website
61177: 03/09/29: Xess' XSA-50 Audio Playback / SDRAM
65604: 04/02/03: 4 bit divisor with flip-flop ?
68939: 04/04/23: ATAPI
104685: 06/07/04: Re: EDK: Using DCR bus on ML310-based project
104686: 06/07/04: Altium Live Desing Eval and Linux
104783: 06/07/06: Re: Altium Live Desing Eval and Linux
109047: 06/09/20: MPMC2 and MontaVista Linux
109220: 06/09/22: Re: MPMC2 and MontaVista Linux
111556: 06/11/06: Re: Scientific Computing on FPGA
111628: 06/11/07: Re: Scientific Computing on FPGA
111629: 06/11/07: Re: Cypress 68013 - Xilinx FPGA
116960: 07/03/21: LZW compression and decompression in vhdl
118368: 07/04/25: Image compression on FPGA
119470: 07/05/21: AccelDSP Systemgenerator ML403
133387: 08/06/26: System Generator Xilinx ML403
134381: 08/08/08: Re: ML403, U-Boot+Linux and Ethernet?
149976: 10/12/04: Re: Help for a embeded system with SPARTAN-6 project
eric - Mtl:
50195: 02/12/04: Re: ISA bus VGA
50227: 02/12/05: Re: ISA bus VGA
50797: 02/12/19: Re: Async RAM on an FPGA board
54824: 03/04/19: Re: Boycott All Xilinx products untill they correct all ISE software
54873: 03/04/21: Re: Boycott All Xilinx products untill they correct all ISE softwareerrors
54883: 03/04/21: Re: Boycott All Xilinx products untill they correct all ISE softwareerrors
55071: 03/04/25: Re: software errors
55072: 03/04/25: Re: Boycott All Xilinx products untill they correct all ISE softwareerrors
55117: 03/04/28: Re: Low pin count SOC
Eric Aardoom:
1038: 95/04/19: Re: $40 Million For NeoCAD & A New FPGA Synthesis Tool
2378: 95/11/26: Re: XBLOX: the good, the bad and the shocking
Eric Anderson:
151414: 11/04/04: Re: SCons build tool as an alternative to makefiles
Eric BATUT:
63790: 03/12/04: Ideal Development Machine Specifications
63833: 03/12/05: Re: Ideal Development Machine Specifications
Eric Bohlman:
55673: 03/05/15: Re: Moore Vs Mealy machine ..
Eric Braeden:
24366: 00/08/04: Re: Memory specification
24843: 00/08/20: Re: Permanently programming FPGAs
25853: 00/09/22: Re: Announce: Free HC11 CPU Core
29354: 01/02/15: Re: Rijndael
29702: 01/03/05: Re: Full Time - No contractors
34491: 01/08/27: Re: FPGA to ASIC conversion?
36157: 01/10/31: Re: Firewire chipset
46493: 02/09/01: Re: Thermoelectric Controller by FPGAs
46610: 02/09/04: Re: Actel Proto Boards
Eric Brombaugh:
104338: 06/06/24: Spartan3E Starter kit on Linux?
106116: 06/08/07: Re: Open source Xilinx JTAG programmer with Digilent USB support
109589: 06/09/29: Re: Audio interface in Spartan 3E Starter kit
114364: 07/01/12: XST bug inferring dynamic shift register
118028: 07/04/16: Re: [xilinx] par [placer] consistency
118238: 07/04/20: Re: Summer with fpgas
119393: 07/05/17: Re: clock wide pulse transfer b/w clock domains
Eric Burke:
13: 94/07/28: Re: FPGA based processors ?
Eric C. Fromm:
28272: 01/01/04: Re: Nondeterministic FSMs in hardware?
28274: 01/01/04: Re: Nondeterministic FSMs in hardware?
28296: 01/01/05: Re: Nondeterministic FSMs in hardware?
Eric Chomko:
145316: 10/02/05: using an FPGA to emulate a vintage computer
145405: 10/02/08: Re: using an FPGA to emulate a vintage computer
145406: 10/02/08: Re: using an FPGA to emulate a vintage computer
145407: 10/02/08: Re: using an FPGA to emulate a vintage computer
145408: 10/02/08: Re: using an FPGA to emulate a vintage computer
145409: 10/02/08: Re: using an FPGA to emulate a vintage computer
145410: 10/02/08: Re: using an FPGA to emulate a vintage computer
145411: 10/02/08: Re: using an FPGA to emulate a vintage computer
145506: 10/02/12: Re: using an FPGA to emulate a vintage computer
145759: 10/02/22: Re: using an FPGA to emulate a vintage computer
145779: 10/02/23: Re: using an FPGA to emulate a vintage computer
145780: 10/02/23: Re: using an FPGA to emulate a vintage computer
145781: 10/02/23: Re: using an FPGA to emulate a vintage computer
145800: 10/02/24: Re: using an FPGA to emulate a vintage computer
145801: 10/02/24: Re: using an FPGA to emulate a vintage computer
145835: 10/02/25: Re: using an FPGA to emulate a vintage computer
145836: 10/02/25: Re: using an FPGA to emulate a vintage computer
145950: 10/03/01: Re: using an FPGA to emulate a vintage computer
146036: 10/03/04: Re: using an FPGA to emulate a vintage computer
146271: 10/03/10: Re: using an FPGA to emulate a vintage computer
147063: 10/04/12: Virtex-5 FPGA PCIe card
147088: 10/04/13: Re: Virtex-5 FPGA PCIe card
Eric Coffin:
962: 95/04/04: Re: Neocad merges with Xilinx
5317: 97/02/06: Re: Embedded SRAM in FPGAs
Eric Crabill:
19108: 99/11/29: Re: Anybody using Lucent OR3TP12?
19159: 99/12/02: Re: backup fifo's
19194: 99/12/04: Re: backup fifo's
19214: 99/12/06: Re: backup fifo's
19271: 99/12/09: Re: backup fifo's(2)
23870: 00/07/13: Re: Functional Simulation for Xilinx PCI Example Ping
24545: 00/08/13: Re: CLKDLL for Virtex PCI?
30012: 01/03/20: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
30018: 01/03/20: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
31344: 01/05/19: Re: Xilinx PCI macro problems
31345: 01/05/19: Re: FPGA consultant needed
31377: 01/05/21: Re: FPGA consultant needed
31845: 01/06/06: Re: Help in FIFO design
33054: 01/07/16: Re: Fixing routing in a Virtex FPGA
33605: 01/07/31: Re: Virtex2: Xilinx PCI core mapping error
34287: 01/08/18: Re: Spartan2 5V PCI IO
34948: 01/09/14: Re: Wanted: ISA bus implementation for Xilinx
35864: 01/10/21: Re: Virtex II powerdown
36086: 01/10/28: Re: Cloning someone else's IP core
36166: 01/10/31: Re: Cloning someone else's IP core
37347: 01/12/07: Re: How to increase clock skew for Spartan-II
37357: 01/12/07: Re: Xilinx FPGA Editor 4.1- problems with manually routing high-fanout
37728: 01/12/19: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37751: 01/12/19: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
38778: 02/01/24: Re: Does Xilinx Spartan-II have reserved pin for PCI?
38869: 02/01/26: Re: Xilinx PCI logicore: clarification on nature of COMPLETE
39107: 02/01/31: Re: Setting PCI command register in WinNT OS
39145: 02/02/01: Re: Setting PCI command register in WinNT OS
39610: 02/02/14: Re: Does anybody have the Xilinx Foundation Series 2.1i newest not
39746: 02/02/18: Re: FPGA: JTAG CABLE
40793: 02/03/15: Re: PCI design in a Spartan II which crashes in some wintel PCs
40819: 02/03/15: Re: Spartan II IOB tristate control FF use
40844: 02/03/16: Re: Spartan II IOB tristate control FF use
41149: 02/03/21: Re: low cost PCI spartan board needed
41209: 02/03/22: Pipelined sorting algorithms...
41214: 02/03/22: Re: Pipelined sorting algorithms...
41304: 02/03/25: Re: Pipelined sorting algorithms...
41651: 02/04/04: Re: Schematic Stuff
41684: 02/04/04: Re: Schematic Stuff
41722: 02/04/05: Re: hand placement
41723: 02/04/05: Re: hand placement
41875: 02/04/09: Re: hand placement
41915: 02/04/10: Re: hand placement
42001: 02/04/12: Re: PCI Bridge Question
42217: 02/04/18: Re: Bidirectionnal bus...multiple sources driving the same signal...
42428: 02/04/23: Re: Xilinx: IP Capture/CoreGenerator
42664: 02/04/30: Re: SpartanIIE hold timing
42735: 02/05/01: Re: SpartanII design considerations...
51704: 03/01/19: Re: Xilinx PCI core PCI-X compatible ?
52538: 03/02/12: Re: Newbie Starting Places + Books?
55504: 03/05/10: Re: help on FPGA-programming tutorial for students
55527: 03/05/11: Re: help on FPGA-programming tutorial for students
55881: 03/05/22: Re: Asynchronous State Machines and HDLs
56924: 03/06/18: Re: FPGA GPU (Spartan IIe 300K)
57502: 03/07/01: Re: Suitable motherboard for Spartan-IIE PCI design
58197: 03/07/16: Re: vertex2 pci pinout
58239: 03/07/17: Re: PCI - disabling
58240: 03/07/17: Re: PCI - disabling
58623: 03/07/29: Re: VHDL Book Recommendations Please
59407: 03/08/18: Re: Which software from Xilinx
59461: 03/08/19: Re: Which software from Xilinx
60153: 03/09/05: Re: Switching problem
60500: 03/09/15: Re: Xilinx S3 I/O robustness question
61740: 03/10/09: Re: pci-x133 to parallel pci-66
61770: 03/10/10: Re: pci-x133 to parallel pci-66
61771: 03/10/10: Re: Problems with PCI-CardbusCard (interface is an FPGA) on Windows
61826: 03/10/13: Re: PCI-X bridge from Xilinx LogiCORE and half bridge
61883: 03/10/14: Re: PCI-X bridge from Xilinx LogiCORE and half bridge
61948: 03/10/15: Re: simple project needed
61950: 03/10/15: Re: PCI-X bridge from Xilinx LogiCORE and half bridge
62352: 03/10/27: Re: SDRAM Controller
62431: 03/10/29: Re: LogiCORE PCI-X question
62725: 03/11/05: Re: FPGA Prototyping Board
62810: 03/11/07: Re: PCI - X Boot up
62827: 03/11/08: Re: 0.13u device with 5V I/O
62837: 03/11/09: Re: 0.13u device with 5V I/O
62838: 03/11/09: Re: 0.13u device with 5V I/O
62874: 03/11/10: Re: 0.13u device with 5V I/O
62876: 03/11/10: Re: 0.13u device with 5V I/O
62903: 03/11/10: Re: 0.13u device with 5V I/O
63027: 03/11/12: Re: 0.13u device with 5V I/O
63230: 03/11/18: Re: None
63231: 03/11/18: Re: PCI interface with attached PLD
63451: 03/11/21: Re: Xilinx legacy situation
63686: 03/11/29: Re: PCI LogiCORE with ISE 5.2
63812: 03/12/04: Re: Need a few tips working with an Xilinx FPGA
64083: 03/12/15: Re: datasheet needed!
64193: 03/12/19: Re: Xilinx IOSTANDARD for PCI-X 100MHz interface
64470: 04/01/05: Re: Xilinx Logicore PCI64 Problem
64779: 04/01/13: Re: logicore PCIX issue/question
64809: 04/01/14: Re: logicore PCIX issue/question
64876: 04/01/15: Re: yo, Mr. FPGA Engineer
64877: 04/01/15: Re: DMA w/ Xilinx PCIX core: speed results and question
64887: 04/01/15: Re: DMA w/ Xilinx PCIX core: speed results and question
64960: 04/01/16: Re: System Ace - Flash card formatting
65113: 04/01/20: Re: changing values in a fifo
65404: 04/01/27: Re: Which Environment for Xilinx Design?
65454: 04/01/29: Re: pci-x core/ XC2VP/ pin capacitance
65683: 04/02/04: Re: how to get a vendor id of a pci
65811: 04/02/06: Re: Xilinx WARNING:NetListWriters:117
66119: 04/02/12: Re: Help: Configure PCI Device in Windows 2k
66131: 04/02/12: Re: Xilinx FPGA Editor - can one see the switch box detail?
66652: 04/02/24: Re: CardBus prototype in FPGA
66776: 04/02/26: Re: Done Pin Remains Low after JTAG Configuration of V2Pro
67064: 04/03/04: Re: DMA PCI-X core
67280: 04/03/09: Re: sorting need help as soon as possible
67362: 04/03/10: Re: novice for FPGA
67370: 04/03/10: Re: novice for FPGA
67690: 04/03/17: Re: pcix-core target memory write
67809: 04/03/19: Re: PCI Development Board
67828: 04/03/19: Re: PCI Development Board
67842: 04/03/20: Re: PCI Development Board
67863: 04/03/21: Re: PCI Development Board
67922: 04/03/22: Re: PCI Development Board
68460: 04/04/05: Re: Can I use the Done signal in FPGA to reset my design
69063: 04/04/26: eBay auction for PCI proto board...
69065: 04/04/26: Re: pcix core master dma
69114: 04/04/27: Re: Xilinx Block RAM Init
69596: 04/05/14: Re: program flash memory through JTAG on FPGA
69775: 04/05/19: Re: Nios II Going Live...
69776: 04/05/19: Re: program flash memory through JTAG on FPGA
70126: 04/06/03: Re: tri-state in altera and xilinx
70307: 04/06/11: Re: Avoid action on very short peak on input signal (Xilinx Spartan 2)
70308: 04/06/11: Re: Problems about Using Xilinx Command Line !
70792: 04/06/28: Re: GT10_PCI_EXPRESS_n
71114: 04/07/08: Re: Xilinx Student Foundation Edition on Windows-XP ??
71364: 04/07/15: Re: Spartan3 Dev Boards
71571: 04/07/22: Re: Resources on FPGA wanted...
71651: 04/07/26: Re: PCI Core implementation in Spartan 2E FG456 package
72749: 04/08/31: Re: From good-old ISA bus cards to PCI bus
72764: 04/08/31: Re: Xilinx Spartan II and 5V PCI
73779: 04/09/29: Re: FPGAs as a PCI (target) controller
73874: 04/09/30: Re: FPGAs as a PCI (target) controller
73875: 04/09/30: Re: FPGAs as a PCI (target) controller
73876: 04/09/30: Re: FPGAs as a PCI (target) controller
73189: 04/09/15: Re: Virtex 4 released today
73198: 04/09/15: Re: Virtex 4 released today
73284: 04/09/17: Re: VHDL Design for running sorter
73292: 04/09/17: Re: Virtex 4 released today
73497: 04/09/22: Re: 5V Tolerant?
73554: 04/09/23: Re: 5V Tolerant?
75186: 04/10/28: Re: Newbie: Read from Compact Flash using System ACE
74307: 04/10/07: Re: Advice for a Beginner?
74920: 04/10/21: Re: Async reset
75593: 04/11/10: Re: Research Project Re: Graphics Processor
75847: 04/11/16: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
75874: 04/11/17: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
75899: 04/11/18: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
75900: 04/11/18: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
75937: 04/11/19: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
76563: 04/12/06: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
77338: 05/01/04: Re: documents on practicing microblaze ( ML310 ) ?
77882: 05/01/19: Re: eric
78303: 05/01/28: Re: PCI X MSI Capability (XILINX Core)
78365: 05/01/30: Re: which version PCI LogiCore for XC4000E?
78477: 05/02/01: Re: which version PCI LogiCore for XC4000E?
79115: 05/02/14: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
79523: 05/02/20: Re: VHDL State Machine - Literature
79843: 05/02/24: Re: publishing IP
80128: 05/03/01: Re: MGT RXLOSSOFSYNC problem
83642: 05/05/04: Re: Why does the optional delay element with input FF help me?
83977: 05/05/10: Re: Fake Buffers in ECS
84403: 05/05/18: Re: Xilinx IP: PCI Express
84770: 05/05/26: Re: State Machines.. and their efficiency.
85216: 05/06/06: Re: Why does RocketIO Wizard always create dual GT11 tranceiver blocks?
85225: 05/06/06: Re: Why does RocketIO Wizard always create dual GT11 tranceiver blocks?
85326: 05/06/07: Re: FPGA/CPLD trend
86032: 05/06/20: Re: 5 Volt tolerance - Altera
95600: 06/01/24: Verilog tutorial by John Sanguinetti
95761: 06/01/25: Re: Verilog tutorial by John Sanguinetti
97610: 06/02/24: Re: bypass between ilogic and ologic
103665: 06/06/07: Re: IOBDELAY's delay value
103810: 06/06/12: Re: from VHDL to FPGA
104558: 06/06/29: Re: Xilinx BUFGMUX Setup Time requirement clarification needed
104592: 06/06/30: Re: Spartan3e starter kit vga mod
104821: 06/07/06: Re: Can a BUFGMUX drive a global clock in the Spartan-3?
104869: 06/07/07: Re: PCI IOs, tiofoi, source sampling bypass
104944: 06/07/10: Re: PCI IOs, tiofoi, source sampling bypass
105289: 06/07/19: Re: Sorting algorithm for FPGA availlable?
105293: 06/07/19: Re: Which PCI core for Cyclone II board?
105643: 06/07/27: Re: Guided MAP/PAR in ISE
105650: 06/07/27: Re: Guided MAP/PAR in ISE
105909: 06/08/02: Re: Sorting algorithm for FPGA availlable?
105918: 06/08/02: Re: Sorting algorithm for FPGA availlable?
106100: 06/08/07: Re: FPGA : PCI-Xilinx Core, PC not booting
106158: 06/08/08: Re: Who is your favourite FPGA guru?
107456: 06/08/28: Re: Question on Virtex-4 CLB
107462: 06/08/28: Re: Question on Virtex-4 CLB
107665: 06/08/30: Re: Question on Virtex-4 CLB
108051: 06/09/04: Re: Virtex2Pro: Xilinx PCI core mapping error
108052: 06/09/04: Re: Virtex2Pro: Xilinx PCI core mapping error
110729: 06/10/20: Re: Xilinx PCIe 8-lane endpoint constraints
112320: 06/11/20: Re: Spartan-3E slice resources
113234: 06/12/08: Re: Query :Regarding Synthesis Report
114363: 07/01/12: Re: picoblaze RS-232 using 62.5 MHz
116617: 07/03/13: Re: WTF? - Spartan-3E starter kit with no printed board manual?
116988: 07/03/21: Re: Looking for resources on timing analysis
117017: 07/03/21: Re: Looking for resources on timing analysis
118266: 07/04/20: Re: DARNAW! - PGA Style FPGA Module
118444: 07/04/26: Re: How to configure SPI FLASH using Spartan-3E?
118494: 07/04/27: Re: How to configure SPI FLASH using Spartan-3E?
118638: 07/05/01: Re: How many Xilinx devkits does one need?
118854: 07/05/04: Re: Spartan 3A Starter Kit Multiboot Demo Config 4 Display Problem
118868: 07/05/04: Re: Spartan 3A Starter Kit Multiboot Demo Config 4 Display Problem
118895: 07/05/06: Re: Spartan 3A Starter Kit Multiboot Demo Config 4 Display Problem
119919: 07/05/29: Re: ML505 : beginners problems
120000: 07/05/30: Re: ML505 : beginners problems
121324: 07/07/02: Re: s3a kit - Use sma as signal output ?
123086: 07/08/15: Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits
123087: 07/08/15: Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits
123142: 07/08/16: Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits
124709: 07/10/01: Re: www.fpga-games.com website died?
125398: 07/10/24: Re: LEDs, buttons and LCD
125601: 07/10/29: Re: Xilinx, MIG, UCF: timing constraints for DDR2 DRAM
127993: 08/01/11: Re: Spartan 3AN LVDS I/O
127994: 08/01/11: Re: Spartan 3AN LVDS I/O
128658: 08/02/01: Re: Why use small resistor for Vcco voltage regulator
129019: 08/02/12: Re: Spartan 3A starter kit
130385: 08/03/21: Re: Spartan 3E intefacing for dummies
131513: 08/04/23: Re: Verilog state machines, latches, syntax and a bet!
134292: 08/08/04: Re: Schematic Capture tutorials/books?
Eric DELAGE:
54476: 03/04/11: Re: Dynamic Reconfigurable FPGAs
72087: 04/08/08: Re: LEGO mindstorms and FPGA
72089: 04/08/08: Re: Power Supply for Xilinx FPGA
72090: 04/08/08: Re: Comparing Quality of Results of FPGA CAD Tools
81856: 05/04/02: Re: ModelSim XE and WindowsXP
81988: 05/04/05: ISA vs. patent/trademark
81994: 05/04/05: Re: Parallelsignal at 85 MHz
81996: 05/04/05: Re: ModelSim XE and WindowsXP
82000: 05/04/05: Re: ISA vs. patent/trademark
82001: 05/04/05: Re: ISA vs. patent/trademark
82040: 05/04/05: Re: DCM LOCKED as reset
82485: 05/04/13: Re: CCD and Graphics - which FPGA?
87483: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
89844: 05/09/28: Re: Sythesis software for Virtex-4
90744: 05/10/20: Re: How to speed up the critical path (Xilinx)
Eric Dellinger:
2405: 95/11/30: Re: NeoCAD and AT&T vs. Xilinx
5564: 97/02/24: Re: Reverse Engineering FPGAs
5695: 97/03/07: Re: Reverse Engineering FPGAs
5738: 97/03/11: Re: Reverse Engineering FPGAs
Eric Doenges:
27284: 00/11/17: Re: ANNOUNCE: Checksum and CRC Code/Article
Eric Edwards:
122: 94/08/18: Re: FPGA Hobbyist and their software/programmer/hardware
178: 94/09/10: Lattice ISP software: really bad or just different?
248: 94/10/02: Re: What do think about the Intel Flexlogic8160?
417: 94/11/11: Sources for FGPA's and "exotic" PLDs?
879: 95/03/19: Re: Free Viewlogic design kits?
2309: 95/11/18: Re: [q][Reverse Engineering Protection]
2313: 95/11/19: options for VHDL or Verilog simulation/synthesis < $10,000 ?
2334: 95/11/21: Re: options for VHDL or Verilog simulation/synthesis < $10,000 ?
2505: 95/12/21: Career value: VHDL or Verilog?
2729: 96/01/31: Re: GAL programming for hobby use...Is there no hope?
2744: 96/02/01: Re: GAL programming for hobby use...Is there no hope?
2753: 96/02/02: Re: GAL programming for hobby use...Is there no hope?
2765: 96/02/04: Re: GAL programming for hobby use...Is there no hope?
3528: 96/06/15: Re: UART for Actel FPGA
3646: 96/07/07: Re: FPGA Companies
3954: 96/08/24: Re: CHEAP XILINX FPGA ROUTING SOFTWARE ?
4341: 96/10/18: What are I/O's doing prior to configuration?
4834: 96/12/19: design should fit, but it doesn't
4849: 96/12/20: Re: Exemplar's Leonardo on Linux
4965: 97/01/06: Re: design should fit, but it doesn't
4955: 97/01/04: Re: ASICs Vs. FPGA in Safety Critical Apps.
11840: 98/09/12: ASIC -> FPGA async issues
Eric Fleischman:
6572: 97/06/03: ECL FPGA Demo at DAC
6573: 97/06/03: New High-Speed FPGA - Demo at DAC
Eric Friedrichs:
21741: 00/03/30: Re: Memory cores
Eric GAUDET:
21823: 00/04/02: Re: Bitstream Format of Xilinx 4000 and Virtex Available for Download
22050: 00/04/16: Re: FPGA/PLD design tools?
Eric Hammervold:
13477: 98/12/04: Re: Will XILINX survive?
13482: 98/12/04: Re: Will XILINX survive?
Eric Holland:
74991: 04/10/23: Re: Spartan 3 - Internal busses & tristate ?
Eric Holmberg:
4409: 96/10/24: Altera FPGA's
4425: 96/10/28: Re: Altera FPGA's
4442: 96/10/29: Altera EPX880
4690: 96/11/30: Altera Max+Plus
Eric Huber:
4463: 96/11/01: Position Available - Programmable logic design
Eric Inazaki:
34118: 01/08/14: Building a clock out of a PLD
34125: 01/08/14: Re: Building a clock out of a PLD
34164: 01/08/15: Re: Building a clock out of a PLD
51650: 03/01/17: Re: Lecroy Research Systems - what happened?
51818: 03/01/22: Re: Lecroy Research Systems - what happened?
Eric J. Korpela:
14373: 99/01/27: Re: The development of a free FPGA synthesis tool
14379: 99/01/27: Re: The development of a free FPGA synthesis tool
14395: 99/01/28: Re: The development of a free FPGA synthesis tool
Eric Jacobsen:
35603: 01/10/11: Re: qpsk clock recovery
39436: 02/02/09: Re: solutions manuals, and no they are not for school
40953: 02/03/19: Re: All Digital PLL for locking DDS to input clock
56110: 03/05/28: Re: JTAG madness
56111: 03/05/28: Re: JTAG madness
56263: 03/06/02: Re: JTAG madness
62552: 03/11/01: Re: Shannon Entropy for Black Holes
90738: 05/10/19: Re: MAC Architectures
107645: 06/08/30: Re: Performance Appraisals
107710: 06/08/31: Re: Performance Appraisals
133950: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
133965: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
139366: 09/03/27: Re: FIFO controlled loop, PLL, FLL or something else?
139381: 09/03/27: Re: FIFO controlled loop, PLL, FLL or something else?
139408: 09/03/28: Re: FIFO controlled loop, PLL, FLL or something else?
141486: 09/06/25: Re: 720 Mhz IF Processing
152834: 11/10/26: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152843: 11/10/26: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152851: 11/10/27: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152854: 11/10/28: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152866: 11/10/28: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152876: 11/10/29: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152886: 11/10/29: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152908: 11/10/31: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152915: 11/10/31: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152920: 11/11/01: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152970: 11/11/06: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152980: 11/11/07: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152981: 11/11/07: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152989: 11/11/08: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152992: 11/11/08: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
153051: 11/11/23: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
153071: 11/11/25: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
Eric Jay Crabill:
4191: 96/09/24: FS: Data IO MESA-I
6709: 97/06/18: Re: Help: Interfacing a Xilinx 4k to a microprocessor
"Eric Jeandeau":
29074: 01/02/05: Handel-C language.
29130: 01/02/07: Re: Re: Handel-C language.
Eric K. Ka-shu Ko:
1263: 95/05/23: Re: PLDShell Plus
Eric Kim / ±èÀÀȯ:
8669: 98/01/20: Do you know ATMEL?
Eric Kral:
42190: 02/04/18: Bidirectionnal bus...multiple sources driving the same signal...
Eric L:
23393: 00/06/23: a lot of basic questions - where's the FAQ?
23398: 00/06/24: Re: a lot of basic questions - where's the FAQ?
23429: 00/06/24: Re: a lot of basic questions - where's the FAQ?
23430: 00/06/24: Re: a lot of basic questions - where's the FAQ?
23447: 00/06/25: Re: a lot of basic questions - where's the FAQ?
23552: 00/06/29: Buying Xilinx Chips online?
23795: 00/07/09: Xilinx Data memory
24298: 00/08/03: models of digital ICs
Eric LaForest:
26917: 00/11/03: Re: cryptography/Block ciphers
35822: 01/10/18: XST verilog synthesis of Virtex-II BlockRAM
Eric Lewis:
32138: 01/06/15: Re: Xilinx Virtex 2: Configurations problems
32149: 01/06/15: Re: Xilinx Virtex 2: Configurations problems
32505: 01/06/28: Re: Xilinx Virtex 2: Configurations problems
Eric Lo:
8597: 98/01/12: VHDL to GigaOps
Eric Lukac-Kuruc:
38313: 02/01/11: Actel Libero for ProAsic in big trouble?
Eric Lussier:
9805: 98/04/06: Effects of IC production
Eric McCaughrin:
3505: 96/06/11: Re: %% Trolling For DAC Dirt... From Users & The "Dark Side" %%
Eric Montreal:
26427: 00/10/16: Asynchronous pulse generation with Spartan.
26465: 00/10/17: Re: Asynchronous pulse generation with Spartan.
26557: 00/10/20: Mailbox (was "Asynchronous pulse generation with Spartan.")
26566: 00/10/20: Re: Mailbox (was "Asynchronous pulse generation with Spartan.")
26599: 00/10/21: Re: 12C508 / SX20 / AVR security from pirating an FPGA
26428: 00/10/16: Asynchronous pulse generation with Spartan.
26928: 00/11/03: Re: Need a PCB speaker driven by XCV100
27354: 00/11/19: Rambus Reveals Plans To Collect Royalties From Chipset Makers
27410: 00/11/21: Re: Rambus Reveals Plans To Collect Royalties From Chipset Makers
27412: 00/11/21: Re: In the news
29183: 01/02/09: Re: Xilinx vs Altera
29184: 01/02/09: Re: Xilinx vs Altera
29244: 01/02/11: Re: any idea ?
29281: 01/02/12: Re: any idea ?
29666: 01/03/04: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
Eric Mullaley:
35406: 01/10/03: Virtex II DCM: Phase Shifting
Eric Page:
4218: 96/09/30: money maker
Eric Paillet:
61717: 03/10/09: Re: Programmimg Altera serial configuration devices
68514: 04/04/07: Re: Cyclone and ByteBlasterMV?
Eric Pearson:
170: 94/09/08: GigaOps video-compute-engine
1574: 95/07/19: Re: ACTEL PLACE AND ROUTE
2502: 95/12/20: Re: UART in PLD
3032: 96/03/18: Re: experience with Actel Act2 family
4266: 96/10/07: Re: Q on Xilinx/Viewsim macros
4541: 96/11/11: Re: Actel Designer and Win NT 4.0
5267: 97/02/03: Re: Suggestions how wire wrap mount a Xilinx PG223
8449: 97/12/16: Re: bus design in Altera 10K, how to increase speed
8832: 98/01/30: Re: MAX+II Version 8.2
12303: 98/10/08: Altera MAXPLUS2 V9 slow.
12809: 98/10/30: Re: Altera MAXPLUS2 V9 slow .
13345: 98/11/27: Re: Combining busses Xilinx
18618: 99/11/03: Re: WEB reconfigurable FPGA, How?
23056: 00/06/12: Re: Readout of an FPGA?
23488: 00/06/27: Re: JTAG emulation of TI DSPs
23958: 00/07/18: Re: Altera fitter woes
23960: 00/07/18: Re: Altera fitter woes
24241: 00/07/31: Re: Look-up tables in Altera
24256: 00/08/01: Re: Look-up tables in Altera
24264: 00/08/01: Re: Look-up tables in Altera
24313: 00/08/03: Re: 32-input AND and 100-input OR - can I do it fast?
25790: 00/09/20: Re: VHDL to SCHEMATIC
27625: 00/11/30: Re: high level timing by C generated VHDL?
30307: 01/04/02: Re: pseudo random numbers
37590: 01/12/16: Re: Certicom challenge and FPGA based modular math
37708: 01/12/19: Re: Divide by 3, with remainder, efficient and fast, for Altera or Xilinx
37936: 01/12/25: Re: Where could I get a signal waveform editor?
39890: 02/02/21: Re: Here is an argument and can anyone help me out
42159: 02/04/17: Re: Virtex Development Board with a 4M or more gates
45714: 02/08/02: Re: clock timing
49095: 02/10/31: Re: BLOCK RAM : FIFO implementation
51079: 02/12/30: Re: interface DRAM to FPGA
51123: 03/01/02: Re: interface DRAM to FPGA
52450: 03/02/10: Re: JBits
52501: 03/02/11: Re: JBits
54384: 03/04/09: Re: Clock Doubled domain
54731: 03/04/16: Re: Clock Doubled domain
54752: 03/04/17: Re: Clock Doubled domain
58474: 03/07/24: Re: FPGA Editor
Eric Rose:
3066: 96/03/25: LOG/iC Installation Problem
Eric Ryherd:
2755: 96/02/02: Re: VHDL Microcontroller Model
2809: 96/02/11: Re: PIC16C71 CORE for XC4000 ?
2810: 96/02/11: Re: 8274 Inside FPGA?
2827: 96/02/13: Re: FPGA density
2892: 96/02/25: Re: PCI models synthesized to FPGAs?
2893: 96/02/25: Re: Xilinx 8100 Series
3212: 96/04/26: FPGA leaders - Who are they? Xilinx, Altera, Actel?
3319: 96/05/13: Xilinx 4013 80% utilized but won't route
5687: 97/03/06: Re: Rising_Edge/Falling_Edge Functions
5959: 97/03/31: Re: Any FPGA with 6809 core?
6275: 97/05/07: Xilinx .UCF file examples
6301: 97/05/12: Re: Xilinx .UCF file examples
6699: 97/06/16: Re: XCHECKER Download to Xilinx 9500 CPLDs
7484: 97/09/16: 6809 discontinued
7514: 97/09/18: Atmel 17256 serial config EEPROMs
7513: 97/09/18: Re: 6809 discontinued
8686: 98/01/20: Xilinx byte wide ROM builder up to 4K bytes
11036: 98/07/13: Dataio Chipwriter won't burn Altera EPC1 generated with Maxplus2 8.2 or greater???
11316: 98/08/04: Re: Silicore VHDL 8-bit RISC uC core for FPGA
12498: 98/10/13: Re: Processor Cores
eric schonning:
2607: 96/01/10: Re: [q][Reverse Engineering Protection]
Eric Smith:
411: 94/11/11: Re: about downloading FPGAs
412: 94/11/11: Re: about downloading FPGAs
1972: 95/09/27: Re: Alliance, FPGA's, VHDL code......
3133: 96/04/10: Re: Sun bpp bidirectional parallel port
24367: 00/08/04: Re: Memory specification
25357: 00/09/07: Re: Permanently programming FPGAs
25306: 00/09/05: Re: Model for 8101 - 8104
25358: 00/09/07: Re: Cypress Delta39K availability
25642: 00/09/15: Re: hardware compatibility and patent infringement
25744: 00/09/18: Xilinx software licensing (was Re: MAX PLUS 2)
25902: 00/09/25: Difference between Foundation Base and Foundation ISE Base Express?
26644: 00/10/23: Re: RS422 interfacing to a FPGA ?
26660: 00/10/23: Re: RS422 interfacing to a FPGA ?
26661: 00/10/23: Re: New PACT 50 GOP Reconfigurable Processor
26954: 00/11/04: Re: Alliance under Linux?
26896: 00/11/02: Re: OT: Xilinx T-Shirt
27029: 00/11/07: Re: Spartan2 macros in WebPACK
27149: 00/11/13: Re: Spartan-II with 5V ISA bus
27174: 00/11/13: Re: Spartan-II with 5V ISA bus
27265: 00/11/16: Re: ANNOUNCE: Checksum and CRC Code/Article
27277: 00/11/16: Re: can FPGA perform float point calculaton?
27677: 00/12/01: Re: Virtex ROM ques.
27766: 00/12/06: JBits, Xilinx customer "support" (was Re: Virtex ROM ques.)
27777: 00/12/07: Re: JBits, Xilinx customer "support" (was Re: Virtex ROM ques.)
27734: 00/12/05: Re: Issues with Spartan II
27816: 00/12/09: Re: Linear Regulator troubles
28349: 01/01/08: Re: Alliance for Linux
28374: 01/01/10: Re: grey code counters
28474: 01/01/14: Re: Please explain these terms
28475: 01/01/14: Re: revision control tools ??
28548: 01/01/16: Re: revision control tools ??
28549: 01/01/16: Re: Oscillator for FPGA - low cost
28602: 01/01/17: Re: revision control tools ??
28661: 01/01/19: Re: Alliance for Linux
28802: 01/01/24: Re: Encryption is supported in new Virtex II but.....
28812: 01/01/24: Re: Encryption is supported in new Virtex II but.....
29091: 01/02/05: Re: Rijndael
29179: 01/02/08: Re: on making it too convenient to download PDFs
29181: 01/02/08: Re: Xilinx vs Altera
29215: 01/02/09: Re: Xilinx vs Altera
29471: 01/02/22: Re: Virtex II availability
29472: 01/02/22: Re: Virtex E:Sample price
29507: 01/02/23: Re: Samll quantities ordering
29584: 01/02/27: Re: Samll quantities ordering
29655: 01/03/03: Re: Bad Xilinx bitstream=big bang?
29657: 01/03/03: Re: Virtex II availability
29661: 01/03/04: webpack ISE synthesis fails with exit code: 0002
29673: 01/03/04: Re: webpack ISE synthesis fails with exit code: 0002
29694: 01/03/05: Re: webpack ISE synthesis fails with exit code: 0002
29696: 01/03/05: Re: Bad Xilinx bitstream=big bang?
29736: 01/03/06: More detailed Spartan II CLB drawings?
29757: 01/03/07: Re: More detailed Spartan II CLB drawings?
29770: 01/03/08: Foundation ISE Evaluation Kit - how to order?
29771: 01/03/08: Re: Foundation ISE Evaluation Kit - how to order?
29776: 01/03/08: JBits on Red Hat 7.0? (was Re: More detailed Spartan II CLB drawings?)
29787: 01/03/09: Re: Spartan-II Evaluation Board
29803: 01/03/11: sample code for JTAG configuration of Virtex, Spartan II?
29921: 01/03/16: Re: xilinx Webpack missing speed grade
29973: 01/03/19: Re: xilinx Webpack missing speed grade
30085: 01/03/22: Re: Looking for Processor Core info/advice
30132: 01/03/24: Re: How to find out where par placed things?
30135: 01/03/24: Re: How to find out where par placed things?
30281: 01/03/30: Re: Reed/Solomon ENcoder
30323: 01/04/02: Re: Reed/Solomon ENcoder
30658: 01/04/21: Re: Hobbiest + LINUX
30933: 01/05/03: Re: Shannon Capacity
30934: 01/05/03: Re: Shannon Capacity
31066: 01/05/10: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31074: 01/05/10: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31087: 01/05/11: Re: Asynchronous Compare
31106: 01/05/11: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31140: 01/05/12: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31221: 01/05/15: Re: FREE IP CORES
31542: 01/05/29: Re: Peripheral for Microcontroller
31656: 01/06/01: Re: Xilinx XC4010E Problem
31785: 01/06/05: Re: Help in FIFO design
31790: 01/06/05: Re: Help in FIFO design
31837: 01/06/06: Re: Help in FIFO design
31846: 01/06/06: Re: Help in FIFO design
31847: 01/06/06: Re: Help in FIFO design
31883: 01/06/07: Re: Help in FIFO design
31903: 01/06/07: Re: system clock speed
32145: 01/06/15: efficient CAM in Virtex or Spartan II?
32562: 01/06/30: Re: obfuscated tools
32578: 01/06/30: Re: Newbee and FAQ
32579: 01/06/30: Re: xr16vx: a GPL 16-bit xr16 microcontroller in JHDL
32592: 01/07/01: Re: xr16vx: a GPL 16-bit xr16 microcontroller in JHDL
32806: 01/07/09: Re: What chip!?
32870: 01/07/10: Re: What chip!?
32881: 01/07/10: Re: Large Power up Current on Spartan2
33067: 01/07/16: Re: I NEED XILINX FOUNDATION PROFESSIONAL
33236: 01/07/19: Re: foundation series 2.1i
33261: 01/07/20: Re: Modulator Sizing Questions
33462: 01/07/27: Re: Opinions on cypress warp 6.1 and devices?
33474: 01/07/27: Re: Opinions on cypress warp 6.1 and devices?
33610: 01/07/31: Re: computer science Vs Computer Enginnering
34239: 01/08/16: hardware damage to a Virtex or Spartan-II?
34270: 01/08/17: Re: hardware damage to a Virtex or Spartan-II?
34453: 01/08/24: Re: PCI Postcode Display
34606: 01/08/30: Re: WebPack Con-Game
34612: 01/08/30: Re: WebPack Con-Game
34613: 01/08/30: Re: Defending Austin Franklin
34637: 01/08/31: Re: WebPack Con-Game
34638: 01/08/31: Re: Jbits: more info required
34644: 01/08/31: Re: WebPack Con-Game
34737: 01/09/05: Re: WebPack Con-Game
35164: 01/09/24: Re: comp.arch.fpga : Unusual clock divider ckt
35166: 01/09/24: WebPack ISE 4.1 is out
35167: 01/09/24: Spartan-IIE?
35194: 01/09/25: Re: FPGA with embedded Memory
35295: 01/09/27: Re: Spartan-IIE?
35296: 01/09/27: Re: Opinions on cypress warp 6.1 and devices?
35953: 01/10/24: Re: S/PDIF interface for FPGA
36000: 01/10/25: Re: S/PDIF interface for FPGA
36043: 01/10/26: Re: Cloning someone else's IP core
36055: 01/10/26: Re: Cloning someone else's IP core
36097: 01/10/29: Re: Cloning someone else's IP core
36328: 01/11/06: Re: Counter detects both edge of clock?? (verilog)
36632: 01/11/13: Re: Reassemble a BGA560 device
36901: 01/11/23: Re: wget of WebPack
37151: 01/12/01: Re: Is there a full open-source synthesis path for any FPGA?
37272: 01/12/05: Re: where is designed FPGA for apple II computer...?
37301: 01/12/06: Re: where is designed FPGA for apple II computer...?
37383: 01/12/08: Re: I need a Xilinx Spartan PCI Development Board
37427: 01/12/10: Re: where is designed FPGA for apple II computer...?
37498: 01/12/12: Re: Initialization of RAM
37499: 01/12/12: Re: xilinx ise 4
37810: 01/12/20: Re: Spartan-IIE schematic symbol?
37999: 01/12/29: Re: How to set block ram contents ?
38097: 02/01/04: Re: PCI Solution: LogiCore?
38169: 02/01/07: Re: 128 bit compare delay kill me!
38192: 02/01/08: Re: latch vs. register
38193: 02/01/08: Re: S-video -> VGA
38568: 02/01/17: Re: Audio time delay circuit
38571: 02/01/17: Re: Audio time delay circuit
38680: 02/01/21: Re: Signal processing using FPGAs
38954: 02/01/28: Re: Homebrew computers using FPGA?
39066: 02/01/30: Re: glitchless clock enable/disable in spartanII
39485: 02/02/11: Re: Altera's new family Stratix
39630: 02/02/14: Re: SpartanXL & VHDL -- free software?
39681: 02/02/15: Re: SpartanXL & VHDL -- free software?
39786: 02/02/19: Re: Whether an FPGA & CPLD device has been spoiled.
39850: 02/02/21: Re: Need good PCI book
39898: 02/02/21: Re: EDIF to .bit file conversion for Xilinx Spartan XCS10
39899: 02/02/21: Re: EDIF to .bit file conversion for Xilinx Spartan XCS10
40693: 02/03/12: IBIS simulation (was Re: max frequency of obuf_lvdci_dv2_18)
42033: 02/04/13: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
42438: 02/04/23: Re: sharing SDRAM between processor and VirtexII?
42480: 02/04/24: Re: Using 74HCT245N between Spartan-II and ISA
42556: 02/04/27: Re: Hack an bitstream file for AT40Kxx
43162: 02/05/15: Life Support (was Re: Architecture for high-level reconfigurable computing)
45547: 02/07/25: Re: TMS 1000
45588: 02/07/27: Re: ALU in VHDL and a bunch of questions
46031: 02/08/14: Re: "flip flop" and "register"
46032: 02/08/14: Re: Reed-Solomon polynom transform....
46134: 02/08/19: Re: I2C License
46255: 02/08/22: Re: Downloading bit streams in Xilinx
46363: 02/08/26: Spartan-II inrush and other power suppy isues (was Re: need cheap and dirty time delay for spartan2e)
46476: 02/08/31: Re: Spartan-II inrush and other power suppy isues (was Re: need cheap and dirty time delay for spartan2e)
46576: 02/09/03: Re: why Xilinx does not make its own HDL synthesiser?
46665: 02/09/05: Re: QUARTUS II V2.1 LINUX (C) ALTERA
47497: 02/09/26: Re: Xilinx will not provid free ISE Allanice 5.1i?
47499: 02/09/26: Re: Altera Cyclone 'FPGA'
47680: 02/10/01: Re: USB2 in FPGA?
47681: 02/10/01: Re: Implementing Delta-Sigma ADC and DAC in Spartan IIE
48471: 02/10/17: Re: Intel ARM 'XScale' cores as IP blocks that can be synthesized into an FPGA/ASIC?
48556: 02/10/20: Re: Virtex2 5V tolerant I/O ??
48907: 02/10/26: Re: Virtex2 5V tolerant I/O ??
48908: 02/10/26: Re: FPGA XC4005E
48909: 02/10/26: Re: Microblaze
48910: 02/10/26: Re: 6809 FPGA
49108: 02/10/31: Re: FPGA XC4005E
49329: 02/11/08: Re: Spartan I with ISE Webpack
49568: 02/11/15: Webpack and Virtex Pro?
49723: 02/11/19: Re: Webpack and Virtex Pro?
50357: 02/12/09: Re: FPGA/PCI on low budget
50446: 02/12/10: Re: ISA bus VGA
50601: 02/12/13: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
51293: 03/01/09: Re: FPGA accelerated FPGA/ASIC tools
51536: 03/01/15: Re: Schematic design approach compared to VHDL entry approach
51541: 03/01/15: Re: Schematic design approach compared to VHDL entry approach
51590: 03/01/16: Re: Schematic design approach compared to VHDL entry approach
51644: 03/01/17: Re: Schematic design approach compared to VHDL entry approach
51661: 03/01/17: Re: Schematic design approach compared to VHDL entry approach
51690: 03/01/19: Re: Schematic design approach compared to VHDL entry approach
51702: 03/01/19: Re: Schematic design approach compared to VHDL entry approach
51703: 03/01/19: Re: A Request: VHDL Source of a 32bit Floating Point ALU
51725: 03/01/20: Re: Schematic design approach compared to VHDL entry approach
51726: 03/01/20: Re: Schematic design approach compared to VHDL entry approach
51825: 03/01/22: Re: Schematic design approach compared to VHDL entry approach
51826: 03/01/22: Re: Problem with XST libraries.
51827: 03/01/22: Re: Problem with XST libraries.
51828: 03/01/22: What's a "D-MIPS"?
51866: 03/01/23: Re: What's a "D-MIPS"?
52387: 03/02/07: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
52575: 03/02/13: Re: which microprocessor core?
52952: 03/02/26: Re: New release of Xilinx ISE tools (5.2)
53101: 03/03/03: Re: PCI specification doubt
53897: 03/03/26: Re: Cypress Users Anyone?
53898: 03/03/26: Re: triple des
53899: 03/03/26: Re: where is SMC34c60 similar IP ?
54119: 03/04/02: 2.5V switching regulator for Spartan 2
54162: 03/04/03: Re: uP interface question
54229: 03/04/04: Re: Cyclone power up problem - 'Engineerus Emptor'
54267: 03/04/06: Re: 2.5V switching regulator for Spartan 2
54268: 03/04/06: Re: Spartan-3 in docsan Webpack release notes... a joke???
54353: 03/04/08: Re: 2.5V switching regulator for Spartan 2
54429: 03/04/10: Re: Cheap(er) FPGA configuration?
54430: 03/04/10: Ethernet MAC (was Re: Cheap(er) FPGA configuration?)
54431: 03/04/10: Re: Webpack 5.2 and Win98se
54433: 03/04/10: Re: Webpack 5.2 and Win98se
54503: 03/04/11: Re: Webpack 5.2i download
54590: 03/04/14: Re: Xilinx has released SpartanIII
54591: 03/04/14: Re: Xilinx has released SpartanIII
54596: 03/04/14: Re: Testing engineering ability prior to work?
54730: 03/04/16: Re: 2.5V switching regulator for Spartan 2
54776: 03/04/17: Re: 2.5V switching regulator for Spartan 2
54948: 03/04/22: Re: Virtex2 and Logic Analyzer
54994: 03/04/23: Re: Virtex2 and Logic Analyzer
55324: 03/05/04: Re: 802.11
55325: 03/05/04: Re: PLL chips
55677: 03/05/15: Re: Low power, high temperature CPLD
56098: 03/05/28: Re: JTAG madness
56243: 03/05/31: Re: DES-encrypt, Spartan3, was Re: FPGA's an Flash
56498: 03/06/06: Re: spartan2e vs cyclone
56499: 03/06/06: Re: Xilinx Block RAM
56504: 03/06/06: Re: Xilinx Block RAM
56861: 03/06/17: Re: Simple FEC algorithm
56959: 03/06/19: Re: Cyclone vs. Acex consumption?
57103: 03/06/23: Re: MIPS instruction set?
57124: 03/06/23: Re: MIPS instruction set?
57125: 03/06/23: Re: MIPS instruction set?
58553: 03/07/25: Re: device selection for game system
58576: 03/07/27: Re: device selection for game system
58683: 03/07/30: Mentor Hyperlynx IBIS simulator (was Re: Spartan IIE max pin switching)
58692: 03/07/30: Re: Mentor Hyperlynx IBIS simulator (was Re: Spartan IIE max pin switching)
58811: 03/08/01: Re: Mentor Hyperlynx IBIS simulator (was Re: Spartan IIE max pin switching)
59354: 03/08/15: Re: Old Xilinx FPGAs
59364: 03/08/16: Re: Old Xilinx FPGAs
60340: 03/09/10: Re: Spartan-3 3S50 in Web ISE 5.2i = no block RAM, no multiplier?
60910: 03/09/24: Re: ISE 6.1 and Redhat 9
60915: 03/09/24: Re: Configuration Options:
60954: 03/09/25: Re: ISE 6.1 and Redhat 9
61161: 03/09/29: Re: OT: spam poll
61904: 03/10/14: Re: Electronic Dice ( 3 die ) In VHDL
61906: 03/10/14: Re: Electronic Dice ( 3 die ) In VHDL
62025: 03/10/16: Spartan-3 non-ES availability, and misleading pricing info
62030: 03/10/16: Re: Spartan-3 non-ES availability, and misleading pricing info
62240: 03/10/22: Re: VHDL Souce Code Beautifiers
62906: 03/11/10: Re: Announcement
63821: 03/12/04: Re: Slightly unmatched UART frequencies
63822: 03/12/04: Re: Slightly unmatched UART frequencies
63823: 03/12/04: Re: Slightly unmatched UART frequencies
63824: 03/12/04: Re: Slightly unmatched UART frequencies
64172: 03/12/18: Re: Spartan3 availability
64197: 03/12/19: Re: Spartan3 availability
65115: 04/01/20: Re: BIST FPGA testing - Applying a test vector
65524: 04/02/01: Re: New USB chip for fast FPGA bitstream download
65809: 04/02/06: Re: Pricing, 101
66200: 04/02/13: Re: regarding opto isolators
66457: 04/02/19: Re: Plea for help - 29PL141
66998: 04/03/03: Re: Does iseWebPack 6.2w has FPGA-Editor inside?
67297: 04/03/09: Re: copy protection on FPGA using embedded serial number
68200: 04/03/29: Re: Question : Serial PROM
68295: 04/03/31: Re: rs232 interface on nios
69201: 04/04/29: Re: package choice, temperature and obsolesence issues with a xilinx fpga
69229: 04/04/30: Re: SpyGlass Software
69845: 04/05/21: Re: Nios II Going Live...
70010: 04/05/26: Re: Altium FPGA board
70236: 04/06/09: Re: Hardware implementation of the Xilinx configuration CRC generator
71154: 04/07/09: Re: comparison between FPGA and computer
71915: 04/08/03: Re: Spartan 3 errata and pricing
72333: 04/08/15: Re: let me have logic design for traffic light
72354: 04/08/16: Xilinx VQ100 package drawings?
72809: 04/09/02: Re: Spartan 3 Starter Kit and ISE WebPACK
72838: 04/09/03: Re: Completed my first Virtex4 design
74989: 04/10/22: Re: Webpack 6.3i support for Spartan 3
75129: 04/10/26: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
74597: 04/10/14: WebPACK post-PAR min clock period?
74614: 04/10/14: Re: WebPACK post-PAR min clock period?
74645: 04/10/15: Re: WebPACK post-PAR min clock period?
74769: 04/10/18: Re: WebPACK post-PAR min clock period?
74770: 04/10/18: Re: WebPACK post-PAR min clock period?
74771: 04/10/18: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
74813: 04/10/19: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
74866: 04/10/20: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
74883: 04/10/20: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
75848: 04/11/16: 5V inputs with series resistor on Spartan-3
75867: 04/11/17: Re: 5V inputs with series resistor on Spartan-3
75902: 04/11/18: Ordering Xilinx BaseX software for Linux
75903: 04/11/18: Re: 5V inputs with series resistor on Spartan-3
75941: 04/11/19: Re: digital analog conversion
77073: 04/12/21: Re: Using low-core-voltage devices in industrial applications
77122: 04/12/23: Re: Using low-core-voltage devices in industrial applications
77299: 05/01/03: Using LM317S adjustable linear regulator for Spartan 3?
77327: 05/01/04: Re: Using LM317S adjustable linear regulator for Spartan 3?
77341: 05/01/04: Re: Using LM317S adjustable linear regulator for Spartan 3?
77356: 05/01/05: Re: Using LM317S adjustable linear regulator for Spartan 3?
77357: 05/01/05: Re: Using LM317S adjustable linear regulator for Spartan 3?
77444: 05/01/06: Re: San Jose job offer - need advice
77551: 05/01/10: Re: San Jose job offer - need advice
77626: 05/01/12: Re: Starting with xilinix and Linux
77670: 05/01/13: Re: Programming and copyright
77671: 05/01/13: Re: Starting with xilinix and Linux
78017: 05/01/22: WebCase problem
78018: 05/01/22: Re: Microscope examination of a PLD
78311: 05/01/28: Re: Copying/Reverse Engineering PAL
78312: 05/01/28: Re: EDK 6.3 Eval with Spartan 3 Starter Kit
78313: 05/01/28: Re: lowest-cost FPGA and CPLD
78424: 05/01/31: Re: Using LM317S adjustable linear regulator for Spartan 3?
78425: 05/01/31: Re: i need xilinx edk
79002: 05/02/10: Re: Writing IP-Cores while sleeping ;)
79003: 05/02/10: Re: Writing IP-Cores while sleeping ;)
79046: 05/02/11: Re: Writing IP-Cores while sleeping ;)
79047: 05/02/11: Re: Writing IP-Cores while sleeping ;)
79611: 05/02/21: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40 !
80038: 05/02/28: Re: Maximum Current utilized by Spartan-3
80239: 05/03/02: Re: Xilinx ISE history?
80240: 05/03/02: Re: Xilinx ISE7.1
80327: 05/03/03: Re: Xilinx ISE7.1
80394: 05/03/04: Re: Maximum Current utilized by Spartan-3
80403: 05/03/04: Re: Maximum Current utilized by Spartan-3
80528: 05/03/07: Re: state encoding in FSM for simple cases ?
80605: 05/03/08: Re: Async FIFO problem...
80828: 05/03/11: Re: Xilinx ISE7.1
80885: 05/03/13: Re: (Stupid/Newbie) Question on UART
80926: 05/03/14: Re: Xilinx ISE7.1
80927: 05/03/14: Re: Xilinx ISE7.1
80928: 05/03/14: Re: (Stupid/Newbie) Question on UART
80996: 05/03/15: Re: (Stupid/Newbie) Question on UART
81046: 05/03/16: Re: Filename of Webpack 7.1 installer on linux (anyone who got it on CD?)
81117: 05/03/17: Re: Performance evaluation of Distributed Arithmetic architectures for FIR filters
81327: 05/03/21: Re: ISE 7.1 WebPack + EDK 6.3
81329: 05/03/21: Re: PAL problems (again)
81330: 05/03/21: Re: ISE Foundation/BaseX 7.1i evaluation for Linux
81863: 05/04/02: Re: Open PowerPC Core?
81920: 05/04/04: Re: Open PowerPC Core?
82013: 05/04/05: Re: Open PowerPC Core?
82014: 05/04/05: Re: Open PowerPC Core?
82085: 05/04/06: Re: ISA vs. patent/trademark
82086: 05/04/06: Re: ISA vs. patent/trademark
82087: 05/04/06: Re: ISA vs. patent/trademark
82213: 05/04/08: Re: ISA vs. patent/trademark
82216: 05/04/08: Re: Hey Xilinx
82217: 05/04/08: Reverse engineering masked ROMs, PLAs
82235: 05/04/08: Re: Reverse engineering masked ROMs, PLAs
82274: 05/04/10: Re: where can i get xilinx ise 7.1 evalution ?
82516: 05/04/13: Re: ISE 7.1 for 64 bit Linux ???
82603: 05/04/14: Re: ISE 7.1 for 64 bit Linux ???
82604: 05/04/14: Re: Xilinx VIIPro power supplies
82669: 05/04/15: Re: ISE 7.1 GUI (slightly OT)
82760: 05/04/17: Re: salary ballpark please guys
82825: 05/04/18: Re: Xilinx tools on Linux
82840: 05/04/18: Re: Xilinx tools on Linux
82841: 05/04/18: Re: Xilinx tools on Linux
82842: 05/04/18: Re: source control and Xilinx ISE 6 and 7
82848: 05/04/18: Re: source control and Xilinx ISE 6 and 7
82851: 05/04/18: Re: source control and Xilinx ISE 6 and 7
82920: 05/04/19: Re: Xilinx tools on Linux
82921: 05/04/19: Re: source control and Xilinx ISE 6 and 7
83039: 05/04/21: Re: FIFO as a Logic Analyzer; Clock synthesizer
83188: 05/04/25: Re: New FPGA Development Board
83268: 05/04/26: Re: How do I convert binary data from Agilent logic analyzer 16702 into plain text?
83592: 05/05/03: Re: Xilinx tools from the commandline
83806: 05/05/06: Re: Which chip should I use?
84418: 05/05/18: Re: IP core supply
84553: 05/05/20: Re: ISE and Linux
84630: 05/05/23: Re: ISE and Linux
85543: 05/06/10: Re: computer upgrade time.
86268: 05/06/23: Spartan-3e order of availability?
86324: 05/06/24: Re: Need help for Xilinx FPGA
86795: 05/07/06: Re: Spartan II 2s200 PCI Board
88425: 05/08/17: Re: Fastest way to compute floating point log and exp
88427: 05/08/17: Re: Digilent's JTAG-USB cable with chipscope
88941: 05/08/31: Re: Welcome back Mr. Knapp
88942: 05/08/31: Re: FPGA Development Board Wish List
88943: 05/08/31: Re: xilinx or digilent
89154: 05/09/06: Spartan-3E Starter Kit availability slips to December
90473: 05/10/13: Re: ISE 7.1i & Linux / reg code question
90494: 05/10/14: Re: How to Reduce Interconnects (VDD and VSS)
90775: 05/10/20: Re: Simple PWM Spartan 3
90787: 05/10/20: Re: EDK on Virtex4 FX using embedded ethernet MAC
90951: 05/10/25: 7.1i on Linux installation saga
91179: 05/10/31: Re: Spartan-3E starter kit
91180: 05/10/31: Re: ISE 8.1, EDK 8.1 any pre-release info available?
91181: 05/10/31: Re: Why are there two patents with same title
91228: 05/11/01: Re: ISE 8.1, EDK 8.1 any pre-release info available?
91277: 05/11/02: Re: FPGA : PCI core needed
91279: 05/11/02: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91280: 05/11/02: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91284: 05/11/02: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91295: 05/11/02: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91296: 05/11/02: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91489: 05/11/07: Re: Why Spartan-3e is the best
91490: 05/11/07: Re: Spartan-3E starter kit
91494: 05/11/07: ISE 8.1 news--BaseX going away, but WebPack gains devices and features
91617: 05/11/09: Re: Why Spartan-3e is the best
91688: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91698: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91699: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91703: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91704: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91709: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91754: 05/11/11: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91915: 05/11/16: Re: ISE SP4 installer on Linux
92517: 05/11/30: Xilinx LUT behavior question
92518: 05/11/30: Re: Q-bus or Unibus bus transactions in FPGA?
92519: 05/11/30: Re: ISE Simulator not present in Linux?
92579: 05/12/01: Re: Xilinx LUT behavior question
92580: 05/12/01: Re: Xilinx LUT behavior question
92847: 05/12/07: Re: I2C controller chipset to interface with FPGA
92888: 05/12/08: Re: I2C controller chipset to interface with FPGA
92954: 05/12/09: Re: ISE purchase
92962: 05/12/09: Re: ISE purchase
92964: 05/12/09: Re: ISE purchase
93116: 05/12/13: Re: ISE WebPack 8.1i
93227: 05/12/15: ISE 8.1i on Fedora Core 4 (64-bit)
93231: 05/12/16: Re: ISE 8.1i on Fedora Core 4 (64-bit)
93422: 05/12/21: Re: More beginner's verilog questions
93428: 05/12/21: Re: lpc922
93447: 05/12/22: Re: lpc922
93820: 05/12/31: Re: Brute Force Examination of a PLD
93875: 06/01/02: Re: Why 'a plurality of N' must be used for 'N' in patent claims
94502: 06/01/12: Re: ISE 8.1i WebPack available
94590: 06/01/13: Re: FPGA Journal Article
95381: 06/01/23: Re: FPGA Journal Article
94592: 06/01/13: Re: FPGA Journal Article
94869: 06/01/18: Re: FPGA Journal Article
94600: 06/01/13: Re: Don't even get me started on lead,
94657: 06/01/16: Re: Don't even get me started on lead,
94594: 06/01/13: Re: FPGA Altair Advice
94656: 06/01/16: Re: FPGA Altair Advice
94597: 06/01/13: Re: how do I minimize the logic in this function?
94595: 06/01/13: Re: Attack of the clones
94658: 06/01/16: Re: Any FPGA with programming info available?
94784: 06/01/17: Re: PCI arbiter doubt
94785: 06/01/17: Re: S3e slower than S3
95727: 06/01/25: Re: ISE8.1 on Linux, first impressions
94870: 06/01/18: Spartan-3E MultiBoot (was Re: xilinx free Sample Pack info now also on Xilinx own webpages)
95175: 06/01/21: Re: EDK 8.1, Finally!
95730: 06/01/25: Re: help:dual-edge flip-flop possible using Verilog?
95732: 06/01/25: Re: encryption
95734: 06/01/25: Re: Spartan-3 Starter Board
95905: 06/01/26: Re: Stop. Go. Yield.
96014: 06/01/27: Re: EDK 8.1 ... delay
96211: 06/01/31: Re: Xilinx Legal
96468: 06/02/03: Re: FPGA ogg Vorbis/Theora player
96632: 06/02/07: Re: cheap USB analyzer based on FPGA
96669: 06/02/08: Re: cheap USB analyzer based on FPGA
96941: 06/02/13: Re: spartan-3e starter kit
97345: 06/02/21: Re: FPGA - software or hardware -2-
97417: 06/02/21: Re: FPGA - software or hardware -2-
97418: 06/02/21: Re: ISE Simulator Price
97544: 06/02/23: Re: Combinatorial Division?
97556: 06/02/23: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
97731: 06/02/26: Re: Combinatorial Division?
97742: 06/02/27: tricks to make large PLAs fast?
97779: 06/02/27: Re: tricks to make large PLAs fast?
97780: 06/02/27: Re: tricks to make large PLAs fast?
97798: 06/02/27: Re: tricks to make large PLAs fast?
97809: 06/02/27: Re: tricks to make large PLAs fast?
97859: 06/02/28: Re: tricks to make large PLAs fast?
97860: 06/02/28: Re: tricks to make large PLAs fast?
97915: 06/03/01: Re: tricks to make large PLAs fast?
97916: 06/03/01: Re: tricks to make large PLAs fast?
97917: 06/03/01: Re: tricks to make large PLAs fast?
97918: 06/03/01: Re: problem with ISE versions
97919: 06/03/01: Re: Pulse Shape in a functional simulation
98167: 06/03/06: Re: why use an FPGA when a CPLD will do ??
98176: 06/03/06: Re: Which CPU and Screen Rez for ISE 6.3i ?
98191: 06/03/06: Re: Which CPU and Screen Rez for ISE 6.3i ?
98521: 06/03/12: Re: (no subject)
98522: 06/03/12: Re: fpga to 5v ttl logic
98632: 06/03/13: Re: Combinatorial Division?
98845: 06/03/17: Re: fpga to 5v ttl logic
98937: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
98939: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
98941: 06/03/17: Re: ISE 8.1 linux 64bit license key
99010: 06/03/18: Re: for all those who believe in ASICs....
99061: 06/03/19: Re: Urgent Help Needed!!!!!
99131: 06/03/20: Re: Urgent Help Needed!!!!!
99479: 06/03/24: Re: this JTAG thing is a joke
99576: 06/03/26: Re: chip reverse engineering
99577: 06/03/26: Spartan 3e Starter Kit finally available? No, not really.
99759: 06/03/28: Re: spartan FPGA with PLCC package
100007: 06/04/01: Re: Xilinx Webpack vs Foundation ?
100167: 06/04/04: Re: ISE under 64-bit Linux?
100272: 06/04/05: Re: ISE under 64-bit Linux?
100276: 06/04/05: Re: Compressing DVI stream
100558: 06/04/12: Spartan 3E Starter Kit is finally here!
100755: 06/04/17: Re: Where is the xilinx online store gone?
100756: 06/04/17: Re: Did National cheat with the Virtex 4? Or are they just smart engineers?
100757: 06/04/17: Re: PLD610
100759: 06/04/17: Re: Wasn't the S3E board cost 149$@Xilinx , it's 178$@Avnet !!!!
100974: 06/04/21: Re: Bluetooth with FPGA?????
101147: 06/04/26: Re: ISE 8.1i for Linux ?
101166: 06/04/26: Re: Async FPGA ~2GHz
101232: 06/04/27: Re: Async FPGA ~2GHz
101297: 06/04/28: Re: Async FPGA ~2GHz
101299: 06/04/28: Re: Async FPGA ~2GHz
101357: 06/04/29: Re: Working Altera USB-Blaster compatible design published underGPL
101480: 06/05/01: Re: design optimization
101686: 06/05/04: Re: 87C52 & 87C51 core
101766: 06/05/05: Re: Xilinx 3s8000?
101767: 06/05/05: Re: 87C52 & 87C51 core
101791: 06/05/06: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
102037: 06/05/09: Re: Superscalar Out-of-Order Processor on an FPGA
102269: 06/05/12: Re: reverse engineering ?
102570: 06/05/17: Re: Make a signal free for glitches?
102572: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
102573: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
102586: 06/05/17: Re: disappointing 550Mhz performance of V5 DSP slices
102588: 06/05/17: Re: disappointing 550Mhz performance of V5 DSP slices
102673: 06/05/18: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
102675: 06/05/19: Re: Superscalar Out-of-Order Processor on an FPGA
102676: 06/05/19: Re: Spartan 3 Readback
102755: 06/05/19: Re: Superscalar Out-of-Order Processor on an FPGA
102756: 06/05/19: Re: Ethernet & ML401
102882: 06/05/22: QuickLogic PolarPro (was Re: Virtex 5 announced and sampling: apologia for FX woes on V4)
102905: 06/05/23: Re: Superscalar Out-of-Order Processor on an FPGA
103030: 06/05/24: Re: Superscalar Out-of-Order Processor on an FPGA
103034: 06/05/24: Re: Superscalar Out-of-Order Processor on an FPGA
104030: 06/06/16: Re: Anyone get a Pictiva OLED to work?
104031: 06/06/16: Re: Floppy to FPGA?
104048: 06/06/17: Re: Anyone get a Pictiva OLED to work?
105428: 06/07/22: Re: Why 8 clock trees in Xilinx Spartan-3 device?
107005: 06/08/23: Re: fastest FPGA
107464: 06/08/28: Re: fastest FPGA
107751: 06/08/31: Re: Open-source CableServer for Impact (no more need for Jungo driver on Linux)
109895: 06/10/06: Re: Open protocol USB JTAG cable
111094: 06/10/28: Re: OT: FPGA soft-core humor
111096: 06/10/28: Re: OT: FPGA soft-core humor
112341: 06/11/20: Re: Platform USB Cable and Windows XP Pro x64
112343: 06/11/20: Re: board - T562.jpg
113115: 06/12/06: Re: Firmware for Xilinx USB cable
113945: 06/12/29: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
114018: 07/01/02: EDK 8.2 bidir gpio in XBD (board definition)
114071: 07/01/03: Re: EDK 8.2 bidir gpio in XBD (board definition)
114388: 07/01/13: Re: Ones' complement addition
114498: 07/01/17: Re: Ones' complement addition
114621: 07/01/21: Re: SPARC V7 CORE
114684: 07/01/22: Re: Ones' complement addition
114685: 07/01/22: Re: Xilinx ISE 8.2
114818: 07/01/24: Re: Xilinx ISE 8.2
114834: 07/01/24: Re: FPGA workstation - should I wait for Window Vista?
114928: 07/01/26: Re: Xilinx ISE 8.2
115040: 07/01/29: Re: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2)
115391: 07/02/08: Re: question abt DPRAM
115418: 07/02/09: Re: Xilinx Platform Studio Evaluation Trial Expired (included in Spartan 3E Starter Kit)
116023: 07/02/27: Re: Xilinx platform cable USB API?
116026: 07/02/27: Re: Xilinx platform cable USB API?
116213: 07/03/04: Re: Digital AM/FM Receiver
116214: 07/03/04: Re: V.34 Modem IP core
116429: 07/03/08: Re: V.34 Modem IP core
116484: 07/03/09: Re: Spartan3AN - Roadmap - bigger questions may prevail...
117009: 07/03/21: Re: CPLD erase??
117160: 07/03/24: Re: convertion real to std_logic_vector
117202: 07/03/26: Re: Where is Open Source for FPGA development?
117220: 07/03/26: Re: Where is Open Source for FPGA development?
117221: 07/03/26: Re: how to read a sequence of video
117762: 07/04/09: Re: ISE on Fedora?
117763: 07/04/09: Re: EDK 9.1i installation
117764: 07/04/09: Re: Problem with PHY clocks on Spartan 3E Starter Kit
117765: 07/04/09: Re: Clocking data into a shift register on positive AND negative edges
117936: 07/04/13: Re: Which are the best books about CORDIC algorithms and applications
117937: 07/04/13: Distributor stock (was Re: spartan 3e availability)
117945: 07/04/13: picoblaze C compiler download wanted
117967: 07/04/14: Re: picoblaze C compiler download wanted
117968: 07/04/14: Re: picoblaze C compiler download wanted
118367: 07/04/24: Re: Summer with fpgas
118505: 07/04/28: Re: picoblaze C compiler download wanted
118519: 07/04/28: driving Spartan-3 input from 74LS TTL
118545: 07/04/29: Re: driving Spartan-3 input from 74LS TTL
118602: 07/04/30: Re: driving Spartan-3 input from 74LS TTL
118809: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
118994: 07/05/08: Re: An Open-Source suggestion for Xilinx
118995: 07/05/08: Re: ISE : Linux - coregen, compxlib errors
119032: 07/05/09: Re: An Open-Source suggestion for Xilinx
119033: 07/05/09: Re: Xilinx software quality - how low can it go ?!
119112: 07/05/11: Re: how to choose the perfect fpga support
119121: 07/05/12: Re: driving Spartan-3 input from 74LS TTL
119141: 07/05/12: Re: downto usage in EDK
119197: 07/05/14: Re: An Open-Source suggestion for Xilinx
119321: 07/05/16: Re: Video scaler for Spartan 3E?
119322: 07/05/16: Re: DVI over fiber
119348: 07/05/17: Re: Video scaler for Spartan 3E?
119455: 07/05/19: Re: releasing some FPGA tools-ip as open-source
119512: 07/05/21: Re: UART Receiver Parity Check
119513: 07/05/21: Re: Timing not met but working on board
119941: 07/05/29: Re: 6502 and CPU licences in general
119942: 07/05/29: Re: Docs on s/w interfacing EDK based design
120068: 07/05/31: Re: Spartan-3E DIG-3E1600 Development Board Kit
120217: 07/06/03: Re: Weekend pop quiz
120540: 07/06/08: Re: A first FPGA project
120598: 07/06/11: Re: A first FPGA project
120599: 07/06/11: Re: DVI-D Tx directly from FPGA?
120600: 07/06/11: Re: EDK 9.1 + Virtex 5 Hard MAC
120650: 07/06/12: Re: xilinx spartan3e kit ddr sdram
120796: 07/06/16: Re: EDK - Microblaze question
121537: 07/07/06: Re: Xilinx ISE, EDK and some ground roules in software development
121993: 07/07/16: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
122031: 07/07/17: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
122033: 07/07/17: Re: Generating video noise.
122077: 07/07/18: Re: Generating video noise.
122247: 07/07/24: tiny Spartan 3 module?
122263: 07/07/24: Re: Xint64 ?
122264: 07/07/24: Re: Altera or Xilinx
122267: 07/07/24: Re: tiny Spartan 3 module?
122271: 07/07/24: Re: tiny Spartan 3 module?
122445: 07/07/27: Re: Best CPU platform(s) for FPGA synthesis
122578: 07/07/31: Re: Looking for PLD with embedded memory
122579: 07/07/31: Re: Upgrading from EDK 8.1 to EDK 9.1i
122634: 07/08/01: Re: Xilinx Webpack 9.2 and Windows 2000 Pro?
122635: 07/08/01: Re: Xilinx Webpack for Linux 64 bit?
122683: 07/08/02: Re: Best CPU platform(s) for FPGA synthesis
122703: 07/08/03: Re: Looking for PLD with embedded memory
122783: 07/08/06: Re: bidirectional pin
122867: 07/08/08: Re: Write of 64 from PowerPC to my IP conected to the PLB?
122961: 07/08/12: Re: Amount of wire and logic
122997: 07/08/13: Re: Amount of wire and logic
123138: 07/08/16: Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits
124063: 07/09/11: Re: Uses of Gray code in digital design
124144: 07/09/12: Re: Uses of Gray code in digital design
124221: 07/09/14: Re: Open-Source VHDL Synthesis for FPSLIC?
124472: 07/09/23: Re: Gated Clock Problems
124473: 07/09/23: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
124570: 07/09/26: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
124571: 07/09/26: Re: Own soft-processor
125029: 07/10/15: Re: Quartus II 7.2 web edition - Linux or not?
125143: 07/10/16: Re: FPGA to FPGA Bus
125212: 07/10/17: Re: difference between XC5VLX50-1FFG676C and XC5VLX50-1FFG676CES
125303: 07/10/19: Re: ethernet phy or mac
125515: 07/10/26: Re: fgpa beginner
125591: 07/10/29: Re: Is it possible to check how cache memories are mapped to FPGA block rams?
125634: 07/10/30: Re: Is it possible to check how cache memories are mapped to FPGA block rams?
125783: 07/11/04: Linux (not uClinux) on Microblaze 7.0 w/MMU?
125917: 07/11/08: Microblaze PLB vs. OPB busses
125959: 07/11/09: Re: Xilinx Parallel Cable IV, API spec
125960: 07/11/09: Re: ROM (altsyncram) corruption
125982: 07/11/10: Re: Xilinx Parallel Cable IV, API spec
126392: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
126568: 07/11/27: Re: Global Reset using Global Buffer
126574: 07/11/27: Re: Global Reset using Global Buffer
126627: 07/11/28: Re: Global Reset using Global Buffer
126635: 07/11/28: Re: CPU design uses too many slices
126794: 07/12/02: Memec Flancter app note?
126795: 07/12/02: Re: Fedora 8 and ISE 9.2
126835: 07/12/03: Re: Memec Flancter app note?
126836: 07/12/03: Re: Xilinx Platform USB Cable
126861: 07/12/04: Re: converting verilog to vhdl
127204: 07/12/13: Re: Newbee Microblaze system BRAM utlization confusion
127333: 07/12/18: Re: Virtex BRAM Configuration
127382: 07/12/19: Routing Vccint on four-layer PCB
127385: 07/12/19: Re: Routing Vccint on four-layer PCB
127386: 07/12/19: Re: help with rising edge matching
127420: 07/12/21: Re: PowerPC & Spartan-3E Embedded Processing Development Kit - SP3E1600E MicroBlaze Edition
127427: 07/12/23: Re: DQS contention with ddr_sdr from Opencores
127473: 07/12/27: Re: TechXclusives from Xilinx
127474: 07/12/27: Re: TechXclusives from Xilinx
127477: 07/12/27: Re: TechXclusives from Xilinx
127537: 08/01/01: Re: Where are the LCD or OLED bitmapped displays?
127890: 08/01/09: Re: Synthesizing big RAMs
127988: 08/01/11: Re: Place-and-Route : Intel vs AMD
128015: 08/01/12: Re: Place-and-Route : Intel vs AMD
128304: 08/01/20: Re: Debbuging a RISC processor on an FPGA
128557: 08/01/30: Re: define a new bust interface
128705: 08/02/04: Re: 4-bit table look-up
128709: 08/02/04: Re: 4-bit table look-up
128710: 08/02/04: Re: 4-bit table look-up
128850: 08/02/07: Re: beleive
129062: 08/02/13: Re: When are FPGAs the right choice?
129314: 08/02/20: Re: Which Linux Distro to use for Xilinx tools
129565: 08/02/27: Re: How to connect FPGA to a ASIC Board?
129710: 08/03/03: Re: Random Number Generation in VHDL
129826: 08/03/06: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129827: 08/03/06: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
130106: 08/03/14: Re: SiliconBlue enters the FPGA fray
130107: 08/03/14: Re: Virtex-5 FX when ? (III)
130108: 08/03/14: Re: Xilinx ISE Evaluation DVD 10.1 request...
130202: 08/03/17: Re: DDR3 speed, Altera vs Xilinx
130203: 08/03/17: Re: ISE 9.2SP4 error
130987: 08/04/07: Re: Xilinx inferred FIFOs
131101: 08/04/10: Re: Xilinx CPLD programming tool under Linux
131102: 08/04/10: Re: Serial Transmission w/o 8B/10B encoding
131127: 08/04/11: Re: 64 bit WebPack
131190: 08/04/14: Re: 64 bit WebPack
131191: 08/04/14: Re: Xilinx tech Xclusive
131226: 08/04/15: Re: 64 bit WebPack
131227: 08/04/15: Re: Which to learn: Verilog vs. VHDL?
131228: 08/04/15: Re: Which to learn: Verilog vs. VHDL?
131615: 08/04/26: Re: Survey: FPGA PCB layout
131750: 08/04/30: Re: how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY
131831: 08/05/02: Re: Forking in One-Hot FSMs
131878: 08/05/06: Re: Forking in One-Hot FSMs
132040: 08/05/11: Re: Problem writing quadrature decoder
132052: 08/05/11: Re: Problem writing quadrature decoder
132325: 08/05/21: Re: Every newbie's favorite project: the Quadrature Rotary Encoder revisited
132327: 08/05/21: Re: Every newbie's favorite project: the Quadrature Rotary Encoder revisited
132524: 08/05/29: Re: Xilinx Clock Doubler
132582: 08/06/01: Re: (won't even attempt to try again .. .. ..)
132754: 08/06/06: Re: xilinx and jtag
132877: 08/06/09: Re: SDRAM controller
133011: 08/06/13: Re: FPGA to solve the two most annoying problems on usenet - Suggestions Welcome
133505: 08/07/01: Re: Standard forms for Karnaugh maps?
134044: 08/07/22: Re: DVI to BT.656
134068: 08/07/23: Re: The littlest CPU
134089: 08/07/24: Re: The littlest CPU
134370: 08/08/07: Re: Microblaze to LCD module via FSL bus
134486: 08/08/12: Re: Using a Spartan 3 FPGA kit with a USB/DB9
134758: 08/08/28: Re: Genode FPGA graphics project launched
134965: 08/09/08: Re: Signed multiplication
135023: 08/09/10: Re: Can Soft microprocessor replace DSP's
135116: 08/09/16: Re: Xilinx Spartan E
135202: 08/09/19: Re: WebPack on CentOS 5 ?
135203: 08/09/19: Re: WebPack on CentOS 5 ?
135398: 08/09/30: Re: Is it possible to get an RTL netlist from Xilinx tools?
135722: 08/10/13: Re: XMOS XC-1 kits are shipping
135723: 08/10/13: Re: writing files to micro-SD with spartan 3e
135728: 08/10/13: Re: writing files to micro-SD with spartan 3e
135754: 08/10/14: Re: XMOS XC-1 kits are shipping
135755: 08/10/14: Re: XMOS XC-1 kits are shipping
136334: 08/11/11: Re: Linux on Microblaze
136436: 08/11/16: Spartan-3E SDRAM interface
136513: 08/11/19: Re: Linux on Microblaze
136550: 08/11/21: Re: Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell
136905: 08/12/11: Re: encrypted and unencrypted design in the same device
138007: 09/02/03: Re: Spartan-6
138008: 09/02/03: Re: Why the second flip-flop in Virtex-6?
138192: 09/02/09: Re: Is this phase accumulator trick well-known???
138742: 09/03/06: Re: 32x32 -> 64 multiplier in virtex-5
139034: 09/03/18: Re: Zero operand CPUs
144483: 09/12/09: Data2MEM - finding the blockrams after PAR?
144524: 09/12/12: Re: Data2MEM - finding the blockrams after PAR?
144541: 09/12/13: Re: Data2MEM - finding the blockrams after PAR?
144706: 09/12/26: Re: More details: VHDL: assignment to two different fields of the
144767: 09/12/31: Re: More details: VHDL: assignment to two different fields of the
145524: 10/02/13: Re: VHDL vs Verilog
145614: 10/02/15: Re: The more you read, the more you are confused: about Intel's a
145992: 10/03/02: Re: Tabula. (FPGA start up)
146026: 10/03/04: Re: Tabula. (FPGA start up)
146491: 10/03/20: Re: Update init data in dualport BRAM without re-run anything?
146556: 10/03/22: Re: Why hardware designers should switch to Eclipse
146557: 10/03/22: Re: Why hardware designers should switch to Eclipse
146567: 10/03/22: Re: Why hardware designers should switch to Eclipse
147018: 10/04/09: Re: Can Spartan-6 Support M-LVDS ?
147848: 10/05/26: Re: crc16 with 16 bit inputs
147969: 10/06/08: Re: How to Disable IP Core after Evaluation Period
148207: 10/06/28: Re: Using Xilinx TFT controller IP for normal VGA port on Spartan 3E
149153: 10/10/04: Re: Why did Microsemi buy Actel?
150165: 10/12/22: Re: Simple ISE Microblaze with GPIO and custom logic example?
150339: 11/01/10: Re: Xilinx ML561 Schematics
150358: 11/01/11: Re: Xilinx ML561 Schematics
150882: 11/02/19: Re: Mathematical definition of an FPGA
158651: 16/02/26: VQ44 recommended footprint
158697: 16/03/25: Vivado MIG says "Design entry" is VERILOG, how to change to VHDL?
158698: 16/03/26: Re: VQ44 recommended footprint
Eric T. Brewer:
1238: 95/05/20: Re: affordable fpga design tools?
1242: 95/05/21: Re: affordable fpga design tools?
Eric Vannerson:
23928: 00/07/15: Re: Error: Clock skew plus hold time of destination register exceeds
Eric Venditti:
16923: 99/06/17: Re: Synopsys DC & Modelsim
Eric W Braeden:
7502: 97/09/17: Re: 6809 discontinued
11758: 98/09/07: PCI cores again!!!!!
11791: 98/09/09: Design Security Question
11855: 98/09/14: PCI Initiator/Target questions
14166: 99/01/16: 300 MHz core with 50 MHz bus
Eric Wallin:
155224: 13/06/13: Re: New soft processor core paper publisher?
155225: 13/06/13: Re: New soft processor core paper publisher?
155228: 13/06/14: Re: New soft processor core paper publisher?
155230: 13/06/14: Re: New soft processor core paper publisher?
155231: 13/06/15: Re: New soft processor core paper publisher?
155233: 13/06/15: Re: New soft processor core paper publisher?
155236: 13/06/16: Re: New soft processor core paper publisher?
155239: 13/06/16: Re: New soft processor core paper publisher?
155267: 13/06/20: Re: New soft processor core paper publisher?
155270: 13/06/20: Re: Modelsim ought to be cheaper
155274: 13/06/20: Re: New soft processor core paper publisher?
155279: 13/06/21: Re: New soft processor core paper publisher?
155292: 13/06/22: Re: New soft processor core paper publisher?
155293: 13/06/22: Re: New soft processor core paper publisher?
155298: 13/06/22: Re: New soft processor core paper publisher?
155301: 13/06/22: Re: New soft processor core paper publisher?
155302: 13/06/22: Re: New soft processor core paper publisher?
155303: 13/06/22: Re: New soft processor core paper publisher?
155314: 13/06/23: Re: New soft processor core paper publisher?
155324: 13/06/23: Re: New soft processor core paper publisher?
155325: 13/06/23: Re: New soft processor core paper publisher?
155330: 13/06/23: Re: New soft processor core paper publisher?
155334: 13/06/23: Re: New soft processor core paper publisher?
155344: 13/06/24: Re: New soft processor core paper publisher?
155350: 13/06/24: Re: New soft processor core paper publisher?
155355: 13/06/24: Re: New soft processor core paper publisher?
155364: 13/06/24: Re: New soft processor core paper publisher?
155365: 13/06/24: Re: New soft processor core paper publisher?
155368: 13/06/24: Re: New soft processor core paper publisher?
155371: 13/06/24: Re: New soft processor core paper publisher?
155395: 13/06/25: Re: New soft processor core paper publisher?
155396: 13/06/25: Re: New soft processor core paper publisher?
155403: 13/06/25: Re: New soft processor core paper publisher?
155405: 13/06/25: Re: New soft processor core paper publisher?
155408: 13/06/25: Re: New soft processor core paper publisher?
155409: 13/06/25: Re: New soft processor core paper publisher?
155424: 13/06/26: Re: New soft processor core paper publisher?
155425: 13/06/26: Re: New soft processor core paper publisher?
155427: 13/06/26: Re: New soft processor core paper publisher?
155430: 13/06/27: Re: New soft processor core paper publisher?
155436: 13/06/28: Re: New soft processor core paper publisher?
155447: 13/06/28: Re: New soft processor core paper publisher?
155459: 13/06/29: Re: New soft processor core paper publisher?
155461: 13/06/29: Re: New soft processor core paper publisher?
155467: 13/06/29: Re: New soft processor core paper publisher?
155477: 13/06/30: Re: New soft processor core paper publisher?
155494: 13/07/01: Re: New soft processor core paper publisher?
156323: 14/03/05: Re: New soft processor core paper publisher?
Eric Weaver:
22420: 00/05/08: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
Eric Williams:
48086: 02/10/10: FPGA Design Engineer Needed
Eric Yeh:
90492: 05/10/14: xilinx fpga beginner question
91918: 05/11/16: ml300 LCD question
<eric.amundsen@gmail.com>:
105771: 06/07/31: DDR2 SRAM Stratix II questions
105788: 06/07/31: Re: DDR2 SRAM Stratix II questions
<eric.jacobsen@ieee.org>:
159708: 17/02/13: Re: All-real FFT for FPGA
159720: 17/02/14: Re: All-real FFT for FPGA
159721: 17/02/14: Re: All-real FFT for FPGA
<eric.levrault@mageos.com>:
28742: 01/01/23: multiplier architecture
<eric>:
19780: 00/01/11: freemoneyfast
Eric_at_AccelChip:
83913: 05/05/09: Re: Do Synplify DSP and Accelchip support multiple clock domains?
84173: 05/05/13: Re: How to implement this C function in FPGA
90490: 05/10/14: Re: Simulink to hdl conversion
erica:
22247: 00/05/03: Re: Beginner's Guide
22271: 00/05/03: Re: Beginner's Guide
<ericd>:
2362: 95/11/23: Re: NeoCAD and AT&T vs. Xilinx
Erich Krause:
49243: 02/11/06: Re: BLOCK RAM : FIFO implementation
Erich Wagner:
2988: 96/03/09: Re: JEDEC Specification?
18914: 99/11/21: Altera JAM
19234: 99/12/07: Re: Actel Programming Information Sought
Erik:
34980: 01/09/17: Re: Problems with Xilinx App Note 223 (UART with Internal 16-Byte Buffer)
45220: 02/07/16: Re: I want to buy 4 Xilinx FPGA
45260: 02/07/17: Re: I want to buy 4 Xilinx FPGA
45261: 02/07/17: Re: I want to buy 4 Xilinx FPGA
45318: 02/07/18: Re: I want to buy 4 Xilinx FPGA
45320: 02/07/18: Re: I want to buy 4 Xilinx FPGA
45377: 02/07/21: Re: I want to buy 4 Xilinx FPGA
45585: 02/07/27: Re: I want to buy 4 Xilinx FPGA
45703: 02/08/01: Re: I want to bay 4 Xilinx FPGA
Erik Anderson:
123516: 07/08/29: Re: intialize memory in fpga
124119: 07/09/12: Re: Address sensitive process, Xilinx virtex2pro
124120: 07/09/12: VHDL Design Pattern Book
124560: 07/09/26: Re: partial reconfiguration, par error
131280: 08/04/17: Re: ICAP_VIRTEX4 primitive
132483: 08/05/28: FIFO verses RAMB
133322: 08/06/24: Configuration Management Best Practices
140630: 09/05/20: Synthesis of Xilinx's PLB DDR Controller
Erik Blake:
1503: 95/07/04: Re: Who makes low-power 22v10-type PLDs?
Erik Bolton:
57082: 03/06/23: Programmable Delay (not clock driven)
57584: 03/07/02: Re: Programmable Delay (not clock driven)
Erik Brunvand:
25329: 00/09/06: FPGA Express, Xilinx, and Powerview
44101: 02/06/11: Synopsys, Spartan2, and Viewsim...
Erik Chalupa:
157118: 14/10/14: PicoBlaze IDE
157613: 15/01/06: Re: PicoBlaze IDE
Erik Coenders:
58712: 03/07/31: Tiny TCP/IP stack and tiny MAC controller on FPGA for direct download to S(D)RAM memory
59009: 03/08/06: Re: Tiny TCP/IP stack and tiny MAC controller on FPGA for direct download to S(D)RAM memory
Erik Corry:
5259: 97/02/02: Re: ASICs Vs. FPGA in Safety Critical Apps.
Erik de Castro Lopo:
3351: 96/05/17: Re: Xilinx 4013 80% utilized but won't route
3497: 96/06/11: Xilinx 4013E and PCI
3574: 96/06/27: Re: Need recommendation for PCI interface on 68332
3825: 96/08/07: Re: Xilinx clock doubler?
3965: 96/08/26: Re: Interesting Xilinx XACT observation.
5520: 97/02/22: Re: 2nd try: What kind of functions mostly implemented using FPGAs?
7743: 97/10/09: Re: How fast can fully pipelined XC4000 logic go?
7803: 97/10/17: Re: Can I use M1.3 with Protel Schematic 3.2 ?
7964: 97/11/04: Re: Anyone using Protel Schematic 3 for XILINX?
7974: 97/11/05: Re: Anyone using Protel Schematic 3 for XILINX?
8207: 97/11/28: Free C hardware synthesizer (still available ???)
8010: 97/11/07: Re: Digital reverberator on FPGA
8276: 97/12/05: A suggestion for Xilinx
8430: 97/12/14: Re: dynamic power in Xilinx designs
8610: 98/01/13: Anybody using Orcad Express?
9213: 98/03/02: Re: The case for Linux and EDA
10236: 98/05/06: Re: Xilinx Foundation and Linux
10809: 98/06/22: Re: FPGA design tools for Xilinx and Altera on WinNT and Alpha
10973: 98/07/08: Orcad Express and Xilinx M1.4 TIMESPEC problems
11818: 98/09/11: Re: Design Security Question
12223: 98/10/06: Re: Orcad Capture error DSM0006 and DBO3203
12418: 98/10/12: Re: Xilinx may not support schematics for Virtex?????
12419: 98/10/12: Re: Xilinx may not support schematics for Virtex?????
12420: 98/10/12: Re: Xilinx may not support schematics for Virtex?????
12517: 98/10/15: Re: Schematic entry?
13178: 98/11/19: Re: XNF issue
16714: 99/06/04: Xinx M1.5 under WinNT how to `nice' par
16752: 99/06/07: Re: Xinx M1.5 under WinNT how to `nice' par
20191: 00/01/31: Re: Announcement: Xilinx on Linux HowTo
87413: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87416: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
98715: 06/03/15: Re: Why does Xilinx hate version control?
106030: 06/08/06: Re: verilog versus vhdl
Erik Fischer:
49738: 02/11/20: Problems With DW8051 Synthesis
Erik Hansen:
53163: 03/03/05: Re: scripting leonardo spectrum
60407: 03/09/12: Re: EMAC in EDK...
63218: 03/11/18: Re: microblaze as submodule
63357: 03/11/20: Re: Xilinx microblaze : SRAM external mem controller
Erik Jessen:
1803: 95/09/05: Re: Help Needed-FPGA Apps Eng.-AllentownPA.-Recruiter
1893: 95/09/16: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
2143: 95/10/19: Re: Needed: Suggestions for FPGA design CAD
2162: 95/10/23: Re: FPGAs as a substitute for glue logic?
2163: 95/10/23: Re: Problem using Xilinx XC4025
2175: 95/10/26: Re: Xilinx Configuration Memory Hacking
2282: 95/11/17: Re: Industry Trends
2295: 95/11/17: Re: Any user experiences with Exemplar VHDL synthesis for FPGA
2296: 95/11/17: Re: NeoCAD and AT&T vs. Xilinx
2297: 95/11/17: Re: request for RTL netlists
2298: 95/11/17: Re: Wanted-limited Verilog or VHDL synthesis
2300: 95/11/17: Re: [q][Reverse Engineering Protection]
2320: 95/11/20: Re: [q][Reverse Engineering Protection]
2329: 95/11/20: Re: [q][Reverse Engineering Protection]
2330: 95/11/20: Re: [Q] FPGA Software for Linux
2423: 95/12/04: Re: PC VHDL synth for FPGA?
2434: 95/12/05: Re: Search for programs implementing Finite State Machine
2446: 95/12/06: Re: Xilinx vs Altera with Verilog/VHDL
2461: 95/12/08: Where is the FAQ?
2465: 95/12/08: Re: FPGA Synthesis/Simulation
2748: 96/02/01: Re: Xilinx or Altera?
2766: 96/02/04: Re: AT&T Orca vs Xilinx
2921: 96/02/29: Re: Languages for reconfigurable computing.
2937: 96/03/03: Re: High Level Languages
2938: 96/03/03: Re: ORCA and 3.3V logic
2939: 96/03/03: Re: Reconfigurable Computing Languages
2955: 96/03/05: Re: Reconfigurable Computing Languages
2956: 96/03/05: Re: Languages for reconfigurable computing.
2957: 96/03/05: Re: Languages for reconfigurable computing.
3005: 96/03/12: Re: Multiple FPGA Partitioning
3398: 96/05/24: Re: impossible for Synthesizer to optimize FSM??!
3486: 96/06/07: Re: impossible for Synthesizer to optimize FSM??!
5722: 97/03/10: Re: A viewlogic story
Erik Kobal:
9124: 98/02/23: Correlation implementation...
9207: 98/03/02: constant coefficients
Erik L. Kobal:
9171: 98/02/27: Correlation--Multichannel
Erik Larsen:
31159: 01/05/13: Registers/Latches in Lattice ispLSI1024EA???
Erik Lins:
6757: 97/06/25: Asynchronous Peripheral Download Mode, Probs
8891: 98/02/05: Q: Workview Office and M1
11168: 98/07/22: unknown speedgrade question
21833: 00/04/03: need FIFOs, urgent!
35542: 01/10/10: Handel-C
35625: 01/10/12: Re: Handel-C
35627: 01/10/12: Re: Xilinx dev. kit for Linux?
35781: 01/10/17: Re: pci-card with Virtex2?
35785: 01/10/17: Re: Handel-C
35878: 01/10/22: one-hot statemachine
36106: 01/10/30: Re: Probing BGA Designs
36153: 01/10/31: Re: Can anyone guide me in selecting an FPGA?
36800: 01/11/20: Foundation ISE 4.1
Erik Markert:
63533: 03/11/25: Re: Dual port RAM for Xilinx
63781: 03/12/04: Spartan-IIe CCLK after config
Erik Spaenig:
52874: 03/02/25: config SlewRate for PCI-pads in Xilinx WebPack ??
54499: 03/04/11: Re: Webpack 5.2 and Win98se
58384: 03/07/22: Xilinx WebPack support "dual edge clock" ??
58387: 03/07/22: Re: Xilinx WebPack support "dual edge clock" ??
58390: 03/07/22: Re: Xilinx WebPack support "dual edge clock" ??
58431: 03/07/23: Generate .mcs file
59698: 03/08/26: Re: Two near-identicial clocks?
60224: 03/09/08: Re: PIC Programming Help
Erik van Duijn:
11438: 98/08/13: Continuously Charging 9V-battery
Erik Verhagen:
106214: 06/08/09: DSP core, use of real type signals (Altera Stratix)
106543: 06/08/15: IIR filter example ?
Erik Wahlstrom:
29373: 01/02/16: Vertex Place & Route Time
Erik Walthinsen:
76281: 04/11/29: Verilog newbie with clocking question
76286: 04/11/29: Re: Verilog newbie with clocking question
76299: 04/11/30: Re: Verilog newbie with clocking question
77736: 05/01/15: Re: Looking for low-cost protoboards.
82626: 05/04/14: Re: Fitting functionality in an XC2VP30 FPGA.
82719: 05/04/16: Re: Xilinx tools on Linux
83042: 05/04/21: Re: VHDL or Verilog
83048: 05/04/22: Re: Xilinx Impact in Linux 2.6.x
83101: 05/04/23: Re: Xilinx Impact in Linux 2.6.x
85335: 05/06/07: Re: Pissed off with Xilinx - Spartan 3
85384: 05/06/08: Re: General gripe session ....
85455: 05/06/09: Re: General gripe session ....
85456: 05/06/09: Re: General gripe session ....
85466: 05/06/09: Re: General gripe session ....
Erik Widding:
4535: 96/11/10: Re: Xilinx and cost of tools
7472: 97/09/15: Re: Large FPGA
14236: 99/01/21: CORDIC (was: Best way to digitally synth. stable frequencies?)
29375: 01/02/16: Re: Mentor Advice
29418: 01/02/20: Re: Fine Phase Shift in VirtexII
29422: 01/02/20: Re: Fine Phase Shift in VirtexII
29841: 01/03/13: Re: 64 simultan A/D Converters in an SPARTAN-II
29845: 01/03/13: Re: 64 simultan A/D Converters in an SPARTAN-II
29853: 01/03/13: Re: 64 simultan A/D Converters in an SPARTAN-II
29857: 01/03/14: Re: 64 simultan A/D Converters in an SPARTAN-II
30006: 01/03/20: Re: FFT in FPGAs
30045: 01/03/21: Re: backup FLEX10K
30465: 01/04/09: Re: High Speed PLA/FPGA
30742: 01/04/27: Re: Configuration via PCI JTAG
30850: 01/05/01: Re: Multiple state machines in altera AHDL
30851: 01/05/01: Re: ccd imaging with fpga
30922: 01/05/03: Re: ccd imaging with fpga
30950: 01/05/04: Re: ccd imaging with fpga
30978: 01/05/07: Re: Licensing PB in Synplify_pro 6.2
31015: 01/05/09: Re: Virtex-2 - experiences ?
31123: 01/05/12: Re: Implementation Of LUT in Vertex-E
31125: 01/05/12: Re: Virtex-2 - experiences ?
31323: 01/05/18: Re: FPGA Express 3.5 One hot state machine Synthesis problem
31828: 01/06/06: Re: one state machine
32464: 01/06/27: Re: clock speed in XC95288XL
33801: 01/08/06: Re: Building ROM and RAM blocks - Xilinx Foundation Series 3.1i
34848: 01/09/11: Re: Data cache for fpga-cpu using Xilinx BlockRam
53346: 03/03/11: Re: digikey d2e microblaze help
53347: 03/03/11: Re: Can you recommend a text on...?
53714: 03/03/20: Re: PCI target design
57567: 03/07/02: Re: Why not DDR in FPGAs?
62491: 03/10/30: Re: How to protect fpga based design against cloning?
62587: 03/11/02: Re: How to protect fpga based design against cloning?
62977: 03/11/11: Re: FPGAs and DRAM bandwidth
63317: 03/11/19: Re: Embedded Development Kit + performance
65056: 04/01/19: Re: Trouble using ChipsCope Pro with MicroBlaze
65163: 04/01/21: Re: SDRAM Controller timing problem
66351: 04/02/17: Re: GZIP algorithm in FPGA
66657: 04/02/24: Re: GZIP algorithm in FPGA
69284: 04/05/04: Re: Not enough sites to place MULT18X18?
69627: 04/05/16: Re: Video Blob Analysis on FPGAs
69763: 04/05/19: Re: Video Blob Analysis on FPGAs
71691: 04/07/27: Re: Xilinx EDK PCI
71730: 04/07/28: Re: Xilinx EDK PCI
74432: 04/10/11: Re: Use Xilinx VP20 with 2 ppc and one DRAM chip
79331: 05/02/17: Re: PPC405 sleep?
79599: 05/02/21: Re: Antti Lukats: all my past live projects to be published...
79635: 05/02/22: Re: Antti Lukats: all my past live projects to be published...
85762: 05/06/15: Re: Somewhat OT - falling behind the times ...
90512: 05/10/15: Re: Storing a file onto FPGA
92666: 05/12/03: Re: ML403 "small" problem
96013: 06/01/27: Re: Virtex-4 ISERDES and ADS527X ADCs
96049: 06/01/28: Re: Virtex-4 ISERDES and ADS527X ADCs
96559: 06/02/06: Re: porting linux on ml403
99047: 06/03/19: Re: Urgent Help Needed!!!!!
99171: 06/03/20: An Open Letter to Mr. John Bass (was: Urgent Help Needed!!!!!)
99882: 06/03/30: Re: FpgaC developers wanted :)
99898: 06/03/30: Re: FpgaC developers wanted :)
99918: 06/03/30: Re: FpgaC developers wanted :)
99965: 06/03/31: Re: FpgaC developers wanted :)
102492: 06/05/16: Re: Virtex4 FX12 dynamic clock divider
102574: 06/05/17: Re: Virtex4 FX12 dynamic clock divider
103092: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
104505: 06/06/28: Re: Help in the platform studio(EDK)
106772: 06/08/18: Re: EDK vs. ISE for image processing
106781: 06/08/18: Re: EDK vs. ISE for image processing
111077: 06/10/28: Re: Xilinx Virtex4 Outputs for Camera Link
111105: 06/10/29: Re: Xilinx Virtex4 Outputs for Camera Link
112946: 06/12/01: Re: MPMC2: MPMC2 with DDR2 SDRAM
113746: 06/12/20: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
113747: 06/12/20: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
114063: 07/01/03: Re: PPC cache errata
114110: 07/01/04: Re: PPC cache errata
114526: 07/01/18: Re: Process on both edges
115761: 07/02/19: Xilinx MIG DDR2 Documentation
115763: 07/02/19: Re: Xilinx MIG DDR2 Documentation
116791: 07/03/18: Re: DCM Autoconfiguration??
118588: 07/04/30: Re: Problem cascading 2 DCMs
120661: 07/06/13: Re: DVI-D Tx directly from FPGA?
122659: 07/08/02: Re: Xilinx/ModelSim bug ? Clocking headache ...
<erik.kimball@mailexcite.com>:
9478: 98/03/16: Free Printed Circuit Board Symposium
erika:
31534: 01/05/29: ignore
"erika churchil":
29313: 01/02/13: ignore it
29421: 01/02/20: to you sir Peter Alfke...
Erika Van Baelen:
7462: 97/09/13: DES implementation
<erika_uk@my-deja.com>:
19623: 00/01/05: GSR pulse
19626: 00/01/05: CLKDLL
19627: 00/01/05: STARTUP
19628: 00/01/05: STARTUP
19996: 00/01/21: timing simulation
20453: 00/02/10: quantiser + ....
20556: 00/02/14: Re: MULTIRATE DESIGN
23151: 00/06/15: 3.1i
23345: 00/06/22: how to lock the lut inputs
23346: 00/06/22: Re: how to lock the lut inputs
23396: 00/06/23: F2.1i
23415: 00/06/24: Re: F2.1i
23419: 00/06/24: Re: F2.1i
23462: 00/06/26: serial 2's C add/substractor msb first
23560: 00/06/30: Re: Maximum Speed on obtainable on FPGAs?
23602: 00/07/02: why???
23932: 00/07/16: Re: Silicon Valley Housing Nightmare?
24005: 00/07/20: Re: Foundation 3.1i in Germany
24036: 00/07/24: jedec ???
24037: 00/07/24: XC4000 select ram
24081: 00/07/26: F3.1 in Great Britain
24216: 00/07/30: Re: LFSR as a divider
24238: 00/07/31: tbuf
24408: 00/08/07: Re: Help! Troubles using async FIFO cores in Virtex
24652: 00/08/16: Re: Help!!! Bit serial Baugh-Wooley multiplier
24856: 00/08/20: timing simulation vs functional one
24880: 00/08/21: Re: timing simulation vs functional one
24881: 00/08/21: Re: timing simulation vs functional one
25159: 00/08/29: Re: run time doubled with Xilinx 3.1i upgrade
25318: 00/09/06: floorplanning
25405: 00/09/10: virtex shape
25420: 00/09/11: xilinx web site access
25620: 00/09/15: Physical Interpretation
25750: 00/09/19: Re: Safe voltage regulator for Xilinx XC2S150 part?
25762: 00/09/19: VHDL to SCHEMATIC
25763: 00/09/19: Re: VHDL to SCHEMATIC
25799: 00/09/20: Re: VHDL to SCHEMATIC
26090: 00/10/03: Re: FEC in FPGAs?
26032: 00/10/01: Re: multi-input adders in virtex ?
26052: 00/10/02: Re: multi-input adders in virtex ?
26088: 00/10/03: Pwr/Gnd ( again)
26108: 00/10/04: Re: Pwr/Gnd ( again)
26138: 00/10/05: Re: Pwr/Gnd ( again)
26533: 00/10/19: Re: scripting with xilinx tools (foundation) ????
26586: 00/10/21: Re: VHDL vs Verilog
26607: 00/10/22: Re: xilinx floor planner issues
26777: 00/10/28: Re: High fan out CE signal.
26823: 00/10/31: Re: High fan out CE signal.
27044: 00/11/08: Re: PLL vs DLL
27192: 00/11/14: reset pulse ?
27193: 00/11/14: Re: reset pulse ?
27292: 00/11/17: Re: reset pulse ?
27315: 00/11/17: Re: reset pulse ?
27725: 00/12/05: Re: Wide AND function.
28406: 01/01/11: address of ram using the clk net
28423: 01/01/12: Re: address of ram using the clk net
28491: 01/01/15: Re: Virtex-II officially launched
28496: 01/01/15: Re: grey code counters
28572: 01/01/17: CMOS or TTL
28875: 01/01/26: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip multiprocessor!
28944: 01/01/30: Re: Advice on FPGA board.
29101: 01/02/06: can -(A+B) computed in one level of logic ?
29195: 01/02/09: counter
29232: 01/02/10: does a disabled FDC consume power ?
erikdm:
93184: 05/12/15: Re: Parallel Cable III is not detected
93186: 05/12/15: Re: Parallel Cable III is not detected
<eriks@avidyne.com>:
28250: 01/01/03: NIOS Processor soft core
erjs:
76427: 04/12/01: FF/Latch trimming : Xilinx ISE 6.3 i
78435: 05/01/31: Co design : Verilog and C : Examples needed
Ernest Jamro:
20274: 00/02/03: Re: Visualizing EDIF netlist for Xilinx
24128: 00/07/27: Re: Arithmetic Operators
52066: 03/01/30: Re: Interfacing to a PC using EPP parallel port
52148: 03/02/03: Re: one hot encoding
52157: 03/02/03: which microprocessor core?
Ernest Scheiber:
97488: 06/02/23: virtex 4
151421: 11/04/06: RocketIO
Ernesto Guevara:
19181: 99/12/03: Re: Help with ROM in Xilinx Virtex
ernie:
71481: 04/07/19: 32-channel PC-based logic analyzers
71577: 04/07/22: Re: 32-channel PC-based logic analyzers
71578: 04/07/22: Re: 32-channel PC-based logic analyzers
85387: 05/06/08: In-system configuration
85678: 05/06/13: Re: In-system configuration
86742: 05/07/05: Stratix open-drain pins
86784: 05/07/06: Re: Stratix open-drain pins
86789: 05/07/06: Re: Stratix open-drain pins
88144: 05/08/10: Cypress CY7B923/33 models
88196: 05/08/11: Re: Cypress CY7B923/33 models
88315: 05/08/15: Re: Cypress CY7B923/33 models
88316: 05/08/15: Re: globally asyncronous vs locally syncronous?
88422: 05/08/17: Re: Cypress CY7B923/33 models
96365: 06/02/02: Re: high input to CPLD
96680: 06/02/08: Re: why does speed grade effect VHDL program??
96730: 06/02/09: Re: why does speed grade effect VHDL program??
97290: 06/02/20: Quartus Tcl interface
97327: 06/02/20: Re: Quartus Tcl interface
Ernst Rattenhuber:
30600: 01/04/18: Wanted: ISA bus implementation for Xilinx
30645: 01/04/20: Re: Wanted: ISA bus implementation for Xilinx
Ernst Zwingenberger:
24920: 00/08/22: Re: Leonardo Spectrum with Altera - am I being stupid???
25747: 00/09/19: Re: Looking for an Altera APEX eval board
erojr:
63257: 03/11/18: Altera Stratix synthesis error
63288: 03/11/19: Re: Anyone use HDL as design tool for PCBs?
63480: 03/11/22: Re: Altera Stratix synthesis error
64844: 04/01/15: Re: Altera Cyclone data is incomplete or messy
64921: 04/01/16: Re: yo, Mr. FPGA Engineer
65650: 04/02/04: Sporadic errors in the JTAG chain
66956: 04/03/02: TRST Pin in Altera FPGAs
67051: 04/03/04: Re: TRST Pin in Altera FPGAs
67086: 04/03/05: Re: TRST Pin in Altera FPGAs
67136: 04/03/06: Re: TRST Pin in Altera FPGAs
67137: 04/03/06: Re: TRST Pin in Altera FPGAs
67518: 04/03/13: Re: Altera, Cyclone: pin not connected warning
67631: 04/03/16: Re: Altera, Cyclone: pin not connected warning
67782: 04/03/19: Re: LVDS
68045: 04/03/25: Re: study verilog or vhdl?
68089: 04/03/26: Re: CPLD: assign pins first, or design content first?
68090: 04/03/26: Re: Back Annotated Gate Level Simms (Xilinx)
68226: 04/03/30: Quartus removes Tristate Buffer
68249: 04/03/31: Re: Quartus removes Tristate Buffer
68477: 04/04/06: Re: Quartus removes Tristate Buffer
68523: 04/04/07: Re: Quartus removes Tristate Buffer
eromlignod:
117249: 07/03/27: PCI-Express drivers with Xilinx FPGA?
117256: 07/03/27: Re: PCI-Express drivers with Xilinx FPGA?
117265: 07/03/27: Re: PCI-Express drivers with Xilinx FPGA?
117274: 07/03/27: Re: PCI-Express drivers with Xilinx FPGA?
121047: 07/06/23: Substitute for FORK / JOIN?
122657: 07/08/02: Inputs as an Array in Verilog??
131675: 08/04/28: Debounce in Verilog?
134320: 08/08/06: Downsizing Verilog synthesization.
134326: 08/08/06: Re: Downsizing Verilog synthesization.
134327: 08/08/06: Re: Downsizing Verilog synthesization.
134331: 08/08/06: Re: Downsizing Verilog synthesization.
134332: 08/08/06: Re: Downsizing Verilog synthesization.
134336: 08/08/06: Re: Downsizing Verilog synthesization.
134338: 08/08/06: Re: Downsizing Verilog synthesization.
134356: 08/08/07: Re: Downsizing Verilog synthesization.
134363: 08/08/07: Re: Downsizing Verilog synthesization.
134367: 08/08/07: Re: Downsizing Verilog synthesization.
134368: 08/08/07: Re: Downsizing Verilog synthesization.
134377: 08/08/07: Re: Downsizing Verilog synthesization.
134410: 08/08/09: Re: Downsizing Verilog synthesization.
134432: 08/08/10: Re: Downsizing Verilog synthesization.
134457: 08/08/11: Re: Downsizing Verilog synthesization.
134460: 08/08/11: Re: Downsizing Verilog synthesization.
EROTIK:
Ersin:
45641: 02/07/30: ntelist problem
45665: 02/07/31: Re: ntelist problem
45667: 02/07/31: Re: ntelist problem
ertw:
130122: 08/03/15: ISSI SRAM.
133241: 08/06/22: Image Sensor Interface.
133242: 08/06/22: Re: Image Sensor Interface.
133282: 08/06/23: Re: Image Sensor Interface.
133283: 08/06/23: Re: Image Sensor Interface.
133285: 08/06/23: Re: Image Sensor Interface.
133330: 08/06/24: Re: Image Sensor Interface.
135608: 08/10/09: Virtex 5 DSP48E Instantiation.
Erwan:
50685: 02/12/17: MPEG FPGA
50817: 02/12/20: Re: MPEG FPGA
56911: 03/06/18: Data organization for DSP on FPGA
91937: 05/11/17: Re: Error (XST): translate terminal to FCT (bis)
Erwin Oertli:
4663: 96/11/27: Programming the AT17C256
6670: 97/06/12: Re: ATMEL 17Cxxx ISP function
8600: 98/01/12: Re: serial conf. PROMS
11420: 98/08/12: Re: Combinatoric Divide-by-3 Algorithm
Erwin Rol:
40380: 02/03/06: Re: exceeding 2GB limits in xilinx
40574: 02/03/11: Re: exceeding 2GB limits in xilinx
40639: 02/03/12: Re: exceeding 2GB limits in xilinx
48583: 02/10/21: Re: Webpack download problem
Erwin Ruoff:
7883: 97/10/27: Configuring ALTERA in JTAG-chains
ery:
45713: 02/08/01: vcs synplify
eryer:
149047: 10/09/24: Virtex5 minimodule
149303: 10/10/15: Newbie question IO pin and Spartan6
149306: 10/10/15: Re: Newbie question IO pin and Spartan6
<eryksson@gmail.com>:
120588: 07/06/11: Unexpected resources utilization
120601: 07/06/11: Re: Unexpected resources utilization
eschabor:
152331: 11/08/10: Re: FPGA
153075: 11/11/27: Re: Compatible Xilinx USB Cables: worth to bother?
Eser Chamoglu:
37319: 01/12/07: Re: For Sale: Huge Xilinx FPGA lots
Eshkar Lidor:
905: 95/03/27: ASIC data sites
Eshwar:
102879: 06/05/22: FPGA PCIe core connectivity w/ a PC
103101: 06/05/25: Xilinx ML321 (v2pro rocket io): Adding PCIe functionality
103296: 06/05/30: Re: Xilinx ML321 (v2pro rocket io): Adding PCIe functionality
Eshwar varma:
157943: 15/05/19: Oqpsk Demod
eSjteTuV:
22240: 00/05/02: <!-- To use a different cobrand, make sure you have a template for it in /parts/cobrand/ -->
Espen Tallaksen:
158568: 15/12/29: Re: FPGA for a beginner
158659: 16/03/04: Advanced VHDL Verification - Made simple - For anyone
158692: 16/03/09: Simplify handling of SW accessible registers in FPGA
158923: 16/05/25: VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for
159454: 16/11/16: Free webinar on UVVM (Universal VHDL Verification Methodology, Free
160143: 17/06/21: =?UTF-8?Q?VHDL_Verification_components_=E2=80=93_The_obvious_solutio?=
160505: 18/02/27: Re: HDL simple survey - what do you actually use
160582: 18/04/24: =?UTF-8?Q?Free_Webinar_Thursday=3A___UVVM_=E2=80=93_The_standardized_o?=
160590: 18/05/04: Sharing VHDL Verification IP
161191: 19/02/25: =?UTF-8?Q?Your_existing_VHDL_testbench_says_=E2=80=98Hello_world=E2=80=99_?=
161312: 19/03/27: Re: High-level synthesis
Espen Tislevoll:
18065: 99/09/27: EHW and Virtex
18300: 99/10/13: Interconnecting LUTs on a Virtex
<espen.tallaksen@bitvis.no>:
156118: 13/11/28: Free VHDL Testbench library for logging/reporting and checking. A
ESPSys:
3636: 96/07/05: Re: size of fpga
4452: 96/10/30: Re: VHDL for Xilinx designs?
essay:
80129: 05/03/02: Nios II timing question
80258: 05/03/03: Re: Nios II timing question
80325: 05/03/04: Re: Nios II timing question
Essy:
138653: 09/03/03: Re-synthesizing with minor changes
138656: 09/03/03: Re: Re-synthesizing with minor changes
139250: 09/03/24: Flow Control
<est0@lehigh.edu>:
23633: 00/07/04: How to augment the output of a Xilinx lfsr in verilog??
23653: 00/07/04: Re: How to augment the output of a Xilinx lfsr in verilog??
<estess@rtisDOTray.com>:
9948: 98/04/15: Dynachip DL6035
<eswar.saladi@gmail.com>:
122951: 07/08/12: Used Stratix II FPGA's
etantonio:
133703: 08/07/10: Low cost solution to program Spartan 3AN DSP development board
153702: 12/04/26: No bitstream generation on ISE 13.4 evaluation license
153705: 12/04/26: Re: No bitstream generation on ISE 13.4 evaluation license
153706: 12/04/27: Platform Cable USB II in Windows 7 not Found (ISE 13.4)
153708: 12/04/28: Re: Platform Cable USB II in Windows 7 not Found (ISE 13.4)
Etantonio:
79255: 05/02/15: Electronics on ... www.etantonio.it
80975: 05/03/15: Help on Looser-Take-All / Winner-Take-All circuit
133809: 08/07/16: Re: Low cost solution to program Spartan 3AN DSP development board
133825: 08/07/16: Re: Low cost solution to program Spartan 3AN DSP development board
<etantonio@gmail.com>:
95442: 06/01/23: Xilinx ISE & StateCad
eteam:
28313: 01/01/05: Re: Fixing pins on Spartan II
28380: 01/01/10: Re: Xilinx Spartan II - PQ208 Orcad symbols
28443: 01/01/12: Re: APEX20K multi-device configuration
28508: 01/01/15: Re: grey code counters -- BUG FIX (OOPS!)
29447: 01/02/21: Re: Clocks
29645: 01/03/03: Re: Bad Xilinx bitstream=big bang?
30632: 01/04/19: Re: some general questions about FPGA design
30669: 01/04/22: Re: Something about the counter
31432: 01/05/23: Re: fast divider
31450: 01/05/24: spartan xl rise/fall time ?
31578: 01/05/30: Re: Help: RAM clear in one clock cycle
31817: 01/06/06: Re: Help needed on Max7000 pin assignments (Max-plus II)
32038: 01/06/11: Re: Pin locking in Maxplus2
145286: 10/02/04: Re: university platform cable
Etem Tezcan:
77220: 04/12/30: Re: AHB VHDL code
Eternal Vigilance:
<eternal_nan@yahoo.com>:
83625: 05/05/04: Re: Virtex 4 Power consumption
93980: 06/01/04: Spartan 3 PCI development card
104081: 06/06/18: Re: High speed differential to single ended
104139: 06/06/19: Re: High speed differential to single ended
Etienne Racine:
19457: 99/12/22: Re: XC4000E
19659: 00/01/07: Re: Virtex real time debugging
19907: 00/01/17: Re: Random Number Generator
20380: 00/02/08: Re: FLASH-based reconfigurability
20867: 00/02/24: Virtex DLL & JTAG (was Re: Xchecker schematic?)
21784: 00/03/31: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
21796: 00/03/31: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
21906: 00/04/06: Re: JTAG programming
21915: 00/04/06: Re: JTAG programming
23319: 00/06/22: Re: JTAG for debugging on Xilinx devices?
23487: 00/06/27: Re: JTAG emulation of TI DSPs
23644: 00/07/04: Re: BIST in FPGAs?
23678: 00/07/05: Re: Serial Number embedded in PROM.
23862: 00/07/13: Re: Boundary-Scan Tests with JTAG Technologies Tools
24509: 00/08/11: Re: Xilinx, XVC300, 18V02
26667: 00/10/24: Re: Xilinx configuration: JTAG and SPROM
26974: 00/11/06: Re: FPGA programming through XC18V00 eeprom
26983: 00/11/06: Re: FPGA programming through XC18V00 eeprom
27880: 00/12/13: Re: Programming Altera and Xilinx FPGAs with JTAG
28135: 00/12/22: Re: XC18V02 programming with xsvf file
<etorkild@gmail.com>:
129577: 08/02/27: Making changes to custom IP in EDK
etrac:
60308: 03/09/10: Power on problems
60489: 03/09/15: Re: Power on problems
61933: 03/10/15: Re: Power on problems
62126: 03/10/20: Re: Power on problems
63123: 03/11/15: Re: Power on problems
64541: 04/01/07: SDRAM Controller timing problem
65094: 04/01/20: Re: SDRAM Controller timing problem
65169: 04/01/21: Re: SDRAM Controller timing problem
<etvive@wanadoo.es>:
71650: 04/07/26: Programming a LCD display with a Celoxica RC100
72455: 04/08/19: A timer with Celoxica RC100
EU:
56448: 03/06/05: Re: DES-encrypt, Spartan3, was Re: FPGA's an Flash
58906: 03/08/04: Re: Parallel Port EPP in FPGA
<eubanksster@gmail.com>:
135965: 08/10/24: Learning WinCUPL; Tried Atmel Suppport but no solution!
135985: 08/10/25: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
135986: 08/10/25: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
135990: 08/10/25: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
=?euc-kr?B?uLa9rA==?=:
118379: 07/04/25: OPB master and slave interface for DDR SDRAM controller
=?EUC-KR?B?wNPA58iv?=:
21305: 00/03/16: question for virtex
21377: 00/03/21: How I can DLL function unsing VHDL in Virtex?
21398: 00/03/22: qestion for Vref pin of Virtex chip
23008: 00/06/09: Please,give me solution for "serious pad to pad delay" in Xilinx.
Eug:
79995: 05/02/28: Problem with LXT970A
84918: 05/05/31: problems with Ultra DMA operations with ATA HDD
EUG:
9136: 98/02/24: ¿Altera to Xilinx? ¿Max+Plus II to Foundation??
<eugen@research.nj.nec.com>:
179: 94/09/12: CPU Research POSTDOC Position
1768: 95/08/29: Research positions available: parallel architectures
1867: 95/09/12: positions available-hardware design
Eugen_pcad_ru:
150995: 11/02/28: PLL Cyclone III vs PLL(DLL) Spartan-3AN
Eugene Fleisher:
10890: 98/06/28: Universal Altera FPGA Downloader - ByteBlaster replacement
10891: 98/06/28: FPGA Downloader - ByteBlaster that works 1.8 V - 5 V
10953: 98/07/07: Altera FPGA Downloader - ByteBlaster Replacement Works 1.8 - 5V
11191: 98/07/24: Altera FPGA/EPLD Downloader that works with any voltage (1.8 - 5 V)
13683: 98/12/17: AnyVoltage Altera FPGA Downloader
Eugene Grayver:
16791: 99/06/08: Die size of Xilinx FPGAs
16924: 99/06/17: Die size of XILINX fpga's
Eugene Sablin:
36104: 01/10/30: Re: University project: DSO
<eugene_huh@yahoo.com>:
13172: 98/11/18: Configuring using Parallel port
<eugenef@jps.net>:
14385: 99/01/28: AnyVoltage Altera Downloader, works 1.8 v - 5.5 V
15188: 99/03/12: AnyVoltage Altera FPGA Downloader - ByteBlaster
15427: 99/03/24: AnyVoltage Altera ByteBlaster 1.8V-5.5V
15680: 99/04/07: AnyVoltage Altera Downloader (ByteBlaster) 1.8v-5.5v
eugenir:
23043: 00/06/10: Re: XILINX RAM Useless
Eugeny M. Zubok (Studio Sound, Ltd.):
28676: 01/01/20: Clear Logic and ALTERA
eulia:
154281: 12/09/23: How to estimate PEAK power consumption on Xilinx FPGA ?
Eun Jong Hong:
15193: 99/03/12: Estimating Post-Layout Info
Euripides Sotiriades:
18742: 99/11/11: read back Altera
EuroEDA Information:
27832: 00/12/11: VHDL Studio for Linux
29301: 01/02/13: Expressive V3 Released in Europe
34543: 01/08/29: X-HDL translation tool now available in Europe from EuroEDA
euronet:
12429: 98/10/12: Exciting Career Opportunities
12430: 98/10/12: Exciting Career Opportunities
Eva Lau:
60681: 03/09/19: Some question about using FPGA
Evagelia Diamantakou:
1923: 95/09/20: Simulation using XC3000 libraries
1934: 95/09/21: Functional simulation of XC3000 libraries
<EvalXX@gmail.com>:
117378: 07/03/29: Re: Problems with Xilinx Parallel III Cable
Evan:
54926: 03/04/22: Re: Boycott All Xilinx products untill they correct all ISE software errors
evan:
81494: 05/03/24: nios-convert
88798: 05/08/28: Altera nios-debug via JTAG
Evan Lavelle:
30385: 01/04/05: Re: QPSK phase rotator implementation in FPGA ?
78568: 05/02/03: CLOCK_SIGNAL constraint/XST?
78616: 05/02/04: Re: See Peter's High-Wire Act next Tuesday
79907: 05/02/25: Re: dealing with NGO files
81179: 05/03/18: Re: Which HDL?
98384: 06/03/09: Re: for all those who believe in ASICs....
98468: 06/03/10: Re: for all those who believe in ASICs....
98651: 06/03/14: Re: for all those who believe in ASICs....
98653: 06/03/14: Re: for all those who believe in ASICs....
104720: 06/07/05: Re: Chaos in FF metastability
104721: 06/07/05: Re: Chaos in FF metastability
104751: 06/07/05: Re: Chaos in FF metastability
104754: 06/07/05: Re: Chaos in FF metastability
106060: 06/08/07: 3.3V configuration of Spartan-3?
106125: 06/08/08: Re: verilog versus vhdl
106146: 06/08/08: Re: verilog versus vhdl
106147: 06/08/08: Re: verilog versus vhdl
106157: 06/08/08: Re: 3.3V configuration of Spartan-3?
106160: 06/08/08: Re: verilog versus vhdl
106270: 06/08/10: Re: xst synthesis with attributes failure
106616: 06/08/16: Re: Maximum Current Draw of FPGA
106621: 06/08/16: Open-source JTAG software?
106634: 06/08/16: Re: Open-source JTAG software?
106710: 06/08/17: Re: FFT on an FPGA
110711: 06/10/20: SDF sim failure: 8.2i/Spartan-3
110825: 06/10/24: Re: SDF sim failure: 8.2i/Spartan-3
111032: 06/10/27: Survey: simulator usage
111109: 06/10/29: Re: Survey: simulator usage
111110: 06/10/29: Re: Survey: simulator usage
111111: 06/10/29: Re: Survey: simulator usage
111389: 06/11/02: Re: A spectre is haunting this newsgroup, the spectre of metastability
111399: 06/11/02: Re: A pre-emptive strike against blaming the chip
111400: 06/11/02: Re: Yet Another Survey: What are code generators worth?(was: Re: Survey: simulator usage)
111403: 06/11/02: Re: A spectre is haunting this newsgroup, the spectre of metastability
111457: 06/11/03: Re: Scientific Computing on FPGA
111590: 06/11/06: Xilinx GSR/reset levels (was: Re: reset)
120461: 07/06/07: Re: Topics and Ideas for BS Project
120618: 07/06/12: Re: Topics and Ideas for BS Project
120688: 07/06/13: Re: Topics and Ideas for BS Project
121023: 07/06/22: Re: Cadence TestBuilder
121100: 07/06/25: Re: Cadence TestBuilder
122290: 07/07/25: Re: pci express pinout
122291: 07/07/25: Re: verilog parser question about `defines
122626: 07/08/01: Re: Looking for PLD with embedded memory
122697: 07/08/03: Re: Static Timing Analysis Using Primetime for FPGAs
122701: 07/08/03: Re: Static Timing Analysis Using Primetime for FPGAs
124463: 07/09/22: Re: Answer: maximum number of state machines in a current chip: > 500k
124700: 07/10/01: Xilinx ISE 'feature': forcing a DUT signal
124714: 07/10/01: Re: Xilinx ISE 'feature': forcing a DUT signal
124814: 07/10/05: Re: Tcl - Xilinx - ISE - WindowsXP
125071: 07/10/16: Re: FPGA quiz: what can be wrong
125173: 07/10/17: Re: FPGA quiz: what can be wrong
131394: 08/04/21: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131435: 08/04/21: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131436: 08/04/21: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131469: 08/04/22: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
133411: 08/06/27: Standard forms for Karnaugh maps?
133423: 08/06/28: Re: Standard forms for Karnaugh maps?
133481: 08/07/01: Re: Standard forms for Karnaugh maps?
133482: 08/07/01: Re: Standard forms for Karnaugh maps?
134844: 08/09/03: Re: XST bug on illigal states of a FSM ?
134850: 08/09/03: Re: XST bug on illigal states of a FSM ?
134859: 08/09/04: Re: XST bug on illigal states of a FSM ?
<"Evan MacArthur"ypuq@osame.com>:
Evan Samuel:
15574: 99/03/31: Schematic Capture & FPGA synthesis
15582: 99/03/31: Re: Schematic Capture & FPGA synthesis
85735: 05/06/15: Re: Problem for xilinx!!!
85739: 05/06/15: Re: Xilinx LVDS and SCSI
85740: 05/06/15: Re: Searching FPGA board for private use
85741: 05/06/15: Re: Best Practices for Hardware Designers
Evan Speight:
14598: 99/02/05: Place and Route Times question
<evans39084@aol.com>:
55223: 03/05/01: Re: Boycott All Xilinx products untill they correct all ISE software errors
55281: 03/05/02: Re: Boycott All Xilinx products untill they correct all ISE software errors
<evansamuel@charter.net>:
120924: 07/06/20: Re: Interesting problems about high performance computing
121058: 07/06/24: Re: How to create simple design?
121157: 07/06/27: Re: How to create simple design?
121224: 07/06/28: Re: How to create simple design?
121528: 07/07/06: Re: Multiplier in Xilinx
121531: 07/07/06: Re: How to choose FPGA for a huge computation?
<evanst@sourcesvc.com>:
8436: 97/12/14: ' MA-Boston ASIC/FPGA FULL RELO provided to qualified candidates.
EveEllsworth:
83660: 05/05/04: Does this group allow JobPostings?
Everett:
152958: 11/11/04: Choose between Cyclone II and Spartan II
Everett M. Greene:
25628: 00/09/15: Re: hardware compatibility and patent infringement
45402: 02/07/22: Re: TMS 1000
82073: 05/04/06: Re: ISA vs. patent/trademark
82154: 05/04/07: Re: ISA vs. patent/trademark
95059: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95225: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95226: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95227: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95327: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95445: 06/01/23: Re: OT:Shooting Ourselves in the Foot
108213: 06/09/06: Re: Please help me with (insert task here)
130588: 08/03/27: Re: A Challenge for serialized processor design and implementation
130620: 08/03/28: Re: A Challenge for serialized processor design and implementation
130621: 08/03/28: Re: A Challenge for serialized processor design and implementation
132791: 08/06/06: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
everphilski@gmail.com:
129006: 08/02/12: Newbie looking for guidance
129039: 08/02/13: Re: Newbie looking for guidance
129040: 08/02/13: Re: Newbie looking for guidance
Evgeni:
62396: 03/10/28: Virtex-II DCM frequency synthesizer
Evgeny Filatov:
158183: 15/09/12: low-level vs. high-level
158204: 15/09/14: Re: low-level vs. high-level
158212: 15/09/15: Re: low-level vs. high-level
158219: 15/09/23: Re: Why is this group so quiet?
158827: 16/04/23: Re: Challenges in data science which can be solved with FPGAs
159350: 16/10/14: Re: CORDIC in a land of built-in multipliers
159360: 16/10/15: Re: CORDIC in a land of built-in multipliers
159423: 16/11/03: Re: Quad-Port BlockRAM in Virtex
159427: 16/11/04: Re: Quad-Port BlockRAM in Virtex
159432: 16/11/05: Re: Quad-Port BlockRAM in Virtex
160287: 17/10/22: Re: Beginer's FPGA with SERDES
160290: 17/10/23: Re: Beginer's FPGA with SERDES
Evgeny Shamin:
43421: 02/05/21: RS232 a utility for debugging serial data transfers between devices.
Evgeny V. Vlasov:
1540: 95/07/11: I want to work in expert system. Help!
evilkidder@googlemail.com:
115688: 07/02/16: LUT based virtex multiplier
115696: 07/02/16: Re: LUT based virtex multiplier
117659: 07/04/06: Re: PCI FPGA Dev Board Suggestions
118882: 07/05/05: Re: Atom HDL
121550: 07/07/07: Re: verilog code for read write in Bram block
125267: 07/10/18: Re: VHDL trivia?
125300: 07/10/19: Re: VHDL trivia?
125685: 07/10/31: Re: Capability of a FPGA device.
125767: 07/11/04: Re: How do I meet this memory IO with least resources on FPGA?
126214: 07/11/16: Re: New Laptop for work
138490: 09/02/24: Re: XST hangs on HDL Analysis
140709: 09/05/22: Re: Unable to run 'xdl -ncd2xdl' on RHEL 5.3 in ISE 10.1
140725: 09/05/22: Re: Unable to run 'xdl -ncd2xdl' on RHEL 5.3 in ISE 10.1
142510: 09/08/13: Re: Mixed language simulation on the cheap
142826: 09/09/02: Re: Choice of Language for FPGA programming
147186: 10/04/16: Re: I'd rather switch than fight!
150386: 11/01/14: Re: Verilog Book for VHDL Users
150390: 11/01/15: Re: Verilog Book for VHDL Users
156203: 14/01/17: Re: Math is hard
<evjapps@inet.uni-c.dk>:
5366: 97/02/11: Re: Serial Communication Controller Design
6547: 97/06/02: Re: Altera Versus Xilinx
6548: 97/06/02: Re: I2C Interface
Evolvable Hardware Conference:
53232: 03/03/07: CFP: 2003 NASA/DoD Conference on Evolvable Hardware
EvSpace:
148145: 10/06/23: Spartan-3E starter kit USB schematics ? (again)
evspronsen:
66841: 04/02/27: comp.arch.fpga : Multisource databus
Ewa:
116230: 07/03/05: Nios II Multiprocessor Collection run in command line
Ewan D. Milne:
1128: 95/05/03: Re: Lattice EPLDs
2130: 95/10/18: Re: Xilinx Configuration Memory Hacking
2193: 95/10/30: Re: Xilinx Configuration Memory Hacking
2521: 95/12/26: Xiling 4025E routing info
3130: 96/04/09: Re: Sun bpp bidirectional parallel port
6081: 97/04/10: Re: Download Xilinx Fpga
10454: 98/05/19: Xilinx Foundation Student Edition
20393: 00/02/08: XC3000 series w/Foundation Student Edition?
20895: 00/02/25: Foundation 2.1i device support?
46341: 02/08/26: Virtex2 Pro Device support in Webpack?
49741: 02/11/20: Foundation 2.1i with Windows 2000?
77366: 05/01/05: iMPACT 5.1i w/Parallel Cable
77382: 05/01/05: Re: iMPACT 5.1i w/Parallel Cable
77441: 05/01/06: Re: iMPACT 5.1i w/Parallel Cable
86406: 05/06/27: Re: Poor PCI performance during read accesses (in master mode)
Ewan D. Milne x3767:
5072: 97/01/20: Re: ASICs Vs. FPGA in Safety Critical Apps.
<ewcce@aol.com>:
31042: 01/05/10: Important news
Ewerson Carvalho:
55631: 03/05/14: deficiency ICAP information.
57513: 03/07/01: VirtexII bitstream relocation
57665: 03/07/03: Re: VirtexII bitstream relocation
58357: 03/07/21: Re: CRC questions
<ewngkj@hotmail.com>:
16811: 99/06/10: Free Sex Links 7070
Executive Search:
6694: 97/06/16: San Diego, Ca.--MTS-FPGA Field Applications Engineer-Recruiter
7058: 97/07/28: San Diego/Santa Clara/Boston--MTS-FPGA Field Applications Engineer-Recruiter
7063: 97/07/28: San Diego/Santa Clara/Boston--MTS-FPGA Field Applications Engineer-Recruiter
7158: 97/08/07: San Diego/Santa Clara/Boston--MTS-FPGA Field Applications Engineer-Recruiter
7531: 97/09/19: San Diego/Santa Clara/Boston--MTS-FPGA Field Applications Engineer-Recruiter
7536: 97/09/19: San Diego/Santa Clara/Boston--MTS-FPGA Field Applications Engineer-Recruiter
7535: 97/09/19: Santa Clara/Boston--MTS-FPGA Field Applications Engineer-Recruiter
7796: 97/10/16: US-Co. Boulder-Site Manager/Software Development Mgr-CAD/FPGA
7799: 97/10/16: US-Pa.-Field Applications Engineering Manager-FPGA/ASIC
Exjobbare Joachim Strombergson:
7150: 97/08/07: Techdef file for Xilinx4013?
7254: 97/08/19: LogiBLOX components in VHDL?
Expensimundo:
33267: 01/07/20: Re: what tools run OK on windows 2000?
Experiment 5:
53570: 03/03/17: Re: footprints
explore:
132193: 08/05/16: System configuration for Xilinx ISE 10.1 - Virtex 5 LX110t or bigger
133058: 08/06/16: XAUI v7.2 - timing issue - *channel bonding attributes*
133060: 08/06/16: Re: XAUI v7.2 - timing issue - *channel bonding attributes*
133287: 08/06/23: XAUI - INTERNAL LOOPBACK SETUP - DRP (DYNAMIC RECONFIGURATION PORT)
133319: 08/06/24: Re: XAUI - INTERNAL LOOPBACK SETUP - DRP (DYNAMIC RECONFIGURATION
154006: 12/07/10: XAUI on V5 FX200T
Extern:
28516: 01/01/16: Re: Please explain these terms
34700: 01/09/04: Re: Interfacing Verilog and VHDL
extra z to stop junk mail:
4305: 96/10/12: Re: Async with FPGA?
4308: 96/10/12: Re: Viewlogic v4.1 Plotter.exe cmd line usage?
4325: 96/10/16: Re: Seeking 16V8: Vcc=3.0-5.0V: Zero standby power.
4363: 96/10/20: Re: price conversion from FPGA to gate array
4362: 96/10/20: Re: VHDL for Xilinx designs?
4376: 96/10/22: Re: VHDL for Xilinx designs?
4406: 96/10/24: Re: VHDL for Xilinx designs?
4405: 96/10/24: Re: Xilinx xchecker.exe and Windows NT
Extrarius:
74274: 04/10/07: Advice for a Beginner?
74446: 04/10/11: Re: Advice for a Beginner?
75136: 04/10/26: Re: inefficient mux synthesis in quartus
Eyal Shachrai:
42944: 02/05/08: DDR reference design
43000: 02/05/08: Re: DDR reference design
43376: 02/05/20: virtex II : CLB with two clocks
43429: 02/05/21: virtex II : DCM phases
43537: 02/05/23: virtex II : FDDRRSE instantiation
43687: 02/05/29: virtex 2 : DCM divided clock
43799: 02/06/03: divide by 5
43888: 02/06/05: virtex 2 : IOBUF tristate plarity
43895: 02/06/05: virtex 2 : init values
44592: 02/06/24: virtex2 : ALT_VRP / ALT_VRN
44763: 02/06/29: virtex2 : 180 deg. phase clocks
46507: 02/09/01: virtex2 : high pulse during configuration
60352: 03/09/10: xilinx ace ibis
Eyal Soha:
8399: 97/12/12: RC5-64 on FPGA
Eyck Jentzsch:
41282: 02/03/25: Re: SystemC compiler
65198: 04/01/22: Re: Synthesis errors?
71945: 04/08/04: Re: Manipulation on netlist for faster simulation.
<eyecatcherdear@gmail.com>:
156019: 13/11/10: generating clocks
156036: 13/11/12: Re: generating clocks
156059: 13/11/17: Re: generating clocks
156190: 14/01/11: 3/4 Punctured Convolution encoding
156385: 14/03/25: Re: 3/4 Punctured Convolution encoding
Eyyub Can Odacioglu:
141791: 09/07/09: EDK 8.2 executable.elf
148500: 10/07/28: please help and advice : Error: Pack:1107 - Unable to combine the
ez:
13420: 98/12/02: Re: Is it normal to have to edit the xnf file???
<eziggurat@gmail.com>:
97116: 06/02/16: WIFI Compact Flash
97121: 06/02/16: Re: VHDL or verilog
98811: 06/03/16: PowerPC Problems in Virtex
98861: 06/03/17: Re: PowerPC Problems in Virtex
98862: 06/03/17: Re: SerialATA with Virtex-II Pro
108334: 06/09/08: Gamma values for LCD modules
108481: 06/09/11: Linear Interploation Algorithms
108664: 06/09/14: Re: Linear Interploation Algorithms
ezpcb.com:
80689: 05/03/10: FIR Filter On FPGA
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