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HI, Do you about the CAPCLK and CAP signals neccessary for the readback. CAP is capture enable signal and CAPCLK is clock that synchorines the readback. Please refer to XAPP138 for more details on this. -- Prasanna Oct 22 99 Gordon Hollingworth wrote: > Hi, > > I've succesfully implemented a SelectMAP interface to the Virtex chip and > can quickly reconfigure the chip no problem. When I come to readback I send > the correct commands (copied directly from the xilinx datasheet!) and when i > read all I get is 0xff, 0xf3, 0xf1, 0xf9, 0xf9, 0xf9 ....... for 207900 > bytes (V300) > > No matter what I do it doesn't seem to help, I originally assumed the bus > was floating and the above was the results of this, but when I look at the > bus it is being driven by these values!!! > > Help > > GordonArticle: 18401
Deutsche NT Benutzer, ihr könnt DM1800 gewinnen! Wenn ihr in Deutschland sind und einen NT Workstation mit einer der folgenden anwendungen benutzen, M-CAD, Electronic Design, DCC, GIS, Financial Analysis, oderr Software Development gehe zu: http://survey.mt01.com/idc/inwac_gr.asp? Man wird da gefragt ob man mitglied eines ‘epanel’ werden möchte, um dort seine Meinungen über diese Anwendungen zu geben. Es dauert nur ein paar Minuten und ein Bleistift wird euch zugeschickt als ‘dankechön’. Besser als das wird man dann auch in eine Ziehung für ein Palm Pilot hinzugefügt. (Auch Zugang zu verschiendenen Berichten usw..) Sag mir dann auch eure Meinnung.Article: 18402
Download Ia.n.i. RemoteControlSystem 1.2 beta. It's free!!! New site: http://jump.to/IaniProjectArticle: 18403
Hi, Altera has a parameterizable Interleaver/DeInterleaver http://www.altera.com/html/tools/mc-interleaver.html Philippe In article <380E4E62.C68598CD@yahoo.com>, Lorant <lorante@yahoo.com> wrote: > Hello, > > Has anyone coded interleaver/deinterleaver modules in Verilog. I'm > looking for > information on interleavers/deinterleavers. Thanks in advance for > anyones help. > > Lorant > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18404
Oops! that should be Do you know about the CAPCLK and CAP signals neccessary for the readback?. Now I am including some more info in detail: To do a readback capture, the Virtex library primitive CAPTURE_VIRTEX must be instantiated in the user design. When a capture is initiated, the flip flop states are loaded into the configuration memory, which may be extracted after a readback of the configuration memory. The CAPTURE_VIRTEX primitive is used to control when the logic states of all the registers are captured into the configuration memory. (See the libraries guide for more details.) CAPTURE_VIRTEX needs two inputs, CLK and CAP to initiate and perform the readback. The CLK pin may be driven by any clock source that would synchronize capture to the changing states of the register. The CAP pin is an enable control. When the CAP is asserted, the register states will be captured into memory on the next CLK transistion. -- Prasanna Oct 22 99 Prasanna Sundararajan wrote: > HI, > Do you about the CAPCLK and CAP signals neccessary for the readback. CAP is > capture enable signal and CAPCLK is clock that synchorines the readback. Please > refer to XAPP138 for more details on this. > > -- > Prasanna > Oct 22 99 > > Gordon Hollingworth wrote: > > > Hi, > > > > I've succesfully implemented a SelectMAP interface to the Virtex chip and > > can quickly reconfigure the chip no problem. When I come to readback I send > > the correct commands (copied directly from the xilinx datasheet!) and when i > > read all I get is 0xff, 0xf3, 0xf1, 0xf9, 0xf9, 0xf9 ....... for 207900 > > bytes (V300) > > > > No matter what I do it doesn't seem to help, I originally assumed the bus > > was floating and the above was the results of this, but when I look at the > > bus it is being driven by these values!!! > > > > Help > > > > GordonArticle: 18405
I'm designing a board with a Virtex FPGA, a CPLD, and a byte-wide Flash. In normal power-up, the FPGA will configure in SelectMap mode out of the Flash with the CPLD providing control/addressing. I would also like to be able to program the FPGA or CPLD or the Flash serially via JTAG. Programming the FPGA or CPLD over JTAG is easy with jtagpgmr, but I would like to use the CPLD to program the Flash from serial data. I'm limited on backplane I/O. Have thought about wrapping the CPLD TDO back into another CPLD pin to provide serial data, which then would be shited into bytes and programmed into the flash by the CPLD. One concern I have is the JTAG instruction data for Bypass getting passed along with the Flash data. Could just offset the data. Would I want to send a Bypass instruction then the bit file for the FPGA? Another option may be to just use more of an Xchecker type interface with just clk and data on two dedicated backplane I/O. Then just download an MCS or hex using Xchecker over these non-JTAG I/O. Just wanted to see what others though about this. It wouldn't surprise me, if somebody has already done this... --Brady Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18406
Also, the tristate long lines run horizontally, favoring left and right edges for I/O to bussed internal registers. Ray Andraka wrote: > > It comes from the fact that the carry chains run vertically. The data busses > not only should be along the sides, but they should also be arranged so that > the LSB is at the bottom. The reason is to keep the routing as short and > simple as possible. > -- Tom Burgess -- Digital Engineer National Research Council of Canada Herzberg Institute of Astrophysics Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3Article: 18407
I see what you mean. Between that and epic and the data published on the Virtex bit stream you should be able to completely reverse engineer the programming for the Virtex. It reminds me of the old LCA format. Makes me wonder why they just don't document the whole thing and be done with it. Steve Casselman, President Virtual Computer Corporation Andreas Doering <doering@iti.mu-luebeck.de> wrote in message news:380F6BC6.FEB3F52C@iti.mu-luebeck.de... > Hi, > more by accident I found the program XDL in my Alliance distribution. > XDL is a program that converts a XILINX design between ncd > (binary undocumented internal) and XDL an ASCII format. > Beside of two work around answers in the data base I have not yet found > any hint or documentation on this. > I think this is a great thing, because it is much easier > finding things, you can use grep/wc/perl what you like > to check things. > Without xdl the only way back to a processable text file is pre-map with > ngd2vhdl/ngd2edif and the like. > Only timing information can added. > I think that such open interfaces are a big win, > especially for reconfigurable computing because access > to very low end features are possible without re-engineered > bit-stream manipulation. > (Of course, meanwhile there is also JavaBits). > Andreas > > ----------------------------------------------------------------- > Andreas C. Doering > Medical University Luebeck, Germany > Home: http://www.iti.mu-luebeck.de/~doering > quiz, papers, VHDL, music > "The fear of the LORD is the beginning of ... science" (Proverbs 1.7) > ---------------------------------------------------------------- >Article: 18408
No. You are all wrong. The Klingons are the only people able to cloak a MAX device, and it requires a quantum hilarity to power it. Or do I mean the ROMulans ?. -- Edward MooreArticle: 18409
Hi all, I am using Foundation 1.5i software service pack #2. I am getting the following Map error for some of my big designs: " FATAL_ERROR:basnc:basncbel.c:142:0.0 - NC_BEL name <inst_1/inst_11/inst_111/inst_1111/inst_11112/inst_111121/inst_1111211/inst_ 11 112112/inst_111121121/inst_1111211211/inst_11112112111/inst_111121121111/ins t _1111211211111/inst_11112112111111/inst_111121121111113/inst_111121121111113 1 /inst_11112112111111311/inst_111121121111113111/inst_1111211211111131111/ins t _11112112111111311111/inst_111121121111113111112/inst_1/$I6/inst_1/inst_11/i n st_111/inst_1111/inst_11112/inst_111121/inst_1111211/inst_11112112/inst_1111 2 1121/inst_1111211211/inst_11112112111/inst_111121121111/inst_1111211211111/i n st_11112112111111/inst_111121121111113/inst_1111211211111131/inst_1111211211 1 111311/net_11112112111111311_2> is too long Process will terminate. Please call Xilinx support. " I had a look at Xilinx data base but did not find a similar case, sent a query to Xilinx help, & still waiting! Has anybody experienced such a problem? Please help! Cheers.Article: 18410
Allan Herriman <allan.herriman.hates.spam@fujitsu.com.au> wrote in article <380fdc19.6028487@newshost.fujitsu.com.au>... > On Thu, 21 Oct 1999 17:55:14 -0400, Ray Andraka <randraka@ids.net> > wrote: > > [snip] > >Someone asked offline what > >constitutes "up" on the chips. A good question, so I'll repeat the answer here. > >Up is what shows as up when you open the floorplanner. IIRC, the quad flatpacks > >have pin one on the top edge. The best way to make sure you get it right is to > >open the floorplanner for the chip and package you are using and look at the pin > >numbers - they are printed on the floorplan screen. Is there a way to do this without having to create a blank design for it to 'read' in? > > This is also how you figure > >out which pins align with which rows/columns. > > I recently had to go through this very exercise. Does anyone know why > this essential information isn't stated explicitly in the data book? OR better yet, why they don't have either an Adobe Acrobat (preferred) or PostScript printable and legible document for each package/die combination. It gets VERY tedious making these for the new Virtex chips....Article: 18411
Ken McElvain wrote: >Here is a more straightforward way of building your own F/HMAPs >and placing them via Synplify. It is also simulatable. I've used xc_map for standalone logic, as in your example, without any problems; as you suggest, it avoids the need for an EQN simulation model. In order to build a complete pipelined carry chain RPM, you also need to control the mapping and placement of flip-flops and carry logic, for which the xc_map attribute doesn't help. Replacing the FMAP/EQN pairs of the carry chain example with xc_map'd entities seems to foul up the HSETs: all of the RLOC'd carry chains and flip-flops still show up as one HSET, but all of the FMAPs implemented with xc_map show up as ungrouped logic needing placement. I haven't yet sorted out why this happens; it could be either a problem with my code or another tool quirk requiring a workaround. I've also had problems using xc_map with packed CLBs; since it doesn't 'know' about flip-flops, if you register the F and G LUT outputs, and then use the H LUT output, the Synplify mapper dies because it thinks all three signals need to exit the CLB on the two available combinatorial outputs. Brian Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18412
I think I posted an example the other day that is similar to this that I have working in a virtex design. I didn't use the xc_rlocs because I couldn't get them to work right with flip-flops and carry chain parts, which are needed as well as the fmaps. A homegrown "RLOC" attribute works fine on xc_map'd LUTs as well as on flip-flops, carry chain components, SRL16's and RAMs. I've successfully gotten a hierarchical RLOC'd 100% placed macro with over 700 CLBs out of this method. I haven't gotten HU_SETs to work right with the homegrown RLOC though. I did have to write an integer to ascii conversion to do the automatic placement. The VHDL function (I can't remember the name now) to do this doesn't seem to be recognized by synplicity. Ken McElvain wrote: > Ken McElvain wrote: > > Here is a more straightforward way of building your own F/HMAPs and > placing > them via Synplify. It is also simulatable. > > library ieee; > use ieee.std_logic_1164.all; > library synplify; > use synplify.attributes.all; > entity fmap_xor4 is > port( z : out std_logic; a, b, c, d : in std_logic); > end entity fmap_xor4; > > architecture lut of fmap_xor4 is > -- tell synplify that this architecture is an "fmap" > attribute xc_map of lut : architecture is "fmap"; > begin > z <= a xor b xor c xor d; > end architecture lut; > > library ieee; > use ieee.std_logic_1164.all; > library synplify; > use synplify.attributes.all; > entity hmap_xor3 is > port( z : out std_logic; a, b, c : in std_logic); > end entity hmap_xor3; > > architecture lut of hmap_xor3 is > attribute xc_map of lut : architecture is "hmap"; > begin > z <= a xor b xor c; > end architecture lut; > > library ieee; > use ieee.std_logic_1164.all; > library synplify; > use synplify.attributes.all; > entity clb_xor9 is > port (z : out std_logic; a, b, c, d, e, f, g, h, i : in std_logic); > end entity clb_xor9; > > architecture clb of clb_xor9 is > -- xc_uset will actually create an HU_SET which will be qualified > -- by the hierarchy path. We could use U_SET as the attribute. > attribute xc_uset of all : label is "myuset"; > attribute xc_rloc of u1 : label is "R0C0.f"; > attribute xc_rloc of u2 : label is "R0C0.g"; > attribute xc_rloc of u3 : label is "R0C0.h"; > signal fout, gout : std_logic; > begin > u1: entity fmap_xor4 port map (fout, a, b, c, d); > u2: entity fmap_xor4 port map (gout, e, f, g, h); > u3: entity hmap_xor3 port map (z, fout, gout, i); > end architecture clb; > > brian_m_davis@my-deja.com wrote: > > > In case anyone else is attempting to build carry > > chain RPM's in VHDL, I've posted an example of an > > XC4000/Spartan carry chain, built by instantiating > > the Xilinx primitives, at: > > > > http://members.aol.com/fpgastuff > > > > file: tc_test1.zip > > > > The code creates a pipelined two's complement CLB > > from the primitives, then places an array of them > > using RLOC's. Although cascading two's complements > > isn't terribly useful, it shows how to work around > > some of the tool quirks encountered when connecting > > and placing the carry primitives. > > > > The example was written for Synplify; check > > "readme.txt" in the zipfile for more info. > > > > Credits: > > > > Thanks to Evan for posting examples of > > synthesizable RLOC's, FMAP's, and EQN's at: > > > > http://www.riverside-machines.com/pub2/xilinx/vhdl_rpm/top.htm > > > > Comments: > > > > I view this method as more of a last resort than > > as part of the normal design flow; the large pile > > of code needed for this example could be replaced > > with a few lines of RTL code using inferred operators, > > plus possibly a couple of minutes in the floorplanner, > > with equivalent results. > > > > The technique is useful for repeated structures > > which need explicit mapping and placement for speed, > > and for building library components smart enough to > > size and place themselves; on the down side, it is > > tough to do pre-synthesis simulation ( e.g., you need > > an EQN model which can parse equation attribute strings.) > > > > Brian > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18413
Don't know. I know that I and several other "power users" have asked for this to be published several times. Austin Franklin wrote: > > > > I recently had to go through this very exercise. Does anyone know why > > this essential information isn't stated explicitly in the data book? > > OR better yet, why they don't have either an Adobe Acrobat (preferred) or > PostScript printable and legible document for each package/die combination. > It gets VERY tedious making these for the new Virtex chips.... -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18414
Workgroup MCU & UPL
Belgium
Hello Bob,
We do agree with the point of view of Ray Andraka and
wish to add
that it will be difficult for Abel (Minc formerly a Data IO division) to get
it's syntaxis
revized as Minc stopped it's activities in '98 - parts were bought by Xilinx
and
Lattice-Vantis LSC.
So I do not believe that Minc's language 'Abel' will be maintained as needs
arise
to adapt it towards new technical (calculation intensive) evolutions.
In this way we stopped investing our time in 'Abel' and changed towards
'VHDL'
because it's believed to have a more prosperous future.
Regards,
Michel HEUTS
WMU
Bob Weber <rweber@txc.com> wrote in message
news:6g4K3.1176$GH4.2498@client...
> Hi,
> I wondering how much Programmable Design work is done using ABEL. I find
it
> useful for small to medium CPLD designs. I am curious about how widespread
> is its use?
> Anyone else use it on a regular basis?
> Bob W
...snip...
I only use Abel for PLD design. Anything larger than a small PLD, I use an
FPGA. Sometimes in the FPGA I use Abel for state machines or combinatorial
logic...but keep my data path in schematic. Easy to use, and works great.
... snip ...
Abel was and is the standard for EPLD and low to moderate size FPGA designs.
Abel is much more compact than VHDL and much more focused for FPGA designs
than VHDL. Typically 1 page of Abel equals 5 pages of VHDL. If you have
Data I/O (Mincs) Synario w/ VHDL you can do designs in either Abel or VHDL
and automatically convert from one another.
Abel is real handy if you need to change devices across manufactures or
accurately compare different devices. You can start a design in Xilinx and
finish it with Lattice painlessly. Simply choose the new device, regenerate
the device fit and your are done.
...snip...
Depends on what you are doing. For mathemeatically intense data-path stuff,
VHDL code can be more compact than ABEL. VHDL is also supported by more
simulators etc.
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
Article: 18415>>Someone asked offline what >>constitutes "up" on the chips. A good question, so I'll repeat the answer >>here. Up is what shows as up when you open the floorplanner. IIRC, the >>quad flatpacks have pin one on the top edge. The best way to make sure >>you get it right is to open the floorplanner for the chip and package you >>are using and look at the pin numbers - they are printed on the floorplan >>screen. This is also how you figure out which pins align with which >>rows/columns. > >I recently had to go through this very exercise. Does anyone know why >this essential information isn't stated explicitly in the data book? > >Allan. This essential data belongs in the data book, and has been requested over and over for at least the last 10 years. The solution for those who care has always been the cumbersome approach of running the XACT chip editor (XDE) in the old days, and EPIC in the most recent software, and FPGA Editor in the current software. Basically, bring up the viewer, then navigate around the perimeter of the display, making notes of the pin labels on your note pad. The Floorplanner has also been an option, but requires a design before it will let you look at the pinout of your target package, which is just a little bit late in the design flow. The only FPGA software product for which this is not true is the XC5200 product line because Xilinx decided not to have XDE support for it. The best solution today is to buy the Fliptronics ChipView program that among other things, includes a template mode where it will show you the pin layout for any XC4000E/EX/XL/XLA/XV or Spartan or SpartanXL chip. http://www.fliptronics.com/flibtools.html works for me. Philip Freidin FliptronicsArticle: 18416
Hello, As far as I know FPGAs have relatively high static power consumption (a few mA) when comparing with an ASIC. Obvisouly we need more transistors when implementing the same design in a FPGA than we need in an ASIC. So the static power should be higher. Is this the only reason why FPGAs have a relatively high static power consumption? Thanks, Jonas ThorArticle: 18417
Hello I have a signal processing application that requires a large amount of floating point arithmetic inside a Xilinx Virtex FPGA. Because the function is rather algorithmic and will require many configurations I want to design at a very high level. Does anyone know a convenient way to synthesize single precision floating point multiplications and additions in VHDL? Through my customer I have access to a tool called Cossap from synopsys. Would that tool help? I have hand crafted a VHDL multiplier for the Virtex architecture that runs at 50MHz with two pipeline registers and two of these will fit into an XCV50. Instantiating these structurally seems awkward for the scale of design work we need to do. Thanks in advance for any ideas. Peter Dudley Arroyo Grande Systems Incorporated Signal Processing in Hardware and SoftwareArticle: 18418
I recommend the Actel Desktop software. It is a complete CAE environment for Actel FPGA's based on the Veribest tool set. It's free until 2000.1.13. Go to http://www.actel.com/ to request the CD. Good luck. Marek Ponca <marek.ponca@et.stud.tu-ilmenau.de> wrote in message news:380D9CE7.E6A74234@et.stud.tu-ilmenau.de... > Hi, > > Hope, that some FPGA expert will spend a minute with this... > > > I want to lear-try something more about programming and synthesizing > to programmable logic devices. > > Can You recommend some tool (for VHDL synthesis), some design board > (starter kit) ? > (FPGA and CPLD boards too) > > Are there some known problems (especially for beginners) with specific > chips ? > > > Thanks > > > -- > > Marek Ponca > > > Fak. der Elektrotechnik und Informatik > FG Mikroelektronische Schaltungen ud Systeme > TU Ilmenau > PF 10 05 65 > 986 84 Ilmenau > Deutschland > > Tel: 0049 3677 69 1168 > Fax: 0049 3677 69 1163Article: 18419
You need to decide what family you are interested in pursuing before chosing a 'starter kit'. If you are doing anything that involves lots of artihmetic or counters, then you'll probably want to use a device that has a carry chain:xilinx, altera 10k or 20K or lucent. If it's a dsp application, you'll want to have the ability to use the CLBs as RAM to implement lots of independent delay queues: rules out altera. If you're gathering a bunch of random logic or have lots of high fanin combinatorial logic, the altera architecture is probably going to work better for you. Go on-line and peruse the databooks for the devices you are interested in. Look particularly at the CLB structure an try to imagine how your typical circuit would be implemented in that technology. Not a pretty starting place, I know, but it is the best place to start if you want the best fit to the device. peter dudley wrote: > I recommend the Actel Desktop software. It is a complete CAE environment for > Actel FPGA's based on the Veribest tool set. It's free until 2000.1.13. Go > to http://www.actel.com/ to request the CD. > > Good luck. > > Marek Ponca <marek.ponca@et.stud.tu-ilmenau.de> wrote in message > news:380D9CE7.E6A74234@et.stud.tu-ilmenau.de... > > Hi, > > > > Hope, that some FPGA expert will spend a minute with this... > > > > > > I want to lear-try something more about programming and synthesizing > > to programmable logic devices. > > > > Can You recommend some tool (for VHDL synthesis), some design board > > (starter kit) ? > > (FPGA and CPLD boards too) > > > > Are there some known problems (especially for beginners) with specific > > chips ? > > > > > > Thanks > > > > > > -- > > > > Marek Ponca > > > > > > Fak. der Elektrotechnik und Informatik > > FG Mikroelektronische Schaltungen ud Systeme > > TU Ilmenau > > PF 10 05 65 > > 986 84 Ilmenau > > Deutschland > > > > Tel: 0049 3677 69 1168 > > Fax: 0049 3677 69 1163 -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18420
Part of it comes from making the transistors 'leaky' so that they can switch faster. An FPGA could be made with considerably lower power if the fabrication process were tweaked for power instead of speed, but they'd be a lot slower, and well, speed sells. Jonas Thor wrote: > Hello, > > As far as I know FPGAs have relatively high static power consumption > (a few mA) when comparing with an ASIC. Obvisouly we need more > transistors when implementing the same design in a FPGA than we need > in an ASIC. So the static power should be higher. > > Is this the only reason why FPGAs have a relatively high static power > consumption? > > Thanks, Jonas Thor -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18421
On 23 Oct 1999 04:42:10 GMT, fliptron@netcom.com (Philip Freidin) wrote: > >>>Someone asked offline what >>>constitutes "up" on the chips. A good question, so I'll repeat the answer >>>here. Up is what shows as up when you open the floorplanner. IIRC, the >>>quad flatpacks have pin one on the top edge. The best way to make sure >>>you get it right is to open the floorplanner for the chip and package you >>>are using and look at the pin numbers - they are printed on the floorplan >>>screen. This is also how you figure out which pins align with which >>>rows/columns. >> >>I recently had to go through this very exercise. Does anyone know why >>this essential information isn't stated explicitly in the data book? >> >This essential data belongs in the data book, and has been requested over >and over for at least the last 10 years. [snip] There was a thread several months ago about why metastability figures didn't appear in the datasheets (*). Someone from Xilinx (IIRC) said that they didn't get requests for that information, so it didn't go in. (*) there is an app note, but it never seems to have the data for the current generation of parts (which are the ones the designers need the specs for, 'cause they're the parts that are going into new designs). Peter Alfke has contacted me via private email, which proves that they do listen. I will take the time to tell him exactly how I would like the chip orientation information to appear in the datasheets. BTW, I actually find the Xilinx documentation pretty good. (Look on the bright side: it could be a lot worse. I recently had a problem with the documentation for a newish microprocessor from company 'M'. Something about the description of the reset sequence in the datasheet didn't seem right. When I contacted them, I was told that most of the section I was worried about was completely wrong, and should be disregarded! This still hasn't appeared in the errata list and if I hadn't contacted them, I'd never know that the datasheet was wrong.) Regards, Allan.Article: 18422
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platforms. If you are comfortable with test benches or
TextIO, this is the tool for you....
Article: 18423Does your application really need floating point? If it does, how much of the design really needs to be floating point. For example, it is often useful to separate off the exponent early in the chain, work the significand with fixed point arithmetic and then renormalize, adjusting the exponent at the back end. If you can do that, it saves a ton of hardware and usually reduces the truncation noise of floating point designs as implemented on microprocessors. The easiest way to synthesize (that I know of anyway) floating point is to separately treat the exponent and significand as fixed point values, pretty much as I described above. The degree the two pipelines talk to each other determines how much 'floating point' hardware you have. If you break the stuff down into components, you can keep it an RTL level, but your performance is likely to suffer unless you do soe floorplanning and perhaps some optimization for the placement of the registers to force a favorable partitioning of the logic among the LUTs. If this is a one-up design, then I'd do it at what I've been calling pipeline level RTL (in other words be explicit as to what logic lies between each register and call out each register in the design) so that you wind up with a synthesized pipeline that is optimum for the device. Then use the floorplanner to place the pieces manually. That way there is no level structural instantiation. If it is a piece that is to be replicated many times or is a macro, then spend the extra time structurally building the small pieces so you can RLOC them in place. See the recent posts by myself and Brian Davis on placement from within VDHL (hopefully you are using synplicity). One last thing, if you do the small pieces so that they are scalable, then you'll only have to do them once. The upper levels in the hierarchy, for the most part at least, should look pretty much the same whether you are doing the design structurally or at a pipeline RTL level - with the exception of the RLOC attributes you'll be adding for placement. peter dudley wrote: > Hello > > I have a signal processing application that requires a large amount of > floating point arithmetic inside a Xilinx Virtex FPGA. Because the function > is rather algorithmic and will require many configurations I want to design > at a very high level. > > Does anyone know a convenient way to synthesize single precision floating > point multiplications and additions in VHDL? Through my customer I have > access to a tool called Cossap from synopsys. Would that tool help? > > I have hand crafted a VHDL multiplier for the Virtex architecture that runs > at 50MHz with two pipeline registers and two of these will fit into an > XCV50. Instantiating these structurally seems awkward for the scale of > design work we need to do. > > Thanks in advance for any ideas. > > Peter Dudley > Arroyo Grande Systems Incorporated > > Signal Processing in Hardware and Software -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18424
Khaled BENKRID wrote: > Hi all, > > I am using Foundation 1.5i software service pack #2. I am > getting the following Map error for some of my big designs: > " > FATAL_ERROR:basnc:basncbel.c:142:0.0 - NC_BEL name > > <your_instance> is too long Process will terminate. > Please > call Xilinx support. > " > > I had a look at Xilinx data base but did not find a similar case, sent a > query to Xilinx help, & still waiting! Has anybody experienced such a > problem? > > Please help! > > Cheers. I think this doesn't have to do with Xilinx' tool. It seems to be the instance naming of the synthesizer. Your syntesizer has tried to create a name for that instance and because of "divergence" or something like that, it ended up with the name above. Please check out the logic/module/entity in which this instance has been used. You can find it in your schematic editor. Open your gate-level view of your chip and find this instance. With a very little schematic or HDL change you might be able to fix this problem. We faced the same problem, but we found that the problem came from the synthesizer. Xilinx tools do not change the name of the instances. Utku -- I feel better than James Brown.
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