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Threads Starting Jul 1997
6824: 97/07/01: Austin Franklin: Xilinx CPLD Tool Flow....
6852: 97/07/02: Austin Franklin: Re: Xilinx CPLD Tool Flow....
6826: 97/07/01: Koenraad Schelfhout VH14 8993: Which Xilinx devices of the 40xxE, 40xxEX series available ?
6858: 97/07/02: Steven K. Knapp: Re: Which Xilinx devices of the 40xxE, 40xxEX series available ?
6828: 97/07/01: Austin Franklin: Does the Xilinx Xchecker work with NT 4.0?
6839: 97/07/01: Austin Franklin: Re: Does the Xilinx Xchecker work with NT 4.0?
6829: 97/07/01: Christian Ciressan: FPGA -> NLP question !
6830: 97/07/01: Christian Ciressan: FPGA ->NLP question !
6831: 97/07/01: RCSTWKS: Fast Turbo-Fault Simulator
6833: 97/07/01: Neal Becker: Altera archiving
6842: 97/07/02: Daniel K. Elftmann: Re: Altera archiving
6875: 97/07/04: Monnerie: Re: Altera archiving
6877: 97/07/05: <spp@bob.eecs.berkeley.edu>: Re: Altera archiving
6893: 97/07/07: Mark Adams: Re: Altera archiving
6836: 97/07/02: Roger: Re: HackÉA°o¤X?
6837: 97/07/02: Roger: Re: HackÉA°o¤X?
6841: 97/07/02: Joe Chan - ³¯ Ä~ ¯ª: Re: HackÉA°o¤X?
6838: 97/07/01: D.F. Spencer: inexpensive Xilinx 3042A development
6849: 97/07/02: Arnold Columbo: Re: inexpensive Xilinx 3042A development
6857: 97/07/02: Steven K. Knapp: Re: inexpensive Xilinx 3042A development
6840: 97/07/01: Richard Schwarz: BEST FPGA/EDA INFORMATION SITE
6847: 97/07/02: Dmitry Cherniavsky: Does FAQ for this group exist? (empty)
6856: 97/07/02: Steven K. Knapp: Re: Does FAQ for this group exist? (empty)
6868: 97/07/04: Austin Franklin: Re: Does FAQ for this group exist? (empty)
6895: 97/07/07: Ray Andraka: Re: Does FAQ for this group exist? (empty)
6848: 97/07/02: john oatis: Free 5 Page Commercial Web Site
6850: 97/07/02: <ulkjhlk@poikj.com>: !800 SERVICE AT 7.9 CENTS PER MINUTE!!!!!!
6853: 97/07/02: Brad Kelley: Anyone use Altera Flex6000 yet?
6855: 97/07/02: Richard Schwarz: FREE EDA Newsletter
6859: 97/07/02: Karl Kristianson: FS: CADKEY '97 (8.0)-100+ Available- Save $700.00 EACH!!!
6861: 97/07/03: muzo: Altera MaxPlus2 verilog HIERARCHICAL writer ?
6864: 97/07/03: Scott Guest BNR: Re: Altera MaxPlus2 verilog HIERARCHICAL writer ?
6863: 97/07/03: <aps@associatedpro.com>: FREE Q2 EDA NEWSLETTER RELEASED
6867: 97/07/04: <Information>: Metrics
6871: 97/07/04: Mark Sandstrom: How to describe XC4000EX/XL FIFOs/RAMs in VHDL?
6873: 97/07/04: Steven K. Knapp: Re: How to describe XC4000EX/XL FIFOs/RAMs in VHDL?
6880: 97/07/05: Arrigo Benedetti: Re: How to describe XC4000EX/XL FIFOs/RAMs in VHDL?
6878: 97/07/05: Mike Saunders: Quicklogic PASIC1 to PASIC2 problems?
6888: 97/07/06: Steven K. Knapp: Re: Quicklogic PASIC1 to PASIC2 problems?
6883: 97/07/06: Sarah Marsden: free report
6886: 97/07/06: <wteturttyjr@kjptppwthy.com>: Your ONENUMBER for everything!!!
6887: 97/07/06: <dre32d@msn.com>: sell/your/photos$$$$$
6890: 97/07/06: Wenyi - Feng: test
6891: 97/07/06: <Mavin>: Metrics
6894: 97/07/07: Damn Yankee: !!!Hello!!!
6896: 97/07/07: Catherine Dezan: Two days courses on XC6200 - First in FRANCE (BREST)
6897: 97/07/07: Wesley Webb: VHDL to EDIF translater
6904: 97/07/08: Richard B. Katz: Re: VHDL to EDIF translater
6919: 97/07/09: Marcum N. Nance III: Re: VHDL to EDIF translater
6898: 97/07/07: <john@axt.com>: Who was Spamming Who
6900: 97/07/07: Sean Cundiff: D Algorithm
6901: 97/07/07: Richard Schwarz: Re: Vhdl synthesis tools for PC
6907: 97/07/08: Piet du Toit: Xilinx Prom Generation Problem
6932: 97/07/10: Philip Freidin: Re: Xilinx Prom Generation Problem
6936: 97/07/10: Hal Murray: Re: Xilinx Prom Generation Problem
6943: 97/07/12: Peter: Re: Xilinx Prom Generation Problem
6947: 97/07/13: Philip Freidin: Re: Xilinx Prom Generation Problem
6962: 97/07/16: Peter: Re: Xilinx Prom Generation Problem
7029: 97/07/24: Peter Alfke: Re: Xilinx Prom Generation Problem
6908: 97/07/08: Kris Jacobs: Try Me!
6909: 97/07/08: Joseph H Allen: xilinx pci question...
6910: 97/07/08: Sandip Dasgupta: SPICE tutorial
6913: 97/07/08: Damn Yankee: I Am Very Sorry!!!
6915: 97/07/08: Stephane BRETTE: Vhdl synthesis tools for PC
6924: 97/07/09: Juerg Haefliger: FIFO in XC4000
6925: 97/07/09: Pete Burch: Altera FLEX10K initialization
6942: 97/07/12: Steve Dewey: Re: Altera FLEX10K initialization
6952: 97/07/15: Julian Cox: Re: Altera FLEX10K initialization
6926: 97/07/09: David Pashley: ANNOUNCE: Free seminars on language-based FPGA design (UK)
6931: 97/07/10: Georg Diebel: Simulating large VHDL design (FPGA backannotated)
7094: 97/07/31: Thomas Berndt: Re: Simulating large VHDL design (FPGA backannotated)
7133: 97/08/04: Ramesh Narayanaswamy: Re: Simulating large VHDL design (FPGA backannotated)
6935: 97/07/10: <randy97>: http://www.love.com
6938: 97/07/11: Navneet S Yadav: VHDL Synthesis in Xilinx Foundation Series
6939: 97/07/11: Georg Diebel: Re: VHDL Synthesis in Xilinx Foundation Series
7005: 97/07/22: A.C.Rochat: Re: VHDL Synthesis in Xilinx Foundation Series
7014: 97/07/22: Richard Schwarz: Re: VHDL Synthesis in Xilinx Foundation Series
7090: 97/07/30: A.C.Rochat: Re: VHDL Synthesis in Xilinx Foundation Series
7099: 97/07/31: Richard Schwarz: Re: VHDL Synthesis in Xilinx Foundation Series
7020: 97/07/23: George Noten: Re: VHDL Synthesis in Xilinx Foundation Series
6944: 97/07/13: <a19@a.a>: $$$$ NEW SYSTEM, BETTER THAN "ADD ME TO YOUR MAILING LIST" $$$
6945: 97/07/13: <a12@a.a>: $$$$ LOAN BUSINESS, EASY MONTHLY INCOME, NO BRAINER $$$$
6948: 97/07/14: Wade D. Peterson: Best FPGA language for portability
6950: 97/07/14: Rune Baeverrud: Re: Best FPGA language for portability
6953: 97/07/15: Utku Ozcan: UTOPIA?
6960: 97/07/16: David Chhoeun: Re: UTOPIA?
6954: 97/07/15: <richard_steinman@cmagroup.com>: Job; Senior Engineer; Altera; FPGA; High Speed Digital
6955: 97/07/15: Tom Burgess: Bus termination - cool parts & app. notes
6956: 97/07/15: Peter Welten: Selection Criteria for CPLD's/FPGA's
6958: 97/07/16: Philip Freidin: Re: Selection Criteria for CPLD's/FPGA's
6959: 97/07/16: Brian Dipert: Re: Selection Criteria for CPLD's/FPGA's
6961: 97/07/16: L. Kumpa: Re: Selection Criteria for CPLD's/FPGA's
6971: 97/07/17: Brian Dipert: Re: Selection Criteria for CPLD's/FPGA's
6957: 97/07/16: <18734757@compuserve.com>: GET FREE 2100 $ex-Web $Sites FREE! @?
6963: 97/07/16: <98776555554453@compuserve.com>: FREE...Don't Pay For $ex $site Pa$$words,
6964: 97/07/16: Arrigo Benedetti: Problem simulating 3-state output with M1 and Synopsys
7078: 97/07/29: Martin Vorbach: Re: Problem simulating 3-state output with M1 and Synopsys
7095: 97/07/31: Thomas Berndt: Re: Problem simulating 3-state output with M1 and Synopsys
6965: 97/07/17: <gary099g@erols.com>: FREE SEX SITE..password is.
6966: 97/07/17: <188d77@compuserve.com>: Get FREE PASSWORD TO 2000 SEX SITEs
6967: 97/07/17: Alexander Taubin: CALL FOR PAPERS (CSD'98)
6968: 97/07/17: Herbert Kleebauer: free FPGA software from actel
6969: 97/07/17: Herbert Kleebauer: free FPGA software from actel
6985: 97/07/19: L. Kumpa: Re: free FPGA software from actel
7025: 97/07/24: Nic: Re: free FPGA software from actel
7067: 97/07/28: Nico Coesel: Re: free FPGA software from actel
7168: 97/08/08: David R Brooks: Re: free FPGA software from actel
7170: 97/08/09: Ian Stirling: Re: free FPGA software from actel
7173: 97/08/10: Richard Steven Walz: Re: free FPGA software from actel
7180: 97/08/11: <dstewart@dmicros.com>: Re: free FPGA software from actel
7197: 97/08/13: Richard Steven Walz: Re: free FPGA software from actel
7199: 97/08/13: David R Brooks: Low-cost programming FPGAs (was: Re: free FPGA software from actel)
7202: 97/08/14: Richard Schwarz: Re: Low-cost programming FPGAs (was: Re: free FPGA software from actel)
7204: 97/08/14: Alex Lait: Re: Low-cost programming FPGAs (was: Re: free FPGA software from actel)
7219: 97/08/15: Mark Aaldering: Re: Low-cost programming FPGAs (was: Re: free FPGA software from actel)
7239: 97/08/18: Andreas Kugel: Re: Low-cost programming FPGAs (was: Re: free FPGA software from actel)
7214: 97/08/15: Steven K. Knapp: Re: Low-cost programming FPGAs (was: Re: free FPGA software from actel)
7203: 97/08/14: Richard Schwarz: Re: free FPGA software from actel
7221: 97/08/15: <timolmst@nospam.cyberramp.net>: Re: free FPGA software from actel
7015: 97/07/23: Gerald Coe: Re: free FPGA software from actel
7060: 97/07/28: Sam Falaki: Re: free FPGA software from actel
6970: 97/07/17: Mark Sandstrom: Problem with unexpanded logic in xnf synhesized by Leonardo
6977: 97/07/18: David Storrar: Re: Problem with unexpanded logic in xnf synhesized by Leonardo
6978: 97/07/18: Mark Sandstrom: Re: Problem with unexpanded logic in xnf synhesized by Leonardo
6984: 97/07/18: Ruth Mayeda: Re: Problem with unexpanded logic in xnf synhesized by Leonardo
6997: 97/07/21: Mark Sandstrom: Re: Problem with unexpanded logic in xnf synhesized by Leonardo
6972: 97/07/17: Martin Vorbach: Exists a special measurement newgroup?
6973: 97/07/17: Martin Vorbach: How is the ALTERA 10K100 IO-Pin state before (!) configuration (I
6974: 97/07/18: Man`y: looking for a contract opening
6975: 97/07/17: Matt Hosler: request for Xilinx 6200 FPGA mappings
6976: 97/07/17: Richard Schwarz: Re: FPGA design tools
6979: 97/07/18: Gianpaolo Scassellati: Clock generator
6988: 97/07/19: Symon Brewer: Re: Clock generator
6989: 97/07/19: Symon Brewer: Re: Clock generator
7008: 97/07/22: Andre Powell: Re: Clock generator
6980: 97/07/18: Klaus Falser: Production testing of Design with CPLD's
7001: 97/07/21: Kayvon Irani: Re: Production testing of Design with CPLD's
7018: 97/07/23: Tim Forcer: Re: Production testing of Design with CPLD's
6982: 97/07/18: Kim Hofmans: Xabel mapping into xilinx
6983: 97/07/18: Reetinder P. S. Sidhu: FPGA design tools
6986: 97/07/19: <timolmst@cyberramp.net>: Re: FPGA design tools
6993: 97/07/20: Martin Vorbach: Re: FPGA design tools
7035: 97/07/25: Tim Warland: Re: FPGA design tools
6987: 97/07/19: Zoltan Kocsi: Survey
6990: 97/07/20: Ron N. Boissoneault: fpga
6991: 97/07/20: Alfred Bos: Larger designs with Lattice fitter ???
6992: 97/07/20: Marcin Czeczko: GAL Programmer
6994: 97/07/20: Malcolm Bugler: AM186 to P/C104 PLD design
6995: 97/07/21: Joseph H Allen: PCI burst transfers
6996: 97/07/21: Bruno Sauter: Re: PCI burst transfers
6998: 97/07/21: Duane Clark: Re: PCI burst transfers
6999: 97/07/21: Dave Dea: Re: PCI burst transfers
7000: 97/07/21: Wen-King Su: Re: PCI burst transfers
7002: 97/07/22: Joseph H Allen: Re: PCI burst transfers
7004: 97/07/22: Wen-King Su: Re: PCI burst transfers
7010: 97/07/22: Austin Franklin: Re: PCI burst transfers
7007: 97/07/22: Peter: Re: PCI burst transfers
7011: 97/07/22: Wen-King Su: Re: PCI burst transfers
7044: 97/07/26: John Eaton: Re: PCI burst transfers
7046: 97/07/26: Wen-King Su: Re: PCI burst transfers
7049: 97/07/27: Paul DeMone: Re: PCI burst transfers
7056: 97/07/28: Peter: Re: PCI burst transfers
7080: 97/07/29: Hydrochloric Asad: Re: PCI burst transfers
7087: 97/07/30: Austin Franklin: Re: PCI burst transfers
7103: 97/07/31: Peter: Re: PCI burst transfers
7104: 97/07/31: Tim Warland: Re: PCI burst transfers
7117: 97/08/01: Peter: Re: PCI burst transfers
7129: 97/08/04: Joseph H Allen: Re: PCI burst transfers
7131: 97/08/04: Peter: Re: PCI burst transfers
7106: 97/07/31: Paul DeMone: Re: PCI burst transfers
7145: 97/08/06: Austin Franklin: Re: PCI burst transfers
7012: 97/07/22: George Herbert: Re: PCI burst transfers
7013: 97/07/22: George Herbert: Re: PCI burst transfers
7017: 97/07/23: Peter: Re: PCI burst transfers
7009: 97/07/22: Austin Franklin: Re: PCI burst transfers
7003: 97/07/22: Casper K. Chen: Altera and Synopsys
7006: 97/07/22: Stephen D. Scott: tech. report available
7016: 97/07/23: Mike Kelly: Epitaxial Layer on EPLD
7041: 97/07/26: Richard B. Katz: Re: Epitaxial Layer on EPLD
7019: 97/07/23: Peter: Should Xiling have more local clock nets?
7037: 97/07/25: Tom Burgess: Re: Should Xiling have more local clock nets?
7055: 97/07/28: Tim Warland: Re: Should Xiling have more local clock nets?
7062: 97/07/28: Tom Burgess: Re: Should Xiling have more local clock nets?
7064: 97/07/28: Don Husby: Re: Should Xiling have more local clock nets?
7084: 97/07/30: Peter: Re: Should Xiling have more local clock nets?
7040: 97/07/25: Stuart Clubb: Re: Should Xiling have more local clock nets?
7042: 97/07/26: Peter: Re: Should Xiling have more local clock nets?
7051: 97/07/27: Stuart Clubb: Re: Should Xiling have more local clock nets?
7057: 97/07/28: Peter: Re: Should Xiling have more local clock nets?
7066: 97/07/28: Stuart Clubb: Re: Should Xiling have more local clock nets?
7085: 97/07/30: Peter: Re: Should Xiling have more local clock nets?
7198: 97/08/13: Steve Lass: Re: Should Xiling have more local clock nets?
7233: 97/08/17: Stuart Clubb: Re: Should Xiling have more local clock nets?
7250: 97/08/18: Steve Lass: Re: Should Xiling have more local clock nets?
7021: 97/07/23: Peter Welten: Why fast message delete in this group?
7022: 97/07/23: Peter Alfke: Re: Why fast message delete in this group?
7026: 97/07/24: Austin Franklin: Re: Why fast message delete in this group?
7023: 97/07/24: Philip Freidin: Re: Why fast message delete in this group?
7024: 97/07/24: Tim Forcer: Re: Why fast message delete in this group?
7030: 97/07/25: TM: Re: Why fast message delete in this group?
7053: 97/07/27: Nic: Re: Why fast message delete in this group? - date format "flame"
7054: 97/07/28: Tim Forcer: Re: Dates (was: fast delete)
7027: 97/07/24: Robert M. Münch: How do FPGAs outperform DSP at FFT?
7031: 97/07/25: Jeff Millar: Re: How do FPGAs outperform DSP at FFT?
7032: 97/07/24: Kayvon Irani: Re: How do FPGAs outperform DSP at FFT?
7047: 97/07/27: Robert M. Münch: How do FPGAs outperform DSP at FFT?
7033: 97/07/25: Philip Freidin: Re: How do FPGAs outperform DSP at FFT?
7050: 97/07/27: Stuart Clubb: Re: How do FPGAs outperform DSP at FFT?
7034: 97/07/25: Kardos, Botond: Re: How do FPGAs outperform DSP at FFT?
7048: 97/07/27: Robert M. Münch: How do FPGAs outperform DSP at FFT?
7028: 97/07/24: Jeffrey R. White: real-life Aptix experiences
7036: 97/07/25: John Schewel: Hardware/Software Co-Design
7038: 97/07/25: Linda Boyd: Qualis VHDL Training
7039: 97/07/25: Linda Boyd: Qualis Verilog Training
7043: 97/07/26: Reetinder P. S. Sidhu: FPGA die photograph
7045: 97/07/26: Philip Freidin: Re: FPGA die photograph
7052: 97/07/27: Peter Alfke: Re: FPGA die photograph
7077: 97/07/29: Martin Vorbach: Re: FPGA die photograph
7058: 97/07/28: Executive Search: San Diego/Santa Clara/Boston--MTS-FPGA Field Applications Engineer-Recruiter
7059: 97/07/28: Mauro Olivieri: information on RIPP10
7083: 97/07/30: Stephen Smith: Re: information on RIPP10
7061: 97/07/28: Sam Falaki: Design Protection in FPGAs
7070: 97/07/29: Philip Freidin: Re: Design Protection in FPGAs
7091: 97/07/30: Wade D. Peterson: Re: Design Protection in FPGAs
7101: 97/07/31: Philip Freidin: Re: Design Protection in FPGAs
7072: 97/07/29: Rich K.: Re: Design Protection in FPGAs
7075: 97/07/29: Henry Spencer: Re: Design Protection in FPGAs
7082: 97/07/30: Wade D. Peterson: Re: Design Protection in FPGAs
7063: 97/07/28: Executive Search: San Diego/Santa Clara/Boston--MTS-FPGA Field Applications Engineer-Recruiter
7068: 97/07/29: Philip Freidin: Re: San Diego/Santa Clara/Boston--MTS-FPGA Field Applications Engineer-Recruiter
7139: 97/08/05: Bob Walance: Re: San Diego/Santa Clara/Boston--MTS-FPGA Field Applications Engineer-Recruiter
7065: 97/07/28: Muhammad Hamid: Giga Ops g900 board
7069: 97/07/29: <@ihr.mrc.ac.uk>: MEM_CS16 timing on ISA BUS
7073: 97/07/29: Austin Franklin: Re: MEM_CS16 timing on ISA BUS
7107: 97/08/01: bob elkind: Re: MEM_CS16 timing on ISA BUS
7143: 97/08/06: Tim: Re: MEM_CS16 timing on ISA BUS
7144: 97/08/06: bob elkind: Re: MEM_CS16 timing on ISA BUS
7148: 97/08/07: Terry Harris: Re: MEM_CS16 timing on ISA BUS
7071: 97/07/29: John Chambers: MEM_CS16 TIMING (repeat)
7074: 97/07/29: Jackie Meyer: Memory workshop
7076: 97/07/29: Martin Vorbach: ASIC NRE costs, how are they calculated, which values are typical
7079: 97/07/29: <davewang@wam.umd.edu.delete.after.edu>: Quick prototyping? Best solution?
7081: 97/07/29: Tom Burgess: Re: Quick prototyping? Best solution?
7100: 97/07/31: Richard Schwarz: Re: Quick prototyping? Best solution?
7089: 97/07/30: John Chambers: Re: Quick prototyping? Best solution?
7098: 97/07/31: J. Mejia: Re: Quick prototyping? Best solution?
7102: 97/07/31: Philip Freidin: Re: Quick prototyping? Best solution?
7086: 97/07/30: Alexandr Solovkin: Where is Actel's www?
7088: 97/07/30: Adam J. Elbirt: Re: Where is Actel's www?
7109: 97/08/01: J. Mejia: Re: Where is Actel's www?
7092: 97/07/30: Contact Lenses: Contact Lenses for Internet users
7093: 97/07/31: Richard B. Katz: digitizer design, high speed
7105: 97/07/31: John Wettroth: Re: digitizer design, high speed
7132: 97/08/04: A William Sloman: Re: digitizer design, high speed
7151: 97/08/07: Julian Cox: Re: digitizer design, high speed
7157: 97/08/07: Rich K.: Re: digitizer design, high speed
7096: 97/07/30: Dan: Make extra cash..it works.
7097: 97/07/31: Thomas Berndt: Download FLEX10K over the LPT port
7116: 97/08/01: Jeffrey C. Marden: Re: Download FLEX10K over the LPT port
7161: 97/08/07: Yun Feng: Re: Download FLEX10K over the LPT port
7176: 97/08/11: no@spam no@spam J.Szamosfalvi: Re: Download FLEX10K over the LPT port
7194: 97/08/13: Steve Wiseman: Re: Download FLEX10K over the LPT port
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
