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Tom Burgess wrote: > David T. Wang wrote: > > > > Hi all. > > > > I am working on a project using Actel 1280 FPGA's. However, This > FPGA > > would eventually be used to control another piece of ASIC, whose > > performance characteristic is not entirely clear to us. (Custom > ASIC, > > no manufacturer to provide fancy manual, we figure it out) So We'd > > like to do some prototyping. Which involve the following set of > > tasks. > > > > 1. provide an init sequence/string to the ASIC. > > > > 2. provide a regular alternating set of signals to the ASIC. > > > > 3. upon triggering, te ASIC would provide a trigger, the FPGA would > > stop the alternating set of signals, and go into the third > sequence > > of signals to digitize some analog signals, and then serially > clock > > out the data. The serial data then has to be converted to > paralle, > > and decoded (it's in gray code) > > > > An approach I have seen used for flexible CCD imager control is to > keep the control logic relatively simple and to use a downloadable > RAM as a high speed arbitrary pattern generator. That way you can > just edit the pattern to change the timing and don't need to recompile > > a bunch of logic every time. Don't recall the reference, but could > look > it up if you want. > > regards, tom (tburgess@drao.nrc.ca) I use our X84 FPGA PC board all the time to provide stimulus and test vector to our other products we develop. It has access to the PC ISA bus via an 8255 and has sockets on board to allow different oscillators to be used as inputs. I have used it recently to check out and generate an Intelsat Reed Solomon FEC implementation. It was used to generate the concatenated FEC in both serial and parallel formats. It's low cost and high flexibility make it ideal for just such testing. You can purchase the board with or with out XILINX development software. see http://www.associatedpro.com/aps/x84.html -- ---------------------------------------------------------------- Richard Schwarz, President Associated Professional Systems (APS) EDA and Communications Tools http://www.associatedpro.com richard@associatedpro.com 410.569.5897 fx:410.661.2760Article: 7101
In article <5ro485$ft8@epx.cis.umn.edu> peter299@maroon.tc.umn.edu writes: >fliptron@netcom.com (Philip Freidin) wrote: > >> The same also applies to trying to reverse >> engineer an SRAM FPGA bitstream. To my knowledge, this has only been >> done successfully once, by a very motivated company, and the intent was >> not to ripoff an end user's design, but rather to create competitive >> CAE software. > >I've never tried it, but I would think it would be fairly easy to >break SRAM code. XILINX and guys like that claim that it's >impossible, but if you think about it, it should be that hard. (I assume you intended the word to be "shouldn't") Xilinx does not claim that it is impossible. If you discuss it with people at Xilinx who know how this stuff works (as opposed to people at Xilinx who are just guessing) they will tell you that it is very hard to do. As I wrote above, to my knowledge, this has only ever been done once (in 13 years of Xilinx's existance), and the guy that did it has said that it was non-trivial. Certainly some of the bits are easy to decode, such as the bits that make up the function generators, but there are far more bits in the interconnect and I/O area, as well as diagnostic, mode, config control, and other functions that even with the schematics of the FPGA itself in front of you, are tough to figure out. >For example, if you took some design tools for a XC400X device, and >(a) programmed only one interconnect at a time and (b) looked at the >resulting bitstream, I think you should be able to break their code. The reason this simple approach fails is that there are many things in the interconnect that are NOT independent one-to-one mappings between the user view of a design, and the bitstream. This is why the bitstream is a fairly secure representation of a design (which I seem to remember was the thread topic). >This could be repeated until a total picture of the bitstream results. >Furthermore, there's probably pattern to the bit patterns. I would >think you should be able to find the pattern in a few days of work. > > >>4) The highest security is with SRAM FPGAs that have a power-down/battery >> backed up mode of operation (such as the XC3000L products). With these >> devices, the bitstream is loaded into the device during manufacturing, >> and a battery maintains the configuration data in the device, even when >> the system is turned off. Unless you want to have a big battery, you >> need an FPGA that can maintain its data in a power down mode with very >> little power. The XC3000L parts can do this as low as 5uA, which is >> down at the battery's own leakage current, and with appropriate >> batteries, could give an operation life of 5 to 10 years. > >I don't really care for this from a manufacturing standpoint. Any >glitch (caused by a fat probe, etc.) on the power rail would render >the product useless, as the FPGA would forget it's program and >couldn't be reset in the field. >Wade D. Peterson | TEL: 612.722.3815 The initent of implementing this level of security is to specifically make the bitstream go away if someone tries to get at it. Obviously if you want this level of security, then it is also your responsibility to create a robust backup power system to maintain the bitstream, as well as having a plan for when a system in the field looses it mind. I.E. identify whether or not someone was trying to break into the design, etc. There ARE companies that are in industries that are so competative (and maybe all participants are not of stellar moral ethics) that have chosen to use this type of security. The arcade machine business is such an example. Other examples include companies that prefer to use trade secrets rather than patents to protect their intellectual investments, and of course military/crypto applications, including cable descrambler boxes. Philip FreidinArticle: 7102
Look out folks, Phil's got a product now, and he has counted up how many articles others have posted that repetatively advertise a company's product at every possible chance, even if the thread is unrelated, so it's time for catch up :-) Complaints by email will be considered. Yes the following article is from the same guy that recently mini-flamed a head hunter in this news group for in-appropriate postings. In article <5rl7em$nf7$1@hecate.umd.edu> davewang@wam.umd.edu.delete.after.edu@Glue.umd.edu (David T. Wang) writes: >Hi all. >I am working on a project using Actel 1280 FPGA's. However, This FPGA >would eventually be used to control another piece of ASIC, whose >performance characteristic is not entirely clear to us. (Custom ASIC, >no manufacturer to provide fancy manual, we figure it out) So We'd >like to do some prototyping. Which involve the following set of tasks. > >1. provide an init sequence/string to the ASIC. > >2. provide a regular alternating set of signals to the ASIC. > >3. upon triggering, te ASIC would provide a trigger, the FPGA would > stop the alternating set of signals, and go into the third sequence > of signals to digitize some analog signals, and then serially clock > out the data. The serial data then has to be converted to paralle, > and decoded (it's in gray code) > >I had though about going ahead and use the Actel to do this, except that >since the exact performance characterisitic of the custom ASIC isn't >known, we'd like to fiddle with the sequence, and timing of the signals. >And as we all know, the Actel isn't too amiable to being reprogrammed :) >I also thought about using something like GAL's, since I know I can get >basically free tools to program them, and the language isn't too >terribly difficult to pick up. However, GAL's are too small for my purpose >in this case. What FPGA/PLD's would be best for my purpose of generating >about 14 control signals, probably requiring about 50 to 100 FF's for latching >in various signals, and generate the control state machine. It should be >easily reprogrammable, and the programming language should be simple to pick >up. (I do know VHDL). The programming software should be inexpensive. >(prefer free), and I need to develope this piece of hardware in a giffy. I have a product that is probably architecturally what you need, is available now, but it isn't free, and the customization requires the use of development software that isn't free either (but your .edu organization may already have a copy) The product is a general purpose prototyping board that includes a Xilinx 4025E or 4028EX, a big wire wrap area, ISA bus interface, and SRAM and DRAM for either stimulus or capture. It was recently used for one of my clients specifically for testing an ASIC, and the results were very good. Some standard application designs are available for the board (in which case you may not need to do your own), that include up to 90 user controllable I/O signals that can be accessed by the test program runnin on your host system. the rest of the I/O on the FPGA are talking to the ISA bus, or the SRAM/DRAM. email me if you can get over the fact that the product isn't free. Philip Freidin fliptron@netcom.comArticle: 7103
Here in the UK, firms (e.g. Orbit) advertise a zero-NRE conversion from a Xilinx netlist. Practically of course they inflate the price a bit to do this, and the normal NRE is about $8k. Still very good, for as little as 1k chips. I looked into these firms in detail about 1 year ago, but eventually went to an analog+digital design which they could not do. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 7104
Austin Franklin wrote: > > > I redid a 8000 gate FPGA built in a 0.6 um process with a 10,000 gate > gate array (I > > added a few extra functions) in a nearly obsolete two metal 1.0 um > process. > > The gate array was about 25% the cost... > > ... and the gate array NRE plus my time was paid for after selling less > > than a 100 units. > > A Xilinx 4010 cost is about $70, and your ASIC was %25 or $17.50 (which is > about the right price, may be even a little high, for a 10k ASIC in 1um). > Therefore savings were $5250 with these numbers. At $75/hour for > engineering time, that is 70 hours. Say it took you 20 hours for your time > (which would be quite a low estimate), leaving $3750 for NRE. Also, most > ASIC houses won't make an ASIC without a minimum number P.O., say a few > thousand... <snip> Yeah, but... the analysis fails to consider the NRE incurred in developing the FPGA. While people who only design FPGAs may see this as trivial, the ASIC people have to go back to the source code, tweak it for speed, replace RAM/ROMs, re synthesize, then through the M1 tool, and back for simulation to prove it meets spec. For a 4010, you could do the spin in a day IFF you knew what you were doing, and the simulation passes (like that ever happens first go). If the original designer did the device in an FPGA instead of an ASIC, he would still incure NRE. Tim. -- You better be doing something so that in the future you can look back on "the good old days" My opinions != Nortel's opinion; Nortel's Hardware :-)Article: 7105
Richard B. Katz wrote: > > hi, > > as part of a space flight instrument, a high speed digitizer is required. > here's a brief specification. > > 1. sample rate >= 1 gigasample/second, 8-bit resolution; > 1.6 > Gigasample/second desired. > 2. input bandwith >= 250 MHz > 3. memory depth >= 32,000 samples; > 64,000 samples desired. > 4. 100 MHz clock input, PLL to increase speed as needed > 5. 80 Hz rate. > 6. power <= 25 watts. > 7. prefer mcm packaging > 8. design life >= 8 years, 5 years on-orbit. > > we welcome any ideas that you may have. also, if you have experience in > this area, like a good challenge, and would like to be considered for this > assignment, please contact me (info at the bottom). > > one concept we're exploring is to use, for example, the 1 GSample/second > SPT ADC and RAMBUS DRAMS. This can give us a huge memory (and cheap > redundancy) and is a bonus for the system design. for this, obviously, we > would like a high-speed asic to provide the connection between the ADC (500 > MHz w/ the 1:2 on-chip demux) and the RDRAMs for acquisition and system > logic for readout (which is relatively slow). spt adc and RDRAMS have > already passed preliminary radiation tests and are currently undergoing > construction analysis. > > other concepts are being explored and feel free to come with a clean sheet > of paper. > > you may contact me at: > > Rich Katz > NASA/GSFC > Code 738 > Greenbelt, MD 20771 > > Tel: (301) 286-9705 > Fax: (301) 286-0220 > email: rich.katz@gsfc.nasa.gov Maxim makes these types of ADC- 8 bits and 1Gs/sec (See MAX101, etc.) Regards JohnArticle: 7106
Austin Franklin wrote: [snip] > A Xilinx 4010 cost is about $70, and your ASIC was %25 or $17.50 (which is > about the right price, may be even a little high, for a 10k ASIC in 1um). This was several years ago. The ACT1280A ran around C$300. The replacement ASIC in PPGA was around C$70. If you looked at industrial or mil temp the cost difference was even more pronounced. > Therefore savings were $5250 with these numbers. At $75/hour for > engineering time, that is 70 hours. Say it took you 20 hours for your time > (which would be quite a low estimate), leaving $3750 for NRE. Also, most It took a lot longer than that but most of the effort was putting stuff back into the design that was stripped to fit the FPGA. I also simulated the ASIC to death to ensure no spin. When vendor sales rep dropped off samples I was confident enough to demonstrate the frame grabber/video processor card with the FPGA, power it down, pull the FPGA, pop in the ASIC, power it back up and continue the demo (all in front of my manager *phew*) > ASIC houses won't make an ASIC without a minimum number P.O., say a few > thousand... That is a growing problem for system houses with small volumes. It seems like the major ASIC houses all want the "playstation" wins and don't want to deal with small fry any more. > > My experience has shows your NRE to be quite low for a 10k ASIC, unless you > made up the low NRE by ordering a larger quantity of chips, therefore > including part of the NRE in the chip price, instead of up front. My employer at the time actually got a rather good deal on NRE because I had worked for the ASIC vendor previously and knew the tools and procedures inside and out - no hand holding required. Under normal circumstances, the break even point might have been 125 or 150 units instead of <100. > > If you could post your actual numbers (actual NRE, minimum number of chips > you had to order, and at what price, how many hours it took for you to do > this 'conversion') this would make your numbers more 'compelling'. Do you want the bill of materials and customer list as well ? ;-) > > Thanks, > > Austin Franklin > darkroom@ix.netcom.com -- Paul W. DeMone The 801 experiment SPARCed an ARMs race Kanata, Ontario to put more PRECISION and POWER into demone@mosaid.com architectures with MIPSed results but PaulDeMone@EasyInternet.net ALPHA's well that ends well.Article: 7107
John, The MEM_CS16 line has to be yanked as soon as you even *think* that your board *might* be selected. If you wait for a strobe to "validate" the address, you've already waited too long. What has worked well for me is to yank on the MEMCS16 line whenever the address lines point to the memory board. Mo latching, no registering, and no gating. Caveat: this suggestion applies well in my experience with PCI bus systems, where PCI traffic doesn't even appeay on the ISA bus, and the ISA bus is ignored for PCI transfers. Also, in general the only two available (64KB) pages in the lowest 1M of system address space are D000:xxxx and E000:xxxx. It would be well for you to maximise your chances of success by limiting yourself to one of these pages, and not use both. good luck to you... -- Bob @ihr.mrc.ac.uk said... > Any advise on the timing of the MEM_CS16 line of the PC ISA Bus would be > appriciated. I'm trying to design a DSP board with a shared memory > interface to the PC. I want to use 16 bit transfers for the memory but > this seems to affect the video card. I've already assertained that the > address bits of the auxiliary channel need to be used on the decode for > this signal (imposing 16 bit transfers on a 128KB page) but what other > signals need to be incorparated to produce the required decode? I'm > using an open collector pull down transistor and a Lattice 2032 for the > decode logic. Any help or pointers to where I can get help would be > appriciated > > John **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****Article: 7108
Friends and colleagues, I've an application with piles of ISP CPLDs on a board, all connected together via a JTAG chain, awaiting programming. Rather than use the CPLD vendor's HW and SW to program the board in production, I'd like to write a PC-based application to drive the JTAG bus and, effectively, "download" the programming files. After an hour on the web, surfing for supporting docs, I've come up empty. Any pointers on the fine art of driving a JTAG bus, or is this self-evident stuff after reading the IEEE 1149 document? Your help is appreciated! Please remove the .nospam when replying directly via e-mail. -- Bob Elkind **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****Article: 7109
Try http://www.actel.com again. It is still there... Alexandr Solovkin <sol@elvis.ru> wrote in article <5rn23q$m95$1@public.elvis.ru>... > > Hi, FPGA - mans. > I confused I can't to reach Actel www site with > URL: http://www.actel.com. > Who knows Is it problems of my ISP or Actel > changes www site? > > Alex. > ELVIS + Ltd. > > >Article: 7110
Anyone out there programming the Xilinx 4036XL device in a HQ304 package...? I only ask because we've just bought this device and have received the Alliance M1.2 software only to find that the HQ304 package is not supported! According to MicroCall, our Xilinx distributor, the HQ304 package has been accidently left out of not only the M1.2 release, but the M1.3 release as well! Patches will be available soon, apparently! So presumably, no one can actually program this device yet!!?!?! -- Cliff cjbradshaw@dra.hmg.gb "Linux: The Choice of a GNU Generation"Article: 7111
bob elkind wrote: > > Friends and colleagues, > > I've an application with piles of ISP CPLDs on a board, all > connected together via a JTAG chain, awaiting programming. > > Rather than use the CPLD vendor's HW and SW to program the > board in production, I'd like to write a PC-based application > to drive the JTAG bus and, effectively, "download" the > programming files. > > After an hour on the web, surfing for supporting docs, I've > come up empty. > > Any pointers on the fine art of driving a JTAG bus, or is this > self-evident stuff after reading the IEEE 1149 document? > > Your help is appreciated! > > Please remove the .nospam when replying directly via e-mail. > > -- Bob Elkind > > **************************************************************** > Bob Elkind mailto:eteam@aracnet.com > 7118 SW Lee Road part-time fax number:503.357.9001 > Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 > ****** Video processing, R&D, ASIC, FPGA design consulting ***** I too, would like to know how to do this using Altera EPLDs (7000S parts). I did obtain from Altera the authorization to generate the appropriate .SVF files from their .POF files. Altera doesn't seem to have any app notes on how this information is to be used to actually send this file over the JTAG port from a micro. I must not be looking in the right place for the information. Christine Price cprice@telogy.com Member of Technical Staff Telogy Networks, Inc. 20250 Century Blvd. Germantown, MD 20874 V: (301)515-6634 F: (301)515-7687Article: 7112
Qualis Design Corporation has published the Fall schedule for our many
hands-on, application-focused courses in Verilog- and VHDL-based design.
Our courses are like no other -- just take a look at our lineup:
Verilog System Design
---------------------
Introductory:
High Level Design Using Verilog
System Verification Using Verilog
Verilog for Board-Level Design
Elite:
ASIC Synthesis and Verification Strategies Using Verilog
Advanced Techniques Using Verilog
Verilog Synthesis
-----------------
Introductory:
Verilog for Synthesis: A Solid Foundation
Elite:
ASIC Synthesis Strategies Using Verilog
Behavioral Synthesis Strategies Using Verilog
For more info on our suite of HDL classes, to review our Fall schedule,
or if you're interested in an on-site class, check out our web site at
http://www.qualis.com or call Michael Horne on our hotline at 888.644.9700.
Qualis Design Corporation
8705 SW Nimbus Suite 118
Beaverton OR 97008 USA
Ph: +1.503.644.9700 Fax: +1.503.643.1583
http://www.qualis.com
Copyright (c) 1997 Qualis Design Corporation
Article: 7113
Qualis Design Corporation has published the Fall schedule for our many
hands-on, application-focused courses in VHDL- and Verilog-based design.
Our courses are like no other -- just take a look at our lineup:
VHDL System Design
------------------
Introductory:
High Level Design Using VHDL
System Verification Using VHDL
VHDL for Board-Level Design
Elite:
ASIC Synthesis and Verification Strategies Using VHDL
Advanced Techniques Using VHDL
VHDL Synthesis
--------------
Introductory:
VHDL for Synthesis: A Solid Foundation
Elite:
ASIC Synthesis Strategies Using VHDL
Behavioral Synthesis Strategies Using VHDL
For more info on our suite of HDL classes, to review our Fall schedule,
or if you're interested in an on-site class, check out our web site at
http://www.qualis.com or call Michael Horne on our hotline at 888.644.9700.
Qualis Design Corporation
8705 SW Nimbus Suite 118
Beaverton OR 97008 USA
Ph: +1.503.644.9700 Fax: +1.503.643.1583
http://www.qualis.com
Copyright (c) 1997 Qualis Design Corporation
Article: 7114Has anyone else had problems with XILINX changing parts (i.e. programming algorithms), and not noting the change. We have had 3 instances - XC7336, XC7236, and XC95108, where all of the sudden part programming stops working. Lo and behold, we find out we find out we just got a new batch of parts that don't work any more. After consulting XILINX (and them initially claiming nothing has changed), we find out the changed the die and we need a new algorithm (which will take a month or 2 out of DATAIO or another adapter to buy - but that's another story). Just trying to find out if anyone has seen this problem, or if we are jus "Special". Steve Darby Huntsville Microsysems, Inc. http://www.him.com/Article: 7115
Hi guys,
I have an elementary doubt in PCI interfacing.
I want to design a card with a PCI interface.
1. Can I make use of the DMAC of any 486/Pentium machines for data
transfers ? Or do I have to use a DMAC on my card and develop
an arbiter as well ?
2. If I can indeed use the DMAC of the 486/Pentium do I need a
PCI/ISA bridge ? (since I cannot find any signals related to
DMAC on the PCI interface)
3. And how do I get to know which of the channels of the DMAC have
been already used by the system (for eg. for floppy
disks/controllers ) and which are free to be used by a new I/O
device ?
It would be nice if I could get a lead from you guys....
Thanks,
Kuldeep
Article: 7116On 31 Jul 1997 05:15:42 GMT, berndt@eas.iis.fhg.de (Thomas Berndt) wrote: > >Hi, > >does anybody knows how I can download designs which are compiled with MAXPLUS2 >over the LPT port? > >Thanks in forward. > >Thomas > ______________________________________________________________________________ >| | >| Dipl.-Ing. Thomas Berndt Tel: 0351 / 4640-731 | >| email: berndt@eas.iis.fhg.de | >| URL: http://www.eas.iis.fhg.de/sim/staff/berndt| >| FAX: 0351 / 4640-703 | >| | >| Fraunhofer-Institut fuer Integrierte Schaltungen (IIS) | >| EAS Dresden | >| Zeunerstr. 38 | >| 01069 Dresden | >|______________________________________________________________________________| > > Altera makes the ByteBlaster Parallel Download Cable (pn PL-BYTEBLASTER) to do this. It connects to the PC parallel port, and is controlled by Altera's MaxPlus2 Software programmer. ~$150.00 I think. Hope this helps, Jeff Marden GammaGraphX, Inc. jmarden@ggx.comArticle: 7117
This is a very good point. One can spend a lot of time running around IF one did not do one's homework first. I won't mention names, but certain firms who extensively advertise FPGA conversion capability either don't have it, or they have it available only for very limited circumstances. For example, when I did my last FPGA -> ASIC job, I found that the ASIC firm could not accept the Xilinx netlist format (XNF). It is hard to imagine someone advertising "Xilinx FPGA netlist conversion" and not being able to accept XNF. They could only accept a netlist from Cadence or Verilog or whatever (I am not familiar with these $50k+ tools :)) In the end, they wrote a converter for XNF to their in-house netlist format. A day's work. Next, The design has two VCC rails. One for the logic, and one for a real time clock section which obviously needs separate power. Their place/route tools "could only route one power regime at one time". So I now had to split the design into two, and give them two netlists. This was a big job, and the result was never simulated in an FPGA, but the *overall* test vectors (from Viewsim) were still applicable to the whole job, so I relied on that (successfully, as one would expect). Next, they could not accept the Viewsim text vectors. NOW WHAT IS THE POINT in doing a FPGA -> ASIC conversion if the ASIC vendor cannot make use of (at least some) FPGA test vectors. Generating test vectors has always been a highly time consuming part of doing an ASIC, and being able to test the ASIC (certainly the ASIC vendor's simulation database, and ideally also the actual silicon) with those same vectors greatly reduces the risk. In the end, they wrote a test vector converter. Next, their library did not have a D-type with a clock enable. They thought that is the same as a D-type with an AND gate in the clock. This had to be sorted out. The reason we went to this firm was because of their analog capability. We would have never used them for a digital-only design. The sales people for this ASIC firm had seen the whole project up front, and assured us ALL above was fine. Never talk to marketing about details like that, and get it in writing. >Yeah, but... the analysis fails to consider the NRE incurred in >developing the FPGA. While people who only design FPGAs may see this as trivial, >the ASIC people have to go back to the source code, tweak it for speed, >replace RAM/ROMs, re synthesize, then through the M1 tool, and back for >simulation to prove it meets spec. For a 4010, you could do the spin in a day IFF >you knew what you were doing, and the simulation passes (like that ever >happens first go).Article: 7118
hello everybody,
i am facing some problems compiling my design in the
lattice pDS+ viewlogic software. the version of pDS+ i am using is
1.0 and lattice no longer provides support to it as it is too old(1993).
my design is very simple...it basically consists of two counters, three
muxs and five user( i.e., me) defined macros. all the user defined macros
have only and & or gates and compile fine. i am attaching a part of the
report file and the message log...
-------------------------------------------------------------------------
excerpts from the report file....
------------------------------------
Fitter Parameters Used
----------------------
AVG_GLB_IN: 16
AUTO: OFF
EFFORT: 4
IGNORE_FIXED_PIN: OFF
MAX_DELAY: 2
MAX_GLB_IN: 16
PARAM_FILE:
PART: ispLSI1016-90LJ
TIMING_SIM: timing
TRY:
FAST_ROUTE: OFF
STRONG_ROUTE: FIXED
Process Status
--------------
Design Analysis: complete
Pre-Route Netlisting: complete
Logic Partitioning: complete
Place and Route: incomplete
Post Route: incomplete
Fuse File Generation: incomplete
------------------------------------------------------------------------
excerpts from the message log....
------------------------------------
dpm> pass1 elapsed time: 00:00:52
dpm> formatting output...
LAF2LIF Version 1.50 8/19/93
Copyright (c) Lattice Semiconductor Corp. 1991-1992. All rights reserved.
17018 INTERNAL ERROR: - 25: yacc: Syntax error, state 58.
17018 INTERNAL ERROR: - 31: yacc: Syntax error, state 58.
17018 INTERNAL ERROR: - 33: yacc: Syntax error, state 58.
17018 INTERNAL ERROR: - 35: yacc: Syntax error, state 203.
17018 INTERNAL ERROR: - 36: yacc: Syntax error, state 203.
17018 INTERNAL ERROR: - 37: yacc: Syntax error, state 203.
17003 INTERNAL ERROR: - 130: Invalid <sym_phys_loc>: '/'
17018 INTERNAL ERROR: - 131: yacc: Syntax error, state 282.
17004 INTERNAL ERROR: - 131: Illegal pin attribute.
17003 INTERNAL ERROR: - 154: Invalid <sym_phys_loc>: '/'
17018 INTERNAL ERROR: - 155: yacc: Syntax error, state 282.
17004 INTERNAL ERROR: - 155: Illegal pin attribute.
17003 INTERNAL ERROR: - 162: Invalid <sym_phys_loc>: '/'
17018 INTERNAL ERROR: - 163: yacc: Syntax error, state 282.
17004 INTERNAL ERROR: - 163: Illegal pin attribute.
17016 INTERNAL ERROR: IOC on net RAS has no associated XPIN!
17016 INTERNAL ERROR: IOC on net W has no associated XPIN!
17016 INTERNAL ERROR: IOC on net CAS has no associated XPIN!
dpm> creating reports...
dpm> 25502 WARNING: could not open report file CASRASW.rp7
dpm> abnormal exit. process stopped.
dpm> total elapsed time: 00:02:08
-----------------------------------------------------------------------------
the error numbers above are not listed in the error index in the manual and
i have no clue as to what the problem could be. if someone can give some
insight into this situation, it would be great.
thanks a lot in advance and email replies are most welcome to
kirann@eecs.umich.edu
regards,
kiran nimmagadda.
Article: 7119Sorry to .jps readers for this third post, but I don't think it was propagating past .jps because I had an illegal return adr for the spamers. This time I'll just go straight. ____ I believe I could be more productive producing large, DSP, intensive, Xilinx designs, with two or even more PCs. I believe it would greatly reduce the dead time during long simulations, and place and routs. (In addition to the Xact 6.0 tools, I use ViewLogic's WorkView Office ViewDraw and ViewSim on Win95. I also, MatLab for generating test vectors and viewing results) Someone at Xilinx told me the current version of M1 chokes on NT running multiple PROs. Xilinx Hot Line also does not know if everything runs on the Pentium II. I guess I will have to use M1 in order to target the bigger chips, so. . . 1. If I do FPGAs all day long, and most evenings too, Extra PCs are easily justified, Right? Even $8k or $9k PCs, right? In a network environment, are two PCs enough? Please help me out here. I'm trying to sell my boss. 2. I've seen a switch that can switch a monitor, keyboard, and mouse. among up to 4 live PC boxes. (OmniView Belkin F1D066 for ~$300.00.) Is it any good? 2a. There is also the possibility of controlling multiple PCs on a network, remotely, from one PC. Carbon Copy, I think. Is this a better way? 3. I'm wondering about my two PC flow. Would I want both PCs on my company 10M/sec Novel network? What about hot plugable 8Gig Ultra Wide SCSI drives. They're only $1300 + $119 for the RAID Tray. Any comments? Would I want WVO on one and Xilinx on the other, or would I really need both on both? Thanks very much, We are having fun now! Dave Decker "Animals . . . are not brethren they are not underlings; they are other nations, caught with ourselves in the net of life and time, fellow prisoners of the splendor and travail of the earth." Henry Beston - The Outermost HouseArticle: 7120
There is nothing special about the package that affects the way it is programmed, or what the bit stream looks like. Regardless of package, it is the same piece of silicon (well a functionally identical chip). So the only place that the package selection is involved with the design process is in the naming of the physical pins. So your problem is that when you tell the sw that the package is HQ304, and use pin numbers for that package, it tells you it doesn't exist. Here is a quick work around you could use till Xilinx gets an update to you: Tell the sw you are using the XC4036EX in a PG411 package, and use the equivalent pin names for that package. See page 4-118 of the data book. As an example, if you wanted to specify P302 on the HQ304 package, instead specify pin F6 on a PG411 package. The PG411 has a superset of pins to the HQ304, so all possible pins should be specifyable. Create the bitstream, then load it into your HQ304 part. By the way, in my copy of M1, V1.2.11 (according to the design manager), the XC4036EX HQ304 at least comes up in the part list. I don't have a design handy (or the time) to confirm that the software fails later on, which I guess is what you are seeing. A better fix would be to go in an edit the package files (like you could with the XACTSTEP 6.0.1 sw), but unfortunately M1 data files are all binary, and so can't be edited to fix bugs quickly. (Are you listening Xilinx???) In article <5rsr9r$tsc$1@trog.dra.hmg.gb> cjbradshaw@dra.hmg.gb writes: > >Anyone out there programming the Xilinx 4036XL device in a HQ304 >package...? > >I only ask because we've just bought this device and have received >the Alliance M1.2 software only to find that the HQ304 package is >not supported! > >According to MicroCall, our Xilinx distributor, the HQ304 package >has been accidently left out of not only the M1.2 release, but the >M1.3 release as well! Patches will be available soon, apparently! > >So presumably, no one can actually program this device yet!!?!?! > > >-- >Cliff >cjbradshaw@dra.hmg.gb >"Linux: The Choice of a GNU Generation"Article: 7121
Hi all,
I'm curios about the possibility to change the logic
of a allready programmed FPGA incrementally.
Are there any FPGA's in the market available which allow incremental
updates ???
Best regards
___/___ Armin Steinhoff <Armin@steinhoff.de>
/ / STEINHOFF Automations- & Feldbus-Systeme
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Article: 7122In article <5s02t5$6j@drn.zippo.com> Armin Steinhoff <Armin@Steinhoff.de> writes: > >Hi all, >I'm curios about the possibility to change the logic >of a allready programmed FPGA incrementally. >Are there any FPGA's in the market available which allow incremental >updates ??? > ___/___ Armin Steinhoff <Armin@steinhoff.de> Sure. The Atmel 6000 series and the Xilinx 6200 series. To a lesser extent, all of the Xilinx 4000 series (and derivatives, including the Lucent devices that have RAM capability in the function generators), have some reconfigurability possible by writing to the function generators as ram, then using them as logic. But the first mentioned devices are designed for partial config while running, whearas the use of the function generator RAM is a bit of a stretch. Philip Freidin.Article: 7123
hi, is there anyway to restrict the pins of a Flex10K device to certain orientations in the floor plan tool ? I am trying to assign certain pins to top, left, right or bottom of the device without assigning them to fully specified locations. I am coming from an ASIC background and this is the first floor plan tool which doesn't have this feature in an obvious location if at all. BTW, I have noticed the row and column assignment in the LAB view but there doesn't seem to be any correlation between LAB row, columns and the pin locations on the device. Am I missing something ? thanks muzo WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>Article: 7124
Christine Price <cprice@telogy.com> wrote:
:bob elkind wrote:
[snip]
:> Any pointers on the fine art of driving a JTAG bus, or is this
:> self-evident stuff after reading the IEEE 1149 document?
:>
[snip]
:
:I too, would like to know how to do this using Altera EPLDs (7000S
:parts).
[snip]
I have done this successfully with Xilinx XC4005 parts. The design
(the wole thing, source code included) is on my Web site (URL below).
Follow the "Nice Ideas" link.
-- Dave Brooks <http://www.iinet.net.au/~daveb>
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