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Does anyone know how to instantiate the use of the flip-flops / buffers in the unbonded pads in OrCAD? In a previous desgin I used verilog / synopsys to tell XACT to use those flip-flops to instantiate a 100 bit FIFO. However, I cannot figure out how to do it when starting from OrCAD. Thanks, John -- John ArchambeaultArticle: 7276
Steven J. Ackerman wrote: > <snip> > If you're using Lattice parts, you have to fully complete and debug > your design before you lay out a circuit board. And the signal pinout > will be completely arbitrary, not easily circuit board routable. If > you think that you can go in and re-assign pinouts or make logic > changes after the fact you may be in for a nasty suprise - the Lattice > router may no longer be able to fit your design into the part ! I have > found this to be the case if the part is over 50% utilized. Yikes! We have just completed a design where we routed the PCB FIRST ! ( using ATMEL ATF1500 PLDs, 100% & 87% packed ) This gave very close to single sided routing between RAM, 2 x PLCC44 PLDs, 1 x PLCC44 uC. The other side is now 95% ground plane, and we have a very quiet, 2 layer, design that is a VGA Terminal. I shudder to think how a 'PLD determined' design would have performed :-( This 'my fitter knows best' philosophy is too common, but with pressure, things will get better :-) - jim G. > > The Synario software is easy to use, much better than their own PDS. > > Other than these discrepancies we find the Lattice parts to be useful > and have shipped several thousand units of various designs with no > manufacturing problems. > > Steven J. Ackerman, Consultant > ACS, Sarasota, FL > sja@gte.net > http://www.acscontrol.com -- ======= Manufacturers of Serious Design Tools for uC and PLD ========= = Optimising Modula-2 Structured Text compilers for ALL 80X51 variants = Reusable object modules, for i2c, SPI and SPL bus interfaces = Safe, Readable & Fast code - Step up from Assembler and C = Emulators / Programmers for ATMEL 89C1051, 2051, 89C51 89S8252 89C55 = *NEW* Bondout ICE for 89C51/89C52/89C55 = for more info, Email : DesignTools@xtra.co.nz Subject : c51ToolsArticle: 7277
Provisional Programme
3rd International Workshop on Applications of the
Reed-Muller Expansion in Circuit Design
(Reed-Muller 97)
In Cooperation with IFIP WG 10.5.
Place: Oxford University, Oxford, UK.
Date: September 19-20, 1997
just after ESSCIRC 97 (European Solid-State Circuits Conference)
Southampton, UK, September 16-18 .
This workshop focuses on the application of new techniques in the
representation and realization of discrete functions. AND-EXOR based
representations are often simpler than AND-OR based representations,
and have other important properties. Decision diagrams are being
extensively studied, and have offered powerful new techniques for
verification and synthesis. The goal of the workshop is to bring
together researchers in these and related fields to discuss new
approaches and results. The first workshop was held in September 1993,
in Hamburg, and the second in August 1995, in Tokyo.
Call for posters: As well as the refereed work listed below we are
also making space available for the display of posters describing very
recent work. If you'd like to take advantage of this, simply contact
Frances Page at the address below with the title of your poster and a
list of authors. Space will be allocated on a first come first served
basis.
Enquiries :
Miss Frances Page
Oxford University Computing Laboratory
Wolfson Building
Parks Road
Oxford OX1 3QD, UK.
Tel: +44 1865 283505/273838
Fax: +44 1865 273839
Email: Frances.Page@comlab.ox.ac.uk
Further details are available on the website:
http://www.comlab.ox.ac.uk/oucl/users/jon.saul/ReedMuller97.html
*************************************************************************
FRIDAY 19 SEPTEMBER 1997
************************
08.45-09.10 Registration
09.10-09.15 Welcome
09.15-09.40
Decision Diagrams and AND/OR Graphs for Design Automation Problems
Rolf Drechsler, Wolfgang Kunz, Dominik Stoffel and Alenka Zuzek
09.40-10.05
Reordering Based Synthesis
Andreas Hett, Rolf Drechsler and Bernd Becker
10.05-10.30
ETDD-based Generation of Complex Terms for Incompletely Specified Boolean
Functions
Gueesang Lee
******************
10.30-11.30
Coffee and Posters
******************
11.30-11.55
Minimized Generalized Partially Mixed Polarity Reed-Muller Expansion
M Marek-Sadowska, G Guner, T Krishnamurthy, S Gargeshwari and Ch Sharma
11.55-12.20
Exclusive-OR of Two Sum-of Products Expressions: Simplification and an
Upper Bound on the Number of Products
Debatosh Debnath and Tsutomu Sasao
12.20-12.45
New Fast Approach to Approximate ESOP Minimization for Incompletely
Specified Multi-Output Functions
Ning Song and Marek Perkowski
************
12.45-02.00
Buffet Lunch
************
02.00-02.25
Low Power Aspects of XOR based Circuit Design
Yibin Ye, Kaushik Roy and Rolf Drechsler
02.25-02.50
Lattice Diagrams Using Reed-Muller Logic
Marek Perkowski, Malgorzata Chrzanowska-Jeske and Yang Xu
02.50-03.15
Hardware Acceleration of Two-level ESOP Minimization Using CAMs
Jonathan Saul
***************
03.15-04.00
Tea and Posters
***************
04.00-04.25
Two Hierarchies of Generalized Kronecker Trees, Forms, Decision Diagrams
and Regular Layouts
Marek Perkowski, Lech Jozwiak and Rolf Drechsler
04.25-04.50
Spectral Transforms and Word-Level Decision Diagrams
Rolf Drechsler, Radomir Stankovic and Tsutomu Sasao
***********************
WORKSHOP DINNER
***********************
Day 1 Posters
*************
In addition to posters relating to all the above papers the following
will be displayed during Friday:
Non-Abelian Groups in Optimization of Decision Diagrams Representations
of Discrete Functions
Radomir Stankovic
Reed-Muller Transform and Wavelets Theory: An Alternative Look at
Reed-Muller Expansions
Radomir Stankovic and Yasushi Endow
Test Set Generation for Functional Decision Diagram Circuits using
Genetic Algorithm
A Bystrov and A Almaini
A General Data Structure for XOR-Decomposition of Sets of Switching
Functions
Bernd Steinbach and Christian Lang
Compact Testing of AND-EXOR Programmable Logic Arrays
Roustam Latypov
****************************************************************************
SATURDAY 29 SEPTEMBER 1997
**************************
09.15-09.40
Complexity Measures for AND-EXOR Expressions
Tsutomu Sasao
09.40-10.05
Minimizing Polynomial Implementation of Weakly Specified Logic Functions
and Systems
Arkadij Zakrevskij
10.05-10.30
The Complexity of Symmetric Functions in the Polynomial Forms
Julia Manstivoda and Nikolay Peryazev
******************
10.30-11.30
Coffee and Posters
******************
11.30-11.55
Case Study: Manipulating EXOR-OBDDs by Means of Signatures
Christoph Meinel and Harald Sack
11.55-12.20
Compilation of Fast Manipulation Algorithms for K*BMDs
Stefan Horeth and Rolf Drechsler
12.20-12.45
Combinational Logic-Level Verification using Boolean Expression Diagrams
Henrik Hulgaard, Poul Williams and Henrik Andersen
************
12.45-02.00
Buffet Lunch
************
02.00-02.25
A Heuristic Procedure for Finding AND-OR-XOR Expansions of Incompletely
Specified Boolean Functions
Elena Dubrova, Michael Miller and Jon Muzio
02.25-02.50
A Canonical AND/EXOR Form that includes both the Generalized Reed-Muller
Forms and Kronecker Reed-Muller Forms
Marek Perkowski, Lech Jozwiak and Rolf Drechsler
02.50-03.15
A Critique of Mixed Exclusive-/Inclusive-OR Logic Synthesis for the
Xilinx XC6200 FPGA
Paul Metzgen and Jonathan Saul
***************
03.15-04.00
Tea and Posters
***************
04.00-04.25
A New Linearly Independent, Zhegalkin Galois Field Reed-Muller Logic
Karen Dill, Konika Ganguly, Robert Safranek and Marek Perkowski
04.25-04.50
Universal and Robust Testing of Stuck-Open Faults in Reed-Muller
Canonical CMOS Circuits
D Das, S Chakraborty and B Bhattacharya
04.50-05.15
Reed-Muller-Fourier Representations Versus Galois Field Representations
of Four-Valued Logic Functions
Radomir Stankovic, Dragan Jankovic and Claudio Moraga
05.15-05.20 Closing
Day 2 Posters
*************
Decision Diagrams for Discrete Functions Representations
Radomir Stankovic
On Self-dual Complements of Fixed Polarity Reed-Muller 2-forms
Ken Fok, Malgorzata Marek-Sadowska and Simone Boehringer
Evolutionary Minimization of Generalized Reed-Muller Forms
Karen Dill and Marek Perkowski
Decomposition of Logical Functions in Reed-Muller Logic
Elena Zaitseva and D Popel
Parallel and Distributed Algorithms for Minimization of Incompletely
Specified Logic Functions in Reed-Muller Domain
Svetlana Yanushkevich, Grzegorz Holowinski, Vlad Shmerko and
Elena Zaitseva
************************************************************************
--
Jonathan Saul, Tel: +44 1865 273842
Oxford University Computing Laboratory, Fax: +44 1865 273839
Wolfson Building, Parks Road, Email: Jon.Saul@comlab.ox.ac.uk
Oxford OX1 3QD, UK.
Article: 7278
Hi! Logiblox components are to be viewed as black boxes in Synopsys. The
vhi file
provided is for helping in instantiating the component in your design.
However,
you should attach a dont_touch attribute on these instances in VHDL. Please
note that dont_touch attribute must be attached on the instance name and
not the component name.
For e.g.,
if you have a statement as UADD: ADDER
you have to attch the dont_touch attribute in Synopsys to UADD
dont_touch {UADD}
This will tell Synopsys not to look at this module. Synopsys will issue a
warning to this effct which you can ignore. Later in M1, ngdbuild will
merge
your Logiblox netlist ADDER.ngo with the other netlists and create the
merged
.ngd file.
Anil.
Exjobbare Joachim Strombergson <qmwchim@emw.ericsson.se> wrote in article
<33F9781E.1CFBAE39@emw.ericsson.se>...
> Hi!
>
> I'm having problems using LogiBLOX components as component instances in
> my VHDL-code. I'm using the LBGUI tool to customize the blocks to match
> my need. I then try to include these block in my code by inserting the
> generated VHI-file into my code and completing the port assignments. But
> when I try to read in the design into Synopsys Design Analyzer the tool
> does not recognize the component.
>
> I either would like to inlude the LogiBLOX like any other library, and
> then customize the component with attributes (but don't know how), or
> somehow make Synopsys realize that the implementation of the component
> is given by the generated netlist in the NGO-file.
>
> I've read through the material in the dltext documentation, but it
> doesen't help me out.
>
> Any help greatly appreciated.
> Joachim Strömbergson
>
Article: 7279I just finished a new paper describing two new radix-8 division algorithms that are based on comparisons of relatively narrow operands rather than on confusing, bug-inducing P-D plots. One of the algorithms is maximally- redundant and uses two's complement partial remainders, while the other algorithm is minimally-redundant and uses redundant partial remainders in signed-digit format (requiring no assimilation for each iteration). These algorithms are similar to the ones I presented at ICCD '96, but are fixed-radix (radix-8). That is, the new algorithms no longer retire an unpredictable number of bits per iteration, but instead retire exactly three bits. For a copy of the paper or questions please contact me at Vitit Kantabutra Department of Mathematics Idaho State University Pocatello, ID 83209, U.S.A. vkantabu@howland.isu.edu kantviti@fs.isu.edu (208) 236-3405 (voice) (208) 236-2636 (fax)Article: 7280
Joel W. Kolstad <Joel.Kolstad@Techne-Sys.com> wrote in article <01bcadaa$d72d3140$0307e38f@zimbo>... > Steven J. Ackerman <sja@gte.net> wrote in article > <5tc6sr$6l9$1@gte2.gte.net>... > Cypress likes to pride themselves on the ability to use completely > arbitrary pin assignments when they're trying to convince you to use their > stuff over Lattice's. In general I think they're correct, but one thing > they don't mention is that even their pin assignments start becoming > non-arbitrary when you start utilizing over about 75% of the device. > Better than Lattice, but definitely not as cool as they'd have you believe. Certainly Cypress does reasonably well with user-defined pin assignments even when the device is pretty full. I have been running very close to the wind with one of their devices approx 98% full, and still able to do the odd tweaks to the design. It is noticeable that I had to hand assign the pins originally on this device because Cypresses fitter could not handle the part. The routability of these parts is better than average. GrahamArticle: 7281
Terry Harris wrote: > > Lattice parts have a GRP (global routing pool) which can route any > signal anywhere but unfortunately with some undocumented limitations, > when you lock down pins and the fitter can't fit (which sounds like > the problem the previous poster was getting) it is because of these > GLB restrictions. Being undocumented it is pretty hard to know what to > do about it. > The Lattice parts also have a Output Routing Pool (ORP), which can route any the output of a GLB to any of a set of pins. This is where I found the fitter was running out of resources. Each GLB has a set of associated pins where the ORP can be bypassed, but the fitter was too dumb to assign GLBs to bypass the ORP (even though I assigned the GLBs, the fitter would move them and it wouldn't fit). After some searching, I found I could designate the output as CRIT, the fitter finally bypassed the ORP, and it routed. My experience has been that the Lattice router is the hardest to work with to get pins locked. It clearly takes the "fitter knows best" philosophy. I have also used XILINX XACT fitter, and it is better, but still has problems. I recently had a design with all my pins locked and only one free pin lest on the chip. When I added one more output, I assumed the fitter would know where to put it (the one free pin seemed like a good choice). To my chagrin, the fitter couldn't route this last output. When I locked the pin to the only free output, it routed fine. With fitters like these, it is kind of scarry that Vantis is designing HW around their fitter. Steve Darby Huntsville Microsystems, Inc.Article: 7282
Since the Samsung site is being hacked into pieces can anyone identify these chips. Chip 1: Model No KM41C1600AJ-6 Chip 2: Model No KM41C1600AJ-6 I believe that these are 72 pin chips for pc's but how many megs are they and what speed, etc. Chip3: Model No KMM3144C213AT-6 Chip4: Model No KMM51441000BTG-8 I believe that these chips are for Sun workstations, They are 200 pins but again can anyone supply me with any further details. please send replies to jab@mediatecnicsplc.demon.co.uk as we don't read the newsgroups regularly. Many thanks in advance, Sufyaan Kazi c/o Mediatecnics Plc United KingdomArticle: 7283
John Archambeault wrote: > > Does anyone know how to instantiate the use of the flip-flops / buffers in the > unbonded pads in OrCAD? In a previous desgin I used verilog / synopsys to tell > XACT to use those flip-flops to instantiate a 100 bit FIFO. > > However, I cannot figure out how to do it when starting from OrCAD. > > Thanks, > John > -- > John Archambeault I have never used Orcad for Xilinx design, however, with any schematic capture program you can put a location constraint on the IFD or OFD primitive to specify the location. All unbonded I/O are designated U? instead of P?. So use a constraint similar to LOC=U52. You can find the unused I/O names in XDE. Jim ChaseArticle: 7284
> We are considering the use of ISP CPLD's. Anyone have any amusing > or helpful anecdotes regarding their use? > Thanks much. [M.Vorbach] We crashed a design using Lattice. Don´t use it. Now we use Altera MAX9K and they are OK. We have good experience using 9320 and 9560 and the result is very well up to an utilization of 80% cells and 80% pins. The MaxIIPlus Version 7.2 fitter contains a bug and the result is a very very bad fitting: If you´ll get this problem ask ALTERA for the internal release 7.22. This version works very well! Also we have very good experience using Altera 8K and 10K, but they work with SRAM cells. Please don´t use 7K, they are not very satisfying.Article: 7285
On an Altera Flex 10k130-4 fpga there is a 12.6ns input delay between an external I/O pin and the IOE input register. I'm told this was added to improve the Input Hold time and that the only way to bypass it is to use a register in the LE. This contradicts the 1996 data book recommendation to use the "input register for external data that requires a fast setup time". Adding the 3.8ns FF setup time and subtracting the 5.8 clk distribution, results in a 10.6ns setup time of data to the external clock. Since we advance our fpga clock with an external PLL, this Tinreg=12.6ns is a direct waste of useful clock budget. Needless to say, at 40 MHz, it amounts to half of one's clock cycle. Has anyone dealt with this? Is there some way to get around it? On smaller Flex parts, it is faster using an internal LC register, but doesn't appear to be on the 10K100 and 10K130 parts. Tom -- ------------------------------------------------------------------------------ Thomas P. Pawelko phone: (519) 746-4918Article: 7286
John Archambeault wrote: > > Does anyone know how to instantiate the use of the flip-flops / > buffers in the > unbonded pads in OrCAD? In a previous desgin I used verilog / > synopsys to tell > XACT to use those flip-flops to instantiate a 100 bit FIFO. > > However, I cannot figure out how to do it when starting from OrCAD. > Don't recall where or if this is documented, but you just put the INTERNAL attribute into the part options_1 name field. If you want to lock it to a particular unbonded IOB, I think some variation of "LOC=unnn,INTERNAL" will work. The "u" indicates unbonded, and you need to go into XDE to find out what "nnn" is for a particular unbonded IOB. regards, tom (tburgess@drao.nrc.ca)Article: 7287
I am using OrCAD Express to design into a Xilinx FPGA. My opeations are mostly defined by VHDL. The project simulates perfectly with no problems. When I try to compile so I can move into the Xilinx tools I receive the error message below. c:\orcadwin\express\samples\vhdl\stave_select.vhd(64) : Failure : [Load061] Unsynthesizable element of design: use of generic symbol stave ERROR [SYN0003] The synthesis operation failed. Compile operation failed When I double click on that line in the session log the line below is highlighted in the VHDL source file. else delay_num := (abs(Beam - stave)) mod mod_num; Beam and delay_num are variables. mod_num is a constant. stave is a generic. Thank you for your help. **************************************************** *Michael R. Palmer * *Scientific Programmer * *e-mail: m_palmer@edocombat.com * *Ph. (757) 424-1004 * *Fax (757) 424-1602 * **************************************************** Sincerely, Michael R. PalmerArticle: 7288
Steve Darby wrote: > > Terry Harris wrote: > > > > > Lattice parts have a GRP (global routing pool) which can route any > > signal anywhere but unfortunately with some undocumented limitations, > > when you lock down pins and the fitter can't fit (which sounds like > > the problem the previous poster was getting) it is because of these > > GLB restrictions. Being undocumented it is pretty hard to know what to > > do about it. > > > > The Lattice parts also have a Output Routing Pool (ORP), which can route > any the output of a GLB to any of a set of pins. This is where I found > the fitter was running out of resources. Each GLB has a set of > associated pins where the ORP can be bypassed, but the fitter was too > dumb to assign GLBs to bypass the ORP (even though I assigned the GLBs, > the fitter would move them and it wouldn't fit). After some searching, > I found I could designate the output as CRIT, the fitter finally > bypassed the ORP, and it routed. > > My experience has been that the Lattice router is the hardest to work > with to get pins locked. It clearly takes the "fitter knows best" > philosophy. > > I have also used XILINX XACT fitter, and it is better, but still has > problems. I recently had a design with all my pins locked and only one > free pin lest on the chip. When I added one more output, I assumed the > fitter would know where to put it (the one free pin seemed like a good > choice). To my chagrin, the fitter couldn't route this last output. > When I locked the pin to the only free output, it routed fine. > > With fitters like these, it is kind of scarry that Vantis is designing > HW around their fitter. > > Steve Darby > Huntsville Microsystems, Inc. Maybe you just didn't know how to best utilize the fitter! Pins can be fixed in the source file (schematic or VHDL), with a seperate pin file or in the most recent Lattice fitter by point and click. In the last case a window opens showing the signal names - you click on the signal name than click on the pin shown on the package diagram. I don't know what could be easier. I have not seen any issues with Lattice parts pin-lock performance even at very dense utilization. They also have an app note benchmarking pin locking performance on their web page at http://www.latticesemi.com. EdArticle: 7289
The X84 FPGA development board is available in the
Month of September for $199.00. The price goes back up
to $275.00 at the end of September.
*The X84 is a XILINX FPGA development
*Board which can run in a PC or stand alone.
*It feature:
*An on board FPGA,
*Prom socket,
*Oscillator socket,
*Timer circuit,
*Status LEDs,
*Download software,
*C code,
*8255 chip,
*Decode pal,
*Strapable PC address,
*Accepts XILINX Download cable.
*Four 20 pin IDC IO connectors.
*VHDL examples
*C code boilerplates.
The FPGA is socketed and the board
can take the following FPGAs:
X84 BOARD FPGA Typical Gate
Count
XC5202PC84
2-3K
XC5204PC84
4-6K
XC5206PC84
6-10K
XC5210PC84
10-16K
XC4003PC84
2-5K
XC4005PC84
3-9K
XC4006PC84
4-12K
XC4008PC84
6-15K
XC4010PC84
7-20K
The board is also available with the XILINX Foundation Software
See the details of the board and the software kits that go with it at:
http://www.associatedpro.com/aps/x84.html
A free on line tutorial for the board is available at :
http://www.associatedpro.com/aps/x84lab
and a free EDA on line newsletter is available at:
http://www.associatedpro.com/aps
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President
Associated Professional Systems Inc. (APS)
email: aaps@erols.com
web site: http://www.associatedpro.com
Phone: 410-569-5897
Fax: 410-661-2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Article: 7290Aptix 'http://www.aptix.com' is probably your best bet. There is also a fairly comprehensive list of FPGA/CPLD boards listed on The Programmable Logic Jump Station at 'http://www.optimagic.com/boards.html'. -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.com Bjorn Sihlbom <emwbs@emw.ericsson.se> wrote in article <33F9B003.1381@emw.ericsson.se>... | Hi! | | I need to prototype a board incl. a complex ASIC. | Do anyone know about of-the-shelf boards with space for a lot of big | FPGAs and perhaps configurable routing? | | Any other hints? | | Regards, | | Bjorn. |Article: 7291
Martin Vorbach <Martin.Vorbach@SCRAP.de> wrote: >> We are considering the use of ISP CPLD's. Anyone have any amusing >> or helpful anecdotes regarding their use? >> Thanks much. > [M.Vorbach] > > We crashed a design using Lattice. Don´t use it. Lots of people have crashed BMW's wouldn't stop me guying one <grin> > Now we use Altera MAX9K and they are OK. We have good experience >using 9320 and 9560 and the result is very well up to an utilization of >80% cells and 80% pins. > The MaxIIPlus Version 7.2 fitter contains a bug and the result >is a very very bad fitting: If you´ll get this problem ask ALTERA for >the internal release 7.22. This version works very well! And how is 8.0 that's been out for a couple of months? > > Also we have very good experience using Altera 8K and 10K, but >they work with SRAM cells. Please don´t use 7K, they are not very >satisfying. Must be thousands of not very satisfied Altera 7k users out there then? I don't suppose anyone wanting faster then 15ns would find the 9k series very satisfying either. Cheers Terry...Article: 7292
Ed Barrett <ed.barrett@worldnet.att.net> wrote: >Maybe you just didn't know how to best utilize the fitter! Pins can be >fixed in the source file (schematic or VHDL), with a seperate pin file >or in the most recent Lattice fitter by point and click. In the last >case a window opens showing the signal names - you click on the signal >name than click on the pin shown on the package diagram. I don't know >what could be easier. Duhh I think we figured out how to ask it to lock pins, we didn't figure out how to make it fit after locking pins. Having a pair of 16bit data buses randomly scattered around a 208pin package is pretty ugly. Slightly less ugly is as close as I got. >I have not seen any issues with Lattice parts >pin-lock performance even at very dense utilization. Well you can't have looked too closely because there are. The way product terms are shared within GLBS mean a complex function only leaves room for simple ones so there is some arbitrary gouping into GLBS based on function product term requirements. Then there is the limited number of inputs to GLBS which again can cause grouping. Then product term clocks feed all 4 flipflops in a GLB so one flipflop with a product term clock means the rest of the GLB can only be used for non-registered functions. Within a Megablock you have the output routing pool which can help a lot but there are also undocumented restrictions in the GRP which means even if you have things nicely fitting into GLBS (or twin GLBS in the 3k series) you can't move the GLBS around in the device. You try it and the fitter just takes longer, prints a few more dots and barfs saying it can't route (or something like that). When you do get something the fitter manages to route you don't get any indication of GRP usage except perhaps how many dots the fitter printed while trying, just cross your fingers and hope that it will take more than a few 'straws' to break the fitter again. That said I don't think the Lattice parts are significantly worse than anyone else they have a larger number of small restrictions (like I said quirky) so some designs will fit and run better in a Lattice part compared to the competition. Cheers Terry...Article: 7293
My division paper is now available at the following site: http://math.isu.edu/~vkantabu/radix8.pdf I'd really appreciate any comments you may have about these new results.Article: 7294
Terry Harris started a thread: >>> Lattice parts .. global routing pool ... undocumented limitations, >>> when you lock down pins and the fitter can't fit .... To which Steve Darby added comments including: >> The Lattice parts also have a Output Routing Pool (ORP), which can route >> any the output of a GLB to any of a set of pins. This is where I found >> the fitter was running out of resources. Each GLB has a set of >> associated pins where the ORP can be bypassed, but the fitter was too >> dumb to assign GLBs to bypass the ORP (even though I assigned the GLBs, >> the fitter would move them and it wouldn't fit). After some searching, >> I found I could designate the output as CRIT, the fitter finally >> bypassed the ORP, and it routed. Then Ed Barrett commented: > Maybe you just didn't know how to best utilize the fitter! Pins can be > fixed in the source file (schematic or VHDL), with a seperate pin file > or in the most recent Lattice fitter by point and click. In the last > case a window opens showing the signal names - you click on the signal > name than click on the pin shown on the package diagram. I don't know > what could be easier. I have not seen any issues with Lattice parts > pin-lock performance even at very dense utilization. They also have an > app note benchmarking pin locking performance on their web page at > http://www.latticesemi.com. Read Steve's post more carefully. Steve DID know all about locking pins, his problem was that he had to lock the GLB, the pin, AND the interconnect between them before the fitter would come up with the right answer. A different problem to the one you comment on, but very significant given the architecture. Using Lattice's TERRIBLE pDS software I ended up fixing just about everything, so the fitter had almost nothing to do. Even most of the logic was sorted outside pDS. That way I knew what I was getting and how it was derived. (Note that when Lattice recently updated pDS, they didn't even bother to tell me, despite my pDS being a full-price, registered copy. Unless the new one is a vast improvement, I'm not sure it would be worth upgrading anyway.) A secondary issue with Lattice (and many other CPLDs) is that despite all these routing pools, the silicon is arranged in blocks of blocks, so there is no way (with the bigger parts at least) that you can have totally free pin assignment. I'm not knocking the architecture - it has a lot of good points - but it isn't, and can't be, a total solution. Tim Forcer tmf@ecs.soton.ac.uk Department of Electronics & Computer Science The University of Southampton, UK The University is not responsible for my opinionsArticle: 7295
Does anyone know of a supplier of tested & documented VHDL code for a VME slave interface? Thanks in advance, PatrickArticle: 7296
I finally found someone at Xilinx who 'explained' what was going on in the simulations... He said that the timing numbers that are in the simulation file are 'extremely conservative' and they have a perl script that I have to run on the back annotated .xnf file to put in the 'databook' numbers. So, I ran this script, and now my simulation works fine....but the actual silicone still doesn't work behind a DEC bridge...and when we try to probe it...it works... So, next question is has anyone tested out their Xilinx PCI design behind a PCI bridge? Austin Franklin darkroom@ix.netcom.com Austin Franklin <dark9room@ix.netcom.com> wrote in article <01bcacd2$220a6ef0$f249bacd@drt1>... > The PCI bus spec guarantees 7ns setup and 0ns hold. In order to meet the > PCI spec, the 4k IOB flip flops have to be set to delay...which claims to > require a 7ns setup, and 0ns hold. > > Ok, all that seems fine...but when I generate a .vsm file and simulate this > using ViewSim and a command file that gives 7ns setup and 0ns hold, I get > setup violations..claiming setup is 6.2, 10.2 is required. Interestingly > enough, it's not the 7ns setup that is causing the problem, it's the 0ns > hold. When I change the 0ns hold to 11, it works fine. > > Now...my first guess is something is wrong with the timing model that > Xilinx provides. I have not gone into the .vsm file to see what it is that > is wrong, but I am about to. > > What my question is, has anyone simulated a Xilinx PCI design using ViewSim > and using 7ns setup and 0ns hold....successfully? > > Thanks, > > Austin Franklin > darkroom@ix.netcom.com > > To reply to this post, remove the number from the reply address. > >Article: 7297
MaxPlus2 works well in general but I have a few complaints: (1) It has a habit of overwriting your design input files (e.g. *.acf, maxplus2.ini). So, for consistent results you must keep extra copies of these and write a script that copies them into the relevant directories. (2) After invocation, it will chug along for minutes before it tells you "license in use". (3) It does not always reserve device pins as you would expect based on your design input. (I think if you have an undriven output pin, it will not reserve it. Things like that.) SteveArticle: 7298
Steven J. Ackerman wrote: > ... > > If you're using Lattice parts, you have to fully complete and debug > your design before you lay out a circuit board. And the signal pinout > will be completely arbitrary, not easily circuit board routable. If > you think that you can go in and re-assign pinouts or make logic > changes after the fact you may be in for a nasty suprise - the Lattice > router may no longer be able to fit your design into the part ! I have > found this to be the case if the part is over 50% utilized. > ... I have the bad habit that I design the PCB fisrt and assume that all PLDs would fit. Altera FPGAs cause no trouble. But the puzzle game I have to play with Lattice GLBs to fit in the given part can be very annoying. Cheers, Botond -- Kardos, Botond - at Innomed Medical Ltd. in Hungary eMail: kardos@mail.matav.hu phone/fax: (0036 1) 351-2934 fax: (0036 1) 321-1075Article: 7299
Oops, I've almost forgot to mention that besides their routing problems I do like Lattice PLDs. They're fast (consume a lot :< ) and the ISP is quite easy with them. -- Kardos, Botond - at Innomed Medical Ltd. in Hungary eMail: kardos@mail.matav.hu phone/fax: (0036 1) 351-2934 fax: (0036 1) 321-1075
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