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Authors (T)

T:
    128251: 08/01/19: Re: effect of xray on fpga electronic circuits
t hicks:
    58037: 03/07/12: edge card connectors and high speed design
    58059: 03/07/13: Re: Graduation Day: My first 4-layer PCB
    58154: 03/07/15: Re: Graduation Day: My first 4-layer PCB
T Lee:
    73802: 04/09/29: Re: embedded linux on FPGA?
    75201: 04/10/28: Re: Newbie: Read from Compact Flash using System ACE
    74377: 04/10/08: Use Xilinx VP20 with 2 ppc and one DRAM chip
    74423: 04/10/11: Re: Use Xilinx VP20 with 2 ppc and one DRAM chip
    74424: 04/10/11: low cost MPEG4 codec (from Atmel )
    75834: 04/11/16: Suggestion for Xilinx parallel port cable replacement.
    75870: 04/11/17: Re: Suggestion for Xilinx parallel port cable replacement.
    75871: 04/11/17: Re: Suggestion for Xilinx parallel port cable replacement.
    75968: 04/11/20: How to get the PPC profiler to work in Xilinx VP2 platform?
T Stewart:
T-Mike:
    116857: 07/03/19: Sparten 3E clock generator
T-Online:
    31476: 01/05/27: Fragen zu PCI und FPGA
    31483: 01/05/27: Help for PCI and FPGA
    31560: 01/05/30: Re: Fragen zu PCI und FPGA
    31576: 01/05/30: Re: Fragen zu PCI und FPGA
    31696: 01/06/03: PCI Config Register Space
    31963: 01/06/09: SRAM 8 Bit access write/32 Bit acces read
T. D. Bouvia:
    2709: 96/01/26: VHDL/Verilog training
T. Franklin:
    14649: 99/02/08: comp.arch.fpga Archives
T. Irmen:
    57104: 03/06/23: Re: JBits and Virtex II Pro
    60937: 03/09/25: chipscope pro and jtag
    60961: 03/09/25: Re: chipscope pro and jtag
    62348: 03/10/27: Re: chipscope pro and jtag
    63571: 03/11/25: XVPI
    64484: 04/01/05: v2px70 available?
    65225: 04/01/22: systemc download page?
    65283: 04/01/23: sccom and win32? when does it come available?
    65291: 04/01/23: Re: systemc download page? [OK now]
    66888: 04/02/28: netlist tricks
    66931: 04/03/01: Re: netlist tricks
    66968: 04/03/02: Re: netlist tricks
    67254: 04/03/09: a way to use netlists from C
    68630: 04/04/11: Re: 66B mode of VirtexII-ProX Rocket I/O
    68646: 04/04/12: Re: 66B mode of VirtexII-ProX Rocket I/O
    75808: 04/11/15: RocketIO clock recovery
    75810: 04/11/15: JTAG boundary scan xc2v6000
    77887: 05/01/19: Re: LVDS through connectors
    78990: 05/02/11: configuration problem xc2v6000/8000
    90089: 05/10/04: ise (lin64) and debian
T. Konschak:
    8202: 97/11/27: AHDL vs. VHDL
t.bartzick@gmx.net:
    135160: 08/09/18: Clock Enable safe?
    135162: 08/09/18: Re: Clock Enable safe?
    135166: 08/09/18: Re: Clock Enable safe?
    135170: 08/09/19: Re: Clock Enable safe?
T.Dattuprasad:
    32963: 01/07/13: Foundation2.1i
T.E.Lawrence:
T.Hansen:
    127634: 08/01/04: Vendors of FPGA's
    127751: 08/01/07: Re: Vendors of FPGA's
T.Koyama:
    20345: 00/02/07: Where SpartanXL CS280 Pin Locatin
    26787: 00/10/29: Webpack Error?
T.SWIFT:
    24809: 00/08/19: Xilinx Student Edition Floorplanning
t2531998@126.com:
    104086: 06/06/18: --.-Low Cost High quality pcb prototype and Assembly manufacturer(CHINA).
TA:
    84826: 05/05/29: beginer
Taavi Hein:
    66704: 04/02/25: Re: Free PCI-bridge in VHDL for Spartan-IIE
    66751: 04/02/26: Re: Free PCI-bridge in VHDL for Spartan-IIE
tabenash2002:
    153653: 12/04/10: Data Transfer from PC to FPGA through USB
    153689: 12/04/22: Re: Data Transfer from PC to FPGA through USB
tachometer:
    153528: 12/03/25: Digital Tachometer VHDL
taco:
    123392: 07/08/27: Re: xilinx usb cable question
    124057: 07/09/11: microblaze toolchain compilation question
    124100: 07/09/12: Re: microblaze toolchain compilation question
    125328: 07/10/22: Re: Building a Huffman codebook in VHDL
    125662: 07/10/31: xilinx bmm file problem
    125785: 07/11/05: Re: xilinx bmm file problem
    126462: 07/11/23: Re: xilinx spartan 3 + 16 adc
    127350: 07/12/19: FPGA program cable suggestion
    127356: 07/12/19: Re: FPGA program cable suggestion
    128394: 08/01/24: microblaze question
    128417: 08/01/25: Re: microblaze question
    128418: 08/01/25: Re: microblaze question
    128691: 08/02/04: Re: microblaze question
    128829: 08/02/07: Prom alternatives for xilinx
    128870: 08/02/08: Re: Prom alternatives for xilinx
    131940: 08/05/08: EDK for spartan2?
    132129: 08/05/15: xilinx spi core question (microblaze)
    132337: 08/05/22: problem with microblaze connected ip core
    132338: 08/05/22: Re: problem with microblaze connected ip core
    132634: 08/06/04: Re: VHDL to Verilog Converter
    134491: 08/08/13: Re: Microblaze Projects
    134617: 08/08/21: Re: Workaround for installing EDK on Vista x64?
    136910: 08/12/12: dsp boards with multiple AD channels question
Taco Walstra:
    154482: 12/11/14: viewing old aldec/xilinx foundation schematics
    154484: 12/11/14: Re: viewing old aldec/xilinx foundation schematics
Tactics:
    5923: 97/03/26: Consulting Opportunity
Tad B Artis:
    2739: 96/01/31: Xilinx or Altera for Newbie?
    2750: 96/02/01: Re: Xilinx or Altera?
    2813: 96/02/12: Re: FPGA entry for <$1000?
    2844: 96/02/16: Re: Xilinx is NOT specified MINIMUM delay -
Tadaaki Koyama:
    7733: 97/10/08: Japanese FPGA mailing list
    10616: 98/06/06: Write to XC17S20 fail
    26802: 00/10/30: Re: Webpack Error?
Tadashi Kobayashi:
    39472: 02/02/12: Re: Multiple clock domein synchronization.
    39960: 02/02/23: Re: Replacing expensive configuration SPROM
TADedek:
    5491: 97/02/20: Re: Q: Search Engines for Electronic Parts?
Tadej:
    31311: 01/05/18: PCI IP Core spec AVAILABLE !
    31442: 01/05/24: PCI core PROGRESS
Tadesa:
    36687: 01/11/15: CAM
    36699: 01/11/16: Re: CAM
<taetzsch@asic-alliance.com>:
    21943: 00/04/07: US - Engineering Opportunities in NH,MA,NJ,NY,CA
tagough@gmail.com:
    125430: 07/10/25: Signetics N82F101F
    125565: 07/10/29: Re: Signetics N82F101F
Tahoma Toelkes:
    9977: 98/04/20: Re: Effects of IC production
Tails:
    73736: 04/09/28: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
    74278: 04/10/06: Re: DCM and CLKFX - is this allowed?
    74728: 04/10/17: Re: NI*S II-verilog in Virtex FPGA
<TaiYing@gmail.com>:
    109729: 06/10/04: Xilinx ML310 logical analyzer
Taka:
    52941: 03/02/26: Programming Altera EPC1 with ByteBlaster
    53888: 03/03/26: Programming algorithm of Altera EPC1
<takanori_fujiki@usa.net>:
    11047: 98/07/15: Looking for useful "Shell Script" for HDL tools
    11093: 98/07/18: How can I do Gate Level Simulation by Verilog-XL after mapping by ALTERA MAX +plus II ?
Takashi Hidai:
    440: 94/11/16: Look for FPGA/ASIC tool
    2788: 96/02/08: Help ! Xilinx FPGA -> ASIC conversion
    3945: 96/08/23: Verilog vs. VHDL
<takecards@answerme.com>:
    5796: 97/03/15: ACCEPT MAJOR CREDIT CARDS !!!!!!
<takehiro@rr.iij4u.or.jp>:
    17514: 99/08/04: RLOC constraint not interpreted correctly?
Takemoto,Satoru:
    20843: 00/02/24: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
takkaya:
    62918: 03/11/11: Multiple clock domains in a FPGA (using DLL's)
Tal Lachmann:
    59268: 03/08/13: PCI on Virtex II Pro
    59269: 03/08/13: PCI on Virtex II Pro (corrected)
tal_h:
    65997: 04/02/11: Configuration Altera Decives using EPC16 in PPS mode
    65998: 04/02/11: Altera EPC16 Configuration Problem
    66151: 04/02/12: Re: Configuration Altera Decives using EPC16 in PPS mode
    75479: 04/11/07: Fifo problem in Cyclone devices
Talal:
    50174: 02/12/04: Full-Page in SDRAM
    51167: 03/01/04: place and route problem
    51179: 03/01/05: Re: place and route problem
    52049: 03/01/29: problem in Virtex
    52249: 03/02/05: Mix VHDL with Verilog modules
TalentLab:
    20594: 00/02/15: Product Validation Engineers Needed!
TalentLab Inc.:
    18208: 99/10/07: FPGA ???
<tali.cliff@gmail.com>:
    104408: 06/06/26: Accelerated Bioinformatics Data Processing Solutions
talkb:
    128452: 08/01/27: Re: problem simulating in modelsim - swiftpli_mti.dll
    128453: 08/01/27: Xilinx Spartan 3A/DSP with Coregen 9.2i?
    128468: 08/01/27: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
    128472: 08/01/27: Re: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
    128474: 08/01/27: Re: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
    128498: 08/01/29: Re: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
    128504: 08/01/29: Active-HDL 7.3 web-eval and Xilinx 9.2i.04 Smartmodel simulation?
    128529: 08/01/30: Re: Active-HDL 7.3 web-eval and Xilinx 9.2i.04 Smartmodel simulation?
    128530: 08/01/30: Re: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
    128632: 08/02/01: Re: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
    128672: 08/02/03: Re: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
TAM ERNEST CHI YUI:
    986: 95/04/07: PPR problem
Tam/WB2TT:
    77743: 05/01/15: Re: What is the difference between ASIC and FPGA?.
tamania:
    104364: 06/06/26: problem in simulating FFT core on ISE 7.1
Tamar Poker:
    39517: 02/02/12: Power estimation for Virtex-2 device
    39611: 02/02/14: Re: Power estimation for Virtex-2 device
Tamas Csetkovics:
    35537: 01/10/10: Re: VHDL code
<tammie.eric@gmail.com>:
    155220: 13/06/12: New soft processor core paper publisher?
<tammie_eric@verizon.net>:
    155512: 13/07/12: Re: New soft processor core paper publisher?
tamoruso:
    145477: 10/02/11: Re: Multple architectures in ISE top level module?
tamu.edu:
    41490: 02/03/29: PCI Compliance..
Tan Peng Khiang:
    52407: 03/02/08: Overclock Xilinx Coolrunner 2 ?
    52446: 03/02/10: Re: Overclock Xilinx Coolrunner 2 ?
    54281: 03/04/07: Coolrunner 2 's 16 pins output effect
    54320: 03/04/08: Re: Coolrunner 2 's 16 pins output effect
    54321: 03/04/08: Re: Coolrunner 2 's 16 pins output effect
    54322: 03/04/08: Re: Coolrunner 2 's 16 pins output effect
    54410: 03/04/10: Re: Coolrunner 2 's 16 pins output effect
    54841: 03/04/20: Re: Xilinx to process 8-bit paralell binary to ICM7212 for LED display
Tan Shin Account:
    11527: 98/08/21: Re: 4PPM Algoritm
<tandon.sourabh@gmail.com>:
    109674: 06/10/02: Re: Looking for HDL code for sin( a ) and x ** y Functions
tandt_53:
    151813: 11/05/20: AVI container and VGA display
tang:
    126751: 07/11/30: Traffic Light with counter
    126764: 07/12/01: Re: Traffic Light with counter
    126765: 07/12/01: Re: Traffic Light with counter
Tang King:
    44882: 02/07/03: Who are making BGA and gasket ?
<tangirala@gmail.com>:
    78052: 05/01/23: question regarding the physical dimensions of FPGAs
    78054: 05/01/23: question regarding the physical dimensions of FPGAs
    79006: 05/02/10: doubt on configuring FPGA
tangozebra:
    25720: 00/09/18: Re: Non-disclosures in job interviews, Round Two
Tania Shpirer:
    15141: 99/03/09: Virtex secondary clock drivers fan out
taniwha:
    23937: 00/07/16: Re: Error: Clock skew plus hold time of destination register exceeds
Tank:
    98797: 06/03/16: Re: Where are FPGA heading?
    99544: 06/03/26: Re: chip reverse engineering
    99554: 06/03/26: Re: chip reverse engineering
Tanthanuch.SAWIT:
    20372: 00/02/08: Xilinx board
    20394: 00/02/09: Re: Xilinx board
Tara:
    108321: 06/09/07: Hennessy & Patterson new ed Computer Architecture:A Quantitative Approach
Taras Zima:
    21606: 00/03/25: RTL vs. gate level simulation
    21696: 00/03/28: Re: RTL vs. gate level simulation
    22046: 00/04/15: synchronous FIFO
    22053: 00/04/16: Re: synchronous FIFO
Tariq Naqvi:
    51621: 03/01/17: Atmel FPSLIC UART Code
Tarmo Palm:
    70579: 04/06/21: Re: Frequency synthesizer.
    71103: 04/07/07: Re: Urgent : Xilinx PACE question
    72193: 04/08/11: Hardware Multipliers with Virtex II
<tarmopalm@gmx.de>:
    130806: 08/04/02: Re: "Number of BSCANs: 2 out of 1 200%"
    131559: 08/04/25: Re: noob question
tarujab:
    141647: 09/07/02: Technology mapping in edif netlist to adders and multipliers
tasi:
    21623: 00/03/27: [co-design] HW/SW co-design
tasi@emc:
    34657: 01/09/02: [testbench] testbench porting from Cadence to Altera
Taufik Siswanto:
    62623: 03/11/03: 5 input LUT in virtex
Tauno Voipio:
    39082: 02/01/31: Re: Java or bytecode processors??
    40701: 02/03/13: Re: Mystery two wire interface, or am I being dense?
    42203: 02/04/18: Re: I2C Slave sampling edge
    52271: 03/02/05: Re: clock ditribution tree
    57093: 03/06/23: Re: regarding I2C protocols
    57095: 03/06/23: Re: regarding I2C protocols
    57153: 03/06/24: Re: regarding I2C protocols
    66476: 04/02/20: Re: Amontec problems...
    82039: 05/04/06: Re: ISA vs. patent/trademark
    82072: 05/04/06: Re: ISA vs. patent/trademark
    117527: 07/04/03: Re: Implementing a communication protocol for data transfer over
    149191: 10/10/06: Re: Driving a design via TCP/IP
    149196: 10/10/06: Re: Driving a design via TCP/IP
Taylor Hutt:
    116916: 07/03/20: Why is Xilinx's WebPACK so inferior?
    116990: 07/03/21: Re: Why is Xilinx's WebPACK so inferior?
    117002: 07/03/21: Re: Why is Xilinx's WebPACK so inferior?
    117085: 07/03/22: Re: How to use the DDR SDRAM instead of Block RAM?
    117548: 07/04/03: Xilinx: WARNING:PhysDesignRules:372 (What the heck?)
tb:
    33816: 01/08/06: Re: Which is the best Design Toolchain?
tbiggs:
    51282: 03/01/09: Virtex-II Pro misfire?
    51314: 03/01/10: Re: Virtex-II Pro misfire?
    63306: 03/11/19: Re: NB! I do not use *Keeper* feature for I/O pin termination.
    68123: 04/03/26: Re: study verilog or vhdl?
tbrown:
    110482: 06/10/16: Re: echo $LM_LICENCE_FILE not working
    111395: 06/11/02: Re: I can not simulate "pipelined divider v3.0"
    111473: 06/11/03: Re: EDK 8.2i/cygwin issues
    113841: 06/12/24: Re: Need Recommandation for DDR2 controller virtex4
<tbrychcy@my-deja.com>:
    26277: 00/10/10: Setup error
tbx135:
    64173: 03/12/19: Re: How LVDS Drivers kills?
    64223: 03/12/21: Re: WHAT APPLICATION WE CAN IMPLEMENT ON VERTEX II PRO
    64226: 03/12/21: Re: How LVDS Drivers kills?
    64227: 03/12/21: Re: Spartan3 availability
    64233: 03/12/22: Re: Spartan II Block Ram
    64245: 03/12/22: Re: Hyperthreading vs. Dual proc
    64246: 03/12/22: Re: Spartan II Block Ram
    64247: 03/12/22: Re: Spartan II Block Ram
    64257: 03/12/22: Re: Spartan II Block Ram
    64269: 03/12/23: Re: Hyperthreading vs. Dual proc
    64662: 04/01/10: Re: Dedicated CLK lines in CPLD
    64676: 04/01/11: Re: Dedicated CLK lines in CPLD
    64692: 04/01/11: Protecting Designs - any suggestions
TC:
    47375: 02/09/24: Re: Fast serial interconnect bus using spartan-II
    50165: 02/12/03: Re: Low Speed Serial Bus Suggestions
    54855: 03/04/20: Re: bidirectional differential pairs, possible?
    54951: 03/04/22: Re: bidirectional differential pairs, possible?
    54952: 03/04/22: Re: bidirectional differential pairs, possible?
    58304: 03/07/19: Re: Level translators on PCI
    58305: 03/07/19: Re: PCI - disabling
    63124: 03/11/15: Re: PCI Slot Expansion
    91101: 05/10/29: Re: Semi-OT: LVDS and Cold Sparing
    97558: 06/02/24: Re: Kalman filters
    97562: 06/02/24: Re: Kalman filters
    97627: 06/02/24: Re: Kalman filters
    115181: 07/02/02: Re: PCI Express user group
    116055: 07/02/28: Re: PCI-E TS1s
    116130: 07/03/02: Re: PCI-E TS1s
    128653: 08/02/01: Re: Low Pin Count (LPC) bus code available?
    130709: 08/03/30: Re: Serial Transmission w/o 8B/10B encoding
<tchoh@my-deja.com>:
    29071: 01/02/05: Rijndael
    29095: 01/02/06: Re: Rijndael
<tclin1998@gmail.com>:
    112041: 06/11/15: VCD (value change dump) files
<tcollera@altera.com>:
    99598: 06/03/27: Re: Altera web site inaccessible
    99704: 06/03/28: Re: Altera web site inaccessible
TD:
    88972: 05/09/01: Xilinx Virtex II fpga - providing single ended signal to lvds defined pin
    88984: 05/09/01: Re: Modelsim XE and multi-file Verilog projects
td:
    60456: 03/09/13: Re: Foundation 3.1 to ISE 5.2
<tdillon@dilloneng.com>:
    115222: 07/02/03: Re: circle generation algorithm
Tea:
    108854: 06/09/18: how to do the synthesis
    108856: 06/09/18: Re: how to do the synthesis
Team C:
    149567: 10/11/05: crazy error message
techG:
    125409: 07/10/24: builing a SPI interface in vhdl
    125643: 07/10/30: Re: builing a SPI interface in vhdl
    126343: 07/11/20: problem with adding custom logic to an IP core (xilinx edk)
    129854: 08/03/07: Re: Xilinx MIG2.0 DDR2 memory controller
    132845: 08/06/09: TI DSP + Virtex-5 using EMIF interface
    133247: 08/06/22: virtex-5: can't use DCM (too low input frequency)
    133257: 08/06/22: Re: virtex-5: can't use DCM (too low input frequency)
    133310: 08/06/24: Re: virtex-5: can't use DCM (too low input frequency)
techie:
    84656: 05/05/24: how to apply different stimulus files to a test bench
Technisource:
    3584: 96/07/01: WANTED: SOME HELP PLEASE
    3730: 96/07/22: I NEED HELP!!!!
Technisource Inc.:
    22748: 00/05/22: US-IL-In desperate need of FPGA engineer
Technology Consultant:
    60251: 03/09/09: Re: Clock Synchronization of PC and FPGA
    60298: 03/09/10: Re: Clock Synchronization of PC and FPGA
techpaperx:
    139675: 09/04/08: How to insert Chipscope blocks directly in Xilinx Project Navigator
    139707: 09/04/09: Re: How to insert Chipscope blocks directly in Xilinx Project
TED:
    44965: 02/07/08: Are these design guideline safe ?
    44974: 02/07/08: Re: Are these design guideline safe ?
    46210: 02/08/21: Is this asynchronous design safe ?
ted:
    45987: 02/08/13: Altera Byteblaster MAX7k programming problem
    46051: 02/08/15: Re: Altera Byteblaster MAX7k programming problem
    46365: 02/08/27: Altera Quartus II problems
    46379: 02/08/27: Re: Altera Quartus II problems
    46398: 02/08/28: Re: Altera Quartus II problems
    46424: 02/08/29: Re: Altera Quartus II problems
    48782: 02/10/24: DLL and PLL in Xilinx and Altera
    49451: 02/11/12: Re: Altera MAX7000E (EPM7128ELC84) - programmer?
    49494: 02/11/13: Costing FPGA design projects
    49589: 02/11/16: CoolBlaze and PicoBlaze
    49935: 02/11/26: Fast Digital Synthesis Generator
    49973: 02/11/27: Re: Fast Digital Synthesis Generator
    50104: 02/12/02: Re: Fast Digital Synthesis Generator
    55844: 03/05/21: Programming Altera EPC1 and EPC1441
    57086: 03/06/23: Re: Altera FPGA
    62178: 03/10/21: Re: Altera programming problem
    65712: 04/02/05: Quartus II taking forever to compile
    65832: 04/02/07: Re: Quartus II taking forever to compile
    67954: 04/03/23: Re: How many times can I burn an FPGA?
    68136: 04/03/27: AHDL, VERILOG or VHDL??
    69140: 04/04/28: Re: Altera ByteBlaster II schematic
    72549: 04/08/24: Xilinx in Linux
    113130: 06/12/06: VHDL Variable Length Input file.
    123064: 07/08/15: ChipHit: ASIC, FPGA, EDA Search Engine
    123158: 07/08/17: Re: ChipHit: ASIC, FPGA, EDA Search Engine
Ted:
    35157: 01/09/24: Re: comp.arch.fpga : Unusual clock divider ckt
    65049: 04/01/19: QUES: Where can I find Xilinx M1 tools
    65626: 04/02/03: QUES: ODFX/IDFX inferred in syplify, and not in XACT libraries ????
    70416: 04/06/15: C Header files for User Design Logic in the Nios.
    70476: 04/06/17: Re: C Header files for User Design Logic in the Nios.
    70477: 04/06/17: Re: C Header files for User Design Logic in the Nios.
    70527: 04/06/18: Re: C Header files for User Design Logic in the Nios.
    70672: 04/06/23: Re: C Header files for User Design Logic in the Nios.
    72261: 04/08/12: Quartus warning
    72601: 04/08/26: Re: JTAG software
    72605: 04/08/26: Xilinx Command Prompt
    74046: 04/10/02: Re: XPower help Update
    72850: 04/09/05: PCI Noise
    74014: 04/10/02: XPower help.
    72822: 04/09/03: Fanout Xilinx
    72950: 04/09/08: ISE 6.2 - Bug or folly?
    72991: 04/09/09: Re: ISE 6.2 - Bug or folly?
    73225: 04/09/16: Burning Questions- FPGA architecture, packing, LUTs....
    73259: 04/09/16: Re: Burning Questions- FPGA architecture, packing, LUTs....
    73260: 04/09/16: Routing Resources
    105390: 06/07/21: Re: Hardware book like "Code Complete"?
Ted Boydston:
    2131: 95/10/18: Chip Express Expreiences Wanted
    2168: 95/10/24: Chip Express Results...So Far
    2192: 95/10/30: Results of Chip Express Questions
    4583: 96/11/18: Re: VHDL adder: how do I get at the carry bit?
    4652: 96/11/26: Re: How to utilize XC4000e IOB FFs in Synopsys?
Ted Bronson:
    43133: 02/05/14: Altera/Quartus II: unconditional loop?
    43155: 02/05/14: Re: Altera/Quartus II: unconditional loop?
Ted Corbell:
Ted Lechman:
    62673: 03/11/04: help with 120MHz comparator
    66983: 04/03/02: Dongle compatibility
    67096: 04/03/05: Re: Dongle compatibility
    72856: 04/09/05: Re: PCI Noise
    72857: 04/09/05: Re: PCI Noise
    73614: 04/09/25: FPGA -> ASIC
    76095: 04/11/24: MIL-Qualified RTOS for uBlaze or NiosII
Ted Moreno:
    35148: 01/09/24: comp.arch.fpga : Unusual clock divider ckt
Ted Wood:
    18730: 99/11/10: Re: CAN tools reccomendations?
ted.franklin3@gmail.com:
    113129: 06/12/06: VHDL Variable Length Input file.
<ted.marena@latticesemi.com>:
    99761: 06/03/28: Re: Cyclone II EP2C70 dev kits, where are they?
<ted_buswell@yahoo.com>:
    157217: 14/11/04: Re: practical experience with GPL IP core in commercial product
<ted_jmt@zapta.com>:
    44331: 02/06/17: Seeking CPLD/FPGA recomendation
    44348: 02/06/18: Re: Seeking CPLD/FPGA recomendation
    44355: 02/06/18: Re: Seeking CPLD/FPGA recomendation
    44451: 02/06/20: Re: ISE Webpack Basics
    44900: 02/07/04: How to improve this VHDL code ?
    44901: 02/07/04: Please ignore my previous postings
Tedd Hadley:
    71091: 04/07/07: false paths, Synplify
TeddyM:
    106667: 06/08/16: Re: xilinx or altera?
Teece:
    115824: 07/02/21: Can someone give me some pointers on using ibis models?
    135567: 08/10/08: I need a good reference for VHDL
    137167: 08/12/29: How do I xor two signals in VHDL?
teen:
    82564: 05/04/14: tools used for ASIC synthesis
    82624: 05/04/14: Re: tools used for ASIC synthesis
    82625: 05/04/14: Soft CPU vs Hard CPU's
    82941: 05/04/19: Re: Soft CPU vs Hard CPU's
TehPron:
    135008: 08/09/10: Re: Can Soft microprocessor replace DSP's
TeikMing Goh:
    20458: 00/02/10: ROL VHDL operator.. need help!
    20531: 00/02/13: Logiblox Model failed in functional simulation by vhdldbx
    21771: 00/03/31: Synthesize components within a block using FPGA compiler
Teilnehmer Informatik I:
    7891: 97/10/27: Counter Problem
    9720: 98/04/01: Re: Altera Bitblaster or Byteblaster??
teixeira:
    139613: 09/04/07: Chipscope debug in EDK
<teixeirafms@gmail.com>:
    156169: 14/01/06: Re: Cyclone V hard memory controller
<tejaswyh@gmail.com>:
    132972: 08/06/11: PLB master : Split bus architecture
Teknomage:
    2618: 96/01/11: What exactly does an FPGA do?
    2621: 96/01/12: Re: What exactly does an FPGA do?
TEL:
tel:
Tel:
<tel2003@pathfinder.gr>:
    61724: 03/10/09: Re: Quartus II simulation question.
<TEL4 tel2003@pathfinder.gr, tel2003@popmail.com, tel4@ath.forthnet.gr>:
tel4@ath.forthnet.gr, tel2003@pathfinder.gr:
Telenochek:
    87754: 05/07/30: struggling with general digital design
    87794: 05/08/01: Bidirectional Bus problem with ModelSim.
    87795: 05/08/01: Re: struggling with general digital design
    89523: 05/09/17: Software tools for architectural diagrams and for timing diagram entry?
    89527: 05/09/17: Re: Software tools for architectural diagrams and for timing diagram entry?
    93409: 05/12/21: Buffers/Line drivers for 6pin JTAG?
    93421: 05/12/21: Re: Buffers/Line drivers for 6pin JTAG?
    102864: 06/05/22: Building a board with Spartan 3 FPGA.
    102868: 06/05/22: Re: Building a board with Spartan 3 FPGA.
    102872: 06/05/22: Re: Building a board with Spartan 3 FPGA.
    102873: 06/05/22: Re: Building a board with Spartan 3 FPGA.
    102886: 06/05/22: Re: Building a board with Spartan 3 FPGA.
    117705: 07/04/07: Xilinx ISE constanly asking to regenerate a core file.
    117708: 07/04/07: Re: Xilinx ISE constanly asking to regenerate a core file.
    121114: 07/06/26: Confused about FPGA devices recommended by Xilinx for my FFT project
    121136: 07/06/26: Re: Confused about FPGA devices recommended by Xilinx for my FFT project
    123040: 07/08/14: How to save simulation results in Xilinx ISE ?
    142923: 09/09/08: Traversing hierarchy in UCF works for OBUF, but not IOBUF, please
    142937: 09/09/09: Re: Traversing hierarchy in UCF works for OBUF, but not IOBUF, please
    142953: 09/09/09: Re: Traversing hierarchy in UCF works for OBUF, but not IOBUF, please
    142954: 09/09/09: Re: Traversing hierarchy in UCF works for OBUF, but not IOBUF, please
<teleporteur@my-deja.com>:
    27479: 00/11/23: fpga kit from kanda HELP !
temp:
    86923: 05/07/09: Re: Bit serial, book, other info???
Tempe Dele:
    55609: 03/05/13: Xilinx Coregen FFT64
    55798: 03/05/20: Re: Xilinx Coregen FFT64
tendy the:
    4399: 96/10/24: Integer Multiplier
tenteric:
    112810: 06/11/29: FPGA application field
    112813: 06/11/29: Re: FPGA application field
    112844: 06/11/29: Re: FPGA application field
    113338: 06/12/11: Give me job :)
Teo:
    80645: 05/03/09: Re: Differences among the FPGA development tools.
    80647: 05/03/09: Lattice's XP (flash + sram) fpga
    80816: 05/03/11: Re: Interfacing Compact Flash with Spartan 3
    80924: 05/03/14: Re: FPGA programming
    81328: 05/03/21: Re: TPS75003 for FPGAs
    81686: 05/03/29: Re: hook up SRAM to Spartan3
    81840: 05/04/01: Re: Parallelsignal at 85 MHz
    82115: 05/04/06: Re: Hey Xilinx
    83753: 05/05/06: Re: FPGA choice advice needed
    83756: 05/05/06: Re: FPGA choice advice needed
    83780: 05/05/06: Re: FPGA choice advice needed
    83845: 05/05/07: Re: Which chip should I use?
    83973: 05/05/10: Add on bus
    85477: 05/06/09: Re: DDR desing with FPGA
    85511: 05/06/10: Re: DDR desing with FPGA
    86230: 05/06/23: Re: Xilinx Powe Requirements V2PRO complaint
    87526: 05/07/25: Free 8 bit micro for fpga
    87637: 05/07/27: Re: isplever and GAL
    89737: 05/09/23: Re: Power Management for Xilinx and Altera FPGAs
    90753: 05/10/20: Re: which is Low power FPGA?
    97010: 06/02/14: Re: Altera EPLD
    97522: 06/02/23: Re: News from Embedded World in Nurnber
    97632: 06/02/24: Re: FPGA Selection Question
    121223: 07/06/28: Re: USB JTAG Programming
    121231: 07/06/28: Re: USB JTAG Programming
    127291: 07/12/17: Re: Xilinx MAC experience ?
    128576: 08/01/31: Re: About 10-bit pixel datum from CMOS image sensor
teo_80:
    77561: 05/01/11: use of JTAG pins
    77825: 05/01/18: Programming one page of an Altera configuration device
teodor:
    84028: 05/05/11: Re: RS 232 receiver using spartan 3 board
tepa:
    15629: 99/04/04: Help: Xilinx FPGA demonstration board and parallel cable iii doesn't work
    15636: 99/04/05: Re: Help: Xilinx FPGA demonstration board and parallel cable iii doesn't work
    15682: 99/04/08: Re: Help: Xilinx FPGA demonstration board and parallel cable iii doesn't work
Teppo Hemia:
    4205: 96/09/26: Partition tool for FPGAs?
terabits:
    112080: 06/11/15: USB and AHB
    112110: 06/11/16: Re: USB and AHB
    112119: 06/11/16: Re: USB and AHB
    112132: 06/11/16: Maximum Operating Frequency
    112183: 06/11/17: Re: USB and AHB
Terje Mathisen:
    10494: 98/05/24: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
    10498: 98/05/25: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU
    10505: 98/05/25: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
    10514: 98/05/26: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
    10520: 98/05/27: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
    10536: 98/05/28: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
    11453: 98/08/15: Re: Combinatoric Divide-by-3 Algorithm
    19535: 99/12/29: Re: An online division unit with constant divisor
    19608: 00/01/04: Re: An online division unit with constant divisor
    19635: 00/01/05: Re: An online division unit with constant divisor
    20937: 00/02/29: Re: Extremely fault tolerant strategies
    28286: 01/01/05: Re: Nondeterministic FSMs in hardware?
    29229: 01/02/10: Re: double precision floating point arithmetic
    29250: 01/02/11: Re: OT: IEEE & Floating point
    29264: 01/02/11: Re: double precision floating point arithmetic
    29289: 01/02/12: Re: double precision floating point arithmetic
    31798: 01/06/06: Re: FPU IEEE-754 calculation
    46528: 02/09/02: Re: Hardware Code Morphing?
    57574: 03/07/02: Re: Fixed point signed multiplication algorithm
    61782: 03/10/10: Re: Questions on Function Approximation (using FPGAs)
    82164: 05/04/07: Re: ISA vs. patent/trademark
    120404: 07/06/06: Re: Topics and Ideas for BS Project
    121218: 07/06/28: Re: Bit error counter - how to make it faster
Tero Rissa:
    60216: 03/09/08: Re: Compact FIR filters with multiplier blocks?
    61139: 03/09/29: Re: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
    61709: 03/10/09: Re: Compact FIR filters with multiplier blocks?
    63363: 03/11/20: Re: Memory Initialization: mif, coe, hex, etc,
    63752: 03/12/03: Re: Modelsim 5.8 corrupt call stack when adding signals to wave window.
    78228: 05/01/26: FPL 2005 - Call for Papers
<Terradestroyer@gmail.com>:
    85018: 05/06/02: Spartan 3 ata interface
    85075: 05/06/03: Re: re:Spartan 3 ata interface
    85289: 05/06/07: Re: Spartan 3 ata interface
    85440: 05/06/09: Re: Spartan 3 ata interface
    88553: 05/08/22: uDMA Hard drive interface - putting together multiple programs.
    88588: 05/08/23: Re: uDMA Hard drive interface - putting together multiple programs.
    88612: 05/08/23: Re: uDMA Hard drive interface - putting together multiple programs.
    88647: 05/08/24: Drive startup mode - PIO write problems from FPGA
    88704: 05/08/25: Re: Drive startup mode - PIO write problems from FPGA
    88718: 05/08/25: Re: Drive startup mode - PIO write problems from FPGA
    91497: 05/11/07: looking for FPGA pin header board
    91550: 05/11/08: Re: looking for FPGA pin header board
Terrence Mak:
    34628: 01/09/01: Re: JTAG issue again ...
    34629: 01/09/01: Re: Jbits: more info required
    34699: 01/09/04: ISE vs Foundation
    34756: 01/09/06: Re: Xilinx design flow
    35344: 01/09/30: about JBits
    39434: 02/02/09: beside System Generator
    44926: 02/07/06: Problems on using JBits
    50660: 02/12/16: VirtexII Pro question
    50661: 02/12/16: Virtex2Pro question
    53253: 03/03/08: Re: best way to read/write contents of BRAM to a file during simulation?
    56590: 03/06/10: System generator and Virtex2Pro Design
    56715: 03/06/12: SystemC and ISE
    62738: 03/11/06: Virtex2Pro--ppc405-FPGA communication
    64409: 04/01/02: Virtex2Pro + SysGen
    66728: 04/02/26: powerpc
    66915: 04/03/01: embedded powerpc in VirtexII-pro
    66953: 04/03/02: Re: cpu time of the computation
    67450: 04/03/12: Re: Virtex 2 P -> PPC write to block RAM
    76162: 04/11/27: microblaze using SysGen
    77353: 05/01/05: SysGen installation problem
terry:
    72147: 04/08/09: Differences between FPGA & CPLD
Terry:
    39422: 02/02/08: Schematic Entry in Xilinx ISE 4.1i
    40427: 02/03/07: Re: Quartus II 2.0 fast fit option
    41531: 02/04/01: Configuring the Virtex II FPGA
    59475: 03/08/20: Xilinx XC3000 with Xilinx ISE student edition 4.2i
    59576: 03/08/22: Re: Xilinx XC3000 with Xilinx ISE student edition 4.2i
    59871: 03/08/31: Xilinx Foundation Series 2.1i on Linux
Terry Andersen:
    58780: 03/08/01: Speed Grade...
    60269: 03/09/09: EMAC in EDK...
    60313: 03/09/10: DDR in EDK 3.2sp2...
    60411: 03/09/12: Error when downloading with EDK
    60412: 03/09/12: Re: EMAC in EDK...
Terry Bailey:
    1967: 95/09/26: NEW person
Terry Brown:
    100989: 06/04/23: Re: More Xilinx S/W problems... ISE won't start
    103151: 06/05/26: Re: Independent clock FIFOs
    103188: 06/05/27: Re: Independent clock FIFOs
    106310: 06/08/11: Re: TIG on Xilinx Asynch FIFO?
    114942: 07/01/27: Re: Timing Diagram Tool
    153900: 12/06/28: Replacement for XC4005E
    153912: 12/06/29: Re: Replacement for XC4005E
    153914: 12/06/29: Re: Replacement for XC4005E
Terry Chevalier:
    582: 95/01/11: PCB design with Xilinx
Terry E. Koontz:
    1070: 95/04/24: Sunrise ???
Terry Fowler:
    89418: 05/09/14: Re: Microblaze & Memory DMA operation
    89515: 05/09/16: Re: Microblaze & Memory DMA operation
    90993: 05/10/26: Re: Microblaze & Memory DMA operation
    91036: 05/10/27: Re: Microblaze & Memory DMA operation
Terry Fraser:
    11200: 98/07/24: Re: Xilinx Dynatext and NTFS ?
    14213: 99/01/20: Secondary clock nets in Xilinx Virtex
    16803: 99/06/09: Simultaneous switching outputs in Xilinx Spartan XL
Terry Given:
    84915: 05/06/01: Re: need a book: Hilbert transform
    84946: 05/06/02: Re: need a book: Hilbert transform
    85011: 05/06/03: Re: need a book: Hilbert transform
    95391: 06/01/23: Re: OT:Shooting Ourselves in the Foot
    95501: 06/01/24: Re: OT:Shooting Ourselves in the Foot
    95507: 06/01/24: Re: OT:Shooting Ourselves in the Foot
    115337: 07/02/08: Re: question about power dissipation
    128496: 08/01/29: Re: effect of xray on fpga electronic circuits
Terry Graessle:
    8019: 97/11/07: Re: Where can I find documents talking about constraining FPGA?
    8101: 97/11/17: Re: Xilinx Logiblox in Synopsys
    8210: 97/11/28: Re: Gigaops Reconfiguration board
    7988: 97/11/05: Re: interface between FPGA & user?
    8270: 97/12/04: Re: Integration between Xilinx & Synopsys
    8651: 98/01/16: Re: Using Xiling schematic library macro from VHDL
Terry Harris:
    6154: 97/04/18: Re: Pentium Pro Worth it for Altera Max Plus?
    6692: 97/06/15: Re: Don't Design With Altera Parts... Altera Obsolete Parts
    6929: 97/07/09: Re: Generating Sine/Cosine digitally
    7148: 97/08/07: Re: MEM_CS16 timing on ISA BUS
    7189: 97/08/12: Re: Any one getting 125MHz out of XILINX CPLDs?
    7195: 97/08/13: Re: Any one getting 125MHz out of XILINX CPLDs?
    7271: 97/08/20: Re: ISP Stories
    7292: 97/08/22: Re: ISP Stories
    7291: 97/08/22: Re: ISP Stories
    8581: 98/01/11: Re: Xilinx Stock
    8614: 98/01/13: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    11824: 98/09/11: Re: Cypress CPLD Jam Player
    13653: 98/12/16: Re: Fast *Industrial* 22V10?
    13663: 98/12/17: Re: Fast *Industrial* 22V10?
    13677: 98/12/18: Re: Fast *Industrial* 22V10?
    13681: 98/12/18: Re: Fast *Industrial* 22V10?
    13786: 98/12/28: Re: 22V10 Metastability - help please
    13874: 98/12/30: Re: 22V10 Metastability - help please
    13888: 98/12/31: Re: 22V10 Metastability - help please
    14987: 99/03/02: Re: ALTERA pin assignment
    15930: 99/04/21: Lattice buys Vantis
    23254: 00/06/19: Re: Hand soldering a PQ208 - It looks tough to do.
Terry Herter:
    46110: 02/08/19: Stratix Experience
    51488: 03/01/14: Off Topic: Single Board Computers?
    51498: 03/01/14: Re: Off Topic: Single Board Computers?
Terry Hicks:
    27344: 00/11/18: Re: Microprocessor Verilog/VHDL Models
    27857: 00/12/12: Re: Fpga Newbie
    28554: 01/01/16: Re: Virtex-II officially launched
    28603: 01/01/17: FAQ for this news group? (or What is an FPGA?)
    28984: 01/01/31: Re: 64-bit counter @ 200 MHz on FPGA?
    29038: 01/02/02: Re: Encryption is supported in new Virtex II but.....
    29043: 01/02/03: sorry: Encryption is supported in new Virtex II but.....
    29044: 01/02/03: Re: Help for a novice. Where to begin?
Terry Koontz:
    975: 95/04/06: Synopsys design_analyzer Problem
Terry L. Zumwalt:
    10838: 98/06/24: Re: AHDL vs. VHDL vs. Verilog HDl
    10875: 98/06/26: Re: Free Computer (Read--Easy, No money down)
Terry Mayhugh:
    470: 94/11/28: Re: Any one with i_Logix experience?
Terry Newton:
    44547: 02/06/23: Re: Xilinx's 4.1i's Lastest webpack
    49434: 02/11/12: Re: new to fpga, what language is better to start with
    49488: 02/11/13: Re: new to fpga, what language is better to start with
Terry Payman:
    67498: 04/03/12: Re: anyone using nios kit APEX?
Terry Ragsdale:
    6337: 97/05/16: Re: VHDL or Verilog?
Terry Spoon:
    6304: 97/05/12: Gatefield FPGA Design Experiences
Terry Walters:
<terry@norpak.ca>:
    136170: 08/11/04: ALTERA ALT2GXB RECONFIG BLOCK
tersono:
    109331: 06/09/24: Balanced inputs on Spartan3E
    113541: 06/12/15: Xilinx WebPack 8.2.03i: can't make .bit file when memories used in design
    113580: 06/12/17: Re: Frequency divider?
    113857: 06/12/26: Re: moving from xlinx 8.1 to 8.2 or better wait ?
    113926: 06/12/29: Re: moving from xlinx 8.1 to 8.2 or better wait ?
    113973: 06/12/31: Re: SPI slave problem
    118596: 07/04/30: Re: Please help me fast !!!!!
    120532: 07/06/08: Re: Newbie Question: Using Includes in Verilog
    123373: 07/08/25: A beginner asks questions about synthesis under Xilinx XST
    123379: 07/08/26: Re: A beginner asks questions about synthesis under Xilinx XST
    128348: 08/01/22: Re: Ballistic chronograph using a Spartan 3E starter board
    134530: 08/08/16: A timing question
    134556: 08/08/18: Re: A timing question
Tesisti DSPLab:
    27826: 00/12/11: ERROR: The net has more than one driver?
tesla:
    78771: 05/02/07: usb 2.0 micromodule
    78896: 05/02/09: Re: usb 2.0 micromodule
    109078: 06/09/20: Re: MicroFpga = program an FPGA as it would be a MCU !
test:
    20927: 00/02/28: XABEL State Machines?
    21159: 00/03/08: Logiblox from ABEL?
    22080: 00/04/19: Test : Please ignore...
    73937: 04/10/01: Re: Evaluation Board for Xilinx Virtex
    130485: 08/03/25: MP7 and Actel Fusion FPGA
Test:
    47139: 02/09/18: Xilinx Spartan II PIN Status?
    135954: 08/10/23: Need Lattice FUSE TABLE --->> LOGIC conversion service. $$$
Test01:
    118081: 07/04/17: Re: FPGA High speed Transceivers for source synchronus bus
    118311: 07/04/23: V5 GTP question
    118342: 07/04/24: Re: V5 GTP question
    118396: 07/04/25: Re: V5 GTP question
    118576: 07/04/30: Re: V5 GTP question
    118891: 07/05/06: V5 LVPECL Inputs
    118913: 07/05/07: Re: V5 LVPECL Inputs
    118914: 07/05/07: Re: V5 LVPECL Inputs
    118916: 07/05/07: V5 GTP Transceivers supporting LVPECL
    118918: 07/05/07: Re: V5 LVPECL Inputs
    118919: 07/05/07: Re: V5 LVPECL Inputs
    118932: 07/05/07: Re: V5 LVPECL Inputs
    118966: 07/05/08: Re: V5 LVPECL Inputs
    118982: 07/05/08: Re: V5 LVPECL Inputs
    119076: 07/05/10: V5 serial link
    119295: 07/05/16: CML output swing for V5
    119318: 07/05/16: Re: SERDES question (Lattice ispHSI)
    119573: 07/05/22: LVCMOSS33 I/O sink current
    119589: 07/05/23: Re: LVCMOSS33 I/O sink current
    119657: 07/05/24: Re: CML output swing for V5
    119803: 07/05/26: Spartan3 LVCMOS33 Slew rate
    119807: 07/05/26: Re: Spartan3 LVCMOS33 Slew rate
    119814: 07/05/26: Re: Spartan3 LVCMOS33 Slew rate
    119816: 07/05/26: Re: Spartan3 LVCMOS33 Slew rate
    119817: 07/05/26: Re: Spartan3 LVCMOS33 Slew rate
    119823: 07/05/26: Re: Spartan3 LVCMOS33 Slew rate
    119830: 07/05/27: Re: Spartan3 LVCMOS33 Slew rate
    119838: 07/05/27: Re: Spartan3 LVCMOS33 Slew rate
    119843: 07/05/27: Re: Spartan3 LVCMOS33 Slew rate
    119857: 07/05/28: Re: Spartan3 LVCMOS33 Slew rate
    119858: 07/05/28: Re: Spartan3 LVCMOS33 Slew rate
    119922: 07/05/29: Re: Spartan3 LVCMOS33 Slew rate
    119930: 07/05/29: Re: Spartan3 LVCMOS33 Slew rate
    119945: 07/05/29: Re: Spartan3 LVCMOS33 Slew rate
    120006: 07/05/30: 180 differential inputs each 800Mbps using V5
    120070: 07/05/31: Re: 180 differential inputs each 800Mbps using V5
    120151: 07/06/01: Re: 180 differential inputs each 800Mbps using V5
    120158: 07/06/01: Re: 180 differential inputs each 800Mbps using V5
    120169: 07/06/02: Re: 180 differential inputs each 800Mbps using V5
    120177: 07/06/02: Re: 180 differential inputs each 800Mbps using V5
    120181: 07/06/02: Re: 180 differential inputs each 800Mbps using V5
    120191: 07/06/02: Re: 180 differential inputs each 800Mbps using V5
    120195: 07/06/02: Re: 180 differential inputs each 800Mbps using V5
    120198: 07/06/02: Re: 180 differential inputs each 800Mbps using V5
    120209: 07/06/03: Re: 180 differential inputs each 800Mbps using V5
    120341: 07/06/05: svf file programming issue
    120420: 07/06/06: How many OSERDES per bufio
    141273: 09/06/15: How to convert from 2x data rate signals to 1x data rate signals
    141284: 09/06/15: Re: How to convert from 2x data rate signals to 1x data rate signals
    141381: 09/06/22: Question on FPGA driver
    141385: 09/06/22: Re: Question on FPGA driver
    141392: 09/06/22: Re: Question on FPGA driver
    141393: 09/06/22: Re: Question on FPGA driver
    142449: 09/08/11: Is it possible to use OSERDES and ISERDES primitives internal to
    142452: 09/08/11: Re: Is it possible to use OSERDES and ISERDES primitives internal to
    142473: 09/08/12: Re: Is it possible to use OSERDES and ISERDES primitives internal to
    142503: 09/08/13: Re: Is it possible to use OSERDES and ISERDES primitives internal to
    142519: 09/08/14: Is it possible to generate double data rate stream in the Virtex4
    142522: 09/08/14: Re: Is it possible to generate double data rate stream in the Virtex4
    142595: 09/08/19: Emulation of highly complex superscaler processor using FPGAs
    143405: 09/10/09: ASIC Prototyping using FPGA
    143498: 09/10/13: Re: ASIC Prototyping using FPGA
    143542: 09/10/15: Re: ASIC Prototyping using FPGA
    143904: 09/11/02: Inter FPGA communication bus for Cypress Ez USB device
    144180: 09/11/17: Avalon-ST to Avalon-MM Bridge
    144191: 09/11/18: Re: Avalon-ST to Avalon-MM Bridge
    144197: 09/11/19: Avalon-ST to Avalon-MM Bridge
    144198: 09/11/19: AvalonST to Avalon MM Bridge
    144201: 09/11/19: Re: AvalonST to Avalon MM Bridge
    144224: 09/11/20: Re: AvalonST to Avalon MM Bridge
    144875: 10/01/11: How to gracefully terminate the PCIe read request
    144886: 10/01/12: Re: How to gracefully terminate the PCIe read request
    145505: 10/02/12: Why is following Verilog code snipper considered a Latch
    145511: 10/02/12: Re: Why is following Verilog code snipper considered a Latch
    145721: 10/02/20: Question about altera root-port for Stratix4GX Hard IP
    148204: 10/06/28: Altera Stratix4GX PCIe card as a root-port
    152451: 11/08/23: FPGA based PCIe Gen3 Endpoint question
    152610: 11/09/18: How to digitize the VGA output using FPGA?
    152612: 11/09/18: Re: How to digitize the VGA output using FPGA?
    152613: 11/09/18: Re: How to digitize the VGA output using FPGA?
    152664: 11/09/25: FPGA + TVP70025i Board
    153108: 11/12/02: Is it possible to save the FPGA state periodically?
    153110: 11/12/02: Re: Is it possible to save the FPGA state periodically?
tester:
    104436: 06/06/27: Montavista linux Xilinx Virtex4 ML403
    104519: 06/06/29: Problem to extend Xilinx GSRD Design
    104644: 06/07/03: Re: Problem to extend Xilinx GSRD Design
Tetsuo HIRONAKA:
    8804: 98/01/28: [CFP] The Sixth FPGA/PLD Design Conference & Exhibit (Deadline 2/6)
    8874: 98/02/04: Re: [CFP] The Sixth FPGA/PLD Design Conference & Exhibit (Deadline 2/6)
    10673: 98/06/10: CFPP:The Sixth Japanese FPGA/PLD Design Conference & Exhibit 6/24-6/26
    12849: 98/11/02: [CFP] The Seventh Japanese FPGA/PLD Conf. & Exhibit (July 7-9, 1999)
    13548: 98/12/09: [CFP] The Seventh Japanese FPGA/PLD Conf. & Exhibit (June 30 - July 1, 1999)
Teun Docter:
    7557: 97/09/22: cpld and fpga help needed
<tgallati@hotmail.com>:
    18702: 99/11/08: Altera Releases First in New Line of PLDs
tgarrel:
    9236: 98/03/04: Re: Survey - Proto Board for Xilinx FPGA
<tgau3qk4@gmail.com>:
    133920: 08/07/19: Howto disable Quartus infering M4Ks??
    134015: 08/07/22: Re: Howto disable Quartus infering M4Ks??
    134017: 08/07/22: help me improve this simple function
    134435: 08/08/10: Re: help me improve this simple function
    134436: 08/08/10: Re: help me improve this simple function
<tgg@hpl.hp.com>:
    12840: 98/11/01: Re: New free FPGA CPU
    12945: 98/11/06: Re: New free FPGA CPU
<tgg@hplb.hpl.hp.com>:
    3249: 96/05/03: Re: SILAGE
<tgingold@pc204.ipricot.fr>:
    35935: 01/10/24: Re: Verilog vs. VHDL
<tgingold_nospam@yahoo.com>:
    84612: 05/05/23: Re: GHDL under x86_64 Linux
<tgschwind@tiscalinet.ch>:
    102927: 06/05/23: Re: ISE 8.1SP4 PN doesnt start
    114354: 07/01/12: Re: Too many warnings in Modelsim?
    123269: 07/08/22: Power Reduction Strategy
Thad Smith:
    2110: 95/10/16: Re: Bet you can't do these....
    58673: 03/07/30: Re: PLL / DPLL phase question
    58691: 03/07/30: Re: PLL / DPLL phase question
    58761: 03/08/01: Re: PLL / DPLL phase question
    58762: 03/08/01: Re: PLL / DPLL phase question
    58788: 03/08/01: Re: PLL / DPLL phase question
    58822: 03/08/01: Re: PLL / DPLL phase question
    63592: 03/11/25: Re: Soft-core processor construction
    81908: 05/04/04: Re: problem in driving I2C bus through memory-mapped register
    92351: 05/11/28: Re: ADC keeps outputting negative numbers, how?
    130414: 08/03/22: Re: A Challenge for serialized processor design and implementation
<Thaisextours@vklblosn.com>:
    15107: 99/03/07: ThaiSexHolidays
Thales Belchior:
    71192: 04/07/11: Xact 4.12 or 5.0
    71194: 04/07/11: Re: Is the Xilinix XC3020 atill supported?
Thales2:
    149900: 10/12/01: Help for a embeded system with SPARTAN-6 project
Thanaporn:
    79835: 05/02/24: Using XBERT(XAPP661) with EDK6.3SP1
Thanassis Roubies:
    59430: 03/08/19: Xilinx Parallel Cable III Schematic
    59886: 03/08/31: Parallel Cable III Problems
THANG NGUYEN:
    109708: 06/10/03: Virtex-II Pro Platform FPGA : Assembling the modules
    109721: 06/10/04: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    109722: 06/10/04: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    109750: 06/10/04: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    109770: 06/10/05: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    109832: 06/10/05: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    109873: 06/10/06: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    109874: 06/10/06: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    109875: 06/10/06: Re: Virtex-II Pro Platform FPGA : Assembling the modules
Thang Nguyen:
    110250: 06/10/12: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    110350: 06/10/14: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    110369: 06/10/14: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    110569: 06/10/17: Re: Virtex-II Pro Platform FPGA : Assembling the modules
    111870: 06/11/12: EDK : path set
    111884: 06/11/12: Re: EDK : path set
    112017: 06/11/14: EDK: command not found
    112018: 06/11/14: Software Compile : gcc command not found
    113494: 06/12/14: Port OS: Error when generate the Libraryies and BSPs
    113598: 06/12/17: ERROR:MDT - ERROR FROM TCL:- linux_mvl31 ()
    116188: 07/03/03: EDK 8.1i : add port for component
    116189: 07/03/03: Re: EDK 8.1i : add port for component
    116190: 07/03/03: Re: EDK 8.1i : add port for component
    116196: 07/03/04: Re: EDK 8.1i : add port for component
thangkho:
    67824: 04/03/19: Virtex-E IOB programmable delay
    67909: 04/03/22: Re: Virtex-E IOB programmable delay
    68062: 04/03/25: Re: CPLD: assign pins first, or design content first?
    68231: 04/03/30: Re: Is there any Sync separator IP(Intellectual property) exists?
    69550: 04/05/13: Re: V2p block ram clock -> Q delay help
    69916: 04/05/24: Re: How to select an FPGA size (beginner)
    70396: 04/06/15: Re: >Math Skills = >Engineer ?
    74915: 04/10/21: Re: interfacing a PC based program with a FPGA
    75552: 04/11/09: Re: SDRAM sustained bursts
    81640: 05/03/29: ISE 6.3 sp3 - PAR result strange
    81775: 05/03/31: Re: One or two DLLs for a SDRAM controller?
thankfo:
    71575: 04/07/22: Re: Open Collector Circuit - How to Simulate?
thao:
    35584: 01/10/11: Error : Operand divide
<thaynes@pacbell.net>:
    15171: 99/03/10: ASIC Verification Engineer NEDDED! Trattner Patrick Lowney
The ATM man:
    22224: 00/05/02: VDHL and ASIC people
    22232: 00/05/02: Re: VDHL and ASIC people
The Bearded Dave:
    13132: 98/11/16: Re: DES in VHDL
    13268: 98/11/22: RE: DES in VHDL
The Big Bear:
    62692: 03/11/04: FPGA Prototyping Board
    62723: 03/11/05: Re: FPGA Prototyping Board
The Big Lebowski:
    104593: 06/06/30: Re: How to comm with Altera JTAG UART (from custom host software)?
The Eighth Doctor:
    81276: 05/03/21: PAL problems (again)
    81308: 05/03/21: Re: PAL problems (again)
    81394: 05/03/22: Re: PAL problems (again)
The Elftmanns:
    22865: 00/05/28: Re: STD_LOGIC_VECTOR problem.....
The Employment Solution:
    11081: 98/07/17: FPGA Designers ?????
    11094: 98/07/18: FPGA Designer
    11445: 98/08/14: FPGA Designer
    11446: 98/08/14: BIG MONEY !!!!!!
the Geez:
    43184: 02/05/15: Re: Exemplar in ISE
The IRS:
    21952: 00/04/08: top50 keywords january - february - march...
The Lord of War:
    141669: 09/07/02: how to use ram or memory
    141673: 09/07/03: Re: how to use ram or memory
    141698: 09/07/03: Re: how to use ram or memory
    141706: 09/07/04: Re: how to use ram or memory
    141718: 09/07/04: Re: how to use ram or memory
    141723: 09/07/04: Re: how to use ram or memory
The Mighty Shaman:
    104428: 06/06/27: XilFatFS and CF...
The Other Guy:
    99510: 06/03/26: C-based FPGA programming/mixed languages
    99682: 06/03/28: Re: C-based FPGA programming/mixed languages
The PeopleWeb Inc.:
    29907: 01/03/16: Senior I/O Designer - Canada
    29908: 01/03/16: ASIC Designer
    29909: 01/03/16: Graphics Board Design Engineers
    29910: 01/03/16: ASIC Continuation Engineer
    29911: 01/03/16: Senior Engineer, Process & Technology
    29912: 01/03/16: Senior Engineer, Physical Design
    29913: 01/03/16: Senior Memory IC Designer
    29914: 01/03/16: DV (Design Verification) Engineers
The POLIS team:
    4714: 96/12/05: Announcement: public release of POLIS-0.2, an embedded system design software
    4738: 96/12/09: Repost: Announcement: public release of POLIS-0.2, an embedded system
The Real Bev:
    62812: 03/11/07: Re: Programmer's unpaid overtime.
The Right Reverend <name withheld by request>:
    1528: 95/07/09: QLogic FAS246 info?
The Vincer:
    3977: 96/08/28: DO I REALLY NEED A XCHECKER CABLE?
<the.gaffar@googlemail.com>:
    96968: 06/02/14: XPower report precision
    96988: 06/02/14: Re: XPower report precision
    96994: 06/02/14: Re: XPower report precision
    96998: 06/02/14: Re: XPower report precision
    103457: 06/06/02: Changing the random seed in Xilinx tools
<theanonymous83@gmail.com>:
    124640: 07/09/28: [offtopic] job inquiry; entry/trainee FPGA/ASIC designer
    124664: 07/09/29: Re: job inquiry; entry/trainee FPGA/ASIC designer
thecreator:
    135989: 08/10/25: linux usb-drivers: Cable connection failed.
TheDoc:
    75000: 04/10/23: Re: Looking for FPGA design services in India or similar
    95475: 06/01/23: Re: OT:Shooting Ourselves in the Foot
TheGlimmerMan:
    149648: 10/11/12: Re: cool BGA pattern
<theidel@advis.de>:
    23935: 00/07/16: Re: Looking for 'FREE' FPGA software
<theidel@my-deja.com>:
    23934: 00/07/16: Re: Looking for 'FREE' FPGA software
    23945: 00/07/17: Re: Looking for 'FREE' FPGA software
thejay:
    104915: 06/07/09: Is while loop synthesizable if the number of iterations is known
TheMightyShaman:
    79800: 05/02/24: Re: 2 microblaze access same BRAM ?
    79857: 05/02/25: Re: 2 microblaze access same BRAM ?
    80073: 05/03/01: Re: 2 microblaze access same BRAM ?
    80078: 05/03/01: Re: 2 microblaze access same BRAM ?
    80172: 05/03/02: Re: 2 microblaze access same BRAM ?
    83237: 05/04/26: Re: DDR SODIMM on Avnet Virtex II PRO development kit
    83609: 05/05/03: Re: DDR SODIMM on Avnet Virtex II PRO development kit
    104634: 06/07/03: Re: XilFatFS and CF...
Theo:
    43079: 02/05/13: Virtex-II DCM Frequency Synthesis
    46450: 02/08/30: Virtex-II partial reconfiguration flow diagram
Theo Markettos:
    50790: 02/12/19: Re: State of the PCB world
    50894: 02/12/22: Re: State of the PCB world
    142408: 09/08/10: Re: AES encryption of bitstream - is my design secure?
    144154: 09/11/14: OT: Moderator Vacancy Investigation: comp.arch.hobbyist
    154992: 13/03/22: Re: Using Quartus II without GUI
    155137: 13/04/25: Re: Modelsim ought to be cheaper
    155183: 13/05/24: Re: Development/Experimenter's kits
    155191: 13/05/24: Re: Development/Experimenter's kits
    155214: 13/06/10: Re: A Question about FPGA IO Standard
    155227: 13/06/14: Re: New soft processor core paper publisher?
    155229: 13/06/14: Re: New soft processor core paper publisher?
    155256: 13/06/19: Re: Chasing Bugs in the Fog
    155431: 13/06/28: Re: New soft processor core paper publisher?
    155514: 13/07/13: Re: Low cost board with built-in USB for fast data transfer and lots of gates
    155578: 13/07/23: Re: Nios II problem with DDR core SOPC builder
    155583: 13/07/24: Re: Nios II problem with DDR core SOPC builder
    155588: 13/07/24: Re: Nios II problem with DDR core SOPC builder
    155622: 13/07/30: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155677: 13/08/02: Re: NiosII 8.0 make error Windows XP
    155693: 13/08/06: Re: NiosII 8.0 make error Windows XP
    156046: 13/11/13: Re: Qsys and clock crossings
    156058: 13/11/16: Re: Cyclone V hard memory controller
    156093: 13/11/22: Re: FPGA Cryptosystem
    156253: 14/01/24: Re: chip-to-chip serial comms
    156440: 14/04/06: Re: Tristates in synthesis
    156493: 14/04/10: Re: on-chip bypass caps
    156516: 14/04/14: Re: Actel Designer on multiple cores
    156527: 14/04/15: Re: Help: Altera megafunctions, Quartus II
    156552: 14/04/23: Re: JTAG issues Cyclone V SoC
    156579: 14/05/04: The USB FPGA?
    156589: 14/05/06: Re: The USB FPGA?
    156594: 14/05/07: Re: The USB FPGA?
    156678: 14/06/03: Re: Linux driver for Xilinx axi_10g_ethernet_0_ten_gig_eth_mac core?
    156742: 14/06/11: Re: 22V10 programmer
    156754: 14/06/18: Re: PLA? PAL? PLD? GAL?
    156932: 14/07/30: Re: Primitive debuggable UART interface to a Nios within a multi-Nios system
    156973: 14/08/09: Re: LVDS problem - Black magic anyone?
    156984: 14/08/11: Re: LVDS problem - Black magic anyone?
    156992: 14/08/13: Re: LVDS problem - Black magic anyone?
    157124: 14/10/15: Re: Need ideas for FYP
    157127: 14/10/16: Re: Need ideas for FYP
    157137: 14/10/17: Re: Need ideas for FYP
    157203: 14/11/04: Re: Quartus II TCL or Command line
    157350: 14/11/26: Low-end FPGA mezzanine standard
    157353: 14/11/27: Re: Low-end FPGA mezzanine standard
    157358: 14/11/27: Re: Low-end FPGA mezzanine standard
    157359: 14/11/27: Re: Low-end FPGA mezzanine standard
    157364: 14/11/28: Re: Low-end FPGA mezzanine standard
    157374: 14/12/02: Re: Which Altera to buy?
    157381: 14/12/02: Re: Which Altera to buy?
    157388: 14/12/02: Re: Which Altera to buy?
    157389: 14/12/03: Re: Which Altera to buy?
    157390: 14/12/03: Re: Which Altera to buy?
    157423: 14/12/04: Re: Which Altera to buy?
    157486: 14/12/12: Re: Which Altera to buy?
    157487: 14/12/12: Re: Which Altera to buy?
    157489: 14/12/12: Re: Monitor connections
    157491: 14/12/12: Re: Using FPGA to feed 80386
    157577: 14/12/17: Re: Monitor connections
    157616: 15/01/06: Re: Low-end FPGA mezzanine standard
    157629: 15/01/08: Re: Timing Constraints: are there any "design patterns" indicating good practice?
Theodor Calin:
    7911: 97/10/29: Polynomial division tool for LFSR/MISR simulation
theom:
    143068: 09/09/18: Re: xc3sprog
<theonlysim@yahoo.com>:
theosib@gmail.com:
    127044: 07/12/10: keep_hierarchy attribute equivalent for Lattice/Synplicity?
    127056: 07/12/10: Re: keep_hierarchy attribute equivalent for Lattice/Synplicity?
    127081: 07/12/11: Re: keep_hierarchy attribute equivalent for Lattice/Synplicity?
thepiper:
    142162: 09/07/27: PAR runs successfully, simulation fails
Theron Hicks:
    18741: 99/11/11: fast programmable divider using xilinx xc4002xl
    18933: 99/11/22: Re: PADS Experience?
    19269: 99/12/09: EEPROM for spartan xl series FPGA?
    20141: 00/01/28: Re: LVPECL I/O interface
    20142: 00/01/28: Re: LVPECL I/O interface
    20622: 00/02/16: loading FPGA from PROM's? file type?
    21548: 00/03/24: Re: FPGA openness
    21549: 00/03/24: Re: FPGA openness
    21551: 00/03/24: Re: FPGA openness
    22173: 00/04/28: Re: xilinx prom 2nd source.
    22197: 00/05/01: Re: Why are there no "cheap" FPGAs?
    22223: 00/05/02: Re: Why are there no "cheap" FPGAs?
    22265: 00/05/03: Re: new2fpga
    22434: 00/05/09: Re: Programming FPGA
    23293: 00/06/21: Re: Problem copying text from the Spartan II data sheet
    24575: 00/08/14: Re: Virtex 2.5V part with 5V IO problems
    24577: 00/08/14: Re: what does 0.35 micron mean
    24726: 00/08/17: Re: When will SpartanII be in ditribution
    25332: 00/09/06: Re: 3.3/2.5 voltage regulators
    25376: 00/09/08: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
    25943: 00/09/27: Re: SV: hdl
    26237: 00/10/09: Re: Analogue FPGAs ?
    26647: 00/10/23: Re: Very Lucrative FPGA Jobs
    27210: 00/11/15: .mif and .coe files in coregen vs. green mountain 68hc11
    27306: 00/11/17: COREGEN ROM in VHDL... How do I use it?
    27380: 00/11/20: initialization of ROM contents in COREGEN part
    27462: 00/11/22: Re: Power consumption FPGA...
    27518: 00/11/27: Re: COREGEN ROM in VHDL... How do I use it?
    27884: 00/12/13: really fast counter in SpartanXL?
    28072: 00/12/20: Re: really fast counter in SpartanXL? THANKS!
    28504: 01/01/15: Re: grey code counters
    28722: 01/01/22: VirtexII and high speed counter
    28820: 01/01/25: Re: Spartan-II serial vs. parallel configuration
    31760: 01/06/05: selection of software for xilinx devices
    35087: 01/09/20: Maximum clock rate of various Xilinx families?
    35093: 01/09/20: Re: Maximum clock rate of various Xilinx families?
    35361: 01/10/01: bufgmux in virtex2 not found
    35413: 01/10/03: Re: error from BUFGMUX in ModelSim?? Sorry wrong address...
    35505: 01/10/08: virtex2 simulation and modelsim_xe/starter 5.5b
    35548: 01/10/10: contract assembler for BGA based board???
    35599: 01/10/11: DCM simulation results do not match part spec's
    35658: 01/10/12: Re: future Xilinx products wish list ...
    35782: 01/10/17: simple question
    35810: 01/10/18: Re: simple question
    35982: 01/10/25: Re: How to make an implementable big counter?
    36701: 01/11/16: Re: High Speed PWM?
    36802: 01/11/20: Re: Modelsim
    36811: 01/11/20: don't cares and X's in a case statement?
    36937: 01/11/26: Re: Device Support in Webpack
    37010: 01/11/28: Re: don't cares and X's in a case statement?
    37150: 01/12/01: problem with manual floorplanner
    37523: 01/12/13: Re: How to use the CoreGen hdl code within my source?
    38696: 02/01/22: Re: help me!
    38704: 02/01/22: analog input via serial connection
    38708: 02/01/22: Re: analog input via serial connection
    38945: 02/01/28: glitchless clock enable/disable in spartanII
    38980: 02/01/29: Re: glitchless clock enable/disable in spartanII
    38981: 02/01/29: Re: glitchless clock enable/disable in spartanII
    38990: 02/01/29: dll error message in ModelSim XE/Starter 5.5b
    39213: 02/02/04: par and carry chains not allowing manual floorplanning
    39227: 02/02/04: Re: par and carry chains not allowing manual floorplanning
    39415: 02/02/08: Re: NT parallel port driver ...Any serial NT drivers?
    39416: 02/02/08: Modelsim questions
    39509: 02/02/12: fifo in coregen? Xilinx (ise4.1) is screwed up!
    39518: 02/02/12: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
    39766: 02/02/19: Re: SpartanXL & VHDL -- free software?
    39767: 02/02/19: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
    39784: 02/02/19: spartan2 clock input from LVPECL signals
    39864: 02/02/21: Re: Here is an argument and can anyone help me out
    39865: 02/02/21: Xilinx (ise4.1) is screwed up! SCREAM LOUD!!
    39872: 02/02/21: Re: Here is an argument and can anyone help me out
    39873: 02/02/21: EDIF IN A VHDL PROJECT (kcpsm.edn) in ISE4.1
    39874: 02/02/21: Re: Using a CoreGen component
    39877: 02/02/21: Re: Using a CoreGen component
    39978: 02/02/22: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
    40037: 02/02/25: Re: EDIF IN A VHDL PROJECT (kcpsm.edn) in ISE4.1
    40448: 02/03/07: Re: Rising and falling edge of a clk
    40594: 02/03/11: spartan2e startup module not being expanded
    40596: 02/03/11: Has anyone used the LVDS or LVPECL I/O on spartan2e?
    40597: 02/03/11: Re: FPGA wich supports LVDS
    40598: 02/03/11: Re: SPI interface
    40996: 02/03/19: Re: 1,5V power supply?
    41057: 02/03/20: XPOWER accuracy?
    41129: 02/03/21: Re: XPOWER accuracy? Commendations
    41227: 02/03/22: Re: Poor availability problems on Coolrunner
    41857: 02/04/09: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
    41954: 02/04/11: Re: Price List ?
    41988: 02/04/12: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
    42119: 02/04/16: creating my own RPMs(?) or similar
    42133: 02/04/16: Re: creating my own hard macro or similar
    42138: 02/04/16: Re: creating my own hard macro or similar
    42419: 02/04/23: problem with coding a bidirectional bus simulation
    42659: 02/04/30: clock buffer infered on master reset in ISE for spartan2E
    42815: 02/05/03: LVPECL question?
    42819: 02/05/03: VCCO vs. VCCINT on spartan2e
    42820: 02/05/03: Re: VCCO vs. VCCINT on spartan2e
    42974: 02/05/08: "easter egg" in FPGA design?
    44464: 02/06/20: Re: 5V tolerance
    44506: 02/06/21: Re: 5V tolerance
    45265: 02/07/17: problem with configuration of spartan2e
    45273: 02/07/17: Re: problem with configuration of spartan2e
    46086: 02/08/16: CLOCK DLL IN SPARTAN2E Timing question
    46281: 02/08/23: need cheap and dirty time delay for spartan2e
    46282: 02/08/23: done output signal drive levels? (spartan2e)
    46290: 02/08/24: Re: need cheap and dirty time delay for spartan2e
    46292: 02/08/24: Re: need cheap and dirty time delay for spartan2e
    47210: 02/09/20: Question on Spartan2E maximum toggle frequency
    47353: 02/09/24: Re: Fast serial interconnect bus using spartan-II
    47604: 02/09/30: FFT in FPGA?
    47645: 02/10/01: Re: FFT in FPGA?
    47659: 02/10/01: USB2 in FPGA?
    47758: 02/10/03: Re: Need advice wiring up a CPLD
    47950: 02/10/08: Re: USB2 in FPGA?
    47951: 02/10/08: Re: USB2 in FPGA?
    48288: 02/10/15: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48296: 02/10/15: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48301: 02/10/15: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48336: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48603: 02/10/21: Re: 6502 core available
    48656: 02/10/22: Re: slow slew rate signal...
    48693: 02/10/22: Re: 6502 core available
    48756: 02/10/23: Re: Xilinx POS Power On Surge Current
    48799: 02/10/24: Re: Pin locking Virtex 2 FPGA
    48874: 02/10/25: Re: Just some newbie ISE questions...
    48875: 02/10/25: Re: Just some newbie ISE questions...
    49042: 02/10/30: Re: Handel-C Coding for the Motorola 68HC11 chip
    49996: 02/11/27: Re: question about PCB traces for FPGA board... ?
    50051: 02/11/29: Re: programmable FSM
    50356: 02/12/09: question about fft vs. cross corelation in fpga
    50852: 02/12/20: thermal issues on FPGA
    50944: 02/12/23: Re: thermal issues on FPGA
    50945: 02/12/23: Re: thermal issues on FPGA
    51081: 02/12/30: Re: thermal issues on FPGA
    51336: 03/01/10: ESD question on Spartan2e series inputs?
    52181: 03/02/03: Re: Targeting the VirtexII version of Picoblaze at a SpartanII....
    52211: 03/02/04: Re: Difference between : CPLD , FPGA , ASICS
    52266: 03/02/05: Re: Clock Enables
    52321: 03/02/06: Re: Clock Enables
    52365: 03/02/07: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
    52366: 03/02/07: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
    52380: 03/02/07: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
    52628: 03/02/17: Re: About automatically programming my FPGA
    52629: 03/02/17: Re: Generating a sin wave with vhdl
    52778: 03/02/21: Re: Should I choose Xilink or Altera for a small project
    52856: 03/02/24: Re: Connect USB device to Spartan 2e FPGA
    52889: 03/02/25: Re: Connect USB device to Spartan 2e FPGA
    52976: 03/02/27: Re: Spartan II PCB, I/O pins consederations
    52988: 03/02/27: Re: Spartan II PCB, I/O pins consederations
    53021: 03/02/28: Re: 10 MHz Clock out of 30 MHz
    53038: 03/02/28: Re: PCB board design software vs outsourcing?
    53126: 03/03/04: Re: VHDL & FPGA Design tools
    53127: 03/03/04: Re: Spartan II PCB, bypass Capacitors
    53240: 03/03/07: Re: Implementation of latch in FPGA
    53318: 03/03/10: Re: Implementation of latch in FPGA
    53319: 03/03/10: Re: Clocking a spartanIIE with a 5V signal?
    53356: 03/03/11: Re: State of the PCB world
    53406: 03/03/12: Re: Buying memory for FPGA...
    53661: 03/03/19: Re: usb spartan prototype
    53755: 03/03/21: troubleshooting programming of spartan2e
    53891: 03/03/26: Re: Virtex II pro board design question
    54021: 03/03/31: Re: connecting 2 FPGAs
    54247: 03/04/05: help with DLL problem in Spartan2E
    54265: 03/04/06: Re: help with DLL problem in Spartan2E
    54301: 03/04/07: Re: help with DLL problem in Spartan2E
    54579: 03/04/14: error correcting codes
    54601: 03/04/14: Re: Xilinx has released SpartanIII
    55557: 03/05/12: Re: OK I am pissed off with Xilinx webpack.
    56477: 03/06/06: fifo or bram in spartan2e vs spartan3
    57954: 03/07/10: Re: okay what am I missing??? Please
    58473: 03/07/24: Where do I find model sim xe starter download?
    59996: 03/09/03: Using a different editor for ISE 5
    60061: 03/09/04: Re: Moving Sum
    60188: 03/09/07: Spartan3 multiplier
    60648: 03/09/18: divide by on spartan3?
    60688: 03/09/19: Re: divide by on spartan3?
    60701: 03/09/19: Re: divide by on spartan3?
    60901: 03/09/24: Speed of various elements in the spartan3
    61544: 03/10/06: Re: Xilinx courses
Theron Hicks (Terry):
    29126: 01/02/06: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
    29384: 01/02/17: Re: Configuration of FPGA using SPROM
    29829: 01/03/12: VirtexE LVPECL I/O Ports? experience?
    36908: 01/11/24: Re: How to make an implementable big counter?
    38684: 02/01/21: Re: help me!
    39243: 02/02/04: Re: par and carry chains not allowing manual floorplanning
    39461: 02/02/10: Re: par and carry chains not allowing manual floorplanning
    39462: 02/02/10: Re: NT parallel port driver ...Any serial NT drivers?
    40163: 02/02/28: Re: Creation of FPGA tips and tricks forum - help required
    40187: 02/03/01: Re: high-speed clock distribution/divider in a FPGA?
    41829: 02/04/08: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
    42913: 02/05/06: LVPECL clock: which inputs?
    43195: 02/05/15: output rise and fall time for Spartan2E??
    43222: 02/05/16: Re: output rise and fall time for Spartan2E, but don't talk about IBIS??
    43226: 02/05/16: Re: output rise and fall time for Spartan2E, but don't talk about IBIS??
    43284: 02/05/17: Re: Reading GSR signal of Spartan-II
    43295: 02/05/18: Re: Reading GSR signal of Spartan-II
    47613: 02/09/30: Re: FFT in FPGA?
    47672: 02/10/01: Re: USB2 in FPGA?
    48318: 02/10/15: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48319: 02/10/15: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48321: 02/10/15: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    50866: 02/12/20: Re: State of the PCB world
    50867: 02/12/20: Re: State of the PCB world
    50898: 02/12/22: Re: thermal issues on FPGA
    50899: 02/12/22: Re: thermal issues on FPGA (oops.. wrong patent no.)
    50990: 02/12/24: Re: thermal issues on FPGA
    52329: 03/02/06: Re: Clock Enables
    52330: 03/02/06: Re: Clock Enables
    52331: 03/02/06: USB2 or firewire or 100Mb ethernet link to FPGA design
    52333: 03/02/06: Re: debounce circuit
    52334: 03/02/06: Re: Quartus II 2.2 doesn't run when installed to a newly transferred
    52335: 03/02/06: Re: clock ditribution tree
    52337: 03/02/06: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
    53221: 03/03/06: Re: Implementation of latch in FPGA
    53252: 03/03/07: Re: Implementation of latch in FPGA
    53770: 03/03/21: Re: troubleshooting programming of spartan2e
    54043: 03/03/31: Re: Input Characteristics : HCMOS vs TTL
    54684: 03/04/15: Re: error correcting codes
    54685: 03/04/15: Re: spartan 3 pin compatible with 2E?
    57969: 03/07/10: Re: okay what am I missing??? Please
    60659: 03/09/18: Re: divide by on spartan3?
    61466: 03/10/04: Re: Xilinx courses
Theron Wong:
    49063: 02/10/31: XST Constraint
<theshai@my-deja.com>:
    25440: 00/09/11: An online FPGA and CPLD course
TheToad:
    75575: 04/11/10: Research Project Re: Graphics Processor
thevlsiguru:
    74009: 04/10/02: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
they call me frenchy:
    89376: 05/09/13: Is a CPLD appropriate for this triple PWM application?
    89412: 05/09/14: Re: Is a CPLD appropriate for this triple PWM application?
    89413: 05/09/14: Re: Is a CPLD appropriate for this triple PWM application?
    89415: 05/09/14: Re: Is a CPLD appropriate for this triple PWM application?
    89458: 05/09/15: Re: Is a CPLD appropriate for this triple PWM application?
    89462: 05/09/15: Re: Is a CPLD appropriate for this triple PWM application?
    89464: 05/09/15: Re: Is a CPLD appropriate for this triple PWM application?
    89500: 05/09/16: Re: Is a CPLD appropriate for this triple PWM application?
    89502: 05/09/16: Re: Is a CPLD appropriate for this triple PWM application?
    89510: 05/09/16: Re: Is a CPLD appropriate for this triple PWM application?
    89562: 05/09/19: Re: Is a CPLD appropriate for this triple PWM application?
thi:
    18765: 99/11/13: Re: What are the steps involved in the developement of a CAD tool
THIEBOLT Francois:
    8956: 98/02/09: Re: Free FPGA tools???
    9047: 98/02/17: Xilinx download cable ??????
    8979: 98/02/11: List of free FPGA Tools suite....
    9730: 98/04/02: Choosing the right FPGA tools...
    9751: 98/04/03: Choosing the right tools and company....
    10674: 98/06/10: Re: Foundation M1.4 functional simulation problems
    11729: 98/09/04: Where to buy Atmel AT17C256 (i only needs a dozen)
Thielemans - Van Heghe:
    7762: 97/10/12: design sites
    7877: 97/10/26: design sites
Thiemo Nordenholz:
    128319: 08/01/22: Re: effect of xray on fpga electronic circuits
Thierry BOGEY:
    6516: 97/05/30: XC5215-5 BG352 help
Thierry Garrel:
    16672: 99/06/02: Re: Printing to picture files : my experience with Viewlogic
    16749: 99/06/06: Re: Memec 8250 core with Xilinx Spartan device
    17784: 99/09/03: Technology Comparison of FPGAs families
Thierry Gschwind:
    70352: 04/06/14: Several Problems with Spartan2 Configuration
    70362: 04/06/14: Re: Several Problems with Spartan2 Configuration
    70471: 04/06/17: Re: Several Problems with Spartan2 Configuration
    70625: 04/06/22: Re: Synthesis of loops
Thijs:
    44036: 02/06/10: programming xc3030 using atmel's ATDH2225 programmer cable
    44049: 02/06/11: Re: programming xc3030 using atmel's ATDH2225 programmer cable
    44118: 02/06/12: Re: programming xc3030 using atmel's ATDH2225 programmer cable
    47160: 02/09/19: slightly OT: does anyone know free parallel flash programmer schematics?
    52093: 03/01/31: problem programming atmel fpga config mem
thilo jeremias:
    35747: 01/10/16: Repost: Fine graine vs coarse graine FPGA
Thilo Thiessenhusen:
    10696: 98/06/11: Xilinx 4000/Spartan: Maximum pin pullup
    10708: 98/06/11: Re: Xilinx 4000/Spartan: Maximum pin pullup
Thina Nguyen:
    7770: 97/10/13: Help with School Project
<thiru1457@my-deja.com>:
    17717: 99/08/27: Feasibility of 200 MHz, 12K design on FPGA
thirumurugan:
    29632: 01/03/02: Netlis : Webpack Vs Foundation
Thom Drake:
    61215: 03/09/30: Logic Analyzer for FPGAs
Thoma:
    143086: 09/09/19: Symbolic string for vector values under modelsim
    143097: 09/09/20: Re: Symbolic string for vector values under modelsim
Thomas:
    24687: 00/08/16: SV: how to use script file in the Design Manager
    29473: 01/02/22: SV: UCF problem "- Could not find NET "
    41643: 02/04/04: download PC - to Lattice ispLSI 2192 (jtag) device WinNT
    41739: 02/04/06: Re: How to probe internal signals from Xilinx netlist?
    41762: 02/04/07: Re: FPGA config without boot PROM???
    44399: 02/06/19: ISE Webpack Basics
    44572: 02/06/24: Agilent ADS generated Code
    44630: 02/06/25: Programming examples for Spartan II
    44820: 02/07/02: Communication between FPGA and PC
    44866: 02/07/03: Re: Communication between FPGA and PC
    46401: 02/08/28: Webpack : Order of compiling modules
    52318: 03/02/06: Re: clock ditribution tree
    56934: 03/06/19: bidirectional bus (tristate issue)
    56945: 03/06/19: Re: Port Mode
    56947: 03/06/19: Re: FPGA GPU (Spartan IIe 300K)
    57034: 03/06/21: Re: Bidirectional bus (tristate issue) // with ABV comments
    57072: 03/06/23: ModelSim 5.7 and xilinx libraries
    57087: 03/06/23: Re: ModelSim 5.7 and xilinx libraries
    57224: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
    57225: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
    57261: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
    57328: 03/06/27: Re: ModelSim 5.7 and xilinx libraries
    57461: 03/07/01: NgdBuild:477 - clock net xx has non-clock connections
    57464: 03/07/01: MapLib:93 - Illegal LOC on symbol "clk.PAD" (pad signal=clk) or BUFGP symbol "u1" (output signal=u1), IPAD-IBUFG should only be LOC'd to GCLKIOB site."
    57737: 03/07/05: hidden remap failed
    57738: 03/07/05: Re: hidden remap failed
    57782: 03/07/07: spartan2e block ram error
    59205: 03/08/12: Yet another modelsim problem
    60039: 03/09/04: Clock Recovery from 8B10B encoded Data Stream
    65246: 04/01/22: Down Sample, FFT
    78810: 05/02/08: Input Timing Specification
    78860: 05/02/09: Re: Input Timing Specification
    81231: 05/03/19: Re: rocketio
    83481: 05/04/30: Decoupling V2P
    83499: 05/05/01: Re: Decoupling V2P
    83613: 05/05/04: Re: Decoupling V2P
    93286: 05/12/19: Problem with downloading elf file to ML403 using XMD
    109482: 06/09/27: Addressing DDR-RAM
    111309: 06/11/01: Yet Another Survey: What are code generators worth?(was: Re: Survey: simulator usage)
    111431: 06/11/02: Re: Yet Another Survey: What are code generators worth?(was: Re: Survey: simulator usage)
    111468: 06/11/03: Re: Yet Another Survey: What are code generators worth?(was: Re: Survey: simulator usage)
    127223: 07/12/14: Re: using fstream to access File on Compact Flash Card
thomas:
    3840: 96/08/08: Monostable multivibrator
    3841: 96/08/08: (no subject)
    3842: 96/08/08: 74HC123 MVR modify to TTL CIRCUIT
    71659: 04/07/27: Re: Programming a LCD display with a Celoxica RC100
Thomas A. Coonan:
    8852: 98/02/01: Re: FPGA/ASIC - same difference?
    8870: 98/02/03: Re: FPGA/ASIC - same difference?
    9775: 98/04/04: Re: Rees-Solomon
    9824: 98/04/08: Re: Effects of IC production
    11108: 98/07/20: Re: Too much advertising in this news group?
    11205: 98/07/25: Re: Silicore VHDL 8-bit RISC uC core for FPGA
    11224: 98/07/28: Re: [Q] motor control onto an FPGA
    11810: 98/09/10: Re: Need Permutation generator
    12959: 98/11/07: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
    12965: 98/11/08: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
    12987: 98/11/09: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
    13129: 98/11/17: Re: Example of clock circuit needed !
    14111: 99/01/14: Re: 1-wire
    14458: 99/01/30: Re: Help for the scientifically-challenged
    14745: 99/02/14: Re: EEProm erasing?
    15235: 99/03/16: Re: How can I improve an adder?
    15663: 99/04/07: Re: viterbi/trellis decoder
    16944: 99/06/18: Read/Writes to memories/register files for PIC core
    16948: 99/06/18: Re: Read/Writes to memories/register files for PIC core
    16960: 99/06/19: Re: Read/Writes to memories/register files for PIC core
    17044: 99/06/28: Re: Read/Writes to memories/register files for PIC core
    17069: 99/06/28: Re: Read/Writes to memories/register files for PIC core
    17086: 99/06/29: Re: Read/Writes to memories/register files for PIC core
Thomas A. Sutera:
    1234: 95/05/19: 6502 processor
Thomas Bachman:
    1359: 95/06/06: Asynch. Periph. Prog. of FPGAs
    1397: 95/06/14: Re: HELP on programming XC3090A
Thomas Bartzick:
    49332: 02/11/09: FPGA: SPARTAN IIE-Configuration via JTAG
    65349: 04/01/25: Problem with TBUF-Placing
    65353: 04/01/25: TBUF-PAR-Warning in detail
    65535: 04/02/01: Re: Problem with TBUF-Placing
    68846: 04/04/20: State machines vs. Schematics
    68879: 04/04/20: Re: State machines vs. Schematics
    72718: 04/08/30: PCI-Core
    74960: 04/10/22: Re: Experiences with SPARTAN3?
    75172: 04/10/28: Question to TBUS-Placement in SPARTAN3 again!
    74791: 04/10/19: Experiences with SPARTAN3?
    74831: 04/10/20: Re: Experiences with SPARTAN3?
Thomas Berndt:
    7094: 97/07/31: Re: Simulating large VHDL design (FPGA backannotated)
    7095: 97/07/31: Re: Problem simulating 3-state output with M1 and Synopsys
    7097: 97/07/31: Download FLEX10K over the LPT port
Thomas Bornhaupt:
    19399: 99/12/19: JamPlayer and 10K10
    19403: 99/12/20: Re: JamPlayer and 10K10
    19426: 99/12/21: Re: JamPlayer and 10K10
    36089: 01/10/29: Jam Player and MAX+plus II
    36093: 01/10/29: Re: Jam Player and MAX+plus II
    61851: 03/10/14: Re: EPC16 will not Flash Program
Thomas Buerner:
    43790: 02/06/03: FPGA Download via FTP
    44578: 02/06/24: book recommenation
    48493: 02/10/18: Webpack4.2
    48570: 02/10/21: Re: Webpack4.2
    49244: 02/11/06: webpack 5.1 under w2k
    50131: 02/12/03: ISA bus VGA
    50179: 02/12/04: Re: ISA bus VGA
    50393: 02/12/10: Re: ISA bus VGA
    51616: 03/01/17: Generating EDIF from HandelC
    51836: 03/01/23: Xilinx Impact on a SUN/Solaris
Thomas Burchard:
    20088: 00/01/26: Re: Viterbi decoder in FPGA
Thomas C. Jones:
    4848: 96/12/19: Re: FPGA market overview
    5019: 97/01/13: Any PEEL22CV10A replacements with more capacity?
Thomas D. Tessier:
    5753: 97/03/12: Re: A viewlogic story
    5964: 97/03/31: Re: Sole source
    5965: 97/03/31: Re: System Level Integration on Deep submicron FPGAs
    5988: 97/04/02: Re: 8051 core for XC40xx
    11020: 98/07/10: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
    12611: 98/10/20: Re: Xilinx F1.5/FPGA Express wackiness
    12744: 98/10/27: Re: ORCAD Compile error
    12827: 98/10/30: Re: Schematic entry?
    12923: 98/11/04: Re: Schematic entry?
    12924: 98/11/04: Re: Schematic entry?
Thomas D. Tessier 303-939-5487:
    263: 94/10/07: Re: AT&T ORCA FPGA
thomas daehler:
    33141: 01/07/18: Spartan2XC2S30 vs ACEXEP1K30
Thomas Dölle:
    12332: 98/10/09: clock divider chips
Thomas Ebert:
    2622: 96/01/12: PCI-interface chip from PLX
    3207: 96/04/24: Re: ECL, PECL gate arrays or FPGA's
    3682: 96/07/12: Re: WANTED:: Altera second source
    14673: 99/02/10: Altera freecore library ?
    14674: 99/02/10: Re: PLX9050 Dev. Software
    14681: 99/02/11: Q: PCMCIA Interface For ALTERA
Thomas Ekberg:
    21859: 00/04/04: Replication control in Xilinx P&R
Thomas Entner:
    78573: 05/02/03: Re: Altera PLL and Timing Analysis
    78648: 05/02/04: Re: Spartan-3 Starter Kit supplier in the UK?
    79451: 05/02/19: Re: Nios performance
    79459: 05/02/19: Re: Nios performance
    79830: 05/02/24: Re: Nios performance
    80111: 05/03/01: Re: FPGA tool benchmarks on Linux systems
    80819: 05/03/11: Maximum LVDS-rate of Spartan 3E
    80956: 05/03/15: Re: Quartus II and DSE
    80978: 05/03/15: Re: Which HDL?
    81249: 05/03/20: Re: Spartan 3E vs. Cyclone2
    81294: 05/03/21: Re: Spartan 3E vs. Cyclone2
    81387: 05/03/22: Re: PowerPC soft-core?
    81392: 05/03/22: Re: PowerPC soft-core?
    81414: 05/03/23: Re: PowerPC soft-core?
    81634: 05/03/29: Re: some +. for Altera
    81638: 05/03/29: Re: some +. for Altera
    81645: 05/03/29: Re: some +. for Altera
    81700: 05/03/30: Re: C compiler for Picoblaze - FPGA
    82252: 05/04/09: Re: ISE 7.1 for 64 bit Linux ???
    82479: 05/04/13: Re: General question about soft CPUs
    82690: 05/04/16: Re: salary ballpark please guys
    82779: 05/04/18: Re: Multi-page schematics (.bdf) in Quartus II?
    84439: 05/05/19: Re: How many logic cells are there in one slice
    84715: 05/05/25: Re: VHDL vs. Schematic Capture
    85242: 05/06/07: Re: Pissed off with Xilinx - Spartan 3
    85245: 05/06/07: Re: Pissed off with Xilinx - Spartan 3
    85266: 05/06/07: Re: Pissed off with Xilinx - Spartan 3
    86217: 05/06/23: Re: Minimum allowed clock frequency for Nios 2 processor (Stratix 2)
    86225: 05/06/23: Re: Minimum allowed clock frequency for Nios 2 processor (Stratix 2)
    86287: 05/06/24: Re: Spartan-3e order of availability?
    86297: 05/06/24: Re: Xilinx webshop
    86574: 05/06/30: Re: from email into FPGA !!
    86909: 05/07/08: Re: Max Sample Rate for Signal Tap in Altera Quartus?
    86954: 05/07/11: Re: new PLD and FPGA devices from Lattice
    87487: 05/07/25: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87635: 05/07/27: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
    88135: 05/08/10: Re: Welcome back Mr. Knapp
    88226: 05/08/12: Re: Welcome back Mr. Knapp
    88227: 05/08/12: Re: high speed image capture
    88514: 05/08/21: Re: Altera mysupport
    88662: 05/08/24: Re: Stdin / stdout through RS232
    88747: 05/08/27: Re: 36x36 signed multiplier?
    88775: 05/08/28: mails from Aman Mediratta
    88778: 05/08/28: Re: mails from Aman Mediratta
    88804: 05/08/29: Re: fast universal compression scheme and its implementation in VHDL
    89921: 05/09/30: Re: Antti is back
    90003: 05/10/02: Re: Xilinx dev board with high quality video?
    92270: 05/11/25: Re: FPGA ARM IP Core
    92754: 05/12/06: Re: IDE for Nios2 does not compile on windows XP
    92915: 05/12/09: No, not FIFOs again...
    92935: 05/12/09: Re: No, not FIFOs again...
    92941: 05/12/09: Re: No, not FIFOs again...
    92972: 05/12/10: Re: No, not FIFOs again...
    92973: 05/12/10: Re: No, not FIFOs again...
    94020: 06/01/04: Re: Schematic Entry, Xilinx or Altera?
    96871: 06/02/12: Re: Microblaze using SPI flash as instruction memory
    96895: 06/02/13: Re: Microblaze using SPI flash as instruction memory
    99030: 06/03/19: Re: Altera Cyclone II DQ/DQS pins location
    100295: 06/04/06: Re: Bizarre behaviour by Quartus?
    103169: 06/05/26: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
    104808: 06/07/06: Re: Can I use all 18bits of a BlockRAM?
    105865: 06/08/02: Re: Where are Huffman encoding applications?
    106095: 06/08/07: Re: DDR2 SRAM Stratix II questions
    106109: 06/08/07: Re: DDR2 SRAM Stratix II questions
    106269: 06/08/10: Re: Real-world soft-cpu performance
    106525: 06/08/15: Re: Crystal input for FPGA
    106526: 06/08/15: Re: Crystal input for FPGA
    106550: 06/08/15: Re: Crystal input for FPGA
    106567: 06/08/15: Re: Crystal input for FPGA
    107461: 06/08/28: Re: Actel Fusion?
    108108: 06/09/05: Re: Exploring Quartus' Messages and Warnings
    109640: 06/10/02: Re: LatticeMico32 extremly poor performance without caches
    109812: 06/10/05: Re: a clueless bloke tells Xilinx to get a move on
    109938: 06/10/08: Re: free CAN field bus IP for EDK ?
    109975: 06/10/09: Re: Quartus II 6.0: System clock has been set back
    110024: 06/10/09: Re: Quartus II 6.0
    110151: 06/10/11: Re: Quartus II 6.0: System clock has been set back
    110300: 06/10/13: Re: multithreaded Synthesis and Place and route... Finally!
    110358: 06/10/14: Re: FPGA comparision
    110866: 06/10/24: Re: Survey on Quartus SOPC/Nios-II
    110904: 06/10/25: Re: Survey on Quartus SOPC/Nios-II
    111481: 06/11/03: Re: Fastest ISE Compile PC?
    111818: 06/11/10: Re: Stratix-III announced
    111828: 06/11/10: Re: Stratix-III announced
    111844: 06/11/11: Re: Stratix-III announced
    112205: 06/11/17: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
    112218: 06/11/18: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
    113056: 06/12/05: Re: First Look at QuartusII 6.1
    113261: 06/12/09: Re: About Unstable Operation of ACTEL(A3P1000)....
    116967: 07/03/21: Re: Off topic: what is the purpoe of XST?
    117037: 07/03/22: Re: Off topic: what is the purpoe of XST?
    117791: 07/04/10: Re: Ross Freeman - inventor of the FPGA
    118177: 07/04/19: Re: Altera M4K memory usage
    118371: 07/04/25: Re: Image compression on FPGA
    124386: 07/09/20: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    146638: 10/03/24: EMC discussion
    146671: 10/03/25: Re: EMC discussion
    146722: 10/03/26: Re: Any advice on which is the best book on CMOS digital circuit
    147659: 10/05/13: Re: New 'standard' compact programming header needed!
    147708: 10/05/18: Re: New 'standard' compact programming header needed!
    148317: 10/07/07: EEBlaster - USB-JTAG-tool for Altera
    148757: 10/08/19: Re: Altera blasters missing ESD protection
    148877: 10/09/06: Re: We need an administrator for the group to fight spam
    149111: 10/10/02: Re: SDRAM for specific use - performance and timing questions
    149707: 10/11/19: Re: hot- or cold-plugging altera cyclone-3 LVDS inputs causing damage?
    149775: 10/11/23: Re: Atom 6000C perspective, anyone?
    149912: 10/12/01: Re: Brain Cramps...
    150081: 10/12/10: Re: Interfacing DS92LV1021 with FPGA serdes
    150082: 10/12/10: Re: Interfacing DS92LV1021 with FPGA serdes
    150279: 11/01/07: Re: OT: Fast Circuits
    150287: 11/01/07: Re: OT: Fast Circuits
    150877: 11/02/18: Re: why an FSM is not a counter?!
    151164: 11/03/12: Re: pcb&bitstream
    151278: 11/03/19: Re: NIOS II license?
    151535: 11/04/18: Re: NibzX7 processor
    151537: 11/04/18: Re: NibzX7 processor
    152189: 11/07/18: Re: Issues with Soft-Cores
    152261: 11/07/29: Re: Bitstream compression
    152475: 11/08/28: Re: cheating Arria FPGA i/o count
    153081: 11/11/28: Re: XC7V2000T, the perfect Thanksgiving gift
    153261: 12/01/19: Re: Compatible Xilinx USB Cables: worth to bother?
    153262: 12/01/19: Compatible Altera USB Cable
    153429: 12/02/23: Re: What is a PLD/FPGA with serial or Ethernet port logic or block
Thomas Falk:
    25403: 00/09/10: Clock skew in XILINX CPLD
    25454: 00/09/12: Re: Clock skew in XILINX CPLD
    25455: 00/09/12: Re: Clock skew in XILINX CPLD
    25518: 00/09/13: Re: Clock skew in XILINX CPLD
    25531: 00/09/13: Re: Clock skew in XILINX CPLD
    25563: 00/09/14: Re: Clock skew in XILINX CPLD
Thomas Feller:
    114624: 07/01/21: Re: Xilinx website login problems
    114941: 07/01/27: Re: xilinx 8.2 xps debug problems
    119211: 07/05/15: Xilinx ISE 9.1 Simulator does not work with glibc 2.5
    119242: 07/05/15: Re: Xilinx ISE 9.1 Simulator does not work with glibc 2.5
    126735: 07/11/30: Re: Fedora 8 and ISE 9.2
Thomas Finke:
    6191: 97/04/24: EDIF200
Thomas Fischer:
    82706: 05/04/16: Re: Power supply design
    83121: 05/04/24: Re: motherboard w/o 3.3V PCI fingers
    83549: 05/05/02: Re: JTAG communication Problems in Quartus using Signal Tap
    86100: 05/06/22: Re: nios2 / terminal
Thomas Focke:
    11424: 98/08/12: FFT-Speed
Thomas Fuchs:
    58026: 03/07/12: CLKDLLE CLK2X180 Outpu doesn't work
Thomas Gebauer:
    25809: 00/09/21: Re: SYNOPSYS using BLOCK RAM (VIRTEX)
    80483: 05/03/07: Re: DCT in FPGA
    81279: 05/03/21: Re: Is an XC3S1500 enough to implement a MP@ML MPEG-2 decoder?
    94916: 06/01/19: Re: ISE8.1 on Linux, first impressions
    96409: 06/02/03: Re: xilinx linux source?
Thomas Glanzmann:
    116812: 07/03/19: Re: DDR2 and SDRAM modules for Raggedstone 1
Thomas Grant Edwards:
    2736: 96/01/31: Re: How Big Chips Will Be Designed In The Not Too Distant Future
Thomas Hadlich:
    49: 94/08/04: Mouseproblems using Makebits (Xilinx 4.3)
    577: 95/01/09: Re: Motorola FPGA
    3465: 96/06/03: Re: impossible for Synthesizer to optimize FSM??!
    3542: 96/06/18: Q: Xilinx Foundation stuff?
    4978: 97/01/08: Re: design should fit, but it doesn't
    5710: 97/03/10: Re: help:Prog. Xilinx demo board
Thomas Hauri:
    10374: 98/05/15: Re: Motion Controller design for DC motor wanted
Thomas Hedler:
    18591: 99/11/02: Optimizing Logic Cells
Thomas Heidel:
    30430: 01/04/07: Re: How to combine bus in schematic
Thomas Heller:
    45091: 02/07/12: Replacing a XC4006E
    45345: 02/07/19: PCI FPGA prototype board with lots of SDRAM?
    49067: 02/10/31: Spartan-II configuration
    49076: 02/10/31: Re: Spartan-II configuration
    49742: 02/11/20: Re: Foundation 2.1i with Windows 2000?
    55637: 03/05/14: Re: OK I am pissed off with Xilinx webpack.
    56697: 03/06/11: Re: DVI with a Virtex-II - summary
    57706: 03/07/04: Re: Xilinx ISE drops support for more parts
    57777: 03/07/07: Re: Xilinx ISE drops support for more parts
    66152: 04/02/13: Re: Peter's 1Hz-640MHz Synth project
    66501: 04/02/20: Spartan 3 - avaliable in small quantities?
    117925: 07/04/13: Simulating LogicCores with Webpack
    118149: 07/04/18: Problems in simulation (Webpack 9.1.03i)
    118200: 07/04/19: Re: Problems in simulation (Webpack 9.1.03i)
    118251: 07/04/20: Looking for a spartan 3 board
    118258: 07/04/20: Re: Looking for a spartan 3 board
    118908: 07/05/07: UCF file for LT FastDAACS board?
    119993: 07/05/30: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
    135573: 08/10/08: Re: How to synthesize a delay of around 10 ns in FPGA?
    135626: 08/10/10: Re: How to synthesize a delay of around 10 ns in FPGA?
    148419: 10/07/21: How to create a LVPECL_25 output pair (Spartan3, ISE 9.1)
    148426: 10/07/22: Re: How to create a LVPECL_25 output pair (Spartan3, ISE 9.1)
    149376: 10/10/20: Designing for Xilinx Spartan in 2010?
    149389: 10/10/21: Re: Designing for Xilinx Spartan in 2010?
    149711: 10/11/20: Spartan3 device with long availability
    149729: 10/11/21: Re: Spartan3 device with long availability
    149828: 10/11/25: Re: Spartan3 device with long availability
    149829: 10/11/25: Re: Spartan3 device with long availability
    150102: 10/12/13: Re: Lattice XO2 video
    150393: 11/01/16: Location constraints questions
    150395: 11/01/16: Re: Location constraints questions
    150399: 11/01/16: Re: Location constraints questions
    150407: 11/01/17: Re: Location constraints questions
    150408: 11/01/17: Re: Location constraints questions
    150410: 11/01/17: Re: Location constraints questions
    150412: 11/01/18: Re: Location constraints questions
    150830: 11/02/15: Re: lattice machXO2 VCCP pin
    150923: 11/02/22: Re: timing issues at high speed
    151146: 11/03/11: Re: Nanosecond pulse generator using Spartan-3E
    152137: 11/07/13: Looking for a FPGA board
    152142: 11/07/13: Re: Looking for a FPGA board
    152157: 11/07/14: Re: Looking for a FPGA board
    152158: 11/07/14: Re: Looking for a FPGA board
    152165: 11/07/15: Re: Looking for a FPGA board
    153571: 12/03/29: Re: FPGA communication with a PC (Windows)
    153749: 12/05/09: Comparing virtex2 to spartan6
    153751: 12/05/10: Re: Comparing virtex2 to spartan6
    153828: 12/06/01: PRNG
    153838: 12/06/01: Re: PRNG
    153839: 12/06/01: Re: PRNG
    153974: 12/07/06: Re: Generate a pulse with a definite width
    154381: 12/10/18: Serial LVDS ADC to spartan6
Thomas Hellerforth:
    15836: 99/04/16: Re: How to write BIDIR IO in MAXPLUS2 VHDL ?
    21525: 00/03/24: Re: [REQ] download function of Xilinx CPLD
Thomas J. Gritzan:
    137983: 09/02/03: Re: rs232 uart: testbench vs real world, and the missing first
Thomas J. Loftus:
    4461: 96/11/01: Re: What is the fastest fpga for ...
    5051: 97/01/16: Meta Assembler wanted
Thomas Johansson:
    6257: 97/05/05: Re: Implementing three state output MUXes with Synopsys
    10752: 98/06/16: Re: Wallace trees
    10763: 98/06/17: Re: Wallace trees
Thomas Jones:
    54440: 03/04/10: Using DP RAM for message passing
    54622: 03/04/14: Re: Using DP RAM for message passing
    147753: 10/05/21: Any V6's available?
Thomas Karlsson:
    24782: 00/08/18: Re: Instantiation of Virtex-E Block SelectRAMs
    25272: 00/09/04: Re: XC3000A Configuration data
    25275: 00/09/04: Re: XC3000A Configuration data
    25320: 00/09/06: Re: About XNF, EDIF and UCF
    25367: 00/09/08: How do I mix vhdl and verilog source files in Synplify?
    25572: 00/09/14: Re: How do I mix vhdl and verilog source files in Synplify?
    27907: 00/12/14: Re: Spartan configuration : Why Done returns to Low?
    31642: 01/06/01: Re: Help on Xilinx 6200
    31643: 01/06/01: Re: Help on Xilinx 6200
    31757: 01/06/05: Re: Xilinx Configuration Bitstream
    31762: 01/06/05: Re: Help needed on Max7000 pin assignments (Max-plus II)
    31929: 01/06/08: safe state machine design problem
    32084: 01/06/13: Re: Newbie
Thomas Karolyshyn:
    82209: 05/04/08: Altera programming via Embedded processor
Thomas Kobler:
    4323: 96/10/15: Xilinx xchecker.exe and Windows NT
Thomas Kurth:
    47513: 02/09/27: Re: Xilinx will not provid free ISE Allanice 5.1i?
    47996: 02/10/09: Re: Why can't Altera sw be as good as Xilinx's sw?
    51132: 03/01/03: Re: Unused FPGA I/O Pins?
    54475: 03/04/11: Re: Double Edge FlipFlop
    65714: 04/02/05: installing stand alone xilinx impact
    67246: 04/03/09: LVDS
    67309: 04/03/10: Re: LVDS
    67313: 04/03/10: Re: LVDS
Thomas Lane:
    3070: 96/03/26: Picdesigner--Archived Design Woes
Thomas Langås:
    114836: 07/01/24: General Number Field Sieve in FPGA
Thomas Lehner:
    32529: 01/06/29: Digital PLL, frequency multiplication: looking for problem : )
    32629: 01/07/03: Re: Digital PLL, frequency multiplication: looking for problem : )
    53086: 03/03/03: Nios - > 8 bit Ram
Thomas LeMense:
    15338: 99/03/19: Re: Foundation V1.5 Crash
Thomas Loftus:
    21971: 00/04/10: Re: Distributed Arithmetic
Thomas M Malec:
Thomas Maaø Langås:
    98842: 06/03/17: SerialATA with Virtex-II Pro
    98885: 06/03/17: Re: SerialATA with Virtex-II Pro
    98923: 06/03/17: Re: SerialATA with Virtex-II Pro
    98929: 06/03/17: Re: SerialATA with Virtex-II Pro
    99132: 06/03/20: Re: SerialATA with Virtex-II Pro
    99211: 06/03/21: Re: SerialATA with Virtex-II Pro
Thomas Magma:
    87393: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
Thomas Maslen:
    28278: 01/01/05: Re: Nondeterministic FSMs in hardware?
    46650: 02/09/05: Re: Hardware Code Morphing?
Thomas Nilsen:
    72076: 04/08/08: Re: LEGO mindstorms and FPGA
    72244: 04/08/12: Different capabilities
    72266: 04/08/12: Re: Different capabilities
Thomas Oehme:
    60048: 03/09/04: Re: ISE 5.2 constraint file problem
    60105: 03/09/05: ISE: use verilog-modules in an vhdl-design-flow
    97477: 06/02/23: OpenRisc 1200 on Spartan 3 - problems with stability and enabling
    97492: 06/02/23: Re: OpenRisc 1200 on Spartan 3 - problems with stability and enabling
Thomas P. Missert:
    10767: 98/06/17: re: Urgent need for HW Engineering talent
Thomas P. Myers:
    20794: 00/02/22: Re: IEC 1131-3 i NEED HELP
Thomas Pollischansky:
    49253: 02/11/06: Compiling Altera Nios Designs
    49280: 02/11/07: Re: Compiling Altera Nios Designs
    49422: 02/11/11: Re: Compiling Altera Nios Designs
    49538: 02/11/14: Re: Compiling Altera Nios Designs
    50538: 02/12/12: Re: Problem with Symbol generation in Quartus2
    50539: 02/12/12: NIOS C Programming: Accesing the Status Register?
Thomas Pornin:
    9348: 98/03/07: Re: The case for Linux and EDA
    9275: 98/03/05: Re: The case for free operating systems and EDA
    9293: 98/03/05: Re: The case for free operating systems and EDA
    9349: 98/03/07: Re: The case for free operating systems and EDA
    9357: 98/03/07: Re: The case for Linux and EDA
    9358: 98/03/07: Re: The case for Linux and EDA
    9366: 98/03/07: Re: The case for Linux and EDA
    10192: 98/05/03: Re: Xilinx Foundation and Linux
Thomas Rathgen:
    16813: 99/06/10: Configuring AlteraFlex10k with maxII
    19313: 99/12/13: power on reset with FLEX 10K
    19471: 99/12/23: Re: Global buffer insertion (Synplify/Flex10K)
    19822: 00/01/13: Re: PCI Bus Problems with Burst Transfers
Thomas Reinemann:
    11259: 98/07/31: Re: How to connect my reset with GSR at Xilinx-FPGAs - response and Additional questions!
    12105: 98/09/29: Using Xilinx TBUF?
    14809: 99/02/18: Re: Free circuit design
    17327: 99/07/21: Re: Solaris vs. NT
    17544: 99/08/09: Re: Solaris vs. NT
    28392: 01/01/11: Re: Alliance for Linux
    28429: 01/01/12: Re: Alliance for Linux
    32787: 01/07/09: Vitrtex selectram
    45635: 02/07/30: Re: Bit serial arithmetic Vs Digit serial Arithmetic
    47049: 02/09/16: Re: Custom plug-in for HDL Designer
    69297: 04/05/05: ChipScope Core Generator Flow
    69394: 04/05/10: Re: ChipScope Core Generator Flow
    71774: 04/07/30: NCD difference
    71879: 04/08/03: Re: NCD difference
    71888: 04/08/03: Instantiation of BUFGMUX
    73450: 04/09/22: Re: Virtex 4 integrated A/Ds? Yes it does.
    74103: 04/10/04: XC2V1000 Block RAM size
    74110: 04/10/04: Chipscope and BlockRam
    74417: 04/10/11: Multiple Access on long lines
    75504: 04/11/08: Partial reconfiguration, Special kind of bus macro
    75548: 04/11/09: Re: Partial reconfiguration, Special kind of bus macro
    75685: 04/11/12: Re: Partial reconfiguration, Special kind of bus macro
    75686: 04/11/12: Re: Partial reconfiguration, Special kind of bus macro
    76381: 04/12/01: Re: Xilinx Virtex 4 question
    76464: 04/12/03: Re: how to start with development of eda tools
    76536: 04/12/06: Re: how to start with development of eda tools
    78197: 05/01/26: Re: Another problem getting ISE 6.3i running on Linux
    78391: 05/01/31: Listing unrouted nets in FPGA Editor
    80554: 05/03/08: RPM creation
    80767: 05/03/11: Re: RPM creation
    86945: 05/07/11: Search for FPGA
    91316: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
    94465: 06/01/12: Re: ISE 8.1i WebPack available
    97741: 06/02/27: Re: VHDL to create LUT based delay
    100773: 06/04/18: How to connect FPGA and =?ISO-8859-15?Q?=B5C?=
    102424: 06/05/16: Re: Actel Fusion FPGAs
    105128: 06/07/14: Need for reset in FPGAs
    109568: 06/09/29: Filter trouble
    109578: 06/09/29: Re: Filter trouble
    111997: 06/11/14: Influence of temperature and manufacturing to propagation delay
    112097: 06/11/16: Re: In defence of Austin and Xilinx
    113516: 06/12/15: Resource estimation
    113951: 06/12/30: Re: SPI slave problem
    115059: 07/01/30: Differential pairs per Bank
    122221: 07/07/24: Arming the Chipscope Pro ILA
    122232: 07/07/24: Re: Arming the Chipscope Pro ILA
    129291: 08/02/20: Re: Antti needs a job
    133145: 08/06/19: Re: MIG core generator problem
Thomas Riesenberg:
    12774: 98/10/29: Re: I2C core design
Thomas Rinder:
    22016: 00/04/12: Modeltech Error
    24502: 00/08/11: Xilinx, XVC300, 18V02
Thomas Rock:
    5726: 97/03/10: Re: Galileo... Leonardo... Renoir... ?
    8737: 98/01/22: Re: ALtera Devices.
Thomas Rouam:
    126223: 07/11/17: Re: VHDL language is out of date! Why? I will explain.
Thomas Rudloff:
    50122: 02/12/03: Re: question about series termination resistors and VIAS
    50274: 02/12/07: Re: CPLD current measurement
    51151: 03/01/04: Re: interface DRAM to FPGA
    51797: 03/01/22: Re: FLEXlm
    52962: 03/02/27: Re: configuring xilinx fpga with nand flash
    52963: 03/02/27: Re: Extend PCI slot to outside PC
    52969: 03/02/27: Re: PCI specification question
    64385: 03/12/31: Re: Newbie VHDL issue with CPLD
    72849: 04/09/05: Re: 1GHz FPGA counters
    72865: 04/09/06: Re: VHDL modelling USB device
    72941: 04/09/08: Re: i2c-core from opencores.org
    72942: 04/09/08: Re: 1GHz FPGA counters
    72944: 04/09/08: Re: 1GHz FPGA counters
    73433: 04/09/21: Spartan-3 DDR Speed
    74976: 04/10/22: Re: Xilinx translate error : Cannot find signal "clk"
    74978: 04/10/22: Re: unstable fpga design
    74979: 04/10/22: VCXO Emulation
    74985: 04/10/23: Re: VCXO Emulation, or using a DLL to shift phase infinitely, or
    75003: 04/10/24: Re: unstable fpga design
    75133: 04/10/26: Re: Clock Extraction from Bi-Phase Data
    78890: 05/02/09: Re: laptop for fpga design - acer ferrari?
    80446: 05/03/06: Re: spartan3 development board in Europe?
    81499: 05/03/25: Re: LVPECL, Virtex II and the EP445
    81553: 05/03/27: Re: reset on startup
    81594: 05/03/28: Re: reset on startup
    83726: 05/05/06: Re: 200+ MHz through a SCSI cable
    83731: 05/05/06: Re: Clock Gating
    83769: 05/05/06: Re: Parallel Cable IV opened in "Compatibility Mode"
    83790: 05/05/07: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
    83797: 05/05/07: Re: Using capacitor to slow the rise time.
    83799: 05/05/07: Re: Metastability / MUX question
    83801: 05/05/07: Re: Which chip should I use?
    83824: 05/05/07: Re: Which chip should I use?
    89993: 05/10/01: Re: Count "1" bit in bit stream
    90037: 05/10/03: Re: RLDRAM-II controller - Read problem
    93825: 06/01/01: Re: real-time compression algorithms on fpga
    93906: 06/01/03: Re: Start up condition of flip flops in FPGA?
    97721: 06/02/26: Re: realize pci in fpga
    127433: 07/12/24: Re: Spartan 3e and SDRAM
    141606: 09/06/29: SATA Phy
    143379: 09/10/07: Re: 8 phase clock output
    143380: 09/10/07: Spartan-6 SERDES Speed
    143430: 09/10/11: Re: Development boards for CPU development ?
    143433: 09/10/11: Re: 8 phase clock output
Thomas Sailer:
    9501: 98/03/19: Re: Linux and Xchecker
    10641: 98/06/08: XC4000: post routing "customization"
Thomas Scherrer:
    4217: 96/09/30: Z8000 microprocessors, C cross-compiler and a PLZ/ASM assembler
Thomas Schmidt:
    34909: 01/09/13: FPGA--? huh
Thomas Siebert:
    53175: 03/03/05: Re: Square root implementation
    53213: 03/03/06: Re: altera quartusII help
    53758: 03/03/21: Re: EPXA1 Development Kit Getting Started
Thomas Sitt:
    20020: 00/01/24: How to access standard sdram ?
Thomas St.Pierre:
    1775: 95/08/30: PCI, ACTEL&ALTERA,any experience?
Thomas Stanka:
    33312: 01/07/23: Re: a newbie question -- The cost between 3-to-1 MUX and 4-to-1 MUX
    33424: 01/07/26: Re: prospects for tiny FPGA supercomputer?
    34087: 01/08/14: Re: Q: Revision and Database Control for FPGA Designs
    34088: 01/08/14: Re: Quicklogic and Actel floorplanning?
    34131: 01/08/15: Re: Q: Revision and Database Control for FPGA Designs
    34389: 01/08/23: Re: Logic Emulation
    34427: 01/08/24: Re: Actel Pad locations
    34776: 01/09/07: Re: cannot replace 'if' with 'case' ???
    35634: 01/10/12: Re: PWM Signal in VHDL ?
    35768: 01/10/17: Re: System Gates
    35875: 01/10/22: Re: Verilog vs. VHDL
    36558: 01/11/12: Re: Incrementing counter from state-machine
    36607: 01/11/13: Re: Incrementing counter from state-machine
    36946: 01/11/27: Re: Which vendor to choose
    38077: 02/01/04: Re: asic vs. fpga
    38302: 02/01/11: Re: asic vs. fpga
    38452: 02/01/15: Re: Falling edge in PLD
    39252: 02/02/05: Re: Xilinx synthesis tools
    39732: 02/02/18: Re: Handel-C, System-C, Formal verification ???
    39930: 02/02/22: Re: Here is an argument and can anyone help me out
    40303: 02/03/05: Re: Converting VHDL netlist to EDN/EDF/XNF
    45235: 02/07/16: Re: I want to buy 4 Xilinx FPGA
    45236: 02/07/17: Re: Sensitivity list (VHDL) & FPGA pin assignment
    46790: 02/09/09: Re: Fault tolerant FPGA design
    46923: 02/09/12: Re: C/C++ to Verilog/VHDL ?!
    46925: 02/09/12: Re: Fault tolerant FPGA design
    46966: 02/09/13: Re: scan insertion is easily feasible
    47644: 02/10/01: Re: DFT , Design For Test HELPPPPP
    47886: 02/10/07: Re: C\C++ to VHDL Converter
    51301: 03/01/10: Re: Power usage of CLOCK in FPGA
    52576: 03/02/13: Re: FPGA for audio record and playback???
    53424: 03/03/13: Re: RESET --- Synchronous Vs Asynchronous
    53487: 03/03/14: Re: RESET --- Synchronous Vs Asynchronous
    54398: 03/04/10: Re: $4000 FPGAs
    57070: 03/06/23: Re: What's the difference between ASIC and FPGA?
    57137: 03/06/24: Re: Programmable Delay (not clock driven)
    58162: 03/07/16: Re: what are libraries for??
    58900: 03/08/04: Re: Showing my ignorance of VHDL again...
    59295: 03/08/14: Re: Actel Core PCI
    61995: 03/10/15: Re: vhdl code
    62119: 03/10/19: Re: BGA packages in high vibration environments
    62624: 03/11/03: Re: Some FPGA questions
    62700: 03/11/05: Re: Building the 'uber processor'
    64616: 04/01/09: Re: Synthesis in VHDL vs. Verilog
    64904: 04/01/15: Re: Gray encoding for FSM
    65136: 04/01/20: Re: BIST FPGA testing - Applying a test vector
    65207: 04/01/22: Re: BIST FPGA testing - Applying a test vector
    65360: 04/01/26: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
    65859: 04/02/08: Re: Artificial Intelligence/FPGA
    66411: 04/02/19: Re: Design Verification tools and Resources ?
    66738: 04/02/25: Re: difference btw H/W & S/W implementations !!
    67670: 04/03/16: Re: Speed of Linux vs Solaris
    67793: 04/03/19: Re: Speed of Linux vs Solaris
    68176: 04/03/28: Re: study verilog or vhdl?
    68314: 04/04/01: Re: simulation time
    70030: 04/05/27: Tool to help detecting race conditions with asych inputs?
    70083: 04/06/01: Re: Tool to help detecting race conditions with asych inputs?
    70088: 04/06/02: Re: Tool to help detecting race conditions with asych inputs?
    70190: 04/06/08: Re: comp.arch.fpga: reset strategy
    70565: 04/06/20: Re: >Math Skills = >Engineer ?
    71061: 04/07/07: Re: *RANT* Ridiculous EDA software "user license agreements"?
    71062: 04/07/07: Re: *RANT* Ridiculous EDA software "user license agreements"?
    71133: 04/07/09: Re: *RANT* Ridiculous EDA software "user license agreements"?
    71452: 04/07/18: Re: FPGA in a Compact Flash format.
    71742: 04/07/29: Re: FPGA vs CPLD
    71744: 04/07/29: Re: FPGA vs CPLD
    71935: 04/08/03: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
    71987: 04/08/05: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
    75089: 04/10/26: Re: Bus interfaces & FSMs
    75354: 04/11/02: Re: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps.
    74282: 04/10/07: Re: IBM Paper with answer to FPGA vs ASIC comparisons
    75387: 04/11/04: Re: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps.
    75414: 04/11/05: Re: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps.
    76150: 04/11/26: Re: Searching for rad tolerant, non-volatile (once programmable) FPGA (or CPLD).
    76465: 04/12/03: Re: Searching for rad tolerant, non-volatile (once programmable) FPGA (or CPLD).
    78366: 05/01/31: Re: Actel A54SX72A - FF with clear and preset? Necessary for triple redundant register
    78439: 05/02/01: Re: Actel A54SX72A - FF with clear and preset? Necessary for triple redundant register
    78497: 05/02/02: Re: Actel A54SX72A - FF with clear and preset? Necessary for triple redundant register
    78918: 05/02/10: Re: ProAsic3 (PA3)
    79007: 05/02/11: Re: FPGA design problem
    80267: 05/03/03: Re: Need suggestion abt FFs without RST for pipelined datapath.
    80268: 05/03/03: Re: Fault Tolerant FPGA design
    83149: 05/04/25: Re: "Correct design" and practical trouble and simulation trouble but why
    83871: 05/05/09: Re: Which chip should I use?
    84516: 05/05/19: Re: Actel Designer on Linux
    84517: 05/05/20: Re: Coloring by clock?
    86565: 05/06/30: Re: Small FPGA
    86985: 05/07/11: Re: Search for FPGA
    92859: 05/12/07: Re: VERIFICATION AND TESTING
    93013: 05/12/11: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
    96643: 06/02/07: Re: why does speed grade effect VHDL program??
    97260: 06/02/20: Re: FPGA - software or hardware?
    98126: 06/03/05: Re: why use an FPGA when a CPLD will do ??
    98206: 06/03/07: Re: why use an FPGA when a CPLD will do ??
    99679: 06/03/27: Re: How to write compact DFF chain?
    100833: 06/04/19: Re: Multiple Independent Circuits on a Single FPGA
    100878: 06/04/20: Re: Multiple Independent Circuits on a Single FPGA
    100915: 06/04/21: Re: Multiple Independent Circuits on a Single FPGA
    101493: 06/05/02: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    102966: 06/05/24: Re: Verilog vs VHDL
    104258: 06/06/22: Re: keys to the Kingdom
    104578: 06/06/30: Re: Generic synthesis target in Synplify Pro
    104835: 06/07/07: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
    104849: 06/07/07: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
    106604: 06/08/15: Re: Reset asynchronous assertion synchronous deassertion
    108008: 06/09/04: Re: Qestion about the ability of synthesis
    108077: 06/09/05: Re: Qestion about the ability of synthesis
    108258: 06/09/07: Re: Qestion about the ability of synthesis
    108414: 06/09/11: Re: RESET Signals
    109013: 06/09/20: Re: What is the difference ?
    109836: 06/10/06: Re: An implementation of a clean reset signal
    109958: 06/10/09: Re: Antifuse, lower cost?
    109960: 06/10/09: Re: Antifuse, lower cost?
    110470: 06/10/16: Re: more than 90% occupancy in an Actel FPGA
    110512: 06/10/17: Re: more than 90% occupancy in an Actel FPGA
    110974: 06/10/26: Re: Jumps in FPGA implemented integrator
    111015: 06/10/26: Re: Jumps in FPGA implemented integrator
    111129: 06/10/29: Re: Jumps in FPGA implemented integrator
    111370: 06/11/02: Re: Rad-hard (neutron/SEU and space) tutorial?
    111561: 06/11/06: Re: Formal Logic Equivalent Check (LEC)
    112149: 06/11/17: Re: Synthesis size of Circuits?
    112258: 06/11/18: Re: Synthesis size of Circuits?
    112860: 06/11/29: Re: Hardware in the loop simulation for Altera design
    113203: 06/12/07: Re: FPGA : LIFO
    113315: 06/12/11: Re: About Unstable Operation of ACTEL(A3P1000)....
    114126: 07/01/05: Re: DC timing violation, what to do first?
    114225: 07/01/08: Re: (-1)*xn operation in FPGA
    114268: 07/01/10: Re: Delaying signal
    114557: 07/01/19: Re: Different Modelsim versions disagree in same backannotation!
    114857: 07/01/25: Re: On-chip randomness (V4FX)
    115772: 07/02/20: Re: ACTEL ProAsic Plus
    116386: 07/03/08: Re: FPGA Vs ASIC design and implementation
    116445: 07/03/09: Re: FPGA Vs ASIC design and implementation
    117110: 07/03/23: Re: multiple clock domain issues
    117399: 07/03/29: Re: RFC: Enhancing VHDL for OO, Randomization, Functional Coverage
    117822: 07/04/11: Re: Flip Flop problem (asynchronous or synchronous???? )
    119603: 07/05/23: Re: Design running on board but timing are not met
    120088: 07/05/31: Re: After PAR simulation, should I assume that it will work on FPGA board?
    123242: 07/08/20: Re: Globally Asynchronous in FPGA
    124377: 07/09/19: Re: help! ACTEL PROASIC PLUS clock buffer
    124418: 07/09/20: Re: help! ACTEL PROASIC PLUS clock buffer
    124475: 07/09/23: Re: help! ACTEL PROASIC PLUS clock buffer
    124476: 07/09/23: Re: help! ACTEL PROASIC PLUS clock buffer
    124581: 07/09/26: Bug in Synplify?
    124607: 07/09/27: Re: Bug in Synplify?
    124608: 07/09/27: Re: Bug in Synplify?
    124742: 07/10/02: Re: Bug in Synplify?
    124743: 07/10/02: Re: Bug in Synplify?
    125159: 07/10/16: Re: FPGA quiz: what can be wrong
    125279: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
    125518: 07/10/27: Re: FPGA vs ASIC
    125603: 07/10/29: Re: FPGA Configuration
    125638: 07/10/30: Re: FPGA vs ASIC
    125639: 07/10/30: Re: FPGA vs ASIC
    125647: 07/10/30: Re: FPGA vs ASIC
    125733: 07/11/01: Re: can i use dual edge or two clocks?
    125984: 07/11/11: Re: Non-volatile FPGA in a small package
    127150: 07/12/12: Re: Debugging designs that are running on FPGA
    127778: 08/01/07: Re: converting floating point number to integer and vice versa
    127833: 08/01/08: Re: Real examples of metastability causing bugs
    128531: 08/01/29: Re: My first Flash FPGA
    128573: 08/01/30: Re: ROM/LUT
    128631: 08/01/31: Re: FPGA in Telecommunications
    129023: 08/02/12: Re: ModelSim versus Active-HDL....redux
    129677: 08/03/02: Re: real to signed
    130457: 08/03/24: Re: Actel SX-A Timing Constraints Issues
    131230: 08/04/15: Re: Snythesis error
    131677: 08/04/28: Re: Debounce in Verilog?
    131787: 08/05/01: Re: asic gate count
    132269: 08/05/20: Re: SKEW greater than Time period of CLK
    132422: 08/05/26: Re: signal value at power up
    132461: 08/05/27: Re: signal value at power up
    132499: 08/05/28: Re: asic gate count
    132600: 08/06/02: Re: Checksums
    132665: 08/06/04: Re: Compare and update in same clock cycle synthesis problem
    132726: 08/06/05: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
    133331: 08/06/24: Re: Cycle-based or Event-based simulation?
    133399: 08/06/26: Re: synthesis error
    134703: 08/08/26: Re: AES decryption (ASIC)
    135168: 08/09/18: Re: Clock Enable safe?
    135391: 08/09/29: Re: if data moves faster faster than the Clock....
    135585: 08/10/08: Re: Actel constraints?
    135586: 08/10/08: Re: Another problem....
    136000: 08/10/26: Re: how to program virtex 4?
    136126: 08/11/02: Re: needs help on CLOCK
    136338: 08/11/11: Re: CPLD newbie questions
    136486: 08/11/18: Re: opinion about various code generators
    136604: 08/11/24: Re: distributed dual port RAM with asynchronous read in ACTEL
    136687: 08/11/30: Re: what is the difference between post-synthesis simulation and
    136689: 08/11/30: Re: simulation results is correct but synthesis result is not correct
    136918: 08/12/13: Re: Online C-to-FPGA tool
    136982: 08/12/16: Re: clock reducing leads what
    137036: 08/12/20: Re: FPGA partial/catastrophic failure mode question
    137125: 08/12/24: Re: DFFR using DFF (only, may be extra gates)
    137171: 08/12/30: Re: FPGA > ASIC
    137659: 09/01/26: Re: problem with test bench should be an easy one.
    139542: 09/04/02: Re: Maximum frequency
    141841: 09/07/12: Re: What is Clock Input? (Proofread)
    143613: 09/10/18: Re: FSM-states after reconf.
    144440: 09/12/07: Re: ASIC Prototyping
    144695: 09/12/23: Re: Strange behavior with serial ADC chip select and MISO pin
    145300: 10/02/05: Re: How good are Actel tools
    145724: 10/02/21: Re: System design in FPGA
    145771: 10/02/22: Re: FPGA platform??
    145804: 10/02/24: Re: FPGA platform??
    145860: 10/02/25: Re: FPGA platform??
    146710: 10/03/26: Re: Ring Oscillator -> counter differences
    148066: 10/06/18: Re: Programming the Actel Smartfusion Eval Kit in Linux
    148620: 10/08/09: Re: VHDL newbie- stuck just weeks before project submission
    148626: 10/08/10: Re: VHDL newbie- stuck just weeks before project submission
    149365: 10/10/19: Re: IO pin question
    149428: 10/10/25: Re: 0x80000000 Integer not supported??
    149946: 10/12/03: Re: FSM single process...BIG question
    150084: 10/12/10: Re: spacewire project on opencores.org
    150222: 11/01/03: Re: Error in Clock Divider!
    150223: 11/01/03: Re: Error in Clock Divider!
    150324: 11/01/10: Re: Low slewrate, abnormal current consumption.
    150523: 11/01/25: Re: FPGA changes behaviour when the resource's usage percentage changes
    150760: 11/02/09: Re: Designing in Altium
    150874: 11/02/18: Re: Simulation vs. Hardware mismatch
    151021: 11/03/01: Re: Question regarding bitstream generation
    151993: 11/06/20: Re: Sporadic simulation result with modelsim
    152018: 11/06/22: Re: Sporadic simulation result with modelsim
    152044: 11/06/27: Re: Sporadic simulation result with modelsim
    152717: 11/10/06: Re: VHDL connection problem
    152942: 11/11/03: Re: CSV pinout from Actel
    153025: 11/11/16: Re: Migrating to Actel Libero
    154378: 12/10/17: Re: My First CPU but.. one problem
    154379: 12/10/17: Re: My First CPU but.. one problem
    154551: 12/11/27: Re: VHDL expert puzzle
    154552: 12/11/27: Re: VHDL expert puzzle
    154556: 12/11/28: Re: VHDL expert puzzle
    154567: 12/11/28: Re: VHDL expert puzzle
    154594: 12/11/30: Re: VHDL expert puzzle
    154595: 12/11/30: Re: VHDL expert puzzle
    154596: 12/11/30: Re: VHDL expert puzzle
    154645: 12/12/10: Re: Is this Multicycle?
    154695: 12/12/19: Re: FPGA DSP basics: clock enable / new clock
    154708: 12/12/21: Re: FPGA DSP basics: clock enable / new clock
    155247: 13/06/18: Re: Ask about finding maximum and second's maximum number in array is given.
    155953: 13/10/20: Re: reset strategy FPGA Igloo
    155957: 13/10/22: Re: reset strategy FPGA Igloo
    155966: 13/10/29: Re: microsemi technical support
    155998: 13/11/05: Re: Verilog Binary Division
    156006: 13/11/06: Re: Verilog Binary Division
    156011: 13/11/08: Re: built in adc in fpga????
    156119: 13/11/29: Re: FPGA Cryptosystem
    156560: 14/04/30: Re: Synthesis / PAR options mess up design functionality
    156806: 14/07/03: Re: What use of Python, Perl in FPGA development?
Thomas Taranowski:
    153666: 12/04/11: XSpi_Transfer within interrupt context
Thomas Vogel:
    47096: 02/09/17: Re: C\C++ to VHDL Converter
Thomas W.:
    114744: 07/01/23: Re: ABEL to VHDL translate
Thomas W. Fry:
    19279: 99/12/09: FPGA Benchmarks
Thomas Wambera:
    30789: 01/04/29: Verilog + VHDL - and the other?
    36602: 01/11/13: Fast Fourier Transformation - camera data
    46771: 02/09/08: Re: I2C BUS
    47363: 02/09/24: Xilinx Cordic Core and Square Root...help
    47751: 02/10/03: Re: Xilinx Cordic Core and Square Root...help
Thomas Wesenberg:
    114745: 07/01/23: Re: ABEL to VHDL translate
Thomas Wollinger:
    45598: 02/07/29: secure FPGA
    45634: 02/07/30: Re: physical attacks (& secure FPGA) - some more questions
Thomas Womack:
    10493: 98/05/24: Re: FPGA-based CPUs (was Re: Minimal ALU instruction set)
    50401: 02/12/10: Re: Tiny Forth Processors
    50402: 02/12/10: State of the PCB world
    60363: 03/09/11: Re: The real history of computer architecture: the short form
    62671: 03/11/04: I/O on current FPGAs - deserialise first ??
    63095: 03/11/14: Re: Building the 'uber processor'
    63191: 03/11/17: Re: Is this a good starter kit?
    63476: 03/11/22: Re: Is this a good starter kit?
    65746: 04/02/05: European supplier of Xilinx chips
    65752: 04/02/05: Re: European supplier of Xilinx chips
    65794: 04/02/06: Re: Pricing, 101
    66129: 04/02/13: Sensible starter FPGA board
    66158: 04/02/13: Re: Sensible starter FPGA board
    68422: 04/04/04: Re: Logic required for multiplication
    69148: 04/04/28: Stupid question
    69919: 04/05/24: Re: Never right, always room for improvement
    70765: 04/06/27: Re: Xilinx ML310 Experience?
    70794: 04/06/28: Battle of the Vapours
    70798: 04/06/28: Re: Battle of the Vapours
    70874: 04/06/30: Re: Xilinx $99 Spartan-3 kit
    74347: 04/10/08: Daft modelsim question
    74493: 04/10/12: Interfacing from the analogue domain
    74500: 04/10/12: Re: Interfacing from the analogue domain
    75649: 04/11/11: Re: Where to find very basic FPGAs
    76023: 04/11/23: Re: 18x18 Multipliers - Spartan III
    76717: 04/12/09: Re: Open source FPGA EDA Tools
    76719: 04/12/09: Re: Getting Started With Simple Sound Synthesis
    76720: 04/12/09: Re: Open source FPGA EDA Tools
    81680: 05/03/30: Re: Dividing a 24 bit std_logic_vector by a decimal number
    81734: 05/03/30: Re: Out of Memory Error comes suddenly.
    81782: 05/03/31: Re: Dividing a 24 bit std_logic_vector by a decimal number
    81921: 05/04/04: Stupid question
    82078: 05/04/06: Re: Stupid question
    82079: 05/04/06: Re: Xilinx ISE Input Pins Problem
    83020: 05/04/21: Re: CAM for FPGA ...
    83031: 05/04/21: Re: CAM for FPGA ...
    83446: 05/04/30: Re: Median Filter for floating points
    83597: 05/05/03: Re: Multiply Accumulate FPGA/DSP
    83598: 05/05/03: Re: Multiply Accumulate FPGA/DSP
    85716: 05/06/14: Re: Somewhat OT - falling behind the times ...
    86418: 05/06/27: Re: Maintaining a Pipeline
    88502: 05/08/20: Re: Best FPGA for floating point performance
    88503: 05/08/20: Re: Best FPGA for floating point performance
    89312: 05/09/12: Re: future of antifuse fpgas?
    89643: 05/09/21: Re: Count "1" bit in bit stream
    90393: 05/10/12: Re: Question regarding FPGA startup ROMs
    90728: 05/10/19: Re: Implementation of 1024 point FFT in Actel FPGA
    98402: 06/03/09: Re: for all those who believe in ASICs....
    98450: 06/03/10: Re: FPGA imple. of aes
    98501: 06/03/11: Re: FPGA imple. of aes
    98917: 06/03/17: What will the next FPGA IP-blocks be?
    100234: 06/04/05: Re: Compressing DVI stream
    100779: 06/04/18: Re: Counting bits
    100949: 06/04/21: Re: Video circle generator
    101776: 06/05/06: Re: Opteron HT coprocessors
    101777: 06/05/06: Re: Xilinx 3s8000?
    101880: 06/05/08: Re: Xilinx 3s8000?
    101881: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
    101889: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
    101998: 06/05/09: Re: Xilinx 3s8000?
    103636: 06/06/07: Re: FlipChip BGA Conformal Coating
    103648: 06/06/07: Re: FlipChip BGA Conformal Coating
    104073: 06/06/18: Re: High speed differential to single ended
    104099: 06/06/19: Re: High speed differential to single ended
    104100: 06/06/19: Re: High speed differential to single ended
    104116: 06/06/19: Re: High speed differential to single ended
    106642: 06/08/16: Re: Large Spartan3 vs. Small V5
    114838: 07/01/25: Re: General Number Field Sieve in FPGA
    115642: 07/02/16: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
    119986: 07/05/30: Re: Inverse of a matrix
    120180: 07/06/02: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
    120333: 07/06/05: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer
    124839: 07/10/06: Re: Opteron performance tuning (for Quartus / Linux)?
    138495: 09/02/25: Re: mb-gcc producing incorrect code ???
    138754: 09/03/08: Re: Dual port RAM on Spartan
    142820: 09/09/02: Re: GF(233) example
    142832: 09/09/03: Re: GF(233) example
    142880: 09/09/05: Interfacing variable-speed functional units
    144157: 09/11/14: Re: New blog post on alphas in packagin
    145059: 10/01/23: Re: FPGA farm
    145568: 10/02/14: Re: 28nm FPGAs are coming...
    148869: 10/09/05: Re: Want to get into FPGA
    149810: 10/11/24: Re: Atom 6000C perspective, anyone?
    149915: 10/12/02: Re: Atom 6000C perspective, anyone?
    150428: 11/01/20: Re: Prime number testing on FPGA
    151013: 11/02/28: Re: regarding usage of IOBs and Warning XST 2036
    151015: 11/02/28: Re: regarding usage of IOBs and Warning XST 2036
    151038: 11/03/02: Re: Slice Usage
    151204: 11/03/15: Re: pcb&bitstream
    151228: 11/03/16: Re: pcb&bitstream
    152835: 11/10/26: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
    152852: 11/10/28: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
    152853: 11/10/28: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
    152864: 11/10/28: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
    153829: 12/06/01: Re: PRNG
    153832: 12/06/01: Re: PRNG
    153835: 12/06/01: Re: PRNG
    153841: 12/06/01: Re: PRNG
    154422: 12/10/28: Re: Altera delivery
Thomas Worsch:
    5089: 97/01/22: Question: XC4013E configuration in async. periph. mode
Thomas Zipper:
    14680: 99/02/11: Parity and flex10k
    22014: 00/04/12: parity - block ram
    25244: 00/09/01: Re: SYNOPSYS using BLOCK RAM (VIRTEX)
    31083: 01/05/11: Asynchronous Compare
    32173: 01/06/18: Re: PCI Config Address Space
    40174: 02/03/01: high-speed clock distribution/divider in a FPGA?
<thomas.b36@gmail.com>:
    98189: 06/03/06: Terminologie/knowledge issu
    98271: 06/03/07: Re: Terminologie/knowledge issu
    102961: 06/05/23: Config XCF04S using iMPACT
    120031: 07/05/31: Spartan 3E Starter Kit and EDK 8.2
<thomas.entner99@gmail.com>:
    153806: 12/05/24: Re: ITU656 to JPEG/Mpeg4 with Fpga?
    154090: 12/08/02: Re: how much costs the Artix 7 devices?
    155090: 13/04/08: Re: FPGA for large HDMI switch
    155133: 13/04/25: Re: Low cost and/or small size CPU in an FPGA
    155193: 13/05/26: Re: Development/Experimenter's kits
    155205: 13/06/04: Re: [ANN] XMODZ-Fast modulo reduction VHDL IPs
    155402: 13/06/25: Re: New soft processor core paper publisher?
    155410: 13/06/25: Re: New soft processor core paper publisher?
    155412: 13/06/25: Re: New soft processor core paper publisher?
    155428: 13/06/26: Re: New soft processor core paper publisher?
    155630: 13/07/30: Re: Lattice Announces EOL for XP and EC/P Product Lines
    156972: 14/08/09: LVDS problem - Black magic anyone?
    156974: 14/08/10: Re: LVDS problem - Black magic anyone?
    156982: 14/08/11: Re: LVDS problem - Black magic anyone?
    156997: 14/08/14: Re: LVDS problem - Black magic anyone?
<thomas.hedler@fen.baynet.de>:
    18322: 99/10/14: Estimating Gates in FPGA
<thomas.neitzel@gmail.com>:
    113616: 06/12/18: unexplainable Problem on Spartan 3
    113683: 06/12/19: Re: unexplainable Problem on Spartan 3
<thomas.schatz@hotmail.fr>:
    139374: 09/03/27: Where to find a xc6200 xilinx fpga?
<thomas.streuer@gmx.net>:
    128336: 08/01/22: Re: SRL16x2 in Virtex5
<thomasrt2008@gmail.com>:
    129546: 08/02/27: Xilinx's microblaze hangs when a timer interrupt occurs after a
ThomRScott:
    958: 95/04/04: Re: Neocad merges with Xilinx
    1044: 95/04/20: Re: Neocad merges with Xilinx
Thor Arne Johansen:
    10343: 98/05/13: Xilinx FGA Express
    11222: 98/07/27: Re: Shift Invarient Bit Transform
Thorsten Brandt:
    74387: 04/10/10: Xilinx : Memory-Compiler for DDR-1
Thorsten Bunte:
    22426: 00/05/09: Altera Megafunction in Exemplar Leonardo
    22716: 00/05/19: Printed magazines
    29432: 01/02/21: Re: Integrated Conf.EPROM / smaller Footprints?
    51307: 03/01/10: DLL/PLL with global clock net
    51401: 03/01/13: Re: DLL/PLL with global clock net
    51439: 03/01/13: Re: DLL/PLL with global clock net
    52352: 03/02/07: Byteblaster II
    52746: 03/02/20: Re: Quartus II problem
    53278: 03/03/10: Re: Cyclone power up problem
    53401: 03/03/12: Re: Cyclone power up problem
    53458: 03/03/13: Re: Cyclone power up problem
Thorsten Kiefer:
    129030: 08/02/13: floating point arithmetic in vhdl
    142584: 09/08/18: Re: Post sythesys vs FPGA board implementation
    142716: 09/08/27: program spartan3 under linux
    142747: 09/08/30: Re: program spartan3 under linux
    142754: 09/08/30: Re: program spartan3 under linux
    146460: 10/03/18: Spartan 3 Starter Kit Example
    146480: 10/03/19: Re: Spartan 3 Starter Kit Example
    146481: 10/03/19: Re: Spartan 3 Starter Kit Example
    146628: 10/03/24: Re: Spartan 3 Starter Kit Example
    153594: 12/04/03: Mandelbrot set on Spartan3
    153622: 12/04/05: Re: Mandelbrot set on Spartan3
    153627: 12/04/06: Re: Mandelbrot set on Spartan3
    154119: 12/08/13: My Spartan3 video
    154121: 12/08/13: Re: My Spartan3 video
    154136: 12/08/20: Re: My Spartan3 video
    154137: 12/08/20: Re: My Spartan3 video
    156769: 14/06/24: A new domain for FPGAs ? Function approximation
    156770: 14/06/24: Need help for freehdl
    156772: 14/06/24: Re: A new domain for FPGAs ? Function approximation
    156773: 14/06/24: Re: Need help for freehdl
    156777: 14/06/24: A free VHDL simulator
    156778: 14/06/24: Re: A new domain for FPGAs ? Function approximation
    156790: 14/06/25: Re: A free VHDL simulator
    156953: 14/08/04: Re: floating point synthesis on Xilinx FPGAs using ISE Webpack
Thorsten Klatt:
    57786: 03/07/07: Problem with user defined logicinterface in Nios
Thorsten Kukuk:
    9752: 98/04/03: Save status of XC6216
    9814: 98/04/07: Re: Synthesis tool for XC6200
thorsten mader:
    41001: 02/03/19: using carry logic
Thorsten Neumann:
    19226: 99/12/07: Problems with Leonardo Spectrum
Thorsten Trenz:
    42404: 02/04/23: Re: Prototyping Boards for Hobbyist CPU/System Designs
    43214: 02/05/16: Re: SPARTAN II - Master serial mode configuration problem
    44947: 02/07/08: Re: Newbie FPGA recommedation
    48410: 02/10/17: Re: Hobbyist FPGA
    51263: 03/01/09: Re: USB OPENCORE IP usage
    51403: 03/01/13: Re: USB OPENCORE IP usage
    52871: 03/02/25: Re: Xilinx FPGA on PCI board
    60941: 03/09/25: [ANN] New Prototyping boards speed Spartan-IIE FPGA development
    62382: 03/10/28: Re: Trenz-electronics (spartan2 development board) help?
    103516: 06/06/05: Re: FPGA board for USB experiments?
    115900: 07/02/24: Re: Small FPGA Dev Board with Ethernet
    128715: 08/02/05: Re: Possible CRC error on XC3S400 - now what?
    128769: 08/02/06: Re: Possible CRC error on XC3S400 - now what?
thranduil:
    144472: 09/12/09: Spartan 3E starter Kit
threehero:
    24531: 00/08/12: state encoding in Synplify!!!
    24561: 00/08/14: Re: state encoding in Synplify!!!
throned:
    143646: 09/10/19: Re: Digilent Nexys 2 Issue
thunder:
    152773: 11/10/21: FPGA development
    152776: 11/10/21: Re: FPGA development
thutt:
    134909: 08/09/06: Are Xilinx tools that bad, or am I missing something?
    134911: 08/09/06: Re: Are Xilinx tools that bad, or am I missing something?
    134926: 08/09/07: Re: Are Xilinx tools that bad, or am I missing something?
    134927: 08/09/07: Re: Are Xilinx tools that bad, or am I missing something?
    134928: 08/09/07: Re: Are Xilinx tools that bad, or am I missing something?
    134996: 08/09/09: Re: Are Xilinx tools that bad, or am I missing something?
    135210: 08/09/20: Is it possible to get an RTL netlist from Xilinx tools?
    135233: 08/09/22: Re: Is it possible to get an RTL netlist from Xilinx tools?
    135248: 08/09/23: Re: Is it possible to get an RTL netlist from Xilinx tools?
    135341: 08/09/27: Re: Is it possible to get an RTL netlist from Xilinx tools?
    135342: 08/09/27: Re: Is it possible to get an RTL netlist from Xilinx tools?
    135343: 08/09/27: Re: Is it possible to get an RTL netlist from Xilinx tools?
    135346: 08/09/27: Re: Is it possible to get an RTL netlist from Xilinx tools?
    135389: 08/09/29: Re: Low frequency clock generation - need help
    135467: 08/10/02: Re: Is it possible to get an RTL netlist from Xilinx tools?
    135468: 08/10/02: Re: WEBPACK for linux
    135469: 08/10/02: Re: Low frequency clock generation - need help
    135479: 08/10/03: Re: Low frequency clock generation - need help
    135482: 08/10/04: Re: Low frequency clock generation - need help
Thuy Pham:
    115489: 07/02/12: How to develop STM-16 framer in FPGA
    117494: 07/04/02: Standard PCI Xilinx board with Ethernet port
    117738: 07/04/09: Looking for Xilinx fpga board that works in Linux and has Ethernet card
    127566: 08/01/02: Looking for used spartan3 fpga board
    127923: 08/01/10: Purchasing IC components at a good price
Thyda Ly:
    143681: 09/10/21: EDK/DDR Problem with HTG-V5-DDR3-PCIE Development Board
TI:
    50768: 02/12/18: vlsi training in austria, greece, romania or hungary?
    51061: 02/12/29: Future of VLSI in developing countries
    51084: 02/12/30: VLSI training and prospects?
    51087: 02/12/30: VLSI training in Germany, the Balcans or Russia?
    52139: 03/02/02: Ip core pricing info
    52919: 03/02/25: VLSI outsourcing?
    53152: 03/03/04: Issues in Outsourcing?
    54271: 03/04/06: Testing engineering ability prior to work?
Tia:
    73928: 04/10/01: Re: luts are optimized away
Tiago Noronha:
    133554: 08/07/03: Constraints for router
tianhangchen:
    138744: 09/03/06: Re: IEEE1588
Tianlun:
Tiberio Fanti:
    58650: 03/07/30: Searching for SONET/SDH verification libraries
Tibo:
    91454: 05/11/07: Malloc on PowerPC on VirtexII pro
Tibor:
    41146: 02/03/21: cpga : Converting PAL design
Tibor Szolnoki:
    16363: 99/05/19: Need crack
    16957: 99/06/19: Synopsys FPGA Express vs. Compiler II
    16958: 99/06/19: Re: Synopsys FPGA Express vs. Compiler II
tider:
    30123: 01/03/23: Re: PLACE and ROUTE
    30161: 01/03/26: RAM read?
    30171: 01/03/26: Virtex II RLOC
tiderh:
    30737: 01/04/26: clock to pad timing
    30956: 01/05/04: timing simulation on Modelsim
    32714: 01/07/05: low skew in vertex II
Tier Logic:
    143679: 09/10/20: Done pin won't go high
    143695: 09/10/21: Re: Done pin won't go high
    146261: 10/03/10: Tier Logic introduces the world's first 3D FPGA
    146299: 10/03/10: Re: Tier Logic introduces the world's first 3D FPGA
    146316: 10/03/11: Re: Tier Logic introduces the world's first 3D FPGA
Ties Bos:
    16692: 99/06/03: Q: How to set a "dont touch" attribute?
    23747: 00/07/06: Q: high fanout distribution
TigerMole:
    50889: 02/12/21: CPLD ISP cables (newbie question)
    51360: 03/01/12: Bidirectional Digital Switch in CPLD ?
    51436: 03/01/13: Re: Bidirectional Digital Switch in CPLD ?
    51473: 03/01/14: Re: Bidirectional Digital Switch in CPLD ?
    53242: 03/03/07: Xilinx ISP Header
    53246: 03/03/07: Re: Xilinx ISP Header
    53784: 03/03/23: Re: Leonardo Spectrum: Synthesis without optimization
TigerSatish:
    96181: 06/01/31: Re: starting MacroBlaze development
    96161: 06/01/31: URGENT: Need to get the USB Balster Driver for the UNIX machines which has FT245BM
    96182: 06/01/31: Re: URGENT: Need to get the USB Balster Driver for the UNIX machines which has FT245BM
    96238: 06/02/01: Re: URGENT: Need to get the USB Balster Driver for the UNIX machines which has FT245BM
    96239: 06/02/01: For our Study We need STM1, 4 , 16 Block diagram where to get it
    96521: 06/02/05: Re: For our Study We need STM1, 4 , 16 Block diagram where to get it
<tigerz@my-dejanews.com>:
    11610: 98/08/26: CPLD/FPGA software
    11631: 98/08/27: Re: CPLD/FPGA software
tigtag04@yahoo.com.au:
    72237: 04/08/11: How big is LEON on Virtex2?
Till Wollenberg:
    116542: 07/03/12: Initialization of arrays in Verilog
    116552: 07/03/12: Re: Initialization of arrays in Verilog
Tilmann Reh:
    147213: 10/04/19: Re: Need to run old 8051 firmware
    147255: 10/04/21: Re: Need to run old 8051 firmware
    147268: 10/04/21: Re: Need to run old 8051 firmware
<tiltonjones@my-dejanews.com>:
    10929: 98/07/04: Consultants
tim:
    18020: 99/09/24: Re: Synopsys inside Foundation 2.1i does not infer fast-adder
    87218: 05/07/19: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87256: 05/07/20: Re: July 20th Altera Net Seminar: Stratix II Logic Density
    87257: 05/07/20: Re: July 20th Altera Net Seminar: Stratix II Logic Density
Tim:
    7143: 97/08/06: Re: MEM_CS16 timing on ISA BUS
    19669: 00/01/07: Earn Extra Cash
    21401: 00/03/21: Re: Clock nets using non-dedicated resources
    21408: 00/03/21: Virtex Secondary Clock Nets
    21440: 00/03/22: Re: Foundation 2.1: Prevent Optimizing away of open Signals/Pins ?
    21744: 00/03/30: Re: Global clock nets. Can I use it for signal other than clock.
    21856: 00/04/04: Re: MaxPlus9.5 License and Fitter problems
    21879: 00/04/05: Re: MaxPlus9.5 License and Fitter problems
    21881: 00/04/05: Re: MaxPlus9.5 License and Fitter problems
    22704: 00/05/18: Apex LVDS
    25311: 00/09/06: Cypress Delta39K availability
    31027: 01/05/09: Re: Virtex-2 - experiences ?
    31038: 01/05/10: Re: Virtex-2 - experiences ?
    31156: 01/05/13: Re: How to make FPGA_Express recongize my RAM code? Urgent.....
    31275: 01/05/16: Re: Ideas for Faster XILINX compilations ?
    31478: 01/05/27: Re: New Xilinx data book Frisbee
    31582: 01/05/30: Re: Is anybody using FPGAs for scientific computing?
    32677: 01/07/04: Re: Downloading FPGA (XBN) bitstream to XCV50E
    32679: 01/07/04: Re: Problem with resolution functions
    32700: 01/07/05: Re: Driven clocks balancing
    32761: 01/07/08: Re: Problem with resolution functions
    33388: 01/07/25: Re: Silo-3 Demo Program Crashes onDell 4100
    33477: 01/07/27: Re: Xilinx/Altera "behavioral" verilog
    33486: 01/07/28: Re: Xilinx/Altera "behavioral" verilog
    33491: 01/07/28: Re: The Continuing Saga of Installing Modelsim software on Windows 2000 Pro
    33492: 01/07/28: Re: SRL16
    33530: 01/07/29: Re: Xilinx/Altera "behavioral" verilog
    33738: 01/08/03: Re: Spartan II and asynchronous memory interface
    33778: 01/08/04: Re: how to replicate the Logic through VHDL attribut ?
    33833: 01/08/06: Re: Bitgen persist option
    33890: 01/08/07: Re: Looking for a Particular Used Book
    34226: 01/08/16: Re: Internal clock skew when using DLL
    34230: 01/08/16: Re: fpga with the smallest i/o setup and hold requirement
    34309: 01/08/20: Re: Spartan2 5V PCI IO
    34351: 01/08/22: Re: hardware damage to a Virtex or Spartan-II?
    34352: 01/08/22: Re: Logic Emulation
    34371: 01/08/22: Re: Logic Emulation
    34383: 01/08/23: Re: Virtex-II place and route : Design doesn't route
    34404: 01/08/23: Re: Testbench book
    34475: 01/08/27: Re: Some questions about Spartan2 (& a bug report for XST sp8)
    34575: 01/08/29: Re: Version Control
    34593: 01/08/30: Re: Version Control
    34594: 01/08/30: Re: Big SR in Virtex-E
    34614: 01/08/30: Re: XCV800 : Jbits
    34623: 01/08/31: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC?
    34659: 01/09/02: Re: Problems with Synthesis and Implementation in Xilinx Foundation 3.3i SP8(ELITE)
    34890: 01/09/13: Re: Block RAM initialization
    34893: 01/09/13: Re: convert
    34913: 01/09/13: Re: convert
    34915: 01/09/13: Re: configuration latency for PCI bridge in FPGA
    34926: 01/09/14: Re: Foundation 3.1i REINSTALLATION
    34927: 01/09/14: Re: Looking for knowledge on CORDIC, division, correlators, TSBs, sorting, and path-delay handling
    34929: 01/09/14: Re: Virtex-E1600 unsupported?
    34930: 01/09/14: Re: Clock Multiplication
    34970: 01/09/17: Re: INIT attribute of SRL16E
    34986: 01/09/17: Re: how to simulate virtex components?
    34988: 01/09/17: Re: INIT attribute of SRL16E
    35027: 01/09/18: Re: Synplify BUFG instantiation bug
    35043: 01/09/18: Re: Synplicity logic replication
    35044: 01/09/19: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
    35070: 01/09/20: Re: Synplify BUFG instantiation bug
    35128: 01/09/22: Re: Analyse static timing for Xilinx FPGA
    35141: 01/09/24: Re: Analyse static timing for Xilinx FPGA
    35142: 01/09/24: Forcing a LUT logic function (was Synplicity logic replication)
    35197: 01/09/25: Re: Virtex2 slice level instantiation in verilog question
    35236: 01/09/26: Re: Spartan-IIE?
    35322: 01/09/28: Re: Spartan-IIE?
    35358: 01/10/01: Re: Forcing a LUT logic function (was Synplicity logic replication)
    35448: 01/10/05: Re: Barrel Shifter
    35460: 01/10/06: Re: Xilinx Spartan-II slave parallel configuration
    35547: 01/10/10: Re: Handel-C
    35614: 01/10/11: Re: Virtex-2 maximum clock speed
    35617: 01/10/12: Re: Virtex-2 maximum clock speed
    35649: 01/10/12: Re: High level synthesis will never work well :)
    35668: 01/10/13: Re: Reassemble a BGA560 device
    35669: 01/10/13: Re: future Xilinx products wish list ...
    35692: 01/10/13: Re: How to instantiate I/O port with both registered input and output?
    35693: 01/10/13: Re: future Xilinx products wish list ...
    35707: 01/10/15: Re: future Xilinx products wish list ...
    35715: 01/10/15: Re: future Xilinx products wish list ...
    35906: 01/10/23: Re: Verilog vs. VHDL
    36155: 01/10/31: Re: Field Programmable Logic in energy poor environments
    36430: 01/11/08: Re: FPGA Wish list
    36499: 01/11/09: Re: Decoupling capacitors on Virtex II
    36785: 01/11/20: Re: what is the price of XC2V2000?
    36984: 01/11/28: Re: Creating a jitter free clock
    37425: 01/12/10: PC Cache size. Was: ModelSim performance on Solaris/sparc and Linux/x86
    37722: 01/12/19: Re: Kindergarten Stuff
    37879: 01/12/22: Re: How do i get rid of "Signal xx has a multisource" warning in Xilinx webpack ?
    38308: 02/01/11: Re: Avoid routing through a certain area (Xilinx)
    38858: 02/01/26: Re: Problem with Altera programmer
    38937: 02/01/28: Re: Books on DSP
    38948: 02/01/28: Spartan II power-up current - again
    38961: 02/01/29: Re: Xilinx webpack
    38968: 02/01/29: Re: Xilinx webpack
    38985: 02/01/29: Re: glitchless clock enable/disable in spartanII
    39006: 02/01/30: Re: glitchless clock enable/disable in spartanII
    39036: 02/01/30: Re: function synthesis.
    39068: 02/01/31: Re: ROM dimension question
    39098: 02/01/31: Re: WebPack 4.1 ISE Errors with Insight Demo files
    39099: 02/01/31: Re: The LUT puzzle, Iam on the way
    39100: 02/01/31: Re: {72,64} extended hamming ECC
    39221: 02/02/04: Re: Virtex-II and SDRAM Controller at 133MHz
    39223: 02/02/04: Re: Destroying a CPLD by JTAG
    39242: 02/02/05: Re: Destroying a CPLD by JTAG
    39424: 02/02/08: Re: CLKDLL x4 problem
    39443: 02/02/10: Re: Xilinx synthesis tools
    39464: 02/02/11: Re: I think it's a synthesis bug
    39487: 02/02/11: SRL/Logic - was Altera's new family Stratix
    39504: 02/02/12: Re: Pseudorandom Bitstream
    39524: 02/02/12: Re: Xilinx EDIF to BIT transation
    39525: 02/02/12: Re: Making Altera development quicker
    39629: 02/02/15: Re: Create a bit stream (BIT file) from an NCD file?
    39686: 02/02/15: Re: SpartanXL & VHDL -- free software?
    39722: 02/02/17: Re: Virtex-II and SDRAM Controller at 133MHz
    39862: 02/02/21: Re: CLKDLL x4 problem
    39885: 02/02/21: Re: EDIF to .bit file conversion for Xilinx Spartan XCS10
    39886: 02/02/21: Re: EDIF IN A VHDL PROJECT (kcpsm.edn) in ISE4.1
    39887: 02/02/21: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
    39904: 02/02/22: Re: Problems : INOUT not allowed, alternatives
    39938: 02/02/22: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
    40027: 02/02/25: Re: Is it possible to have an output FF in IOB, but a tri-state control FF outside of IOB?
    40170: 02/03/01: Re: Comparison between two FPGAs- what is decisive factor?
    40171: 02/03/01: Re: Synopsys Design Compiler
    40450: 02/03/07: Re: exceeding 2GB limits in xilinx
    40494: 02/03/08: Re: exceeding 2GB limits in xilinx
    40535: 02/03/09: Xilinx Download Cable Connectors
    40614: 02/03/11: Re: FPGA download fails
    40615: 02/03/11: Re: floating pins
    40616: 02/03/11: Re: Xilinx Download Cable Connectors
    40736: 02/03/14: Re: Synthesis tools comparison?
    40799: 02/03/15: Re: Universal FPGA Programmer
    40800: 02/03/15: Re: powerpc in virtex2pro
    40854: 02/03/17: Re: just bought...
    40895: 02/03/17: Re: That vs Which // Common confusion among engineer writers
    40985: 02/03/19: Re: 1,5V power supply?
    41006: 02/03/19: Re: Unused I/Os + External Clock on Virtex II
    41025: 02/03/19: Re: A petition for Synplify's new fature (FPGA synthesis tool)
    41026: 02/03/19: Re: Constraint File NET syntax
    41069: 02/03/20: Re: FPGA or Micro-controller in Lowpower designs?
    41072: 02/03/20: Re: Constraint File NET syntax
    41073: 02/03/20: Re: Constraint File NET syntax
    41107: 02/03/21: Re: Possibility of RTL and Gate-level simulation dont match?
    41201: 02/03/22: Re: simple Free FPGA tool
    41269: 02/03/24: Re: A petition for Synplify's new fature (FPGA synthesis tool)
    41426: 02/03/27: Partial Reconfiguration (was: GREAT availability on Coolrunner)
    41488: 02/03/30: Re: Xilinx : Mixed-languages design?
    41542: 02/04/02: Re: Laying out the design
    41606: 02/04/03: Re: Compiler library ...
    41608: 02/04/03: Re: Xilinx makesrc
    41671: 02/04/04: Re: hand placement
    41708: 02/04/05: Re: Design a crystal oscillator in a Xilinx XCR3256XL
    41817: 02/04/08: Re: XST Synthesis tool
    41871: 02/04/09: Re: Low-cost FPGA + processor board?
    41872: 02/04/09: Re: Tying Virtex II unused pins to GND???
    42034: 02/04/13: Re: Slave serial loading of spartan II bitstream
    42035: 02/04/13: Re: new to fpga's need insight
    42235: 02/04/18: Re: 1000 I/O Pins -- What is cheapest FPGA?
    42251: 02/04/18: Re: fpga limitation
    42253: 02/04/19: Re: problem installing xilinx foundation 3.1 on a P4
    42309: 02/04/20: Re: Source code for a NIOS instruction set simulator?
    42310: 02/04/20: Re: fpga limitation
    42311: 02/04/20: Re: Xilinx Programmable World 2002 - Review
    42312: 02/04/20: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
    42329: 02/04/20: Re: Xilinx Easypath- Selling parts with known defects
    42394: 02/04/22: Re: Xilinx Programmable World 2002 - Review
    42424: 02/04/23: Re: Xilinx Easypath- Selling parts with known defects
    42479: 02/04/25: Re: Using 74HCT245N between Spartan-II and ISA
    42513: 02/04/26: Re: Freeware EDIF viewer
    42514: 02/04/26: Re: Xilinx Easypath- Selling parts with known defects
    42523: 02/04/26: Re: Newbie with signals
    42524: 02/04/26: Hot stuff from John Cooley's newsletter
    42570: 02/04/28: Re: SpartanII design considerations...
    42584: 02/04/28: Re: SpartanII design considerations...
    42648: 02/04/30: Re: fpga limitation
    42693: 02/05/01: Re: Xilinx Easypath- Selling parts with known defects
    42695: 02/05/01: Re: EDIF parser (perl)
    42710: 02/05/01: Re: Newbie--Where to start learning?
    42727: 02/05/01: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
    42832: 02/05/04: Re: Xilinx 2GB limit... something has to be done
    42994: 02/05/09: Re: Transistor Counts for Xilinx FPGAs
    43097: 02/05/14: Re: Architecture for high-level reconfigurable computing
    43098: 02/05/14: Re: Architecture for high-level reconfigurable computing
    43150: 02/05/14: Re: Architecture for high-level reconfigurable computing
    43183: 02/05/15: Re: Altera/Quartus II: unconditional loop?
    43247: 02/05/17: Re: Architecture for high-level reconfigurable computing
    43264: 02/05/17: Re: Architecture for high-level reconfigurable computing
    43520: 02/05/22: Re: 50Mhz driven - Overheat by Program?
    43552: 02/05/23: Re: Time for a new computer. Suggestions?
    46118: 02/08/20: Re: rising_edge detector?
    46696: 02/09/06: Re: C/C++ to Verilog/VHDL ?!
    47357: 02/09/24: Re: Altera Cyclone low-cost FPGA chips?
    47742: 02/10/03: Re: C\C++ to VHDL Converter
    47811: 02/10/04: Re: TCP/IP in FPGA
    47826: 02/10/04: Re: TCP/IP in FPGA
    47975: 02/10/09: Re: Why can Xilinx sw be as good as Altera's sw?
    47976: 02/10/09: Re: LPT voltage level and Xilinx CPLD programming?
    48009: 02/10/09: Re: Why can Xilinx sw be as good as Altera's sw?
    48158: 02/10/12: Re: Why can Xilinx sw be as good as Altera's sw?
    48281: 02/10/15: Re: VHDL v. Verilog, Xilinx v. Altera.
    48310: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48391: 02/10/17: Re: Xilinx microblaze vs. picoblaze
    48460: 02/10/18: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48466: 02/10/18: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    48612: 02/10/22: Re: Ms-DOS formatting in an CompactFlash card?
    48694: 02/10/23: Re: Ms-DOS formatting in an CompactFlash card?
    48760: 02/10/24: Re: Xilinx POS Power On Surge Current
    48820: 02/10/25: Re: Pin locking Virtex 2 FPGA
    48928: 02/10/27: Re: Xilinx POS Power On Surge Current (... the Starbucks connection)
    49211: 02/11/05: Re: C\C++ to HDL Converter, why not HDL -> C instead
    49514: 02/11/14: Cool LED Flasher
    49621: 02/11/18: Re: Virtex is the 4th Xilinx Fpga generation
    50238: 02/12/06: Re: meaning of system gates vs. logic gates?
    50461: 02/12/11: Re: Tiny Forth Processors
    50519: 02/12/12: Re: Tiny Forth Processors
    50597: 02/12/13: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    50626: 02/12/14: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    50627: 02/12/14: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    50628: 02/12/14: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    50629: 02/12/14: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    50630: 02/12/14: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    50650: 02/12/16: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
    50950: 02/12/23: Combinatorial clock source question
    50984: 02/12/24: Re: Combinatorial clock source question
    51115: 03/01/02: Re: Xilinx Gate Counts
    51284: 03/01/10: Re: Virtex-II Pro misfire?
    51333: 03/01/10: Re: Power usage of CLOCK in FPGA
    51493: 03/01/14: Re: SChematic design approach compared to VHDL entry approach
    51495: 03/01/15: Clock routing in Virtex/E/II
    51550: 03/01/16: Re: SChematic design approach compared to VHDL entry approach
    51852: 03/01/23: Re: VHDL or Verilog?
    51868: 03/01/24: Re: VHDL or Verilog?
    52018: 03/01/29: Re: XC3020 .nph
    52444: 03/02/10: Re: Virtex-II Pro PowerPC cache memory as main program/data storage?
    52565: 03/02/13: Re: Easy links to Xilinx documentation
    53937: 03/03/27: Re: Tristate pins + Inputs => External Pullup ?
    53950: 03/03/28: Re: Tristate pins + Inputs => External Pullup ?
    54025: 03/03/31: Re: Xilinx announces 90nm sampling today!
    54212: 03/04/05: Re: Xilinx announces 90nm sampling today!
    54674: 03/04/15: Re: Xilinx has released SpartanIII
    54782: 03/04/18: Re: spartan2e vs cyclone
    55739: 03/05/18: Mini solder masks - was Re: I want a 800 k gates FPGA in 40 pin DIL
    56542: 03/06/09: Re: Logical analyzer via USB or printer port
    56666: 03/06/11: Re: XC95288 programming problem
    56748: 03/06/13: Re: Analog signals connected to xilinx spartan2
    56776: 03/06/14: Re: Power consumed in a non configured FPGA?
    57312: 03/06/27: Spartan2e variable input threshold
    57531: 03/07/02: Re: SPARTAN-3 vs. VIRTEX-II
    57532: 03/07/02: Re: why so many problems Xilinx ?
    58262: 03/07/18: Re: Graduation Day: My first 4-layer PCB
    60271: 03/09/09: Re: Original (5V) Xilinx Spartan ?
    60276: 03/09/09: Re: opinions are OK
    60315: 03/09/10: ABEL help needed
    60839: 03/09/23: Re: Regarding XC6216
    61076: 03/09/27: Re: FPGA implementation of a lexer and parser - feasible?
    61077: 03/09/27: Re: Graphics rendering
    61245: 03/10/01: Re: Ask the hotline, you may be surprised and pleased
    61578: 03/10/07: Re: More RPM / RLOC fun
    61618: 03/10/07: Re: More RPM / RLOC fun
    61747: 03/10/10: Re: Implementing a fast cache in Altera Cyclone
    61748: 03/10/10: Re: Digesting runs of ones or zeros "well"
    61926: 03/10/15: Re: Xilinx Logic Handbook
    61938: 03/10/15: Re: SpartanXL
    62370: 03/10/28: Re: Electronic Dice VHDL Program
    62403: 03/10/29: Re: Are clock and divided clock synchronous?
    62405: 03/10/29: Re: Logic Analyzer for FPGAs
    63428: 03/11/21: Re: Xilinx legacy situation
    63553: 03/11/25: Re: Slightly unmatched UART frequencies
    64201: 03/12/19: Re: Spartan3 availability
    64210: 03/12/20: Re: Spartan3 availability
    65810: 04/02/06: Re: Pricing, 101
    65849: 04/02/08: Re: Pricing, 101 and bananas
    66093: 04/02/12: Dual 7segment decoder in ABEL
    66242: 04/02/16: Re: Do Xilinx Fix Their Prices?
    66678: 04/02/25: Re: Spartan 3 - avaliable in small quantities?
    67413: 04/03/11: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
    67609: 04/03/15: Re: Which should I use, Floorplanner or PACE
    67904: 04/03/22: Virtex-4
    67905: 04/03/22: Re: 64bit cpu on Xilinx
    68945: 04/04/22: Re: PLL and DLL
    69197: 04/04/29: Re: best machine setup for ISE ??
    69762: 04/05/19: Re: Nios II Going Live...
    69815: 04/05/21: Re: Never right, always room for improvement
    69917: 04/05/24: Re: Never right, always room for improvement
    69994: 04/05/26: Re: SDRAM controller
    70538: 04/06/19: Re: compressing Xilinx bitstreams
    70722: 04/06/24: Re: Xilinx's interp on EDIF properties
    70848: 04/06/30: Re: simprim X_FF component
    70869: 04/06/30: Re: Xilinx $99 Spartan-3 kit
    70927: 04/07/01: Re: Compact FPGA Board?
    70948: 04/07/02: Re: Compile 30% of my multipliers with LUT?
    71272: 04/07/13: Re: Xilinx Virtex 4
    71283: 04/07/13: Re: Xilinx Virtex 4
    71579: 04/07/22: Re: 32-channel PC-based logic analyzers
    71610: 04/07/24: VHDL model of Xilinx's Rocket I/O MGT
    71615: 04/07/25: Re: VHDL model of Xilinx's Rocket I/O MGT
    72127: 04/08/09: Re: Now I am really confused!
    73729: 04/09/28: Re: fast adder and equal
    73813: 04/09/29: Re: Pricing info for Synplify Pro Xilinx...
    73961: 04/10/01: Re: FPGA vs ASIC area
    73563: 04/09/24: Re: Mr. Greenfield, spare us the propaganda !
    75103: 04/10/26: Re: PCBs for modern FPGAs.
    74459: 04/10/12: Re: IBM Paper with answer to FPGA vs ASIC comparisons
    76118: 04/11/25: Re: PCI interrupt negation
    77047: 04/12/21: Re: making an fpga hot
    77424: 05/01/06: Re: Tracking down HardWired History
    77426: 05/01/06: Re: is this memory implementation synthesizeable?
    78021: 05/01/23: Google citation top 10 for FPGA
    78038: 05/01/23: Re: Google citation top 10 for FPGA
    79755: 05/02/24: Re: embedded 2005 in Nuernburg
    81970: 05/04/05: Re: Open PowerPC Core?
    85908: 05/06/17: area group constraint for quadranting
    85912: 05/06/17: Re: area group constraint for quadranting
    95352: 06/01/22: Re: Xilinx padding LC numbers, how do you feel about it?
    96309: 06/02/02: BGA central ground matrix
    97083: 06/02/16: Re: DIFF_OUT buffer example
    98249: 06/03/07: Re: for all those who believe in ASICs....
    98804: 06/03/16: Re: for all those who believe in ASICs....
    99387: 06/03/23: Re: Lattice FPGA
    99419: 06/03/24: Xilinx - was Lattice FPGA
    99599: 06/03/27: Re: XST takes unusually long
    102701: 06/05/19: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
    102893: 06/05/23: Re: xilinx pricing discrepancy
    102978: 06/05/24: Re: Verilog vs VHDL
    103001: 06/05/24: Re: ISE 8.1SP4 PN doesnt start
    103108: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
    103258: 06/05/29: Re: Remote Application delivery for EDA
    103354: 06/05/31: Re: Virtex-4FX12MM: Any hardware MAC address accessable?
    103364: 06/05/31: Re: Virtex-4FX12MM: Any hardware MAC address accessable?
    103428: 06/06/01: Re: clockless arbiters on fpgas?
    104497: 06/06/28: Re: DDR2 at 125MHz or lower with Cyclone2
    105248: 06/07/19: Re: Virtex 4, LVDS I/O: Sanity check please
    105450: 06/07/23: Re: Why 8 clock trees in Xilinx Spartan-3 device?
    105763: 06/07/31: Re: 100m JTAG cable
    107685: 06/08/31: Re: fastest FPGA
    109268: 06/09/22: Re: Fast Platform for ISE?
    109998: 06/10/09: Re: a clueless bloke tells Xilinx to get a move on
    110215: 06/10/12: Re: Virtex 4 RAMB16 Clock: optional inverter missing
    111024: 06/10/27: Re: Problema when upgrading from Xilinx 8.1 to Xilinx 8.2
    111143: 06/10/30: Re: Taking forever to synthesise (XILINX ISE 8.1i)
    111203: 06/10/31: DSP48 carry logic for multi-precision addition
    111369: 06/11/02: Re: DSP48 carry logic for multi-precision addition
    111467: 06/11/03: Re: DSP48 carry logic for multi-precision addition
    111471: 06/11/03: Re: DSP48 carry logic for multi-precision addition
    111480: 06/11/03: Re: DSP48 carry logic for multi-precision addition
    111504: 06/11/04: Re: Scientific Computing on FPGA
    111914: 06/11/13: Re: DSP48 carry logic for multi-precision addition
    112086: 06/11/16: Re: 8080 FSGA model in an FPGA
    112107: 06/11/16: Re: 8080 FSGA model in an FPGA
    112166: 06/11/17: Re: combinatorical divide by 2 in FPGA
    113164: 06/12/07: Re: Spartan-3A launched
    113426: 06/12/13: Re: Virtex4 : cleaner signals?
    113611: 06/12/18: Re: electrical level conversion
    113744: 06/12/20: Re: Manually creating a LUT in VHDL
    114042: 07/01/03: Re: Surface mount ic's
    114166: 07/01/06: Re: Surface mount ic's
    114425: 07/01/15: Re: Surface mount ic's
    114575: 07/01/19: Re: Phasse Detector
    114981: 07/01/28: Re: How to make an internal signal embedded deep in hierarchy to
    115062: 07/01/30: Re: 1 Gbps - state of the art?
    115069: 07/01/30: Re: USB 2.0 Streaming using FPGAs
    115360: 07/02/08: Re: Replacing/emulating an asynchronous FIFO
    115570: 07/02/14: Re: Typical clock frequencies of FPGA designs
    115622: 07/02/15: Can't be too thin or too rich or have too many ground pads
    115644: 07/02/16: Re: Do you like Virtex-5 ?
    115648: 07/02/16: Re: Do you like Virtex-5 ?
    115649: 07/02/16: Re: Do you like Virtex-5 ?
    115698: 07/02/17: Re: Do you like Virtex-5 ?
    115961: 07/02/26: Re: Making a 32KB BRAM block, virtex-4
    115985: 07/02/27: Re: Spartan-3AN
    116006: 07/02/27: Re: Spartan-3AN
    116007: 07/02/27: Re: Making a 32KB BRAM block, virtex-4
    116011: 07/02/28: Re: Spartan-3AN
    116015: 07/02/28: Re: Making a 32KB BRAM block, virtex-4
    116017: 07/02/28: Re: Spartan-3AN
    116039: 07/02/28: Re: XC3S400 and XC3S500E in PQ208
    116065: 07/03/01: Re: XC3S400 and XC3S500E in PQ208
    116066: 07/03/01: Re: what does a 'blank check' do exactly
    116067: 07/03/01: Re: Making a 32KB BRAM block, virtex-4
    116101: 07/03/01: Re: what does a 'blank check' do exactly
    116129: 07/03/02: Re: Bypass caps, X2Y and 'puddles'.
    116131: 07/03/02: Re: apologia
    116192: 07/03/04: Re: Large power planes vs. power islands vs. slits for decoupling
    116194: 07/03/04: Re: Large power planes vs. power islands vs. slits for decoupling
    116281: 07/03/06: Re: Large power planes vs. power islands vs. slits for decoupling
    116299: 07/03/06: Re: How to implement pipeline in this case?
    116471: 07/03/09: Re: Xilin X-Fest Lunacy
    116625: 07/03/14: Re: Heatsink on FPGA?
    116708: 07/03/15: Re: Xilinx Netlist
    116999: 07/03/21: Re: Off topic: what is the purpoe of XST?
    117135: 07/03/23: Re: Altera introduces Cyclone III devices, 'ships' 65nm
    117439: 07/03/31: Re: ModelSim VHDL Pragmas
    117966: 07/04/14: Re: Order of the synchronous operations
    118143: 07/04/18: Re: Seeking the solutions of high speed interconnection for the long
    118569: 07/04/30: Re: Xilinx software quality - how low can it go ?!
    119226: 07/05/15: Re: How low DDR2 Clock Frequency can be? To make it work on FPGA.
    120062: 07/05/31: Re: 180 differential inputs each 800Mbps using V5
    120253: 07/06/04: Re: ise9.1 : partitions with edif flow
    120275: 07/06/04: Re: Lattice XP2 finally announced
    120293: 07/06/05: Re: ise9.1 : partitions with edif flow
    152056: 11/06/29: Re: Delta-Sigma in an FPGA
    152101: 11/07/07: Re: Spartan3DSP TphDCM spec question
    152117: 11/07/10: Re: VHDL rollover of counter
    152164: 11/07/15: Re: ASM vs. RAM
    152819: 11/10/26: Re: Peter Alfke has passed away
    153055: 11/11/24: XC7V2000T, the perfect Thanksgiving gift
    155850: 13/10/01: Re: Lattice diamond / MachXO2
    155854: 13/10/01: Re: Lattice diamond / MachXO2
    156465: 14/04/09: Re: Lattice MachXO3L - is it available anywhere ?
    156833: 14/07/06: Re: ECP5 support in Latest Diamond 3.2 IDE from Lattice ( 64-bit
    157370: 14/12/01: FPGA on Android
Tim (one of many):
    120297: 07/06/05: Re: Lattice XP2 finally announced
    120329: 07/06/05: Re: Lattice XP2 finally announced
    120331: 07/06/05: Re: ARM in FPGA's?
    120900: 07/06/19: Re: synthesis translate_off
    121406: 07/07/03: Re: Spartan-3e JTAG no device id
    121414: 07/07/03: Re: Spartan-3e JTAG no device id
    122005: 07/07/17: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
    123200: 07/08/20: Re: DDR controller - best device to perform
    124696: 07/09/30: Synplicity and the Xilinx MAP Memory Monster
    128447: 08/01/26: Re: Craignell FPGA DIP Module
    129241: 08/02/19: Re: FPGA Programming solution
    129418: 08/02/23: Re: Xilinx self-termination
    129542: 08/02/27: Re: How to connect FPGA to a ASIC Board?
    131036: 08/04/08: Re: 32 bit multiplier
Tim at this Newsgroup:
    68409: 04/04/03: Re: Schematic Edition Tool : Suggestions
    68784: 04/04/18: Re: Document State Machines?
Tim At This Newsgroup:
    51853: 03/01/23: Xilinx/Altera pricing
    51856: 03/01/23: Re: Xilinx/Altera pricing
Tim Boescke:
    25735: 00/09/18: Re: Good FPGA prototyping boards?
    25736: 00/09/18: Re: Good FPGA prototyping boards?
    26282: 00/10/10: Bidirectional IO with ispDesignEXPERT
    29727: 01/03/06: Re: SRAM fpga cell
    36240: 01/11/02: spartan synthesis with synopsis
    38008: 01/12/30: Re: How to generate .edn in Webpack ?
    55744: 03/05/18: Re: SID chip describtion
    55745: 03/05/18: Re: Interfacing cpld with eeprom, energy metering ic, real time clock
    55784: 03/05/20: Re: SID chip describtion
    55964: 03/05/25: Re: Newbie CPLD question
Tim Callahan:
    144: 94/08/31: Dynamic Incremental Reconfiguration
    158: 94/09/02: Re: Dynamic Incremental Reconfiguration
    1032: 95/04/19: Re: BLIF to XNF translator
    3206: 96/04/24: Re: On FPGAs as PC coprocessors
    17336: 99/07/21: Re: C language to programmable logic
    20011: 00/01/23: Re: Transmeta CM & Conf. Comp?
Tim Climber:
    144891: 10/01/12: .sopc example for PCI Express Development Kit, Stratix II GX Edition
tim colleran:
    64216: 03/12/20: Re: Spartan3 availability
    64660: 04/01/10: clarity on Gibson Guitar Story(ies)
Tim Conway:
    7226: 97/08/15: ISP Stories
    7269: 97/08/20: Re: ISP Stories
Tim Courtney:
    22571: 00/05/12: Xilinx Virtex SRL16
    23365: 00/06/23: Re: Looking for 'FREE' FPGA software
    23453: 00/06/26: Re: Looking for 'FREE' FPGA software
Tim Davis:
    13398: 98/11/30: Re: Will XILINX survive?
    13406: 98/12/01: Re: HELP, Tool selection
    15330: 99/03/18: PCI: Xilinx Core in Virtex versus Lucent Orca 3TP12
    15360: 99/03/19: Re: FPGA Express FSM Synthesis Concern
    15446: 99/03/24: Re: Current State of FPGA-based PCI Interfaces?
    15461: 99/03/24: Re: Free Xilinx Vendor Tools ... NOT :-(
    15462: 99/03/24: Re: Free Xilinx Vendor Tools ... NOT :-(
    15732: 99/04/10: Re: FPGAs with ECL-compatible I/Os
    15744: 99/04/11: Re: FPGAs with ECL-compatible I/Os
    15733: 99/04/10: Re: viterbi/trellis decoder
    15855: 99/04/16: Re: std_logic_arith
    15892: 99/04/19: Re: High speed reconfigurability
    16307: 99/05/14: Re: Synchronizer design?
    17300: 99/07/19: Re: License sharing for synopsys/cadence/modeltech
    18096: 99/09/29: IEEE 1076.6 Synthesis standard dialog
Tim Eccles:
    2238: 95/11/08: Re: Xilinx Configuration Memory Hacking
    2854: 96/02/17: Re: JAVA and beer
    2984: 96/03/08: Re: Reconfigurable Computing Languages
    3426: 96/05/28: Re: WEIRD NOISE PROBLEM WITH XILINX XC3064 - can anyone help?
Tim Forcer:
    3715: 96/07/19: CPLD Failure
    4010: 96/09/03: Re: Looking for s/w to generate test vectors
    4011: 96/09/03: No such thing ....
    4538: 96/11/11: Re: Async with FPGA?
    5509: 97/02/21: Re: Q: Search Engines for Electronic Parts?
    6200: 97/04/25: Re: Call for participation, Advanced PLD & FPGA Day UK and Sweden
    6243: 97/05/02: Re: New Lattice (is)pLSI Resynthesis Server now online
    6335: 97/05/16: Re: Scientific American article on FPGAs
    6425: 97/05/23: Re: Cheap way to develop for FPGAs?
    6586: 97/06/04: Re: ECL FPGA Demo at DAC
    7018: 97/07/23: Re: Production testing of Design with CPLD's
    7024: 97/07/24: Re: Why fast message delete in this group?
    7054: 97/07/28: Re: Dates (was: fast delete)
    7255: 97/08/19: Re: ISP Stories
    7294: 97/08/22: Re: ISP Stories
    7469: 97/09/15: Re: Q: Lattice Synario and ISPLSI1048
    7494: 97/09/17: Re: AMD PAL design change
    7805: 97/10/17: Re: Download Cable for In-System programming of LATTICE ispLSI, ....
    7806: 97/10/17: [Reposted due to Enlow UCE cancel]: Re: Download Cable for In-System programming of LATTICE ispLSI, ....
    8134: 97/11/20: Re: What is the difference between CPLD and FPGA ?
    8329: 97/12/09: Re: A suggestion for Xilinx
    8675: 98/01/19: Re: Vantis Enters FPGA Market Unveiling New Variable-Grain-Architecture Devices With Industry Leading Performance
    9960: 98/04/17: Re: state machine
    10699: 98/06/11: Re: How about Lattice ispLSI?
    10742: 98/06/15: Re: old PLDShell software wanted
    11219: 98/07/27: ANNOUNCE: Design Entry Workshop
    11466: 98/08/17: Data I/O Chiplab and NT
    13355: 98/11/30: PCB rules for Xilinx ICs
    13509: 98/12/07: Re: PCB rules for Xilinx ICs
    13532: 98/12/08: Re: ALTERA isp cable
    13639: 98/12/15: Re: XESS FPGA Board?
    13644: 98/12/16: Fast *Industrial* 22V10?
    13685: 98/12/18: Re: Fast *Industrial* 22V10?
    13959: 99/01/05: Re: 22V10 Metastability - my 2c
    15451: 99/03/24: Re: DIY Xilinx Download Cable
    15702: 99/04/09: Re: Xilinx Download Serial Cable
    15701: 99/04/09: FAQ
    15785: 99/04/14: Re: Lattice
    19225: 99/12/07: Re: hobbyist friendly pld?
    19348: 99/12/15: Re: hobbyist friendly pld?
    20614: 00/02/16: Using JTAG on XC4k
    20855: 00/02/24: Re: Using JTAG on XC4k
    22172: 00/04/28: Re: FPGA price vs Size
    23017: 00/06/09: ANNOUNCE: Call for Contributions
    24077: 00/07/26: ANNOUNCE: Workshop on Embedded Systems & Hardware/Software co-design
    33680: 01/08/02: ANNOUNCE: Workshop on Computer based learning (etc) for electronics
    36819: 01/11/21: Re: ask for ispLSI 1016
    36820: 01/11/21: Re: GAL compiler
    46226: 02/08/22: ANNOUNCE: Workshop on Educational ECAD for FPGAs
    63378: 03/11/20: Xilinx legacy situation
    63419: 03/11/21: Re: Xilinx legacy situation
    63425: 03/11/21: Re: Xilinx legacy situation
    63498: 03/11/24: Re: Xilinx legacy situation
    63507: 03/11/24: Re: Xilinx legacy situation
Tim Good:
    80959: 05/03/15: Creating own RPMs using Xilinx ISE
    81286: 05/03/21: Re: DDR simulation
    81437: 05/03/23: Re: Problem writing Pinouts on Webpack
    92173: 05/11/23: Re: Design Implementation in Xilinx XST
    92231: 05/11/24: Re: case statement fault
Tim Gordon:
    27624: 00/11/30: FC II & Xilinx libraries macros
    27726: 00/12/05: Re: FC II & Xilinx libraries macros
Tim Green:
    4361: 96/10/19: Re: help Flex 10K configuration
Tim Hart:
    35287: 01/09/27: Re: Orcad symbol for a Virtex II
Tim Hogard:
    57838: 03/07/08: Copy Altera Config EPC2 via JTAG?
    58469: 03/07/24: Re: Pricing question....
Tim Hove:
    25156: 00/08/29: Using a FPGA as I/O expansion on embedded PC ??
Tim Hubberstey:
    4386: 96/10/23: Re: VHDL for Xilinx designs?
    4396: 96/10/24: Re: VHDL for Xilinx designs?
    5191: 97/01/30: Re: FPGA Lab.
    14070: 99/01/11: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10
    14087: 99/01/12: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10
    14994: 99/03/02: Re: Under-clocking SDRAM
    33655: 01/08/01: Re: BlockRAM architecture
    36396: 01/11/08: Re: "Illegal assignment" message, NEED HELP, PLEASE!!!
    36421: 01/11/08: Re: Hex numbers in VHDL
    36480: 01/11/09: Re: Counter detects both edge of clock?? (verilog)
    36636: 01/11/13: Re: Place your orders....
    37806: 01/12/20: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
    40857: 02/03/17: Re: just bought
    55153: 03/04/28: Re: ModelsimSE5.6/5.7 crashes with ISE5.1i
    58880: 03/08/04: Re: opencores.org - Question on project licensing?
    66832: 04/02/27: Re: DPRAM issue
    82662: 05/04/15: Re: Functional vs, Timing
    83348: 05/04/28: Re: Synplify warning CL209
Tim Jaynes:
    27012: 00/11/07: Re: Spartan2 macros in WebPACK
    27013: 00/11/07: Re: FFT LogiCore
    27075: 00/11/09: Re: Spartan2 macros in WebPACK
    27076: 00/11/09: Re: Non routable design
    27093: 00/11/10: Re: Non routable design
    27095: 00/11/10: Re: VHDL: FFS in IOBs
    27169: 00/11/13: Re: Webpack 3.2WP3.x from Xilinx is useless
    27219: 00/11/15: Re: BUFT conflict with LOC
    27667: 00/12/01: Re: xilinx NGDanno
    27736: 00/12/05: Re: Gate Level Simulation Questions
    29011: 01/02/01: Re: vector / edif format / LeonardoSpectrum
    29753: 01/03/07: Re: ERROR in Xilinx softaware !
    29843: 01/03/13: Re: sample code for JTAG configuration of Virtex, Spartan II?
    30528: 01/04/12: Re: How to use clock generator in Vertex-e?
    30529: 01/04/12: Re: Is this realistic?
    30899: 01/05/02: Re: Newbie
    31099: 01/05/11: Re: SpartanII: non clock pad drives clock net ?
    31222: 01/05/15: Re: CLKFX of DCM stops working.
    31410: 01/05/22: Re: LFSR Taps for 64 bit registers?
    33894: 01/08/07: Re: URL for XILINX's free 314-page design and sythesis guide
    33895: 01/08/07: Re: URL for XILINX's free 314-page design and sythesis guide
    49195: 02/11/04: Re: tips for cutting down on slice usage in a VirtexII
Tim Johansen:
    7333: 97/08/27: Re: VHDL Synthesis for Linux?
Tim Kennedy:
    12554: 98/10/15: Re: PCI target code
Tim Kippen:
    20025: 00/01/24: FPGA to manage serial DAQ?
Tim Lee:
    48184: 02/10/13: Xilinx VirtexII peripheral code.. can't open
Tim Lin:
    12798: 98/10/30: Buy ic component on line
Tim Lindquist:
    471: 94/11/29: Re: Should I jump to Actel when using Synopsys/Altera?
    3849: 96/08/09: Re: Quick question for Model Tech. experts:
Tim McBrayer:
    150594: 11/01/27: Re: Wow! No TestbenchWow!
Tim McCaffrey:
    12815: 98/10/30: Re: New free FPGA CPU
    146862: 10/03/30: Re: Which is the most beautiful and memorable hardware structure in a
    146966: 10/04/05: Re: Which is the most beautiful and memorable hardware structure in a ?CPU?
Tim McCoy:
    85125: 05/06/06: Xilinx + ModelSim XE Linux
    85144: 05/06/06: Re: Xilinx + ModelSim XE Linux
Tim McManamon:
    7628: 97/09/29: Job Opportunities With A Hot California Company
Tim Michaels:
    73285: 04/09/17: Statix II vs. Virtex 4
Tim Morlion:
    120118: 07/06/01: ise9.1 : partitions with edif flow
Tim Nicolson:
    32474: 01/06/27: linking Logiboxes
    48483: 02/10/18: log calculation
    48484: 02/10/18: Re: log calculation
    48485: 02/10/18: Re: log calculation
    48486: 02/10/18: Re: log calculation
    49854: 02/11/22: hardware image processing - log computation
    49977: 02/11/27: Microblaze, OPBs, ZBTs and other animals
Tim O:
    12090: 98/09/28: Re: Cypress CPLDs
    12091: 98/09/28: Re: I2C controller references needed!
    12279: 98/10/07: Altera's reply to request for Max+Plus II under Linux
    13646: 98/12/16: Re: Dedicated pin in ALTERA 10K familly
    13689: 98/12/18: VHDL books (seeking)
Tim O'Connell:
    32840: 01/07/10: Re: assigning signals with Altera Max+PlusII vhdl
    33228: 01/07/19: Re: assigning signals with Altera Max+PlusII vhdl
    35790: 01/10/17: Re: Linux tools
Tim Olson:
    10501: 98/05/25: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
    11516: 98/08/20: Re: vector product minimization problem
    11526: 98/08/20: Re: vector product minimization problem
    52040: 03/01/29: Re: GNU C for custom processor
    52975: 03/02/27: Re: picoChip - DSP as fast as an FPGA - is this for real
Tim Ottley:
    39395: 02/02/08: Xilinx DCM question anyone? (or Peter if he is there?)
    39402: 02/02/08: Re: Xilinx DCM question anyone? (or Peter if he is there?)
Tim P:
    127099: 07/12/11: Re: Xilinx ise 9.2i clean up project files
Tim Pagden:
    52811: 03/02/23: Re: Timing diagram input
Tim Plant:
    47413: 02/09/25: FPDP
Tim Pope:
    131403: 08/04/21: Celoxica RC1000
    131443: 08/04/21: Re: Celoxica RC1000
Tim Riemann:
    45771: 02/08/05: Soundchip?
    45784: 02/08/06: Re: Soundchip?
    45785: 02/08/06: Re: Soundchip?
    45796: 02/08/06: Re: Soundchip?
    45797: 02/08/06: Re: Soundchip?
Tim Schneider:
    187: 94/09/15: Re: Lattice ISP software: really bad or just different?
    670: 95/02/01: emacs mode for AHDL? VHDL?
    1123: 95/05/02: Re: Is anybody using FPGA's to do PCI interfaces?
    2548: 95/12/30: Re: Need help: Actel "bibuf" working with Quicksim II (Men 8.4)
    3089: 96/03/29: Re: MTI VHDL simulation w/ Xilinx
Tim Sheen:
    2455: 95/12/07: Re: Median filter
Tim Shoppa:
    13251: 98/11/21: Re: CPUs: Big Endianness vs Small Endianness
    22658: 00/05/16: Re: SMT 7 segment display ??
    22671: 00/05/17: Re: SMT 7 segment display ??
    56092: 03/05/28: Re: Nois generator - project
    97518: 06/02/23: Re: Input stage for VHF frequency counter in an FPGA?
tim simpson:
    25854: 00/09/23: Re: memory interface trouble...
    43462: 02/05/22: Re: Using Impact with XCR5064 coolrunner?
    50443: 02/12/11: Re: Tiny Forth Processors
    50493: 02/12/12: Re: Tiny Forth Processors
    74565: 04/10/14: Re: EP1C12 or XC3S400?
Tim Sinkins:
    39081: 02/01/31: Re: Java or bytecode processors??
Tim Stewart:
    36498: 01/11/09: 18V8Z and Philips SNAP compiler
Tim Tait:
    7505: 97/09/18: Re: Can 3.3v Xilinx drive CMOS?
Tim Tuan:
    20700: 00/02/18: protocol implementations
    20722: 00/02/18: Xilinx 9500 CPLD
Tim Tyler:
    10534: 98/05/28: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
    10569: 98/05/31: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
    10606: 98/06/05: Re: minimalist FPGA - C API for FPGA
    10618: 98/06/06: Re: minimalist FPGA - C API for FPGA
    11125: 98/07/20: Re: Partial reprogramming
    11158: 98/07/21: Re: Partial reprogramming
    11833: 98/09/12: Re: New Evolutionary Electronics Book
    13387: 98/11/30: Re: Will XILINX survive?
    13390: 98/11/30: Re: Will XILINX survive?
    13402: 98/12/01: Re: Will XILINX survive?
    13759: 98/12/22: Re: MP3 and FPGA's
    15344: 99/03/19: Re: Reconfigurable computing thesis on the web
    15401: 99/03/22: Re: Reconfigurable computing thesis on the web
    15572: 99/03/31: Re: PAMette for Rapid Prototyping
    15869: 99/04/17: Re: High speed reconfigurability
    16433: 99/05/21: Re: High Speed Reconfigurability
    16452: 99/05/23: Re: High Speed Reconfigurability
    16453: 99/05/23: Re: High Speed Reconfigurability
    16479: 99/05/25: Re: High Speed Reconfigurability
    16525: 99/05/26: Re: High Speed Reconfigurability
    16548: 99/05/27: Re: High Speed Reconfigurability
    16561: 99/05/28: Re: High Speed Reconfigurability
    16604: 99/05/29: Re: Evolutionary computation
    16685: 99/06/02: Re: Evolutionary computation
    16705: 99/06/03: Re: Evolutionary computation
    16706: 99/06/03: Re: Evolutionary computation
    16790: 99/06/08: Re: Evolutionary computation
    16805: 99/06/09: Re: Evolutionary computation
    16928: 99/06/17: Re: Evolutionary computation
    16829: 99/06/11: Re: Virtex Boards
    17722: 99/08/27: Re: Virtex dev boards
    17746: 99/08/29: UK programmable logic companies
    17836: 99/09/09: Re: Virus virtex_arch.zip in file?
    18142: 99/10/03: Re: Reconfigurable FPGAs-- A query on this..
    19333: 99/12/14: Re: Virtex boards
    20003: 00/01/22: Re: Transmeta CM & Conf. Comp?
    20144: 00/01/28: Re: ARM core?
    20262: 00/02/03: Re: Can hobbyist buy altera in uk?
    20713: 00/02/18: Re: Suggested prototyping boards < $200
    20888: 00/02/25: Re: A FPGA hickup
    21054: 00/03/04: Re: Comment on Atmel AT40K ?
    21055: 00/03/04: Re: Comment on Atmel AT40K ?
    21259: 00/03/14: Re: I need parallel processor SIMULATOR
    21742: 00/03/30: Re: Virtex bitstreams wanted for compression study
    30192: 01/03/27: Re: FPGA based Neural Networks
    50616: 02/12/14: Re: Tiny Forth Processors
    50617: 02/12/14: Re: Tiny Forth Processors
Tim Verstraete:
    67189: 04/03/08: Xilinx IPCORE compilation error (DA FIR)
    78617: 05/02/04: EDK + user ip : can't find library
    87651: 05/07/27: chipscope/impact Virtex4 problem
    87680: 05/07/28: Re: chipscope/impact Virtex4 problem
    87684: 05/07/28: Re: chipscope/impact Virtex4 problem
    88067: 05/08/08: warning for ODDR primitive?
    89194: 05/09/07: ISE7.1 SP4: proble and chipscope problem
    89226: 05/09/08: [XST] FSM extraction question
    89229: 05/09/08: Re: FSM extraction question
    90420: 05/10/12: IDELAYCTRL floorplanner/fpga editor/pace problem
    90454: 05/10/13: Re: IDELAYCTRL floorplanner/fpga editor/pace problem
    91144: 05/10/31: [xst]:clk information question
    92873: 05/12/08: [ISE7.1] Equivalent register removal + register duplication + register balancing
    102832: 06/05/22: [Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins
    102834: 06/05/22: Re: DDR2 SDRAM controller + dual purpose pins
    102859: 06/05/22: Re: [Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins
    102866: 06/05/22: Re: DDR2 SDRAM controller + dual purpose pins
    103082: 06/05/25: Re: ChipScope and the FPGA Editor ILA command
    103162: 06/05/26: Re: FPGA : FFT
    103224: 06/05/29: Re: DDR2 SDRAM controller + dual purpose pins
    104175: 06/06/20: Synplicity PREMIER
    106975: 06/08/23: Re: Xilinx FPGA editor error ISE8.2
    110282: 06/10/13: [ISE8.2] DIFF_TERM and unused pin
    114091: 07/01/04: [XST 8.2.3] DSP48 inference multiply/add
    114093: 07/01/04: Re: [XST 8.2.3] DSP48 inference multiply/add
    114094: 07/01/04: Re: [XST 8.2.3] DSP48 inference multiply/add
    114661: 07/01/22: Re: what happened to modular design in ISE9
    127466: 07/12/27: Re: Xilinx XST questions
Tim Warland:
    6381: 97/05/20: Re: Fast comparator
    6382: 97/05/20: Re: FPGA gate counting: No truth in advertising
    6384: 97/05/20: Re: Problem in Leonardo synthesis targetting Altera
    6460: 97/05/26: Re: Best way to learn VHDL?
    6650: 97/06/09: Re: XC6200 Gate Count
    7035: 97/07/25: Re: FPGA design tools
    7055: 97/07/28: Re: Should Xiling have more local clock nets?
    7104: 97/07/31: Re: PCI burst transfers
    7137: 97/08/05: Re: Are 2 PCs better than One?
    7268: 97/08/20: Re: LogiBLOX components in VHDL?
    7829: 97/10/20: Re: Synopsys, XACT, XC4000: CLB estimates
    8100: 97/11/17: Re: What is the difference between CPLD and FPGA ?
    8099: 97/11/17: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
    9837: 98/04/08: Re: FLEX 10K : FPGA or CPLD
    9940: 98/04/15: Re: Synplicity
    9988: 98/04/21: Re: XNF to EDIF utility
    10611: 98/06/05: Re: Non-periodic clock
Tim Warnes:
    17580: 99/08/11: UART
    17687: 99/08/24: Parallel in Serial out
    17692: 99/08/24: Re: Parallel in Serial out
    17706: 99/08/25: Re: Parallel in Serial out
Tim Watkins:
    8365: 97/12/10: Re: Need a fast ADC
Tim Wescott:
    67165: 04/03/07: Re: Implementing a reliable counter inside SDRAM memory mapped device
    70494: 04/06/17: Re: compressing Xilinx bitstreams
    81169: 05/03/18: Re: Which HDL?
    81266: 05/03/20: Re: RS 232 receiver using spartan 3 board
    81314: 05/03/21: Re: question about salary
    82932: 05/04/19: Re: College Project
    87391: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87392: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87793: 05/08/01: Re: Best Practices to Manage Complexity in Hardward/Software Design?
    87893: 05/08/03: Re: System Engineering in the R/D World
    87906: 05/08/03: Re: System Engineering in the R/D World
    90719: 05/10/19: MAC Architectures
    90725: 05/10/19: Re: MAC Architectures
    90758: 05/10/20: Re: MAC Architectures
    90894: 05/10/24: Re: a few questions
    90938: 05/10/25: Re: a few questions
    91151: 05/10/31: Re: Integrator
    91657: 05/11/10: Re: fpga speed logic/density MIPS/FLOPS as compared to general purpose
    91746: 05/11/11: Re: Factory Mutual Approvable Sealed Lead Acid Battery
    91924: 05/11/16: Re: UART CORE FOR NIOS
    92024: 05/11/19: Re: Asynchronous design
    92420: 05/11/29: Re: first time managing a project
    92424: 05/11/29: Re: first time managing a project
    93546: 05/12/23: Re: Can somone work on the pci express project?
    93621: 05/12/26: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar
    93787: 05/12/30: Re: Can some give me some advice?
    93824: 05/12/31: Re: basic DSP with FPGA
    93919: 06/01/03: Re: basic DSP with FPGA
    93961: 06/01/03: Re: Using posedge and negedge causing me grief
    94189: 06/01/06: Re: CRC error correction
    95104: 06/01/20: Re: Constellation symbol to bit's soft-probability?
    95108: 06/01/20: Re: need for a group FAQ?
    96106: 06/01/30: Re: TI Technical screening phone interview
    96610: 06/02/07: Re: why does speed grade effect VHDL program??
    96615: 06/02/07: Re: why does speed grade effect VHDL program??
    96836: 06/02/11: Re: using FPGA in control field
    96857: 06/02/11: Re: using FPGA in control field
    97117: 06/02/16: Re: Need some Advice, please
    97312: 06/02/20: Re: Is FPGA code called firmware?
    97379: 06/02/21: Re: Is FPGA code called gateware?
    97380: 06/02/21: Re: Is FPGA code called firmware?
    98589: 06/03/13: Re: Why does Xilinx hate version control?
    98622: 06/03/13: Re: Why does Xilinx hate version control?
    99144: 06/03/20: Re: Fixed vs Float ?
    99146: 06/03/20: Re: Fixed vs Float ?
    99210: 06/03/21: Re: Fixed vs Float ?
    99239: 06/03/21: Re: Fixed vs Float ?
    99376: 06/03/23: Re: Number of taps for a FIR
    100421: 06/04/08: Re: Compiler to FPSLIC
    100449: 06/04/09: Re: Compiler to FPSLIC
    100796: 06/04/18: Re: How to connect FPGA and =?ISO-8859-15?Q?=B5C?=
    103531: 06/06/05: Re: MIL Qualified RTOS for PowerPc 405
    104084: 06/06/18: Re: Newbie to FPGA
    105378: 06/07/20: Re: system design
    105657: 06/07/27: Re: OT (2nd try): do you get paid for your travel time?
    106019: 06/08/05: Re: verilog versus vhdl
    106516: 06/08/14: Re: Crystal input for FPGA
    106945: 06/08/22: Re: Running DDR below the min frequency
    107505: 06/08/29: Re: Undergrad project-8051 specifications??
    107507: 06/08/29: Re: Undergrad project-8051 specifications??
    107931: 06/09/02: Re: I do not know this !
    108448: 06/09/11: Re: VHDL or Verilog or SystemC?
    108459: 06/09/11: Re: VHDL or Verilog or SystemC?
    108952: 06/09/19: Re: Fixed-point FIR eyediagram problem
    110719: 06/10/20: Re: how to implement integrator?
    111241: 06/10/31: Re: filter design for low-pass
    111286: 06/10/31: Re: filter design for low-pass
    111310: 06/11/01: Re: filter design for low-pass
    112506: 06/11/23: Re: C++ on uBlaze : C++ Problems...Possible Xilinx bugs ?
    112685: 06/11/27: Re: I2C Controller implementation
    113448: 06/12/13: Re: Complex mixer
    113584: 06/12/17: Re: DSP or FPGA for high-speed image processing?
    114220: 07/01/07: Re: Basic questions about digital phase locked loop
    114811: 07/01/24: Re: Does xiling cpld's need a power supply bypass cap?
    115740: 07/02/18: Re: need help on our thesis proposal in our school.
    115840: 07/02/21: Re: Determine error in asynchronous signal
    118026: 07/04/16: Re: dual port memory from single port RAM.
    123821: 07/09/05: Re: high bandwitch ethernet communication
    123855: 07/09/06: Re: high bandwitch ethernet communication
    127293: 07/12/17: Re: global clock (gclk) input at xilinx virtex4 fpga
    131480: 08/04/22: Re: How to independently program the embedded PowerPC in a Virtex?
    139382: 09/03/27: Re: FIFO controlled loop, PLL, FLL or something else?
    139383: 09/03/27: Re: FIFO controlled loop, PLL, FLL or something else?
    141500: 09/06/25: Re: 720 Mhz IF Processing
    145981: 10/03/02: Re: Help with avoiding ground-loops on my PCB+external
    145982: 10/03/02: Re: Help with avoiding ground-loops on my PCB+external
    145984: 10/03/02: Re: Help with avoiding ground-loops on my PCB+external
    147218: 10/04/19: Re: Need to run old 8051 firmware
    148179: 10/06/25: Re: fooling the compiler
    148183: 10/06/25: Re: fooling the compiler
    148380: 10/07/16: Dumb VHDL Question -- Type Conversion
    148383: 10/07/16: Re: Dumb VHDL Question -- Type Conversion
    148385: 10/07/16: Re: Dumb VHDL Question -- Type Conversion
    148420: 10/07/21: Parallel Cable IV under Ubuntu Linux 10.04
    148421: 10/07/21: WTB: Xilinx USB JTAG Cable
    148435: 10/07/22: Re: Parallel Cable IV under Ubuntu Linux 10.04
    148436: 10/07/22: Re: WTB: Xilinx USB JTAG Cable
    148484: 10/07/27: Re: All Digital PLL
    148494: 10/07/27: Re: All Digital PLL
    148528: 10/07/29: Re: Data-path accuracy in IIR filters?
    148529: 10/07/29: Re: Data-path accuracy in IIR filters?
    148580: 10/08/03: Xilinx ISE Webpack and Pipeline Optimization
    148610: 10/08/05: Re: Vendor Tool Stability
    148682: 10/08/17: Re: Getting started with FPGA
    148687: 10/08/17: Re: Getting started with FPGA
    148688: 10/08/17: Re: Getting started with FPGA
    148722: 10/08/18: Re: Getting started with FPGA
    148792: 10/08/24: Re: Text compression Huffman Encoder and Decoder
    148887: 10/09/08: Divide clock by 4/5 in Spartan 3A?
    148888: 10/09/08: Re: Divide clock by 4/5 in Spartan 3A?
    148893: 10/09/08: Re: Divide clock by 4/5 in Spartan 3A?
    149060: 10/09/27: Re: FPGA For Image Processing[Economical]
    149150: 10/10/04: Re: Starting a career with FPGAs
    149151: 10/10/04: Re: Starting a career with FPGAs
    149359: 10/10/18: Re: Combined Microprocessor and FPGA
    149440: 10/10/25: Re: 0x80000000 Integer not supported??
    149473: 10/10/27: Re: FPGA and ethernet phy problem
    149692: 10/11/17: Re: Signal is connected to multiple drivers
    149752: 10/11/22: Re: Synthesis/place and route with Solid-State Drives
    149880: 10/11/30: Re: What should I use for highspeed/low latency communication beteen
    150012: 10/12/06: Re: Linux on Microblaze
    150030: 10/12/06: Re: Linux on Microblaze
    150045: 10/12/07: Re: Linux on Microblaze
    150323: 11/01/10: Re: FPGA to PHY/MAC chip
    150333: 11/01/10: Re: FPGA to PHY/MAC chip
    150351: 11/01/11: Re: FPGA to PHY/MAC chip
    150432: 11/01/20: Re: Overview for non-technicals.
    150433: 11/01/20: Re: Overview for non-technicals.
    150635: 11/01/30: Re: Discrete time PID control
    150641: 11/01/30: Re: Discrete time PID control
    150678: 11/02/02: Trivia: Where are you on the HDL Map?
    150716: 11/02/05: Re: Why is the Cyclone IV so expensive?
    150851: 11/02/16: Re: PLD suggestions for classroom use
    150859: 11/02/16: Re: Software process.
    150886: 11/02/19: Re: Mathematical definition of an FPGA
    151003: 11/02/28: Re: PLL Cyclone III vs PLL(DLL) Spartan-3AN
    151016: 11/02/28: Re: regarding usage of IOBs and Warning XST 2036
    151032: 11/03/01: Re: PLL Cyclone III vs PLL(DLL) Spartan-3AN
    151050: 11/03/02: Re: iir filter
    151105: 11/03/06: Re: iir filter
    151445: 11/04/08: Re: Do people do this by hand?
    151899: 11/06/02: Re: How could I get LUT-level netlist in Xilinx ISE?
    152051: 11/06/28: Re: Delta-Sigma in an FPGA
    152052: 11/06/28: Re: XST 13.1 explodes with generic of enum type with only one member
    152063: 11/06/29: Re: Delta-Sigma in an FPGA
    152089: 11/07/04: Re: Help with bidirectional interface of a FPGA with a uC
    152111: 11/07/07: Re: Spartan3DSP TphDCM spec question
    152116: 11/07/09: Re: Spartan3DSP TphDCM spec question
    152123: 11/07/11: Re: VHDL rollover of counter
    152145: 11/07/13: Re: Looking for a FPGA board
    152163: 11/07/14: Re: Looking for a FPGA board
    152179: 11/07/15: Re: ASM vs. RAM
    152236: 11/07/25: Re: synthesizing
    152250: 11/07/27: Re: FPGA security, Actel down, now Xilinx too?
    152286: 11/08/03: Re: Regarding process time calculation
    152287: 11/08/03: Re: Regarding process time calculation
    152288: 11/08/03: Re: Regarding process time calculation
    152297: 11/08/04: Re: Regarding process time calculation
    152307: 11/08/05: Re: Regarding process time calculation
    152309: 11/08/05: Re: Regarding process time calculation
    152317: 11/08/08: Re: elf of jpeg code to the microblaze
    152319: 11/08/08: Re: Newbie PCB
    152356: 11/08/11: Re: Help needed to emulate a microcontroller.
    152361: 11/08/11: Re: Help needed to emulate a microcontroller.
    152362: 11/08/11: Re: Help needed to emulate a microcontroller.
    152365: 11/08/11: Re: Help needed to emulate a microcontroller.
    152586: 11/09/15: Re: LFSR in xilinx 13.2
    152705: 11/10/04: Re: FPGA acceleration v.s. GPU acceleration
    152781: 11/10/21: Re: FPGA development
    152815: 11/10/25: Re: ADC by using counter method on FPGA using VHDL language
    152938: 11/11/02: Re: draw lines, circles, squares on FPGA by mouse and display on
    152998: 11/11/10: Re: ASIC design job vs FPGA design job
    153048: 11/11/23: Re: RTOS with support for TCP/IP sockets on Spartan 3E
    153158: 11/12/16: Re: Clock distribution for ADC and jitter
    153189: 12/01/05: Re: Beginner question on FIFO in
    153202: 12/01/06: Re: Handling overflow in a self-repeating frequency counter
    153210: 12/01/07: Re: Handling overflow in a self-repeating frequency counter
    153227: 12/01/12: Re: balancing IIR filter (after adding extra registers)
    153233: 12/01/14: Re: balancing IIR filter (after adding extra registers)
    153234: 12/01/14: Re: balancing IIR filter (after adding extra registers)
    153237: 12/01/15: Re: balancing IIR filter (after adding extra registers)
    153253: 12/01/18: Re: balancing IIR filter (after adding extra registers)
    153256: 12/01/18: Re: balancing IIR filter (after adding extra registers)
    153260: 12/01/19: Re: balancing IIR filter (after adding extra registers)
    153274: 12/01/24: Re: balancing IIR filter (after adding extra registers)
    153280: 12/01/25: Re: slow edge on clk inputs
    153287: 12/01/26: Re: slow edge on clk inputs
    153427: 12/02/22: Re: What is a PLD/FPGA with serial or Ethernet port logic or block
    153433: 12/02/23: Re: What is a PLD/FPGA with serial or Ethernet port logic or block
    153434: 12/02/23: Re: What is a PLD/FPGA with serial or Ethernet port logic or block
    153439: 12/02/24: Re: What is a PLD/FPGA with serial or Ethernet port logic or block
    153440: 12/02/24: Re: What is a PLD/FPGA with serial or Ethernet port logic or block
    153449: 12/02/27: Re: Strassen algorithm in vhdl
    153516: 12/03/20: Re: ways to find frequency of operation in early phase of the
    153527: 12/03/24: Re: Why are my S3A pins getting destroyed?
    153529: 12/03/25: Re: Digital Tachometer VHDL
    153532: 12/03/25: Re: Digital Tachometer VHDL
    153558: 12/03/27: Re: FPGA communication with a PC (Windows)
    153568: 12/03/28: Re: FPGA communication with a PC (Windows)
    153569: 12/03/28: Re: FPGA communication with a PC (Windows)
    153573: 12/03/29: Re: FPGA communication with a PC (Windows)
    153593: 12/04/03: Re: Expectations from newly minted EE?
    153601: 12/04/03: Re: Expectations from newly minted EE?
    153606: 12/04/03: Re: Very poor Xilinx experience
    153608: 12/04/03: Re: Expectations from newly minted EE?
    153612: 12/04/04: Re: Very poor Xilinx experience
    153634: 12/04/07: Re: Watchdog reset for fpga designs
    153656: 12/04/10: Re: Data Transfer from PC to FPGA through USB
    153669: 12/04/11: Re: XSpi_Transfer within interrupt context
    153717: 12/04/29: Re: Smallest GPL UART
    153720: 12/04/30: Re: Smallest GPL UART
    153728: 12/05/01: Re: Smallest GPL UART
    153833: 12/06/01: Re: PRNG
    153834: 12/06/01: Re: PRNG
    153880: 12/06/20: Re: Data transfers between MicroBlaze and VHDL
    153955: 12/07/03: Re: accumulator (again)
    153956: 12/07/03: Re: Generate a pulse with a definite width
    153993: 12/07/09: Re: accumulator (again)
    154001: 12/07/09: Re: accumulator (again)
    154003: 12/07/10: Re: accumulator (again)
    154135: 12/08/19: Re: "Decimals" word in binary space
    154140: 12/08/20: Re: "Decimals" word in binary space
    154207: 12/09/09: Re: Looking for an extremely cheap FPGA board (in quantity,
    154225: 12/09/11: Re: New(?) fast binary counter for FPGAs without carry logic (e.g.
    154228: 12/09/11: Re: New(?) fast binary counter for FPGAs without carry logic (e.g.
    154230: 12/09/11: Re: New(?) fast binary counter for FPGAs without carry logic (e.g.
    154232: 12/09/11: Re: New(?) fast binary counter for FPGAs without carry logic (e.g.
    154259: 12/09/18: Re: picoblaze help
    154288: 12/09/23: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
    154308: 12/09/25: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
    154314: 12/09/26: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
    154319: 12/09/27: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
    154322: 12/09/27: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
    154329: 12/09/28: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
    154345: 12/10/10: Re: Spartan 6 MCB refresh timing
    154474: 12/11/10: Re: help
    154475: 12/11/10: Re: help
    154477: 12/11/11: Re: What the advantages and disadvantages between distributed
    154479: 12/11/12: Re: What the advantages and disadvantages between distributed
    154654: 12/12/12: Re: Where to move for an embedded software engineer.
    154718: 12/12/28: Re: Which to learn: Verilog vs. VHDL?
    154744: 13/01/03: Re: Which to learn: Verilog vs. VHDL?
    154759: 13/01/04: Re: Which to learn: Verilog vs. VHDL?
    154867: 13/01/21: Re: i've used a verilog ip core of 8051...plz someone tell me what
    154871: 13/01/22: Re: implementation of 8051 ip core on fpga
    154902: 13/02/10: Re: Idea Hunt, FPGA + ARM Cortex-M3
    154941: 13/02/25: Re: add-compare-select
    154944: 13/02/25: Re: add-compare-select
    155106: 13/04/18: Re: FPGA board with 4 channel 500Msps ADC?
    155818: 13/09/19: Re: Legal Issues Reproducing Old CPU
    155821: 13/09/20: Re: Legal Issues Reproducing Old CPU
    155871: 13/10/09: Re: Book recommendation
    155981: 13/11/02: Re: Simulation of VHDL code for a vending machine
    155982: 13/11/02: Re: Partnership Request
    155985: 13/11/02: Re: Partnership Request
    156008: 13/11/07: Re: Verilog Binary Division
    156025: 13/11/11: Re: how does PC communicate with FPGA?
    156026: 13/11/11: Re: generating clocks
    156076: 13/11/22: Re: microZed adventures
    156083: 13/11/22: Re: microZed adventures
    156084: 13/11/22: Re: microZed adventures
    156101: 13/11/22: Re: microZed adventures
    156163: 14/01/03: Re: Optimising pin allocation
    156195: 14/01/15: Re: 3/4 Punctured Convolution encoding
    156201: 14/01/17: Re: Math is hard
    156308: 14/02/13: Re: Monostable multivibrator
    156424: 14/04/03: Re: Any good reference works on serial buses?
    156459: 14/04/08: Re: on-chip bypass caps
    156602: 14/05/10: Re: The USB FPGA?
    156608: 14/05/12: Re: need coding
    156609: 14/05/12: Re: need coding
    156616: 14/05/13: Re: need coding
    156624: 14/05/14: Re: need coding
    156662: 14/05/27: Re: Trigger implementation on ADC-FPGA
    156687: 14/06/04: Re: ECG signals Compression/Decompression
    156691: 14/06/04: Re: ECG signals Compression/Decompression
    156711: 14/06/06: Re: ECG signals Compression/Decompression
    156712: 14/06/06: Re: ECG signals Compression/Decompression
    156756: 14/06/18: Re: PLA? PAL? PLD? GAL?
    156761: 14/06/18: Re: NAND flash interface through FPGA
    156793: 14/06/28: Re: [cross-post] dither generator on fpga
    156797: 14/06/29: Re: [cross-post] dither generator on fpga
    156799: 14/06/29: Re: [cross-post] dither generator on fpga
    156916: 14/07/28: Re: Primitive debuggable UART interface to a Nios within a
    156941: 14/07/31: Re: Professional VHDL Examples?
    156969: 14/08/08: Re: Basic question: sequence of execution within FPGAs
    156979: 14/08/10: Re: Basic question: sequence of execution within FPGAs
    157152: 14/10/18: Re: Fast and slow clocks
    157161: 14/10/22: Re: [cross-post] verification vs design
    157170: 14/10/23: Re: [cross-post] verification vs design
    157446: 14/12/10: Re: VHDL Synchronization- two stage FF on all inputs?
    157447: 14/12/10: Re: VHDL Synchronization- two stage FF on all inputs?
    157467: 14/12/11: Re: Using FPGA to feed 80386
    157468: 14/12/11: Re: Using FPGA to feed 80386
    157469: 14/12/11: Re: Using FPGA to feed 80386
    157470: 14/12/11: Re: difference between fpga and epld
    157472: 14/12/11: Re: VHDL Synchronization- two stage FF on all inputs?
    157484: 14/12/12: Re: Using FPGA to feed 80386
    157488: 14/12/12: Re: Using FPGA to feed 80386
    157503: 14/12/12: Re: Using FPGA to feed 80386
    157504: 14/12/12: Re: Using FPGA to feed 80386
    157549: 14/12/15: Re: Using FPGA to feed 80386
    157589: 14/12/22: Re: How to automatically allocate multiple bit fields into constant
    157601: 14/12/26: Re: Prime number in verilog
    157603: 14/12/27: Re: Prime number in verilog
    157663: 15/01/22: Re: Send a pulse across clocks
    157665: 15/01/22: Re: [RANT] XILINX, Are you freaking kidding me ?
    157669: 15/01/22: Re: Send a pulse across clocks
Tim Williams:
    5253: 97/02/01: Re: Suggestions how wire wrap mount a Xilinx PG223
    107900: 06/09/02: Re: Performance Appraisals
    125926: 07/11/08: Re: not totally repulsive
    155775: 13/08/29: Re: FPGA temperature measurement
    156505: 14/04/11: Re: on-chip bypass caps
tim.....:
    136671: 08/11/30: Re: make phone calls from fpga. is it possible?
tim.linden@gmail.com:
    80925: 05/03/14: Re: Parallel ATA/Spartan 3 starter board / Student Project
<tim_kellis@ahh.com>:
    9099: 98/02/20: PROBS W/ ALTERA MAX+PLUS II 8.2 S/W
Timing Newb:
    49224: 02/11/05: How to approch timing constraints...
timinganalyzer:
    132595: 08/06/02: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
    132680: 08/06/05: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
    132837: 08/06/08: ANNOUNCE: TimingAnalyzer -- new updated version
    132999: 08/06/12: Re: ANNOUNCE: TimingAnalyzer -- new updated version
    133442: 08/06/29: ANNOUNCE: TimingAnalyzer version beta 0.85
    133456: 08/06/30: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
    133463: 08/06/30: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
    133605: 08/07/05: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
    133630: 08/07/07: ANNOUNCE: TimingAnalyzer version beta 0.86
    133632: 08/07/07: Re: ANNOUNCE: TimingAnalyzer version beta 0.86
    133756: 08/07/13: Re: ANNOUNCE: TimingAnalyzer version beta 0.86
    133783: 08/07/14: Re: ANNOUNCE: TimingAnalyzer version beta 0.86
    133928: 08/07/19: ANNOUNCE: TimingAnalyzer version beta 0.87
    133931: 08/07/19: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
    133949: 08/07/20: Re: ANNOUNCE: TimingAnalyzer version beta 0.87
    134837: 08/09/03: request for beta testers -- TimingAnalyzer Program
    136034: 08/10/28: TimingAnalyzer beta version 0.90 -- beta testers wanted
    136039: 08/10/28: Re: TimingAnalyzer beta version 0.90 -- beta testers wanted
    136227: 08/11/07: request: sample vcd files for TimingAnalyzer
    136314: 08/11/10: Re: request: sample vcd files for TimingAnalyzer
    136327: 08/11/11: Re: request: sample vcd files for TimingAnalyzer
    138313: 09/02/15: Announce: new TimingAnalyzer version beta 0.92
    138383: 09/02/18: Re: Announce: new TimingAnalyzer version beta 0.92
    141362: 09/06/20: TimingAnalyzer is now freeware
    142513: 09/08/13: new version TimingAnalyzer
    144192: 09/11/18: TimingAnalyzer -- Build Timing Diagrams directly from VHDL or
    145093: 10/01/26: Re: GTKWave 3.3.0 for Windows is available
    145778: 10/02/23: Re: free waveform drawing tool
    145794: 10/02/23: Re: free waveform drawing tool
    145951: 10/03/01: Re: free waveform drawing tool
<timjeno@my-deja.com>:
    27007: 00/11/07: Re: ACEX1K vs FLEX10K
    27062: 00/11/09: Re: ISO C -> VHDL translator, prefer open source
    27161: 00/11/13: Re: ISO C -> VHDL translator, prefer open source
Timmestein:
    40659: 02/03/12: nOOb: wants to start using an fpga
    40702: 02/03/13: Re: How would I know somebody has copied my files in Unix?
timnicolson:
    35177: 01/09/25: verification problems please help
Timo:
    57483: 03/07/01: Seriell Decoder possibly in ABEL for Lattice CPLD
Timo Dammes:
    70039: 04/05/28: Xilinx System Generator
    70282: 04/06/11: example designs for Xilinx System Generator ?
    71458: 04/07/19: fpga board with audio in/out (xilinx fpga) ?
    75784: 04/11/15: IO pins : short circuit protection ?
    75807: 04/11/15: Re: IO pins : short circuit protection ?
    75819: 04/11/16: thx
Timo Gerber:
    126398: 07/11/21: Xilinx XST 8.2, Error on multi-source, bug?
    126430: 07/11/22: Re: Xilinx XST 8.2, Error on multi-source, bug?
    126438: 07/11/22: React on falling edge in testbench
    126445: 07/11/22: Re: React on falling edge in testbench
    126594: 07/11/28: Adding Desing to an Xilins Platform Studio project
    126843: 07/12/04: EDK does not find Modelsim
Timo Schneider:
    114207: 07/01/08: Build an FPGA programmer cable
    114240: 07/01/08: Re: Build an FPGA programmer cable
    114245: 07/01/08: Re: Build an FPGA programmer cable
<timolmst@cyberramp.net>:
    4534: 96/11/10: Re: Xilinx and cost of tools
    4597: 96/11/19: Re: Advantage of third party software?
    4653: 96/11/26: Re: How to use Xilinx ?
    4693: 96/12/01: Re: In Search of Xilinx Routing Statistics
    4753: 96/12/11: Re: Xilinx configuration PROM
    5028: 97/01/14: Re: Great Xilinx FPGA Kits & prices
    5037: 97/01/15: Re: Great Xilinx FPGA Kits & prices
    5174: 97/01/29: Re: Able to reverse a .JED back to logic?
    5429: 97/02/15: Re: HELP: XC4000 download cable
    5477: 97/02/19: Re: Xilinx or Altera?
    5831: 97/03/19: Re: EDA tools
    5897: 97/03/24: Re: What tools for $8000?
    5997: 97/04/03: Re: XC2018
    6107: 97/04/12: Re: In search of free/low cost PAL/PEEL design sw
    6108: 97/04/12: Re: Seeking PALASM/ABEL/CUPL/?
    6443: 97/05/24: Re: What is M1?
    6448: 97/05/25: Re: What is M1?
    6501: 97/05/29: Re: Cheap way to develop for FPGAs?
    6563: 97/06/03: Re: What is M1?
    6986: 97/07/19: Re: FPGA design tools
    7613: 97/09/27: Re: Still for sale OrCAD SDT & Xilinx XACT
    7623: 97/09/29: Re: Still for sale OrCAD SDT & Xilinx XACT
    7640: 97/09/30: Re: Still for sale OrCAD SDT & Xilinx XACT
    7721: 97/10/07: Re: Wanted: cheap way to learn VHDL
    7853: 97/10/23: Re: Upgrade to Alliance 3.0 CAD VLSI software
    8002: 97/11/06: Re: ABEL HDL state machine question
    8396: 97/12/12: Re: Z80 in FPGA: clockspeed?
    9071: 98/02/18: Re: Xilinx download cable ??????
    9072: 98/02/18: Re: Xilinx download cable ??????
    9652: 98/03/28: Re: XactStep6 - The cure for a dongle
    9872: 98/04/10: Re: Xilinx XACT 6.01 crack
    10202: 98/05/03: Re: Xilinx Foundation and Linux
    10408: 98/05/17: Re: XC5200s and Foundation 1.4
    10865: 98/06/26: Re: Xilinx Foundation simulator problem?
    11953: 98/09/21: What is the current revision of the Xilinx M1.x s/w?
    12812: 98/10/30: Re: New free FPGA CPU
    12949: 98/11/06: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
    12980: 98/11/09: Re: help xc3000 series
    13197: 98/11/19: Re: Abel limitations in xilinx foundation base?
    14162: 99/01/16: Re: The development of a free FPGA synthesis tool
    14715: 99/02/12: Re: Xilinx de-compiler
    14917: 99/02/25: Re: Xilinx ABEL?
<timolmst@nospam.cyberramp.net>:
    7221: 97/08/15: Re: free FPGA software from actel
Timothy A. Seufert:
    6023: 97/04/06: Re: PCI Bus Problems
Timothy Barr:
    336: 94/10/23: Re: I/O pin currents on Xilinx FPGAs?
Timothy Campbell:
    65101: 04/01/20: RocketIO evaluation
    66632: 04/02/24: DCM Simulation Error
    66649: 04/02/24: Experience with Simulating RocketIO in Modelsim
Timothy Del Sol:
    6176: 97/04/22: ISP CPLD from AMD or Cypress???
Timothy J. Ryan:
    5168: 97/01/28: Re: Able to reverse a .JED back to logic?
Timothy Miller:
    16284: 99/05/13: Verilog example for Xilinx?
    19526: 99/12/29: Virtex Config Help
    19532: 99/12/29: Re: Virtex Config Help
    19555: 99/12/30: Re: Virtex Config Help
    62677: 03/11/04: Voila: Nedit macro to produce verilog module instantiations
    62708: 03/11/05: Re: Voila: Nedit macro to produce verilog module instantiations
Timothy Oconnell:
    9051: 98/02/17: Re: Free FPGA tools???
    9077: 98/02/18: Re: Free FPGA tools???
    9078: 98/02/18: Re: Free FPGA tools???
Timothy P. Ganley:
    2587: 96/01/08: Re: Need Re-programable VXI Module
    5763: 97/03/13: Re: A viewlogic story
    5764: 97/03/13: Re: A viewlogic story
Timothy Pagden:
    3090: 96/03/29: ANNOUNCE: New Model of the Month 8 bit ADC
    3091: 96/03/29: ANNOUNCE: New VHDL Tip of the Month
Timothy R. Sloper:
    17523: 99/08/05: Re: Counters
    29669: 01/03/04: Re: Actel's FPGA : A54SX32A
    29670: 01/03/04: Re: ACTEL 54SX bidir IF Problem
    29711: 01/03/06: Re: Actel's FPGA : A54SX32A
    38317: 02/01/11: Re: Actel Libero for ProAsic in big trouble?
    45346: 02/07/19: Re: Theft protection of FPGA configuration data
    45614: 02/07/29: Re: secure FPGA
    45617: 02/07/29: Re: secure FPGA
    45646: 02/07/30: Re: secure FPGA
    47913: 02/10/07: Re: FPGA with an EPROM on it?
Timothy Scott Stilson:
    3261: 96/05/06: plpl2.3 device def. format?
Timothée GROS:
    52776: 03/02/21: PC-CARD to ISA converter
    53741: 03/03/21: Glue logic beetween an Xscale PXA250 and PC104 Bus
<timotoole@gmail.com>:
    90100: 05/10/04: Systolic array architectures
    90180: 05/10/06: Re: Systolic array architectures
Tin-Yau Fung:
    85344: 05/06/08: false path on asyn. fifo
Tina:
    41502: 02/03/30: Memory design for processor
Tina Falkenberg:
    45327: 02/07/19: Re: dsp v fpga
    47088: 02/09/17: FPGA Design and IP Cores
    48435: 02/10/17: Re: Quartus design question
<tinaliu9089@gmail.com>:
    156311: 14/02/15: How to implement Ethernet packet classification with vhdl on FPGA?
Tino Konschak:
    16847: 99/06/14: Re: EPC2 and JTAG
Tinoosh Mohsenin:
    47603: 02/09/30: Simulating mixed Verilog and VHDL files
Tippawan Aranwattananon:
    16254: 99/05/12: How synthesize tools concern with size of the design?
    16255: 99/05/12: Re: UART Design
tirsys:
    125450: 07/10/25: fgpa beginner
TIVPC:
    8336: 97/12/09: Re: I looked up Altera in an Italian dictionary.....
    8335: 97/12/09: Re: Q: MAX+ Plus II External connections
Tiwana:
    141063: 09/06/04: Dumb questions needs urgent answer
TJ:
    6796: 97/06/28: Smart Card Design and Interface. How?
TJB:
    79227: 05/02/15: Re: Virtex II Slice Design - ARGH!
    79272: 05/02/16: Re: Virtex4: where is ICAP?
tk:
    51244: 03/01/08: Newbie question
    51248: 03/01/09: Re: Newbie question
    51375: 03/01/12: State machine problem
    51386: 03/01/13: Re: State machine problem
    51462: 03/01/15: Re: State machine problem
    56750: 03/06/13: Learning Virtex II Pro
    57068: 03/06/23: JBits and Virtex II Pro
    57180: 03/06/25: ERROR:iMPACT:583
    57226: 03/06/26: Re: ERROR:iMPACT:583
    57228: 03/06/26: Xilinx ML300 JTAG Configuration Problem
    57235: 03/06/26: Re: ERROR:iMPACT:583
    57273: 03/06/27: Re: Dynamic Reconfiguration, Virtex II Pro
    57614: 03/07/03: Re: Virtex 2Pro, ML300, VP2PDK, EDK, etc..
    57711: 03/07/04: Re: Virtex 2Pro, ML300, VP2PDK, EDK, etc..
    57720: 03/07/04: Re: Virtex 2Pro, ML300, VP2PDK, EDK, etc..
    57741: 03/07/05: Re: Virtex 2Pro, ML300, VP2PDK, EDK, etc..
    58121: 03/07/15: "ML300 Embedded" Mapping Help
    58170: 03/07/16: Re: "ML300 Embedded" Mapping Help
    58238: 03/07/17: Re: "ML300 Embedded" Mapping Help
    58347: 03/07/21: Re: "ML300 Embedded" Mapping Help
    58587: 03/07/28: Re: "ML300 Embedded" Mapping Help
    58651: 03/07/30: Re: "ML300 Embedded" Mapping Help
    61113: 03/09/29: Virtex-II Pro Equations for Finding a Bit Location
    62006: 03/10/16: Re: ICAP Virtex2
    68606: 04/04/09: Re: XAPP662 readframe and writeframe functions.
    70993: 04/07/05: Re: uClinux on MicroBlaze
    72383: 04/08/18: Re: Using SDRAM on Xilinx AFX V2P board
_TK_:
    133168: 08/06/19: FPGA JTAG commands
<tkanmijnischelen@hotmail.com>:
    81020: 05/03/16: Register X is equivalent to Y, is this my problem?
    81383: 05/03/22: clock division using DCM, how?
tkvhdl@gmail.com:
    118859: 07/05/04: Re: Atom HDL
<tlb@tlb.org>:
    90777: 05/10/20: Re: re:Xilinx ISE WebPACK-7.1i on NetBSD
tlbs:
    92503: 05/11/30: Re: Q-bus or Unibus bus transactions in FPGA?
tlbs101:
    108135: 06/09/05: Re: Please help me with (insert task here)
    128312: 08/01/21: Re: effect of xray on fpga electronic circuits
<tlenomade@googlemail.com>:
    117625: 07/04/05: suitability of systolic architecture on FPGA
    119172: 07/05/14: does SRL exist in non-xilinx FPGAs?
    120673: 07/06/13: how to speed up the write to the off chip ram
    122962: 07/08/12: LUT distributed memory in FPGA devices
    122996: 07/08/13: Re: LUT distributed memory in FPGA devices
tln:
    95053: 06/01/20: Virtex II Pro-X Rocket I/O problems
    95288: 06/01/21: Re: Virtual Pin in Xilinx ISE
TM:
    6064: 97/04/09: PCI and DRAM control - Xilinx 4000 -Verilog
    7030: 97/07/25: Re: Why fast message delete in this group?
TMA:
    7393: 97/09/05: Re: export pins from MAX+ to orcad schem symbol
<tmcdon4ld@gmail.com>:
    156392: 14/03/27: Re: built in adc in fpga????
TMItools:
    11160: 98/07/21: Re: Dataio Chipwriter won't burn Altera EPC1 generated with Maxplus2 8.2 or greater???
tmpstr:
    127280: 07/12/16: Ethernet data rates using Spartan-3 FPGA
    127347: 07/12/18: Re: Ethernet data rates using Spartan-3 FPGA
    129335: 08/02/21: which IOSTANDARD to use for IO-bank in Spartan-3
    129371: 08/02/22: Re: which IOSTANDARD to use for IO-bank in Spartan-3
    143243: 09/09/28: Problem flashing the AT45DB161D on Sparkfun board
TMU:
    92392: 05/11/29: The reason of implementation of morphological operator in FPGA
tmueller:
    143056: 09/09/17: VHDL: obtaining the length of a record
<tnbiggs@gmail.com>:
    98491: 06/03/10: Re: a problem with coolrunner CPLD (XC2C256) GCK0 pin
tns:
    86994: 05/07/12: Re: QII simulation annoyance
    87005: 05/07/12: Re: QII simulation annoyance
    87021: 05/07/13: Re: QII simulation annoyance
    87053: 05/07/13: Re: QII simulation annoyance
tns1:
    68778: 04/04/17: Nios - cyclone toolchain questions
    68876: 04/04/20: Re: Nios - cyclone toolchain questions
    70756: 04/06/26: Nios stops responding to interrupts
    70787: 04/06/28: Re: Nios stops responding to interrupts
    70846: 04/06/29: Re: Nios stops responding to interrupts
    70886: 04/06/30: Quartus web editions vs licenced compatibility problems
    70902: 04/07/01: Re: *RANT* Ridiculous EDA software "user license agreements"?
    70920: 04/07/01: Re: *RANT* Ridiculous EDA software "user license agreements"?
    70984: 04/07/03: Re: nios-run ignores kbd.
    71009: 04/07/05: Re: nios-run ignores kbd.
    71111: 04/07/08: Re: Quartus web editions vs licenced compatibility problems
    71312: 04/07/14: Nios SDK - understanding nm output
    71350: 04/07/15: Nios reset behavior
    71367: 04/07/15: Re: Nios reset behavior
    71408: 04/07/17: Re: Nios reset behavior
    86978: 05/07/11: QII simulation annoyance
    87016: 05/07/12: Re: QII simulation annoyance
TNT:
    13598: 98/12/11: Need basic info on FPGA!
to ja:
    43747: 02/05/31: Re: How to add delay in fpga(spartan)?
To: Kshitij Arora <:
    124694: 07/09/30: Planning to switch to FPGA domain, any advice would be highly appreciated
toanfxt:
    117129: 07/03/23: iMPACT:CRC Error bit is NOT 0
Tobasco:
    142578: 09/08/17: Re: GTKWave 3.2.2 for Windows is available
Tobi Delbruck:
    17720: 99/08/27: Re: map hang
    17743: 99/08/29: Re: map hang
Tobias:
    37282: 01/12/06: Timing Constraints Spartan, divided Clk
    93453: 05/12/22: Cordic v2.0 : cordic translate algorithm problem
    135929: 08/10/22: Design security
    136017: 08/10/28: Re: Design security
Tobias =?iso-8859-1?Q?M=F6glich?=:
    63506: 03/11/24: Dual port RAM for Xilinx
    63705: 03/12/01: Re: Dual port RAM for Xilinx
    63711: 03/12/01: CoreGenerator
    63758: 03/12/03: DPRAM - DIN, DOUT
    64557: 04/01/07: DPRAM using the CoreGenerator, VHDL-example
    64577: 04/01/08: Re: DPRAM using the CoreGenerator, VHDL-example
    64578: 04/01/08: old articels of this newsgroup
    64592: 04/01/08: Dual Port RAM Block RAM using Core Generaot
    64734: 04/01/12: using signal as clk source
    64772: 04/01/13: Re: using signal as clk source
    65100: 04/01/20: Tristate buffer
    65173: 04/01/21: Re: Tristate buffer
    65611: 04/02/03: dual port RAM - write cycle problems
    66270: 04/02/16: Xilinx Chipscope Sample rate
    66271: 04/02/16: IOB's
    66325: 04/02/17: Re: Xilinx Chipscope Sample rate
    66334: 04/02/17: Re: Xilinx Chipscope Sample rate
    66335: 04/02/17: Re: dual port RAM - write cycle problems
    66337: 04/02/17: Re: IOB's
    66356: 04/02/18: ChipScope for ISE 6.1
Tobias Baumann:
    149910: 10/12/01: MicroBlaze Software Debugging print problem
    150124: 10/12/15: microblaze spi core problem
    150155: 10/12/21: Re: microblaze spi core problem
    150167: 10/12/23: Re: microblaze spi core problem
    151324: 11/03/23: Xilinx EDK - max array size
    151376: 11/03/29: EDK - program behavior
    151383: 11/03/31: Re: EDK - program behavior
    157021: 14/09/01: Re: Functional safety guidelines
Tobias F. Garde:
    25570: 00/09/14: Re: Xilinx and CD databooks (rant)
    25749: 00/09/19: Re: Xilinx Web Pack
Tobias Hilpert:
    8170: 97/11/24: AT17C256 problems
    8401: 97/12/12: ATMEL 17C256 problems solved ...
Tobias Kahre:
    153517: 12/03/21: Spartan 3 DiffPairs restricted to Banks 0 and 2?
    153519: 12/03/22: Re: Spartan 3 DiffPairs restricted to Banks 0 and 2?
Tobias Moeglich:
Tobias Russ:
    33812: 01/08/06: Re: Which is the best Design Toolchain?
Tobias Schuele:
    2593: 96/01/09: Simulator for LATTICE pDS
    4043: 96/09/05: PCI compliant FPGA / free P&R software
Tobias Stumber:
    23887: 00/07/14: Re: i2c VHDL code
    25516: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
    30749: 01/04/27: VirtexE 5V PCI
    32014: 01/06/11: Re: Force tristate enable register into IOB
    35967: 01/10/25: Re: Xilinx PCI core and XST
    36016: 01/10/26: Re: Xilinx XST vs FPGA Express?
    36805: 01/11/20: Altera & Actel prices
    37450: 01/12/11: Re: xilinx ise 4
    47896: 02/10/07: Re: Xilinx ISE does not use Resgisters in IOB
    53665: 03/03/19: Re: Cheapest Spartan II/IIE configuration flash EEPROM!
Tobias Weihmann:
    65328: 04/01/24: XC6200 bitstream readback
    88046: 05/08/07: Spartan-3: Own P&R, generate bitstream from
    88117: 05/08/09: Re: Spartan-3: Own P&R, generate bitstream from
    88130: 05/08/10: Re: Spartan-3: Own P&R, generate bitstream from
Tobias Weingartner:
    77982: 05/01/21: Good references for ADPLL in FPGA?
    78166: 05/01/25: Re: Xilinx Engineering Samples [JTAG issues]
    78700: 05/02/06: Re: Exportability of EDA industry from North America?
    79034: 05/02/11: Re: Writing IP-Cores while sleeping ;)
    79036: 05/02/11: Re: ProAsic3 (PA3)
    80501: 05/03/07: Re: for debugging
    81617: 05/03/29: Re: Multi-FPGA PCB data aggregation?
    81909: 05/04/04: Re: Open PowerPC Core?
    81910: 05/04/04: Reverse engineering ASIC into FPGA
    81997: 05/04/05: Re: Open PowerPC Core?
    81999: 05/04/05: Re: Reverse engineering ASIC into FPGA
    82066: 05/04/06: Re: Reverse engineering ASIC into FPGA
    83626: 05/05/04: Re: Multiply Accumulate FPGA/DSP
    91484: 05/11/07: Re: Why Spartan-3e is the best
    91542: 05/11/08: Re: Why Spartan-3e is the best
    91543: 05/11/08: Re: Why Spartan-3e is the best
    93951: 06/01/04: Re: RTL for Z8000 series CPU?
    94300: 06/01/09: Re: RTL for Z8000 series CPU?
    94604: 06/01/14: Re: FPGA Journal Article
    94693: 06/01/16: Re: FPGA Journal Article
    94876: 06/01/18: Re: FPGA Journal Article
    94694: 06/01/16: Re: FPGA Journal Article
    94879: 06/01/18: Re: FPGA Journal Article
    95081: 06/01/20: Re: FPGA Journal Article
    95082: 06/01/20: Re: FPGA Journal Article
    95460: 06/01/23: Re: FPGA Journal Article
    94880: 06/01/18: Re: FPGA Journal Article
    94605: 06/01/14: Re: FPGA Altair Advice
    94695: 06/01/16: Re: FPGA Altair Advice
    94603: 06/01/14: Any FPGA with programming info available?
    96207: 06/01/31: Re: Analog FPGA Project -- VIdeo Router
    98732: 06/03/15: CSV files available for Xilinx FPGA parts pinouts?
    98914: 06/03/17: Re: CSV files available for Xilinx FPGA parts pinouts?
    101768: 06/05/05: Re: Xilinx 3s8000?
    102476: 06/05/16: Re: Spartan 3E
    102595: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
    103660: 06/06/07: Re: Easily add 4 Gb/s Ethernet link to FPGA systems for control & data transfer
    124284: 07/09/17: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
Tobias-Dirk Stumber:
    23622: 00/07/03: Re: Powering XCV300
    23676: 00/07/05: Virtex-E PCI (MB with 3.3Vsignaling)
<tobias@nord.eunet.no>:
    3466: 96/06/03: Xilinxs FPGAs (newbies)
Tobin Fricke:
    21108: 00/03/07: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
    21236: 00/03/12: Altera LPM from VHDL
    22109: 00/04/24: xilinx --> altera vhdl
    26964: 00/11/05: ViewLogic ViewDraw questions
toby:
    63868: 03/12/06: Verilog-2001 `define expressions?
    103378: 06/05/31: Re: Quartus and source control
    103379: 06/05/31: Re: Quartus and source control
    106730: 06/08/17: Re: Quartus and source control (continued)
Toby:
    55579: 03/05/13: Ramb16_s18_s18
Toby Thain:
    75151: 04/10/27: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
Tod Adamson:
    83109: 05/04/23: WTB Xilinx Ver. 6.2 EDK
    83525: 05/05/02: WTB: Xilinx 6.2i EDK
    83553: 05/05/02: Re: Xilinx 6.2i EDK
Todd:
    111184: 06/10/30: FPGA's for Ethernet?
todd:
    45355: 02/07/20: WTB: Old xilinx development system or dongle (circa 1993-7)
Todd A. Kline:
    4953: 97/01/03: wir2xnf problem with NT 4.0 network
    5743: 97/03/11: VHDL & ABEL synthesis tools on 95/NT
Todd Brisebois:
    5328: 97/02/07: Software for FPGA software
Todd Brown:
    34006: 01/08/10: Low Cost FPGA or PLD
Todd Fleming:
    102589: 06/05/17: Verilog Draggable Window Library
    106345: 06/08/11: ISE Webpack 8.1 adder wierdness
    106371: 06/08/12: Re: ISE Webpack 8.1 adder wierdness
    106387: 06/08/12: Re: ISE Webpack 8.1 adder wierdness
    106560: 06/08/15: Re: ISE Webpack 8.1 adder wierdness
    108831: 06/09/17: Re: uclinux on spartan-3e starter kit
    109435: 06/09/26: Re: PUBLISHABLE PAPER RELATED TO FPGA!
    109471: 06/09/27: Re: PERISHABLE PAPER RELATED TO FPGA!
    109513: 06/09/27: Re: PERISHABLE PAPER RELATED TO FPGA!
    111770: 06/11/09: XUP-V2Pro banking rule problem
    111771: 06/11/09: Re: XUP-V2Pro banking rule problem
    111772: 06/11/09: Re: XUP-V2Pro banking rule problem
    111776: 06/11/09: Re: XUP-V2Pro banking rule problem
    111777: 06/11/09: Re: XUP-V2Pro banking rule problem
    111781: 06/11/09: Request to Xilinx
Todd Funderburg:
    3467: 96/06/04: Re: RS422 Connections and Pin-outs
Todd Kline:
    9962: 98/04/17: Question about DRAM market forcasts
    9994: 98/04/21: Re: XNF to EDIF utility
    10027: 98/04/22: Re: Ask for / Discuss which FPGA & ASIC tools best buy
    12691: 98/10/23: Re: State machines in VHDL/Verilog
    12696: 98/10/23: Re: How can I estimate number of Xilinx CLB?
    12697: 98/10/23: Re: How can I estimate number of Xilinx CLB?
    12698: 98/10/23: Re: Foundation Express in M1.5
    12725: 98/10/26: Re: State machines in VHDL/Verilog
    13019: 98/11/11: Re: hard macros design flow for XILINX Foundation Express
    13023: 98/11/11: Re: connecting 2 FPGA together
    13405: 98/12/01: Re: Is it normal to have to edit the xnf file???
    13480: 98/12/04: Re: Is it normal to have to edit the xnf file???
    13578: 98/12/10: Re: A short digression...
    13481: 98/12/04: Re: XILINX FPGA reaches GHz speeds
    13521: 98/12/07: Re: computer requirements for CAE systems
    14038: 99/01/08: 68K synthesizable core
    15003: 99/03/02: Re: Problems inferring RAM memory
    15004: 99/03/02: Fast-turn ASIC vendors
    15064: 99/03/04: Re: Fast-turn ASIC vendors
    15795: 99/04/14: Re: Anyone using FPGA Express 'Time Tracker' option?
    15796: 99/04/14: Re: simulator
    15799: 99/04/14: Re: 75% PAL video bars
    16234: 99/05/11: Re: Spartan Metastability parameters
    16136: 99/05/05: Re: Xilinx netlister - Workaround needed
    16137: 99/05/05: Re: Anyone use 27256 for config?
    16187: 99/05/07: Re: BGA Prototyping ?
    16235: 99/05/11: Re: Synopsys DC & Modelsim
    16236: 99/05/11: Re: Synchronizer design?
Todd KLine:
    8094: 97/11/17: VHDL based Pull-up for tri-state lines
    8627: 98/01/14: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
    8629: 98/01/14: SDRAM Interface from an FPGA
    8831: 98/01/30: Re: Comments about Xilinx Alliance m1.4 w/Novell and other problems
    8830: 98/01/30: Re: Comments about Xilinx Alliance m1.4 w/Novell and other problems
    9715: 98/04/01: Xilinx post routed VHDL/VITAL simulation
Todd L James:
    5185: 97/01/29: Re: Synthesizing fast counter (carry look ahead adder)
Todd Lawson:
    12286: 98/10/07: Re: Verilog Simulators
Todd Lue:
    1177: 95/05/11: Re: Lattice EPLDs
Todd M. Caplan:
Todd McKenzie:
    29012: 01/02/01: Opportunity Knocks
Todd Parker:
    244: 94/10/01: copy a GAL16V8B ?
Todd Peterson:
    4453: 96/10/31: FREE ELECTRONICS DIRECTORY
    4529: 96/11/08: Electronics/ Microcontroller On-Line Electronics Resource Directory
    4576: 96/11/16: Electronics Directory
    5013: 97/01/12: INTERNET ELECTRONICS DIRECTORY
    5171: 97/01/28: Device Control Application Note
    15846: 99/04/16: Newsletter: Embedded Design Bulletin
Todd Selden:
    271: 94/10/10: Re: AT&T ORCA FPGA
Todd Simonds:
    152673: 11/09/26: Actel .DCF Constraint File
Todd Stevens:
    7339: 97/08/28: Re: .vho file creation in MaxplusII
Todd Walbert:
    8911: 98/02/06: ASIC position in Sacramento
Todd Walk:
    7323: 97/08/26: Re: ANNOUNCE: VHDL Synthesis for $495
    7327: 97/08/27: Re: VHDL Synthesis for Linux?
    7332: 97/08/27: Re: VHDL Synthesis for Linux?
    9421: 98/03/12: Re: The case for Linux and EDA
<Todd>:
    1873: 95/09/13: UART for Actel FPGA needed
    2566: 96/01/03: Re: Need help: Actel "bibuf" working with Q
<todd>:
    1900: 95/09/18: Kayvon! (was UART for FPGA)
Token:
    110449: 06/10/16: WiFi signal repeater using any virtix fpga
Tolga:
    57325: 03/06/27: Re: ModelSim 5.7 and xilinx libraries
    57788: 03/07/07: Re: Spartan-3 availability
Tolgay Akkaya:
tollyska:
    38890: 02/01/27: 18bit counter
Tom:
    24790: 00/08/18: Contract and Permanent vacancies in the UK
    24792: 00/08/18: Permanent Jobs in the UK
    26471: 00/10/17: Has anyone done a biquad filter in xilinx FPGAs?
    27194: 00/11/15: Re: Please guide newbies to real PLD ?
    27288: 00/11/17: Re: Can FPGA perform float point calculation?
    29437: 01/02/21: Second Source For ALTERA EPC1 ?
    29965: 01/03/19: Re: Hardware Design Engineer Needed in Santa Clara, CA
    30247: 01/03/29: Re: Wanted: test vector generation software
    30249: 01/03/29: Re: Any Expert FPGA Engineers out there?
    30277: 01/03/30: Re: Xilinx GSR in Verilog simulations
    30826: 01/04/30: Re: Need info : Training on ASIC/FPGA
    31194: 01/05/14: Re: Xilinx and Actel
    31415: 01/05/22: Re: FPGA
    34861: 01/09/11: Question concerning Verilog scheduling
    35885: 01/10/22: Re: What is a difference?
    37254: 01/12/05: Board Level Sim: Models And Pullup ?
    38923: 02/01/28: Re: Books on DSP
    40222: 02/03/02: Re: share two months salary with you if you have job information
    40319: 02/03/05: Re: share two months salary with you if you have job information
    40748: 02/03/14: WTB: Coolrunner
    49699: 02/11/19: FPGA to implement Bluetooth baseband
    49810: 02/11/21: Look up tables
    50181: 02/12/04: Digital filter
    52274: 03/02/05: JTAG from CAN
    52315: 03/02/06: Re: JTAG from CAN
    63031: 03/11/13: linker script
    63497: 03/11/24: store program in external sdram
    63600: 03/11/26: external sdram and gdb tool
    63648: 03/11/27: Re: external sdram and gdb tool
    63649: 03/11/27: Re: external sdram and gdb tool
    64136: 03/12/18: interfacing a WishBone IP core to a CoreConnect bus
    64187: 03/12/19: Re: interfacing a WishBone IP core to a CoreConnect bus
    69094: 04/04/27: device driver
    69323: 04/05/06: headers linker script
    71736: 04/07/29: wishbone protocol documentation
    71979: 04/08/05: Re: New WinFilter Digital Filter design freeware tool release available.
    79485: 05/02/19: hdl:lament
    84620: 05/05/23: Nondeterministic ISE Placement
    93272: 05/12/17: Re: verification tools?
    93596: 05/12/25: Re: Opencores Can Controller
    104637: 06/07/03: Timing constraints on ISERDES
    111225: 06/10/31: Re: A spectre is haunting this newsgroup, the spectre of metastability
    112100: 06/11/16: Re: Seemingly random delays on Xilinx OSERDES
    112246: 06/11/18: IDELAY setup/hold
    116128: 07/03/01: Re: Where can i get free CAN VHDL core
    116439: 07/03/08: Re: CAN vhdl code document
    118814: 07/05/03: Atom HDL
    118869: 07/05/04: Re: Atom HDL
    118872: 07/05/04: Re: Atom HDL
    118887: 07/05/06: Re: Atom HDL
    120568: 07/06/11: ANNOUNCE: Atom 2007.06
    129527: 08/02/26: Preventing optimization in cross clock domain logic
    129574: 08/02/27: Re: Preventing optimization in cross clock domain logic
    129578: 08/02/27: Re: Preventing optimization in cross clock domain logic
    129613: 08/02/28: Re: Preventing optimization in cross clock domain logic
    132840: 08/06/08: Re: FPGA reprogrammable? (urgent)
    133368: 08/06/25: Re: Signal forwarding between FPGAs
    133396: 08/06/26: Re: Signal forwarding between FPGAs
    133407: 08/06/27: Re: Signal forwarding between FPGAs
    133419: 08/06/27: Re: Signal forwarding between FPGAs
    133422: 08/06/27: Re: Signal forwarding between FPGAs
    133439: 08/06/28: Re: Signal forwarding between FPGAs
    134091: 08/07/24: Re: Xilinx FFT core's IFFT function not working? Dun Xilinx TEST
    134250: 08/08/01: Re: Xilinx FFT core's IFFT function not working? Dun Xilinx TEST
    140387: 09/05/12: Re: OpenCores CAN/Ethernet cores
tom:
    70438: 04/06/16: help for finding a company which can provide FPGA based PCI board with ethernet port
    77104: 04/12/22: Re: Open source FPGA EDA Tools
    77837: 05/01/18: Re: Creating a pyramid of shift registers
    77853: 05/01/18: Re: Creating a pyramid of shift registers
    77855: 05/01/18: Re: Creating a pyramid of shift registers
    78297: 05/01/28: Re: Rocket I/O + Optical Fiber
    79352: 05/02/17: Confluence 0.10.3 Released
    79506: 05/02/20: Re: hdl:lament
    79518: 05/02/20: Re: hdl:lament
    79520: 05/02/20: Re: hdl:lament
    79569: 05/02/21: Re: hdl:lament
    82523: 05/04/13: Free VHDL Analysis Tool (vhdlarch 0.1.0)
    82912: 05/04/19: Re: VHDL Analysis Tool (vhdlarch 0.1.0)
    83538: 05/05/02: Re: Sync + FIFO
    90497: 05/10/14: Re: Anyone remember the really early Xilinx FPGAs?
    90498: 05/10/14: Re: Anyone remember the really early Xilinx FPGAs?
    90499: 05/10/14: Re: Anyone remember the really early Xilinx FPGAs?
Tom Verbeure:
    75328: 04/11/02: Re: How to preserve net names in DC while synthesis
    75332: 04/11/02: Re: TIME borrowing in synthesis
    75333: 04/11/02: Re: max frequency with TSMC .18u std cell library
    74926: 04/10/21: Re: Async reset
    75367: 04/11/03: Re: Physical Compiler Vs Design Complier
Tom Barber:
    15961: 99/04/23: Re: fpga express stripping out Viewlogic busses
    15962: 99/04/23: Re: Anyone Use SpeedWave? Help with Simulation Problem
    15963: 99/04/23: Re: Intelliflow question: ORD files?
Tom Barraza:
    5588: 97/02/26: Customizing Viewdraw in Workview Office 7.3 ... Is it possible?
    5692: 97/03/07: Re: A viewlogic story
Tom Becker:
    70856: 04/06/30: GAL22V10D vs GAL22V10A
Tom Biggs:
    180: 94/09/13: Re: Xilinx and 8.4 -- not!
    726: 95/02/17: Re: Can I implement a digital PLL in an FPGA??
    873: 95/03/18: Re: FPGA multi-chip modules ?
    1448: 95/06/23: Re: Who was the winner on latest PREP benchmark
    2169: 95/10/25: Re: FPGAs as a substitute for glue logic?
    2459: 95/12/08: Re: Xilinx 5200 vs. 3000, & Xilinx-ABEL?
    2588: 96/01/09: Re: Career value: VHDL or Verilog?
    3612: 96/07/03: FPGA job
    4956: 97/01/04: Re: ASICs Vs. FPGA in Safety Critical Apps.
    11901: 98/09/17: Re: Onboard reprogramming of config EEPROM
    30079: 01/03/22: Re: Xilinx XC18v04 programming via FPGA
Tom Bishop:
    17395: 99/07/24: Re: Frequency multiplier in XC4000
Tom Bowns:
    930: 95/03/30: Re: Excuse me while I vent about Data I/O & Abel...
    1317: 95/05/31: Re: ABEL optimization
    1300: 95/05/30: Re: ABEL optimization
    2146: 95/10/19: Re: Needed: Suggestions for FPGA design CAD
    2354: 95/11/22: Re: Xilinx Configuration Memory Hacking
    2462: 95/12/08: Re: Synario and 22V10 problems
    4083: 96/09/09: Re: ORCA and Viewlogic - any good?
    4520: 96/11/08: Re: Actel Designer and Win NT 4.0
    4521: 96/11/08: Re: Info on FPGA Internal Architecture/ Programming
    5810: 97/03/17: Re: VHDL & ABEL synthesis tools on 95/NT
    6221: 97/04/29: Re: 1 or 2 flip-flops to synchronise an async.
    7724: 97/10/07: Re: Help: ABEL program for ISPLSI1000 series.
    7892: 97/10/27: Re: generic library for lattice isp
    7921: 97/10/30: Re: Counter Problem
    8036: 97/11/10: Re: ABEL HDL state machine question
    8169: 97/11/24: Re: what is metastability time of a flip_flop
    8228: 97/12/01: Re: what is metastability time of a flip_flop
    8267: 97/12/04: Re: what is metastability time of a flip_flop
    8379: 97/12/11: Re: I looked up Altera in an Italian dictionary.....
Tom Branca:
    15186: 99/03/11: Re: Virtex LUT equation syntax in Xilinx EPIC 1.5?
    27213: 00/11/15: Re: BUFT conflict with LOC
    27259: 00/11/16: Re: BUFT conflict with LOC
    61739: 03/10/09: Re: Where is the logic?
Tom Brooks:
    35195: 01/09/25: Xilinx 4.1 software
    35226: 01/09/26: Re: Xilinx 4.1 software
Tom Brown:
    3630: 96/07/05: Needed: Hardware Design Engineer
Tom Bruhns:
    373: 94/11/01: Re: linear feedback shift registers
    13847: 98/12/29: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
    115525: 07/02/12: Re: Building Coaxial transmission line on PCB?
Tom Burgess:
    3672: 96/07/10: Re: Xilinx Xc4000E Questions
    3696: 96/07/17: Re: What about the XC6200 ?
    3778: 96/07/30: Re: ATT serial EEPROMs
    5239: 97/02/01: Re: FPGA power dissipation
    5238: 97/02/01: Re: FPGA power dissipation
    5423: 97/02/15: Re: Inversion 1/T with registers
    5707: 97/03/09: Re: Xil FPGA: Usage of Multi-purpose pins as I/O
    5879: 97/03/21: Re: 8-bit divider in FPGA
    5887: 97/03/23: Re: Sole source
    5946: 97/03/28: Re: 8-bit divider in FPGA
    5953: 97/03/30: Re: Sole source
    6047: 97/04/07: Re: Sole source
    6096: 97/04/11: Re: Sole source
    6003: 97/04/03: Re: Sole source
    6015: 97/04/05: Re: Pentium Pro Worth it for Altera Max Plus?
    6222: 97/04/29: Re: Low power PLD?
    6250: 97/05/02: Re: Schmitt trigger inputs?
    6436: 97/05/23: Re: Glitches in timing simulation of Xilinx FPGAs with Synopsys
    6462: 97/05/26: Re: Fine Pitch PQFP : anyone any hassles?
    6637: 97/06/07: Re: Fine Pitch PQFP : anyone any hassles?
    6678: 97/06/13: Re: Power consumption (Xilinx FPGA) questions
    6764: 97/06/25: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
    6791: 97/06/28: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
    6793: 97/06/28: Re: Help!!
    6876: 97/07/05: Re: Fast sampling techniques. Was: Fast scopes, How?
    6884: 97/07/06: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
    6934: 97/07/10: Re: Generating Sine/Cosine digitally
    6955: 97/07/15: Bus termination - cool parts & app. notes
    7037: 97/07/25: Re: Should Xiling have more local clock nets?
    7062: 97/07/28: Re: Should Xiling have more local clock nets?
    7081: 97/07/29: Re: Quick prototyping? Best solution?
    7166: 97/08/08: Re: Price of Serial EPROM is Outrageous - Better Explanation
    7286: 97/08/21: Re: Unbonded Pad Resources
    7499: 97/09/17: Re: Can 3.3v Xilinx drive CMOS?
    7517: 97/09/18: Re: Atmel 17256 serial config EEPROMs
    7587: 97/09/24: Re: Gray code difference
    7599: 97/09/25: Re: Gray code difference
    7686: 97/10/02: Re: High Speed FPGAs
    7931: 97/10/31: Re: Complex Multiplier
    8119: 97/11/19: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
    8197: 97/11/26: Re: FPGAs for hobbyist, HELP
    8286: 97/12/05: Re: A suggestion for Xilinx
    9074: 98/02/18: Re: Atmel SPROMs for Xilinx
    9209: 98/03/02: Re: Correlation--Multichannel
    9248: 98/03/04: Re: Analog crossbar switch matrix IC?
    10562: 98/05/29: Re: Compiling a HLL to FPGA
    10609: 98/06/05: Re: Non-periodic clock
    11875: 98/09/15: Re: measuring junction temperature
    12763: 98/10/28: Re: FPGA Decouple Capacitor values
    12793: 98/10/29: Re: FPGA Decouple Capacitor values
    13434: 98/12/02: Re: XILINX FPGA reaches GHz speeds
    13456: 98/12/03: Re: XILINX FPGA reaches GHz speeds
    13519: 98/12/07: Re: XILINX FPGA reaches GHz speeds
    13652: 98/12/16: Re: Problem with timing spec through a RAM
    13945: 99/01/04: Re: 1.5i changes
    14246: 99/01/21: Re: Q: Counting GHz pulses - ?
    14268: 99/01/22: Re: Q: Counting GHz pulses - ?
    14313: 99/01/25: Re: Q: Counting GHz pulses - ?
    14314: 99/01/25: Re: Power Consumption in FPGAs
    14375: 99/01/27: Re: Xilinx - Questions on clock & Async delays.
    14528: 99/02/03: Re: Q:EEPROM for Xilinx XC4k
    14720: 99/02/12: Re: Very Long Write Enable in Xilinx Dual Port RAMs
    15030: 99/03/03: Re: experience with Xilinx 4K series I/Os
    15126: 99/03/08: Re: experience with Xilinx 4K series I/Os
    15183: 99/03/11: Re: FOUNDATION EPIC EDITOR
    15258: 99/03/16: Re: Xilinx routing issue
    15260: 99/03/16: Re: Xilinx routing issue
    15261: 99/03/16: Re: Power Estimiation
    15263: 99/03/16: Re: Power Estimiation
    15285: 99/03/17: Re: Power Estimiation
    15293: 99/03/17: Re: Power Estimiation - report.zip (0/1)
    15295: 99/03/17: Re: Power Estimiation
    15299: 99/03/17: Re: experience with Xilinx 4K series I/Os
    15346: 99/03/19: Re: Power Estimiation
    15353: 99/03/19: Re: Power Estimiation - report.zip (0/1)
    15476: 99/03/25: Re: Info about FPGA/PLD
    15503: 99/03/26: Re: IBM 600MHz FPGA
    15557: 99/03/30: Re: FPGAs with ECL-compatible I/Os
    15576: 99/03/31: Re: FPGAs with ECL-compatible I/Os
    16072: 99/04/30: Re: High speed PLL inside FPGA
    16153: 99/05/06: Re: Bugs in place and route s/w....XLINX???
    16783: 99/06/08: Re: LINE DELAYS USING RAMS
    16784: 99/06/08: Re: ALtera 20KE LVDS IO
    16908: 99/06/16: Re: 3 Questions with XILINX CPLD
    16932: 99/06/17: Re: aobut analog
    16950: 99/06/18: Re: FW: Xilinx Acquisition of CoolRunners
    18235: 99/10/08: Re: Altera 10K50V in-rush/temp problem...
    18406: 99/10/22: Re: Xilinx Orientation Question
    18732: 99/11/10: Re: CAN tools reccomendations?
    18947: 99/11/22: Re: PADS Experience?
    19914: 00/01/17: Re: Xilinx Spartan2
    20279: 00/02/03: Re: Xilinx Virtex Decoupling Cap Guidelines
    20444: 00/02/10: Re: SRAM part question
    20449: 00/02/10: Re: Spartan and timing analyzer: clock nets using non-dedicated
    20454: 00/02/10: Re: Spartan and timing analyzer: clock nets using non-dedicated
    20777: 00/02/21: Re: Spartan and timing analyzer: clock nets using non-dedicated
    20831: 00/02/23: Re: Xchecker schematic?
    20894: 00/02/25: Re: Design security
    20920: 00/02/28: Re: Xilinx Abel Problems
    21221: 00/03/10: Re: Extremely fault tolerant strategies
    21006: 00/03/02: Re: DLL Details of Xilinx Virtex FPGAs
    21126: 00/03/07: Re: Stupid Foundation question
    21447: 00/03/22: 4000XLA bitgen problem?
    21554: 00/03/24: Re: 4000XLA bitgen problem?
    21571: 00/03/25: Re: FPGA & single point failure
    21609: 00/03/26: Re: FPGA openness
    21610: 00/03/26: Re: FPGA & single point failure
    21649: 00/03/27: Re: FPGA & single point failure
    21670: 00/03/28: Re: FPGA & single point failure
    21710: 00/03/29: Re: New Place and Route Software for Non-Commercial Research (Academic
    21733: 00/03/30: Re: 10 gbit/s input
    21749: 00/03/30: Re: FPGA & single point failure
    21777: 00/03/31: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
    21798: 00/03/31: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
    21918: 00/04/06: Re: FPGA Openness/ Summary
    22031: 00/04/14: Re: XCHECKER 3V adapter
    22045: 00/04/14: Re: XCHECKER 3V adapter
    22372: 00/05/06: Re: Q: simplest FPGA structure for novel technology demonstration
    22616: 00/05/14: Re: New Robot info and general news site
    22819: 00/05/25: Re: Apex supply problem
    22848: 00/05/27: Re: Apex supply problem
    22850: 00/05/27: Re: 8087 in FPGA?
    23041: 00/06/10: Re: XCV vs. XCV-E ?
    23049: 00/06/11: Re: math help needed
    23161: 00/06/16: Re: Designing a narrowband bandpass filter to pass a tone (analog
    23282: 00/06/20: Re: Problem copying text from the Spartan II data sheet
    23431: 00/06/25: Re: Different ?
    23433: 00/06/25: Re: Different ?
    23498: 00/06/27: Re: Different ?
    23524: 00/06/28: Re: I cant stand it any more.
    23596: 00/07/02: Re: How much would a PCI core be worth?
    25755: 00/09/19: Re: Virtex-E: LVDS vs LVPECL
    26514: 00/10/18: Re: source PROM 17512
    26516: 00/10/18: Re: source PROM 17512
    26543: 00/10/19: CoolRunner news :(
    26576: 00/10/20: Re: CoolRunner news :(
    26583: 00/10/20: Re: CoolRunner news :(
    29034: 01/02/02: Re: Xilinx question
    29924: 01/03/18: Re: Senior I/O Designer - Canada
    30963: 01/05/04: Re: Reading FPGA output on Parallel Port
    35665: 01/10/12: Re: future Xilinx products wish list ...
    35844: 01/10/19: Re: Glitch Hunting, a true story ;-)
    37014: 01/11/28: Re: Creating a jitter free clock
    38987: 02/01/29: Re: Books on DSP
    38996: 02/01/29: Re: Books on DSP
    39000: 02/01/29: Re: Memory Question on Virtex
    39048: 02/01/30: Re: Memory Question on Virtex
    40412: 02/03/06: Re: FPGA which supports LVDS
    44142: 02/06/12: Re: LVPECL open-emitter interface to Virtex-II
    46117: 02/08/19: Re: Polyphase filtering...
    47140: 02/09/18: Re: using CPLD's inverter in oscillator circuit
    48294: 02/10/15: Re: VHDL v. Verilog, Xilinx v. Altera.
    48794: 02/10/24: Re: LVDS standard
    48869: 02/10/25: Re: 3.3V Device Programmer Suggestions ?
    49096: 02/10/31: Re: Chip for fine delays
    49811: 02/11/21: Re: Sub-busses...
Tom Burns:
    11506: 98/08/20: Re: Newbie seeks cheap fun w/FPGAs
    11507: 98/08/20: Max+Plus II Ver 8.3 compiler problems?
Tom Curran:
    129272: 08/02/19: Re: Which Linux Distro to use for Xilinx tools
tom curran:
    7889: 97/10/27: Re: design sites
    7905: 97/10/28: Re: Counter Problem
    8138: 97/11/20: Re: ? State Machine Design
    8155: 97/11/21: Re: Dr watson & M1
    8372: 97/12/11: Re: Xilinx M1, NT, and 5200
    10905: 98/06/29: Re: I squared C on an FPGA
    10906: 98/06/29: Re: Q: I squared C on an FPGA
    11318: 98/08/04: Re: how much ? prices of Xilinx chips
    13363: 98/11/30: Re: Will XILINX survive?
    14068: 99/01/11: Re: I2C core
    35036: 01/09/18: C designs wanted
    46056: 02/08/15: Re: EDIF netlist from XST
    46111: 02/08/19: xilinx pci troubles with flakey host initiator
    53757: 03/03/21: need vhdl sequential divider
Tom D:
    45075: 02/07/11: Using an FPGA as an embedded system timing master
    45190: 02/07/15: Spartan clock mirroring
Tom Dahlen:
    96911: 06/02/13: spartan-3e starter kit
    97002: 06/02/14: Re: spartan-3e starter kit
Tom Davidson:
    14312: 99/01/25: Re: AHDL VS. VHDL
    18903: 99/11/20: Re: Need advice on interfacing SDRAM modules
Tom Deblauwe:
    51032: 02/12/27: sram cells
    51457: 03/01/14: fpga versus cpld
Tom Del Rosso:
    34256: 01/08/17: Re: star-wars ascii-animation:)
    34292: 01/08/19: Re: star-wars ascii-animation:)
    64432: 04/01/04: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
    125923: 07/11/08: Re: not totally repulsive
Tom Derham:
    59582: 03/08/22: Simulating single module of design in ModelSim (Xilinx)
    60768: 03/09/22: Synchronous counter enable pulse length
    62340: 03/10/27: Input pins that are driven but not used
    69926: 04/05/24: Driving fpga pin out over long cable
    70038: 04/05/28: Re: Driving fpga pin out over long cable
Tom Dillon:
    1366: 95/06/07: Re: Xblox oo !!!!
    1632: 95/08/08: Re: Xilinx xc4013 routing problems ??
    1684: 95/08/15: Re: Xilinx xc4013 routing problems ??
    2439: 95/12/05: Re: Xilinx vs Altera with Verilog/VHDL
    2489: 95/12/17: Re: Gated Clock Problem in Xilinx FPGA Implementation
    2567: 96/01/03: Re: Verilog simulator for PC
    29203: 01/02/09: Re: Low skew lines in Virtex-E
    29205: 01/02/09: Re: Synplify on Windows2000?
    29206: 01/02/09: Re: Xilinx Implementation Error! need help urgently
    29559: 01/02/26: Re: Searching for FPGA designer (PCI interface,DES, IDE)
    30049: 01/03/21: Re: FFT in FPGAs
    30080: 01/03/22: Re: Looking for Processor Core info/advice
    30115: 01/03/23: Re: Looking for Processor Core info/advice
    30196: 01/03/27: Re: Any Expert FPGA Engineers out there?
    31338: 01/05/19: Re: free simulator
    32111: 01/06/14: Re: Video Compression on an FPGA
    32272: 01/06/21: Re: FFT limited size input
    32297: 01/06/22: Re: synplicity 6.2.4 'optimizing' instantiated designs
    33101: 01/07/17: Re: Using the Xilinx Alliance 3.1i/3.3i Tools under Linux
    34979: 01/09/17: Re: FPU core
    35373: 01/10/02: Re: barrel shifter in Xilinx Virtex-E
    35441: 01/10/04: Re: multipliers in virtex-II
    35530: 01/10/10: Re: Help in speeding up image processing
    36799: 01/11/20: Re: Synplicity and BlockRAM?
    36958: 01/11/27: Re: FFT with Distributed Arithmatic
    37288: 01/12/06: Re: Where can I find the implemention of block float multiplier?
    37546: 01/12/14: Re: svf files in webpack 4.2
    38442: 02/01/14: Re: Leonardo + Xilinx tools help
    59494: 03/08/20: Re: BlockRAM in VHDL
    70506: 04/06/18: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
    118714: 07/05/02: Re: prevent ROM inferration
    121377: 07/07/03: Re: Multiplier in Xilinx
Tom Drabenstott:
    2546: 95/12/30: Re: Career value: VHDL or Verilog?
Tom Drake:
Tom Fischaber:
    22169: 00/04/28: Re: A Question on Virtex Configuration
    22152: 00/04/27: Re: Xilinx "length count" question
    23168: 00/06/16: Re: Virtex IRDY and TRDY
    23765: 00/07/07: Re: Before and after configuration, are the undefined I/O ports input or
    30887: 01/05/02: Re: failed to configure virtex
    31023: 01/05/09: Re: Licensing PB in Synplify_pro 6.2
    32615: 01/07/02: Re: Xilinx Foundation vs Foundation ISE?
Tom Gardner:
    152146: 11/07/13: Re: [ANN] HercuLeS high-level synthesis tool
    155099: 13/04/14: Re: Ray Andraka's Book?
    155132: 13/04/25: Re: Low cost and/or small size CPU in an FPGA
    155144: 13/04/26: Re: DEP function development on a low budget
    155235: 13/06/16: Re: New soft processor core paper publisher?
    155237: 13/06/16: Re: New soft processor core paper publisher?
    155240: 13/06/17: Re: New soft processor core paper publisher?
    155268: 13/06/20: Re: New soft processor core paper publisher?
    155276: 13/06/21: Re: New soft processor core paper publisher?
    155278: 13/06/21: Re: New soft processor core paper publisher?
    155285: 13/06/22: Re: New soft processor core paper publisher?
    155286: 13/06/22: Re: New soft processor core paper publisher?
    155294: 13/06/22: Re: New soft processor core paper publisher?
    155295: 13/06/22: Re: New soft processor core paper publisher?
    155296: 13/06/22: Re: New soft processor core paper publisher?
    155299: 13/06/22: Re: New soft processor core paper publisher?
    155304: 13/06/22: Re: New soft processor core paper publisher?
    155313: 13/06/23: Re: New soft processor core paper publisher?
    155328: 13/06/23: Re: New soft processor core paper publisher?
    155340: 13/06/24: Re: New soft processor core paper publisher?
    155346: 13/06/24: Re: New soft processor core paper publisher?
    155352: 13/06/24: Re: New soft processor core paper publisher?
    155357: 13/06/24: Re: New soft processor core paper publisher?
    155359: 13/06/24: Re: New soft processor core paper publisher?
    155363: 13/06/24: Re: New soft processor core paper publisher?
    155366: 13/06/24: Re: New soft processor core paper publisher?
    155376: 13/06/25: Re: New soft processor core paper publisher?
    155380: 13/06/25: Re: New soft processor core paper publisher?
    155384: 13/06/25: Re: New soft processor core paper publisher?
    155387: 13/06/25: Re: New soft processor core paper publisher?
    155400: 13/06/25: Re: New soft processor core paper publisher?
    155406: 13/06/26: Re: New soft processor core paper publisher?
    155422: 13/06/26: Re: New soft processor core paper publisher?
    155435: 13/06/28: Re: New soft processor core paper publisher?
    155439: 13/06/28: Re: New soft processor core paper publisher?
    155442: 13/06/28: Re: New soft processor core paper publisher?
    155443: 13/06/28: Re: New soft processor core paper publisher?
    155445: 13/06/28: Re: New soft processor core paper publisher?
    155453: 13/06/29: Re: New soft processor core paper publisher?
    155454: 13/06/29: Re: New soft processor core paper publisher?
    155455: 13/06/29: Re: New soft processor core paper publisher?
    155456: 13/06/29: Re: New soft processor core paper publisher?
    155457: 13/06/29: Re: New soft processor core paper publisher?
    155458: 13/06/29: Re: New soft processor core paper publisher?
    155460: 13/06/29: Re: New soft processor core paper publisher?
    155466: 13/06/29: Re: New soft processor core paper publisher?
    155470: 13/06/30: Re: New soft processor core paper publisher?
    155471: 13/06/30: Re: New soft processor core paper publisher?
    155509: 13/07/12: Re: New soft processor core paper publisher?
    155510: 13/07/12: Re: New soft processor core paper publisher?
    155526: 13/07/15: Re: Low cost board with built-in USB for fast data transfer and lots
    155528: 13/07/15: Re: Low cost board with built-in USB for fast data transfer and lots
    155536: 13/07/16: Re: Low cost board with built-in USB for fast data transfer and lots
    155539: 13/07/16: Re: Low cost board with built-in USB for fast data transfer and lots
    155541: 13/07/16: Re: Low cost board with built-in USB for fast data transfer and lots
    155734: 13/08/24: Re: Lattice Announces EOL for XP and EC/P Product Lines
    155793: 13/09/05: Re: Altera EP3CLS70U484C8N
    155873: 13/10/09: Re: Book recommendation
    155880: 13/10/11: Re: Book recommendation
    155921: 13/10/16: Zynq devices, boards and suppliers
    155930: 13/10/16: Re: Zynq devices, boards and suppliers
    155931: 13/10/16: Re: Zynq devices, boards and suppliers
    155934: 13/10/17: Re: Zynq devices, boards and suppliers
    155937: 13/10/17: Re: Zynq devices, boards and suppliers
    155938: 13/10/17: Re: Zynq devices, boards and suppliers
    155941: 13/10/18: Re: Zynq devices, boards and suppliers
    155942: 13/10/18: Re: Zynq devices, boards and suppliers
    155944: 13/10/18: Re: reset strategy FPGA Igloo
    155952: 13/10/20: Re: Zynq devices, boards and suppliers
    155961: 13/10/26: Re: reset strategy FPGA Igloo
    155963: 13/10/27: Re: reset strategy FPGA Igloo
    156023: 13/11/11: Re: Zynq devices, boards and suppliers
    156051: 13/11/13: Re: Zynq devices, boards and suppliers
    156079: 13/11/22: Re: microZed adventures
    156080: 13/11/22: Re: microZed adventures
    156081: 13/11/22: Re: microZed adventures
    156087: 13/11/22: Re: microZed adventures
    156089: 13/11/22: Re: microZed adventures
    156132: 13/12/07: Re: Implementing multiple interrupts
    156135: 13/12/07: Re: Implementing multiple interrupts
    156217: 14/01/18: Re: my first microZed board
    156218: 14/01/18: Re: my first microZed board
    156304: 14/02/13: Re: Monostable multivibrator
    156306: 14/02/13: Re: Monostable multivibrator
    156340: 14/03/11: Re: Ball-park price of Xilinx Virtex 7 FPGA?
    156346: 14/03/12: Re: Ball-park price of Xilinx Virtex 7 FPGA?
    156360: 14/03/18: Re: full functional coverage
    156373: 14/03/20: Re: full functional coverage
    156391: 14/03/27: Re: [cross-post][long] svn workflow for fpga development
    156398: 14/03/28: Re: Xilinx ISERDESE2 deserializer primitive behaviour
    156409: 14/03/31: Re: [cross-post][long] svn workflow for fpga development
    156512: 14/04/14: Re: cloud design flow
    156514: 14/04/14: Re: cloud design flow
    156521: 14/04/14: Re: cloud design flow
    156622: 14/05/14: Re: need coding
    156667: 14/05/28: Re: Zynq devices, boards and suppliers
    156672: 14/06/02: Re: Zynq devices, boards and suppliers
    156674: 14/06/02: Re: Trigger implementation on ADC-FPGA
    156752: 14/06/18: Re: PLA? PAL? PLD? GAL?
    156865: 14/07/12: Re: Using FPGA as dual ported ram
    156876: 14/07/15: Re: Using FPGA as dual ported ram
    156879: 14/07/15: Re: Using FPGA as dual ported ram
    156999: 14/08/17: Re: LVDS problem - Black magic anyone?
    157028: 14/09/03: Re: Know any good public FPGA projects to contribute to?
    157031: 14/09/04: Re: Know any good public FPGA projects to contribute to?
    157032: 14/09/04: Re: Know any good public FPGA projects to contribute to?
    157051: 14/09/17: Re: Comparision of Advantages/Disadvantges of Verilog or VHDL in
    157366: 14/11/28: Re: Low-end FPGA mezzanine standard
    157473: 14/12/11: Re: Using FPGA to feed 80386
    157531: 14/12/15: Re: Using FPGA to feed 80386
    157532: 14/12/15: Re: Using FPGA to feed 80386
    157534: 14/12/15: Re: Using FPGA to feed 80386
    157535: 14/12/15: Re: Using FPGA to feed 80386
    157537: 14/12/15: Re: Using FPGA to feed 80386
    157540: 14/12/15: Re: Using FPGA to feed 80386
    157541: 14/12/15: Re: Using FPGA to feed 80386
    157546: 14/12/15: Re: Using FPGA to feed 80386
    157547: 14/12/15: Re: Using FPGA to feed 80386
    157557: 14/12/16: Re: Using FPGA to feed 80386
    157558: 14/12/16: Re: Using FPGA to feed 80386
    157559: 14/12/16: Re: Monitor connections
    157560: 14/12/16: Re: VHDL Synchronization- two stage FF on all inputs?
    157624: 15/01/07: Timing Constraints: are there any "design patterns"
Tom Geocaris:
    1056: 95/04/21: Xilinx Device Information
Tom Handley:
    11309: 98/08/04: Lattice/Synario v5.1 GXRESET Warning
    12635: 98/10/21: Re: isp download cable ?
Tom Hawkins:
    43382: 02/05/20: Synchronous Single Clock Designs
    43428: 02/05/21: Re: Synchronous Single Clock Designs
    50319: 02/12/08: Synthesis and Design Hierarchy
    50642: 02/12/15: EDIF LPM Support in Synthesis
    50662: 02/12/16: Re: EDIF LPM Support in Synthesis
    51705: 03/01/19: New Language Generates Verilog, VHDL, and C
    51814: 03/01/22: Re: VHDL or Verilog?
    53173: 03/03/05: Xilinx EDIF Flow and Blackbox Instantiation
    53258: 03/03/08: Re: Need help! Any experienced Handel-C user?
    53291: 03/03/10: CF Code Examples (Was: Need help! Any experienced Handel-C user?)
    53687: 03/03/19: Re: Using FPGAs as coprocessors in a PC
    53750: 03/03/21: Re: Using FPGAs as coprocessors in a PC
    53826: 03/03/24: Re: FPGA FFT Questions
    53857: 03/03/25: Re: FPGA FFT Questions
    53958: 03/03/28: Recursion and First Class Components
    55173: 03/04/29: Re: Advice on FPGA IIR Filter
    55258: 03/05/01: Re: Advice on FPGA IIR Filter
    55623: 03/05/14: Re: LDPC Code implmentation using XILINX Vertex
    55781: 03/05/19: Re: smallest embedded cpu....and the most pain?
    56028: 03/05/27: Re: FPGA design: firmware or hardware?
    56411: 03/06/04: Re: ANN: Confluence -> Python for Hardware Verification
    59169: 03/08/11: ANN: Confluence 0.6
    60177: 03/09/06: Re: Schematic simulation and then FPGA programming?
    60310: 03/09/10: Embedded/Microcontroller FPGA and Software Defined Radio
    62276: 03/10/23: [ANN] Confluence 0.7.1 Released
    62320: 03/10/26: Re: Modeling hardware in Matlab/Simulink (delay, etc.)?
    62798: 03/11/07: External Modules and FPGA Primitives
    63098: 03/11/14: Inferring Dual Port Block RAM
    67892: 04/03/22: ANN: Confluence 0.9 -- Open Source, Executable Models, Auto Documentation
    68079: 04/03/25: Re: study verilog or vhdl?
    68117: 04/03/26: Re: study verilog or vhdl?
    68865: 04/04/20: Re: Clock Enables and Power
    69352: 04/05/07: Re: How to drive record fields from procedure AND testbench?
    69395: 04/05/10: One issue about free hardware
    69405: 04/05/10: Re: Which board to buy? Status of open source tools?
    69437: 04/05/11: Re: Which board to buy? Status of open source tools?
    69547: 04/05/13: Re: One issue about free hardware
    71887: 04/08/03: Re: Best tool(s) for filter float->fixed->VHDL flow?
    75540: 04/11/08: [ANN] InFormal 0.1.1 Released
    75551: 04/11/09: Re: [ANN] InFormal 0.1.1 Released
Tom Hicks:
    26158: 00/10/05: Simultaneous Switching question
Tom Hoffend:
    24628: 00/08/15: Re: Non-disclosures in job interviews
Tom Holroyd:
    731: 95/02/19: Re: Real-time fractal gen in h/w
    783: 95/03/02: Re: Real-time fractal gen in h/w
Tom J:
    114010: 07/01/02: Xilinx: Connecting an on-chip memory-like component to Microblaze
    114011: 07/01/02: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
    114041: 07/01/03: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
    114048: 07/01/03: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
    114056: 07/01/03: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
    114098: 07/01/04: Re: Xilinx: Connecting an on-chip memory-like component to Microblaze
    114122: 07/01/04: Re: How to deal with the negative value
    114141: 07/01/05: Re: How to deal with the negative value
    117385: 07/03/29: "undeclared here" error and undesired file persistance in Xilinx Platform Studio
    117409: 07/03/30: Re: "undeclared here" error and undesired file persistance in Xilinx Platform Studio
Tom Jackson:
    16243: 99/05/11: Formal Solutions for Static Verification: An ASIC and IC Design
Tom Johnson:
    152005: 11/06/21: Re: Xilinx or Altera
Tom Kaminski:
    31298: 01/05/17: Re: FPGA Express 3.5 One hot state machine Synthesis problem
    31315: 01/05/18: Re: FPGA Express 3.5 One hot state machine Synthesis problem
tom karabinas:
    10131: 98/04/28: High Speed FPGAs??
Tom Kean:
    10508: 98/05/26: Re: XC6200
    11447: 98/08/14: Re: XC6200 Inspector
    11592: 98/08/26: Re: New Evolutionary Electronics Book
    12249: 98/10/06: Re: Design security again - the Actel solution
    12293: 98/10/08: Re: Design security again - the Actel solution
    12794: 98/10/30: Re: FPGA Decouple Capacitor values
    13980: 99/01/06: Looking for old PLD datasheets
    14172: 99/01/17: Re: Intellectual Property
    14468: 99/01/31: Re: Help for the scientifically-challenged
    14908: 99/02/25: Re: Your view on this article?
    15222: 99/03/15: Re: Possible problem with die shrink of xc4010
    15631: 99/04/05: Re: Help: Xilinx FPGA demonstration board and parallel cable iii doesn't
    15778: 99/04/14: Re: bitstream
    16557: 99/05/28: Re: C to EDIF translator??Anyone?
    17072: 99/06/29: Re: 100 Billion operations per sec.!
    17089: 99/06/30: Re: 100 Billion operations per sec.!
    17145: 99/07/03: Re: 100 Billion operations per sec.!
    17202: 99/07/08: Re: 100 Billion operations per sec.!
    17465: 99/07/30: Re: Partial Reconfiguration?
    18552: 99/10/30: Re: need reference to first paper on FPGA
Tom Keaveny:
    1348: 95/06/05: Re: FPGAs for PCI Interfaces
    2682: 96/01/24: Revision Figure of Merit?
    2870: 96/02/21: Re: Xilinx is NOT specified MINIMUM delay -
    2909: 96/02/28: Re: Xilinx is NOT specified MINIMUM delay -
    6485: 97/05/27: Re: Desperate college students need help!!!
Tom Kerrigan:
    25379: 00/09/08: How many 4005s (4010s) does it take to make a general purpose CPU?
    25385: 00/09/08: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
Tom Kirsch:
    59075: 03/08/07: Re: Gates Counting?
Tom Knight:
    6272: 97/05/07: Re: Advantages/disadvantages between CMOS/BiCMOS
Tom Kotwal:
    144841: 10/01/07: new PC specs for Xilinx tools
    144863: 10/01/08: Re: new PC specs for Xilinx tools
Tom Lane:
    13465: 98/12/04: Re: JPEG Core compliance
    13468: 98/12/04: Re: JPEG Core compliance
    13779: 98/12/26: Re: smallest DCT algorithm?
    13829: 98/12/29: Re: smallest DCT algorithm?
    14078: 99/01/12: Re: smallest DCT algorithm?
Tom Leacock:
    19769: 00/01/11: Configuring virtex devices
    20975: 00/03/01: Virtex loading question
    25476: 00/09/12: Virtex 1800 series ISP proms
Tom Liehe:
    2679: 96/01/23: Re: XILINX XACT 6.0.0 Tools flaky
    2680: 96/01/23: Re: AT&T Orca vs Xilinx
    2725: 96/01/30: Re: XILINX XACT 6.0.0 Tools flaky
    17007: 99/06/23: Virtex data sheet is incomplete
    17022: 99/06/25: Re: Virtex data sheet is incomplete
    42296: 02/04/19: Re: Xilinx Programmable World 2002 - Review
    46475: 02/08/30: Re: The Prodigal Son
Tom Loftus:
    40935: 02/03/18: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
    40983: 02/03/19: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
    41475: 02/03/29: Re: Q: Any Virtex II pro development board on market?
    46105: 02/08/19: Poor man's DSP/FPGA instructional tool?
    46326: 02/08/26: Re: Poor man's DSP/FPGA instructional tool?
    46327: 02/08/26: Re: Poor man's DSP/FPGA instructional tool?
    46328: 02/08/26: Re: Poor man's DSP/FPGA instructional tool?
    46329: 02/08/26: Re: Poor man's DSP/FPGA instructional tool?
    46378: 02/08/27: Re: Evaluation board recommendation?
    46380: 02/08/27: Re: Virtex-IIpro Demo-Boards
Tom Loredo:
    42010: 02/04/12: FPGA eval/dev boards with *serial* interface?
    42061: 02/04/14: Re: FPGA eval/dev boards with *serial* interface?
    42089: 02/04/15: Re: FPGA eval/dev boards with *serial* interface?
    52046: 03/01/29: Re: analog in analog out DSP development board for Xilinx
    62638: 03/11/03: Re: Shannon Entropy for Black Holes
Tom Lucas:
    106849: 06/08/21: Re: Hardware book like "Code Complete"?
    110286: 06/10/13: Re: OT: Internships?
Tom Mayo:
    615: 95/01/19: Re: ACTEL and EXEMPLAR
Tom McCarthy:
    57100: 03/06/23: FPGA/ASIC Rework, Repair, replacement
Tom McDermott:
    17610: 99/08/13: Xilinx FPGA FIR filter number format?
Tom McLaughlin:
    16388: 99/05/19: Assigning pad type in Xilinx Virtex FPGA
    16704: 99/06/03: Initial Values, Xilinx Virtex
    16719: 99/06/04: Re: Initial Values, Xilinx Virtex
    16720: 99/06/04: Re: Initial Values, Xilinx Virtex
    17434: 99/07/27: APEX initial values
    18231: 99/10/08: DLL and programmable delay in Xilinx FPGA
    18232: 99/10/08: Xchecker cable
    18870: 99/11/19: Re: Programming Virtex device via JTAG
    18996: 99/11/23: Re: Programming Virtex device via JTAG
    20451: 00/02/10: Master/Serial mode for Virtex
    20487: 00/02/11: Re: Master/Serial mode for Virtex
    20497: 00/02/11: Re: Master/Serial mode for Virtex
    20897: 00/02/25: Xilinx in system programmable proms and JTAG
    21263: 00/03/14: Programming FPGAs via backplane (Xilinx)
    21718: 00/03/29: Global clock nets. Can I use it for signal other than clock.
    21739: 00/03/30: Re: Global clock nets. Can I use it for signal other than clock.
    21998: 00/04/11: Specifying PCI buffer for Xilinx 4000XLA
    22001: 00/04/11: Re: Specifying PCI buffer for Xilinx 4000XLA
    22015: 00/04/12: Re: Specifying PCI buffer for Xilinx 4000XLA
    22270: 00/05/03: INIT pin on Virtex FPGAs
    22407: 00/05/08: Re: INIT pin on Virtex FPGAs
    22591: 00/05/12: CLKing external RAM from FPGA (Virtex E)
    22653: 00/05/16: .adr files for JTAG programmer
    22654: 00/05/16: Re: .adr files for JTAG programmer
Tom Meagher:
    10103: 98/04/27: Enforcing Clock Enable Connection in Synthesis
    10111: 98/04/27: Re: Enforcing Clock Enable Connection in Synthesis
    10140: 98/04/29: Re: Enforcing Clock Enable Connection in Synthesis
    10141: 98/04/29: Re: Enforcing Clock Enable Connection in Synthesis
    10155: 98/04/30: Re: Enforcing Clock Enable Connection in Synthesis
    10168: 98/04/30: Re: Enforcing Clock Enable Connection in Synthesis
    10169: 98/04/30: Re: Enforcing Clock Enable Connection in Synthesis
    10223: 98/05/05: Re: 3.3V design conversion
    10245: 98/05/06: Cool Clock Enable Synthesis Fix
    10310: 98/05/11: Re: Cool Clock Enable Synthesis Fix with Synplify 3.0b
    12256: 98/10/07: Re: Which FPGA tool is better
    12754: 98/10/27: Re: Need VHDL tools for Win NT/ Win 95
    15860: 99/04/16: Re: High speed reconfigurability
    15882: 99/04/18: Re: flex10k 1 gate change
    15883: 99/04/18: Re: High speed reconfigurability
    18894: 99/11/20: Re: orcad synthesis for simplepld
    25188: 00/08/29: Re: Spurious errors in full FPGA?
    25240: 00/08/31: Re: Spartan II vs. Virtex
tom meany:
    17005: 99/06/23: Purchase of Spartan chips on the internet
Tom Moog:
    25600: 00/09/15: Re: hardware compatibility and patent infringement
tom morrow:
    17979: 99/09/20: Back engineer xc3000
Tom Palermo:
    10161: 98/04/30: Re: Enforcing Clock Enable Connection in Synthesis
Tom Pawelko:
    7285: 97/08/21: Altera Flex10K I/O setup time
tom picard:
    12044: 98/09/25: Re: CardBus CIS useless?
Tom Rokicki:
    10507: 98/05/25: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
Tom Seim:
    32473: 01/06/27: Re: Stupid Xilinx Patent
    35524: 01/10/09: Re: FPGA reset
    35556: 01/10/10: Re: FPGA reset
    35557: 01/10/10: Re: Synplicity/Leonardo License Agreement Information
    35817: 01/10/18: Re: I need free PCI-Core (vhdl)!!
    44616: 02/06/24: Re: CIC filter
    44851: 02/07/02: Re: DC to DC converter at 1.5V
    45335: 02/07/19: Counter Metrics
    58746: 03/07/31: Re: Handel C
    58797: 03/08/01: Re: Handel C
    59928: 03/09/01: Re: Moving Sum
    59964: 03/09/02: Re: Moving Sum
    60058: 03/09/04: Re: FPGA/DSP Expert - business partner for innovative FFT
    60059: 03/09/04: Re: Moving Sum
    60079: 03/09/04: Re: New to FPGA, seeking advice
    60154: 03/09/05: Re: Thinking out loud about metastability
    60371: 03/09/11: Re: pipelined divider
    60753: 03/09/21: Re: divide by on spartan3?
    61338: 03/10/01: ISE 6.1 Dies Out of the Gate
    61339: 03/10/01: Re: Frustrations with Marketing
    61390: 03/10/02: Re: Frustrations with Marketing
    61454: 03/10/03: Re: ISE 6.1 Dies Out of the Gate
    61471: 03/10/04: Re: Interesting article about FPGAs
    61485: 03/10/05: Re: Interesting article about FPGAs
    61486: 03/10/05: Re: Free timing diagram drawing software
    62252: 03/10/22: Re: ISE5.2 to ISE6.1
    69603: 04/05/14: Re: best fpga development board?
    70937: 04/07/01: Re: Xilinx $99 Spartan-3 kit
    70938: 04/07/01: Does Xilinx have the worst web site on the planet?
    71222: 04/07/12: Re: Is the Xilinix XC3020 atill supported?
    71233: 04/07/12: Re: Info on FPGA routing algorithms?
    71400: 04/07/16: Re: Would Tom buy from Nu Horizons?
    71983: 04/08/04: Re: Compact FPGA Board?
    72565: 04/08/24: Re: DSP/FPGA/video board?
    75248: 04/10/30: Re: information about Nuhorizon Spartan-3 Development Board ?
    75270: 04/10/31: Re: FPGA board checking
    74366: 04/10/08: Re: FPGA for OCR processing
    74607: 04/10/14: Re: spartan 3 on 4 layers
    75750: 04/11/13: Re: Digital LP filter in multiplier free FPGA
    76079: 04/11/23: DO NOT use Nu Horizons for a supplier
Tom Smythers:
    4830: 96/12/18: PLD
Tom St Denis:
    26399: 00/10/14: Re: CHES 2001 Workshop
    26449: 00/10/16: Re: CHES 2001 Workshop
    26450: 00/10/16: Re: CHES 2001 Workshop
    35775: 01/10/17: memory cell
    35779: 01/10/17: Re: memory cell
    35803: 01/10/18: Re: 8051 timing diagrams
    35893: 01/10/22: Hardware help requested
    36053: 01/10/27: Re: How to make an implementable big counter?
    36054: 01/10/27: Re: How to make an implementable big counter?
    41610: 02/04/03: Re: Data Compression in FPGAs
    41613: 02/04/03: Re: Data Compression in FPGAs
Tom Standley:
    4621: 96/11/21: Re: FPGA Gate Counts: No Truth in Advertising
tom sutherland:
    11973: 98/09/22: 2D- FFT of image in ALTERA FLEX 10k ?
Tom Tassignon:
    61204: 03/09/30: c++ lcd device driver 2vp4
    61853: 03/10/14: newbie linker script question
Tom Tooley:
    4063: 96/09/06: ..people NOT using Xilinx
Tom Torfs:
    69199: 04/04/29: turning off clock for parts of design
Tom Twist:
    89597: 05/09/20: Re: SoC embedded FPGA
Tom Van Uffelen:
    29885: 01/03/15: Using Virtex DLLs in Leonardo
Tom Varghese:
    230: 94/09/29: Re: Lattice ISP software: really good
Tom Verbeure:
    30951: 01/05/04: Re: Use of record type in a hierarchical architecture
    31260: 01/05/16: Re: PCI The Real Hardware
    31274: 01/05/16: Re: PCI The Real Hardware
    31448: 01/05/24: Re: Vhdl coding style for fpga
    31705: 01/06/03: Re: pci pads
    33446: 01/07/26: Re: Scope of libraries in leonardo spectrum
    36732: 01/11/18: Re: CASE vs. IF statements
Tom Vrankar:
    5545: 97/02/24: Q: Xilinx PPR Strategy Tips?
    23996: 00/07/20: Q: PAL22V10 JEDEC file-toVHDL translators?
    96220: 06/01/31: Ethernet : MAC vs PHY
    96264: 06/02/01: Re: Ethernet : MAC vs PHY
Tom Wyckoff:
    33121: 01/07/17: Newbie Question
    33299: 01/07/23: Re: Newbie Question
Tom&Janet Engel:
    15352: 99/03/20: Re: Placement control in ALtera devices
<tom.brooks@intransa.com>:
    86602: 05/06/30: LogiCore: SGMII autonegotiation
<tom@pixelmetrix.com>:
    94134: 06/01/05: PCI connection to PLB in Xilinx Virtex 4, what is required?
<tom_schaal@my-dejanews.com>:
    11731: 98/09/04: Re: FIFO Design problem
<tom_systek@msn.com>:
    30216: 01/03/28: Wanted: test vector generation software
Tomas:
    53116: 03/03/04: Mac Os X for FPGA design
    53234: 03/03/07: Re: Mac Os X for FPGA design
    68221: 04/03/30: Athlon FX vs Pentium 4 benchmarks for xilinx's par
Tomas D.:
    156550: 14/04/22: Re: JTAG issues Cyclone V SoC
    157020: 14/08/31: Functional safety guidelines
    157322: 14/11/21: Re: Bypass Xilinx flexlm license check
    157343: 14/11/25: Re: Bypass Xilinx flexlm license check
    157351: 14/11/26: Re: Bypass Xilinx flexlm license check
    157361: 14/11/27: Re: Low-end FPGA mezzanine standard
    157622: 15/01/07: Image rotation
    157628: 15/01/08: Re: Image rotation
    157649: 15/01/19: Re: Altera Cyclone II
Tomas Davidovic:
    120110: 07/06/01: ML402 development board
    120135: 07/06/01: ML402 development board
    120146: 07/06/01: Re: ML402 development board
Tomas Lopez:
    49000: 02/10/29: Leonardo 2002d and virtex2_multipliers
Tomas Whitlock:
    217: 94/09/26: XC1765DPD8C
    257: 94/10/04: Re: XC1765DPD8C
    324: 94/10/19: XC3000 series FPGA with XAbel
    8354: 97/12/10: Busses on XC6264
Tomasz Brychcy:
    21776: 00/03/31: 82C54
    21778: 00/03/31: Warning during synthesis
    21902: 00/04/06: Warnings during mapping
    21979: 00/04/11: Programator for xilinx
    21983: 00/04/11: Errors during synthesis
    21986: 00/04/11: Errors during translation
    21828: 00/04/03: Error during synthesis
    22433: 00/05/09: Nets or regs
    22692: 00/05/18: Translate to verilog
    24646: 00/08/16: clock variable problem
    24650: 00/08/16: error during synthesis
    25195: 00/08/30: Synthesis
    25197: 00/08/30: Latches
    25242: 00/09/01: Error during synthesis
    25460: 00/09/12: OUTs after synthesis?
    25461: 00/09/12: Simulation problem
    25830: 00/09/22: Is correct code?
    25464: 00/09/12: Odp: Simulation problem (attached files)
    30745: 01/04/27: back annotation
    30746: 01/04/27: difference?
    30985: 01/05/08: analog and digital?
    31008: 01/05/09: floorplaning and layout
    35873: 01/10/22: What is a difference?
    36995: 01/11/28: What is a difference?
Tomasz Dziecielewski:
    102625: 06/05/18: Clocking ZBT RAM via DCM on ML40x board
    102682: 06/05/19: Re: Clocking ZBT RAM via DCM on ML40x board
    103074: 06/05/25: Metastability question (newbie)
Tomasz Nakielski:
    28644: 01/01/19: Re: About programming cables
Tomasz Pinkiewicz:
    18188: 99/10/06: I/O Interface for Xilinx FPGA
TomC:
    29868: 01/03/14: FLEX10 config with AT17xxx 8DIP device?
<tomchan95124@yahoo.com>:
    83787: 05/05/06: Re: EDK "libSecurity.dll"
<tomderham@my-deja.com>:
    28339: 01/01/08: FPGA for radar digital downconversion
    28654: 01/01/19: Re: FPGA for radar digital downconversion
Tomek:
    25824: 00/09/21: Category : tri state data bus
    25825: 00/09/21: Category : Why CRs are cleared?
    25826: 00/09/21: Category : timinig testbench
    29150: 01/02/08: Re: Verilog model of I2C/SMB
    31869: 01/06/07: FBGA & uC 8031
    31877: 01/06/07: FPGA & uC8031
    32199: 01/06/19: Flexlm and Win2k
    33070: 01/07/17: PROBLEM!!!
    33559: 01/07/30: ERROR
    33681: 01/08/02: Re: ERROR
tomlih:
    45992: 02/08/13: About configuration of Virtex-e&Prom
    46025: 02/08/14: S.O.S
tommy:
    15391: 99/03/22: Frequency synthesis techniques?
    149286: 10/10/14: change with sums and shifts
Tommy Thorn:
    67515: 04/03/13: NIOS 2.0 ALU [Was: 300MHz spartan3 cpu update, and Webpack 6.2 shocker]
    67564: 04/03/14: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
    68735: 04/04/16: Osborne [Was: Apples to Apples? Stratix II <> Virtex-II Pro]
    68978: 04/04/23: Re: Best Xilinx toolchains for under $2,000 ?
    69999: 04/05/26: Re: Read/Write data from/to SRAM
    70081: 04/06/02: Re: Seven leading PC processors benchmarked on Quartus-II Web Ed
    70241: 04/06/10: Re: lancelot VGA daughter board for altera nios dev board
    70242: 04/06/10: Re: Nios II really available ?
    70294: 04/06/11: Re: SDRAM
    74513: 04/10/13: Re: EP1C12 or XC3S400?
    75071: 04/10/26: Re: Hello Xilinx folks -- please answer
    74585: 04/10/14: Re: 64 bit version of xilinx ISE
    77092: 04/12/22: Re: Memory Controller
    77161: 04/12/27: Re: Doubt on DDR SDRAM read/write operation sequence.
    77236: 04/12/31: Re: Altera NIOS II/Stratix II vs Xilinx Products
    77247: 05/01/01: Re: Altera NIOS II/Stratix II vs Xilinx Products
    78050: 05/01/24: Re: Microscope examination of a PLD
    78728: 05/02/07: Re: Quality of Xilinx ML401 video output?
    79080: 05/02/14: Re: Fast counting
    79082: 05/02/14: Re: Fast counting
    79102: 05/02/14: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
    79104: 05/02/14: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
    79216: 05/02/15: Re: Fast counting in Spartan 3
    79992: 05/02/28: Quartus 4.2 SP1 woes with Samba & !@#$ "Flex"LM
    80943: 05/03/15: Re: Which HDL?
    81067: 05/03/17: Re: Quartus II and DSE
    81129: 05/03/18: Re: Quartus II and DSE
    81134: 05/03/18: Re: Which HDL?
    81463: 05/03/24: Re: Xilinx ISE 7.1 - Can this get any worse?
    82120: 05/04/07: Re: x86 Core?
    84114: 05/05/12: Re: An FPGA eval board at $49!!
    84133: 05/05/12: Re: V4 vs. Stratix-II...
    84557: 05/05/21: Re: FPGA design under Mac OS X ?
    86006: 05/06/20: Speeding up FPGA designs
    86106: 05/06/22: Re: Low cost altera board
    86211: 05/06/23: Re: simple SRAM memory controller Avnet V2P development board
    86337: 05/06/25: Re: Module integration, odd state machine behaviour (verilog), etc!
    86359: 05/06/26: Re: Module integration, odd state machine behaviour (verilog), etc!
    86982: 05/07/12: Quartus 5.0sp1 -- Error: Unexpected error in JTAG server -- error
    87676: 05/07/28: Re: simple SRAM memory controller on the Altera Nios Dev Kit (Cyclone
    87716: 05/07/29: Re: simple SRAM memory controller on the Altera Nios Dev Kit (Cyclone
    88520: 05/08/21: Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;
    88799: 05/08/29: Re: Best FPGA for floating point performance
    99621: 06/03/27: Re: Spartan 3e Starter Kit finally available? No, not really.
    99757: 06/03/28: Cyclone II EP2C70 dev kits, where are they?
    99840: 06/03/29: Re: Cyclone II EP2C70 dev kits, where are they?
    99842: 06/03/29: Re: OpenSPARC released
    100434: 06/04/08: Re: C-Compiler for free VHDL controller core ?
    100522: 06/04/10: Re: Very basic question
    100650: 06/04/14: Re: Cyclone II EP2C70 dev kits, where are they?
    100770: 06/04/17: Quartus SignalTap and bus turn around
    100775: 06/04/18: Re: Quartus SignalTap and bus turn around
    101280: 06/04/28: Re: Cyclone II EP2C70 dev kits, where are they?
    101558: 06/05/02: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
    101597: 06/05/03: Re: Measuring Light with LED and FPGA
    102827: 06/05/21: Re: Superscalar Out-of-Order Processor on an FPGA
    102828: 06/05/21: Re: LISP Workshop at ECOOP06
    103878: 06/06/13: Re: FSM state minimization with ISE?
    103880: 06/06/13: Re: FSM state minimization with ISE?
    103881: 06/06/13: Re: FSM state minimization with ISE?
    103908: 06/06/14: Time for a new "Largest FPGA with free tool support"?
    103913: 06/06/14: Re: Time for a new "Largest FPGA with free tool support"?
    104009: 06/06/16: Re: Time for a new "Largest FPGA with free tool support"?
    104242: 06/06/21: XST crashes & websupport denies access
    104401: 06/06/26: Re: ISE WebPack 8.2
    104564: 06/06/29: Re: How to evaluate the space efficiency of a historic design.
    104824: 06/07/06: Re: Fastest platform to run Place & Route?
    104949: 06/07/10: Re: LUT4 INIT value to implement 2:1 MUX ?
    104996: 06/07/11: Re: Assigning unused pins in Quartus II
    105014: 06/07/11: Re: Assigning unused pins in Quartus II
    105195: 06/07/17: Re: ISE 8.2 WebPack does not support Virtex-5 at all?
    105348: 06/07/20: Re: Last Chance for Tarfessock1 Features
    105402: 06/07/21: Re: Hardware book like "Code Complete"?
    105776: 06/07/31: Re: DDR2 SRAM Stratix II questions
    106009: 06/08/04: Re: Newbie question about SDRAM usage
    106231: 06/08/09: Re: Spartan 3E starter kit DDR SDRAM code
    106232: 06/08/09: Re: A Newbie question
    106338: 06/08/11: Re: JOP as SOPC component
    106421: 06/08/12: Re: JOP as SOPC component
    106422: 06/08/12: Re: JOP as SOPC component
    106424: 06/08/12: Re: Dio5 interface with ps2 port
    106425: 06/08/12: Re: JOP as SOPC component
    106473: 06/08/13: Re: JOP as SOPC component
    106597: 06/08/15: Re: Alternatives to 2v6000
    106636: 06/08/16: Re: Alternatives to 2v6000
    106662: 06/08/16: Re: xilinx or altera?
    106666: 06/08/16: Re: xilinx or altera?
    106678: 06/08/17: Reinstalled Quartus + Nios II => cygwin1.dll hell :-(
    106768: 06/08/18: Re: JOP as SOPC component
    107019: 06/08/23: Re: JOP as SOPC component
    107050: 06/08/23: Re: Xilinx ML501 availability
    107091: 06/08/24: Re: JOP as SOPC component
    107093: 06/08/24: Re: Who should buffer, fabric or slave? [was: JOP as SOPC component]
    107248: 06/08/25: Re: fastest FPGA
    107375: 06/08/27: Re: JOP as SOPC component
    107669: 06/08/30: Re: ISE licensing
    107743: 06/08/31: Re: ISE licensing
    107895: 06/09/01: Re: Higher voltages input, quick check....
    108532: 06/09/12: Re: fastest FPGA
    108717: 06/09/15: Re: Digilent 3S200 pcb + webpack ISE 8.2 + service pack
    108721: 06/09/15: Re: Digilent 3S200 pcb + webpack ISE 8.2 + service pack
    108954: 06/09/19: Re: ddr clock issues
    109005: 06/09/19: Re: Virtex-5LX
    109055: 06/09/20: Re: Buffering the critical path.
    109607: 06/09/30: System ACE woes
    109621: 06/10/01: Re: System ACE woes
    109791: 06/10/05: Re: System ACE woes
    109916: 06/10/07: Re: System ACE woes
    109919: 06/10/08: Re: System ACE woes
    110062: 06/10/10: ML501 finally released
    110184: 06/10/11: Re: ISE/EDK computer selection
    110256: 06/10/12: Re: Which Xilinx FPGA/board?
    110318: 06/10/13: Re: Last ISE version that supports XC95xxXL ?
    110677: 06/10/19: FAQ: Re: Fastest ISE Compile PC?
    110739: 06/10/20: Re: FAQ: Re: Fastest ISE Compile PC?
    111425: 06/11/02: Re: Scientific Computing on FPGA
    111486: 06/11/03: Missing constraints [Re: a new spartan3E 1600 starter kit available ?]
    111502: 06/11/03: Re: Missing constraints [Re: a new spartan3E 1600 starter kit available ?]
    111706: 06/11/08: New Quartus 6.1 is multi-threaded
    113002: 06/12/04: Re: Opencores DDR SDRAM controller
    113012: 06/12/04: Re: Opencores DDR SDRAM controller
    113074: 06/12/05: Re: Altera starter kits
    113275: 06/12/09: Re: Opencores DDR SDRAM controller
    113351: 06/12/11: Re: Tarfessock1
    113487: 06/12/14: Re: FPGA : Async FIFO, Programmable full
    113538: 06/12/15: Re: FPGA : Async FIFO, Programmable full
    113546: 06/12/15: Re: FPGA : Async FIFO, Programmable full
    113815: 06/12/22: Re: Virtex-5 Webpack?
    115037: 07/01/29: Re: video buffering scheme, nonsequential access (no spatial locality)
    115041: 07/01/29: Re: video buffering scheme, nonsequential access (no spatial locality)
    115125: 07/01/31: Re: DDR FPGA Design
    115289: 07/02/05: Re: DDR FPGA Design
    115507: 07/02/12: Re: Which is your favorite FPGA language?
    116925: 07/03/20: Re: Why is Xilinx's WebPACK so inferior?
    116931: 07/03/20: Re: Why is Xilinx's WebPACK so inferior?
    117493: 07/04/02: Re: Spartan-3A XC3S1400A development board?
    117691: 07/04/06: Re: Transition from ASIC to FPGA
    119451: 07/05/19: Re: releasing some FPGA tools-ip as open-source
    119872: 07/05/28: Re: 6502 FPGA core
    120080: 07/05/31: Re: Spartan-3E DIG-3E1600 Development Board Kit
    120162: 07/06/01: Re: Weekend pop quiz
    120186: 07/06/02: Re: Weekend pop quiz
    120652: 07/06/13: Stolen Spartan 3E-1600 Development Board
    120993: 07/06/21: Re: Nios II problem
    121934: 07/07/15: Re: Which embedded O/S for a 32-bit RISC microcontroller?
    122026: 07/07/17: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
    122361: 07/07/26: Re: Altera or Xilinx
    122588: 07/07/31: Re: Altera Cyclone II and Cyclone III "distributed" RAM?
    122618: 07/08/01: Re: ASIC Digital Design Blog
    122643: 07/08/02: Re: Static Timing Analysis Using Primetime for FPGAs
    122680: 07/08/02: Re: Spartan 3E starter kit DDR SDRAM
    122827: 07/08/08: Re: New Xilinx forum.
    123083: 07/08/15: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits
    123085: 07/08/15: Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits
    123129: 07/08/16: Re: New Xilinx forum.
    124606: 07/09/28: Re: Never buy Altera!!!!
    124609: 07/09/28: Re: Bug in Synplify?
    124683: 07/09/30: Re: Own soft-processor
    124697: 07/10/01: Re: Own soft-processor
    124973: 07/10/13: Re: Quartus II 7.2 web edition - Linux or not?
    124977: 07/10/14: Re: FPGA tools under VMware or Parallels on a Mac?
    124990: 07/10/15: Re: Quartus II 7.2 web edition - Linux or not?
    125453: 07/10/25: Re: is Quartus 7.1 really that S*** !?
    125922: 07/11/08: Re: Spartan 3E Starter Kit DDR RAM
    126235: 07/11/17: Quartus II warning: "pass-through logic has been added"
    126276: 07/11/18: Re: Quartus II warning: "pass-through logic has been added"
    126559: 07/11/27: Re: yet another Altera Cyclone II EP2C35 dev. board
    126858: 07/12/04: Re: Can't get Quartus to Infer Dual Port Ram for Stratix2GX
    126946: 07/12/06: Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC
    126977: 07/12/07: Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC
    127000: 07/12/08: Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC
    127780: 08/01/08: Re: Compilation of Plasma SW under Linux
    127996: 08/01/11: Re: Place-and-Route : Intel vs AMD
    128897: 08/02/08: Re: My first verilog/cpld project
    129271: 08/02/19: Re: Efficient division algorithm?
    129900: 08/03/08: Re: Cyclone III and Quartus 7.2sp2
    129901: 08/03/08: Re: Altera Quartus II v7.2 SP2 under openSUSE 10.3 (i686)
    129906: 08/03/09: Re: Cyclone III and Quartus 7.2sp2
    130308: 08/03/20: Re: A Challenge for serialized processor design and implementation
    131681: 08/04/29: Could someone tell me NIOS II/MB performance on this benchmark?
    131701: 08/04/29: Re: Could someone tell me NIOS II/MB performance on this benchmark?
    131702: 08/04/29: Re: Could someone tell me NIOS II/MB performance on this benchmark?
    131724: 08/04/29: Re: how to optimize this comparator for better synthesis result?
    131931: 08/05/07: Re: Forking in One-Hot FSMs
    132793: 08/06/06: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
    132919: 08/06/10: Re: Whitepapers are taking over the lost TechXclusives
    132978: 08/06/11: Re: Altera Quartus Web Edition 8.0 available
    133010: 08/06/13: Re: Altera Quartus Web Edition 8.0 available
    135106: 08/09/16: Re: Moving to Altera from Xilinx
    135108: 08/09/16: Re: need fast FPGA suggestions [ AFPGA ? ]
    135331: 08/09/26: Clocking Sync Burst SRAM
    135333: 08/09/26: Re: maximum clock rating
    135354: 08/09/27: Re: Clocking Sync Burst SRAM
    135357: 08/09/27: Re: Clocking Sync Burst SRAM
    135757: 08/10/14: Re: CPU Model for Co-simulation
    136531: 08/11/20: Re: vga interfacing for image display
    136694: 08/12/01: Re: Terasic DE1 board commentary
    139370: 09/03/27: Re: best soft core(s) that have C compiler support
    139378: 09/03/27: What does Xilinx mean by "Real 6-input look-up (LUT) technology"?
    139379: 09/03/27: Re: best soft core(s) that have C compiler support
    139435: 09/03/29: Re: best soft core(s) that have C compiler support
    139436: 09/03/29: Re: best soft core(s) that have C compiler support
    139438: 09/03/29: Re: best soft core(s) that have C compiler support
    139439: 09/03/29: Re: best soft core(s) that have C compiler support
    139454: 09/03/30: Re: Fiber optics protocols for mid range speed
    139870: 09/04/17: Re: Virtex-6 shipping?
    140119: 09/04/29: Re: best soft core(s) that have C compiler support
    140510: 09/05/15: Re: verilog in TV show (soon)
    140511: 09/05/15: Re: some soft-processors
    140624: 09/05/20: Re: Open source processors
    140625: 09/05/20: Re: please recommend a soft processor for small image processing
    140639: 09/05/20: Re: Open source processors
    141092: 09/06/04: Re: Open source processors
    141130: 09/06/08: Re: Open source processors
    141146: 09/06/08: Re: Open source processors
<TommyInTheNews@numba-tu.com>:
    67272: 04/03/09: Re: Release asynchrounous resets synchronously
    67454: 04/03/12: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
    67455: 04/03/12: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
Tomoya:
    92451: 05/11/29: Clock problem? Altera Stratix-II ES and MP
    92742: 05/12/05: Re: Clock problem? Altera Stratix-II ES and MP
Tomppa:
    28001: 00/12/19: Re: 3V -> 5V clock signal level conversion
tomrohit:
    115251: 07/02/05: Re: PCI Express user group
    116141: 07/03/02: Re: PCI-E TS1s
<tomstdenis@gmail.com>:
    101304: 06/04/28: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
    101308: 06/04/28: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
    101310: 06/04/28: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
    101324: 06/04/28: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
    101727: 06/05/05: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
Tonda:
    131733: 08/04/30: Re: how can i recover my unencrypted bitstream starting from
<tonerchips@hotmail.com>:
    100525: 06/04/10: want technical assistance in making toner chips
    100843: 06/04/19: Re: want technical assistance in making toner chips
Tong:
    67261: 04/03/09: novice for FPGA
    67311: 04/03/10: Re: novice for FPGA
    67377: 04/03/11: Re: novice for FPGA
Toni:
    81468: 05/03/24: Programming with XC17S15
Toni Merwec:
    125570: 07/10/29: 2 FPGAs /w programming FLASH in one JTAG chain
    125698: 07/11/01: Re: 2 FPGAs /w programming FLASH in one JTAG chain
    125703: 07/11/01: Re: 2 FPGAs /w programming FLASH in one JTAG chain
    126174: 07/11/16: jitter-sensitive multi-output clk distribution for multi-gigabit-transceivers
<tonico>:
    122442: 07/07/27: Question about GSR?
    122455: 07/07/27: Re: Beginners question
    122483: 07/07/28: Re: Beginners question
<Tonico>:
    122283: 07/07/25: Beginners question
    122288: 07/07/25: Re: Beginners question
    122301: 07/07/25: Re: Beginners question
    122303: 07/07/25: Re: Beginners question
    122307: 07/07/25: Re: Beginners question
    122308: 07/07/25: Re: Beginners question
    122309: 07/07/25: Re: Beginners question
    122315: 07/07/25: Re: Beginners question
    122323: 07/07/25: Documentation/leds/simulation
Tonny:
    64020: 03/12/12: Re: about digilent board
    64609: 04/01/08: Re: Dual Port RAM Block RAM using Core Generaot
    64946: 04/01/16: Xilinx ISE 6.1 problem
    74980: 04/10/22: System Generator problem with XtremeDSP
    75152: 04/10/27: SysGen 6.2: Error when generating hardware cosim
Tony:
    17392: 99/07/24: Re: EVERYTHING YOU WANT !!!! 7306
    18769: 99/11/13: Re: New Altera Max+Plus II full VHDL $1K
    63290: 03/11/19: Re: Problems Configurating MicroBlaze into RC200 board
    65288: 04/01/23: software tool kits for openrisc
    66597: 04/02/23: ML300 EDK 6.1 Simulations
    67914: 04/03/22: EDK 6.1 and MGT UCF Inst Parameters
    67934: 04/03/23: Re: EDK 6.1 and MGT UCF Inst Parameters
    67968: 04/03/23: IBUFDS -> BUFG
    67969: 04/03/23: Re: EDK 6.1 and MGT UCF Inst Parameters
    67973: 04/03/23: Re: IBUFDS -> BUFG
    68014: 04/03/24: Re: IBUFDS -> BUFG
    68358: 04/04/02: ML300 and GigE Experiences
    68382: 04/04/02: Re: ML300 and GigE Experiences
    68384: 04/04/02: Re: ML300 and GigE Experiences
    68385: 04/04/02: Re: ML300 and GigE Experiences
    68499: 04/04/06: EDK 6.2 and Linux
    86644: 05/07/01: Foundation 3.1 in WinXP machine Problems!
    86655: 05/07/01: Re: Foundation 3.1 in WinXP machine Problems!
    107484: 06/08/29: Do I need to adjust sdram clk shift when i lower my system clock?
    107539: 06/08/29: Re: Do I need to adjust sdram clk shift when i lower my system clock?
    107594: 06/08/30: Re: Do I need to adjust sdram clk shift when i lower my system clock?
tony:
    38634: 02/01/19: Re: Audio time delay circuit
    38635: 02/01/19: FS VME BUS Cages ELMA
    44228: 02/06/14: 6505 ip core
    47169: 02/09/19: Modelsim XE question
    47197: 02/09/20: Re: Modelsim XE question
Tony Acquah:
    91464: 05/11/07: VHDL algorithm/code for implementing QAM on FPGA
Tony Ambardar:
    4732: 96/12/08: Controlling Xilinx Xchecker cable...
Tony Benham:
    36420: 01/11/08: Re: Hex numbers in VHDL
    36422: 01/11/08: Re: Hex numbers in VHDL
    65788: 04/02/06: Help with BUFGMUX in Xilinx Virtex2 and Timing constraints ?
tony boyle:
    8990: 98/02/12: Checksums and xchecker
Tony Burch:
    22296: 00/05/04: [Ann] Lowest Cost FPGA Proto Kits SALE
    22602: 00/05/13: Re: HELP - what to choose?
    22701: 00/05/18: [Final Ann] New FPGA Proto Kits Sale Extended for a short time
    22862: 00/05/29: Re: Buying FPGAs in Germany
    23479: 00/06/27: Re: Virtex Demo Board
    23601: 00/07/02: ANN: FPGA Proto Kits now 25% cheaper
    23834: 00/07/12: Re: XC2018 development system xact5 or xact6 sale?
    23952: 00/07/18: Re: FPGA Intro
    23967: 00/07/19: Re: download to a xilinx fpga
    24497: 00/08/11: [Ad] Overstocked on Xilinx Spartan FPGA Proto Kits
    24527: 00/08/12: Re: Getting into FPGAs
    25992: 00/09/30: Re: FPGA development on the cheap?
    26610: 00/10/22: ANN: Make use of your XC4000 chips with a low cost kit
    27781: 00/12/08: Re: FPGA starter kit
    27794: 00/12/09: Re: PLCC adapter
    28008: 00/12/20: New 200K gate, low cost FPGA proto kit
    28009: 00/12/20: Re: FPGA and Board for Microprocessor Design?
    28101: 00/12/21: Re: FPGA and Board for Microprocessor Design?
    28322: 01/01/07: Re: FPGA starter kit recommendations
    29116: 01/02/07: Re: Help for a novice. Where to begin?
    29118: 01/02/07: Re: faq or just basic info
    29219: 01/02/10: Re: Xilinx 4010E development kit
    29461: 01/02/23: Re: How to get Xilinx FPGA demo board?
    29539: 01/02/26: Re: VDHL Book recomendation please. Xilinx designer.
    30653: 01/04/21: Re: What is a FPGA ?
    31291: 01/05/17: Re: Getting Started with FPGAs
    31479: 01/05/28: Re: Internal tri states
    31493: 01/05/28: Re: Internal tri states
    31516: 01/05/29: Re: what cables and softwares do you need to use "Xilinx FPGA Demonstration Evaluation Board"?
    31859: 01/06/07: Re: FPGA / starterkit / VHDL
    31863: 01/06/07: Ann: Low cost FPGA-CPU prototyping kit-set released
    31918: 01/06/08: Re: XC4005XL is it a modern chip?
    32016: 01/06/11: FPGA design tips in new monthly e-newsletter
    32688: 01/07/05: Re: 8031 microcontroller on FPGA development board :-(
    33005: 01/07/15: Re: Which Chip Family?
    33029: 01/07/16: Re: Which Chip Family?
    33124: 01/07/18: Re: processor core
    33877: 01/08/08: Re: I NEED TO BUY A FPGA BOARD
    33932: 01/08/09: Re: interfacing XILINX XC95 to PC parallell port
    36752: 01/11/20: Ann: Low cost Spartan2 FPGA board
    37776: 01/12/20: Ann: FPGA board Super-Value-Pack released
    37943: 01/12/27: Re: Look for FPGA Starterkit
    44207: 02/06/14: Re: 20,000 gates?
    44330: 02/06/18: Re: Pls Recommend a Development Board
    44717: 02/06/28: Re: XESS / Digilent / Trenz Board Experience ? Help.
    44946: 02/07/08: Re: Newbie FPGA recommedation
    46345: 02/08/27: Re: Poor man's DSP/FPGA instructional tool?
    47633: 02/10/01: Re: Anyone knows of a example FPGA design which reads and writes a SmartMedia card?
    47676: 02/10/02: Re: Getting started
    48322: 02/10/16: Re: DIY Xilinx Parallel Cable III
    48601: 02/10/22: Re: Hobbyist FPGA
    51068: 02/12/30: Re: free fpga soft core
    59014: 03/08/07: Re: JTAG programmers
    71368: 04/07/16: News, Sydney-X1 FPGA Computer Challenges Commodore, Amiga and Apple
    71567: 04/07/22: Sydney-X1 FPGA Computer, US$499 introductory price
    72644: 04/08/27: FPGA Board Newsletter August 2004
    73220: 04/09/16: Re: Looking for a Design for a Small FPGA Board
    76694: 04/12/09: Re: Open source FPGA EDA Tools
    76699: 04/12/09: BurchED FPGA Newsletter, December 2004
    84126: 05/05/13: Re: Minimum circuit to get Spartan-3 running
    98398: 06/03/10: New Sydney-X2 FPGA development system
    101457: 06/05/02: BurchED FPGA Expansion Modules, 4-for-1 offer
    101670: 06/05/05: Re: BurchED FPGA Expansion Modules, 4-for-1 offer
    101805: 06/05/07: Re: BurchED FPGA Expansion Modules, 4-for-1 offer
    106061: 06/08/07: Who is your favourite FPGA guru?
    124847: 07/10/08: JTAG interconnect testing, prototypes
    124970: 07/10/13: Re: JTAG interconnect testing, prototypes
    126674: 07/11/30: Hand solder that FPGA on your prototype
    126724: 07/11/30: Re: Hand solder that FPGA on your prototype
    126761: 07/12/02: Re: Hand solder that FPGA on your prototype
    128777: 08/02/07: Single Top FPGA Tips
    128800: 08/02/07: Re: Single Top FPGA Tips
    128916: 08/02/10: Re: Single Top FPGA Tips
    129943: 08/03/12: Ann: New FPGA beginner's Video guide
    129972: 08/03/12: Re: New FPGA beginner's Video guide
    129975: 08/03/12: Re: New FPGA beginner's Video guide
    130129: 08/03/16: Re: Problem with Spartan 3 StarterKit
    130637: 08/03/29: FPGA beginner video guide, blog comments by Max Maxfield
    130638: 08/03/29: Newbies: Answer to "What is an FPGA?" in video
    133718: 08/07/11: Re: Regarding Xilinx tool
    134582: 08/08/20: FPGA Videos - Olympics Celebration Sale
    134583: 08/08/20: Re: FPGA Videos - Olympics Celebration Sale
    135181: 08/09/20: Re: Help~ How to develope with FPGA board?
    135213: 08/09/21: Re: Peter says Good Bye
    135299: 08/09/25: FPGA Lab Liquidation Sale
    135991: 08/10/26: Re: Looking for a FPGA board for starter
    140558: 09/05/17: Re: Getting started with FPGA
Tony C:
    72657: 04/08/27: Xilinx Spartan 3 DCM/DFS
Tony Clark:
    2816: 96/02/12: Re: Altera Simulation
    2817: 96/02/12: Re: Xilinx is NOT specified MINIMUM delay -- is it right??
    3560: 96/06/23: Altera place and route
    3859: 96/08/10: Re: An incompatible problem of ALTERA MAXPLUS2 Ver6.2, Ver 6.1 -- need your help
    8203: 97/11/27: Re: FPGAs for hobbyist, HELP
Tony Cooper:
    7816: 97/10/18: XILINX Severe Gate minimisation within XACT 6 problem/question?
    7817: 97/10/18: [Reposted due to Enlow UCE cancel]: XILINX Severe Gate minimisation within XACT 6 problem/question?
    7844: 97/10/22: Xilinx 5200 libraries and the AND2B1 gate
    10573: 98/06/01: Xilinx XL Pin supply current
    11008: 98/07/10: Re: high-speed place and route
    11009: 98/07/10: Re: Configure with BIT file
    11283: 98/08/02: Just wondrin bout Xilinx stuff.......
    11488: 98/08/19: Linux Toolz
Tony Dean:
    47269: 02/09/21: Spartan II JTAG reconfiguration bug - workaround
    47355: 02/09/24: Re: Spartan II JTAG reconfiguration bug - workaround
    69668: 04/05/17: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
    69700: 04/05/18: Re: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
    69712: 04/05/18: Re: DLL - Change in input frequency (CLKIN)
    69759: 04/05/19: Re: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
Tony Disanto:
    4162: 96/09/20: Re: FPGAs design tools for PC
    4227: 96/10/02: Re: Has anyone changed from ViewLogic to Foundation [Q]
Tony Goodloe:
    2466: 95/12/08: Re: Xilinx vs Altera with Verilog/VHDL
    2605: 96/01/10: Re: Career value: VHDL or Verilog?
Tony Griffiths:
    4696: 96/12/02: Re: Addressbility.
Tony Hirst:
    3648: 96/07/08: online w/s - evolutionary electronics
    3740: 96/07/23: CFP: Evolutionary Electronics (resend)
    3868: 96/08/12: Evolutionary Electronics W/S Papers
    4368: 96/10/21: Evolvable hardware/evolutionary elecronics
Tony Hurson:
    14421: 99/01/29: Re: Hold Time Violation
Tony K:
    74073: 04/10/03: Xilinx Virtex II and EMAC
    74085: 04/10/03: Xilinx FPGA EMAC Drivers
    74752: 04/10/18: Xilinx Virtex II MAC & PHY. ( HELP)
Tony Kirke:
    15672: 99/04/07: Re: viterbi/trellis decoder
    15674: 99/04/07: Re: viterbi/trellis decoder
    15673: 99/04/07: Best FPGA for High Speed DSP Logic?
    15675: 99/04/07: Re: viterbi/trellis decoder
    15761: 99/04/12: Re: Best FPGA for High Speed DSP Logic?
    30688: 01/04/23: Re: CIC interpolate by 3 & filter
    35280: 01/09/27: System DSP Generator on Xilinx
    35795: 01/10/17: SDRAM Controller for Xilinx Virtex
Tony Laundrie:
    16215: 99/05/10: Re: One Sheep Farmer's Impressions of SNUG'99
Tony M:
    47858: 02/10/06: Xilinx WebPack ISE 5.1.01i XC9500 Implement problems
    47932: 02/10/08: Re: Xilinx WebPack ISE 5.1.01i XC9500 Implement problems
    47977: 02/10/09: Re: Booting a FPGA via USB
    48858: 02/10/25: What speed grade do I have?
    48877: 02/10/25: Re: What speed grade do I have?
    48903: 02/10/26: Re: What speed grade do I have?
    49728: 02/11/20: Re: Free FPGA Development Board
    51173: 03/01/05: Re: reconfiguration times
    51175: 03/01/05: Re: reconfiguration times
    51178: 03/01/05: Re: reconfiguration times
Tony McKay:
    54033: 03/03/31: Re: DSP-FPGA interface
Tony Nelson:
    37290: 01/12/06: Synplify to Actel clkbuf problems
Tony Proudfoot:
    31003: 01/05/09: Altera 20K200EFC484 and ChannelLink DS90CR483
    34749: 01/09/06: strange behaviour of LPM_FIFO_DC in altera 10k130e
    34864: 01/09/12: Re: Missing bits Part 2!
Tony San:
    36047: 01/10/26: Re: qpsk clock recovery
    36048: 01/10/26: Re: fir filter
    36052: 01/10/26: Re: Interpolating in QPSK with f_IF = f_clk/4
Tony Stansfield TEMP:
    1515: 95/07/06: Job Advert: Hw/Sw Prototyping (Bristol, UK)
Tony T:
    115398: 07/02/09: Re: Modelsim SE 6.2c trying to use Xilinx ISE 9.1i simulation libraries... not working.
    115431: 07/02/10: Re: Modelsim SE 6.2c trying to use Xilinx ISE 9.1i simulation libraries... not working.
Tony Thai:
    115321: 07/02/07: Modelsim SE 6.2c trying to use Xilinx ISE 9.1i simulation libraries... not working.
Tony Williams:
    116516: 07/03/12: Re: Heritage Data books!
<tony.nospam@nospam.tonyRobinson.com>:
    85853: 05/06/17: Re: Idea exploration - Image stabilization by means of software.
tony.p.lee@gmail.com:
    76930: 04/12/15: Re: pausing execution on ppc405
    86917: 05/07/08: Rocket IO failure after power cycle.
    87224: 05/07/19: Xilinx sysace + xmd -jprog options.
    87319: 05/07/21: Re: Xilinx sysace + xmd -jprog options.
    91885: 05/11/15: Re: downloading with XMD ?
    91955: 05/11/17: FPGA CAM/TCAM
    94697: 06/01/16: Re: best evm for virtex-4 and linux
    94725: 06/01/16: Re: best evm for virtex-4 and linux
    96275: 06/02/01: Strange problem with sysace + linux + Ace on SanDisk.
    96348: 06/02/02: Re: xilinx linux source?
    96358: 06/02/02: Re: xilinx linux source?
<tony.p.lee@gmail.com>:
    86968: 05/07/11: Any Scope/LogicAnalyzer that can decode 8b/10b signals in the Rocket IO?
tony.uniquify@gmail.com:
    115305: 07/02/06: Question about programming a FPGA using Modelsim Designer instead of ISE?? can it be done?
    115319: 07/02/07: Re: Question about programming a FPGA using Modelsim Designer instead of ISE?? can it be done?
Tony30:
    89169: 05/09/07: used boards? cache design? DDR2 controller?
    89499: 05/09/16: re:SDRAM HOW?
<tonycornock@my-deja.com>:
    22961: 00/06/06: Re: VirtexE prototype board
TonyF:
    79393: 05/02/18: EDK, XST & inouts
    79498: 05/02/20: Re: Antti Lukats: all my past live projects to be published...
    79504: 05/02/20: Re: Antti Lukats: all my past live projects to be published...
    79505: 05/02/20: Re: Antti Lukats: all my past live projects to be published...
    79512: 05/02/20: Re: Antti Lukats: all my past live projects to be published...
tonymart:
    13593: 98/12/10: FPGA work at 3com
tonyphan:
    81695: 05/03/30: C compiler for Picoblaze - FPGA
    81696: 05/03/30: C compiler for Picoblaze - FPGA
TonyS2:
    34889: 01/09/13: FS Data I/O 2900 Prog Fixture
    35124: 01/09/22: FS DATA I/O 2900 Proramming Fixture
    35839: 01/10/19: FS Data I/O 2900 Prog Fixture
    38383: 02/01/13: FS xilinx 963//Data I/O 2900 Programmers
TonyTSE99:
    120082: 07/06/01: Re: FIR ON FPGA
tonyz:
    34321: 01/08/20: Set up!
Tool:
    119966: 07/05/30: Help: Best use of DCM in Spartan-3A?
    120015: 07/05/31: Re: Best use of DCM in Spartan-3A?
    120021: 07/05/31: Re: Best use of DCM in Spartan-3A?
Toomas Plaks:
    14989: 99/03/02: CFP: Engineering of Reconfigurable Hardware/Software Objects
    15162: 99/03/10: CFP: Engineering of Reconfigurable Hardware/Software Objects
toomuch:
    64343: 03/12/29: A difference between VHDL sources working
toon:
    90847: 05/10/22: write on a DG834GT modem
Topi Maurola:
    35788: 01/10/17: Re: Digital mixers,complex multipliers
Topi Rinkinen:
    124317: 07/09/18: Re: Symbolic names for pll derived clocks in SDC file? (quartus)
Topjob:
    3592: 96/07/02: Advanced Network Products, Top UK Co., to c55k, Southern England - ECM
    3652: 96/07/09: ASIC/VHDL, Graphics Chips Development, to 35k, Cambridge - ECM
    3653: 96/07/09: Advanced Network Products, Top UK Co., to c55k, Southern England - ECM
    3873: 96/08/13: FPGA's/C++/OWL, Data Acquisition Systems, to 30k, Northants, UK - ECM
Topo Gigio:
    40775: 02/03/15: Re: the server to access to this newgroup
<topweaver@hotmail.com>:
    102003: 06/05/09: TME Free Verilog/VHDL framework generation tool
    106631: 06/08/16: Re: Alternative for Mentor''s HDL Designer
    113026: 06/12/05: Free Anydivider, Divide clock by any number
    113106: 06/12/06: Re: Free Anydivider, Divide clock by any number
    113177: 06/12/07: Re: Free Anydivider, Divide clock by any number
    113178: 06/12/07: Re: Free Anydivider, Divide clock by any number
    113331: 06/12/11: Re: Free Anydivider, Divide clock by any number
    113618: 06/12/18: Re: Free Anydivider, Divide clock by any number
    113850: 06/12/25: Judge complex degree by state numbers?
    114390: 07/01/14: Re: Judge complex degree by state numbers?
    114421: 07/01/15: Re: Judge complex degree by state numbers?
    114524: 07/01/18: Re: Generation of Divided-by-3 clock
Torben AEgidius Mogensen:
    1996: 95/09/29: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
    2010: 95/10/02: Re: REPOST: Design Contest Write-up (
    10500: 98/05/25: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
    28293: 01/01/05: Re: Nondeterministic FSMs in hardware?
Torbjoern Bakke:
    1075: 95/04/25: Re: Bugs in Xilinx Prog.Logic Databook -- how to report?
    3062: 96/03/25: Re: What bus is a Xilinx XC1736DP SPROM?
    3417: 96/05/28: Re: WEIRD NOISE PROBLEM WITH XILINX XC3064 - can anyone help?
Torbjörn Stabo:
    28321: 01/01/06: Timing loops
    43958: 02/06/07: Re: Quick newbie question...
Tore H. Larsen:
    5932: 97/03/27: Any FPGA with 6809 core?
Tore H.Larsen:
    2201: 95/10/31: Re: Where to find more info on PCI
Tore Hansteen:
    75206: 04/10/29: Re: Using Sync Reset as Async Reset
Torfinn Ingolfsen:
    142058: 09/07/23: FPGA development tools for FreeBSD?
    142080: 09/07/24: Re: FPGA development tools for FreeBSD?
    142092: 09/07/24: Re: FPGA development tools for FreeBSD?
    142102: 09/07/24: Re: FPGA development tools for FreeBSD?
    142103: 09/07/24: Re: FPGA development tools for FreeBSD?
    142114: 09/07/25: Re: FPGA development tools for FreeBSD?
    142655: 09/08/24: Re: Yet Another Graphics Controller
    142792: 09/09/01: Re: program spartan3 under linux
    143615: 09/10/18: FPGA programming - Linux
    143624: 09/10/19: Re: FPGA programming - Linux
    143949: 09/11/04: Re: Cyclone IV announced
    143971: 09/11/05: Re: Cyclone IV announced
    143980: 09/11/05: Re: Cyclone IV announced
    151666: 11/05/03: Re: Win an Altera DE0-Nano (Cyclone IV Dev Kit)!
    154982: 13/03/14: Re: The Raspberry Pi JTAG programmer
    156572: 14/05/03: Re: Free alternatives to Xilinx iMPACT?
Tori:
    92355: 05/11/28: HDL Chip Design
Torquemada:
    55397: 03/05/06: Re: I want a 800 k gates FPGA in 40 pin DIL
    55406: 03/05/07: Re: I want a 800 k gates FPGA in 40 pin DIL
    55430: 03/05/07: Re: I want a 800 k gates FPGA in 40 pin DIL
    55454: 03/05/08: Re: I want a 800 k gates FPGA in 40 pin DIL
Torsten Alt:
    77379: 05/01/05: Register names in Quartus Signal Tap Node finder
    108022: 06/09/04: Clock Domain Crossing in Virtex4
    108035: 06/09/04: Re: Qestion about the ability of synthesis
    108197: 06/09/06: Re: Qestion about the ability of synthesis
Torsten Landschoff:
    115988: 07/02/27: Re: Xilinx Platform cable USB and impact on linux without windrvr
    115989: 07/02/27: High throughput TCP/IP on Xilinx FPGA
    116028: 07/02/28: Re: Xilinx platform cable USB API?
    116810: 07/03/19: IOSTANDARD default value in Xilinx UCF-Files?
    116825: 07/03/19: Re: IOSTANDARD default value in Xilinx UCF-Files?
    116883: 07/03/20: Automatically adding pcore from XBD (Xilinx Board Definition) file?
    117514: 07/04/03: Re: Where is Open Source for FPGA development?
    117532: 07/04/03: Re: RFC: Enhancing VHDL for OO, Randomization, Functional Coverage
    117533: 07/04/03: Re: RFC: Enhancing VHDL for OO, Randomization, Functional Coverage
    122051: 07/07/18: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    122752: 07/08/06: Re: xps error never seen before: google reveals nothing; help!
    123015: 07/08/14: Virtex4+PPC+ext. RAM: Problems generating ACE files (solved!?)
    123016: 07/08/14: Re: TEMAC Performance Issues with Virtex 4FX
    123048: 07/08/15: Re: System ACE failure on ML405
    130759: 08/04/01: Simple (?) timing constraint for output pins
    130763: 08/04/01: Re: Simple (?) timing constraint for output pins
    130770: 08/04/01: Re: Simple (?) timing constraint for output pins
    130803: 08/04/02: Re: Simple (?) timing constraint for output pins
    130804: 08/04/02: Re: Simple (?) timing constraint for output pins
    130808: 08/04/02: Re: "Number of BSCANs: 2 out of 1 200%"
    130832: 08/04/03: Re: async clk input, clock glitches
Torsten Lauter:
    66582: 04/02/23: Free PCI-bridge in VHDL for Spartan-IIE
    66623: 04/02/24: Re: Free PCI-bridge in VHDL for Spartan-IIE
    66685: 04/02/25: Re: Using 3.3V compliant FPGA for 5V PCI
    66743: 04/02/26: Re: Free PCI-bridge in VHDL for Spartan-IIE
tortiosedundee@yahoo.com:
    77151: 04/12/25: sdram core in EDK
Toshihiro:
    50891: 02/12/22: I didn't understand altera's max+plus2 software to setting up.
    50927: 02/12/24: Re: I didn't understand altera's max+plus2 software to setting up.
    50929: 02/12/24: Re: I didn't understand altera's max+plus2 software to setting up.
Total Metrics Editor:
    11410: 98/08/11: software measurement for realtime systems
Totally_Lost:
    91762: 05/11/11: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
    91879: 05/11/15: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
    91910: 05/11/16: Re: complexity of arithmetic
    92061: 05/11/21: Re: Xilinx routing details
    93803: 05/12/30: open source xnf to edif script
    93804: 05/12/30: Fitting circuits to fpga LUTs
    93806: 05/12/30: Low cost PCI FPGA cards for reconfigurable computing
    93821: 05/12/31: Re: Brute Force Examination of a PLD
    93966: 06/01/04: Re: RTL for Z8000 series CPU?
    93969: 06/01/04: Re: RTL for Z8000 series CPU?
    106569: 06/08/15: Re: Maximum Current Draw of FPGA
    107023: 06/08/23: Re: fastest FPGA
    107143: 06/08/24: Re: fastest FPGA
    107146: 06/08/24: Re: fastest FPGA
    107147: 06/08/24: Re: fastest FPGA
    107148: 06/08/24: Re: fastest FPGA
    107149: 06/08/24: Re: fastest FPGA
    107156: 06/08/24: Re: fastest FPGA
    107159: 06/08/24: Re: fastest FPGA
    107163: 06/08/24: Re: fastest FPGA
    120164: 07/06/02: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
    120351: 07/06/05: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
    120361: 07/06/05: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
    120369: 07/06/05: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
    120507: 07/06/08: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
    120525: 07/06/08: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
    120799: 07/06/17: Re: anyone know a FPGA designer?
    120903: 07/06/19: Re: Graduate/Junior FPGA Designer concerns
    120906: 07/06/19: Re: Interesting problems about high performance computing
    121029: 07/06/22: Re: Interesting problems about high performance computing
    121300: 07/07/01: Re: How to choose FPGA for a huge computation?
    121332: 07/07/02: Re: How to choose FPGA for a huge computation?
    121339: 07/07/02: Re: How to choose FPGA for a huge computation?
    121387: 07/07/03: Re: How to choose FPGA for a huge computation?
    121429: 07/07/03: Re: How to choose FPGA for a huge computation?
    121578: 07/07/08: Re: How to choose FPGA for a huge computation?
    121639: 07/07/10: Re: How to choose FPGA for a huge computation?
    121694: 07/07/11: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121702: 07/07/11: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121705: 07/07/11: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121709: 07/07/11: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121710: 07/07/11: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121711: 07/07/11: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121712: 07/07/11: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121782: 07/07/12: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121848: 07/07/13: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121943: 07/07/15: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121965: 07/07/16: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121966: 07/07/16: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121976: 07/07/16: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121977: 07/07/16: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121978: 07/07/16: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
    121979: 07/07/16: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
    121980: 07/07/16: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
    122608: 07/08/01: Re: completely open source fpga toolchain
    129856: 08/03/07: Re: Anyone to open "FPGA museum" ? Here is first item :)
    135355: 08/09/27: Looking for Insight S2-PCI w/XC2S150 board documentation/manual
    135356: 08/09/27: Re: Looking for Insight S2-PCI w/XC2S150 board documentation/manual
totallyadmin:
    73882: 04/09/30: FPGA vs ASIC area
tote:
    53802: 03/03/24: CLKDLL synthesized with synplify pro
    53834: 03/03/25: Re: CLKDLL synthesized with synplify pro
    53952: 03/03/28: Re: CLKDLL synthesized with synplify pro
    56598: 03/06/10: ucf file is not used in XILINX project navigator
toto:
    85811: 05/06/16: cmosexod
<totodor@yahoo.com>:
    12535: 98/10/15: Test Tal
totohaha:
    146906: 10/04/01: help with ISE+modelsim XEIII
<Totti10@hotmail.com>:
    109394: 06/09/26: QuartusII: how to find out all the instances of a VHDL module in a design?
<tovijayakumar@yahoo.com>:
    78779: 05/02/07: Max. Operating Frequency - Timing report
Tow, Shane [WWP:1X10:EXCH]:
    20049: 00/01/25: Re: Xilinx Foundation: VHDL to symbol
tpi:
    83158: 05/04/25: Re: VHDL Analysis Tool (vhdlarch 0.1.0)
tpsooraj:
    140423: 09/05/13: How to improve maximum operating frequency of a design using DSP 48E?
tpvn2891:
    141858: 09/07/14: How to initialize a Rom with a list of coefficients
    141865: 09/07/14: Re: How to initialize a Rom with a list of coefficients
    141892: 09/07/15: Re: How to initialize a Rom with a list of coefficients
trackmanatISU@gmail.com:
    117524: 07/04/03: QUIP write_verilog.c
Tracy:
    65975: 04/02/10: Array Divider
Tracy Briscoe:
    34556: 01/08/30: Ethernet CRC
    34584: 01/08/30: Re: Ethernet CRC
trag:
    152291: 11/08/03: Re: What is the advantage of source-syncronization (in SDRAMs)?
Trainee:
    102234: 06/05/12: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
<trainingcity@gmail.com>:
    136040: 08/10/28: Re: VHDL Training Course
tramalo:
    154875: 13/01/25: JTAG, CONF_DONE failed to go high in device 1.
    154876: 13/01/25: Re: JTAG, CONF_DONE failed to go high in device 1.
    154877: 13/01/25: Re: JTAG, CONF_DONE failed to go high in device 1.
Trampus Richmond:
    43093: 02/05/13: New Nios Developer Community Started
Tran Cong So:
    32628: 01/07/03: XC4010 ! help please
Trangdaithi Hoang:
    436: 94/11/16: Re: Sources for FGPA's and "exotic" PLDs?
transformer:
    50305: 02/12/08: vlsi implementation of multipliers
    50338: 02/12/09: Re: vlsi implementation of multipliers
    50531: 02/12/12: Re: vlsi implementation of multipliers
Traveler:
    43220: 02/05/16: Need Help on FPGA and Spiking Neurons
    43279: 02/05/17: Re: Need Help on FPGA and Spiking Neurons
    43322: 02/05/18: Re: Need Help on FPGA and Spiking Neurons
    43381: 02/05/20: Re: Need Help on FPGA and Spiking Neurons
    43441: 02/05/21: Re: Need Help on FPGA and Spiking Neurons
Travis Ayres:
    154731: 12/12/31: Re: picoblaze help
    154912: 13/02/12: Aldec Active-HDL - No Default Binding Errors
Travis Terry:
    5224: 97/01/31: cisco 4500 problem
<trayres@gmail.com>:
    154711: 12/12/24: pBlazSIM
Trent R.:
    65324: 04/01/24: VHDL newbie
Trent Worthington:
    21117: 00/03/07: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
    22703: 00/05/18: tag programming software
Trevor Coolidge:
    112223: 06/11/17: Re: Why 64-bit PLB?
    112225: 06/11/17: Re: JTAG connection for chipscope
    112226: 06/11/17: Re: FPGA's for Ethernet?
    112227: 06/11/17: Re: How stable is the internal clock of a Xilinx CPLD?
    112228: 06/11/18: Re: Have you experience to program the APA series using FlashPro Lite?
    112229: 06/11/18: Re: Xilinx Virtex-4 Clock Multiplexer Inputs
    112230: 06/11/18: Re: PCB Design Houses
    112231: 06/11/18: IDELAY Calibration - Virtex 4
    112232: 06/11/18: Re: Influence of temperature and manufacturing to propagation delay
    112243: 06/11/18: Re: IDELAY Calibration - Virtex 4
    112244: 06/11/18: Re: Input setup time & Output valid delay
    112245: 06/11/18: Re: pulse jitter due to clock
    112287: 06/11/19: Re: board - T562.jpg
Trevor Hall:
    197: 94/09/19: Re: Lattice ISP software: really good
    220: 94/09/27: Re: really good
    232: 94/09/29: Re: Lattice ISP software: really good
    394: 94/11/05: Re: Xilinx chip partitioning
    683: 95/02/06: Re: Question on 22v10 fitting in Warp2
    722: 95/02/17: Re: Real-time fractal gen in h/w
    733: 95/02/20: Re: Real-time fractal gen in h/w
    936: 95/03/31: Re: Excuse me while I vent about Data I/O & Abel...
    957: 95/04/04: Re: Excuse me while I vent about Data I/O & Abel...
    993: 95/04/10: Re: Excuse me while I vent about Data I/O & Abel...
    994: 95/04/10: Re: Excuse me while I vent about Data I/O & Abel...
    995: 95/04/10: Re: AT&T Statement ref Neocad
    1022: 95/04/18: Re: MINC's PLDesigner-XL Series
    1093: 95/04/27: Re: Altera new FLEX 10000 - a worlds first
    1127: 95/05/03: Re: Lattice EPLDs
    1137: 95/05/04: Re: Lattice EPLDs
    1139: 95/05/04: Re: Lattice EPLDs
    1286: 95/05/27: Re: CUPL manual/info
    1357: 95/06/06: Re: LowCost CPLD/FPGA tools ???
    1404: 95/06/16: Re: Need Help with Altera FLEX programing.
    1593: 95/07/24: Re: PREP data
    1971: 95/09/27: Re: PREP benchmarks
    2076: 95/10/11: Re: Help - Searching an PLD/FPGA Selection Software
    2254: 95/11/10: Re: BP Micro and CUPL -- a good start?
    2318: 95/11/20: Re: BP Micro and CUPL -- a good start?
    2665: 96/01/22: Re: PLD JDEC Files
    2770: 96/02/05: Re: help ! pci-interface
    3061: 96/03/25: Re: Troubles with Altera Bitblaster
    3591: 96/07/02: Re: XUMA Digest #9
    3781: 96/07/31: Re: Clearing security fuse on Lattice ispLSI2032?
Trevor Landon:
    17165: 99/07/06: Re: Floating point on fpga, Counters?
    17177: 99/07/07: Re: Floating point on fpga, Counters?
Triax:
    57473: 03/07/01: Celoxica DK1 to Xilinx Spartan II
    58507: 03/07/25: Xilinx Design Manager - Connecting 2 Latches
trican:
    74624: 04/10/15: ISE 6.2 EDF mapping problem
Tricia Dolkas, aka Technoyenta:
    29920: 01/03/16: Hardware Design Engineer Needed in Santa Clara, CA
Tricky:
    123450: 07/08/28: Re: Null statement in VHDL
    124263: 07/09/17: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
    126663: 07/11/29: Re: ISE WARNING Xst:647
    126722: 07/11/30: Re: ISE WARNING Xst:647
    127636: 08/01/04: Re: simulation problems
    128506: 08/01/29: Re: Random Number Generation in VHDL
    128871: 08/02/08: Re: function/process to generate sine and cosine wave
    129587: 08/02/28: Re: DSP newbie
    129628: 08/02/29: Re: real to signed
    129629: 08/02/29: Re: real to signed
    129682: 08/03/03: Re: real to signed
    129726: 08/03/04: Re: verifying UNIFORM using matlab
    129740: 08/03/04: Re: verifying UNIFORM using matlab
    129742: 08/03/04: Re: verifying UNIFORM using matlab
    130264: 08/03/19: Re: Optimizing an inferred counter
    131170: 08/04/14: Re: Task in verilog
    136653: 08/11/28: EPLD - FPGA - Is there a difference
    140279: 09/05/07: Re: Seeding random number generator
    140280: 09/05/07: Re: Seeding random number generator
    146219: 10/03/09: Re: Why doesn't this situation generate a latch?
    146576: 10/03/23: Re: Writing Hex values to file in VHDL?
    147332: 10/04/23: Re: confusion with ADC/DAC interface implementation
    149561: 10/11/05: Re: combinatorial process not simulating correctly
    151025: 11/03/01: Re: Count bits in VHDL, with loop and unrolled loop produces
trigo10:
    148872: 10/09/05: XC4028's to offer
tripledirrble:
    75447: 04/11/05: Jtag problem for Virtex II pro (XC2VP20-6FF896C).
    75536: 04/11/08: Re: Jtag problem for Virtex II pro (XC2VP20-6FF896C).
Tristan Hunt:
trlcoms(news):
    19674: 00/01/07: orca3t125 clock problems
<4tron@syntiac.com>:
    71066: 04/07/07: Synthesis failure Xilinx WebPack XST
    71151: 04/07/09: Re: Synthesis failure Xilinx WebPack XST
Trond Egil Gran:
    83021: 05/04/21: Xilinx Impact in Linux 2.6.x
    83065: 05/04/22: Re: Xilinx Impact in Linux 2.6.x
    83068: 05/04/22: Re: Xilinx Impact in Linux 2.6.x
    83085: 05/04/23: Re: Xilinx Impact in Linux 2.6.x
<tronsmith@my-deja.com>:
    17815: 99/09/07: Re: Flex8000 trouble
    19109: 99/11/29: Re: FPGA vs DSP vs PENTIUM MMX
    25502: 00/09/12: Re: Clock skew in XILINX CPLD
<tronsmith@my-dejanews.com>:
    11361: 98/08/06: Re: [Q] motor control onto an FPGA
    11430: 98/08/12: Fixed Division by 3, 5, 7, 9, 15, 17 ...
    13152: 98/11/17: Re: Big-Endian vs Little-Endian
    13962: 99/01/05: Re: 22V10 Metastability - help please
    14257: 99/01/22: Re: hdl vs. schematics - was <snip>
    15777: 99/04/13: Re: Using the temperature diode on the virtex...
Troy Fuqua:
    435: 94/11/16: Re: Sources for FGPA's and "exotic" PLDs?
Troy Garrett:
    6418: 97/05/22: Re: Problem in Leonardo synthesis targetting Altera
Troy R. Pesola:
    2011: 95/10/02: Re: cheap (free) fpga design software
Troy Schultz:
    44270: 02/06/15: Re: Xilinx ISE BaseX... What is it?
    44285: 02/06/16: Re: Xilinx ISE BaseX... What is it?
    44427: 02/06/19: Re: ATMEL CPLD
    44432: 02/06/19: Re: ATMEL CPLD
    45211: 02/07/16: Re: Webpack under Linux ?
    45525: 02/07/25: Re: Is the WebPack Constraints Editor evil?
    46871: 02/09/10: Re: Xilinx Parallell Cable IV and Wine
    46874: 02/09/10: Re: atmel CPLD documentation
    46905: 02/09/11: Re: atmel CPLD documentation
<troy.scott@latticesemi.com>:
    89955: 05/09/30: Re: Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments
    89958: 05/09/30: Re: Xilinx and Lattice tools on one machine?
    90675: 05/10/18: Re: CPLD design software under WINE?
    93930: 06/01/03: Re: Timing problem in ModelSim, Post-Route Simulation.
    93928: 06/01/03: Re: Lattice XP simple simulator
    94117: 06/01/05: Re: Schematic Entry, Xilinx or Altera?
    96305: 06/02/01: Lattice Semiconductor, Lattice Forums Go Live
    129468: 08/02/25: Re: Using Lattice ispLEVER with VHDL libraries
truhlik_fredy:
    147379: 10/04/24: Helping tools
    147382: 10/04/25: Re: Helping tools
<truongt1024@gmail.com>:
    126941: 07/12/06: student requiring assistance :)
    127237: 07/12/14: Re: student requiring assistance :)
<Truth_In_Media_Please@osiqrav.org.tr>:
<tryggvem@my-deja.com>:
    17134: 99/07/01: Re: FGPA Servo Motor Controller
    19192: 99/12/04: Re: CAN testing - Any CANbus cores out there?
<tryggvem@my-dejanews.com>:
    12932: 98/11/05: Re: A suggestion for Xilinx
    14888: 99/02/23: Re: Problem with xilinx M1
    14889: 99/02/23: Re: High Fanout Signals
    15085: 99/03/05: Re: I/O standards revisited
trythis:
    63443: 03/11/21: Re: 400 Mb/s ADC
<trythis@money.com>:
    4678: 96/11/28: Please Help!!!
<tryyourbestok@hotmail.com>:
    114200: 07/01/07: Basic questions about digital phase locked loop
TS Kutty:
    20505: 00/02/12: Problem in Wildforce synthesis.
    20517: 00/02/13: Re: Problem in Wildforce synthesis.
    20516: 00/02/13: Re: Problem in Wildforce synthesis.
    20537: 00/02/14: Wildforce Board
<ts1@its.com.sg>:
    30696: 01/04/24: * mail server not work on NT through cable modem
tsan:
    120065: 07/05/31: Re: FIR Filter ON FPGA
    120066: 07/05/31: Re: FIR Filter ON FPGA
    120067: 07/05/31: Re: Take verilog code from Xilinx Core generator
    120069: 07/06/01: Re: Help!! FIR Polyphase second - order interpolator
tsao:
    51555: 03/01/16: 200K gates FPGA for GPU
    51557: 03/01/16: Re: 200K gates FPGA for GPU
    51565: 03/01/17: Re: 200K gates FPGA for GPU
    51900: 03/01/25: DK1 grunt
<tsbdeamt@yahoo.com>:
    12711: 98/10/24: Privacy & Anonymity on the Internet
tsemer:
    111563: 06/11/06: choise of fpga platform
    111636: 06/11/07: Re: choise of fpga platform
    111693: 06/11/08: Field Programmable Object Array
TSIuser:
    132028: 08/05/10: Xilinx ML507 evaluation board (V5FXT70)?
    132887: 08/06/09: Re: Aldec Active-HDL and Xilinx/Altera FPGA-vendor library support
tsj:
    55514: 03/05/11: where to buy 1 virtex-e fg680
<tsjusl@zwallet.com>:
TSMGrizzly:
    143840: 09/10/29: Best way to model a large external ROM in a simulation? (XST
    143842: 09/10/29: Re: save data from adc in text file
    143846: 09/10/29: Re: Best way to model a large external ROM in a simulation? (XST
    143850: 09/10/29: Re: Best way to model a large external ROM in a simulation? (XST
    143854: 09/10/29: Simple state machine output question
    143875: 09/10/30: Re: Simple state machine output question
    145258: 10/02/03: Board layout for FPGA
    145262: 10/02/04: Re: Board layout for FPGA
    145270: 10/02/04: Re: Board layout for FPGA
    145290: 10/02/04: Re: Board layout for FPGA
    145291: 10/02/04: Re: Board layout for FPGA
    145297: 10/02/04: Re: Board layout for FPGA
    145396: 10/02/08: Re: Board layout for FPGA
Tsoi Kuen Hung:
    42206: 02/04/18: [Xilinx TRACE timing] two phase clock
    42284: 02/04/19: Re: [Xilinx TRACE timing] two phase clock
    42834: 02/05/04: Re: Hard macro with Xilinx
    42894: 02/05/06: Re: Hard macro with Xilinx
Tsvika Hirst:
    55757: 03/05/19: a (PC) workstation for FPGA development
    55766: 03/05/19: Re: a (PC) workstation for FPGA development
TswvXyooj:
    5578: 97/02/25: Rising_Edge/Falling_Edge Functions
<tswvxyooj@hotmail.com>:
    4756: 96/12/11: Multiply-Accumulate in VHDL
TT:
    105601: 06/07/26: Hold violation in Virtex 4
    105623: 06/07/27: Re: Hold violation in Virtex 4
<tthurnherr@gmail.com>:
    108143: 06/09/05: exporting an image with quartus 2 web edition
TTigger:
    89445: 05/09/15: Re: Address Decoder
TTK Ciar:
    12764: 98/10/28: Re: New free FPGA CPU
TTman:
    152474: 11/08/28: Re: cheating Arria FPGA i/o count
    152763: 11/10/19: Re: Altera FPGA weirdness
TTX:
    137870: 09/02/01: Spartan 3A Starter Kit Comm Problem
tu:
    153480: 12/03/08: CPU Design in Xilinx Spartan 3E
    153635: 12/04/08: Re: CPU Design in Xilinx Spartan 3E
    153636: 12/04/08: Re: CPU Design in Xilinx Spartan 3E
    153637: 12/04/08: Re: What's a good book on FPGA CPU design?
    153670: 12/04/12: Re: CPU Design in Xilinx Spartan 3E
TudaPellini:
    146290: 10/03/10: Xilinx ISE Webpack Schematics
TukryopKim:
    4682: 96/11/29: Addressbility.
tullio:
    107570: 06/08/30: behavioral vs post-P&R simulation mismatch
    107595: 06/08/30: Re: behavioral vs post-P&R simulation mismatch
    107695: 06/08/31: Re: behavioral vs post-P&R simulation mismatch
    108940: 06/09/19: simulation mismatch (xilinx)
    108955: 06/09/19: Re: FPGA : Open core FFT
    109361: 06/09/25: Re: simulation mismatch (xilinx)
    111491: 06/11/03: Re: maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
    112315: 06/11/20: Spartan3E price update ?
    112701: 06/11/27: Re: I2C Controller
    113946: 06/12/29: Re: SPI slave problem
    118038: 07/04/16: Re: Xilinx ISE 9.1
    120706: 07/06/14: Re: Optical RocketIO
    129038: 08/02/13: Xilinx GTP_DUAL: wizard or code ?
    134838: 08/09/03: XST bug on illigal states of a FSM ?
    134866: 08/09/04: Re: XST bug on illigal states of a FSM ?
    148203: 10/06/28: help with OVL on Actel tool
    154472: 12/11/08: Re: Lowest Power Design in an FPGA
tullio grassi:
    139629: 09/04/07: Re: Timing constraints problem
Tullio Grassi:
    11374: 98/08/07: Re: Negative pulse form Altera FPGA's ?
    36301: 01/11/05: FPGA marketplace ?
    41459: 02/03/28: strange RAM timing problem (VirtexE)
    42297: 02/04/19: Re: Availability of Virtex II pro
    42298: 02/04/19: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
    42954: 02/05/08: bug in XST ?
    43145: 02/05/14: Re: bug in XST ?
    43146: 02/05/14: verilof parameter and XST
    43529: 02/05/22: Re: timing violations in fpgas
    48392: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
    49245: 02/11/06: synthesis tools
    49259: 02/11/06: Re: glue logic device
    49577: 02/11/15: Re: Costing FPGA design projects
    51270: 03/01/09: Re: XILINX ISE + ACTIVE-HDL design flow, HELP PLEASE!!!
    51312: 03/01/10: Re: XILINX ISE + ACTIVE-HDL design flow, HELP PLEASE!!!
    51477: 03/01/14: Re: Virtex, Virtex II and Virtex II Pro
    51659: 03/01/17: Re: Lecroy Research Systems - what happened?
    52108: 03/01/31: Re: Xilinx ise 51. how to do a nice simple simulation
    52175: 03/02/03: Re: Group Multiple tables
    53465: 03/03/13: Re: Using divided clock
    55300: 03/05/02: Virtex2 BUFGMUX problem ?
    59419: 03/08/18: Re: VHDL for FPGA VME Slave
    60555: 03/09/16: Re: IBUF, IBUFG, OBUF
    60582: 03/09/16: Re: Xilinx ISE 6.1i
    60816: 03/09/23: Re: Using LUTs for array of coefficients
    62155: 03/10/21: Re: Italy is out of FPGA world?
    62192: 03/10/22: Re: Verilog Encounted Errors
    62588: 03/11/02: Power-On-Reset from a xilinx
    63594: 03/11/26: Re: 5V I/O with 1.8V Core
    63693: 03/11/30: jitter in Virtex2 DCM
    63756: 03/12/03: Re: jitter in Virtex2 DCM
    63850: 03/12/05: Re: XILINX FPGA: DCM locked Signal
    65348: 04/01/26: Re: Tristate buffer
    76796: 04/12/12: Re: Virtex-II PRO, DDR2 SDRAM, RocketIO
    79043: 05/02/11: xilinx MGT compatibility?
    87399: 05/07/22: parallel optic availability
    87406: 05/07/22: Re: parallel optic availability
    88018: 05/08/05: Xilinx XC4VFX140 Availability ?
    88293: 05/08/15: Re: Delays in verilog
Tung Thanh Le:
    156111: 13/11/27: LCD test on Spartan 3E FPGA
    156113: 13/11/27: Re: LCD test on Spartan 3E FPGA
    156114: 13/11/27: Re: LCD test on Spartan 3E FPGA
    156126: 13/12/05: Re: LCD test on Spartan 3E FPGA
Tungsten-W:
    65762: 04/02/06: How may I restrain the P&R to only a small area...
    65996: 04/02/11: Odd behavior of BUFGMUX in Virtex-2...
    66058: 04/02/12: Re: Partial reconfig flow - Aaaarrrrgggghhhh! I am dead!!!
    66468: 04/02/20: How does ISE6 handle mixed-edge design?
    66483: 04/02/20: Re: How does ISE6 handle mixed-edge design?
    66484: 04/02/20: Re: why ISE par does not tell me all buffer usage?
    66485: 04/02/20: Re: Unix workstation runs ISE 6.1 slower than a PC?
Tuomo Auer:
    41312: 02/03/25: Re: Can't detect Altera MAX7000s using JTAG
    41387: 02/03/27: Re: ByteblasterMV EPM7064S voltage problem
    41388: 02/03/27: Re: ByteblasterMV EPM7064S voltage problem
    41468: 02/03/29: Re: Homebuilt Altera-programmer totally dead...
    41473: 02/03/29: Re: Homebuilt Altera-programmer totally dead...
    41476: 02/03/29: Re: Where to get MAX7000S
    42765: 02/05/02: Re: Xilinx Download Cable III
    43621: 02/05/27: Re: Altera 10K30A240C-1
    44783: 02/07/01: Re: 32KHz oscilator in CPLD
tupadre:
    154848: 13/01/18: Button clock
    154850: 13/01/18: Re: Button clock
    154851: 13/01/18: Re: Button clock
    154866: 13/01/21: Re: Button clock
<turas@takas.lt>:
    11407: 98/08/11: THE CHEAPEST ORCAD SOFTWAREZ!
<turbo.satan@gmail.com>:
    93262: 05/12/16: Looking for QuickLogic DeskFab programmer, new or used
Turboproc:
    19955: 00/01/20: Re: Desperate Xilinx problem SOLVED!
Turgut Abacioglu:
    53513: 03/03/14: Re: JTAG
    53514: 03/03/14: Re: JTAG
    53684: 03/03/19: Re: About automatically programming my FPGA
    53706: 03/03/20: Re: What is the diff between FPGA and CPLD?
    53707: 03/03/20: Re: FPGA programming question.
<turin231@gmail.com>:
    155100: 13/04/15: Catapult C floating point exp() function?
    155104: 13/04/17: Re: Catapult C floating point exp() function?
    155157: 13/05/13: Re: Catapult C floating point exp() function?
    155159: 13/05/13: Re: Modelsim ought to be cheaper
Turj:
    151034: 11/03/01: Slice Usage
<turkey_bird@yahoo.com>:
    132385: 08/05/24: Re: Stratix IV Announced
    132390: 08/05/25: Re: Stratix IV Announced
Turquesa:
    64524: 04/01/06: readback spartan2e
Tushar Dongre:
    103281: 06/05/30: Re: tft and uClinux
tushit:
    66253: 04/02/15: Manual Partitioning to Multiple FPGAs
    68672: 04/04/13: Writing PCI constraints in Altera
    68836: 04/04/19: Re: Writing PCI constraints in Altera
    69041: 04/04/26: Re: Writing PCI constraints in Altera
    69087: 04/04/26: Slack gets worst as I relax timing
    69264: 04/05/03: Re: Writing PCI constraints in Altera
    69607: 04/05/15: Quartus Internal Errors
    134308: 08/08/05: impact error with ISE 10.1
<tusunov@my-deja.com>:
    28400: 01/01/11: Re: Which Group is focusing on IC design
Tuukka Toivonen:
    73282: 04/09/17: FPGA with PCI interface for video processing?
    73574: 04/09/24: Re: FPGA with PCI interface for video processing?
    75324: 04/11/02: Re: "frying" FPGAs
    74475: 04/10/12: Re: direct calculation of the modulus ?
    74623: 04/10/15: Re: Question on Xilinx VirtexPro II FPGA chip... please
    74630: 04/10/15: Re: Question on Xilinx VirtexPro II FPGA chip... please
    77456: 05/01/07: Re: Open source FPGA EDA Tools
    77533: 05/01/10: Re: Starting with xilinix and Linux
    77648: 05/01/13: Re: Starting with xilinix and Linux
    79696: 05/02/23: Re: XST: How to select the architecture for synthesis?
    80151: 05/03/02: Re: FPGA tool benchmarks on Linux systems
    80174: 05/03/02: Re: Xilinx ISE7.1
    80178: 05/03/02: Re: Xilinx ISE7.1
    81355: 05/03/22: Re: Free simulator
    81467: 05/03/24: Re: Xilinx ISE 7.1 - Can this get any worse?
    82184: 05/04/08: Re: Linux VHDL Simulator
tuxfriend:
    101365: 06/04/29: Book Software for XC3190A?
    101379: 06/04/30: Re: Book Software for XC3190A?
    101398: 06/04/30: Re: Book Software for XC3190A?
    101465: 06/05/01: Re: Book Software for XC3190A?
    101467: 06/05/01: Re: Book Software for XC3190A?
    101475: 06/05/01: Re: Book Software for XC3190A?
    101535: 06/05/02: Re: Book Software for XC3190A?
tvar_vlsi:
    84839: 05/05/30: Xilinx ISE 6.1i - Fatal Error
<tvnaidu@yahoo.com>:
    77742: 05/01/15: What is the difference between ASIC and FPGA?.
TWColl:
    1936: 95/09/22: Altera FLEX 10K Seminars: 100,000 gates???
    2226: 95/11/06: X-Blox...The good, bad and ugly
    3044: 96/03/20: Re: Xact6.o too slow
tweed_deluxe:
    107072: 06/08/24: Why No Process Shrink On Prior FPGA Devices ?
    107152: 06/08/24: Re: Why No Process Shrink On Prior FPGA Devices ?
Tweetldee:
    64392: 04/01/01: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
twinsparc:
    11561: 98/08/24: Free VHDL editor
twospruces:
    148468: 10/07/26: temporal logic folding
<twtmail@twt.co.il>:
    1889: 95/09/15: Why does MAX5000 is getting hot?
Tximo:
    14721: 99/02/12: Problems with Xilinx F1.5 & latchs
    14760: 99/02/15: Re: Problems with Xilinx F1.5 & latchs
    16487: 99/05/25: Synthesis problem
    16514: 99/05/26: Re: Synthesis problem Solved. Thanks to all
    16515: 99/05/26: Instantiate Clocks
ty:
    68388: 04/04/02: FPGA input
tyew:
    40012: 02/02/25: Altera FPGA MISC Pipeline
<tyhuhgfkjklj@yahoo.com>:
Tyler:
    110794: 06/10/23: XC2V80005FF1517C
Tyler Reed:
    44146: 02/06/12: Re: 20,000 gates?
    81509: 05/03/26: Middleware for FPGA-based computing
tylx_wu:
    119878: 07/05/28: comp.arch.fpga :How to implement a 128-bit input CRC module in
    120005: 07/05/30: Re: comp.arch.fpga :How to implement a 128-bit input CRC module
typhon62:
    99186: 06/03/21: Re: FATAL_ERROR while creating a test bench waveform (ISE WebPack 8.1.01i)
    99434: 06/03/24: Re: Memory leaks with ISE 8.1
    99605: 06/03/27: Re: Memory leaks with ISE 8.1
    105941: 06/08/03: Re: FPGA LABVIEW programming
    109639: 06/10/02: Re: Migration from Spartan-2E to Spartan-3E
Tyron:
    68411: 04/04/03: FPGA and CPLD boards
    68726: 04/04/15: Bus interface?
Tyrone Kwok:
    72367: 04/08/17: Re: Using SDRAM on Xilinx AFX V2P board
    74329: 04/10/08: Re: Synplify on Fedora C2
Tyrone Thompson:
    14850: 99/02/20: Bus Interface
    16021: 99/04/28: Help with XACT 5.2 - 6
    16074: 99/04/30: Re: Help with XACT 5.2 - 6
    18126: 99/10/01: Producing 60/40 clock in vhdl
    18181: 99/10/05: Re: Producing 60/40 clock in vhdl
    18397: 99/10/22: Re: Xilinx Orientation Question
    20027: 00/01/24: Re: Xilinx vs. other FPGAs manufactrers
    20125: 00/01/27: Re: Has anyone created VHDL code to interface to a 68HC11 SPI port yet?
<tzcpes@thehaunting.com>:
    18438: 99/10/24: FAncY BlOwJoB
tzechien:
    2317: 95/11/20: Re: [q][Reverse Engineering Protection]


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