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On 1 Oct 2005 21:38:31 -0700, altera_smells@hotmail.com wrote: >Xilinx is number one. Might as well start using the dominant number one >company. > Looks like seann stifler is back. What a tragedy. With a new name and a IP address, and old attitude. Philip Freidin =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 90026
Francis St-Pierre wrote: > When I try to use more than one embedded system in ISE, it says: > Only one source of type 'XPS FILE' is allowed in a project. > Why can't I add more than one system.xmp file to ISE? > > I need two embedded systems because the hardware and software in each > one are different. And I can not put the two EDK projects in only one > because my VHDL Top Level in ISE will instantiate the first EDK project > only once and the other several times. I want to create a > multiembedded design. ISE should be able to have several embedded > systems; that is not normal! > > I also tried to add a EDK project system.xmp in a ISE project > created(export to ProjNav) with another EDK project. But it can not work > because the two EDK project have "system" for name as sub-module. I try > to put "system_something" as sub-module name, but EDK always export it > as "system" name. > > How to have multiple EDK projects in ISE? > > > Francis St-Pierre > > École Polytechnique de Montréal > http://www.grm.polymtl.ca/~stpierre/ I have tried to add a new microblaze within the same EDK project, and it seems to work. (EDK 7.1.02i)Article: 90027
Francis wrote: > I have a project EDK system.xmp in ISE. ISE does not initialize the > bitstream even if I do a update bitstream in ISE. I had to import ISE to > EDK and do update bitstream so that it works on my FPGA board. Looks > like EDK does it correctly and not ISE. I also tried to use my project > in ISE with an export to ProjNav with the EDK tool. Same thing I had to > import my ISE project to EDK to initialize it correctly. > > I also tried to put my .elf and .bmm file in ISE. But does not change > anything. I use ISE 7.1.04i and EDK 7.1.02i I found my answer to > initialize my bitstream at: > Exporting a EDK design to Project Navigator > http://groups.google.ca/group/comp.arch.fpga/browse_frm/thread/c9dfcb22ff57862/fc5ff8c6327f16a2?lnk=st&q=export+edk&rnum=12#fc5ff8c6327f16a2 > > > It is important that i use my EDK project in my ISE project and not the > other way around. > > Why does ISE do not initialize the memory of the BRAM or bitstream? > > > Francis St-Pierre > > École Polytechnique de Montréal > http://www.grm.polymtl.ca/~stpierre/ > > > > Key Words: EDK in ISE, ISE with EDK, system.xmp in ISE project, > unintiliazed .bit I have the EDK project within an ISE project. From version 7.1 (I think, but not sure), I have been forced to follow this procedure: 1. Compile new/updated project 2. Tools/Clean Bits (took a while to fin this!) 3. Go to ISE and Uopdate Birtstream with Processor Data And there you are.Article: 90028
If you ignore him then he will go away like a bad smell Simon "Philip Freidin" <philip@fliptronics.com> wrote in message news:t6h1k1hqtaaim9q3vqbb98c5rkutbvs014@4ax.com... > On 1 Oct 2005 21:38:31 -0700, altera_smells@hotmail.com wrote: > >Xilinx is number one. Might as well start using the dominant number one > >company. > > > > Looks like seann stifler is back. What a tragedy. > With a new name and a IP address, and old attitude. > > Philip Freidin > > > =================== > Philip Freidin > philip.freidin@fpga-faq.org > Host for WWW.FPGA-FAQ.ORGArticle: 90029
so what your really saying ...
Is you want to make 64 x 8 x (240:1) mux or 122,880 combinations...
What was suggested isn't that hard to implement.. and it isn't pipelined
either.. pipelining assumes a clock and one level per stage.. so a 4 stage
pipeline creates a 4 clock delay... and there is no clock.
so thats 240x8 + 64x8 + (8x6) pins / signals ...
If you think about what you are asking for.. you would see its a might
rediculas! even assuming you have just the 240 bytes .. thats 1,920 signals
all on its own!
Please look at your design and maybe comeup with something a might more
sensable.
Simon
"vssumesh" <vssumesh_asic@yahoo.com> wrote in message
news:1128316000.075586.204600@g47g2000cwa.googlegroups.com...
> I dont fully understand what you are suggesting. But it seems to me
> that you are advicing a pipelined operation. But that is not possible
> in the design. It is a completely random MUX.
> The task is to take data from a 240 byte register and to arrange that
> into a 64 byte wide data bus (simultanious)(each output byte can take
> data from any of the 240 registers). And the selection bits are direct
> to each mux. That is 240 bit selction lines into each MUX. I tried to
> implement it with the LUT but it gave the same result. I am ready to
> wait for days but the ISE is simply giving up. If i reduce the output
> by 32 it is giving the output.
> >" You can also use the carry chains, or if using virtexII the horizontal
> >or chains with this method to help reduce the size of the logic."
> Please give me little more details on this. I tried to to implement
> normal ANDing and then ORed all the bits.
> Sumesh
P.S.
package mux240_1_pkg is
type byte240_typ is array (0 to 239) of std_logic_vector(7 downto 0);
type byte64_typ is array (0 to 63) of std_logic_vector(7 downto 0);
type int240_typ is array (0 to 63) of integer range 0 to 239;
end mux240_1_pkg;
entity mux240_1_byte is
Port (
din: in byte240_typ;
dout: out byte64_typ;
sel: in int240_typ
);
end mux240_1_byte;
library work;
use work.mux240_1_pkg.all;
architecture rtl of mux240_1_byte is
begin
gen: for i in dout'range generate
dout(i) <= din(sel(i));
end generate;
end rtl;
Article: 90030sk.sulabh@gmail.com wrote: > I am using ISE tool for implementing my design.But i am facing a > problem.In this tool it is written that some modules are supported to > infer rather than inatantiate. My prof says to make design wholly > structural . and using the modules available, just like we do in > shematic. But since for some design elements , instatiating is not > supported, i cant do it.I have to write a module code to infer that > module.but according to prof this should not be the way. I'm not sure what your professor is getting at. Is he implying that you should always instantiate everything, even primitives such as AND gates? If so, then there's little point in using an HDL. I suppose, though, that in a logic design course, it's vital that you learn the basics, so rather than coding a counter as count <= count + 1 mod LENGTH, perhaps your professor is requiring that you learn what goes into creating a counter. That's a separate issue, though. Hopefully your professor is making this clear. It's certainly possible to write structural HDL code that infers various logic elements, from the simple (like AND gates) to the complex (like counters and memory elements). I do it all the time! > Second thing while making these design elements (like counter) with > flip flop and gates (for which instantiation is supported), its min > clock period is large compared to the one which is inferred.Suggest me > what can do here. Here's where inference helps you. The synthesis tool recognizes certain structures and knows about the specifics of the chip architecture and how to map those structures to the chip efficiently. I'll bet that in your case, your flops-and-gates implementation of a counter doesn't take advantage of an FPGA's special carry chain. And hopefully you're not coding a ripple counter! -aArticle: 90031
"Simon Peacock" <simon$actrix.co.nz> schrieb im Newsbeitrag news:433f22f3$1@news2.actrix.gen.nz... > who the F*** designed your web site.... I know putting frames around product > briefs lets you keep your logo.. but that's almost 2/3's of the screen > gone... > > Simon > > translated: fire your web designer :-) > Thanks Simon! no translation required, I agree with you 2000 %, but I have no influence to solve the issue. :( Antti PS its not my website. Its from the company I work for at the moment. (my contract ends 31.12.2005)Article: 90032
Hello Simon, Yes i am trying to implement the 64 nos of 8bit wide (240:1) mux. And there is 240 * 64 = 15360 total selction bits (240 bits to each mux). And 240 * 8 = 1920 data bits to whole block of 64 muxs (same data goes to all MUX). Thus the mux array block will have 17280 input lines and 64 * 8 output lines. Why you are saying that it is not possible. All signals are internally generated from other parametrs (I dont know the internal routing efforts of the FPGA). Please advice. The mux (the code) you suggested is a single 240 to 1 byte mux. But i want 64 copies of that. Is that possible. I know that it is not possible to implement it in asingle design by getting the selction signal from external sources; is it because of this constrain that the ISE stops working. I am able to get output if i reduce any of the parametrs to half (no: out put or no: registers etc).Article: 90033
you can try to delete the project implementation files and retry. I also had this portability error but with a different message but it went off once i deleted the project implementation files. Cheers, Adarsh "Matthew Plante" <maplante@iol.unh.edu> wrote in message news:dhjtlc$80c$1@tabloid.unh.edu... > Has anyone else received this error with ISE 7.1i? I added a peripheral > to my embedded system, and when I re-synthesize it it XST, I get: > > ERROR:Portability:3 - This Xilinx application has run out of memory or has > encountered a memory conflict. Current memory usage is 798040 kb. Memory > problems may require a simple increase in available system memory, or > possibly a fix to the software or a special workaround. To troubleshoot or > remedy the problem, first: Try increasing your system's RAM. > Alternatively, you may try increasing your system's virtual memory or swap > space. If this does not fix the problem, please try the following: Search > the Answers Database at support.xilinx.com to locate information on this > error message. If neither of the above resources produces an available > solution, please use Web Support to open a case with Xilinx technical > Support off of support.xilinx.com. As it is likely that this may be an > unforeseen problem, please be prepared to submit relevant design files if > necessary. > > Any ideas? > > > Thanks, > -- Matt > > > +-- > |Matthew Plante > | University of New Hampshire > | InterOperability Lab > | Research & Development > | SMTP: maplante@iol.unh.edu > | Phone: +1-603-862-0203 > +- > >Article: 90034
Hello Chris,
what is the ppc clock?
if it is over 200 MHz: did you watch the Xilinx answer database record
# 21820?
Best regards
Florian
Chris wrote:
> Hello,
>
> I am looking for some help with a particularily nasty problem I have
> run into,
>
> Out of our 10 prototype Virtex-4-FX20 (CES2 stepping) boards, roughly
> half are exhibiting an issue with the PPC405 starting up out of reset.
> After powerup, the bit file is loaded, done goes high, current load
> kicks in, but the PPC never boots. Other logic on the chip is running.
>
> When the device boots properly, there are no issues booting from BRAM,
> loading DDR-DRAM from flash, or executing from DRAM. Everthing is
> working good.
>
> Using chipscope, I can see the data from address 0xfffffffc being
> returned on the PPC405 PLB-I-Master side of the PLB arbiter correctly.
> However, the second address put out is garbage (0x100600), resulting in
> a bus error. The boot code is held in a BRAM off of the PLB. During a
> successful boot, the second address is 0xffffc000 which is correct.
> The reset sequence and first PLB bus cycle look identical in both the
> failing/non-failing cases.
>
> Observations:
> * Freeze spray (now known around here as 'FPGA programming spray') will
> without exception make this problem go away. (suggests a timing /
> power issue??)
> * Warm resets (through the EDK reset controller) have no effect. The
> only way to make this problem go away is to reload the device.
> * Reloading the device does not always work. Some boards will always
> boot fine on the second try, while others will only boot once cooled.
> * The emulator (tried both XMD and Greenhills probe) cannot talk to the
> processor when it is in this state.
> * Clocks, DCM locks, reset signals, debug/jtag signals, all look
> normal.
> * The PPC is in an unrecoverable state which is a little disturbing
> regardless of how it got there.
>
> What else have I tried (none of these have made a difference):
> * clocking the PPC405 slower. Same clock as the PLB.
> * JTAG loading -vs- selectmap loading
> * Boot from the OCM bus instead of the PLB.
> * Removed all other logic from the design except the PPC and an OCM
> BRAM
> * Looked closely at the power supplies / grounding.
> * I have already successfully played 'Stump the Xilinx FAE/factory'.
> * Spent hours in Timing Analyzer looking at any unconstrained nets.
> * Looked closely at errata
>
> What angles still left to explore
> * I am 95% convinced this is either the result of an external
> condition, or a chip defect.
> * So, I am working up a power-supply change to delay VCCO from VCCINT.
> I don't believe that is it, but I am running out of things to try.
>
> ...................
>
> Has anyone ever seen an issue like this (V4, or 2VPro)? I have done
> many FPGA designs over the years (although this is our first PPC-based
> design) and have rarely been this stumped.....
>
> Any and all advice is welcome. Email me or post here.
>
> Thanks,
> Chris
> '<*{{{><
Article: 90035I always think some positive feedback is important :-) Simon "Antti Lukats" <antti@openchip.org> wrote in message news:dhqq2a$up3$00$1@news.t-online.com... > "Simon Peacock" <simon$actrix.co.nz> schrieb im Newsbeitrag > news:433f22f3$1@news2.actrix.gen.nz... > > who the F*** designed your web site.... I know putting frames around > product > > briefs lets you keep your logo.. but that's almost 2/3's of the screen > > gone... > > > > Simon > > > > translated: fire your web designer :-) > > > > Thanks Simon! > > no translation required, I agree with you 2000 %, > but I have no influence to solve the issue. :( > > Antti > PS its not my website. Its from the company I work for at the moment. > (my contract ends 31.12.2005) > >Article: 90036
"wanch" <wpora@hotmail.com> schrieb im Newsbeitrag news:1128180264.823258.225880@g47g2000cwa.googlegroups.com... > Could you suggest some devices which are suitable to run at a clock > rate more than 311MHz? > well my comment was only regarding the DCM max output on slowest S3 (-ES !) I guess that fastest speed grade non -ES S3 parts go above 275MHz as DCM output. as of actual measurement I have measured in S3 -4 silicon internal signals above 400MHz somewhere above 450MHz the fabric stops toggling but if you manage to feed in the 311 MHz clock then the S3 fabric should still work if the design is properly done as of other parts that run at rate of more then 311MHz out of curiosity I tested slowest speed grade Lattice EC FPGA (LFEC3E-3) PLL input 100MHz (from LVDS oscillator) PLL output 325MHz, good signal measured on output pin PLL output 400MHz, looks like working also but as my 500MHz DSO is sampling only 1000GS/s (I dont know how to force the 2GS/s mode!) shows not so nice sinus as there arent much samples. But I think the signals is really 400MHz. so in any case the Lattice part (cheapest, slowest) is working as of the PLL output above 311MHz at least. AnttiArticle: 90037
Elling Diesen wrote: > I am currently designing an RLDRAM-II controller in a Xilinx Virtex-II > Pro with the following specifications: > > Device = MT49H8M36FM-5 > Array = 1 device deep x 4 devices wide (8 Meg x 144) > Speed = 175 MHz > > Mode value = 388 hex > Configuration = 1 (RC = 4, RL=4, WL=5) > Burst length = 4 > Address bus = nonmultiplexed > DLL = enabled > Impedance matching = external > On-die termination = enabled > > The design works well except for one major problem. When reading a four > data-phase burst, the third and fourth data-phase contains identical > data. The value for phase three is duplicated in phase four. If the > written data is A-B-C-D, the read data will be A-B-C-C. > > This symptom is permanent and identical over the entire width and depth > of the memory space. There is reason to believe that the problem is > not caused by an incorrect write sequence, because random data in > memory after power-on is read back with the same symptom (identical > data in third and fourth data-phase). > > The problem is probably not caused by data capture either, because I am > observing the read data just after the input flip-flops (using Xilinx > ChipScope). I have been delaying the read clock (QK) over one clock > period in 300 ps intervals and can never see the correct data sequence. > > Have you seen this problem earlier? Are the RAM devices in an invalid > state? Can an incorrect initialization sequence cause this kind of > behavior? I have implemented the initialization sequence according to > the data sheet. > > Thanks in advance. > > Best regards > Elling Diesen > VMETRO asa > Oslo, Norway Once I had similar problems with SDRAM. You read the C-value twice because the RAM is not driving the D-value to the bus. It simply goes to High-Z after C. Without looking for the specs I would asume you control only 3 beat bursts to the RAM. I gues your forth write is wrong either (but you cannot see it). To prove the behavior let the read burst start at eg address 2 to read the fourth entry. In my case it was B-C-D-D by a capture shifted one cycle back. Regards ThomasArticle: 90038
That's where my snippet is different.. the "for generate " will repeat that mux 64 times for you :-) nice and simple isn't it ??? The problem is you have to think of the resources.. I don't know exactly.. but the number of loads on any CLB are finite.. I doubt they are 64... so the whole thing gets repeated multiple times as you are talking 8x240 outputs you will chew up resources horribly fast. The Next problem is Xilinexs as with all FPGA's are a compromise... the 1 M gate quote is based upon designs which are synchronous.. and yours isn't.. that makes a huge mux very inefficient and not what the tools are designed to cope with. The best bet would be to rethink.. possibly use the idea of shifting the data into a dual port ram.. and using the second port of the ram as the output of the mux... it does mean your design ends up pipelined.. but you will be struggling to do it some other way. The other solution is to put down 4 FPGA's Simon "vssumesh" <vssumesh_asic@yahoo.com> wrote in message news:1128328159.468110.157190@f14g2000cwb.googlegroups.com... > Hello Simon, > Yes i am trying to implement the 64 nos of 8bit wide (240:1) mux. > And there is 240 * 64 = 15360 total selction bits (240 bits to each > mux). And 240 * 8 = 1920 data bits to whole block of 64 muxs (same data > goes to all MUX). Thus the mux array block will have 17280 input lines > and 64 * 8 output lines. Why you are saying that it is not possible. > All signals are internally generated from other parametrs (I dont know > the internal routing efforts of the FPGA). Please advice. > The mux (the code) you suggested is a single 240 to 1 byte mux. But i > want 64 copies of that. Is that possible. I know that it is not > possible to implement it in asingle design by getting the selction > signal from external sources; is it because of this constrain that the > ISE stops working. I am able to get output if i reduce any of the > parametrs to half (no: out put or no: registers etc). >Article: 90039
Antti Lukats wrote: > I am regret to inform you all that this the last time I either > post or reply to comp.arch.fpga newsgroup > ... > ...doesnt make any difference to my decision which is final > ... > A small explanation ... is available but not for free > ... Antti Lukats wrote: >it looks that i cant stay away (e.g. be silent). >I do own an explanation (for my last/previous posting) I know > but that has to wait. Nice to see you changed idea :-) (only stupid peoples never change idea...) Only... I hope You don't ask money to explain... ;-) bye SandroArticle: 90040
Every thing is correct. But i cant simply change my design. What i am thinking now is to proceed with the 120 register version. If required i can switch over to Virtex "XC2V8000". Will that help (with 8M gates). But i am still wondering why Xilinx is not doing any synthesizing work. And about your code is there any way to implement the same in verilog. I dont know VHDL.Article: 90041
I own and use Xilinx ISE 7.1 BaseX and to develop Spartan-3 code. I have a client who owns and uses ISE 6.3 BaseX but is not in a position to upgrade to 7.1 right now, policy against changing tools until a project has been completed. Anyway, I have developed some VHDL code that makes use of the filter and FIFO IPs from CoreGen and I'd like to just turn it over to them so they can integrate it into their project. The problem is they can't just read the .ISE project since Xilinx in their wisdom changed project file formats between 6.3 and 7.1 and I can't export my project in a form readable by 6.3. It does look like my version of CoreGen and my client's version of CoreGen contain the same cores which is promissing. My solution so far is just to give them the VHDL code and a description of the project tree but there as been some confustion at the 6.3 end about how to get the CoreGen output re-integrated. Just giving them the .XCO doesn't always work. Their 6.3 guy has tried to explain the errors to me and they sound mostly like pathname-not-found and file-not-found type errors due to absolute path information. So I write them a description of all the selected options in the core and their 6.3 guy has to re-create the core from their version of CoreGen. Seems a bit slow and silly. Suggestions for a better way? RobArticle: 90042
Florian wrote: > Hello Chris, > > what is the ppc clock? > if it is over 200 MHz: did you watch the Xilinx answer database record > # 21820? I have been running the PPC at the slow PLB clock (77 MHz) for now until I get the startup issue fixed. However, I checked my EDK project and the parameter was not added. It is interesting I did not run into any problems with (DFS_MODE = Low) when running the PPC at 224 MHz. Thanks for pointing that out. Regards, - ChrisArticle: 90043
"Rob Young" wrote: >My solution so far is just to give them the VHDL code and a description of >the project tree but there as been some confustion at the 6.3 end about how >to get the CoreGen output re-integrated. Just giving them the .XCO doesn't >always work. Their 6.3 guy has tried to explain the errors to me and they >sound mostly like pathname-not-found and file-not-found type errors due to >absolute path information. So I write them a description of all the >selected options in the core and their 6.3 guy has to re-create the core >from their version of CoreGen. Seems a bit slow and silly. > >Suggestions for a better way? Yes. Don't use the Graphical User Interfaces. GUIs are, well, gooey. Copy the .xco file to a .txt file so that Xilinx tools will not mess with it. Edit this file to fix the paths to be relative. Generate a make file and run coregen in batch mode with that make file specifying the .txt file as the input to coregen. Run this with both the current (7.1) and the version the client is using (6.3) to make sure that it works for both. If it doesn't, see if you can fix the offending lines. You can have any number of Xilinx versions on your system and switch between them by changing the XILINX variable to point to the correct directory and the path as well: set XILINX=C:\Xilinx_dir path C:\Xilinx_dir\bin\nt;%path% It helps if you specified a meaningful directory name when installing like Xilinx_63 or Xilinx_71. I use GNU make as part of the Cygwin package. Make documentation is at: http://www.gnu.org/software/make/manual/html_mono/make.html Cygwin is a "linux" or "unix" command package for windows. See: http://www.cygwin.com/ The make file can also run all of the tools in command line mode. -- Phil Hays to reply solve: phil_hays at not(coldmail) dot com If not cold then hotArticle: 90044
"logjam" <grant@cmosxray.com> wrote in news:1126586558.061877.123600 @g47g2000cwa.googlegroups.com: > Those pictures were of the ASG, Apple Sound Generator, in the 128k to > Plus macintosh. I figured, based on the pinout you gave. Isn't it easier to apply vectors to the input pins and reverse engineer the equations that way? I'd like to get the equations for the Mac PLUS PALs. Retro www.retro.co.zaArticle: 90045
please someone let me know the effects of having "ibuf_lvcmos33" for each input , "obuf_lvcmos33" for each output and "bufg" in some entity declarations. In addition please let me know the effect of mappimg clk to clock in the following entity declaration. entity test is port (clock : in std_logic ) end clock ; architecture arch_test of test is signal clk : std_logic ; clk <= clock; end architecture arch_test ; in the remainder of the definition, only "clk" is used. "clock" is never used. Why cant we just use "clock".Article: 90046
I don't know spartan devices. I only work with Virtex-II and virtex-II Pro. I have a look on spartan datasheet and according to your requirements I don't see how you can do except if decimation ratio is greater than 4 (or if you increase clock rate upto (decimation filter input data rate)*32). I've seen you can use up to 4 multipliers. Why do you want to use only one? --------------------------------------------- -- TechwaY -- TechwaY Partners -------------------------------------------Article: 90047
Thomas Entner wrote: >>The video out has asynchronous resonant spikes running >>through it. The spikes are about 100 mV p-p, and have a >>resonant frequency of about 250 MHz, with about 6 half-cycles >>present. >> >>There is also about 15 mV p-p of pixel clock and harmonics. >> > > > Hard to believe when Xilinx tells us that they are signal integrity > leader... > > (Sorry, just could not resist ;-) In case anyone is wondering, the comments being made about the VGA quality on the ML401, ML402, and ML403 (they share the same PCB) are correct. All of the initial tests that we did with the VGA output didn't show any screen effects with the monitors that we were using. After we released the boards, we received customer feedback on the VGA quality and after looking over the issue discovered that the analog portions of the PCB were not optimal. We have improved the VGA quality on the upcoming ML405 and ML410 boards that will be released early next year. EdArticle: 90048
"CMOS" <manusha@millenniumit.com> wrote in message news:1128352673.222085.168650@g49g2000cwa.googlegroups.com... > > in the remainder of the definition, only "clk" is used. "clock" is > never used. Why cant we just use "clock". > This technique avoids excessive wear on the 'c' and 'o' keys of your computer. It's important to keep these keys in pristine condition in case you need to email for coffee or cocoa. HTH, Syms.Article: 90049
CMOS wrote:
> please someone let me know the effects of having "ibuf_lvcmos33" for
> each input , "obuf_lvcmos33" for each output and "bufg" in some entity
> declarations.
These connect the device pins
to the design. If you are using synthesis,
these will be inferred where needed.
> In addition please let me know the effect of mappimg clk to clock in
> the following entity declaration.
No effect for syntheses, other than possible confusion.
An extra delta delay for simulation.
I would just change the port name to clk.
-- Mike Treseler
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