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Threads Starting Dec 2005
92534: 05/12/01: backhus: Re: Any fpga tutorials online?
92536: 05/12/01: Reza: Help : Code works in synthesizer (silos), but warnings w/ webpack
92554: 05/12/01: gallen: Re: Help : Code works in synthesizer (silos), but warnings w/ webpack
92562: 05/12/01: johnp: Re: Help : Code works in synthesizer (silos), but warnings w/ webpack
92568: 05/12/01: Reza: Re: Help : Code works in synthesizer (silos), but warnings w/ webpack
92578: 05/12/01: johnp: Re: Help : Code works in synthesizer (silos), but warnings w/ webpack
92605: 05/12/02: gallen: Re: Help : Code works in synthesizer (silos), but warnings w/ webpack
92537: 05/12/01: Marco: Which Phy transceiver for 10/100 ethernet?
92542: 05/12/01: Joseph Samson: Re: Which Phy transceiver for 10/100 ethernet?
92538: 05/12/01: Davy: Multi-layer switch network?
92544: 05/12/01: Kolja Sulimma: Re: Multi-layer switch network?
92607: 05/12/02: Davy: Re: Multi-layer switch network?
92748: 05/12/06: nospam.eric@gmail.com: Re: Multi-layer switch network?
92791: 05/12/06: Iain McClatchie: Re: Multi-layer switch network?
92539: 05/12/01: John Adair: Re: Any fpga tutorials online?
92540: 05/12/01: Martin Schoeberl: Quartus db issue
92545: 05/12/01: Subroto Datta: Re: Quartus db issue
92549: 05/12/01: Martin Schoeberl: Re: Quartus db issue
92543: 05/12/01: Eli Hughes: Re: Any fpga tutorials online?
92548: 05/12/01: Okashii: Any fpga tutorials online?
92583: 05/12/01: Brad Smallridge: Re: Any fpga tutorials online?
92635: 05/12/02: John Adair: Re: Any fpga tutorials online?
92557: 05/12/01: <juendme@yahoo.com>: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92566: 05/12/01: Dave Pollum: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92602: 05/12/02: Simon Peacock: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92686: 05/12/05: Antti Lukats: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92691: 05/12/05: Antti Lukats: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92693: 05/12/05: David Brown: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92694: 05/12/05: Antti Lukats: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92699: 05/12/05: David Brown: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92706: 05/12/05: Antti Lukats: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92712: 05/12/05: Austin Lesea: What's wrong with the document?
92714: 05/12/05: mk: Re: What's wrong with the document?
92720: 05/12/05: Austin Lesea: Re: What's wrong with the document?
92727: 05/12/05: Austin Lesea: Re: What's wrong with the document?
92750: 05/12/06: Brian Drummond: Re: What's wrong with the document?
92716: 05/12/05: Kolja Sulimma: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92572: 05/12/01: <juendme@yahoo.com>: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92653: 05/12/02: Peter Alfke: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92685: 05/12/04: <juendme@yahoo.com>: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92689: 05/12/04: <juendme@yahoo.com>: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92690: 05/12/04: <juendme@yahoo.com>: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92704: 05/12/05: Peter Alfke: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92709: 05/12/05: <juendme@yahoo.com>: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92723: 05/12/05: <juendme@yahoo.com>: Re: What's wrong with the document?
92725: 05/12/05: <juendme@yahoo.com>: Re: What's wrong with the document?
92729: 05/12/05: Peter Alfke: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92733: 05/12/05: <juendme@yahoo.com>: Re: What's wrong with the document?
92734: 05/12/05: <juendme@yahoo.com>: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92736: 05/12/05: Peter Alfke: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92582: 05/12/01: Peter Alfke: Re: Xilinx LUT behavior question
92585: 05/12/02: Frank: Quick question, how do I supply +-5V?
92586: 05/12/01: Michael R. Kesti: Re: Quick question, how do I supply +-5V?
92587: 05/12/01: Ryan Weihl: Re: Quick question, how do I supply +-5V?
92588: 05/12/01: Jerry Avins: Re: Quick question, how do I supply +-5V?
92589: 05/12/02: Steve Underwood: Re: Quick question, how do I supply +-5V?
92590: 05/12/01: Jerry Avins: Re: Quick question, how do I supply +-5V?
92591: 05/12/02: Frank: Re: Quick question, how do I supply +-5V?
92626: 05/12/02: Jerry Avins: Re: Quick question, how do I supply +-5V?
92633: 05/12/02: Dave: Re: Quick question, how do I supply +-5V?
92647: 05/12/02: Grant Edwards: Re: Quick question, how do I supply +-5V?
92645: 05/12/02: Mark Haase: Re: Quick question, how do I supply +-5V?
92646: 05/12/02: Jerry Avins: Re: Quick question, how do I supply +-5V?
92724: 05/12/05: c d saunter: Re: Quick question, how do I supply +-5V?
92728: 05/12/05: Bob Monsen: Re: Quick question, how do I supply +-5V?
92730: 05/12/05: c d saunter: Re: Quick question, how do I supply +-5V?
92735: 05/12/05: Jerry Avins: Re: Quick question, how do I supply +-5V?
92737: 05/12/06: Symon: Re: Quick question, how do I supply +-5V?
92747: 05/12/06: Meindert Sprang: Re: Quick question, how do I supply +-5V?
92749: 05/12/06: Paul Keinanen: Re: Quick question, how do I supply +-5V?
92592: 05/12/01: Fred Marshall: Re: Quick question, how do I supply +-5V?
92630: 05/12/02: Jerry Avins: Re: Quick question, how do I supply +-5V?
92677: 05/12/04: Bob Monsen: Re: Quick question, how do I supply +-5V?
92593: 05/12/01: Len: Re: Quick question, how do I supply +-5V?
92738: 05/12/05: <google@gornall.net>: Re: Quick question, how do I supply +-5V?
92596: 05/12/02: Antti Lukats: Virtex-4 FX60 based products are already shipping now !
92615: 05/12/02: <francesco_poderico@yahoo.com>: Re: Virtex-4 FX60 based products are already shipping now !
92616: 05/12/02: Antti Lukats: Re: Virtex-4 FX60 based products are already shipping now !
92620: 05/12/02: John Adair: Re: Virtex-4 FX60 based products are already shipping now !
92629: 05/12/02: Austin Lesea: What if....
92631: 05/12/02: Antti Lukats: Re: What if....
92634: 05/12/02: John Adair: Re: What if....
92641: 05/12/02: Austin Lesea: Re: What if....
92663: 05/12/03: Brian Drummond: Re: What if....
92687: 05/12/05: Hal Murray: Re: What if....
92696: 05/12/05: H: Re: What if....
92597: 05/12/01: <paddy3118@netscape.net>: Info on packing regular tree-like structures into rectangles?
92761: 05/12/06: Ralf Hildebrandt: Re: Info on packing regular tree-like structures into rectangles?
92598: 05/12/01: <clemenr@wmin.ac.uk>: Curious about FPGAs
92612: 05/12/02: <allanherriman@hotmail.com>: Re: Curious about FPGAs
92619: 05/12/02: John Adair: Re: Curious about FPGAs
92625: 05/12/02: <clemenr@wmin.ac.uk>: Re: Curious about FPGAs
92599: 05/12/02: bijoy: FPGA : Decimation Filter Implementation
92606: 05/12/02: Simon Peacock: Re: FPGA : Decimation Filter Implementation
92643: 05/12/02: Symon: Re: FPGA : Decimation Filter Implementation
92681: 05/12/05: Simon Peacock: Re: FPGA : Decimation Filter Implementation
92722: 05/12/05: Symon: Re: FPGA : Decimation Filter Implementation
92744: 05/12/06: Simon Peacock: Re: FPGA : Decimation Filter Implementation
92777: 05/12/06: Symon: Re: FPGA : Decimation Filter Implementation
92793: 05/12/07: David Brown: Re: FPGA : Decimation Filter Implementation
92856: 05/12/07: bijoy: Re: FPGA : Decimation Filter Implementation
93597: 05/12/25: akcooper8@gmail.com: Re: FPGA : Decimation Filter Implementation
92600: 05/12/02: Chloe: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model
92624: 05/12/02: Ryan Jones: Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model
92662: 05/12/03: John Adair: Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model
92787: 05/12/06: Chloe: Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model
92790: 05/12/06: Chloe: Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model
92603: 05/12/02: kyeyk: Virtex 4 IDELAY implementation
92674: 05/12/04: Jim Wu: Re: Virtex 4 IDELAY implementation
92795: 05/12/07: kyeyk: re:Virtex 4 IDELAY implementation
92613: 05/12/02: Antti Lukats: Spartan3E availability update
92617: 05/12/02: Raymund Hofmann: Re: Spartan3E availability update
92684: 05/12/05: Simon Peacock: Re: Spartan3E availability update
92916: 05/12/09: Antti Lukats: Re: Spartan3E availability update
92622: 05/12/02: Simon: Synthesize: Error
92639: 05/12/02: Brad Smallridge: Re: Synthesize: Error
92649: 05/12/02: Andy Peters: Re: Synthesize: Error
92698: 05/12/05: Simon: Re: Synthesize: Error
92703: 05/12/05: mk: Re: Synthesize: Error
92632: 05/12/02: Weng Tianxiang: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92638: 05/12/02: Brad Smallridge: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92680: 05/12/05: Simon Peacock: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92715: 05/12/05: Brad Smallridge: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92739: 05/12/06: Philip Freidin: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92741: 05/12/06: John Williams: Re: Is it legal to write an logical equation for a FPGA LUT in claims
92640: 05/12/02: Weng Tianxiang: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92710: 05/12/05: Weng Tianxiang: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92719: 05/12/05: Peter Alfke: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92726: 05/12/05: Kolja Sulimma: Re: Is it legal to write an logical equation for a FPGA LUT in claims
92731: 05/12/05: Weng Tianxiang: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92732: 05/12/06: Jim Granville: Re: Is it legal to write an logical equation for a FPGA LUT in claims
92743: 05/12/06: Simon Peacock: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92757: 05/12/06: Weng Tianxiang: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92976: 05/12/10: raul: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92636: 05/12/02: Brad Smallridge: Xilinx V4 ISERDES problem
92692: 05/12/05: joseph: Re: Xilinx V4 ISERDES problem
92713: 05/12/05: Brad Smallridge: Re: Xilinx V4 ISERDES problem
92644: 05/12/02: Dave Pollum: Re: Quick question, how do I supply +-5V?
92650: 05/12/02: <bachimanchi@gmail.com>: problem with timing simulation
92652: 05/12/02: <bachimanchi@gmail.com>: problem with timing simulation (clear explanation of problem)
92752: 05/12/06: Aurelian Lazarut: Re: problem with timing simulation (clear explanation of problem)
92654: 05/12/02: hirenshah.05@gmail.com: internal clock
92657: 05/12/03: Antti Lukats: Re: internal clock
92655: 05/12/03: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: ML403 "small" problem
92664: 05/12/03: Peter Ryser: Re: ML403 "small" problem
92666: 05/12/03: Erik Widding: Re: ML403 "small" problem
92667: 05/12/03: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: ML403 "small" problem
92656: 05/12/03: Akhil: Hardware Modeling Verification
92659: 05/12/03: Pankaj: Using RiscWatch with Xilinx FPGA's for powerpc
92660: 05/12/03: Antti Lukats: Re: Using RiscWatch with Xilinx FPGA's for powerpc
92665: 05/12/03: <nahum@oksi.com>: Looking for FPGA Programming consultant
92668: 05/12/03: nshrestha: Problem Timing Simulation CoolRunner II Design Kit
92670: 05/12/03: <bachimanchi@gmail.com>: how to build 32X32 LUT ROM
92671: 05/12/04: John Retta: Re: how to build 32X32 LUT ROM
92672: 05/12/04: John Adair: Re: how to build 32X32 LUT ROM
92682: 05/12/05: Simon Peacock: Re: how to build 32X32 LUT ROM
92673: 05/12/04: c d saunter: Tip: Spotlight (OS X) indexing of VHDL files
92705: 05/12/05: Andy Peters: Re: Tip: Spotlight (OS X) indexing of VHDL files
92708: 05/12/05: Eli Hughes: Re: Tip: Spotlight (OS X) indexing of VHDL files
92721: 05/12/05: c d saunter: Re: Tip: Spotlight (OS X) indexing of VHDL files
92676: 05/12/04: Vaughn Betz: Power Optimization NetSeminar: Wedesday, Dec. 7 at 11 am PST
92678: 05/12/05: Jim Granville: Re: Power Optimization NetSeminar: Wedesday, Dec. 7 at 11 am PST
92745: 05/12/06: Vaughn Betz: Re: Power Optimization NetSeminar: Wedesday, Dec. 7 at 11 am PST
92688: 05/12/04: Lina: programming flash memeory
92695: 05/12/05: Antti Lukats: Re: programming flash memeory
92700: 05/12/05: Lina: Re: programming flash memeory
92697: 05/12/05: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Chipscope under Linux
92762: 05/12/06: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: Chipscope under Linux
92701: 05/12/05: Brian Drummond: Virtex-4 DSP48 placement restrictions?
92717: 05/12/05: Brian Drummond: Re: Virtex-4 DSP48 placement restrictions?
92718: 05/12/05: Ray Andraka: Re: Virtex-4 DSP48 placement restrictions?
92751: 05/12/06: Brian Drummond: Re: Virtex-4 DSP48 placement restrictions?
92767: 05/12/06: Ray Andraka: Re: Virtex-4 DSP48 placement restrictions?
92702: 05/12/05: kenton: Use EMC to control a FIFO ?
92707: 05/12/05: Antti Lukats: ISE 8.1 release delayed?
92746: 05/12/06: Simon Peacock: Re: ISE 8.1 release delayed?
92766: 05/12/06: Ray Andraka: Re: ISE 8.1 release delayed?
92918: 05/12/09: Antti Lukats: Re: ISE 8.1 release delayed?
92782: 05/12/06: Andy Peters: Re: ISE 8.1 release delayed?
92783: 05/12/07: Symon: Re: ISE 8.1 release delayed?
92785: 05/12/07: Jim Granville: Re: ISE 8.1 release delayed?
92792: 05/12/07: Antti Lukats: Re: ISE 8.1 release delayed?
92922: 05/12/09: Phil Hays: Re: ISE 8.1 release delayed?
92711: 05/12/05: Ryan Jones: Re: ISE 8.1 news--BaseX going away, but WebPack gains devices and features
92753: 05/12/06: Michael: IDE for Nios2 does not compile on windows XP
92754: 05/12/06: Thomas Entner: Re: IDE for Nios2 does not compile on windows XP
92755: 05/12/06: Michael: Re: IDE for Nios2 does not compile on windows XP
92756: 05/12/06: Marco: VHDL SPI core
92781: 05/12/06: Andy Peters: Re: VHDL SPI core
92797: 05/12/07: <rponsard@ac-grenoble.fr>: Re: VHDL SPI core
92758: 05/12/06: <porterboy76@yahoo.com>: Re: xilinx research labs
92759: 05/12/06: Steven Derrien: Re: xilinx research labs
92788: 05/12/07: Antti Lukats: Re: xilinx research labs
92760: 05/12/06: Austin Lesea: Re: xilinx research labs
92765: 05/12/06: Steven Derrien: Re: xilinx research labs
92775: 05/12/06: Austin Lesea: Re: xilinx research labs
92822: 05/12/07: Steven Derrien: Re: xilinx research labs
92763: 05/12/06: <jaxato@gmail.com>: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS
92764: 05/12/06: Paul Hartke: Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS
92773: 05/12/06: Jan Tjernberg: Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS
92769: 05/12/06: <jaxato@gmail.com>: Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS
92770: 05/12/06: Paul Hartke: Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS
92772: 05/12/06: <jaxato@gmail.com>: Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS
92771: 05/12/06: <aiiadict@gmail.com>: Job available... 2 projects
92774: 05/12/06: Dave Pollum: Re: Job available... 2 projects
92900: 05/12/08: bijoy: Re: Job available... 2 projects
92930: 05/12/09: acidocinico: re:Job available... 2 projects
92987: 05/12/10: fahadislam2002: re:Job available... 2 projects
92778: 05/12/06: <jaxato@gmail.com>: Re: xilinx research labs
92780: 05/12/07: Mark McDougall: Re: VHDL SPI core
92784: 05/12/06: Stephen: Re: xilinx research labs
92789: 05/12/06: <aiiadict@gmail.com>: fpga tutorial?
92794: 05/12/07: Marco: How to connect 2 FPGA?
92796: 05/12/07: Antti Lukats: Re: How to connect 2 FPGA?
92802: 05/12/07: Marco: Re: How to connect 2 FPGA?
92803: 05/12/07: Antti Lukats: Re: How to connect 2 FPGA?
92887: 05/12/08: Uwe Bonnes: Re: How to connect 2 FPGA?
92934: 05/12/09: Carsten: Re: How to connect 2 FPGA?
92969: 05/12/10: Marco: Re: How to connect 2 FPGA?
92801: 05/12/07: Rene Tschaggelar: Re: How to connect 2 FPGA?
92798: 05/12/07: <svasus@gmail.com>: I2C controller chipset to interface with FPGA
92799: 05/12/07: Antti Lukats: Re: I2C controller chipset to interface with FPGA
92811: 05/12/07: Martin Thompson: Re: I2C controller chipset to interface with FPGA
92847: 05/12/07: Eric Smith: Re: I2C controller chipset to interface with FPGA
92857: 05/12/08: Antti Lukats: Re: I2C controller chipset to interface with FPGA
92888: 05/12/08: Eric Smith: Re: I2C controller chipset to interface with FPGA
92890: 05/12/09: Jim Granville: Re: I2C controller chipset to interface with FPGA
92841: 05/12/08: Jim Granville: Re: I2C controller chipset to interface with FPGA
92893: 05/12/09: Jim Granville: Re: I2C controller chipset to interface with FPGA
92843: 05/12/07: Kryten: Re: I2C controller chipset to interface with FPGA
92846: 05/12/08: Jim Granville: Re: I2C controller chipset to interface with FPGA
92848: 05/12/07: Ray Andraka: Re: I2C controller chipset to interface with FPGA
92860: 05/12/08: Petter Gustad: Re: I2C controller chipset to interface with FPGA
92879: 05/12/08: Kolja Sulimma: Re: I2C controller chipset to interface with FPGA
92800: 05/12/07: Abbs: VERIFICATION AND TESTING
92859: 05/12/07: Thomas Stanka: Re: VERIFICATION AND TESTING
92953: 05/12/09: Hans: Re: VERIFICATION AND TESTING
92868: 05/12/08: Abbs: Re: VERIFICATION AND TESTING
93126: 05/12/14: Abbs: Re: VERIFICATION AND TESTING
92804: 05/12/07: John Adair: Free Seminars - UK
92805: 05/12/07: hongying meng: FPGA development board with digital image camera
92807: 05/12/07: Antti Lukats: Re: FPGA development board with digital image camera
92808: 05/12/07: Michael: Re: FPGA development board with digital image camera
92810: 05/12/07: Gabor: Re: FPGA development board with digital image camera
92812: 05/12/07: Antti Lukats: Re: FPGA development board with digital image camera
92823: 05/12/07: Joseph Samson: Re: FPGA development board with digital image camera
92826: 05/12/07: Antti Lukats: Re: FPGA development board with digital image camera
92866: 05/12/08: Michael: Re: FPGA development board with digital image camera
92869: 05/12/08: Jan Panteltje: Re: FPGA development board with digital image camera
92876: 05/12/08: Paul Hartke: Re: FPGA development board with digital image camera
92877: 05/12/08: Antti Lukats: Re: FPGA development board with digital image camera
92878: 05/12/08: <kempaj@yahoo.com>: Re: FPGA development board with digital image camera
92806: 05/12/07: ylc199: Stratix EP1S80 DSP development board (Problem for ADC/DAC conversion )
92814: 05/12/07: Rene Tschaggelar: Re: Stratix EP1S80 DSP development board (Problem for ADC/DAC conversion
92850: 05/12/07: ylc199: Re: Stratix EP1S80 DSP development board (Problem for ADC/DAC conversion )
92809: 05/12/07: damir: VGA controller
92813: 05/12/07: Antti Lukats: Re: VGA controller
92817: 05/12/07: damir: Re: VGA controller
92837: 05/12/08: Don McKenzie: Re: VGA controller
92864: 05/12/08: damir: Re: VGA controller
92815: 05/12/07: Antti Lukats: Free x86 IP-Core is really working!
92862: 05/12/08: Hans: Re: Free x86 IP-Core is really working!
92863: 05/12/08: Antti Lukats: Re: Free x86 IP-Core is really working!
92992: 05/12/11: Antti Lukats: Re: Free x86 IP-Core is really working!
92816: 05/12/07: nshrestha: Problem programming CoolRunner II xc2c256_tq144 CPLD using IMPACT
92819: 05/12/07: Aurelian Lazarut: Re: Problem programming CoolRunner II xc2c256_tq144 CPLD using IMPACT
92820: 05/12/07: Antti Lukats: Re: Problem programming CoolRunner II xc2c256_tq144 CPLD using IMPACT
92821: 05/12/07: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: A stupid question about constraints
92824: 05/12/07: jerzy.gbur@gmail.com: Re: A stupid question about constraints
92831: 05/12/07: Antti Lukats: Re: A stupid question about constraints
92825: 05/12/07: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: A stupid question about constraints
92829: 05/12/07: <wtxwtx@gmail.com>: Mean value filter
93078: 05/12/13: gabor: Re: Mean value filter
93094: 05/12/13: <wtxwtx@gmail.com>: Re: Mean value filter
93110: 05/12/13: JustJohn: Re: Mean value filter
93143: 05/12/14: <wtxwtx@gmail.com>: Re: Mean value filter
93162: 05/12/14: JustJohn: Re: Mean value filter
93192: 05/12/15: <wtxwtx@gmail.com>: Re: Mean value filter
93209: 05/12/15: JustJohn: Re: Mean value filter
93271: 05/12/17: <wtxwtx@gmail.com>: Re: Mean value filter
93297: 05/12/19: JustJohn: Re: Mean value filter
93302: 05/12/19: <wtxwtx@gmail.com>: Re: Mean value filter
93303: 05/12/19: <wtxwtx@gmail.com>: Re: Mean value filter
93305: 05/12/19: JustJohn: Re: Mean value filter
93355: 05/12/20: <wtxwtx@gmail.com>: Re: Mean value filter
93390: 05/12/21: Gabor: Re: Mean value filter
93452: 05/12/22: <wtxwtx@gmail.com>: Re: Mean value filter
92830: 05/12/07: Stephen: Re: xilinx research labs
92832: 05/12/07: <reidek@gmail.com>: Embedded ppc405 w/o RAM?
92834: 05/12/07: Antti Lukats: Re: Embedded ppc405 w/o RAM?
92838: 05/12/07: Kunal Shenoy: Re: Embedded ppc405 w/o RAM?
92844: 05/12/07: Austin Lesea: Re: Embedded ppc405 w/o RAM?
92874: 05/12/08: Austin Lesea: Re: Embedded ppc405 w/o RAM?
92840: 05/12/07: Peter Alfke: Re: Embedded ppc405 w/o RAM?
92842: 05/12/07: reidek@gmail.com: Re: Embedded ppc405 w/o RAM?
92845: 05/12/07: reidek@gmail.com: Re: Embedded ppc405 w/o RAM?
92881: 05/12/08: Peter Ryser: Re: Embedded ppc405 w/o RAM?
92833: 05/12/07: <porterboy76@yahoo.com>: Re: xilinx research labs
92835: 05/12/07: Alex: PLX 9056 application
92839: 05/12/07: Alan Nishioka: Re: PLX 9056 application
92836: 05/12/07: Antti Lukats: some new PCIe products
92907: 05/12/09: Ben Twijnstra: Re: some new PCIe products
92908: 05/12/09: Antti Lukats: Re: some new PCIe products
92913: 05/12/09: Jeff Cunningham: Re: some new PCIe products
93070: 05/12/13: Antti Lukats: Re: some new PCIe products
92849: 05/12/07: Scott Bekker: Virtex 4 not meeting timing constraints
92851: 05/12/07: Jeff Cunningham: Re: Virtex 4 not meeting timing constraints
92886: 05/12/08: Ray Andraka: Re: Virtex 4 not meeting timing constraints
93314: 05/12/19: Ray Andraka: Re: Virtex 4 not meeting timing constraints
93301: 05/12/19: Scott Bekker: Re: Virtex 4 not meeting timing constraints
92853: 05/12/07: Chloe: Simulating Post-Synthesis Model on Xilinx FPGA
92880: 05/12/08: <ghelbig@lycos.com>: Re: Simulating Post-Synthesis Model on Xilinx FPGA
92897: 05/12/08: Mike Treseler: Re: Simulating Post-Synthesis Model on Xilinx FPGA
92901: 05/12/08: Ray Andraka: Re: Simulating Post-Synthesis Model on Xilinx FPGA
92892: 05/12/08: Chloe: Re: Simulating Post-Synthesis Model on Xilinx FPGA
92894: 05/12/08: <ghelbig@lycos.com>: Re: Simulating Post-Synthesis Model on Xilinx FPGA
92895: 05/12/08: Newman: Re: Simulating Post-Synthesis Model on Xilinx FPGA
92896: 05/12/08: Chloe: Re: Simulating Post-Synthesis Model on Xilinx FPGA
92898: 05/12/08: Chloe: Re: Simulating Post-Synthesis Model on Xilinx FPGA
92899: 05/12/08: Chloe: Re: Simulating Post-Synthesis Model on Xilinx FPGA
92903: 05/12/08: Ray Andraka: Re: Simulating Post-Synthesis Model on Xilinx FPGA
92854: 05/12/07: rybol: 2 clocks switching
92855: 05/12/07: Peter Alfke: Re: 2 clocks switching
92870: 05/12/08: Aurelian Lazarut: Re: 2 clocks switching
92871: 05/12/08: Len: Re: 2 clocks switching
92858: 05/12/07: <Sudhir.Singh@email.com>: Post PAR Simulation and Actual FPGA results differ
92861: 05/12/08: ALuPin@web.de: Re: Post PAR Simulation and Actual FPGA results differ
92950: 05/12/09: Jeff Cunningham: Re: Post PAR Simulation and Actual FPGA results differ
92967: 05/12/09: <Sudhir.Singh@email.com>: Re: Post PAR Simulation and Actual FPGA results differ
92979: 05/12/10: <juendme@yahoo.com>: Re: Post PAR Simulation and Actual FPGA results differ
92984: 05/12/11: info_: Re: Post PAR Simulation and Actual FPGA results differ
92865: 05/12/08: nospam.eric@gmail.com: Re: How to connect 2 FPGA?
92867: 05/12/08: Marco: Re: How to connect 2 FPGA?
92882: 05/12/09: Simon Peacock: Re: How to connect 2 FPGA?
92884: 05/12/09: Simon Peacock: Re: How to connect 2 FPGA?
92872: 05/12/08: Denaice: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause
92917: 05/12/09: Javier Castillo: Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause
92920: 05/12/09: Antti Lukats: Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause
92923: 05/12/09: Javier Castillo: Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause
92937: 05/12/09: Javier Castillo: Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause
92919: 05/12/09: Denaice: Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause
92924: 05/12/09: Denaice: Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause
92873: 05/12/08: Tim Verstraete: [ISE7.1] Equivalent register removal + register duplication + register balancing
92875: 05/12/08: jamesp: What graphical entry/documentation tools?
92909: 05/12/09: Brian: Re: What graphical entry/documentation tools?
92921: 05/12/09: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: What graphical entry/documentation tools?
92883: 05/12/08: fpgakid@gmail.com: Replace fast ethernet with VDSL2
92885: 05/12/09: Simon Peacock: Re: Replace fast ethernet with VDSL2
92889: 05/12/08: Dal: Re: Replace fast ethernet with VDSL2
92891: 05/12/08: jweissberg: Experiences with Actel ProAsic3E and toolchain?
92906: 05/12/09: Antti Lukats: Re: Experiences with Actel ProAsic3E and toolchain?
92910: 05/12/09: <vinogradov.slava@gmail.com>: Re: Experiences with Actel ProAsic3E and toolchain?
92952: 05/12/09: Hans: Re: Experiences with Actel ProAsic3E and toolchain?
92902: 05/12/08: bijoy: FPGA : MAP slice logic into BLOCK RAM
92905: 05/12/09: Antti Lukats: Re: FPGA : MAP slice logic into BLOCK RAM
92911: 05/12/09: bijoy: Re: FPGA : MAP slice logic into BLOCK RAM
93010: 05/12/11: bijoy: Re: FPGA : MAP slice logic into BLOCK RAM
92904: 05/12/09: Frank: How do I find the signature of PROM bitstreams?
92912: 05/12/09: Aurelian Lazarut: Re: How do I find the signature of PROM bitstreams?
92914: 05/12/09: backhus: ISE = Intelligent Synthesis Expectable :-)
92926: 05/12/09: Jan Decaluwe: Re: ISE = Intelligent Synthesis Expectable :-)
93012: 05/12/12: backhus: Re: ISE = Intelligent Synthesis Expectable :-)
93038: 05/12/12: Jan Decaluwe: Re: ISE = Intelligent Synthesis Expectable :-)
93058: 05/12/13: backhus: Re: ISE = Intelligent Synthesis Expectable :-)
93051: 05/12/13: backhus: Re: ISE = Intelligent Synthesis Expectable :-)
93027: 05/12/12: johnp: Re: ISE = Intelligent Synthesis Expectable :-)
92915: 05/12/09: Thomas Entner: No, not FIFOs again...
92933: 05/12/09: Peter Alfke: Re: No, not FIFOs again...
92935: 05/12/09: Thomas Entner: Re: No, not FIFOs again...
92938: 05/12/09: Antti Lukats: Re: No, not FIFOs again...
92941: 05/12/09: Thomas Entner: Re: No, not FIFOs again...
92948: 05/12/09: John_H: Re: No, not FIFOs again...
92973: 05/12/10: Thomas Entner: Re: No, not FIFOs again...
92972: 05/12/10: Thomas Entner: Re: No, not FIFOs again...
92981: 05/12/10: Ray Andraka: Re: No, not FIFOs again...
92949: 05/12/09: Peter Alfke: Re: No, not FIFOs again...
92985: 05/12/10: Peter Alfke: Re: No, not FIFOs again...
92925: 05/12/09: Roger: ISE purchase
92928: 05/12/09: Antti Lukats: Re: ISE purchase
92954: 05/12/09: Eric Smith: Re: ISE purchase
92959: 05/12/09: Roger: Re: ISE purchase
92962: 05/12/09: Eric Smith: Re: ISE purchase
92964: 05/12/09: Eric Smith: Re: ISE purchase
92936: 05/12/09: John Adair: Re: ISE purchase
92960: 05/12/09: <john.orlando@gmail.com>: Re: ISE purchase
92978: 05/12/10: Brian Drummond: Re: ISE purchase
92983: 05/12/10: Stephen Craven: Re: ISE purchase
92990: 05/12/11: John Adair: Re: ISE purchase
92927: 05/12/09: acetylcholinerd@gmail.com: XC4VFX12 -- availability?
92929: 05/12/09: Antti Lukats: Re: XC4VFX12 -- availability?
92931: 05/12/09: Austin Lesea: Re: XC4VFX12 -- availability?
92932: 05/12/09: Antti Lukats: Re: XC4VFX12 -- availability?
92942: 05/12/09: Finn S. Nielsen: Re: XC4VFX12 -- availability?
92956: 05/12/09: Peter Alfke: Re: XC4VFX12 -- availability?
92939: 05/12/09: Sylvain Munaut: Adding "super-LUTs" to FPGA, good idea ?
92940: 05/12/09: Antti Lukats: Re: Adding "super-LUTs" to FPGA, good idea ?
92946: 05/12/09: Sylvain Munaut: Re: Adding "super-LUTs" to FPGA, good idea ?
92947: 05/12/09: Antti Lukats: Re: Adding "super-LUTs" to FPGA, good idea ?
92961: 05/12/09: Ray Andraka: Re: Adding "super-LUTs" to FPGA, good idea ?
92963: 05/12/10: Sylvain Munaut: Re: Adding "super-LUTs" to FPGA, good idea ?
92966: 05/12/10: Ray Andraka: Re: Adding "super-LUTs" to FPGA, good idea ?
93014: 05/12/12: Morten Leikvoll: Re: Adding "super-LUTs" to FPGA, good idea ?
92980: 05/12/10: <juendme@yahoo.com>: Re: Adding "super-LUTs" to FPGA, good idea ?
92982: 05/12/10: Kolja Sulimma: Re: Adding "super-LUTs" to FPGA, good idea ?
93001: 05/12/11: Bob Perlman: Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?)
93007: 05/12/11: Ray Andraka: Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA,
93029: 05/12/12: John_H: Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?)
93002: 05/12/12: Jim Granville: Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA,
92986: 05/12/10: Peter Alfke: Re: Adding "super-LUTs" to FPGA, good idea ?
92998: 05/12/11: Brian Davis: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?)
92999: 05/12/11: Peter Alfke: Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?)
93000: 05/12/11: Brian Davis: Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?)
93003: 05/12/11: Brian Davis: Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?)
92943: 05/12/09: fad: Securing verilog source code
92951: 05/12/09: Hans: Re: Securing verilog source code
92977: 05/12/10: fad: Re: Securing verilog source code
92944: 05/12/09: Brad Smallridge: Xilinx ML40x VGA Documentation
92945: 05/12/09: Antti Lukats: Re: Xilinx ML40x VGA Documentation
92955: 05/12/10: Antti Lukats: First IP-core designed for and tested with Spartan-3E
92957: 05/12/09: Alan Nishioka: Re: First IP-core designed for and tested with Spartan-3E
92958: 05/12/10: Antti Lukats: Re: First IP-core designed for and tested with Spartan-3E
92965: 05/12/09: Alan Nishioka: Re: First IP-core designed for and tested with Spartan-3E
92968: 05/12/09: <Sudhir.Singh@email.com>: Problem with ChipScope Pro 6.2
92971: 05/12/10: Antti Lukats: Re: Problem with ChipScope Pro 6.2
92974: 05/12/10: <svasus@gmail.com>: Re: Problem with ChipScope Pro 6.2
93004: 05/12/12: Anup Raghavan: Re: Problem with ChipScope Pro 6.2
92970: 05/12/10: PeteS: Re: How to connect 2 FPGA?
92975: 05/12/10: <wv9557@yahoo.com>: Re: FPGA : MAP slice logic into BLOCK RAM
92988: 05/12/10: fahadislam2002: MMC(MultiMedia Card) interfacing with FPGA
92989: 05/12/11: Antti Lukats: Re: MMC(MultiMedia Card) interfacing with FPGA
92994: 05/12/11: Kryten: Re: MMC(MultiMedia Card) interfacing with FPGA
92995: 05/12/11: Antti Lukats: Re: MMC(MultiMedia Card) interfacing with FPGA
92996: 05/12/11: Kryten: Re: MMC(MultiMedia Card) interfacing with FPGA
93018: 05/12/12: Martin Schoeberl: Re: MMC(MultiMedia Card) interfacing with FPGA
93019: 05/12/12: Antti Lukats: Re: MMC(MultiMedia Card) interfacing with FPGA
93022: 05/12/12: Martin Schoeberl: Re: MMC(MultiMedia Card) interfacing with FPGA
93020: 05/12/12: Antti Lukats: Re: MMC(MultiMedia Card) interfacing with FPGA
93042: 05/12/12: fahadislam2002: re:MMC(MultiMedia Card) interfacing with FPGA
93050: 05/12/13: Antti Lukats: Re: re:MMC(MultiMedia Card) interfacing with FPGA
93082: 05/12/13: fahadislam2002: re:MMC(MultiMedia Card) interfacing with FPGA
92991: 05/12/11: Piotr Wyderski: About Spartan 3
92993: 05/12/11: Antti Lukats: Re: About Spartan 3
93005: 05/12/12: Frank: When read back bitstreams from Xilinx PROMs, how to verify?
93006: 05/12/11: <jaxato@gmail.com>: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93013: 05/12/11: Thomas Stanka: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93025: 05/12/12: Austin Lesea: Re: Hello PPl, is there a way of locking a design (NGC) to a particular
93061: 05/12/13: I. Ulises Hernandez: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93062: 05/12/13: Antti Lukats: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93071: 05/12/13: Ray Andraka: Re: Hello PPl, is there a way of locking a design (NGC) to a particular
93077: 05/12/13: Antti Lukats: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93098: 05/12/13: Ray Andraka: Re: Hello PPl, is there a way of locking a design (NGC) to a particular
93144: 05/12/14: Ray Andraka: Re: Hello PPl, is there a way of locking a design (NGC) to a particular
93146: 05/12/14: Antti Lukats: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93150: 05/12/14: Ray Andraka: Re: Hello PPl, is there a way of locking a design (NGC) to a particular
93155: 05/12/14: Antti Lukats: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93151: 05/12/14: Ray Andraka: Re: Hello PPl, is there a way of locking a design (NGC) to a particular
93161: 05/12/15: Symon: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93169: 05/12/15: Hal Murray: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93173: 05/12/15: I. Ulises Hernandez: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93047: 05/12/12: <jaxato@gmail.com>: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93136: 05/12/14: JustJohn: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93147: 05/12/14: <jaxato@gmail.com>: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93164: 05/12/15: Jim Granville: Re: Hello PPl, is there a way of locking a design (NGC) to a particular
93202: 05/12/15: Symon: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93233: 05/12/16: David Brown: Re: Hello PPl, is there a way of locking a design (NGC) to a particular
93171: 05/12/15: henk: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93190: 05/12/15: <jaxato@gmail.com>: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93207: 05/12/15: JustJohn: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93208: 05/12/15: Antti Lukats: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93008: 05/12/11: <lioupayphone@gmail.com>: who can help me? i want to know the bitsream format of Virtex-II
93009: 05/12/12: Frank: Re: who can help me? i want to know the bitsream format of Virtex-II
93052: 05/12/13: Javier Castillo: Re: who can help me? i want to know the bitsream format of Virtex-II
93073: 05/12/13: Ray Andraka: Re: who can help me? i want to know the bitsream format of Virtex-II
93101: 05/12/13: Symon: Re: who can help me? i want to know the bitsream format of Virtex-II
93109: 05/12/13: Ray Andraka: Re: who can help me? i want to know the bitsream format of Virtex-II
93054: 05/12/13: Frank: Re: who can help me? i want to know the bitsream format of Virtex-II
93087: 05/12/13: Antti Lukats: Re: who can help me? i want to know the bitsream format of Virtex-II
93026: 05/12/12: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: who can help me? i want to know the bitsream format of Virtex-II
93015: 05/12/12: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Question about Xilinx UCF files
93016: 05/12/12: Antti Lukats: Re: Question about Xilinx UCF files
93023: 05/12/12: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: Question about Xilinx UCF files
93017: 05/12/12: Christoph Lauer: modelsim settings in edk
93021: 05/12/12: Christoph Lauer: Re: modelsim settings in edk
93024: 05/12/12: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: modelsim settings in edk
93028: 05/12/12: Richard: FreeRTOS.org has support for Microblaze
93030: 05/12/12: calaf: FPGA in industrial environment
93031: 05/12/12: Slurp: Re: FPGA in industrial environment
93032: 05/12/12: <amyler@eircom.net>: Re: FPGA in industrial environment
93035: 05/12/12: Austin Lesea: Re: FPGA in industrial environment
93037: 05/12/12: Balogh Viktor: Re: FPGA in industrial environment
93033: 05/12/12: HB: 3/2 with virtex 300
93034: 05/12/12: Symon: Re: 3/2 with virtex 300
93039: 05/12/12: Austin Lesea: Re: 3/2 with virtex 300
93040: 05/12/13: Symon: Re: 3/2 with virtex 300
93041: 05/12/12: Austin Lesea: Re: 3/2 with virtex 300
93091: 05/12/13: HB: Re: 3/2 with virtex 300
93097: 05/12/13: Symon: Re: 3/2 with virtex 300
93100: 05/12/13: Ray Andraka: Re: 3/2 with virtex 300
93137: 05/12/14: HB: Re: 3/2 with virtex 300
93142: 05/12/14: Ray Andraka: Re: 3/2 with virtex 300
93154: 05/12/14: Symon: Re: 3/2 with virtex 300
93036: 05/12/12: Gabor: Re: 3/2 with virtex 300
93043: 05/12/12: Chloe: Xilinx FPGA - Wrongly Translated Inputs
93048: 05/12/13: Zara: Re: Xilinx FPGA - Wrongly Translated Inputs
93063: 05/12/13: Zara: Re: Xilinx FPGA - Wrongly Translated Inputs
93049: 05/12/12: Chloe: Re: Xilinx FPGA - Wrongly Translated Inputs
93044: 05/12/12: hwguy: Xilinx for PDP
93045: 05/12/12: Ray Andraka: Re: Xilinx for PDP
93046: 05/12/12: Binary: Which decides my design's max frequency?
93086: 05/12/13: Mike Treseler: Re: Which decides my design's max frequency?
93053: 05/12/13: Frank: How can I surpress noise in an ADC board?
93055: 05/12/13: David L. Jones: Re: How can I surpress noise in an ADC board?
93057: 05/12/13: Gregory C. Read: Re: How can I surpress noise in an ADC board?
93079: 05/12/13: PeteS: Re: How can I surpress noise in an ADC board?
93083: 05/12/13: John Herman: Re: How can I surpress noise in an ADC board?
93108: 05/12/14: Frank: Re: How can I surpress noise in an ADC board?
93119: 05/12/14: Mike Yarwood: Re: How can I surpress noise in an ADC board?
93080: 05/12/13: Jerry Avins: Re: How can I surpress noise in an ADC board?
93056: 05/12/13: Antti Lukats: mixed signal flash FPGAs launched!
93059: 05/12/13: Jim Granville: Re: mixed signal flash FPGAs launched!
93066: 05/12/13: Antti Lukats: Re: mixed signal flash FPGAs launched!
93076: 05/12/13: Jan Panteltje: Re: mixed signal flash FPGAs launched!
93075: 05/12/13: Jan Panteltje: Re: mixed signal flash FPGAs launched!
93060: 05/12/13: Monica: xilinx constraint
93064: 05/12/13: <amyler@eircom.net>: Re: xilinx constraint
93074: 05/12/13: Ray Andraka: Re: xilinx constraint
93103: 05/12/13: Jon Elson: Re: xilinx constraint
93065: 05/12/13: Monica: Re: xilinx constraint
93068: 05/12/13: <amyler@eircom.net>: Re: xilinx constraint
93069: 05/12/13: Monica: Re: xilinx constraint
93072: 05/12/13: <amyler@eircom.net>: Re: xilinx constraint
93133: 05/12/14: Monica: Re: xilinx constraint
93067: 05/12/13: kl31n: Xilinx floating point core 1.0
93081: 05/12/13: mk: Re: Xilinx floating point core 1.0
93122: 05/12/14: kl31n: Re: Xilinx floating point core 1.0
93084: 05/12/13: Mike Treseler: Re: Xilinx floating point core 1.0
93124: 05/12/14: kl31n: Re: Xilinx floating point core 1.0
93193: 05/12/15: Mike Treseler: Re: Xilinx floating point core 1.0
93127: 05/12/14: Robin Bruce: Re: Xilinx floating point core 1.0
93153: 05/12/14: rhnlogic: Re: Xilinx floating point core 1.0
93248: 05/12/16: Ben Jones: Re: Xilinx floating point core 1.0
93085: 05/12/13: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Question about Progamming File generation report
93125: 05/12/14: Gabor: Re: Question about Progamming File generation report
93134: 05/12/14: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: Question about Progamming File generation report
93088: 05/12/13: John: fiddling directly with LUT bits on Xilinx
93089: 05/12/13: John Adair: Re: fiddling directly with LUT bits on Xilinx
93090: 05/12/13: Antti Lukats: Re: fiddling directly with LUT bits on Xilinx
93099: 05/12/13: John_H: Re: fiddling directly with LUT bits on Xilinx
93092: 05/12/13: Bill Giovino: Future of Microchip Development Tools?
93095: 05/12/14: Jim Granville: Re: Future of Microchip Development Tools?
93096: 05/12/13: Bill Giovino: Re: Future of Microchip Development Tools?
93107: 05/12/13: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: Future of Microchip Development Tools?
93570: 05/12/24: Ken Scharf: Re: Future of Microchip Development Tools?
93093: 05/12/13: avishay: Frequency dependent SOPC builder components
93102: 05/12/14: Mark McDougall: Re: Frequency dependent SOPC builder components
93159: 05/12/15: Mark McDougall: Re: Frequency dependent SOPC builder components
93111: 05/12/13: avishay: Re: Frequency dependent SOPC builder components
93104: 05/12/14: Jeremy Stringer: SGMII Interface
93130: 05/12/14: PeteS: Re: SGMII Interface
93148: 05/12/15: Jeremy Stringer: Re: SGMII Interface
93105: 05/12/13: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: ISE WebPack 8.1i
93112: 05/12/14: backhus: Re: ISE WebPack 8.1i
93115: 05/12/14: Antti Lukats: Re: ISE WebPack 8.1i
93116: 05/12/13: Eric Smith: Re: ISE WebPack 8.1i
93117: 05/12/14: Antti Lukats: Re: ISE WebPack 8.1i
93118: 05/12/14: Stephane: Re: ISE WebPack 8.1i
93114: 05/12/13: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: ISE WebPack 8.1i
93121: 05/12/14: <abgoyal@gmail.com>: Re: ISE WebPack 8.1i
93106: 05/12/13: ABS: J Tag Protocol
93113: 05/12/14: Antti Lukats: Re: J Tag Protocol
93158: 05/12/14: Neil Glenn Jacobson: Re: J Tag Protocol
93168: 05/12/15: Antti Lukats: Re: J Tag Protocol
93129: 05/12/14: PeteS: Re: J Tag Protocol
93167: 05/12/15: ABS: Re: J Tag Protocol
93120: 05/12/14: Frank: Can ISE 4.2 program Virtex 2 6000K devices?
93123: 05/12/14: Gabor: Re: Can ISE 4.2 program Virtex 2 6000K devices?
93166: 05/12/15: Frank: Re: Can ISE 4.2 program Virtex 2 6000K devices?
93128: 05/12/14: ALuPin@web.de: Simulating CRC32 according to IEEE Std. 802.3
93217: 05/12/15: <Sudhir.Singh@email.com>: Re: Simulating CRC32 according to IEEE Std. 802.3
93234: 05/12/16: ALuPin@web.de: Re: Simulating CRC32 according to IEEE Std. 802.3
93236: 05/12/16: <allanherriman@hotmail.com>: Re: Simulating CRC32 according to IEEE Std. 802.3
93238: 05/12/16: Reiner Huober: Re: Simulating CRC32 according to IEEE Std. 802.3
93239: 05/12/16: ALuPin@web.de: Re: Simulating CRC32 according to IEEE Std. 802.3
93240: 05/12/16: ALuPin@web.de: Re: Simulating CRC32 according to IEEE Std. 802.3
93131: 05/12/14: Daveb: Mission critical & low core voltages
93132: 05/12/14: Peter Alfke: Re: Mission critical & low core voltages
93172: 05/12/15: Aurelian Lazarut: Re: Mission critical & low core voltages
93174: 05/12/15: David Belohrad: Re: Mission critical & low core voltages
93195: 05/12/15: Austin Lesea: Re: Mission critical & low core voltages
93135: 05/12/14: Daveb: Re: Mission critical & low core voltages
93138: 05/12/14: Peter Alfke: Re: Mission critical & low core voltages
93139: 05/12/14: Daveb: Re: Mission critical & low core voltages
93197: 05/12/15: Austin Lesea: Re: Mission critical & low core voltages
93140: 05/12/14: Nitesh: FPGA-pci communication
93141: 05/12/14: John Adair: Re: FPGA-pci communication
93221: 05/12/16: Jerome: Re: FPGA-pci communication
93266: 05/12/17: Jerome: Re: FPGA-pci communication
93206: 05/12/15: Nitesh: Re: FPGA-pci communication
93263: 05/12/16: Nitesh: Re: FPGA-pci communication
93279: 05/12/18: Nitesh: Re: FPGA-pci communication
93280: 05/12/18: <john.orlando@gmail.com>: Re: FPGA-pci communication
93478: 05/12/22: Nitesh: Re: FPGA-pci communication
94039: 06/01/04: Nitesh: Re: FPGA-pci communication
93145: 05/12/14: jjlindula@hotmail.com: Incremental Compilation in Quartus 5.1?
93383: 05/12/21: Banetele news: Re: Incremental Compilation in Quartus 5.1?
93149: 05/12/14: jeffcannon: Custom data rates with Virtex 2 Pro-X MGTs
93152: 05/12/14: Shantha: Error in MAP (Xlinx Project navigator)
93156: 05/12/14: Ramakrishnan: Xst Error
93157: 05/12/14: Paul Hartke: Re: Xst Error
93160: 05/12/14: fpgabuilder: consensus theorem and power
93163: 05/12/14: JustJohn: Re: consensus theorem and power
93420: 05/12/21: fpgabuilder: Re: consensus theorem and power
93427: 05/12/21: Peter Alfke: Re: consensus theorem and power
93165: 05/12/14: AAA: D FLIP -FLOP
93170: 05/12/15: AAA: Re: D FLIP -FLOP
93183: 05/12/15: DerekSimmons@FrontierNet.net: Re: D FLIP -FLOP
93175: 05/12/15: john: How to simulate a .NMC macro?
93176: 05/12/15: Antti Lukats: Re: How to simulate a .NMC macro?
93180: 05/12/15: john: Re: How to simulate a .NMC macro?
93181: 05/12/15: Antti Lukats: Re: How to simulate a .NMC macro?
93177: 05/12/15: al99999: Digilent SRAM Controller
93179: 05/12/15: Antti Lukats: Re: Digilent SRAM Controller
93187: 05/12/15: Antti Lukats: Re: Digilent SRAM Controller
93185: 05/12/15: al99999: Re: Digilent SRAM Controller
93188: 05/12/15: Leon: Re: Digilent SRAM Controller
93191: 05/12/15: al99999: Re: Digilent SRAM Controller
93213: 05/12/15: Brian Davis: Re: Digilent SRAM Controller
93178: 05/12/15: <singhal.prateek@gmail.com>: Parallel Cable III is not detected
93184: 05/12/15: erikdm: Re: Parallel Cable III is not detected
93186: 05/12/15: erikdm: Re: Parallel Cable III is not detected
93199: 05/12/15: Prateek Singhal: Re: Parallel Cable III is not detected
93210: 05/12/15: nshrestha: Re: Parallel Cable III is not detected
93211: 05/12/16: Jerzy Gbur: Re: Parallel Cable III is not detected
93257: 05/12/16: Prateek Singhal: Re: Parallel Cable III is not detected
93182: 05/12/15: <debashish.hota@gmail.com>: Xilinx DCM Shuts down at 75degree centigrade
93189: 05/12/15: PeteS: Re: Xilinx DCM Shuts down at 75degree centigrade
93198: 05/12/15: Austin Lesea: Re: Xilinx DCM Shuts down at 75degree centigrade
93201: 05/12/15: Symon: Re: Xilinx DCM Shuts down at 75degree centigrade
93203: 05/12/15: Peter Alfke: Re: Xilinx DCM Shuts down at 75degree centigrade
93235: 05/12/16: PeteS: Re: Xilinx DCM Shuts down at 75degree centigrade
93194: 05/12/15: Melanie Nasic: Xilinx' encrypted HPICE models in PSPICE
93196: 05/12/15: Jim Thompson: Re: Xilinx' encrypted HPICE models in PSPICE
93200: 05/12/15: Austin Lesea: Re: Xilinx' encrypted HPICE models in PSPICE
93204: 05/12/15: Charlie Edmondson: Re: Xilinx' encrypted HPICE models in PSPICE
93205: 05/12/15: simon.stockton@baesystems.com: Scrambled Net Names!
93212: 05/12/15: Symon: Re: Scrambled Net Names!
93214: 05/12/15: Davy: Inverter Chain Synthesis Problem
93215: 05/12/15: Mike Treseler: Re: Inverter Chain Synthesis Problem
93218: 05/12/16: John_H: Re: Inverter Chain Synthesis Problem
93225: 05/12/16: backhus: Re: Inverter Chain Synthesis Problem
93241: 05/12/16: John_H: Re: Inverter Chain Synthesis Problem
93216: 05/12/15: Davy: Re: Inverter Chain Synthesis Problem
93219: 05/12/15: keyrun: Re: Inverter Chain Synthesis Problem
93220: 05/12/15: Davy: Re: Inverter Chain Synthesis Problem
93247: 05/12/16: Jason Zheng: Re: Inverter Chain Synthesis Problem
93288: 05/12/19: John Penton: Re: Inverter Chain Synthesis Problem
93289: 05/12/19: Javier Castillo: Re: Inverter Chain Synthesis Problem
93222: 05/12/16: Alex Gibson: Avnet hav2 s3e starter kit?
93223: 05/12/16: Antti Lukats: Re: Avnet hav2 s3e starter kit?
93224: 05/12/16: Antti Lukats: Re: Avnet hav2 s3e starter kit?
93242: 05/12/16: John_H: Re: Avnet hav2 s3e starter kit?
93243: 05/12/16: Antti Lukats: Re: Avnet hav2 s3e starter kit?
93265: 05/12/17: Glenn Jones: Re: Avnet hav2 s3e starter kit?
93253: 05/12/16: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Avnet hav2 s3e starter kit?
93255: 05/12/16: Antti Lukats: Re: Avnet hav2 s3e starter kit?
93260: 05/12/16: John_H: Re: Avnet hav2 s3e starter kit?
93261: 05/12/16: Antti Lukats: Re: Avnet hav2 s3e starter kit?
93275: 05/12/19: Alex Gibson: Re: Avnet hav2 s3e starter kit?
93254: 05/12/16: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Avnet hav2 s3e starter kit?
93259: 05/12/16: <jaxato@gmail.com>: Re: Avnet hav2 s3e starter kit?
93226: 05/12/15: Bart: Interfacing externally clocked data to an FPGA (Spartan 3)
93228: 05/12/16: Antti Lukats: Re: Interfacing externally clocked data to an FPGA (Spartan 3)
93249: 05/12/16: Kolja Sulimma: Re: Interfacing externally clocked data to an FPGA (Spartan 3)
93246: 05/12/16: johnp: Re: Interfacing externally clocked data to an FPGA (Spartan 3)
93256: 05/12/16: Bart: Re: Interfacing externally clocked data to an FPGA (Spartan 3)
93264: 05/12/16: johnp: Re: Interfacing externally clocked data to an FPGA (Spartan 3)
93519: 05/12/23: <wtxwtx@gmail.com>: Re: Interfacing externally clocked data to an FPGA (Spartan 3)
93227: 05/12/15: Eric Smith: ISE 8.1i on Fedora Core 4 (64-bit)
93230: 05/12/15: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: ISE 8.1i on Fedora Core 4 (64-bit)
93231: 05/12/16: Eric Smith: Re: ISE 8.1i on Fedora Core 4 (64-bit)
93232: 05/12/16: Antti Lukats: Re: ISE 8.1i on Fedora Core 4 (64-bit)
93229: 05/12/15: <chengwelsion@gmail.com>: Get Start for XtremeDSP Developement Board -IV
93281: 05/12/18: Scott Bekker: Re: Get Start for XtremeDSP Developement Board -IV
93237: 05/12/16: burn.sir@spam-me-not-gmail.com: verification tools?
93272: 05/12/17: Tom: Re: verification tools?
93244: 05/12/16: Brian Davis: Re: Avnet hav2 s3e starter kit?
93245: 05/12/16: acetylcholinerd@gmail.com: How to simulate Virtex-4 PPC, MAC, etc. ?
93258: 05/12/16: Antti Lukats: Re: How to simulate Virtex-4 PPC, MAC, etc. ?
93250: 05/12/16: apurvewarrior@gmail.com: FPGA Implementation Of Real Time Data Compression
93251: 05/12/16: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Avnet hav2 s3e starter kit?
93252: 05/12/16: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Avnet hav2 s3e starter kit?
93262: 05/12/16: <turbo.satan@gmail.com>: Looking for QuickLogic DeskFab programmer, new or used
93267: 05/12/17: Markus Knauss: Altera based Video development board
93274: 05/12/18: Karl: Re: Altera based Video development board
93277: 05/12/18: Markus Knauss: Re: Altera based Video development board
93278: 05/12/18: Jan Panteltje: Re: Altera based Video development board
93511: 05/12/23: SDL: Re: Altera based Video development board
93268: 05/12/17: xavier.tastet@gmail.com: rs232 and picoblaze :)
93269: 05/12/17: Adrian Knoth: Re: rs232 and picoblaze :)
93273: 05/12/18: Antti Lukats: Re: rs232 and picoblaze :)
93270: 05/12/17: <linq936@hotmail.com>: How to use ISE FPGA Editor to compare timing path easily?
93276: 05/12/18: Duane Clark: Re: How to use ISE FPGA Editor to compare timing path easily?
93282: 05/12/19: Peter Rauschert: Powering unused MGTs in XC4VFX20CES2
93283: 05/12/19: Peter Rauschert: Re: Powering unused MGTs in XC4VFX20CES2
93296: 05/12/19: Ed McGettigan: Re: Powering unused MGTs in XC4VFX20CES2
93291: 05/12/19: Austin Lesea: Re: Powering unused MGTs in XC4VFX20CES2
93295: 05/12/19: Ed McGettigan: Re: Powering unused MGTs in XC4VFX20CES2
93284: 05/12/19: <lioupayphone@gmail.com>: where can i get a release copy of ISE 8i?
93285: 05/12/19: Jon Beniston: Re: where can i get a release copy of ISE 8i?
93287: 05/12/19: Eli Hughes: Re: where can i get a release copy of ISE 8i?
93286: 05/12/19: Thomas: Problem with downloading elf file to ML403 using XMD
93329: 05/12/20: Florian: Re: Problem with downloading elf file to ML403 using XMD
93290: 05/12/19: ALuPin@web.de: Differential Pin Pairs in Lattice EC FPGAs
93292: 05/12/19: Antti Lukats: Re: Differential Pin Pairs in Lattice EC FPGAs
93327: 05/12/20: Antti Lukats: Re: Differential Pin Pairs in Lattice EC FPGAs
93325: 05/12/19: ALuPin@web.de: Re: Differential Pin Pairs in Lattice EC FPGAs
93331: 05/12/20: ALuPin@web.de: Re: Differential Pin Pairs in Lattice EC FPGAs
93294: 05/12/19: rmanand: Virtex II Pro XC2VP100
93316: 05/12/19: Nitro: Re: Virtex II Pro XC2VP100
93330: 05/12/20: rmanand: Re: Virtex II Pro XC2VP100
93359: 05/12/20: Antti Lukats: Re: Virtex II Pro XC2VP100
93363: 05/12/20: Duane Clark: Re: Virtex II Pro XC2VP100
93377: 05/12/20: rmanand: Re: Virtex II Pro XC2VP100
93378: 05/12/20: rmanand: Re: Virtex II Pro XC2VP100
93298: 05/12/19: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Virtex-4 Startup
93300: 05/12/19: Peter Ryser: Re: Virtex-4 Startup
93312: 05/12/19: Vic Vadi: Re: Virtex-4 Startup
93321: 05/12/19: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: Virtex-4 Startup
93304: 05/12/19: Philip Pemberton: Mixing XC9500 and XC9500XL, also small qty suppliers
93306: 05/12/19: M.Randelzhofer: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
93307: 05/12/19: Philip Pemberton: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
93308: 05/12/20: Mika Leinonen: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
93311: 05/12/20: Philip Pemberton: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
93309: 05/12/20: M.Randelzhofer: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
93356: 05/12/20: John Adair: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
93473: 05/12/22: Philip Pemberton: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
93310: 05/12/19: Reza Naima: More beginner's verilog questions
93315: 05/12/20: Rob: Re: More beginner's verilog questions
93376: 05/12/21: Rob: Re: More beginner's verilog questions
93319: 05/12/19: Art Stamness: Re: More beginner's verilog questions
93367: 05/12/20: Mike Treseler: Re: More beginner's verilog questions
93395: 05/12/21: Jason Rosinski: Re: More beginner's verilog questions
93412: 05/12/21: Ray Andraka: Re: More beginner's verilog questions
93422: 05/12/21: Eric Smith: Re: More beginner's verilog questions
93418: 05/12/21: Jason Rosinski: Re: More beginner's verilog questions
93434: 05/12/22: Rob: Re: More beginner's verilog questions
93466: 05/12/22: Ray Andraka: Re: More beginner's verilog questions
93522: 05/12/23: Hal Murray: Re: More beginner's verilog questions
93585: 05/12/25: Bob Perlman: Re: More beginner's verilog questions
93586: 05/12/25: Bob Perlman: Re: More beginner's verilog questions
93592: 05/12/25: Jan Decaluwe: Re: More beginner's verilog questions
93649: 05/12/27: Chris F Clark: Re: More beginner's verilog questions
93462: 05/12/22: Jan Decaluwe: Re: More beginner's verilog questions
93437: 05/12/21: Ray Andraka: Re: More beginner's verilog questions
93461: 05/12/22: Chris F Clark: Re: More beginner's verilog questions
93401: 05/12/21: Chris F Clark: Re: More beginner's verilog questions
93323: 05/12/19: Reza Naima: Re: More beginner's verilog questions
93326: 05/12/19: Reza Naima: Re: More beginner's verilog questions
93347: 05/12/20: johnp: Re: More beginner's verilog questions
93354: 05/12/20: Andy Peters: Re: More beginner's verilog questions
93364: 05/12/20: Reza Naima: Re: More beginner's verilog questions
93365: 05/12/20: Reza Naima: Re: More beginner's verilog questions
93375: 05/12/20: Reza Naima: Re: More beginner's verilog questions
93379: 05/12/20: santosh: Re: More beginner's verilog questions
93384: 05/12/21: Reza Naima: Re: More beginner's verilog questions
93400: 05/12/21: johnp: Re: More beginner's verilog questions
93403: 05/12/21: Andy Peters: Re: More beginner's verilog questions
93404: 05/12/21: Andy Peters: Re: More beginner's verilog questions
93416: 05/12/21: Reza Naima: Re: More beginner's verilog questions
93423: 05/12/21: Reza Naima: Re: More beginner's verilog questions
93426: 05/12/21: johnp: Re: More beginner's verilog questions
93433: 05/12/21: Reza Naima: Re: More beginner's verilog questions
93449: 05/12/22: Reza Naima: Re: More beginner's verilog questions
93450: 05/12/22: Reza Naima: Re: More beginner's verilog questions
93457: 05/12/22: <mottoblatto@yahoo.com>: Re: More beginner's verilog questions
93458: 05/12/22: <mottoblatto@yahoo.com>: Re: More beginner's verilog questions
93463: 05/12/22: <mottoblatto@yahoo.com>: Re: More beginner's verilog questions
93483: 05/12/22: Andy Peters: Re: More beginner's verilog questions
93484: 05/12/22: Andy Peters: Re: More beginner's verilog questions
93485: 05/12/22: Andy Peters: Re: More beginner's verilog questions
93576: 05/12/25: Reza Naima: Re: More beginner's verilog questions
93582: 05/12/25: <burn.sir@gmail.com>: Re: More beginner's verilog questions
93313: 05/12/19: JustJohn: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93320: 05/12/19: <mr_reznat@yahoo.com>: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93348: 05/12/20: johnp: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93621: 05/12/26: Tim Wescott: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar
93349: 05/12/20: John_H: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93352: 05/12/20: Pete Fraser: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93360: 05/12/20: Mike Treseler: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar
93361: 05/12/20: Ray Andraka: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar
93368: 05/12/20: <langwadt@ieee.org>: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93369: 05/12/20: JustJohn: Re: Patents and (possible) Plagiarism, an open apology
93371: 05/12/20: Jon Elson: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar
93372: 05/12/21: Jim Granville: Re: Patents and (possible) Plagiarism, Anyone ever been in a similarsituation?
93429: 05/12/21: Jon Elson: Re: Patents and (possible) Plagiarism, Anyone ever been in a similarsituation?
93387: 05/12/21: <wtxwtx@gmail.com>: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93388: 05/12/21: <wtxwtx@gmail.com>: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93389: 05/12/21: <wtxwtx@gmail.com>: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93399: 05/12/21: Kolja Sulimma: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar
93607: 05/12/26: <mr_reznat@yahoo.com>: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93609: 05/12/26: <wtxwtx@gmail.com>: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93610: 05/12/26: <mr_reznat@yahoo.com>: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93616: 05/12/26: <wtxwtx@gmail.com>: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93619: 05/12/26: Peter Alfke: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93620: 05/12/26: <wtxwtx@gmail.com>: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93622: 05/12/26: <wtxwtx@gmail.com>: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93623: 05/12/26: Peter Alfke: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93625: 05/12/26: <mr_reznat@yahoo.com>: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93634: 05/12/27: <wtxwtx@gmail.com>: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93700: 05/12/28: <soar2morrow@yahoo.com>: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93317: 05/12/19: Eric: software application on the virtex-ii pro
93342: 05/12/20: clemens fischer: Re: software application on the virtex-ii pro
93358: 05/12/20: Peter Ryser: Re: software application on the virtex-ii pro
93370: 05/12/20: Peter Ryser: Re: software application on the virtex-ii pro
93318: 05/12/19: <lioupayphone@gmail.com>: help: how to use ICAP of Virtex-II ?
93322: 05/12/19: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: help: how to use ICAP of Virtex-II ?
93328: 05/12/19: Raymond: ISE project with a Microblaze submodule: timing constrains warning
93455: 05/12/22: Steve: Re: ISE project with a Microblaze submodule: timing constrains warning
93332: 05/12/20: Melanie Nasic: Virtex-4 clocking
93333: 05/12/20: Antti Lukats: Re: Virtex-4 clocking
93334: 05/12/20: Bob: Re: Virtex-4 clocking
93343: 05/12/20: Austin Lesea: Re: Virtex-4 clocking
93344: 05/12/20: Antti Lukats: Re: Virtex-4 clocking
93345: 05/12/20: Melanie Nasic: Re: Virtex-4 clocking
93335: 05/12/20: Melanie Nasic: real-time compression algorithms on fpga
93336: 05/12/20: DerekSimmons@FrontierNet.net: Re: real-time compression algorithms on fpga
93353: 05/12/20: Pete Fraser: Re: real-time compression algorithms on fpga
93337: 05/12/20: Stefan Rybacki: Re: real-time compression algorithms on fpga
93338: 05/12/20: =?iso-8859-1?q?Dag-Erling_Sm=F8rgrav?=: Re: real-time compression algorithms on fpga
93339: 05/12/20: Dave: Re: real-time compression algorithms on fpga
93340: 05/12/20: Pete Fraser: Re: real-time compression algorithms on fpga
93341: 05/12/20: Melanie Nasic: Re: real-time compression algorithms on fpga
93350: 05/12/20: Pete Fraser: Re: real-time compression algorithms on fpga
93456: 05/12/22: <news@rtrussell.co.uk>: Re: real-time compression algorithms on fpga
93825: 06/01/01: Thomas Rudloff: Re: real-time compression algorithms on fpga
93346: 05/12/20: Newman: Re: real-time compression algorithms on fpga
93351: 05/12/20: Brannon: Re: real-time compression algorithms on fpga
93451: 05/12/22: Nils: Re: real-time compression algorithms on fpga
93454: 05/12/22: John B: Re: real-time compression algorithms on fpga
93481: 05/12/22: Jerry Coffin: Re: real-time compression algorithms on fpga
93488: 05/12/22: Jerry Coffin: Re: real-time compression algorithms on fpga
93498: 05/12/23: Melanie Nasic: Re: real-time compression algorithms on fpga
93491: 05/12/22: Jerry Coffin: Re: real-time compression algorithms on fpga
93525: 05/12/23: Jerry Coffin: Re: real-time compression algorithms on fpga
93716: 05/12/29: =?ISO-8859-1?Q?Michael_Sch=F6berl?=: Re: real-time compression algorithms on fpga
93357: 05/12/20: marco: Place and Route Algorithms
93362: 05/12/20: Peter Alfke: Re: Place and Route Algorithms
93380: 05/12/21: Stephane: Re: Place and Route Algorithms
93396: 05/12/21: Kolja Sulimma: Re: Place and Route Algorithms
93415: 05/12/21: Kolja Sulimma: Re: Place and Route Algorithms
93417: 05/12/22: Jim Granville: Re: Place and Route Algorithms
93419: 05/12/21: Austin Lesea: Re: Place and Route Algorithms: where's the fat?
93425: 05/12/21: John_H: Re: Place and Route Algorithms: where's the fat?
93431: 05/12/21: Phil Hays: Re: Place and Route Algorithms: where's the fat?
93438: 05/12/22: John_H: Re: Place and Route Algorithms: where's the fat?
93490: 05/12/23: Jeremy Stringer: Re: Place and Route Algorithms: where's the fat?
93436: 05/12/21: Ray Andraka: Re: Place and Route Algorithms: where's the fat?
93440: 05/12/22: Jim Granville: Re: Place and Route Algorithms: where's the fat?
93460: 05/12/22: Austin Lesea: Re: Place and Route Algorithms: where's the fat?
93480: 05/12/23: Jim Granville: Re: Place and Route Algorithms: where's the fat?
93470: 05/12/22: Ray Andraka: Re: Place and Route Algorithms: where's the fat?
93479: 05/12/23: Jim Granville: Re: Place and Route Algorithms: where's the fat?
93459: 05/12/22: Austin Lesea: Re: Place and Route Algorithms: where's the fat?
93472: 05/12/22: Ray Andraka: Re: Place and Route Algorithms: where's the fat?
93477: 05/12/22: Austin Lesea: Re: Place and Route Algorithms: where's the fat? here's some beef?
93366: 05/12/20: Mike Treseler: Re: Place and Route Algorithms
93407: 05/12/21: marco: Re: Place and Route Algorithms
93413: 05/12/21: Peter Alfke: Re: Place and Route Algorithms
93424: 05/12/21: dp: Re: Place and Route Algorithms: where's the fat?
93486: 05/12/22: Andy Peters: Re: Place and Route Algorithms: where's the fat?
93487: 05/12/22: Andy Peters: Re: Place and Route Algorithms: where's the fat?
93489: 05/12/22: dp: Re: Place and Route Algorithms: where's the fat?
93494: 05/12/22: Marc Randolph: Re: Place and Route Algorithms: where's the fat?
93647: 05/12/27: Piotr Wyderski: Re: Place and Route Algorithms
93373: 05/12/20: superman321: Xilinix Modular Flow
93598: 05/12/25: Alan: Re: Xilinix Modular Flow
93728: 05/12/29: superman321: Re: Xilinix Modular Flow
93959: 06/01/03: Alan: Re: Xilinix Modular Flow
93374: 05/12/20: Andrew Ward: Interactive Logic
93381: 05/12/21: Raymond: exception (0xe06d7363) when creating a MicroBlaze from the ISE environment
93382: 05/12/21: AAA: HOW IS GREY BOX VERIFICATION DONE
93385: 05/12/21: bjzhangwn: Is there anyboay work on the subject with the embeded system in the fpga?
93386: 05/12/21: Antti Lukats: Re: Is there anyboay work on the subject with the embeded system in the fpga?
93393: 05/12/21: Antti Lukats: Re: Is there anyboay work on the subject with the embeded system in the fpga?
93397: 05/12/21: Antti Lukats: Re: Is there anyboay work on the subject with the embeded system in the fpga?
93430: 05/12/22: Jeremy Stringer: Re: Is there anyboay work on the subject with the embeded system
93442: 05/12/22: Antti Lukats: Re: Is there anyboay work on the subject with the embeded system in the fpga?
93391: 05/12/21: bjzhangwn: Re: Is there anyboay work on the subject with the embeded system in the fpga?
93394: 05/12/21: bjzhangwn: Re: Is there anyboay work on the subject with the embeded system in the fpga?
93392: 05/12/21: I. Ulises Hernandez: FPGA DDR controller - CKE signal... do I need a pull down?
93518: 05/12/23: <wtxwtx@gmail.com>: Re: FPGA DDR controller - CKE signal... do I need a pull down?
93398: 05/12/21: bjzhangwn: Can anyone have the evaluation board from xilinx and altera?
93405: 05/12/21: Andy Peters: Re: Can anyone have the evaluation board from xilinx and altera?
93402: 05/12/21: Weng Tianxiang: Re: Data Decoding at 10 Gbit/s
93406: 05/12/21: Morten Leikvoll: 8 in clock mux
93408: 05/12/21: Renniks: Spartan 3 Digilent Board Expansion Connectors
93411: 05/12/21: Antti Lukats: Re: Spartan 3 Digilent Board Expansion Connectors
93409: 05/12/21: Telenochek: Buffers/Line drivers for 6pin JTAG?
93414: 05/12/21: John Adair: Re: Buffers/Line drivers for 6pin JTAG?
93421: 05/12/21: Telenochek: Re: Buffers/Line drivers for 6pin JTAG?
93410: 05/12/21: Anshat: lpc922
93428: 05/12/21: Eric Smith: Re: lpc922
93439: 05/12/21: Ray Andraka: Re: lpc922
93447: 05/12/22: Eric Smith: Re: lpc922
93432: 05/12/21: bjzhangwn: call for paper,expresscard specification
93443: 05/12/22: Jim Granville: Xilinbx Online store XC2C32A, XC2C64A missing ?
93444: 05/12/22: Antti Lukats: Re: Xilinbx Online store XC2C32A, XC2C64A missing ?
93448: 05/12/22: Hal Murray: Re: Xilinbx Online store XC2C32A, XC2C64A missing ?
93445: 05/12/22: Marco: Opencores Can Controller
93446: 05/12/22: Antti Lukats: Re: Opencores Can Controller
93596: 05/12/25: Tom: Re: Opencores Can Controller
93453: 05/12/22: Tobias: Cordic v2.0 : cordic translate algorithm problem
93464: 05/12/22: peter.halford@alarmip.com: Going insane - Xilinx VGA controller...
93465: 05/12/22: Ed McGettigan: Re: Going insane - Xilinx VGA controller...
93467: 05/12/22: Dave: Re: Going insane - Xilinx VGA controller...
93471: 05/12/22: peter.halford@alarmip.com: Re: Going insane - Xilinx VGA controller...
93474: 05/12/23: Jim Granville: Re: Going insane - Xilinx VGA controller...
93482: 05/12/22: Sylvain Munaut: Re: Going insane - Xilinx VGA controller...
93492: 05/12/22: bh: Re: Going insane - Xilinx VGA controller...
93493: 05/12/22: dp: Re: Going insane - Xilinx VGA controller...
93688: 05/12/28: peter.halford@alarmip.com: Re: Going insane - Xilinx VGA controller...
93722: 05/12/28: Phil Hays: Re: Going insane - Xilinx VGA controller...
93769: 05/12/30: Symon: Re: Going insane - Xilinx VGA controller...
93795: 05/12/30: Jon Elson: Re: Going insane - Xilinx VGA controller...
93754: 05/12/29: peter.halford@alarmip.com: Re: Going insane - Xilinx VGA controller...
93796: 05/12/30: peter.halford@alarmip.com: Re: Going insane - Xilinx VGA controller...
93468: 05/12/22: motty: Synplicity and the EDK
93469: 05/12/22: Antti Lukats: Re: Synplicity and the EDK
93475: 05/12/22: <ccon67@netscape.net>: edif to vhd black box
93568: 05/12/24: Jim Wu: Re: edif to vhd black box
93476: 05/12/22: ajcrm125: RTL for Z8000 series CPU?
93501: 05/12/23: Antti Lukats: Re: RTL for Z8000 series CPU?
93509: 05/12/23: Grant Edwards: Re: RTL for Z8000 series CPU?
93510: 05/12/23: Antti Lukats: Re: RTL for Z8000 series CPU?
93512: 05/12/23: Monte Dalrymple: Re: RTL for Z8000 series CPU?
93523: 05/12/23: Monte Dalrymple: Re: RTL for Z8000 series CPU?
93536: 05/12/24: Grant Edwards: Re: RTL for Z8000 series CPU?
93538: 05/12/24: rk: Re: RTL for Z8000 series CPU?
93540: 05/12/23: Chuck F.: Re: RTL for Z8000 series CPU?
93550: 05/12/24: Bernard: Re: RTL for Z8000 series CPU?
93553: 05/12/24: Kolja Sulimma: Re: RTL for Z8000 series CPU?
93555: 05/12/24: Anton Erasmus: Re: RTL for Z8000 series CPU?
93559: 05/12/24: Chuck F.: Re: RTL for Z8000 series CPU?
93562: 05/12/24: Monte Dalrymple: Re: RTL for Z8000 series CPU?
94149: 06/01/06: Brian Drummond: Re: RTL for Z8000 series CPU?
93951: 06/01/04: Tobias Weingartner: Re: RTL for Z8000 series CPU?
93956: 06/01/04: Grant Edwards: Re: RTL for Z8000 series CPU?
93963: 06/01/04: Jim Granville: Re: RTL for Z8000 series CPU?
93978: 06/01/04: Bill Davy: Re: RTL for Z8000 series CPU?
94129: 06/01/06: Jonathan Kirwan: Re: RTL for Z8000 series CPU?
94300: 06/01/09: Tobias Weingartner: Re: RTL for Z8000 series CPU?
93521: 05/12/23: Peter Alfke: Re: RTL for Z8000 series CPU?
93527: 05/12/23: ajcrm125: Re: RTL for Z8000 series CPU?
93528: 05/12/23: Peter Alfke: Re: RTL for Z8000 series CPU?
93531: 05/12/23: ajcrm125: Re: RTL for Z8000 series CPU?
93533: 05/12/23: Peter Alfke: Re: RTL for Z8000 series CPU?
93534: 05/12/23: ajcrm125: Re: RTL for Z8000 series CPU?
93535: 05/12/23: Peter Alfke: Re: RTL for Z8000 series CPU?
93542: 05/12/23: ajcrm125: Re: RTL for Z8000 series CPU?
93543: 05/12/23: ajcrm125: Re: RTL for Z8000 series CPU?
93545: 05/12/23: ajcrm125: Re: RTL for Z8000 series CPU?
93547: 05/12/23: dp: Re: RTL for Z8000 series CPU?
93549: 05/12/24: JJ: Re: RTL for Z8000 series CPU?
93702: 05/12/28: MikeJ: Re: RTL for Z8000 series CPU?
93566: 05/12/24: ajcrm125: Re: RTL for Z8000 series CPU?
93648: 05/12/27: Peter Alfke: Re: RTL for Z8000 series CPU?
93872: 06/01/02: ajcrm125: Re: RTL for Z8000 series CPU?
93953: 06/01/03: Didi: Re: RTL for Z8000 series CPU?
93955: 06/01/03: Peter Alfke: Re: RTL for Z8000 series CPU?
93966: 06/01/04: Totally_Lost: Re: RTL for Z8000 series CPU?
93969: 06/01/04: Totally_Lost: Re: RTL for Z8000 series CPU?
93495: 05/12/22: bjzhangwn: microblaze & nios
93496: 05/12/22: bjzhangwn: Is there anybody that have ported the linux to the nios or microblaze?
93497: 05/12/23: Alex Gibson: Re: Is there anybody that have ported the linux to the nios or microblaze?
93499: 05/12/23: Antti Lukats: Re: Is there anybody that have ported the linux to the nios or microblaze?
93502: 05/12/23: Alex Gibson: Re: Is there anybody that have ported the linux to the nios or microblaze?
93530: 05/12/23: Paul Hartke: Re: Is there anybody that have ported the linux to the nios or
93805: 05/12/31: Mike Frysinger: Re: Is there anybody that have ported the linux to the nios or microblaze?
93868: 06/01/02: Mike Frysinger: Re: Is there anybody that have ported the linux to the nios or microblaze?
93537: 05/12/23: bjzhangwn: Re: Is there anybody that have ported the linux to the nios or microblaze?
93541: 05/12/23: John McCaskill: Re: Is there anybody that have ported the linux to the nios or microblaze?
93500: 05/12/23: Antti Lukats: Spartan3e and ChipScope
93504: 05/12/23: Leon: Re: Spartan3e and ChipScope
93505: 05/12/23: Antti Lukats: Re: Spartan3e and ChipScope
93507: 05/12/23: Alex Gibson: Re: Spartan3e and ChipScope
93556: 05/12/25: Alex Gibson: Re: Spartan3e and ChipScope
93508: 05/12/23: Antti Lukats: Re: Spartan3e and ChipScope
93520: 05/12/23: Andy Peters: Re: Spartan3e and ChipScope
93524: 05/12/23: Antti Lukats: Re: Spartan3e and ChipScope
93564: 05/12/24: Antti Lukats: Re: Spartan3e and ChipScope
93565: 05/12/24: Antti Lukats: Re: Spartan3e and ChipScope
93539: 05/12/23: John McCaskill: Re: Spartan3e and ChipScope
93554: 05/12/24: Leon: Re: Spartan3e and ChipScope
93563: 05/12/24: Peter Alfke: Re: Spartan3e and ChipScope
93929: 06/01/03: Antti Lukats: Re: Spartan3e and ChipScope -issue solved
93503: 05/12/23: Arne Demmers: SystemACE problem
93506: 05/12/23: Antti Lukats: Re: SystemACE problem
93515: 05/12/23: Arne Demmers: Re: SystemACE problem
93517: 05/12/23: Antti Lukats: Re: SystemACE problem
93513: 05/12/23: Marco T.: Virtex-4FX and ethernet mac
93529: 05/12/23: Paul Hartke: Re: Virtex-4FX and ethernet mac
93532: 05/12/23: leevv: re:Virtex-4FX and ethernet mac
93548: 05/12/24: Marco T.: Re: Virtex-4FX and ethernet mac
93514: 05/12/23: john: Image processing libraries and VHDL
93516: 05/12/23: Arne Demmers: Re: Image processing libraries and VHDL
93526: 05/12/23: Antti Lukats: FREE Spartan 3e Sample Pack
93544: 05/12/23: bjzhangwn: Can somone work on the pci express project?
93546: 05/12/23: Tim Wescott: Re: Can somone work on the pci express project?
93573: 05/12/25: Kevin Brace: Re: Can somone work on the pci express project?
93595: 05/12/26: mk: Re: Can somone work on the pci express project?
93574: 05/12/25: Kevin Brace: Re: Can somone work on the pci express project?
93575: 05/12/25: Antti Lukats: Re: Can somone work on the pci express project?
93577: 05/12/25: Kevin Brace: Re: Can somone work on the pci express project?
93578: 05/12/25: Antti Lukats: Re: Can somone work on the pci express project?
93571: 05/12/24: bjzhangwn: Re: Can somone work on the pci express project?
93551: 05/12/24: <mail@deeptrace.com>: Xilinx ISE Simulator
93552: 05/12/24: Antti Lukats: Re: Xilinx ISE Simulator
93676: 05/12/28: Paul Hartke: Re: Xilinx ISE Simulator
93719: 05/12/28: <mail@deeptrace.com>: Re: Xilinx ISE Simulator
93933: 06/01/03: <mail@deeptrace.com>: Re: Xilinx ISE Simulator
93558: 05/12/24: <svasus@gmail.com>: XILINX I2C controller core in FPGA and multisource problem.
93599: 05/12/26: <wtxwtx@gmail.com>: Re: XILINX I2C controller core in FPGA and multisource problem.
93601: 05/12/26: Antti Lukats: Re: XILINX I2C controller core in FPGA and multisource problem.
93603: 05/12/26: Antti Lukats: Re: XILINX I2C controller core in FPGA and multisource problem.
93628: 05/12/27: Antti Lukats: Re: XILINX I2C controller core in FPGA and multisource problem.
93773: 05/12/30: Antti Lukats: Re: XILINX I2C controller core in FPGA and multisource problem.
93774: 05/12/30: Uwe Bonnes: Re: XILINX I2C controller core in FPGA and multisource problem.
93602: 05/12/26: <wtxwtx@gmail.com>: Re: XILINX I2C controller core in FPGA and multisource problem.
93618: 05/12/26: <wtxwtx@gmail.com>: Re: XILINX I2C controller core in FPGA and multisource problem.
93761: 05/12/29: <svasus@gmail.com>: Re: XILINX I2C controller core in FPGA and multisource problem.
93772: 05/12/30: <wtxwtx@gmail.com>: Re: XILINX I2C controller core in FPGA and multisource problem.
93775: 05/12/30: <wtxwtx@gmail.com>: Re: XILINX I2C controller core in FPGA and multisource problem.
93567: 05/12/24: Jon Beniston: Re: re:Virtex-4FX and ethernet mac
93569: 05/12/24: Antti Lukats: Re: re:Virtex-4FX and ethernet mac
93572: 05/12/24: Binary: Where to find the Altera Schematic
93579: 05/12/25: bjzhangwn: Re: Where to find the Altera Schematic
93624: 05/12/26: chenboya@gmail.com: Re: Where to find the Altera Schematic
93580: 05/12/25: bjzhangwn: Is the microblaze or nios2 free?
93581: 05/12/25: Antti Lukats: Re: Is the microblaze or nios2 free?
93583: 05/12/25: lioupayphone@gmail.com: how to use ICAP on Virtex-II XC2V1000-FG456-4?
93584: 05/12/25: Antti Lukats: Re: how to use ICAP on Virtex-II XC2V1000-FG456-4?
93587: 05/12/25: Piotr Wyderski: Spartan 3 power requirements
93588: 05/12/25: Hal Murray: Re: Spartan 3 power requirements
93589: 05/12/25: Piotr Wyderski: Re: Spartan 3 power requirements
93590: 05/12/25: Peter Alfke: Re: Spartan 3 power requirements
93591: 05/12/25: Piotr Wyderski: Re: Spartan 3 power requirements
93608: 05/12/26: Hal Murray: Re: Spartan 3 power requirements
93593: 05/12/25: Peter Alfke: Re: Spartan 3 power requirements
93612: 05/12/26: Peter Alfke: Re: Spartan 3 power requirements
93614: 05/12/26: Peter Alfke: Re: Spartan 3 power requirements
93594: 05/12/25: Vik: Looking for 64 bit IEEE802.3 Verilog code or tips for code
93626: 05/12/27: Philip Freidin: Re: Looking for 64 bit IEEE802.3 Verilog code or tips for code
93692: 05/12/28: Vik: Re: Looking for 64 bit IEEE802.3 Verilog code or tips for code
93600: 05/12/26: Binary: IEEE package VHDL reference manual
93636: 05/12/27: <allanherriman@hotmail.com>: Re: IEEE package VHDL reference manual
93604: 05/12/26: Olivier Scalbert: Spartan-3 Starter Kit newbie question
93605: 05/12/26: Antti Lukats: Re: Spartan-3 Starter Kit newbie question
93606: 05/12/26: Olivier Scalbert: Re: Spartan-3 Starter Kit newbie question
93611: 05/12/26: Brad Smallridge: Xilinx V4 LVDS
93615: 05/12/26: Rob: Re: Xilinx V4 LVDS
93629: 05/12/26: Brad Smallridge: Re: Xilinx V4 LVDS
93663: 05/12/28: Rob: Re: Xilinx V4 LVDS
93627: 05/12/26: avishay: Re: Xilinx V4 LVDS
93630: 05/12/27: Brad Smallridge: Re: Xilinx V4 LVDS
93655: 05/12/27: Brad Smallridge: Re: Xilinx V4 LVDS
93665: 05/12/28: Rob: Re: Xilinx V4 LVDS
93691: 05/12/28: Brad Smallridge: Re: Xilinx V4 LVDS
93695: 05/12/28: Sean Durkin: Re: Xilinx V4 LVDS
93697: 05/12/28: Sean Durkin: Re: Xilinx V4 LVDS
93707: 05/12/28: Brad Smallridge: Re: Xilinx V4 LVDS
93715: 05/12/28: Brad Smallridge: Re: Xilinx V4 LVDS
93613: 05/12/26: Frank Schreiber: Download to board with RS232
93617: 05/12/26: Rob: Re: Download to board with RS232
93633: 05/12/27: Antti Lukats: Re: Download to board with RS232
93639: 05/12/27: Martin Schoeberl: Re: Download to board with RS232
93640: 05/12/27: Antti Lukats: Re: Download to board with RS232
93644: 05/12/27: Martin Schoeberl: Re: Download to board with RS232
93631: 05/12/27: =?ISO-8859-1?Q?C=E9dric_Jeanneret?=: Microblaze in a EDK pcore
93632: 05/12/27: Antti Lukats: Re: Microblaze in a EDK pcore
93637: 05/12/27: Petter Gustad: Re: Microblaze in a EDK pcore
93638: 05/12/27: Paul Hartke: Re: Microblaze in a EDK pcore
93635: 05/12/27: Antti Lukats: DDR2 support for EDK
93679: 05/12/28: <wtxwtx@gmail.com>: Re: DDR2 support for EDK
93684: 05/12/28: Antti Lukats: Re: DDR2 support for EDK
93641: 05/12/28: Engine: Xilinx Stepping Methodology
93642: 05/12/27: Ray Andraka: Re: Xilinx Stepping Methodology
93669: 05/12/28: Engine: Re: Xilinx Stepping Methodology
93643: 05/12/27: Austin Lesea: Re: Xilinx Stepping Methodology
93677: 05/12/28: Engine: Re: Xilinx Stepping Methodology
93682: 05/12/28: Austin Lesea: Re: Xilinx Stepping Methodology
93645: 05/12/27: johnp: USB 2.0 testbench available?
93646: 05/12/27: Antti Lukats: Re: USB 2.0 testbench available?
93661: 05/12/27: johnp: Re: USB 2.0 testbench available?
93650: 05/12/27: Nitesh: ERROR:iMPACT:585
93690: 05/12/28: Neil Glenn Jacobson: Re: ERROR:iMPACT:585
93651: 05/12/27: shogmic: Virtex-4 CCLK termination
93652: 05/12/27: Austin Lesea: Re: Virtex-4 CCLK termination
93656: 05/12/27: Brad Smallridge: Re: Virtex-4 CCLK termination
93662: 05/12/27: Peter Alfke: Re: Virtex-4 CCLK termination
93664: 05/12/28: Bob: Re: Virtex-4 CCLK termination
93668: 05/12/28: Bob: Re: Virtex-4 CCLK termination
93674: 05/12/28: Symon: Re: Virtex-4 CCLK termination
93680: 05/12/28: Bob: Re: Virtex-4 CCLK termination
93711: 05/12/28: Austin Lesea: Re: Virtex-4 CCLK termination
93712: 05/12/29: Bevan Weiss: Re: Virtex-4 CCLK termination
93731: 05/12/29: Symon: Re: Virtex-4 CCLK termination
93741: 05/12/29: Austin Lesea: Re: Virtex-4 CCLK termination
93667: 05/12/27: Peter Alfke: Re: Virtex-4 CCLK termination
93670: 05/12/27: Peter Alfke: Re: Virtex-4 CCLK termination
93704: 05/12/28: shogmic: Re: Virtex-4 CCLK termination
93718: 05/12/28: Peter Alfke: Re: Virtex-4 CCLK termination
93653: 05/12/27: motty: Using Synplicity to synthesize EDK user IP's
93683: 05/12/28: Mike Treseler: Re: Using Synplicity to synthesize EDK user IP's
93696: 05/12/28: Bob Efram: Re: Using Synplicity to synthesize EDK user IP's
93713: 05/12/28: motty: Re: Using Synplicity to synthesize EDK user IP's
93721: 05/12/28: motty: Re: Using Synplicity to synthesize EDK user IP's
93654: 05/12/27: Yaju Nagaonkar: serial configuration of Spartan 3 FPGA
93657: 05/12/28: Alex Gibson: S3e starter kits available
93748: 05/12/29: John_H: Re: S3e starter kits available
93751: 05/12/29: Antti Lukats: Re: S3e starter kits available
93791: 05/12/30: Joe Chisolm: Re: S3e starter kits available
93792: 05/12/30: Antti Lukats: Re: S3e starter kits available
93793: 05/12/30: Joe Chisolm: Re: S3e starter kits available
93794: 05/12/30: Antti Lukats: Re: S3e starter kits available
93936: 06/01/03: Antti Lukats: Re: S3e starter kits available
93940: 06/01/03: John_H: Re: S3e starter kits available
93968: 06/01/04: Antti Lukats: Re: S3e starter kits available
94199: 06/01/07: Antti Lukats: Re: S3e starter kits available
94200: 06/01/07: Antti Lukats: Re: S3e starter kits available
94248: 06/01/09: Antti Lukats: Re: S3e starter kits available
94393: 06/01/11: Antti Lukats: Re: S3e starter kits available
93950: 06/01/03: Pierre: Re: S3e starter kits available
94236: 06/01/08: Brian Davis: Re: S3e starter kits available
94258: 06/01/09: Brian Davis: Re: S3e starter kits available
95028: 06/01/20: Joel: Re: S3e starter kits available
93658: 05/12/27: Binary: Can Altera Cyclone device's clock input directly used as CLK with PLL?
93659: 05/12/27: eou4: Re: Can Altera Cyclone device's clock input directly used as CLK with PLL?
93666: 05/12/28: Rob: Re: Can Altera Cyclone device's clock input directly used as CLK with PLL?
93675: 05/12/28: Noway2: Re: Can Altera Cyclone device's clock input directly used as CLK with PLL?
93660: 05/12/27: eou4: disappear silicore
93671: 05/12/28: Soenke: DigitalRadioMondiale
93687: 05/12/28: Uncle Noah: Re: DigitalRadioMondiale
93672: 05/12/28: <camillo79@gmail.com>: Handel-C & DK3
93673: 05/12/28: u_stadler@yahoo.de: ISE WebPack Clock Signals
93764: 05/12/30: <sunyz@bocom.com.cn>: Re: ISE WebPack Clock Signals
93678: 05/12/28: Marco T.: CP2101 <-> Printer?
93685: 05/12/28: Antti Lukats: Re: CP2101 <-> Printer?
93681: 05/12/28: <wtxwtx@gmail.com>: What is the difference betwee 'Method' and 'Apparatus' in a patent claim area
93689: 05/12/28: <dagmargoodboat@yahoo.com>: Re: What is the difference betwee 'Method' and 'Apparatus' in a patent claim area
93729: 05/12/29: Robert Baer: Re: What is the difference betwee 'Method' and 'Apparatus' in a patent
93762: 05/12/30: Robert Baer: Re: What is the difference betwee 'Method' and 'Apparatus' in a patent
93826: 06/01/01: Robert Baer: Re: What is the difference betwee 'Method' and 'Apparatus' in a patent
93827: 06/01/01: Robert Baer: Re: What is the difference betwee 'Method' and 'Apparatus' in a patent
93828: 06/01/01: Keith: Re: What is the difference betwee 'Method' and 'Apparatus' in a patent claim area
93735: 05/12/29: <wtxwtx@gmail.com>: Re: What is the difference betwee 'Method' and 'Apparatus' in a patent claim area
93771: 05/12/30: <wtxwtx@gmail.com>: Re: What is the difference betwee 'Method' and 'Apparatus' in a patent claim area
93797: 05/12/30: <wtxwtx@gmail.com>: Re: What is the difference betwee 'Method' and 'Apparatus' in a patent claim area
93837: 06/01/01: <wtxwtx@gmail.com>: Re: What is the difference betwee 'Method' and 'Apparatus' in a patent claim area
93686: 05/12/28: Piotr Wyderski: Lattice XP simple simulator
93928: 06/01/03: <troy.scott@latticesemi.com>: Re: Lattice XP simple simulator
93693: 05/12/28: Brad Smallridge: Xilinx LVDS termination resistor
93694: 05/12/28: Austin Lesea: Re: Xilinx LVDS termination resistor
93703: 05/12/28: Brad Smallridge: Re: Xilinx LVDS termination resistor
93714: 05/12/28: Brad Smallridge: Re: Xilinx LVDS termination resistor
93720: 05/12/28: Marc Randolph: Re: Xilinx LVDS termination resistor
93698: 05/12/28: Paul Boven: What is 'drive strength' for? (Spartan 3)
93701: 05/12/28: Austin Lesea: Re: What is 'drive strength' for? (Spartan 3)
93706: 05/12/29: Sylvain Munaut: Re: What is 'drive strength' for? (Spartan 3)
93708: 05/12/28: Austin Lesea: Re: What is 'drive strength' for? (Spartan 3)
93710: 05/12/29: Kolja Sulimma: Re: What is 'drive strength' for? (Spartan 3)
93699: 05/12/28: Austin Lesea: Power Optimization: can the routing and placement really save power?
93705: 05/12/28: <soar2morrow@yahoo.com>: Re: Power Optimization: can the routing and placement really save power?
93709: 05/12/28: Austin Lesea: Re: Power Optimization: can the routing and placement really save
93727: 05/12/29: PeteS: Re: Power Optimization: can the routing and placement really save power?
93738: 05/12/29: Martin Schoeberl: Re: Power Optimization: can the routing and placement really save power?
93739: 05/12/29: Symon: Re: Power Optimization: can the routing and placement really save power?
93744: 05/12/29: Martin Schoeberl: Re: Power Optimization: can the routing and placement really save power?
93756: 05/12/29: Martin Schoeberl: Re: Power Optimization: can the routing and placement really save power?
93768: 05/12/30: Jan Panteltje: Re: Power Optimization: can the routing and placement really save power?
93799: 05/12/31: Jim Granville: Re: Power Optimization: can the routing and placement really save
93749: 05/12/29: Peter Alfke: Re: Power Optimization: can the routing and placement really save power?
93758: 05/12/29: Peter Alfke: Re: Power Optimization: can the routing and placement really save power?
93798: 05/12/31: Jim Granville: Re: Power Optimization: can the routing and placement really save
93902: 06/01/03: Vaughn Betz: Re: Power Optimization: can the routing and placement really save power?
93717: 05/12/28: eehinjor: PCI interface on CYCLONE(ep1c6)
93726: 05/12/29: PeteS: Re: PCI interface on CYCLONE(ep1c6)
93723: 05/12/29: Marco T.: USB Printer Interface
93724: 05/12/29: Antti Lukats: Re: USB Printer Interface
93743: 05/12/29: Marco T.: Re: USB Printer Interface
93725: 05/12/29: akun: FSM goes into invalid state after reset...
93730: 05/12/29: <francesco_poderico@yahoo.com>: Re: FSM goes into invalid state after reset...
93732: 05/12/29: John Adair: Re: FSM goes into invalid state after reset...
93733: 05/12/29: Lars: System Monitor in Virtex-4
93734: 05/12/29: Symon: Re: System Monitor in Virtex-4
93737: 05/12/29: Symon: Re: System Monitor in Virtex-4
93742: 05/12/29: Austin Lesea: Re: System Monitor in Virtex-4: alive? or dead? or just forgotten?
93736: 05/12/29: Lars: Re: System Monitor in Virtex-4
93745: 05/12/29: Lars: Re: System Monitor in Virtex-4: alive? or dead? or just forgotten?
93740: 05/12/29: Antti Lukats: Spartan3E Parallel Flash Programming (with free Spartan 3e Sample Pack)
93746: 05/12/29: Antti Lukats: Re: Spartan3E Parallel Flash Programming (with free Spartan 3e Sample Pack)
93752: 05/12/29: Symon: Re: Spartan3E Parallel Flash Programming (with free Spartan 3e Sample Pack)
93753: 05/12/29: Antti Lukats: Re: Spartan3E Parallel Flash Programming (with free Spartan 3e Sample Pack)
93747: 05/12/29: Martin Schoeberl: Actel Fusion
93750: 05/12/29: Antti Lukats: Re: Actel Fusion
93871: 06/01/02: Javier Lopez: Re: Actel Fusion
93755: 05/12/29: Brad Smallridge: Xilinx ML402 DRAM control
93786: 05/12/30: Joseph Samson: Re: Xilinx ML402 DRAM control
93757: 05/12/29: <linq936@hotmail.com>: Virtex 4 desing : ChipScope insertion impacts my timing problem debug
93785: 05/12/30: mike_la_jolla: Re: Virtex 4 desing : ChipScope insertion impacts my timing problem debug
93815: 05/12/31: John Adair: Re: Virtex 4 desing : ChipScope insertion impacts my timing problem debug
93759: 05/12/29: logjam: Brute Force Examination of a PLD
93765: 05/12/30: Mike Harrison: Re: Brute Force Examination of a PLD
93766: 05/12/30: Henry: Re: Brute Force Examination of a PLD
93767: 05/12/30: Antti Lukats: Re: Brute Force Examination of a PLD
93820: 05/12/31: Eric Smith: Re: Brute Force Examination of a PLD
93822: 06/01/01: Jim Granville: Re: Brute Force Examination of a PLD
93801: 05/12/30: logjam: Re: Brute Force Examination of a PLD
93821: 05/12/31: Totally_Lost: Re: Brute Force Examination of a PLD
93760: 05/12/29: king_azman: PPC405 on ISE
93763: 05/12/30: Antti Lukats: Re: PPC405 on ISE
93938: 06/01/03: Peter Ryser: Re: PPC405 on ISE
93782: 05/12/30: Duane Clark: Re: PPC405 on ISE
93937: 06/01/03: Peter Ryser: Re: PPC405 on ISE
93957: 06/01/03: king_azman: Re: PPC405 on ISE
93770: 05/12/30: AAA: TCL SCRIPT AND VHDL DESIGN
93808: 05/12/31: Hans: Re: TCL SCRIPT AND VHDL DESIGN
93958: 06/01/03: AAA: Re: TCL SCRIPT AND VHDL DESIGN
93776: 05/12/30: bjzhangwn: call for papers,Expresscard specification?
93777: 05/12/30: Antti Lukats: Re: call for papers,Expresscard specification?
93779: 05/12/30: bjzhangwn: Re: call for papers,Expresscard specification?
93780: 05/12/30: Antti Lukats: Re: call for papers,Expresscard specification?
93809: 05/12/31: Hans: Re: call for papers,Expresscard specification?
93810: 05/12/31: John Adair: Re: call for papers,Expresscard specification?
93778: 05/12/30: bjzhangwn: Can some give me some advice?
93781: 05/12/30: JJ: Re: Can some give me some advice?
93787: 05/12/30: Tim Wescott: Re: Can some give me some advice?
93783: 05/12/30: drg: using internal POR
93784: 05/12/30: Antti Lukats: Re: using internal POR
93788: 05/12/30: Paul Marciano: How do I instantiate an ADSU8 in ISE7.1i?
93790: 05/12/30: Antti Lukats: Re: How do I instantiate an ADSU8 in ISE7.1i?
93789: 05/12/30: Antti Lukats: Easy and fun: Worlds smallest FPGA module.
93838: 06/01/01: Nial Stewart: Re: Easy and fun: Worlds smallest FPGA module.
93843: 06/01/02: Antti Lukats: Re: Easy and fun: Worlds smallest FPGA module.
93865: 06/01/02: Antti Lukats: Re: Easy and fun: Worlds smallest FPGA module.
93840: 06/01/01: Leon: Re: Easy and fun: Worlds smallest FPGA module.
93800: 05/12/30: Peter Alfke: Re: Power Optimization: can the routing and placement really save power?
93900: 06/01/03: Vaughn Betz: Re: Power Optimization: can the routing and placement really save power?
93802: 05/12/30: Mike Oxlarge: Newbie question - using library "design elements"
93812: 05/12/31: John Adair: Re: Newbie question - using library "design elements"
93816: 05/12/31: Mike Oxlarge: Re: Newbie question - using library "design elements"
93817: 05/12/31: John Adair: Re: Newbie question - using library "design elements"
93803: 05/12/30: Totally_Lost: open source xnf to edif script
93804: 05/12/30: Totally_Lost: Fitting circuits to fpga LUTs
93835: 06/01/01: Kolja Sulimma: Re: Fitting circuits to fpga LUTs
93806: 05/12/30: Totally_Lost: Low cost PCI FPGA cards for reconfigurable computing
93807: 05/12/31: Antti Lukats: Re: Low cost PCI FPGA cards for reconfigurable computing
93811: 05/12/31: John Adair: Re: Low cost PCI FPGA cards for reconfigurable computing
93813: 05/12/31: Dan NITA: Timing problem in ModelSim, Post-Route Simulation.
93814: 05/12/31: Julian Kain: Re: Timing problem in ModelSim, Post-Route Simulation.
93845: 06/01/02: Dan NITA: Re: Timing problem in ModelSim, Post-Route Simulation.
93862: 06/01/02: Mike Treseler: Re: Timing problem in ModelSim, Post-Route Simulation.
94023: 06/01/04: Mike Treseler: Re: Timing problem in ModelSim, Post-Route Simulation.
94032: 06/01/04: Mike Treseler: Re: Timing problem in ModelSim, Post-Route Simulation.
93930: 06/01/03: <troy.scott@latticesemi.com>: Re: Timing problem in ModelSim, Post-Route Simulation.
93981: 06/01/04: Dan NITA: Re: Timing problem in ModelSim, Post-Route Simulation.
94003: 06/01/04: Andy: Re: Timing problem in ModelSim, Post-Route Simulation.
94028: 06/01/04: Andy: Re: Timing problem in ModelSim, Post-Route Simulation.
93818: 05/12/31: <wtxwtx@gmail.com>: Why 'a plurality of N' must be used for 'N' in patent claims
93875: 06/01/02: Eric Smith: Re: Why 'a plurality of N' must be used for 'N' in patent claims
93877: 06/01/03: Robert Baer: Re: Why 'a plurality of N' must be used for 'N' in patent claims
93993: 06/01/04: Dirk Bruere at Neopax: Re: Why 'a plurality of N' must be used for 'N' in patent claims
94013: 06/01/04: Symon: Re: Why 'a plurality of N' must be used for 'N' in patent claims
94306: 06/01/09: mk: Re: Why 'a plurality of N' must be used for 'N' in patent claims
94050: 06/01/05: Robert Baer: Re: Why 'a plurality of N' must be used for 'N' in patent claims
94398: 06/01/11: Simon Peacock: Re: Why 'a plurality of N' must be used for 'N' in patent claims
93891: 06/01/03: <wtxwtx@gmail.com>: Re: Why 'a plurality of N' must be used for 'N' in patent claims
94006: 06/01/04: <soar2morrow@yahoo.com>: Re: Why 'a plurality of N' must be used for 'N' in patent claims
94305: 06/01/09: <soar2morrow@yahoo.com>: Re: Why 'a plurality of N' must be used for 'N' in patent claims
94488: 06/01/12: <soar2morrow@yahoo.com>: Re: Why 'a plurality of N' must be used for 'N' in patent claims
93819: 05/12/31: drg: basic DSP with FPGA
93823: 05/12/31: Binary: Re: basic DSP with FPGA
93824: 05/12/31: Tim Wescott: Re: basic DSP with FPGA
93830: 06/01/01: Slurp: Re: basic DSP with FPGA
93844: 06/01/02: Brian Dam Pedersen: Re: basic DSP with FPGA
93905: 06/01/03: Symon: Re: basic DSP with FPGA
93919: 06/01/03: Tim Wescott: Re: basic DSP with FPGA
93921: 06/01/03: Austin Lesea: Re: basic DSP with FPGA
94057: 06/01/05: Hal Murray: Re: basic DSP with FPGA
94151: 06/01/06: Symon: Re: basic DSP with FPGA
93971: 06/01/04: Symon: Re: basic DSP with FPGA
93833: 06/01/01: drg: Re: basic DSP with FPGA
93834: 06/01/01: Adrian Knoth: Re: basic DSP with FPGA
93839: 06/01/01: <stenasc@yahoo.com>: Re: basic DSP with FPGA
93841: 06/01/01: David R Brooks: Re: basic DSP with FPGA
93852: 06/01/02: jerzy.gbur@gmail.com: Re: basic DSP with FPGA
93954: 06/01/03: drg: Re: basic DSP with FPGA
94115: 06/01/05: drg: Re: basic DSP with FPGA
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