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"ma" <ma@nowhere.com> schrieb im Newsbeitrag news:LcBvf.86365$PD2.51133@fe1.news.blueyonder.co.uk... > Hello, > > I have a Veritex-4 PCI board and I like to program the PowerPC on it. I > don't have the EDK from Xilinx. Here are my questions: > > > How can program the PowerPC without buying EDK? > short answer: you can not long answer: you can if write your own minimal replacement fo EDK > As I know the compiler and linker is free (part of GNU) where can I get > them for free? > ppc gcc can be obtained but it want help you much, see above > How can I download the compiled program to PowerPC? > over JTAG or buy preloading BRAMs > How can I get the output? For example if I write a hello world type of > program, can I see the STDIO on screen? > > use EDK or add your peripherals and re-implemented all the funtionality provide by EDK > Any help is much appreciated. > doing it wihtout EDK costs you WAY more than than obtaining EDK, it could be done, but the time needed for that just isnt worht doing it sorry, but Xilinx REALLY REALLY doesnt want anyone to work on the Virtex PPC without using EDK, it is doable (without EDK) but it really isnt worht trying AnttiArticle: 94176
Thanks. Can I program it without using JTAG possibly over PCI bus? I am ready to write appropriate driver if I know where can I get the documentation for writing such driver. Best regards "Antti Lukats" <antti@openchip.org> wrote in message news:dpmq2m$c97$1@online.de... > "ma" <ma@nowhere.com> schrieb im Newsbeitrag > news:LcBvf.86365$PD2.51133@fe1.news.blueyonder.co.uk... >> Hello, >> >> I have a Veritex-4 PCI board and I like to program the PowerPC on it. I >> don't have the EDK from Xilinx. Here are my questions: >> >> >> How can program the PowerPC without buying EDK? >> > short answer: you can not > long answer: you can if write your own minimal replacement fo EDK > >> As I know the compiler and linker is free (part of GNU) where can I get >> them for free? >> > ppc gcc can be obtained but it want help you much, see above > >> How can I download the compiled program to PowerPC? >> > over JTAG or buy preloading BRAMs > >> How can I get the output? For example if I write a hello world type of >> program, can I see the STDIO on screen? >> >> > use EDK or add your peripherals and re-implemented all the funtionality > provide by EDK > >> Any help is much appreciated. >> > > doing it wihtout EDK costs you WAY more than than obtaining EDK, it could > be done, but the time needed for that just isnt worht doing it > > sorry, but Xilinx REALLY REALLY doesnt want anyone to work on the Virtex > PPC without using EDK, it is doable (without EDK) but it really isnt worht > trying > > Antti > >Article: 94177
"ma" <ma@nowhere.com> schrieb im Newsbeitrag news:X0Cvf.86397$PD2.74779@fe1.news.blueyonder.co.uk... > Thanks. > Can I program it without using JTAG possibly over PCI bus? I am ready to > write appropriate driver if I know where can I get the documentation for > writing such driver. you can "load" the program by any means you wish - as logn as you have written your own bootstrap loader. this can be of PCI bus also. but that is not your problem, without EDK you wast WAY too much time and most likely end up with nothing anyway - there is nothing to 'program' as long as you dont have the proper system bus structure and peripheral IP cores in place, and even as it is possible to be done without using EDK, it doesnt make sense. AnttiArticle: 94178
"ma" <ma@nowhere.com> writes: > Where can I find information about writing a driver for downloading > program to PowerPC It depends. You have to get the code into memory somehow, either BRAM, SDRAM, FLASH, etc. that you have on your board. How you do that depends on the IO interface you have on your board, JTAG, USB, PCI, RS-232, etc. > redirecting its STDIO to a window in PC? That also depends on the IO interface you have on your board. If you have a serial-port you can print to the serial-port and get the output to a window on your PC using kermit or whatever serial program you prefer. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 94179
That make sense. My idea is that I buy EDK and then develop my driver to download and use the processor without JTAG by writing my own driver for PCI. My main aim is to learn in the cheapest way! Where can I find information about writing a driver for downloading program to PowerPC and also redirecting its STDIO to a window in PC? Best regards and thanks for your kind help. "Antti Lukats" <antti@openchip.org> wrote in message news:dpmqni$db0$1@online.de... > "ma" <ma@nowhere.com> schrieb im Newsbeitrag > news:X0Cvf.86397$PD2.74779@fe1.news.blueyonder.co.uk... >> Thanks. >> Can I program it without using JTAG possibly over PCI bus? I am ready to >> write appropriate driver if I know where can I get the documentation for >> writing such driver. > > you can "load" the program by any means you wish - as logn as you have > written your own bootstrap loader. > this can be of PCI bus also. > > but that is not your problem, without EDK you wast WAY too much time and > most likely end up with nothing anyway - there is nothing to 'program' as > long as you dont have the proper system bus structure and peripheral IP > cores in place, and even as it is possible to be done without using EDK, > it doesnt make sense. > > > Antti > > >Article: 94180
I am looking at using a CRC to provide single bit error correction and multiple bit error detection. I have worked with CRCs before and know how to implement them. But I am lacking some of the theoretical background on how to choose the polynomial. My data packets are a total of 191 bits with a 31 bit header containing the CRC and 160 data bits. The header will have its own error correction. I am trying to determine an optimal CRC polynomial for the whole packet. Currently there is space in the header for a CRC-8. I may be able to find a few spare bits to make the CRC 10 or 12 bits if I have to. Any pointers to show me how to evaluate a polynomial? Or any shortcuts that can be recommended? I guess this has been done before.Article: 94181
Thanks
I think I understood what I should do to download the program into PowerPC
at least in theory :)
But I couldn't understand what how can use PCI bus for getting STDIO out of
board? assume that I have the following code in my PowerPC program:
main()
{
printf("hello world\n");
}
what is the path from PowerPC to a window on PC? assuming I know how to
communicate between FPGA board and PC.
Best regards
"Petter Gustad" <newsmailcomp6@gustad.com> wrote in message
news:87wthd0x8m.fsf@parish.home.gustad.com...
> "ma" <ma@nowhere.com> writes:
>
>> Where can I find information about writing a driver for downloading
>> program to PowerPC
>
> It depends. You have to get the code into memory somehow, either BRAM,
> SDRAM, FLASH, etc. that you have on your board. How you do that
> depends on the IO interface you have on your board, JTAG, USB, PCI,
> RS-232, etc.
>
>> redirecting its STDIO to a window in PC?
>
> That also depends on the IO interface you have on your board. If you
> have a serial-port you can print to the serial-port and get the output
> to a window on your PC using kermit or whatever serial program you
> prefer.
>
> Petter
>
> --
> A: Because it messes up the order in which people normally read text.
> Q: Why is top-posting such a bad thing?
> A: Top-posting.
> Q: What is the most annoying thing on usenet and in e-mail?
Article: 94182"rickman" <spamgoeshere4@yahoo.com> wrote in message news:1136591102.008773.180960@g43g2000cwa.googlegroups.com... >I am looking at using a CRC to provide single bit error correction and > multiple bit error detection. I have worked with CRCs before and know > how to implement them. But I am lacking some of the theoretical > background on how to choose the polynomial. My data packets are a > total of 191 bits with a 31 bit header containing the CRC and 160 data > bits. The header will have its own error correction. I am trying to > determine an optimal CRC polynomial for the whole packet. Currently > there is space in the header for a CRC-8. I may be able to find a few > spare bits to make the CRC 10 or 12 bits if I have to. > > Any pointers to show me how to evaluate a polynomial? Or any shortcuts > that can be recommended? I guess this has been done before. > You can't correct errors with a CRC. Detection only, then request a re-transmit. For error correction you need a block code or something like that. If you end up using a CRC anyway, the web site below will generate VHDL or Verilog code to calculate CRCs for any polynomial and any data width. It's incredibly useful. http://www.easics.be/webtools/crctool As for how to choose a polynomial, that's complicated. I'd stick with one of the standard ones. There's a pull-down menu on the site above where you can select from a list of standard polynomials. The only 8-bit one is for the ATM HEC. Good luck. RobArticle: 94183
We occasionally have problems with the DCMs not locking. I just made a simple "DCM watchdog". It is a state machine starting at system reset. It first resets the DCM, then waits for the DCM to lock (as long as specified in the data sheet). If the DCM doesn't lock, the state machine starts over (resetting the DCM again). - Elling On Thu, 05 Jan 2006 15:50:16 +0100, <debashish.hota@gmail.com> wrote: > Hi all, > > i am facing a problem with Xilinx DCM in DFS (not in DLL mode, in which > you need to provide a feedback clock for phase alignmen). So my DCM is > working in without feedback (internal as well as external) mode. > > I am trying to generate a 32Mhz clock from a 16Mhz input clock. Most > of the time it works fine but sometimes after giving a reset to FPGA or > reprogramming the FPGA the DCM is not able to multiply the clock to > give a 32Mhz clock and gives the same input 16Mhz clock as the output. > > But according to Xilinx DCM datasheet, in DFS mode we should be able to > multiply or divide clocks with frequency > 1 Mhz. > > So if anyone has faced any such problem or if there is any synthesis > attribute which I need to set etc then please guide me. > > Thanks in advance > Debashish >Article: 94184
On Fri, 6 Jan 2006 08:52:13 +0000 (UTC), Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> wrote: >John Larkin <jjlarkin@highnotlandthistechnologypart.com> wrote: >> On Wed, 4 Jan 2006 22:08:26 +0000 (UTC), Uwe Bonnes >> <bon@hertz.ikp.physik.tu-darmstadt.de> wrote: > >> >Mike Treseler <mike_treseler@comcast.net> wrote: >> >> Austin Lesea wrote: >> > >> >> > I would invest my time in learning a HDL: VHDL or Verilog. >> > >> >> Good advice, but allow several months. >> > >> >But schematic entry oftem leads to non-registered designs, where you should >> >allow several month of debugging too... > >> Why? Logic is logic. We do lots of complex designs, state machines and >> all, in schematic form, and they come up in days or hours. > >If you do registered designs and don't relay on some function having some >definite delay, things will be fine. However many TTL designs are created >different... Sure, one can do nasty async design in schematics, or in VHDL for that matter. But S/360 and Cray and the HP35 and moon rockets were designed before HDLs, and they worked fine. Some people were good at logic design a long time before FPGAs were invented. I don't have time to learn an HDL. I read the Xilinx book, draw schematics (on paper!), and hand them to a minion to enter and compile. Works great. JohnArticle: 94185
Hi All, I am using Xilinx ISE 7.1 and ModelSim XE III 6.0 to analze flip-flop and routing behavior in a Virtex II part. Ports that are declared in my VHDL entity declaration are simulated and shown in the wave window in ModelSim. My question is this; how does one specify in Xilinx ISE additional signals (that are not routed to IOB's) to be simulated in ModelSim? Using the "add probe" feature seems to route the signals to IOB pads and then simulates the result of that, I need to see the signal inside a slice (or at least right before or after the slice). Thanks, BrendanArticle: 94186
On Sat, 07 Jan 2006 00:06:09 GMT, "ma" <ma@nowhere.com> wrote:
>Thanks
>I think I understood what I should do to download the program into PowerPC
>at least in theory :)
>But I couldn't understand what how can use PCI bus for getting STDIO out of
>board? assume that I have the following code in my PowerPC program:
>
>main()
>{
> printf("hello world\n");
>}
>
>what is the path from PowerPC to a window on PC? assuming I know how to
>communicate between FPGA board and PC.
Telling you the path is the easy part. You need to (re-)implement the
printf library function and instead of writing to a file (number 1
IIRC) you write the data to a memory buffer and generate an interrupt
to the PCI bus. Your driver running on the PC, having received the
interrupt, would read the data from the same buffer. It is no
different than a network card receiving a packet from the network
actually. How would you write a device driver which dumps all the
packets to screen ? It's the same only the data doesn't come from the
wire but from your printf implementation. You can structure your pc
device driver/hardware communication stack similarly.
Article: 94187RobJ wrote: > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:1136591102.008773.180960@g43g2000cwa.googlegroups.com... > >I am looking at using a CRC to provide single bit error correction and > > multiple bit error detection. I have worked with CRCs before and know [snip] > You can't correct errors with a CRC. Detection only, then request a > re-transmit. For error correction you need a block code or something like > that. Actually, you can use a CRC to correct errors, for a sufficiently short message. Think about the equivalence of a CRC and a block code. The terminology is very different (between the CRC and the block coding camps), which makes it hard to understand, but if you try you can formulate the CRC in terms of a generator matrix. Regards, AllanArticle: 94188
<allanherriman@hotmail.com> wrote in message news:1136594549.274038.301910@g14g2000cwa.googlegroups.com... > > Actually, you can use a CRC to correct errors, for a sufficiently short > message. > > Think about the equivalence of a CRC and a block code. The terminology > is very different (between the CRC and the block coding camps), which > makes it hard to understand, but if you try you can formulate the CRC > in terms of a generator matrix. > Wow, that's news to me. Can you show how this is done in equation form? Thanks, RobArticle: 94189
rickman wrote: > I am looking at using a CRC to provide single bit error correction and > multiple bit error detection. I have worked with CRCs before and know > how to implement them. But I am lacking some of the theoretical > background on how to choose the polynomial. My data packets are a > total of 191 bits with a 31 bit header containing the CRC and 160 data > bits. The header will have its own error correction. I am trying to > determine an optimal CRC polynomial for the whole packet. Currently > there is space in the header for a CRC-8. I may be able to find a few > spare bits to make the CRC 10 or 12 bits if I have to. > > Any pointers to show me how to evaluate a polynomial? Or any shortcuts > that can be recommended? I guess this has been done before. > I highly recommend "Error Correction Coding for Digital Communications" by Clark & Cain. It'll tell you how to do it, and if I recall correctly the table at the back will even give you some candidate polynomials. You should probably be searching under the keywords "polynomial codes" for information. -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 94190
John Larkin wrote: > Sure, one can do nasty async design in schematics, or in VHDL for that > matter. But S/360 and Cray and the HP35 and moon rockets were designed > before HDLs, and they worked fine. Some people were good at logic > design a long time before FPGAs were invented. > And some people are still quite lousy with logic design despite having FPGAs and the best HDLs. HDLs do not make a good logic designer, they are simply a tool.Article: 94191
Hi, I have a problem that after Synplify or XST optimizing, my 16x8 RAM is reduced to 1x8. This is not my hope. How to avoid this?Article: 94192
As I know ,in verilog,if the signals you specifys is not in use,and the synthesis tool(synplify pro etc)will optimize it,and will give a warning and remove it.Article: 94193
I think you're wrong.Article: 94194
On Fri, 06 Jan 2006 21:22:51 GMT, "ma" <ma@nowhere.com> wrote in comp.dsp: > Hello, > > I have a Veritex-4 PCI board and I like to program the PowerPC on it. I > don't have the EDK from Xilinx. Here are my questions: > > > > How can program the PowerPC without buying EDK? > > As I know the compiler and linker is free (part of GNU) where can I get them > for free? > > How can I download the compiled program to PowerPC? > > How can I get the output? For example if I write a hello world type of > program, can I see the STDIO on screen? > > > > Any help is much appreciated. > > > > Best regards Your program is not just programming the PowerPC core(s). The processors are hard core, but they have no connection at all to the outside world. You have to configure the FPGA to provide some internally memory, and for a program of any size, to act as a memory controller to more memory off the chip. Virtix provides IP for all of this, and all of this must be done before the PowerPC can even fetch its first instruction. -- Jack Klein Home: http://JK-Technology.Com FAQs for comp.lang.c http://c-faq.com/ comp.lang.c++ http://www.parashift.com/c++-faq-lite/ alt.comp.lang.learn.c-c++ http://www.contrib.andrew.cmu.edu/~ajo/docs/FAQ-acllc.htmlArticle: 94195
Altera In the field of both user interface and functionlity.Article: 94196
>> How can I download the compiled program to PowerPC? >> >over JTAG or buy preloading BRAMs Are they cheaper than the EDK? Are they available through the Xilinx online store? :) (good one) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 94197
news.guardiani@gmail.com wrote: > The solution is simple, but far from obvious. You need to download and > apply the patch for ISE 7.1 or install the latest service pack (4). > There is a bug that inverts all of the outputs of CPLDs (with no > service pack and also maybe SP1). > > Go to www.xilinx.com, select downloads, log in (or create a new > account), then select your ISE version and OS. > > Xilinx has refused to post this information to their download page. I > even talked to a factory FAE and he could not get them to post it. The > only way you can find out about it is to search their site for key > words that match the article. One has to wonder how this schoolboy error got past their supposedly 'rigourous regression testing' - oh, maybe that is only for FPGAs ? You could also move to ISE 8.1 ? -jgArticle: 94198
I had posted a few weeks back about my issue http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/73534630e805751a/21f880630f20ca74?q=fpga+pci&rnum=1#21f880630f20ca74 Now I have one more issue. I have to do a DMA burst transfer. The pci controller on board is a powerspan2 Dual pci bridge from tundra. I have data in my PLB master/slave module. I have to send this data to the host computer to which the card is connected.So If I will have to do a DMA tranfsfer but for DMA the bridge needs the start address and the end address. Now according to my understanding after going though the powerspan II manual for the DMA transfer I have to give a start adress which is any location in the on-board RAM . I have to place the data in the location and then send some configuration commands . Also transfer can take place between powerpc and the pci .I dont want to use powerpc or the on-board RAM . Is nt there a way where I can send data from my module directly to the host pc RAM instaed of sending it via on-board RAM. I have no experience in this area and always get stuck somewhere or the other. I had started with device driver and also was going through the powerspanII manual when I came across this doubt. How exactly a DMA transfer is done from a FPGa in a fpga PCI card to the host pc. I would appreciate any comments on this . Thanks, NiteshArticle: 94199
"Brian Davis" <brimdavis@aol.com> schrieb im Newsbeitrag news:1136552186.711153.183580@g44g2000cwa.googlegroups.com... > Antti Lukats wrote: >> >> you could try there >> http://www.xilinx.com/s3ediscount >> but I am afraid it may as well not lead to the actual online entry form >> :( >> > > I received the sample pack in the mail yesterday (from Avnet/US); > the $25 discount offer on the case says it's valid until the end of > January, but if you click the link it says: > "The introductory pricing period for the Spartan-3E Kit is now over" > > Over before it started, eh... > > The other funny thing was, when I took the board out of the case there > was a strategically placed piece of electrical tape on the board whose > only purpose seemed to be to obscure the "Linear Technology" logo > on the silkscreen. > > The card has pads for four of the new Digilent 6 pin I/O headers, > plus one of those %#@$&!! forty pin, one ground I/O headers. > > have fun, > Brian > we are (having fun) Brian would you be interested to beta-test a standalone utility to configure the sample Pack? we are currently working on the auto-fix of bitstream startup clock, etc, and and having some problems with auto-CRC in the compressed bitstreams, but the main functions already work, so if you have a parallel cable III or compatible you can use the utility. I assume the EDK/XPS/XMD flow for Flash programming also works but it is really not and easy way to reflash the board. http://xilant.com/content/view/28/51/ I can send you discount reigstration code for the s3e Starterkit discount, well I dont know if that is valid either (but I am not going to use it anyway) -- 6pin headers, actually there are 5 of them, the JP1 has same pinout but only 1 I/O and 3 Input only the 40 pin header, funny 1 ground, and 5 unconnected pins !! Antti
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