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Messages from 105825

Article: 105825
Subject: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
From: Ray Andraka <ray@andraka.com>
Date: Tue, 01 Aug 2006 10:24:13 -0400
Links: << >>  << T >>  << A >>
heinerlitz@gmx.de wrote:
> HI,
> 
> thanks for your good replys. So you mean that the FIFO16 should be work
> fine as they use counters instead of the empty/full flags. Thats good.
> 

> 
This is not true.  Even if you use do not use the fifo flags, they are 
used internally.  The FIFO16 cannot be used reliably if the input and 
output clocks are not phase locked to one another with a phase offset 
between them.  This means you can't use the FIFO16 to cross clock 
domains.  Using it synchronously, you have to have a phase offset 
between the read clock and the write clock, which is easiest to do by 
using not clock for one of those.


Article: 105826
Subject: Re: XPS 7.1 to 8.1 Warnings
From: "MM" <mbmsv@yahoo.com>
Date: Tue, 1 Aug 2006 10:34:15 -0400
Links: << >>  << T >>  << A >>
"Kyle H." <kyle.hable@gmail.com> wrote in message
news:1154441984.237461.155880@m73g2000cwd.googlegroups.com...
>
> Any insight to how I can fix these errors?

You can ignore these warnings, but if you want to get rid of them edit the
MPD files. Just delete whatever the tool says is unknown.

/Mikhail



Article: 105827
Subject: Re: XPS 7.1 to 8.1 Warnings
From: "Kyle H." <kyle.hable@gmail.com>
Date: 1 Aug 2006 07:35:12 -0700
Links: << >>  << T >>  << A >>
After looking into the warnings a bit, I noticed some problems with the
mpd file.

PORT OPB_Clk = "", DIR = IN, SIGIS = CLK, TYPE = NOBUS, ASSIGNMENT =
REQUIRE
replaced with:
PORT OPB_Clk = "", DIR = IN, SIGIS = CLK, ASSIGNMENT = REQUIRE

PORT SYS_Rst = "", DIR = IN, TYPE = NOBUS, ASSIGNMENT = REQUIRE
replaced with:
PORT SYS_Rst = "", DIR = IN, ASSIGNMENT = REQUIRE

PORT RGMII_RXD      = "", DIR=I, VEC[3:0]
replaced with:
PORT RGMII_RXD      = "", DIR=I, VEC=[3:0]


Were these warnings just generated though the tools modifying these
files?  What's the mpd file for?


Article: 105828
Subject: Re: Usage of DDR IOBs
From: "johnp" <johnp3+nospam@probo.com>
Date: 1 Aug 2006 07:49:17 -0700
Links: << >>  << T >>  << A >>
I believe you can infer input DDR flops, at least in Verilog.
You need to be careful since the Xilinx tools are picky
about infering IOB registers - if you don't do thing just
right, the tools won't infer the registers in the IOB.

In Verilog:
always @(posedge clk)
  in_p <= io_pin;
always @(neged clk)
  in_n <= io_pin;


NOTE that you may get better timing results if you use the CLK0
and CLK180 from a DCM - this helps avoid clock duty cycle distortion.

I don't know of a way to infer DDR output flops - it seems like the
XIlinx
tools should also easily do this, but I've never been able to get it
to work, I always instantiate output DDR flops.

Good luck,

John Providenza
Jim Wu wrote:
> Below are directly copied from the library guide:
>
> VHDL Instantiation Template
> -- IFDDRRSE: Double Data Rate Input Register with Sync. Clear,
> -- Sync. Preset
> -- and Clock Enable. Virtex-II/II-Pro, Spartan-3
> -- Xilinx HDL Libraries Guide version 7.1i
> IFDDRRSE_inst : IFDDRRSE
> port map (
> Q0 => Q0, -- Posedge data output
> Q1 => Q1, -- Negedge data output
> C0 => C0, -- 0 degree clock input
> C1 => C1, -- 180 degree clock input
> CE => CE, -- Clock enable input
> D => D, -- Data input (connect directly to top-level port)
> R => R, -- Synchronous reset input
> S => S -- Synchronous preset input
> );
> -- End of IFDDRRSE_inst instantiation
> Verilog Instantiation Template
> // IFDDRRSE: Double Data Rate Input Register with Sync. Clear, Sync.
> // Preset and Clock Enable. Virtex-II/II-Pro, Spartan-3
> // Xilinx HDL Libraries Guide version 7.1i
> IFDDRRSE IFDDRRSE_inst (
> .Q0(Q0), // Posedge data output
> .Q1(Q1), // Negedge data output
> .C0(C0), // 0 degree clock input
> .C1(C1), // 180 degree clock input
> .CE(CE), // Clock enable input
> .D(D), // Data input (connect directly to top-level port)
> .R(R), // Synchronous reset input
> .S(S) // Synchronous preset input
> );
> // End of IFDDRRSE_inst instantiation
>
> HTH,
> Jim
> http://home.comcast.net/~jimwu88/tools/
>
>
> Venkat wrote:
> > Hello Heiner,
> > Thanks for your response. I guess this option of IDDR will work for
> > Virtex 4 FPGA. However my FPGA of interest is Virtex II Pro. I am sorry
> > for not mentioning the type of device in my earlier mail. I will
> > appreciate your further suggestions.
> >
> > Kind regards,
> > Venkat.
> >
> > heinerlitz@gmx.de wrote:
> > > HI,
> > >
> > > you just instantiate the iddr buffer and drive it with a single SDR
> > > clock. You dont need the 180phase clk. The idddr then provides the data
> > > on the two output data busses. One data value at the positive clk edge
> > > and one at the negative clock edge.
> > > 
> > > heiner


Article: 105829
Subject: FPGA LABVIEW programming
From: "john" <conphiloso@hotmail.com>
Date: 1 Aug 2006 08:16:13 -0700
Links: << >>  << T >>  << A >>
Hello,
National instruments has introduced new module in their labview 8 for
programming the xilinx FPGA chips. It converts the labview programs
into VHDL . It can borrow image processing libraries from the labview
too. I was wondering that if somebody has used this module form labview

can give me details about it. 
Thanks 
Regards 
John


Article: 105830
Subject: Re: XPS 7.1 to 8.1 Warnings
From: "Kyle H." <kyle.hable@gmail.com>
Date: 1 Aug 2006 08:47:29 -0700
Links: << >>  << T >>  << A >>
Now I'm trying to build the first project and I get swamped with
warnings and errors.  I decided to check out the errors first.

The first Error I get.

ERROR:MDT - wrong # args: should be "source fileName"

Has something to do with sourcing the tcl file.  I check the tcl file's
that come up in the rest of the error, and they have barley anything
inside them:

proc check_iplevel_settings {mhsinst} {
    # check bus connectivity will be done in platgen
}

It seems like the rest of these errors have something to do with the
tcl file.  Any insight as to my new problem?


Article: 105831
Subject: Re: Problems compiling with ISE Webpack 8.2.01i
From: Duane Clark <junkmail@junkmail.com>
Date: Tue, 01 Aug 2006 16:02:57 GMT
Links: << >>  << T >>  << A >>
aijazbaig1@gmail.com wrote:
> Hello Freinds.
> I am a newcomer to the field of programmable logic devices and I am
> currently trying to teach myself VHDL. I hope to learn some VHDL before
> the next semester starts.
> My sole purpose as of now is not to actually synthesise stuff but just
> to simulate the various designs that I may try to create. I am using
> the xilinx ISE webpack 8.2 on a windows XP machine.
> Below I am trying to implement a design called ones_cnt wherein the
> counter just counts the number of ones in a 4 bit array and prints the
> result in a binary format.To understand the concept of configuration
> declarations I have declared multiple architectures and I am trying to
> use the configuration declaration statement to select one the them.
> 
> Heres my code. Its a lil big may be but I hope you guys would have a
> look.
> 

> ...
> use work.all; ----- this is the line where the error is flaged!! see
> below for details.


> ...
> Heres the log report generated by the compiler:
> Started : "Check Syntax".
> Running vhpcomp
> Compiling vhdl file "E:/Xlinx_ISE/workbench/ones_cnt.vhd" in Library
> isim_temp.

I don't know where the library name isim_temp came from. Did you specify 
that somewhere? The default name is normally "work" and it is generally 
best to leave it that way.

If you really want to use a different name for some reason, then in the 
line above that generates the error, you would want to change it to:
use isim_temp.all;

As mentioned, generally you always want to compile entities into a 
directory named work. There is certainly no reason for a beginner to do 
differently. Then, if the entities you are using are part of the current 
project, the "use work.all;" will get them fine.

If you also want to use entities that were compiled elsewhere, that is 
libraries, then you will have a file that provides a mapping. In 
Modelsim, the file is named modelsim.ini, or project_name.mpf. I don't 
know about the simulator you are using, but if it is not Modelsim, it 
will have some similar process. There, it will map a library name used 
in the current directory to the work directory where your library 
actually is located:
[Library]
sse_mezz_lib = ../../sse_mezz/sseio_hdl/work
Notice that the library files are also compiled into a directory named 
work, but it is a work directory in a different location from the 
current project.

Article: 105832
Subject: Re: 100m JTAG cable
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Tue, 01 Aug 2006 18:44:01 +0200
Links: << >>  << T >>  << A >>
Uwe Bonnes schrieb:

>>The speed setting in impact apparently doesn't apply to my Parallel
>>Cable 3.
> 
> 
>>>Another option beside the USB Extender is to convert the levels to a
>>>RS422/485 signal and use a twisted pair cable.
> 
> 
> The FTDI FT2232 happily generates serial protocols. I have a modified version
> of Andrew Rogers's xc3sprog thats talks JTAG to XC3S and XCF via FT2232. It
> knows about JTAG speed. Let me know if you are interested (and willing to
> give feedback).

I guess the point is, that the OP want a quick & dirty solution, wich is 
most probably not possible due to the high delay of 100m cable (which is 
~500ns). Even optical fiber would be that slow.

Regards
Falk

Article: 105833
Subject: Re: FPGA LABVIEW programming
From: "Marco T." <marc@blabla.com>
Date: Tue, 1 Aug 2006 19:43:45 +0200
Links: << >>  << T >>  << A >>

"john" <conphiloso@hotmail.com> wrote in message 
news:1154445373.826354.312250@75g2000cwc.googlegroups.com...
> Hello,
> National instruments has introduced new module in their labview 8 for
> programming the xilinx FPGA chips. It converts the labview programs
> into VHDL . It can borrow image processing libraries from the labview
> too. I was wondering that if somebody has used this module form labview
>
> can give me details about it.
> Thanks
> Regards
> John
>

please don't post in multiple newsgroup.

Marco 



Article: 105834
Subject: Re: Where are Huffman encoding applications?
From: Jack Klein <jackklein@spamcop.net>
Date: Tue, 01 Aug 2006 12:53:03 -0500
Links: << >>  << T >>  << A >>
On 1 Aug 2006 04:02:31 -0700, "Weng Tianxiang" <wtxwtx@gmail.com>
wrote in comp.programming:

> Hi,
> I want to know how many fields Huffman encoding thoery are used.
> 
> As I can counted,
> 1. In Window operating system, similar encoding is used to conpress
> text files;
> 2. Text compression in ZIP files;
> 3. JPEG fram compression;
> 4. MPEG format compression? which one uses it?
> 
> Wireless communication?
> 
> Any other applications?
> 
> Thank you.
> 
> Weng

FAX transmission, although the Huffman codes are predefined and not
generated dynamically from the data.

-- 
Jack Klein
Home: http://JK-Technology.Com
FAQs for
comp.lang.c http://c-faq.com/
comp.lang.c++ http://www.parashift.com/c++-faq-lite/
alt.comp.lang.learn.c-c++
http://www.contrib.andrew.cmu.edu/~ajo/docs/FAQ-acllc.html

Article: 105835
Subject: Re: FPGA LABVIEW programming
From: "john" <conphiloso@hotmail.com>
Date: 1 Aug 2006 11:18:59 -0700
Links: << >>  << T >>  << A >>
Hi,

I posted in multiple groups becuase the fuzzy nature of the question.
The question belongs to labview people, VHDL people and hardware FPGA
people plus its my right to post question in any group I want. IF U
DONT WANT TO ANSWER IT THEN DO NOT BOTHER OK!
Regards
Marco T. wrote:
> "john" <conphiloso@hotmail.com> wrote in message
> news:1154445373.826354.312250@75g2000cwc.googlegroups.com...
> > Hello,
> > National instruments has introduced new module in their labview 8 for
> > programming the xilinx FPGA chips. It converts the labview programs
> > into VHDL . It can borrow image processing libraries from the labview
> > too. I was wondering that if somebody has used this module form labview
> >
> > can give me details about it.
> > Thanks
> > Regards
> > John
> >
> 
> please don't post in multiple newsgroup.
> 
> Marco


Article: 105836
Subject: Re: Accessing one SDRAM from two MicroBlazes
From: quickwayne@gmail.com
Date: 1 Aug 2006 11:54:56 -0700
Links: << >>  << T >>  << A >>

Siva Velusamy wrote:
> quickwayne@gmail.com wrote:
> >>>
> >>>These DATA must be accessed by a second MicroBlaze for multiple
> >>>calculations.
> >>>
> >>>Does Xilinx provide such a multiple access on external memory ?
> >>>Which kind of Memory can you suggest ?
> >>>
> >>>
> >>>Thanks a lot,
> >>>by
> >>>BEN
> >>>
> >>
> >>Try mch_opb_[sdram|ddr] controllers that come with EDK. You should be
> >>able to connect two MB's directly to memory and an OPB channel for
> >>peripheral accesses to memory.
> >>
> >>/S
> >
> >
> > Hello Siva,
> >
> > Do you mean connect all two MB and sdram controller to one OPB bus? Is
> > it possible without arbitrator or you mean something else. I am working
> > on a similar project and thinking of making an arbitrator myself.
> > Thanks for your information.
> >
> > Wayne
> >
>
>
> MicroBlaze version 3 and above allow a direct connection from the I & D
> caches to memory. This channel is called XCL. This provides better
> performance since the protocol over this channel is optimized for cache
> accesses (cacheline bursts & target word first). The memory controllers
> that have this XCL interface are called mch memory controllers -
> mch_sdram/emc/ddr.
>
> So your configuration would like this:
>
> MB1 - i-XCL and d-XCL connected to channels 0 & 1 of mch_sdram
> MB2 - i-XCL and d-XCL connected to channels 2 & 3 of mch_sdram
> OPB and opb peripherals connected to OPB channel (4) of mch_sdram.
>
> The arbitration between the 5 ports (4 XCL, 1 OPB) is done inside the
> memory controller, so you wouldn't have to write any arbitration logic.
>
> In case you want to attach many many more masters to the OPB, even then
> you wouldn't have to write any arbitration logic, since it is included
> in the OPB logic itself.
>
> /Siva

Hi Siva,

Thank you for your information. The MultiCHannel controller is eally an
interesting design and good news for me.

For OPB, I ever tried to connect to Microblaze to one OPB bus but it
didn't work. After I disabled one Microblaze it works. Could you
suggest what's wrong with my design. Thanks for your help.

Sunwei

For


Article: 105837
Subject: Re: Sorting algorithm for FPGA availlable?
From: fpga_toys@yahoo.com
Date: 1 Aug 2006 12:10:54 -0700
Links: << >>  << T >>  << A >>

Kolja Sulimma wrote:
> Smaller datasets can be sorted in hardware by systolic priority queues
> as fast as you can input the data.

You can also sort the words bit serial using a log2(N) array of muxes
for each serial input. This strategy has a serial latency of log2(N) to
the first bit, plus word length clocks, and can be built as wide as you
want it. It's easily reused as part of a block sort.

http://svn.sourceforge.net/viewvc/fpgac/trunk/fpgac/examples/pipelines/BitSer.c?revision=10&view=markup

The strategy is a two input, two output muxes that passes bits through
as pairs. Each bit is compared, and on the first difference, the mux
selector is latched so that the low value  bit stream passes to the
left. The mux selectors are reset on a word flag. With a log2 mux
arrangement, each mux layer sorts with a stream offset of 2, 4, 8, ...,
2^N

Depending on the FPGA, the self selecting bit muxes are a few LUTs
each, making the total cost of the sort engine N * log2(N) * K (where K
is the number of LUTs per bit mux).


Article: 105838
Subject: Re: 100m JTAG cable
From: Jim Granville <no.spam@designtools.co.nz>
Date: Wed, 02 Aug 2006 07:52:25 +1200
Links: << >>  << T >>  << A >>
jvdh wrote:
> Uwe:
> 
> 
>>Isn't there an option to set the JTAG CLK speed in impact?
> 
> The speed setting in impact apparently doesn't apply to my Parallel
> Cable 3.

  I'd ask Xilinx about this. What you are trying to do may be 
specialised, but this ability to tolerate slower links has quite 
widespread applications - for example, opto isolated JTAG could have 
similar delays.
  It sounds like an easy thing to fix, if you can get at the right place
in the software :)


> 
>>Another option beside the USB Extender is to convert the levels to a
>>RS422/485 signal and use a twisted pair cable.
> 
> 
> This is exactly what i'm doing, with an RS485 driver and receiver on
> each end of my cable. I'm getting 230kbps on the system for serial
> communication:), but I think my transmission delay is too large for
> Impact to be happy.  I measured the duration of a clock pulse to be as
> little as 1us - with a delay of 800ns, the reading of data fails.
> 
> Jim:
> Hazardous as in high energy particles, especially protons and neutrons.
>  The board will be used to test radiation tolerance techniques, but
> background radiation is too high to put a PC nearby for control. (and
> want to use it afterwards:)  It is inside a faraday cage, so even very
> high speed wireless options are also out.
> 
> I'm using a differential line pair for every input signal - the R485 is
> only used as a repeater and receiver pair, with no other 485 protocol
> on top of it.

any large magentic fields ? - I think you may still need isolation, as 
the common mode tolerance of RS485 is only around -7V/+12V - which is 
not a large spike....

> 
> Right now I'm looking into the open source options, hoping I can do
> (slower) readback with openwince-jtag.

That may be the best path.

-jg


Article: 105839
Subject: Implementing Haar Decomposition on 256 sample input using only sysgen blocks
From: "Siri" <sirisha.aluru@gmail.com>
Date: 1 Aug 2006 12:57:34 -0700
Links: << >>  << T >>  << A >>
Hi everyone,
i m trying to implement the haar basis decomposition ona  big signal
and need to build a model using Xilinx sysgen blocks only, can anyone
help me with the code or any suggestions regarding blocks i can use...i
have an idea of implementing this as a matrix multiplication (parellel
implementation) .....any suggestions?


Article: 105840
Subject: Re: 100m JTAG cable
From: "jvdh" <johannes.vanderhorst@gmail.com>
Date: 1 Aug 2006 13:22:53 -0700
Links: << >>  << T >>  << A >>
Jim Granville wrote:
>  any large magentic fields ? - I think you may still need isolation, as
>  the common mode tolerance of RS485 is only around -7V/+12V - which is
>  not a large spike....

Not whre I'm working - I'm staying relatively far away from the actual
beam line, and a previous experiment we had (without the JTAG) didn't
show significant magnetic effects.

Uwe Bonnes schreib:
> The FTDI FT2232 happily generates serial protocols. I have a modified version
> of Andrew Rogers's xc3sprog thats talks JTAG to XC3S and XCF via FT2232. It
> knows about JTAG speed. Let me know if you are interested (and willing to
> give feedback).
>

Thanks for reminding me of x3sprog - I had used it a while ago, but
couldn't define a narrow enough search to find it on google again,
until you gave me the name now.

But, I've now downloaded it again, and it happily identifies the JTAG
chain and handles the downloading of data.  (so I'm feeling GOOD right
now).

Next problem:  Readback.  The whole purpose behind JTAG is to get the
configuration data back to the computer, to check what's going on...
And x3sprog doesn't support readback.

This modified version of yours doesn't perhaps have readback
implemented?

Otherwise I can see myself spending tonight extending either x3sprog to
do readback, or openwince-jtag (to support my programmer)...  (Or
disguising my jtag3 cable as a parallel 3 cable)

Thanks for everybody's suggestions and support!


Article: 105841
Subject: Re: 100m JTAG cable
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Tue, 1 Aug 2006 20:58:20 +0000 (UTC)
Links: << >>  << T >>  << A >>
jvdh <johannes.vanderhorst@gmail.com> wrote:
> Jim Granville wrote:
> >  any large magentic fields ? - I think you may still need isolation, as
> >  the common mode tolerance of RS485 is only around -7V/+12V - which is
> >  not a large spike....

> Not whre I'm working - I'm staying relatively far away from the actual
> beam line, and a previous experiment we had (without the JTAG) didn't
> show significant magnetic effects.

> Uwe Bonnes schreib:
> > The FTDI FT2232 happily generates serial protocols. I have a modified version
> > of Andrew Rogers's xc3sprog thats talks JTAG to XC3S and XCF via FT2232. It
> > knows about JTAG speed. Let me know if you are interested (and willing to
> > give feedback).
> >

> Thanks for reminding me of x3sprog - I had used it a while ago, but
> couldn't define a narrow enough search to find it on google again,
> until you gave me the name now.

> But, I've now downloaded it again, and it happily identifies the JTAG
> chain and handles the downloading of data.  (so I'm feeling GOOD right
> now).

> Next problem:  Readback.  The whole purpose behind JTAG is to get the
> configuration data back to the computer, to check what's going on...
> And x3sprog doesn't support readback.

> This modified version of yours doesn't perhaps have readback
> implemented?

> Otherwise I can see myself spending tonight extending either x3sprog to
> do readback, or openwince-jtag (to support my programmer)...  (Or
> disguising my jtag3 cable as a parallel 3 cable)

If you implement readback, let me know :-)

Another obscure idea. It seems you run on linux. Impact via windriver uses
/dev/parport to access the parallel port. Define inp() and outport() with an
appropriate delay function, recompile and reload the module to get slower
jtag access. Perhaps even make the delay configurable via
/proc/sys/dev/parport/parport0/
:-)


-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 105842
Subject: Re: 100m JTAG cable
From: "jvdh" <johannes.vanderhorst@gmail.com>
Date: 1 Aug 2006 14:21:49 -0700
Links: << >>  << T >>  << A >>

Uwe Bonnes wrote:

> Another obscure idea. It seems you run on linux. Impact via windriver uses
> /dev/parport to access the parallel port. Define inp() and outport() with an
> appropriate delay function, recompile and reload the module to get slower
> jtag access. Perhaps even make the delay configurable via
> /proc/sys/dev/parport/parport0/
> :-)

It might be obscure, it might be late, but it's attractive in a
deliciously perverse way... :)  Although I fear it might fail if the
delay is specified inside impact - they have the frequency setting for
the other programmers, so I don't think they are merely depending on
the delays in windriver???  (I dream of the day when an FPGA
manufacturer decides to put their software on sourceforge...)

Looking through the x3sprog code, it seems (touching wood, making sure
that I'm not discharging static electricity onto a sensitive CMOS
device) relatively simple to add the readback code.  I've also spent a
fair amount of time on getting to know the configuration interface of
Spartan 3, so I'm a happy coder right now!

Will keep you up to date...

johannes


Article: 105843
Subject: Re: Where are Huffman encoding applications?
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 1 Aug 2006 15:15:16 -0700
Links: << >>  << T >>  << A >>
Hi Jack,
Fax application cannot be counted as full Huffman encoding. The reason
is the statistics for characters are not dynamically collected.

Thank you.

Weng

Jack Klein wrote:
> On 1 Aug 2006 04:02:31 -0700, "Weng Tianxiang" <wtxwtx@gmail.com>
> wrote in comp.programming:
>
> > Hi,
> > I want to know how many fields Huffman encoding thoery are used.
> >
> > As I can counted,
> > 1. In Window operating system, similar encoding is used to conpress
> > text files;
> > 2. Text compression in ZIP files;
> > 3. JPEG fram compression;
> > 4. MPEG format compression? which one uses it?
> >
> > Wireless communication?
> >
> > Any other applications?
> >
> > Thank you.
> >
> > Weng
>
> FAX transmission, although the Huffman codes are predefined and not
> generated dynamically from the data.
>
> --
> Jack Klein
> Home: http://JK-Technology.Com
> FAQs for
> comp.lang.c http://c-faq.com/
> comp.lang.c++ http://www.parashift.com/c++-faq-lite/
> alt.comp.lang.learn.c-c++
> http://www.contrib.andrew.cmu.edu/~ajo/docs/FAQ-acllc.html


Article: 105844
Subject: Re: Issues w/ 8 lane Aurora sample design
From: "billu" <bkamakot@gmail.com>
Date: 1 Aug 2006 15:18:25 -0700
Links: << >>  << T >>  << A >>
Hi Duane,

Thx for your response.

I modified the code to a 2 MGT configuration to make it easier to
troubleshoot. A 2 MGT link setup using just top MGTs/Clock works fine,
but I get the same error when I use a top MGT and a bottom MGT. Again,
it seems to work w/ the XC2VP30-FF896. (changed settings in ISE and ucf
file accordingly)

I'm only dealing w/ BREFCLK and BREFCLK2 b/c I want to operate in
speeds excess of 2.5Gbps. I see a "REF_CLK_V_SEL" entry in the ucf
file, which is set to '1'. In the aurora module (aurora_link.v;
instantiated twice for the MGTs), I see a section of code commented as
Reference Clocks. BREFCLK is tied to TOP_BREF_CLK, and the others are
tied to ground. I'm planning on using TOP_BREF_CLK for the top MGT and
BOTTOM_BREF_CLK2 for the bottom MGT.REFCLKSEL is set to 1'b0. I'm
guessing it can only be set once, since the same core is being
instantiated twice.

In the verilog code, TOP_BREF_CLK is assigned to top_BREF_CLK_i in the
1st module (top MGT) and TOP_BREF_CLK is assigned bottom_BREF_CLK_i in
the 2nd module (bottom MGT). THe aurora module was generated in Core
generator using BREFCLK and a MGT in the top row.

I tried to change those attributes, but I still get the same error. Any
pointers?

Thanks,
Billu

Duane Clark wrote:
> billu wrote:
> > Yeah, definitely changed that.
> >
> > I changed the settings to ML310 board (XC2VP30-FF896) to see if I can
> > find any cues to the problem. I changed phase align module and clock
> > pins in the ucf file and the compilation goes through fine. I cant
> > really find any board specific settings/properties in the code
>
> Several things change in the source when you select a different clock
> source, at least when using the GT_CUSTOM core and Aurora2.3, assuming
> that is what the 8 lane sample uses.
>
> The input clock signal itself needs to be tied to the the right input to
> GT_CUSTOM; that is one of the 4 B/REFCLK/2 pins.
>
> The input REFCLKSEL needs to reflect the selection. It is '1' for
> B/REFCLK2 and '0' for B/REFCLK.
>
> The generic (in VHDL) REF_CLK_V_SEL is 1 for REFCLK/2 and 0 for BREFCLK/2.


Article: 105845
Subject: Re: Implementing Haar Decomposition on 256 sample input using only sysgen blocks
From: "Marc Reinig" <Marco@newsgroups.nospam>
Date: Tue, 1 Aug 2006 15:20:15 -0700
Links: << >>  << T >>  << A >>
A google of "harr fpga" came up with lots of hits.  Here is the first

http://www.klabs.org/mapld05/presento/199_chandrasekaran_p.ppt


-- 
Marco
________________________
Marc Reinig
UCO/Lick Observatory
Laboratory for Adaptive Optics

"Siri" <sirisha.aluru@gmail.com> wrote in message 
news:1154462254.027845.19640@p79g2000cwp.googlegroups.com...
> Hi everyone,
> i m trying to implement the haar basis decomposition ona  big signal
> and need to build a model using Xilinx sysgen blocks only, can anyone
> help me with the code or any suggestions regarding blocks i can use...i
> have an idea of implementing this as a matrix multiplication (parellel
> implementation) .....any suggestions?
> 



Article: 105846
Subject: Re: 100m JTAG cable
From: Jim Granville <no.spam@designtools.co.nz>
Date: Wed, 02 Aug 2006 10:36:16 +1200
Links: << >>  << T >>  << A >>
jvdh wrote:
> Uwe Bonnes wrote:
>>Another obscure idea. It seems you run on linux. Impact via windriver uses
>>/dev/parport to access the parallel port. Define inp() and outport() with an
>>appropriate delay function, recompile and reload the module to get slower
>>jtag access. Perhaps even make the delay configurable via
>>/proc/sys/dev/parport/parport0/
>>:-)
> 
> It might be obscure, it might be late, but it's attractive in a
> deliciously perverse way... :)  Although I fear it might fail if the
> delay is specified inside impact - they have the frequency setting for
> the other programmers, so I don't think they are merely depending on
> the delays in windriver???  (I dream of the day when an FPGA
> manufacturer decides to put their software on sourceforge...)

'All' FPGA software could have issues, but yes, there IS a strong case 
for placing this level of software on sourceforge.

  It has very low risk exposure, no trade secrets ( it is a transport 
layer only ), but has good benefits : More users can deploy their FPGAs 
in areas they have not thought of - and THAT has to be good for business!
  That means the designer community can do slower, (and faster!), JTAG 
variants.

Austin ? - or anyone in Xilinx willing to shake the tree a little ?

-jg


Article: 105847
Subject: Programmable pulse generator
From: jimwalsh142@hotmail.com
Date: 1 Aug 2006 15:38:06 -0700
Links: << >>  << T >>  << A >>
Hi All,

I'm trying to develop a programmable pulse generator, essentially a
single pulse of variable width repeated at a given rate. I posted a
similar question a few weeks ago on sci.elec.design and someone
suggested that this would make a nice CPLD project. As I'm keen to
learn about programmable logic devices I decided to buy a development
kit (Altera 7000 series) and try implementing the pulse generator.

My ideal specification would be pulse widths from 10ns to 10us
incremented in 10ns steps at repetition rates between 1 to 10 kHz. The
evaluation board has a 25MHz clock so I'm limited to 40ns increments
but that's ok for now.

I've been playing around with various counters etc but am struggling
to create anything useful, would be great if someone more experienced
could give me a few hints!?

Thanks,

Jim W


Article: 105848
Subject: Re: 100m JTAG cable
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 01 Aug 2006 15:52:01 -0700
Links: << >>  << T >>  << A >>
Jim,

Been down that road (making any software source public).  Nope.  Dead
end.  I have more useful things to attend to right now.

There are already many vendors that support JTAG, and the BSDL files are
their for them (or you).  Feel free to buy and use their software
instead of ours.  I am sure it can be made better than ours, and provide
more features than ours does.

I would not want to appear to be competing with these vendors, nor
making their business any less profitable.

Austin

Article: 105849
Subject: Re: Programmable pulse generator
From: =?UTF-8?B?R8OzcnNraSBBZGFt?=
Date: Wed, 02 Aug 2006 01:17:40 +0200
Links: << >>  << T >>  << A >>
Użytkownik jimwalsh142@hotmail.com napisał:
> Hi All,
> 
> I'm trying to develop a programmable pulse generator, essentially a
> single pulse of variable width repeated at a given rate. I posted a
> similar question a few weeks ago on sci.elec.design and someone
> suggested that this would make a nice CPLD project. As I'm keen to
> learn about programmable logic devices I decided to buy a development
> kit (Altera 7000 series) and try implementing the pulse generator.
> 
> My ideal specification would be pulse widths from 10ns to 10us
> incremented in 10ns steps at repetition rates between 1 to 10 kHz. The
> evaluation board has a 25MHz clock so I'm limited to 40ns increments
> but that's ok for now.
> 
> I've been playing around with various counters etc but am struggling
> to create anything useful, would be great if someone more experienced
> could give me a few hints!?
> 
> Thanks,
> 
> Jim W
> 

Hi,

I can do  it for you.
Let me know how you want to set parameters - parallel interface to 
microcontroller , microprocessor or serial controll ?


Adam



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