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"skyworld" <chenyong20000@gmail.com> wrote in message > news:1170036313.133462.61950@v33g2000cwv.googlegroups.com... > Hi, > My design is like this: the data is a serial data stream with data > rate at 312MHz. The sampling circuitry works at 312MHz also, but there > are four clocks to sample the data; each clock works at 312MHz, with > equal spaced phase shift, i.e., 312MHz with 0 degree, 312MHz with 90 > degree, 312MHz with 180 degree and 312MHz with 270 degree. A logic > cell will be used to detect the transition between these four clocks > and determines which clock will be used to sample the data. Well, I recommend using Google before reinventing the wheel. XAPP224. :-) HTH, Syms.Article: 115001
On 28 Jan 2007 15:39:20 -0800, "Weng Tianxiang"
<wtxwtx@gmail.com> wrote:
>I want a global error signal to indicate the situation and I am not
>interested in complex design and all FIFO will be called using one
>simple module.
>
>The global error signal applies not only to FIFOs, but also to any
>module if there is an error situation happening and it will indicate:
>Hi, it is error here in this clock !!! Using this signal will greatly
>reduce error debugging time also.
Weng,
If this is for simulation only, then you can use global signals.
We have, in the past, suggested using an array of global
signals, one for each instance that you are debugging. You can
then attach a generic to each instance, and use it to determine
which signal is driven by that instance:
package DEBUG_SUPPORT is
signal s: std_logic_vector(1 to 100);
end package DEBUG_SUPPORT;
use work.DEBUG_SUPPORT;
entity DEBUG_ME is
generic (DEBUG_ID: natural := 0);
port (....);
end;
architecture TRACEABLE of DEBUG_ME is
-- Internal signal that reflects the error condition
signal HIGH_WHEN_ERROR: std_logic;
begin
...
... all your other stuff
...
DEBUG_TRACING: if DEBUG_ID > 0 generate
DEBUG_SUPPORT.s(DEBUG_ID) <=
'1' when HIGH_WHEN_ERROR = '1'
else '0';
end generate;
end;
However, that's a little messy because you must now use a
complicated hierarchical configuration to assign the right
generic value to each instance. An alternative possibility
is to use a resolved signal for just one global debug signal.
I don't have time to sketch that out now, but if the generics
method doesn't work for you, reply to this and I'll try to post
an example in the next day or two.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 115002"Georg Acher" <acher@in.tum.de> wrote in message news:epgl8q$nek$1@news.lrz-muenchen.de... > > XAPP 780 contains a random bit stream generator with ring-oscillators and > some > "metastability" logic. > > -- Hi Georg, Thanks for that link, it's interesting. Of course, the method described in this XAPP note only protects the design from cloning. It's not going to be impossible to reverse engineer the configuration bit stream and find the secret key in the FPGA. In fact, doesn't this method of attack defeat the random number generator thing in all application? If an attacker has physical access to the design, I think the Vbatt RSA key thing is the only 'secure' way to go, otherwise your configuration bitstream is there to see. Thanks, Syms.Article: 115003
"David" <dpmontminy@gmail.com> writes: > Hi, > > I'm trying to create a design that uses a LUT to control routing on a > Virtex-II Pro. It's pretty easy to create the LUT in VHDL and feed > it into a MUX to select the appropriate output based on the values in > the LUT. I'm trying to use this in a partial reconfiguration design > so that I can change the values in the LUT with a partial bitstream to > change the routing. My problem is that the design is optimized and > broken up in to multiple LUTs making it hard to determine what needs to > be changed. > > Is there any way to force the LUT to be left as a primitive and > implement the equations (or initial value) that I set? I would also > like to be able to force the LUT to be in known location so that I can > find it easily in the NCD file. I've seen plenty of documentation > staying this can be done, I can't find any exampled. I believe I can > use an RLOC but I'm not sure where the RLOC constraint should be > placed. In the past I've had to create LUTs and this bit of code allows you to do it with an equation, rather than figuring the init values out for yourself: -- -- Typical usage: -- -- signal a,b,c,d,x : std_logic; -- -- LU: VLut4 generic map ( ExprStr => "((I0*I1)@(I2*~I3))" ) -- port map (I0=>a, I1=>b, I2=>c, I3=>d, O=>x ); -- -- This evaluates the following expression: -- -- x <= (a and b) xor ( c and (not d)); -- I got it from: http://www.rockylogic.com/freebies.html The code is at: http://www.rockylogic.com/files/VirtexLut.vhd I guess a new version for Virtex-5 is now needed :-) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 115004
Thank you for all follow-ups. It seems to me that ring-oscillators and meta-stability are the "best" sources for weak (but true) on-chip randomness. I greatly appreciate the pointer to the XAPP780 appnote, and would like to add one that I found after Austins and Peters comments. Here's another ring-oscillator example source code: http://www.xilinx.com/products/boards/s3estarter/files/ s3esk_frequency_counter.pdf http://www.xilinx.com/products/boards/s3estarter/files/ s3esk_frequency_counter.zip So thanks again for all the valuable input! Regards, MarcArticle: 115005
Hi, I'm new to using the EDK and need some help. I'm working on a microblaze system which has become to big for the BRAM, and having done some research i realise i need a bootloader. What i have made out from the scraps of information i've read is: 1) Create a new software project which is the bootloader, this simply points to the external memory and says to the system, run this code. 2) program the FPGA as normal, with the bootloader program. 3) load data onto the external memory. 4) It should work. So my first question is, have i understood the principles correctly? Moving on from here i've been struggling to find any detailed tutorials/explinations about how to actually do this. Could someone either explain to me or point to a good tutorial? One more point, when i program my FPGA, i don't directly program the FPGA, i program a device which then with every boot of the development board programs the FPGA. I have a feeling this will affect the steps above(if they are correct in the first place) because i don't want to be manually loading data onto the external memories every time i start the thing running. My availible external memories are a DDR and a flash. Thanks in advanceArticle: 115006
Hi,
I tried to open a project that I created with ISE 7.1,
with ISE 8.2 (both with latest SP).
I get the following error:
ERROR:ProjectMgmt - TOE: ITclInterp::ExecuteCmd gave Tcl result
'couldn't duplicate input handle: bad file number'.
Tcl_ErrnoId: EBADF
Tcl_ErrnoMsg: bad file number
_cmd: source "C:/Xilinx_82/data/projnav/scripts/
dpm_migrateTasks.tcl"; ::xilinx::Dpm::migrateProject {->path to
project file}
errorInfo: couldn't duplicate input handle: bad file number
while executing
"exec "zip" -r $archiveName $archivePath"
(procedure "::xilinx::Dpm::migrateProject" line 18)
invoked from within
"::xilinx::Dpm::migrateProject {->path to project file}"
Can anyone help me with this, what can I do here?
Article: 115007On 29 Gen, 01:42, John Williams <jwilli...@itee.uq.edu.au> wrote: > You must substitute the instance name of your DDR/SDRAM controller into > the "MAIN_MEMORY=" line, and similarly for the stdout/stdin selections. > > The error message you received suggests that you have not specified the > MAIN_MEMORY paramter in your MSS file. > > You can use the XPS GUI to specifiy all of this - once you have chosen > the uClinux BSP, then you move to the next tab to customise it. It will > present options to you for setting the main_memory peripheral and so on. > > I hope this helps, > Ok, many thanks, in XPS I've set main memory on SRAM_256Kx32, main memory bank on 0, and flash memory on none (I'm using spartan 3 XC3S1000). Is it correct? Flash memory should be none? XC3S1000 has XCF04S (4 Mbit) configuration PROM. But I'm unable to set it in Software Platform Settings... Although this, now XPS has generated auto-config.in, I've set it in UNIX format, and put it in uclinux-auto folder. Make dep ends with no error, but make ends with /fs/binfmt_flat.c error in function decompress_exec... I don't know why... Do you know what kind of problem is this? Many thanks RegardsArticle: 115008
When I use DCM in virtex 5 and do the simulation, the modelsim 6.2e
gives the following error message:
Failure: (vsim-3808) Incompatible modes for port "clkfx_out".
# Time: 0 ps Iteration: 0 Instance: /..../dcm3_inst File: .../
dcm3.vhd Line: 31
# ** Failure: (vsim-3808) Incompatible modes for port
"clkin_ibufg_out".
# Time: 0 ps Iteration: 0 Instance: ....dcm3_inst File: .../dcm3.vhd
Line: 32
# ** Failure: (vsim-3808) Incompatible modes for port "clk0_out".
# Time: 0 ps Iteration: 0 Instance: ..../dcm3_inst File: ..../
dcm3.vhd Line: 33
# ** Failure: (vsim-3808) Incompatible modes for port "locked_out".
# Time: 0 ps Iteration: 0 Instance: ...../dcm3_inst File: ...../
dcm3.vhd Line: 34
I don't know why it told me "incompatible modes for port "clkfx_out".
They are all std_logic type and connected with the std_logic signals.
Tank you very much for your help,
Cathy
I generated the dcm file from the core generator 8.2.03i directly and
here is the .vhd code:
-----------------------------------------------------------------------
---------
-- Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
-----------------------------------------------------------------------
---------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 8.2.03i
-- \ \ Application : xaw2vhdl
-- / / Filename : dcm3.vhd
-- /___/ /\ Timestamp : 01/28/2007 16:17:47
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st F:\core\core8.2\CoreGen\dcm3.xaw F:\core
\core8.2\CoreGen\dcm3
--Design Name: dcm3
--Device: xc5vlx50-1ff676
--
-- Module dcm3
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity dcm3 is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end dcm3;
architecture BEHAVIORAL of dcm3 is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND1 : std_logic_vector (6 downto 0);
signal GND2 : std_logic_vector (15 downto 0);
signal GND3 : std_logic;
component BUFG
port ( I : in std_logic;
O : out std_logic);
end component;
component IBUFG
port ( I : in std_logic;
O : out std_logic);
end component;
-- Period Jitter (unit interval) for block DCM_ADV_INST = 6.67 UI
-- Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.38 ns
-- Period Jitter (unit interval) for block DCM_ADV_INST = 0.03 UI
-- Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.20 ns
component DCM_ADV
generic( CLK_FEEDBACK : string := "1X";
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := FALSE;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
DCM_AUTOCALIBRATION : boolean := TRUE;
DCM_PERFORMANCE_MODE : string := "MAX_SPEED";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DUTY_CYCLE_CORRECTION : boolean := TRUE;
FACTORY_JF : bit_vector := x"F0F0";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := FALSE);
port ( CLKIN : in std_logic;
CLKFB : in std_logic;
DADDR : in std_logic_vector (6 downto 0);
DI : in std_logic_vector (15 downto 0);
DWE : in std_logic;
DEN : in std_logic;
DCLK : in std_logic;
RST : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSCLK : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLKDV : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
DRDY : out std_logic;
DO : out std_logic_vector (15 downto 0);
LOCKED : out std_logic;
PSDONE : out std_logic);
end component;
begin
GND1(6 downto 0) <= "0000000";
GND2(15 downto 0) <= "0000000000000000";
GND3 <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_ADV_INST : DCM_ADV
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 3,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
DCM_AUTOCALIBRATION => TRUE,
DCM_PERFORMANCE_MODE => "MAX_SPEED",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "HIGH",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"F0F0",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DADDR(6 downto 0)=>GND1(6 downto 0),
DCLK=>GND3,
DEN=>GND3,
DI(15 downto 0)=>GND2(15 downto 0),
DWE=>GND3,
PSCLK=>GND3,
PSEN=>GND3,
PSINCDEC=>GND3,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
DO=>open,
DRDY=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open);
end BEHAVIORAL;
Article: 115009Gabor, Are you saying that I don't need to activate/precharge the bank when switching to another? I am kind of unclear on this. When do activate and precharge commands need to be issued? I thought when switching to a new row or bank you had to precharge (close) the previously active one, then activate the new row/bank before actually reading from or writing to it. Where am I going wrong here? Also to the notion that I don't need to refresh since I am doing video buffering: I am actually buffering multiple frames of video and then reading out several frames later. In other words, there may be a significant fraction of a second (say 1/8~1/4 sec) of delay between writing data into a particular page of memory and actually reading it back out. Is this too much time to expect my pixel data to still be valid without refreshing? On Jan 26, 6:03 pm, "Gabor" <g...@alacron.com> wrote: > On Jan 26, 3:15 pm, "wallge" <wal...@gmail.com> wrote: > > > I am not sure what you mean by two pass approach. > > The max (theoretical) bandwidth I have available to/from the SDRAM > > is about > > 16 bits * 100 Mhz = 1.6 Gbit/sec > > > This is not an achievable estimate of course, even if I only did full > > page > > reads and writes, since there is overhead associated with each. I also > > have to refresh periodically. > > > My pixel bit width could be brought down to 8 bits. That way I could > > store 2 > > pixels per address if need be.You may be missing an important feature of SDRAM. You don't need to > use full-page reads or writes to keep data streaming at 100% of the > available bandwidth (if you don't change direction) or very nearly 100% > (if you switch from read to write infrequently). This is due to the > ability > to set up another block operation on one bank while another bank is > transferring data. When I use SDRAM for relatively random operations > like this I like to think of the minimum data unit as one minimal burst > (two words in a single-data-rate SDRAM) to each of the four banks. > Any number of these data units can be strung one after another > with no break in the data flow. Then if you wanted to internally > buffer > a square section of the image in internal blockRAM the width > of the minimum block (allowing 100% data rate) would only be > 16 8-bit pixels or 8 16-bit pixels in your case. If the area can > cover the required computational core (4 x 4?) for several pixels > at a time, you can reduce overall bandwidth. This was the point > of suggesting an internal cache memory. > > HTH, > GaborArticle: 115010
"Weng Tianxiang" <wtxwtx@gmail.com> wrote: >Hi, >How to make an internal signal embedded deep in hierarchy to a gloal >output signal? > >I have an internal signal embedded deep in hierarchy showing there is >an error. I would like to see it at the top of hierarchy. > >How can I do it in VHDL? > >Do I have to do the foolish steps to transfer it one module to another >until the top level? If you want to connect it to a physical pin on the FPGA infer an output buffer. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 115011
Hi, I'm programming on a Spartan-II in ISE. I have a few questions about the clk signals and .ucf files. I have assigned my two clock signals PCI_CLK and DHSM_CLK to GCLKBUF0 and GCLKBUF1 respectively. However, when I compile it gives an error that PCI_RST should be assigned to a GCLK. Is this happening because a lot of logic is dependent on the RST? Also when I look at the clock report in Xilinx I see: +---------------------+--------------+------+------+------------ +-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------ +-------------+ | DHSM_CLK_BUFGP | GCLKBUF0| No | 544 | 0.338 | 0.472 | +---------------------+--------------+------+------+------------ +-------------+ | DHSM_RST_BUFGP | GCLKBUF3| No | 231 | 0.091 | 0.523 | +---------------------+--------------+------+------+------------ +-------------+ | PCI_CLK_BUFGP | GCLKBUF1| No | 204 | 0.353 | 0.487 | +---------------------+--------------+------+------+------------ +-------------+ | wf_data_in_flag | GCLKBUF2| No | 12 | 0.077 | 0.506 | +---------------------+--------------+------+------+------------ +-------------+ | d1/c1/mean8_stored | Local| | 2 | 0.000 | 0.908 | +---------------------+--------------+------+------+------------ +-------------+ | d1/c1/rng_stored | Local| | 2 | 0.000 | 0.728 | +---------------------+--------------+------+------+------------ +-------------+ | d1/c1/_not0004 | Local| | 5 | 0.000 | 2.659 | +---------------------+--------------+------+------+------------ +-------------+ | d1/c1/off_stored | Local| | 2 | 0.000 | 0.728 | +---------------------+--------------+------+------+------------ +-------------+ but off_stored, rng_stored, mean8_stored, and wf_data_in_flag are just wires in my design that are intended as flags. Where does _not0004 come from and why is it assuming that all of these things are clocks?? Thanks, IanArticle: 115012
cathy wrote:
> When I use DCM in virtex 5 and do the simulation, the modelsim 6.2e
> gives the following error message:
> Failure: (vsim-3808) Incompatible modes for port "clkfx_out".
> I don't know why it told me "incompatible modes for port "clkfx_out".
> They are all std_logic type and connected with the std_logic signals.
Port mode means direction, not type.
Maybe you have shorted two out ports together.
-- Mike Treseler
Article: 115013
Hi,
I am using a DCM block in my design. i generated it using XPS 7.1i
and exporting it later to ISE7.1i to do synthesis. this is what I put
in the system.mhs file
BEGIN dcm_module
PARAMETER INSTANCE = dcm_module_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLKIN_PERIOD = 7.51879699
PARAMETER C_CLKDV_DIVIDE = 2.0
PARAMETER C_CLKIN_BUF = TRUE
PARAMETER C_CLKDV_BUF = TRUE
PORT CLKIN = dcm_clk_in_s
PORT CLKDV = sys_clk_s
PORT CLKFB = dcm_module_0_CLKFB
PORT CLK0 = dcm_module_0_CLKFB
END
this is the constraint that I put in the ucf file during synthesis by
ISE
Net sys_clk_pin PERIOD = 7518 ps;
however although i specified it as clk freq as divide by 2, I get
errors like the one below:
#######################################################################
#####
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
-----------------------------------------------------------------------
---------
Constraint | Requested | Actual
| Logic
| |
| Levels
-----------------------------------------------------------------------
---------
* NET "bufgp_3/IBUFG" PERIOD = 7.518 ns HIG | 7.518ns | 9.825ns
| 23
H 50% | |
|
-----------------------------------------------------------------------
---------
#######################################################################
#####
which is strange since the period did not get multiplied by 2 as i
mentioned in the system.mhs file. can anyone help? The funny thing is
that when i generated the behavioral model and tried to verify it in
modelsim, the clock coming out of the clkdv port is divided by 2. the
XST somehow does not try to do that. why is not translated to the
correct constraints? this is not what is being said in the xilinx man
pages on how to constraint designs with DCM, that the ngdbuild will
auto translate the constraints into the correct clk period * 2 as in
for the case.
any advice? any one know if this is a bug.
Chris
Article: 115014
"Symon" <symon_brewer@hotmail.com> writes:
>Thanks for that link, it's interesting. Of course, the method described in
>this XAPP note only protects the design from cloning. It's not going to be
That's a start ;-)
>impossible to reverse engineer the configuration bit stream and find the
>secret key in the FPGA. In fact, doesn't this method of attack defeat the
Well, with some code modification you can put the secret into LUTs and/or
"random" logic. Then it's getting harder to find it. It should be also possible
to decrypt the picoblaze instructions "online", so it's not that easy to find the
BRAM that contains the code. After all, you (as the attacker) need to know where
the SHA-stuff is done to start the attack. Using XAPP780 without modifications is
not very clever...
>random number generator thing in all application? If an attacker has
>physical access to the design, I think the Vbatt RSA key thing is the only
>'secure' way to go, otherwise your configuration bitstream is there to see.
Spartans have no Vbatt :-(
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 115015A agree with the others over the size concerns... You're going to very quickly reach the limits of 36 macrocells.... Ben <canest> wrote in message news:45bbfa1a$1_2@mk-nntp-2.news.uk.tiscali.com... >I want to send off a pcb board design for a xiling xc9536 so that I > can experiment with some simple verilog programs. I > want the most minimal design, so I need one xiling > plcc socket, one 0.1uF bypass capacitor, one jtag > socket, and one led and resistor so that I can do some > basic apps that play with the led. Will this work, do I > need anything else? > >Article: 115016
Thank you, I had a stupid mistake of forgetting to put the in/out direction in the complonent declaration. Thank you.Article: 115017
Hallo, I tried to install Webpack 9.1 on three different Suse 10.2 machines: Centrino with 1.5 GiByte, Dual P2 with 640 MiByte and Athlon with 512 MiByte. Only on the Centrino machine, the install finalized. On both "low-memory" machines, install aborted without any further notice at about "86 %" of the install progress bar. "strace" showed 18644 mmap2(NULL, 8392704, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS,\ -1, 0) = -1 ENOMEM (Cannot allocate memory) 18643 <... nanosleep resumed> NULL) = 0 and soon after that 18644 --- SIGABRT (Aborted) @ 0 (0) --- Plenty of Swap was available, but not touched. "top" reported over 1 GiByte "VIRT" memory usage short before that abort. Any other similar observations? Is this perhaps somethind Suse/Linux specific? Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 115018
On a sunny day (Mon, 29 Jan 2007 18:25:17 +0000 (UTC)) it happened Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in <eple6d$9r8$1@lnx107.hrz.tu-darmstadt.de>: >Hallo, > >I tried to install Webpack 9.1 on three different Suse 10.2 machines: >Centrino with 1.5 GiByte, Dual P2 with 640 MiByte and Athlon with 512 MiByte. >Only on the Centrino machine, the install finalized. On both "low-memory" >machines, install aborted without any further notice at about "86 %" of the >install progress bar. > >"strace" showed >18644 mmap2(NULL, 8392704, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS,\ > -1, 0) = -1 ENOMEM (Cannot allocate memory) >18643 <... nanosleep resumed> NULL) = 0 >and soon after that >18644 --- SIGABRT (Aborted) @ 0 (0) --- > >Plenty of Swap was available, but not touched. "top" reported over 1 GiByte >"VIRT" memory usage short before that abort. > >Any other similar observations? Is this perhaps somethind Suse/Linux >specific? > >Thanks Installs fine on a 360 MB memory Linux Debian machine here. Are you sure swap was enabled? man swapon?Article: 115019
On a sunny day (Mon, 29 Jan 2007 18:49:56 GMT) it happened Jan Panteltje <pNaonStpealmtje@yahoo.com> wrote in <eplfkt$5mu$1@news.datemas.de>: >On a sunny day (Mon, 29 Jan 2007 18:25:17 +0000 (UTC)) it happened Uwe Bonnes ><bon@hertz.ikp.physik.tu-darmstadt.de> wrote in ><eple6d$9r8$1@lnx107.hrz.tu-darmstadt.de>: > >>Hallo, >> >>I tried to install Webpack 9.1 on three different Suse 10.2 machines: >>Centrino with 1.5 GiByte, Dual P2 with 640 MiByte and Athlon with 512 MiByte. >>Only on the Centrino machine, the install finalized. On both "low-memory" >>machines, install aborted without any further notice at about "86 %" of the >>install progress bar. >> >>"strace" showed >>18644 mmap2(NULL, 8392704, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS,\ >> -1, 0) = -1 ENOMEM (Cannot allocate memory) >>18643 <... nanosleep resumed> NULL) = 0 >>and soon after that >>18644 --- SIGABRT (Aborted) @ 0 (0) --- >> >>Plenty of Swap was available, but not touched. "top" reported over 1 GiByte >>"VIRT" memory usage short before that abort. >> >>Any other similar observations? Is this perhaps somethind Suse/Linux >>specific? >> >>Thanks > >Installs fine on a 360 MB memory Linux Debian machine here. >Are you sure swap was enabled? >man swapon? Oh and it says it only works on 32 bit processors, the Athlon is out?Article: 115020
Hi All, I was wondering if its possible to stream data at 480Mbps from a PC to a USB 2.0 port on a FPGA development board and send the data out of a SMA port on the board. The XUPV2P board has an onboard USB 2.0 and SMA ports. Can this board be used for this application? Thanks, BilluArticle: 115021
cathy wrote:
> Thank you, I had a stupid mistake of forgetting to put the in/out
> direction in the complonent declaration. Thank you.
You are welcome.
This is one reason that I use direct instances
instead of components.
-- Mike Treseler
Article: 115022Hi, I am using Xilinx ISE 8.2 (SP3) targeted at a spartan 3 device. We are attempting to use an FPGA for F/W and proof of concept work before taping out our ASIC, and are having difficulties with clocking. Our product requires very low power consumption, and we perform global clock gating to reduce power consumption through the clock tree. e.g. Master clock 16MHz, some logic is clocked at 8 or 4MHz, therefore only get a pulse every 2 or 4 clock cycles (we actually have about 12 clocks). In an ASIC flow, we can balance everything from the 16MHz clock and it will work. For FPGA, it considers each clock independent, and we have hold problems, and setup problems (I haven't yet specified the multi-cycle paths for the "slow" clocks. This is my first complex FPGA, and I have a number of questions - When ISE has completed, there are a number of unplaced components, even thought utilization is low. Is this because it has failed timing, so it doesn't even bother. - We may change to locally gated clocks (i.e. so that we only have one global clock). I still need to define the multi-cycle paths. Can anyone supply, or provide a link to, some example constraint files for this type of application. - Any other pointers or suggestions would be greatly appreciated. Thanks, StevenArticle: 115023
Hi, I would like to edit ROM contents in Virtex-4 .bit file (in order to avoid re-synthesis/P&R). Is there any information available how to do this? Already 'googled' the web and searched Xilinx' web page. So far no success. Any suggestion welcome! Thanks. Thanks, PhilArticle: 115024
Hello, I had something similar happening (am using spartan II as well), inexplicable, and it just stopped being a problem after upgrading (from 8.2) to 9.1. I'm a newbie so the hows and whys of what is going on I don't know. Maybe upgrade if you haven't already? Good luck! Jesse idp2 wrote: > Hi, > > I'm programming on a Spartan-II in ISE. I have a few questions about > the clk signals and .ucf files. > > I have assigned my two clock signals PCI_CLK and DHSM_CLK to GCLKBUF0 > and GCLKBUF1 respectively. However, when I compile it gives an error > that PCI_RST should be assigned to a GCLK. Is this happening because > a lot of logic is dependent on the RST? Also when I look at the clock > report in Xilinx I see: > > +---------------------+--------------+------+------+------------ > +-------------+ > | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max > Delay(ns)| > +---------------------+--------------+------+------+------------ > +-------------+ > | DHSM_CLK_BUFGP | GCLKBUF0| No | 544 | 0.338 | > 0.472 | > +---------------------+--------------+------+------+------------ > +-------------+ > | DHSM_RST_BUFGP | GCLKBUF3| No | 231 | 0.091 | > 0.523 | > +---------------------+--------------+------+------+------------ > +-------------+ > | PCI_CLK_BUFGP | GCLKBUF1| No | 204 | 0.353 | > 0.487 | > +---------------------+--------------+------+------+------------ > +-------------+ > | wf_data_in_flag | GCLKBUF2| No | 12 | 0.077 | > 0.506 | > +---------------------+--------------+------+------+------------ > +-------------+ > | d1/c1/mean8_stored | Local| | 2 | 0.000 | > 0.908 | > +---------------------+--------------+------+------+------------ > +-------------+ > | d1/c1/rng_stored | Local| | 2 | 0.000 | > 0.728 | > +---------------------+--------------+------+------+------------ > +-------------+ > | d1/c1/_not0004 | Local| | 5 | 0.000 | > 2.659 | > +---------------------+--------------+------+------+------------ > +-------------+ > | d1/c1/off_stored | Local| | 2 | 0.000 | > 0.728 | > +---------------------+--------------+------+------+------------ > +-------------+ > > but off_stored, rng_stored, mean8_stored, and wf_data_in_flag are just > wires in my design that are intended as flags. Where does _not0004 > come from and why is it assuming that all of these things are clocks?? > > > Thanks, > Ian >
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