Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Peter Alfke wrote: > I suggest an on-chip LFSR pseudo-random sequence generator, clocked by > a ring-oscillator (or equivalent) clock source and timed out by a fixed > delay, derived from the xtal oscillator. That's all very simple, takes > only a few CLBs, when the SRL16 is used for the LFSR. > Peter Alfke, Xilinx I have, more often, seen the ring-oscillator(s) sampled onto a common clock before XORing together and feeding into an LFSR. It's a little bit bigger due to the synchronizers, but has the nice effect that the bulk of the logic is all synchronous to the system clock. -hpaArticle: 114951
In article <45BBCF4D.5020706@zytor.com>,
"H. Peter Anvin" <hpa@zytor.com> writes:
|> Peter Alfke wrote:
|> > I suggest an on-chip LFSR pseudo-random sequence generator, clocked by
|> > a ring-oscillator (or equivalent) clock source and timed out by a fixed
|> > delay, derived from the xtal oscillator. That's all very simple, takes
|> > only a few CLBs, when the SRL16 is used for the LFSR.
|> > Peter Alfke, Xilinx
|>
|> I have, more often, seen the ring-oscillator(s) sampled onto a common
|> clock before XORing together and feeding into an LFSR. It's a little
|> bit bigger due to the synchronizers, but has the nice effect that the
|> bulk of the logic is all synchronous to the system clock.
XAPP 780 contains a random bit stream generator with ring-oscillators and some
"metastability" logic.
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 114952Well, the "bulk of the logic" is one CLB... Peter Alfke On Jan 27, 2:16 pm, "H. Peter Anvin" <h...@zytor.com> wrote: > Peter Alfke wrote: > > I suggest an on-chip LFSR pseudo-random sequence generator, clocked by > > a ring-oscillator (or equivalent) clock source and timed out by a fixed > > delay, derived from the xtal oscillator. That's all very simple, takes > > only a few CLBs, when the SRL16 is used for the LFSR. > > Peter Alfke, XilinxI have, more often, seen the ring-oscillator(s) sampled onto a common > clock before XORing together and feeding into an LFSR. It's a little > bit bigger due to the synchronizers, but has the nice effect that the > bulk of the logic is all synchronous to the system clock. > > -hpaArticle: 114953
Martin Thompson wrote: >> Sure that's VHDL mode? I can't see anything in the docs about >> simulation.. >> > > Yep, definitely... It's in the compilation section as none of it is > simulation specific, I just target the Modelsim compiler. OK. >> Hmm, it looks very interesting but I use Verilog :) >> > > Ahh, in that case, sorry, you're out of luck I think. Unless verilog-mode > is > as far on as vhdl-mode... Apparently not :) It is still very useful though. > See my makefile I posted elsewhere on this thread... Yeah I found a few links, thanks! -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 114954
Hi! I have developed a version of the median filtering algorithm described in XAPP953 and earilier, in more detail in a paper by Chaitali Chakrabarti (mentioned in XAPP953 bibliography). Everything is working almost fine. Why almost? I cannot find information about handling a situation, when 2 or more samples of the same value come into the processed window at once (that is the case in my simple 3x3 implementation, where 3 samples com in and out of the window on every clock cycle). Am I missing something? From what I understand, if the bits resulting from comparation of old samples with the new samples and the new samples among themselves are equal, the 0's and 1's that are then counted to evaluate the rank, the resulting rank would be also the same for all incoming samples, and such situation is not acceptable. I know this post may not be strictly connected to this group's area of interest, but please do not consider it as spam. I just wanted to make sure what do I do wrong, before I try to make any unnecessary modifications.Article: 114955
I want to send off a pcb board design for a xiling xc9536 so that I can experiment with some simple verilog programs. I want the most minimal design, so I need one xiling plcc socket, one 0.1uF bypass capacitor, one jtag socket, and one led and resistor so that I can do some basic apps that play with the led. Will this work, do I need anything else?Article: 114956
Hi, I updated the GTKWave for Win32 port I am maintaining. It's at 3.0.20 now. http://www.dspia.com/gtkwave.htmlArticle: 114957
Hi Symon, thanks for your reply. I'm sorry I still have questions on your reply. 1=2E Don't try and clock two FFs 800ps apart. I have used two seperated clocks from DCM with 90 degree phase=20 seperate, why this is not correct? 2=2E Change the path to something that's easier to meet. I can't understand this. Can you detail it? thanks very much. On 1=D4=C227=C8=D5, =C9=CF=CE=E79=CA=B130=B7=D6, "Symon" <symon_bre...@hotm= ail.com> wrote: > "skyworld" <chenyong20...@gmail.com> wrote in messagenews:1169860287.2875= 89.165750@p10g2000cwp.googlegroups.com... > > > Hi, > > I think you are right. Do you have any advice on how to solve this?Yes.= Don't try and clock two FFs 800ps apart. > > > should I add some constraints on this path? thanks.No. Change the path = to something that's easier to meet. > > HTH, Syms.Article: 114958
Are you still trying to sample data with 4 phase offset clocks? At the speed you are talking about, you are effectively making paths that need to run at a little over 1 GHz. Look at the jitter specs for the DCM clocks. That number is a pretty big portion of a ~800ps period. You may want to consider another method of doing what you need.Article: 114959
On 2007-01-28, <canest> <> wrote: > I want to send off a pcb board design for a xiling xc9536 so that I > can experiment with some simple verilog programs. I They will be *very* simple. If you want PC44, get at least a xc9572! > want the most minimal design, so I need one xiling > plcc socket, one 0.1uF bypass capacitor, Per power pin, plus whatever is required by your regulator. > one jtag > socket, and one led and resistor so that I can do some > basic apps that play with the led. Will this work, do I > need anything else? Some kind of clock. For what you want to do, make it as slow as possible. Connect it to a GCK pin. Keep in mind that a 1MHz clock input used to make your LED blink at 1Hz would take 20 of 36 macrocells for the clock divider! -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 114960
I suggest you use a low-frequency RC oscillator. Look at the second circuit in "six easy pieces" on the Xilinx website. That will save you lots of counter stages. Peter Alfke On Jan 27, 7:23 pm, Ben Jackson <b...@ben.com> wrote: > On 2007-01-28, <canest> <> wrote: > > > I want to send off a pcb board design for a xiling xc9536 so that I > > can experiment with some simple verilog programs. IThey will be *very* simple. If you want PC44, get at least a xc9572! > > > want the most minimal design, so I need one xiling > > plcc socket, one 0.1uF bypass capacitor,Per power pin, plus whatever is required by your regulator. > > > one jtag > > socket, and one led and resistor so that I can do some > > basic apps that play with the led. Will this work, do I > > need anything else?Some kind of clock. For what you want to do, make it as slow as possible. > Connect it to a GCK pin. Keep in mind that a 1MHz clock input used to > make your LED blink at 1Hz would take 20 of 36 macrocells for the clock > divider! > > -- > Ben Jackson AD7GD > <b...@ben.com>http://www.ben.com/Article: 114961
Peter Alfke wrote: > I suggest you use a low-frequency RC oscillator. > Look at the second circuit in "six easy pieces" on the Xilinx website. > That will save you lots of counter stages. > Peter Alfke Another idea is to add a footprint for a HC4060, or a HEF4060. That gives you a Xtal or RC OSC, buffer and divider chain in a low cost (35c 1+, 13c/2500), small SO16 package. Can work with crystals from 32KHz, to some MHz If you've chosen a 9536, then low power is probably not on your radar ?. -jgArticle: 114962
canest wrote: > I want to send off a pcb board design for a xiling xc9536 so that I > can experiment with some simple verilog programs. I > want the most minimal design, so I need one xiling > plcc socket, one 0.1uF bypass capacitor, one jtag > socket, and one led and resistor so that I can do some > basic apps that play with the led. Will this work, do I > need anything else? Regulator ? ONE led is rather too minimalist - why not a 7 segment display, and maybe a Piezo Sounder/speaker ? -jgArticle: 114963
"-jg" <Jim.Granville@gmail.com> wrote in message news:1169963473.520346.66000@m58g2000cwm.googlegroups.com... > canest wrote: >> I want to send off a pcb board design for a xiling xc9536 so that I >> can experiment with some simple verilog programs. I >> want the most minimal design, so I need one xiling >> plcc socket, one 0.1uF bypass capacitor, one jtag >> socket, and one led and resistor so that I can do some >> basic apps that play with the led. Will this work, do I >> need anything else? > > Regulator ? > > ONE led is rather too minimalist - why not a 7 segment display, > and maybe a Piezo Sounder/speaker ? > > -jg > I agree, you will outgrow/get bored with this board rather quickly. Why not buy a simple board? If you scan the web (ebay?) you can find some very low cost boards, see e.g http://www.knjn.com/ShopBoards_RS232.html. As a minimum I would add an expansion connector for all the unused pins, Hans www.ht-lab.comArticle: 114964
David R Brooks wrote: (snip) > I would be careful using an un-locked PLL as a source. I tried that > about 20 years ago, using discretes, & gave it up. It proved highly > non-random. > [Part of my Master's thesis: I was using a 74S124 VCO, with a > sampling-type phase detector running from a sinusoidal reference. VCO > frequency about 4MHz, reference 132kHz.] I remember hearing about the 74S124 about 30 years ago. If it is the one I remember, it is actually a dual VCO, except that it is supposed to be impossible to use both without them phase locking. It might be, then, they it could also phase lock to an external source. -- glenArticle: 114965
"Ben Jackson" <ben@ben.com> wrote in message news:slrnero5pp.17sg.ben@saturn.home.ben.com... > On 2007-01-28, <canest> <> wrote: > > I want to send off a pcb board design for a xiling xc9536 so that I > > can experiment with some simple verilog programs. I > > They will be *very* simple. If you want PC44, get at least a xc9572! I thought xc9536 *is* PC44? > > > want the most minimal design, so I need one xiling > > plcc socket, one 0.1uF bypass capacitor, > > Per power pin, plus whatever is required by your regulator. Do I need three bypass caps, or just one? Is 0.1uF ok or should I use 0.047uF? > > > one jtag > > socket, and one led and resistor so that I can do some > > basic apps that play with the led. Will this work, do I > > need anything else? > > Some kind of clock. For what you want to do, make it as slow as possible. > Connect it to a GCK pin. Keep in mind that a 1MHz clock input used to > make your LED blink at 1Hz would take 20 of 36 macrocells for the clock > divider! One microcell per register bit - 1 MHz = 20 bits = 2 ^ 20 > > -- > Ben Jackson AD7GD > <ben@ben.com> > http://www.ben.com/Article: 114966
Ben, In Louvain-la-Neuve, most courses are given in French as it is the French counterpart of the Leuven University (I might be wrong). But you are right about the beer and the link to IMEC - one of the leading research centres of Europe on advanced ASIC design. Regards, Luc On Sat, 27 Jan 2007 22:49:45 +0100, Ben Twijnstra <btwijnstra@gmail.com> wrote: >M Ihsan Baig wrote: > >> Hi all experts, >> Does any body tell me about the well known institues for fpga/asic >> study in Europe where I can start my MS leading to Ph.D >> Thanks Beg > >I'd try the University of Louvain-la-Neuve in Belgium. They have very good >contacts with IMEC, a major semiconductor research center. Plus, the beer >in the area is just wonderful. > >Best regards, > > >BenArticle: 114967
SRAM = synchronous random access memory, the memory must have its own clock So, it's much easier if you have another 3rd clock running the FIFO, this clock must be faster than the two inputs, then you need to generate the the FIFO's WE and RE pulses base on the rising edges of the two inputs Now consider the counter, it's also running by the SRAM clock, the counter will count up with WE and count down by RE Dunno if you can do this without the 3rd clock On Jan 26, 7:14 am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On 25 Jan 2007 23:14:35 -0800, "aravind" <aramos...@gmail.com> wrote: > > > > >There is a 20 bit counter,with two inputs ,on the rising edge of one > >input the counter must increment and on the rising edge of the other > >input the counter must decrement. > >this is for a 1MB FIFO buffer using single port external SRAM,I'm using > >Xilinx ISE tool.according to the xilinx tool you cannot have two > >(rising_edge()) statements in a single process. > > >How do you code it?You don't. But consider coding two separate counters and computing the > difference between them. > > Since you have two separate clock domains, it can get complicated. > > If you only need the output (difference) in one of the clock domains, > consider re-latching the second domain's counter output on the first > clock, to keep the output computation synchronous. > > - BrianArticle: 114968
On Jan 28, 6:55 pm, "Marlboro" <cco...@netscape.net> wrote: > SRAM = synchronous random access memory, the memory must have its own > clock > > So, it's much easier if you have another 3rd clock running the FIFO, > this clock must be faster than the two inputs, then you need to > generate the the FIFO's WE and RE pulses base on the rising edges of > the two inputs > > Now consider the counter, it's also running by the SRAM clock, the > counter will count up with WE and count down by RE > > Dunno if you can do this without the 3rd clock > > On Jan 26, 7:14 am, Brian Drummond <brian_drumm...@btconnect.com> > wrote: > > > On 25 Jan 2007 23:14:35 -0800, "aravind" <aramos...@gmail.com> wrote: > > > >There is a 20 bit counter,with two inputs ,on the rising edge of one > > >input the counter must increment and on the rising edge of the other > > >input the counter must decrement. > > >this is for a 1MB FIFO buffer using single port external SRAM,I'm using > > >Xilinx ISE tool.according to the xilinx tool you cannot have two > > >(rising_edge()) statements in a single process. > > > >How do you code it?You don't. But consider coding two separate counters and computing the > > difference between them. > > > Since you have two separate clock domains, it can get complicated. > > > If you only need the output (difference) in one of the clock domains, > > consider re-latching the second domain's counter output on the first > > clock, to keep the output computation synchronous. > > > - Brian The RAM used here is Static RAM(ISSI IS61LV25616AL Static RAM) not Synchronous RAM, sorry if i misled you.The 20 bit counter is to generate buffer full and empty signals and also to monitor the size of the buffer used at any instant.The rd and wr addresses are generated separately.I'm planning to use LFSR's to generate the RD and WR addresses.Article: 114969
Ahh, I missed it not you, I haven't touch that static ram for long time :) But my theory is the about same. Even though the FIFO has no clock, the data/address and read/write enables would be synchronized when they going in and out your fpgaArticle: 114970
<canest> wrote: > >"Ben Jackson" <ben@ben.com> wrote in message >news:slrnero5pp.17sg.ben@saturn.home.ben.com... >> On 2007-01-28, <canest> <> wrote: >> > I want to send off a pcb board design for a xiling xc9536 so that I >> > can experiment with some simple verilog programs. I >> >> They will be *very* simple. If you want PC44, get at least a xc9572! > >I thought xc9536 *is* PC44? > >> >> > want the most minimal design, so I need one xiling >> > plcc socket, one 0.1uF bypass capacitor, >> >> Per power pin, plus whatever is required by your regulator. > >Do I need three bypass caps, or just one? Is 0.1uF ok or >should I use 0.047uF? > >> >> > one jtag >> > socket, and one led and resistor so that I can do some >> > basic apps that play with the led. Will this work, do I >> > need anything else? >> >> Some kind of clock. For what you want to do, make it as slow as possible. >> Connect it to a GCK pin. Keep in mind that a 1MHz clock input used to >> make your LED blink at 1Hz would take 20 of 36 macrocells for the clock >> divider! > >One microcell per register bit - 1 MHz = 20 bits = 2 ^ 20 I don't know if this device has luts/flipflops like the Virtex/Spartan which can hold a 16 bit shift register in one cell. If yes, a divide by up to 16 element can be put into one cell. Dividing 1MHz downto 1 Hz takes 5 cascaded shift registers. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 114971
The SRL16 (or SRL32 in Virtex-5) only exists in the newer Xilinx FPGAs, nowhere else. So, dividing by >100 Billion takes only 8 LUTs = one CLB in Virtex-5. (SRL32 used as serial incrementer with a one-bit adder and carry, plus a 5-bit counter and one control flip-flop) But in CPLDs it is one Macrocell per flip-flop. Peter Alfke On Jan 28, 8:48 am, n...@puntnl.niks (Nico Coesel) wrote: > <canest> wrote: > > >"Ben Jackson" <b...@ben.com> wrote in message > >news:slrnero5pp.17sg.ben@saturn.home.ben.com... > >> On 2007-01-28, <canest> <> wrote: > >> > I want to send off a pcb board design for a xiling xc9536 so that I > >> > can experiment with some simple verilog programs. I > > >> They will be *very* simple. If you want PC44, get at least a xc9572! > > >I thought xc9536 *is* PC44? > > >> > want the most minimal design, so I need one xiling > >> > plcc socket, one 0.1uF bypass capacitor, > > >> Per power pin, plus whatever is required by your regulator. > > >Do I need three bypass caps, or just one? Is 0.1uF ok or > >should I use 0.047uF? > > >> > one jtag > >> > socket, and one led and resistor so that I can do some > >> > basic apps that play with the led. Will this work, do I > >> > need anything else? > > >> Some kind of clock. For what you want to do, make it as slow as possible. > >> Connect it to a GCK pin. Keep in mind that a 1MHz clock input used to > >> make your LED blink at 1Hz would take 20 of 36 macrocells for the clock > >> divider! > > >One microcell per register bit - 1 MHz = 20 bits = 2 ^ 20I don't know if this device has luts/flipflops like the Virtex/Spartan > which can hold a 16 bit shift register in one cell. If yes, a divide > by up to 16 element can be put into one cell. Dividing 1MHz downto 1 > Hz takes 5 cascaded shift registers. > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U opwww.adresboekje.nlArticle: 114972
> You may be missing an important feature of SDRAM. You don't need to > use full-page reads or writes to keep data streaming at 100% of the > available bandwidth (if you don't change direction) or very nearly 100% > (if you switch from read to write infrequently). This is due to the > ability > to set up another block operation on one bank while another bank is > transferring data. Hi Gabor, I've missed this too, what happens at the end of the burst? Do you have another "cas" otherwise the burst will stop (unless it's full page) Anyway, if it works like that then we can save bunch of cycles ras to cas and data transfer can be seamless I don't know it's possible to activate another bank while one bank is read/written, please clarify me on this, must be my big miss :) Thanks,Article: 114973
On Sat, 27 Jan 2007 17:19:20 -0800, canestY(m wrote: > I want to send off a pcb board design for a xiling xc9536 so that I can > experiment with some simple verilog programs. I want the most minimal > design, so I need one xiling plcc socket, one 0.1uF bypass capacitor, > one jtag socket, and one led and resistor so that I can do some basic > apps that play with the led. Will this work, do I need anything else? I can send you a PCB for cost of postage that has: location for 44 pin PLCC 9536/9572/9536XL/9572XL (I would recommend 9572XL for price/macrocells) Location for xtal oscillator (1/2 size = DIP 8) RC oscillator with 4 selectable rates 4 leds 1 Pushbutton All I/O brought out to 2x 26 pin headers 6 pin JTAG connector 4 pin power connector (9536XL and 9572XL run fine from 2 AA batteries) Only disadvantage for hobby assembly is that its mostly surface mount Peter WallaceArticle: 114974
Hi, How to make an internal signal embedded deep in hierarchy to a gloal output signal? I have an internal signal embedded deep in hierarchy showing there is an error. I would like to see it at the top of hierarchy. How can I do it in VHDL? Do I have to do the foolish steps to transfer it one module to another until the top level? Weng
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z